Cypress NoBL CY7C1352G User Manual

CY7C1352G  
4-Mbit (256K x 18) Pipelined SRAM with  
NoBL™ Architecture  
Features  
Functional Description[1]  
• Pin compatible and functionally equivalent to ZBT™  
devices  
The CY7C1352G is a 3.3V, 256K x 18 synchronous-pipelined  
Burst SRAM designed specifically to support unlimited true  
back-to-back Read/Write operations without the insertion of  
wait states. The CY7C1352G is equipped with the advanced  
No Bus Latency™ (NoBL™) logic required to enable consec-  
utive Read/Write operations with data being transferred on  
every clock cycle. This feature dramatically improves the  
throughput of the SRAM, especially in systems that require  
frequent Write/Read transitions.  
• Internally self-timed output buffer control to eliminate  
the need to use OE  
• Byte Write capability  
• 256K x 18 common I/O architecture  
• 3.3V core power supply (V  
)
DD  
• 2.5V/3.3V I/O power supply (V  
• Fast clock-to-output times  
)
DDQ  
All synchronous inputs pass through input registers controlled  
by the rising edge of the clock. All data outputs pass through  
output registers controlled by the rising edge of the clock. The  
clock input is qualified by the Clock Enable (CEN) signal,  
which, when deasserted, suspends operation and extends the  
previous clock cycle. Maximum access delay from the clock  
rise is 2.6 ns (250-MHz device).  
— 2.6 ns (for 250-MHz device)  
• Clock Enable (CEN) pin to suspend operation  
• Synchronous self-timed writes  
• Asynchronous output enable (OE)  
Write operations are controlled by the two Byte Write Select  
• Available in lead-free 100-Pin TQFP package  
• Burst Capability—linear or interleaved burst order  
• ZZ” Sleep Mode Option and Stop Clock option  
(BW  
) and a Write Enable (WE) input. All writes are  
[A:B]  
conducted with on-chip synchronous self-timed write circuitry.  
Three synchronous Chip Enables (CE , CE , CE ) and an  
1
2
3
asynchronous Output Enable (OE) provide for easy bank  
selection and output tri-state control. In order to avoid bus  
contention, the output drivers are synchronously tri-stated  
during the data portion of a write sequence.  
Logic Block Diagram  
ADDRESS  
REGISTER 0  
A0, A1, A  
A1  
A0  
A1'  
A0'  
D1  
D0  
Q1  
Q0  
BURST  
LOGIC  
MODE  
C
ADV/LD  
C
CLK  
CEN  
WRITE ADDRESS  
REGISTER 1  
WRITE ADDRESS  
REGISTER 2  
O
U
T
P
O
U
T
P
S
E
N
S
D
A
T
U
T
U
T
ADV/LD  
WRITE REGISTRY  
AND DATA COHERENCY  
CONTROL LOGIC  
A
R
E
G
I
S
T
E
R
S
MEMORY  
ARRAY  
E
B
U
F
DQs  
DQPA  
DQPB  
WRITE  
DRIVERS  
BWA  
BWB  
S
T
E
E
R
I
A
M
P
F
E
R
S
S
N
G
WE  
E
E
INPUT  
REGISTER 1  
INPUT  
REGISTER 0  
E
E
OE  
CE1  
CE2  
CE3  
READ LOGIC  
Sleep  
Control  
ZZ  
Note:  
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05514 Rev. *D  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised July 4, 2006  
CY7C1352G  
Pin Definitions  
Name  
I/O  
Description  
Address Inputs used to select one of the 256K address locations. Sampled at the rising  
are fed to the two-bit burst counter.  
A0, A1, A  
Input-  
Synchronous edge of the CLK. A  
[1:0]  
BW  
WE  
Input-  
Byte Write Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled  
[A:B]  
Synchronous on the rising edge of CLK.  
Input-  
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW.  
Synchronous This signal must be asserted LOW to initiate a write sequence.  
ADV/LD  
Input-  
Advance/Load Input. Used to advance the on-chip address counter or load a new address.  
Synchronous When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW,  
a new address can be loaded into the device for an access. After being deselected, ADV/LD  
should be driven LOW in order to load a new address.  
CLK  
Input-Clock  
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.  
CLK is only recognized if CEN is active LOW.  
CE  
CE  
CE  
Input-  
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction  
1
2
3
Synchronous with CE and CE to select/deselect the device.  
2
3
Input-  
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction  
Synchronous with CE and CE to select/deselect the device.  
1
3
Input-  
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction  
Synchronous with CE and CE to select/deselect the device.  
1
2
OE  
Input-  
Output Enable, asynchronous input, active LOW. Combined with the synchronous logic  
Asynchronous block inside the device to control the direction of the I/O pins. When LOW, the DQ pins are  
allowed to behave as outputs. When deasserted HIGH, DQ pins are tri-stated, and act as input  
data pins. OE is masked during the data portion of a write sequence, during the first clock when  
emerging from a deselected state, when the device has been deselected.  
CEN  
ZZ  
Input-  
Clock Enable Input, active LOW. When asserted LOW the Clock signal is recognized by the  
Synchronous SRAM. When deasserted HIGH the Clock signal is masked. Since deasserting CEN does not  
deselect the device, CEN can be used to extend the previous cycle when required.  
Input-  
ZZ “sleep” Input. This active HIGH input places the device in a non-time-critical “sleep”  
Asynchronous condition with data integrity preserved. During normal operation, this pin has to be low or left  
floating. ZZ pin has an internal pull-down.  
DQs  
I/O-  
Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered  
Synchronous by the rising edge of CLK. As outputs, they deliver the data contained in the memory location  
specified by the address during the clock rise of the read cycle. The direction of the pins is  
controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave  
as outputs. When HIGH, DQ and DQP  
are placed in a tri-state condition. The outputs are  
s
[A:B]  
automatically tri-stated during the data portion of a write sequence, during the first clock when  
emerging from a deselected state, and when the device is deselected, regardless of the state  
of OE.  
DQP  
I/O-  
Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQ . During  
[A:B]  
s
Synchronous write sequences, DQP  
is controlled by BW  
correspondingly.  
[A:B]  
[A:B]  
MODE  
Input Strap Pin Mode Input. Selects the burst order of the device.  
When tied to Gnd selects linear burst sequence. When tied to V or left floating selects  
DD  
interleaved burst sequence.  
V
V
V
Power Supply Power supply inputs to the core of the device.  
I/O Power Supply Power supply for the I/O circuitry.  
DD  
DDQ  
SS  
Ground  
Ground for the device.  
NC  
No Connects. Not internally connected to the die.  
NC/36M,  
NC/72M,  
NC/144M,  
NC/288M  
No Connects. Not internally connected to the die. NC/36M, NC/72M, NC/144M, NC/288M are  
address expansion pins are not internally connected to the die.  
Document #: 38-05514 Rev. *D  
Page 3 of 12  
CY7C1352G  
the state of chip enables inputs or WE. WE is latched at the  
beginning of a burst cycle. Therefore, the type of access (Read  
or Write) is maintained throughout the burst sequence.  
Functional Overview  
The CY7C1352G is a synchronous-pipelined Burst SRAM  
designed specifically to eliminate wait states during  
Write/Read transitions. All synchronous inputs pass through  
input registers controlled by the rising edge of the clock. The  
clock signal is qualified with the Clock Enable input signal  
(CEN). If CEN is HIGH, the clock signal is not recognized and  
all internal states are maintained. All synchronous operations  
are qualified with CEN. All data outputs pass through output  
registers controlled by the rising edge of the clock. Maximum  
Single Write Accesses  
Write accesses are initiated when the following conditions are  
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE , CE ,  
1
2
and CE are ALL asserted active, and (3) the write signal WE  
3
is asserted LOW. The address presented to the address inputs  
is loaded into the Address Register. The write signals are  
latched into the Control Logic block.  
access delay from the clock rise (t ) is 2.6 ns (250-MHz  
CO  
device).  
On the subsequent clock rise the data lines are automatically  
tri-stated regardless of the state of the OE input signal. This  
allows the external logic to present the data on DQs and  
Accesses can be initiated by asserting all three Chip Enables  
(CE , CE , CE ) active at the rising edge of the clock. If Clock  
1
2
3
DQP  
. In addition, the address for the subsequent access  
[A:B]  
Enable (CEN) is active LOW and ADV/LD is asserted LOW,  
the address presented to the device will be latched. The  
access can either be a read or write operation, depending on  
(Read/Write/Deselect) is latched into the Address Register  
(provided the appropriate control signals are asserted).  
the status of the Write Enable (WE). BW  
conduct byte write operations.  
can be used to  
On the next clock rise the data presented to DQs and  
DQP[A:B] (or a subset for byte write operations, see Write  
Cycle Description table for details) inputs is latched into the  
device and the write is complete.  
[A:B]  
Write operations are qualified by the Write Enable (WE). All  
writes are simplified with on-chip synchronous self-timed write  
circuitry.  
The data written during the Write operation is controlled by  
BW  
signals. The CY7C1352G provides byte write  
[A:B]  
Three synchronous Chip Enables (CE , CE , CE ) and an  
1
2
3
capability that is described in the Write Cycle Description table.  
Asserting the Write Enable input (WE) with the selected Byte  
Write Select (BW  
desired bytes. Bytes not selected during a byte write operation  
asynchronous Output Enable (OE) simplify depth expansion.  
All operations (Reads, Writes, and Deselects) are pipelined.  
ADV/LD should be driven LOW once the device has been  
deselected in order to load a new address for the next  
operation.  
) input will selectively write to only the  
[A:B]  
will remain unaltered. synchronous self-timed write  
A
mechanism has been provided to simplify the write operations.  
Byte write capability has been included in order to greatly  
simplify Read/Modify/Write sequences, which can be reduced  
to simple byte write operations.  
Single Read Accesses  
A read access is initiated when the following conditions are  
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE , CE ,  
1
2
Because the CY7C1352G is a common I/O device, data  
should not be driven into the device while the outputs are  
active. The Output Enable (OE) can be deasserted HIGH  
before presenting data to the DQs and DQP  
so will tri-state the output drivers. As a safety precaution, DQs  
and DQP are automatically tri-stated during the data  
and CE are ALL asserted active, (3) the Write Enable input  
3
signal WE is deasserted HIGH, and (4) ADV/LD is asserted  
LOW. The address presented to the address inputs is latched  
into the Address Register and presented to the memory core  
and control logic. The control logic determines that a read  
access is in progress and allows the requested data to  
propagate to the input of the output register. At the rising edge  
of the next clock the requested data is allowed to propagate  
through the output register and onto the data bus, provided OE  
is active LOW. After the first clock of the read access the output  
buffers are controlled by OE and the internal control logic. OE  
must be driven LOW in order for the device to drive out the  
requested data. During the second clock, a subsequent  
operation (Read/Write/Deselect) can be initiated. Deselecting  
the device is also pipelined. Therefore, when the SRAM is  
deselected at clock rise by one of the chip enable signals, its  
output will tri-state following the next clock rise.  
inputs. Doing  
[A:B]  
[A:B]  
portion of a write cycle, regardless of the state of OE.  
Burst Write Accesses  
The CY7C1352G has an on-chip burst counter that allows the  
user the ability to supply a single address and conduct up to  
four Write operations without reasserting the address inputs.  
ADV/LD must be driven LOW in order to load the initial  
address, as described in the Single Write Access section  
above. When ADV/LD is driven HIGH on the subsequent clock  
rise, the chip enables (CE , CE , and CE ) and WE inputs are  
1
2
3
ignored and the burst counter is incremented. The correct  
BW inputs must be driven in each cycle of the burst write  
[A:B]  
Burst Read Accesses  
in order to write the correct bytes of data.  
The CY7C1352G has an on-chip burst counter that allows the  
user the ability to supply a single address and conduct up to  
four Reads without reasserting the address inputs. ADV/LD  
must be driven LOW in order to load a new address into the  
SRAM, as described in the Single Read Access section above.  
The sequence of the burst counter is determined by the MODE  
input signal. A LOW input on MODE selects a linear burst  
mode, a HIGH selects an interleaved burst sequence. Both  
burst counters use A0 and A1 in the burst sequence, and will  
wrap-around when incremented sufficiently. A HIGH input on  
ADV/LD will increment the internal burst counter regardless of  
Sleep Mode  
The ZZ input pin is an asynchronous input. Asserting ZZ  
places the SRAM in a power conservation “sleep” mode. Two  
clock cycles are required to enter into or exit from this “sleep”  
mode. While in this mode, data integrity is guaranteed.  
Accesses pending when entering the “sleep” mode are not  
considered valid nor is the completion of the operation  
guaranteed. The device must be deselected prior to entering  
the “sleep” mode. CE1, CE2, and CE3, must remain inactive for  
the duration of tZZREC after the ZZ input returns LOW.  
Document #: 38-05514 Rev. *D  
Page 4 of 12  
CY7C1352G  
Interleaved Burst Address Table  
(MODE = Floating or VDD  
Linear Burst Address Table (MODE = GND)  
)
First  
Address  
A1, A0  
Second  
Address  
A1, A0  
Third  
Address  
A1, A0  
Fourth  
Address  
A1, A0  
First  
Address  
A1, A0  
Second  
Address  
A1, A0  
Third  
Address  
A1, A0  
Fourth  
Address  
A1, A0  
00  
01  
10  
11  
01  
10  
11  
00  
10  
11  
00  
01  
11  
00  
01  
10  
00  
01  
10  
11  
01  
00  
11  
10  
10  
11  
00  
01  
11  
10  
01  
00  
ZZ Mode Electrical Characteristics  
Parameter  
Description  
Snooze mode standby current  
Device operation to ZZ  
Test Conditions  
Min.  
Max.  
40  
Unit  
mA  
ns  
I
t
t
t
t
ZZ > V 0.2V  
DD  
DDZZ  
ZZ > V 0.2V  
2t  
ZZS  
DD  
CYC  
ZZ recovery time  
ZZ < 0.2V  
2t  
ns  
ZZREC  
ZZI  
CYC  
ZZ active to snooze current  
ZZ inactive to exit snooze current  
This parameter is sampled  
This parameter is sampled  
2t  
ns  
CYC  
0
ns  
RZZI  
Truth Table [2, 3, 4, 5, 6, 7, 8]  
Address  
Used  
Operation  
CE ZZ ADV/LD WE BW  
OE CEN CLK  
DQ  
x
Deselect Cycle  
None  
H
X
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H
L
X
X
H
X
H
X
L
X
X
X
X
X
X
L
X
X
L
L
L
L
L
L
L
L
L
L
L
H
X
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
X
Tri-State  
Tri-State  
Data Out (Q)  
Data Out (Q)  
Tri-State  
Tri-State  
Data In (D)  
Data In (D)  
Tri-State  
Tri-State  
Continue Deselect Cycle  
Read Cycle (Begin Burst)  
Read Cycle (Continue Burst)  
NOP/Dummy Read (Begin Burst)  
Dummy Read (Continue Burst)  
Write Cycle (Begin Burst)  
Write Cycle (Continue Burst)  
NOP/WRITE ABORT (Begin Burst)  
WRITE ABORT (Continue Burst)  
IGNORE CLOCK EDGE (Stall)  
SNOOZE MODE  
None  
External  
Next  
X
L
H
L
L
External  
Next  
H
H
X
X
X
X
X
X
X
L
H
L
External  
Next  
X
L
H
L
X
L
L
None  
H
H
X
X
Next  
X
X
X
H
X
X
X
X
X
Current  
None  
Tri-State  
Truth Table for Read/Write [2, 3]  
Function  
WE  
BW  
BW  
A
B
Read  
H
X
H
H
L
X
H
L
Write No bytes written  
Write Byte A (DQ and DQP )  
L
L
L
L
A
A
Write Byte B (DQ and DQP )  
H
L
B
B
Write All Bytes  
L
Notes:  
2. X=”Don't Care.” H = Logic HIGH, L = Logic LOW. CE stands for ALL Chip Enables active. BW = L signifies at least one Byte Write Select is active, BW = Valid  
X
X
signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.  
3. Write is defined by BW , and WE. See Write Cycle Descriptions table.  
[A:B]  
4. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.  
5. The DQ and DQP pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.  
6. CEN = H, inserts wait states.  
7. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.  
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP  
= tri-state when  
[A:B]  
OE is inactive or when the device is deselected, and DQs and DQP  
= data when OE is active.  
[A:B]  
Document #: 38-05514 Rev. *D  
Page 5 of 12  
CY7C1352G  
DC Input Voltage ...................................... −0.5V to V + 0.5V  
Maximum Ratings  
DD  
Current into Outputs (LOW)......................................... 20 mA  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
Static Discharge Voltage.......................................... > 2001V  
(per MIL-STD-883, Method 3015)  
Storage Temperature ..................................... −65°C to +150°C  
Latch-up Current.................................................... > 200 mA  
Ambient Temperature with  
Power Applied.................................................. −55°C to +125°C  
Operating Range  
Supply Voltage on V Relative to GND.........−0.5V to +4.6V  
DD  
Ambient  
Supply Voltage on V  
Relative to GND .......−0.5V to +V  
Range  
Commercial  
Industrial  
Temperature (T )  
V
V
DDQ  
DDQ  
DD  
A
DD  
DC Voltage Applied to Outputs  
in tri-state..................................................−0.5V to V  
0°C to +70°C  
3.3V –5%  
+10%  
2.5V –5%  
+ 0.5V  
to V  
DDQ  
DD  
–40°C to +85°C  
[9, 10]  
Electrical Characteristics Over the Operating Range  
Parameter  
Description  
Power Supply Voltage  
I/O Supply Voltage  
Output HIGH Voltage  
Test Conditions  
Min.  
Max.  
Unit  
V
V
3.135  
2.375  
2.4  
3.6  
DD  
V
V
V
V
DDQ  
OH  
DD  
for 3.3V I/O, I = –4.0 mA  
V
OH  
for 2.5V I/O, I = –1.0 mA  
2.0  
V
OH  
V
V
V
I
Output LOW Voltage  
for 3.3V I/O, I = 8.0 mA  
0.4  
0.4  
V
OL  
IH  
IL  
OL  
for 2.5V I/O, I = 1.0 mA  
V
OL  
[9]  
Input HIGH Voltage  
for 3.3V I/O  
for 2.5V I/O  
for 3.3V I/O  
for 2.5V I/O  
2.0  
1.7  
V
V
+ 0.3V  
+ 0.3V  
0.8  
V
V
DD  
DD  
[9]  
Input LOW Voltage  
–0.3  
–0.3  
5  
V
0.7  
V
Input Leakage Current GND V V  
except ZZ and MODE  
5
µA  
X
I
DDQ  
Input Current of MODE Input = V  
30  
5  
µA  
µA  
SS  
Input = V  
5
DD  
Input Current of ZZ  
Input = V  
Input = V  
µA  
SS  
DD  
30  
5
µA  
I
I
Output Leakage Current GND V V  
Output Disabled  
5  
µA  
OZ  
I
DDQ,  
V
Operating Supply  
V
f = f  
= Max., I  
= 0 mA,  
4-ns cycle, 250 MHz  
5-ns cycle, 200 MHz  
6-ns cycle, 166 MHz  
7.5-ns cycle,133 MHz  
325  
265  
240  
225  
120  
110  
100  
90  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
DD  
DD  
DD  
OUT  
= 1/t  
MAX CYC  
Current  
I
Automatic CE  
Power-Down  
Current—TTL Inputs  
V = Max, Device Deselected, 4-ns cycle, 250 MHz  
DD  
SB1  
V
V or V V  
IN  
IH  
IN  
IL  
5-ns cycle, 200 MHz  
6-ns cycle, 166 MHz  
7.5-ns cycle,133 MHz  
f = f  
= 1/t  
MAX CYC  
I
I
Automatic CE  
Power-down  
Current—CMOS Inputs  
V
V
V
= Max, Device Deselected, All speeds  
40  
SB2  
DD  
0.3V or  
IN  
IN  
> V  
– 0.3V, f = 0  
DDQ  
Automatic CE  
Power-down  
Current—CMOS Inputs  
V
= Max, Device Deselected, 4-ns cycle, 250 MHz  
105  
95  
mA  
mA  
mA  
mA  
SB3  
DD  
or V 0.3V or  
IN  
> V  
5-ns cycle, 200 MHz  
6-ns cycle, 166 MHz  
7.5-ns cycle,133 MHz  
V
– 0.3V  
IN  
DDQ  
85  
f = f  
= 1/t  
CYC  
MAX  
75  
Notes:  
9. Overshoot: V (AC) < V +1.5V (Pulse width less than t  
/2), undershoot: V (AC)> –2V (Pulse width less than t  
/2).  
IH  
DD  
CYC  
IL  
CYC  
< V  
DDQ DD.  
10. T  
: Assumes a linear ramp from 0V to V (min.) within 200 ms. During this time V < V and V  
Power-up  
DD  
IH  
DD  
Document #: 38-05514 Rev. *D  
Page 6 of 12  
CY7C1352G  
[9, 10]  
Electrical Characteristics Over the Operating Range  
(continued)  
Parameter  
Description  
Automatic CE  
Test Conditions  
Min.  
Max.  
Unit  
I
V
= Max, Device Deselected, All speeds  
DD  
45  
mA  
SB4  
Power-down  
Current—TTL Inputs  
V
V or V V , f = 0  
IN  
IH IN IL  
Capacitance[11]  
100 TQFP  
Max.  
Parameter  
Description  
Input Capacitance  
Test Conditions  
T = 25°C, f = 1 MHz,  
Unit  
pF  
C
C
C
5
5
5
IN  
A
V
= 3.3V,  
= 3.3V  
DD  
Clock Input Capacitance  
Input/Output Capacitance  
pF  
CLK  
I/O  
V
DDQ  
pF  
Thermal Resistance[11]  
100 TQFP  
Package  
Parameter  
Description  
Test Conditions  
Unit  
Θ
Thermal Resistance  
(Junction to Ambient)  
Test conditions follow standard test  
methods and procedures for measuring  
thermal impedance, per EIA/JESD51.  
30.32  
°C/W  
JA  
Θ
Thermal Resistance  
(Junction to Case)  
6.85  
°C/W  
JC  
AC Test Loads and Waveforms  
3.3V I/O Test Load  
1ns  
R = 317Ω  
3.3V  
OUTPUT  
OUTPUT  
ALL INPUT PULSES  
90%  
VDDQ  
90%  
10%  
Z = 50Ω  
0
R = 50Ω  
10%  
L
GND  
5 pF  
R = 351Ω  
1 ns  
1 ns  
V = 1.5V  
T
INCLUDING  
JIG AND  
SCOPE  
(c)  
(a)  
(b)  
2.5V I/O Test Load  
R = 1667Ω  
2.5V  
OUTPUT  
R = 50Ω  
OUTPUT  
ALL INPUT PULSES  
90%  
VDDQ  
GND  
90%  
10%  
Z = 50Ω  
0
10%  
L
5 pF  
R = 1538Ω  
INCLUDING  
JIG AND  
SCOPE  
1 ns  
1 ns  
V = 1.25V  
T
(a)  
(b)  
(c)  
Note:  
11. Tested initially and after any design or process changes that may affect these parameters.  
Document #: 38-05514 Rev. *D  
Page 7 of 12  
CY7C1352G  
[16, 17]  
Switching Characteristics Over the Operating Range  
–250  
–200  
–166  
–133  
Parameter  
Description  
Min. Max. Min. Max. Min.  
Max. Min. Max. Unit  
[12]  
t
V
(typical) to the first Access  
1
1
1
1
ms  
POWER  
DD  
Clock  
t
t
t
Clock Cycle Time  
Clock HIGH  
4.0  
1.7  
1.7  
5.0  
2.0  
2.0  
6.0  
2.5  
2.5  
7.5  
3.0  
3.0  
ns  
ns  
ns  
CYC  
CH  
Clock LOW  
CL  
Output Times  
t
t
t
t
t
t
t
Data Output Valid After CLK Rise  
Data Output Hold After CLK Rise  
2.6  
2.8  
3.5  
4.0  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CO  
1.0  
0
1.0  
0
1.5  
0
1.5  
0
DOH  
CLZ  
[13, 14, 15]  
Clock to Low-Z  
[13, 14, 15]  
Clock to High-Z  
2.6  
2.6  
2.8  
2.8  
3.5  
3.5  
4.0  
4.0  
CHZ  
OEV  
OELZ  
OEHZ  
OE LOW to Output Valid  
[13, 14, 15]  
OE LOW to Output Low-Z  
0
0
0
0
[13, 14, 15]  
OE HIGH to Output High-Z  
2.6  
2.8  
3.5  
4.0  
Set-up Times  
t
t
t
t
t
t
Address Set-up Before CLK Rise  
ADV/LD Set-up Before CLK Rise  
1.2  
1.2  
1.2  
1.2  
1.2  
1.2  
1.2  
1.2  
1.2  
1.2  
1.2  
1.2  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
ns  
ns  
ns  
ns  
ns  
ns  
AS  
ALS  
WES  
CENS  
DS  
GW, BW  
Set-Up Before CLK Rise  
[A:B]  
CEN Set-up Before CLK Rise  
Data Input Set-up Before CLK Rise  
Chip Enable Set-up Before CLK Rise  
CES  
Hold Times  
t
t
t
t
t
t
Address Hold After CLK Rise  
ADV/LD Hold after CLK Rise  
0.3  
0.3  
0.3  
0.3  
0.3  
0.3  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
ns  
ns  
ns  
ns  
ns  
ns  
AH  
ALH  
WEH  
CENH  
DH  
GW, BW  
Hold After CLK Rise  
[A:B]  
CEN Hold After CLK Rise  
Data Input Hold After CLK Rise  
Chip Enable Hold After CLK Rise  
CEH  
Notes:  
12. This part has a voltage regulator internally; tpower is the time that the power needs to be supplied above V minimum initially before a read or write operation  
DD  
can be initiated.  
13. t  
, t  
,t  
, and t  
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.  
CHZ CLZ OELZ  
OEHZ  
14. At any given voltage and temperature, t  
is less than t  
and t  
is less than t  
to eliminate bus contention between SRAMs when sharing the same  
OEHZ  
OELZ  
CHZ  
CLZ  
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed  
to achieve tri-state prior to Low-Z under the same system conditions.  
15. This parameter is sampled and not 100% tested.  
16. Timing reference level is 1.5V when V  
= 3.3V and is 1.25V when V  
= 2.5V.  
DDQ  
DDQ  
17. Test conditions shown in (a) of AC Test Loads unless otherwise noted.  
Document #: 38-05514 Rev. *D  
Page 8 of 12  
CY7C1352G  
Switching Waveforms  
[18, 19, 20]  
Read/Write Timing  
1
2
3
4
5
6
7
8
9
10  
t
CYC  
t
CLK  
t
t
t
CENS  
CES  
CENH  
CL  
CH  
CEN  
t
t
CEH  
CE  
ADV/LD  
WE  
BW[A:B]  
A1  
A2  
A4  
A3  
A5  
A6  
A7  
ADDRESS  
t
CO  
t
t
t
DS  
DH  
t
t
t
DOH  
OEV  
CLZ  
CHZ  
t
t
AS  
AH  
Data  
D(A1)  
D(A2)  
D(A2+1)  
Q(A3)  
Q(A4)  
Q(A4+1)  
D(A5)  
Q(A6)  
In-Out (DQ)  
t
OEHZ  
t
DOH  
t
OELZ  
OE  
WRITE  
D(A1)  
WRITE  
D(A2)  
BURST  
WRITE  
READ  
Q(A3)  
READ  
Q(A4)  
BURST  
READ  
WRITE  
D(A5)  
READ  
Q(A6)  
WRITE  
D(A7)  
DESELECT  
D(A2+1)  
Q(A4+1)  
DON’T CARE  
UNDEFINED  
Notes:  
For this waveform ZZ is tied low.  
18.  
19. When CE is LOW: CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH: CE is HIGH or CE is LOW or CE is HIGH.  
1
2
3
1
2
3
20. Order of the Burst sequence is determined by the status of the MODE (0= Linear, 1= Interleaved). Burst operations are optional.  
Document #: 38-05514 Rev. *D  
Page 9 of 12  
CY7C1352G  
Switching Waveforms (continued)  
[18, 19, 21]  
NOP, STALL, and DESELECT Cycles  
1
2
3
4
5
6
7
8
9
10  
CLK  
CEN  
CE  
ADV/LD  
WE  
BW[A:B]  
A1  
A2  
A3  
A4  
A5  
ADDRESS  
t
CHZ  
D(A4)  
D(A1)  
Q(A2)  
Q(A3)  
Q(A5)  
Data  
In-Out (DQ)  
WRITE  
D(A1)  
READ  
Q(A2)  
STALL  
READ  
Q(A3)  
WRITE  
D(A4)  
STALL  
NOP  
READ  
Q(A5)  
DESELECT  
CONTINUE  
DESELECT  
DON’T CARE  
UNDEFINED  
[22, 23]  
CLK  
ZZ Mode Timing  
t
t
ZZ  
ZZREC  
ZZ  
t
ZZI  
I
SUPPLY  
I
DDZZ  
t
RZZI  
ALL INPUTS  
(except ZZ)  
DESELECT or READ Only  
Notes:  
21. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle.  
22. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.  
23. DQs are in high-Z when exiting ZZ sleep mode.  
Document #: 38-05514 Rev. *D  
Page 10 of 12  
CY7C1352G  
Ordering Information  
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or  
visit www.cypress.com for actual products offered.  
Speed  
(MHz)  
Package  
Diagram  
Operating  
Range  
Ordering Code  
Package Type  
133 CY7C1352G-133AXC  
CY7C1352G-133AXI  
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free  
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free  
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free  
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free  
Commercial  
Industrial  
166 CY7C1352G-166AXC  
CY7C1352G-166AXI  
Commercial  
Industrial  
200 CY7C1352G-200AXC  
CY7C1352G-200AXI  
Commercial  
Industrial  
250 CY7C1352G-250AXC  
CY7C1352G-250AXI  
Commercial  
Industrial  
Package Diagram  
100-Pin TQFP (14 x 20 x 1.4 mm) (51-85050)  
16.00 0.20  
14.00 0.10  
1.40 0.05  
100  
81  
80  
1
0.30 0.08  
0.65  
TYP.  
12° 1°  
(8X)  
SEE DETAIL  
A
30  
51  
31  
50  
0.20 MAX.  
1.60 MAX.  
R 0.08 MIN.  
0.20 MAX.  
0° MIN.  
SEATING PLANE  
STAND-OFF  
0.05 MIN.  
0.15 MAX.  
NOTE:  
1. JEDEC STD REF MS-026  
0.25  
GAUGE PLANE  
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH  
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE  
R 0.08 MIN.  
0.20 MAX.  
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH  
3. DIMENSIONS IN MILLIMETERS  
0°-7°  
0.60 0.15  
0.20 MIN.  
51-85050-*B  
1.00 REF.  
DETAIL  
A
ZBT is a trademark of Integrated Device Technology, Inc. NoBL and No Bus Latency are trademarks of Cypress Semiconductor  
Corporation. All product and company names mentioned in this document are trademarks of their respective holders.  
Document #: 38-05514 Rev. *D  
Page 11 of 12  
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be  
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its  
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
CY7C1352G  
Document History Page  
Document Title: CY7C1352G 4-Mbit (256K x 18) Pipelined SRAM with NoBL™ Architecture  
Document Number: 38-05514  
Issue  
Date  
Orig. of  
Change  
REV. ECN NO.  
Description of Change  
**  
224362 See ECN  
288431 See ECN  
RKF  
VBL  
New data sheet  
Deleted 100 MHz and 225 MHz  
*A  
Changed TQFP package in Ordering Information section to lead-free TQFP  
*B  
*C  
332895 See ECN  
SYT  
RXU  
Modified Address Expansion balls in the pinouts for 100 TQFP Package as per  
JEDEC standards and updated the Pin Definitions accordingly  
Modified V  
V
test conditions  
OL, OH  
Replaced TBD’s for Θ and Θ to their respective values on the Thermal Resis-  
JA  
JC  
tance table  
Added lead-free product information for 119 BGA  
Updated the Ordering Information by shading and unshading MPNs as per avail-  
ability  
419256 See ECN  
Converted from Preliminary to Final  
Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901  
North First Street” to “198 Champion Court”  
Modified test condition from V < V to V < V  
IH  
DD  
IH  
DD  
< V  
Modified test condition from V  
< V to V  
DDQ  
DD  
DDQ DD  
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the  
Electrical Characteristics Table  
Replaced Package Name column with Package Diagram in the Ordering Information  
table  
Replaced Package Diagram of 51-85050 from *A to *B  
Updated the Ordering Information  
*D  
480124 See ECN  
VKN  
Added the Maximum Rating for Supply Voltage on V  
Updated the Ordering Information table.  
Relative to GND.  
DDQ  
Document #: 38-05514 Rev. *D  
Page 12 of 12  

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