IQ80960RM/RN Evaluation
Platform
Board Manual
February 1999
Order Number: 273160-004
Contents
Introduction ......................................................................................................................................1-1
®
i960 RM/RN I/O Processor and IQ80960RM/RN Features .....................................................1-3
1.3.1 IxWorks Real-Time Operating System .........................................................................1-4
1.3.2 TORNADO Build Tools.................................................................................................1-4
1.3.3 TORNADO Test and Debug Tools ...............................................................................1-4
1.4.1 CTOOLS and the MON960 Debug Monitor..................................................................1-5
1.7.1 Intel Customer Electronic Mail Support ........................................................................1-8
1.7.2 Intel Customer Support Contacts..................................................................................1-8
1.7.3 Related Information ......................................................................................................1-9
Getting Started.................................................................................................................................2-1
2.2.1 Installing Software Development Tools ........................................................................2-1
Hardware Installation.................................................................................................................2-2
2.3.1 Battery Backup .............................................................................................................2-2
2.3.2 Installing the IQ80960RM/RN Platforms in the Host System........................................2-2
2.3.3 Verify IQ80960RM/RN Platform is Functional ..............................................................2-2
Creating and Downloading Executable Files.............................................................................2-3
2.4.1 Sample Download and Execution Using GDB960........................................................2-3
Hardware Reference........................................................................................................................3-1
3.2.1 SDRAM Performance ...................................................................................................3-2
3.2.2 Upgrading SDRAM .......................................................................................................3-3
3.3.1 Flash ROM Programming.............................................................................................3-3
3.5.1 PCI Slots Power Availability..........................................................................................3-4
3.5.2 Interrupt and IDSEL Routing.........................................................................................3-5
3.10.1 User LEDs During Initialization.....................................................................................3-8
IQ80960RM/RN Evaluation Platform Board Manual
iii
®
i960 RM/RN I/O Processor Overview ............................................................................................4-1
Local Interrupts..........................................................................................................................4-3
MON960 Support for IQ80960RM/RN.............................................................................................5-1
Secondary PCI Bus Expansion Connectors..............................................................................5-1
MON960 Components...............................................................................................................5-1
5.2.1 MON960 Initialization ...................................................................................................5-1
5.2.2 80960JT Core Initialization ...........................................................................................5-2
5.2.3 Memory Controller Initialization ....................................................................................5-2
5.2.4 SDRAM Initialization.....................................................................................................5-2
5.2.5 Primary PCI Interface Initialization................................................................................5-3
5.2.6 Primary ATU Initialization .............................................................................................5-3
5.2.7 PCI-to-PCI Bridge Initialization .....................................................................................5-4
5.2.8 Secondary ATU Initialization ........................................................................................5-4
5.4.1 Secondary PCI Initialization..........................................................................................5-5
5.4.2 PCI BIOS Routines.......................................................................................................5-6
sysGenerateSpecialCycle............................................................................5-8
5.4.2.11 sysGetIrqRoutingOptions...........................................................................5-11
5.4.2.12 sysSetPCIIrq ..............................................................................................5-12
5.4.3 Additional MON960 Commands .................................................................................5-12
5.5.1 Board Level Diagnostics.............................................................................................5-12
5.5.2 Secondary PCI Diagnostics........................................................................................5-12
Bill of Materials............................................................................................................... A-1
Schematics..................................................................................................................... B-1
PLD Code....................................................................................................................... C-1
Recycling the Battery ..................................................................................................... D-1
iv
IQ80960RM/RN Evaluation Platform Board Manual
Figures
IQ80960RM/IQ80960RN Platform Functional Block Diagram...................................................1-1
®
i960 RM/RN I/O Processor Block Diagram..............................................................................4-1
IQ80960RM/RN Platform Memory Map.....................................................................................4-2
®
i960 RM/RN I/O Processor Interrupt Controller Connections..................................................4-4
®
i960 RM/RN I/O Processor DMA Controller ............................................................................4-6
Tables
A-1
A-2
Switch S1 Settings.....................................................................................................................3-7
IQ80960RM/RN Connectors and LEDs.....................................................................................3-9
IQ80960RN Bill of Materials ..................................................................................................... A-1
IQ80960RM Bill of Materials..................................................................................................... A-5
IQ80960RM/RN Evaluation Platform Board Manual
v
Introduction
1
®
This manual describes the IQ80960RM and IQ80960RN evaluation platforms for Intel’s i960
RM/RN I/O processor. The i960 RM/RN I/O processors combine an 80960JT core with two PCI
bus interfaces, as well as a memory controller, DMA channels, an interrupt controller interface, and
an I2C serial bus. The difference between the two processors is that the 80960RN utilizes 64-bit
primary PCI and secondary PCI buses while the 80960RM utilizes both a 32-bit primary and
secondary PCI bus. The IQ80960RM and IQ80960RN platforms are full-length PCI adapter boards
and are 8.9” in height to accommodate four standard PCI connectors on the secondary PCI bus.
The boards can be installed in any PCI host system that complies with the PCI Local Bus
Specification Revision 2.1. PCI devices can be connected to the secondary bus to build powerful
intelligent I/O subsystems.
Figure 1-1.
IQ80960RM/IQ80960RN Platform Functional Block Diagram
Secondary PCI Slot 4
Secondary PCI Slot 3
Secondary PCI Slot 2
Secondary PCI Slot 1
Console
Port
SDRAM (x72)
User
LED
RS-232
Serial Port
Battery
Backup
Support
Logic Analyzer Interface
i960® RM/RN
Logic
Analyzer
Interface
LED
Register
Flash
ROM
UART
Secondary PCI
I/O Processor
Bus 32/64-bits
ROM Bus
Primary PCI Bus 32/64-bits
IQ80960RM/RN Evaluation Board Manual
1-1
Introduction
Figure 1-2. IQ80960RN Platform Physical Diagram
64-Bit Secondary PCI Slots
168-Pin SDRAM DIMM Socket
J4
J3
J2
J1
RS-232 Serial Port
Flash Memory
J5
SW1
J8
J9
J10
J11
J12
CR1 CR2
CR3 CR4 CR5
J6
J7
U9
U11
JTAG Port
®
i960
U15
NiCd Batteries
Logic Analyzer Connectors
64-Bit PCI
1-2
IQ80960RM/RN Evaluation Board Manual
Introduction
®
1.1
i960 RM/RN I/O Processor and IQ80960RM/RN
Features
The i960 RM/RN I/O processor serves as the main component of a high performance, PCI-based
intelligent I/O subsystem. The IQ80960RM and IQ80960RN platforms allow the developer to
connect PCI devices to the i960 RM/RN I/O processors using the four secondary PCI expansion
connectors. The features of the IQ80960RM and IQ80960RN platforms are enumerated below and
• i960 RM/RN I/O processor
• Modified PCI long-card form factor
• 64-bit or 32-bit primary PCI bus interface (80960RM 32-bit only)
• 64-bit or 32-bit secondary PCI bus connected to the primary PCI interface with a PCI-to-PCI
bridge (80960RM 32-bit only)
• DMA channels on both PCI buses
• I2C Serial Bus
• 168-pin, 3.3V DIMM socket supporting 16 to 128 Mbytes of Synchronous DRAM organized
x72 to support Error Correction Code (ECC) and clocked at 66 MHz (ships with 16 M/ECC
installed)
• Serial console port based on 16C550 UART
• Eight user-programmable LEDs
• 3 Indicator LEDs: processor has passed self-test, 3.3 V is supplied to SDRAM, and 3.3 V is
supplied to secondary PCI slots
• Flash ROM, 2 Mbytes
• Logic analyzer connectors for SDRAM bus, ROM bus and secondary PCI arbitration signals
• Fan heatsink monitor circuit
• Battery backup for SDRAM
• JTAG header
1.2
Software Development Tools
®
1
A number of software development tools are available for the i960 processor family . This
manual provides information on two software development toolsets: Wind River System’s
Tornado* for I 0* and Intel’s CTOOLS. If you are using other software development tools, read
2
use your tools with this board.
IQ80960RM/RN Evaluation Board Manual
1-3
Introduction
1.3
Tornado* for I20* Software Development Toolset
Tornado for I 0 is a complete toolset featuring an integrated development environment including a
2
compiler, assembler, linker, and debugger. It also features a real-time operating system.
1.3.1
IxWorks* Real-Time Operating System
The IQ80960RM/RN platforms are equipped with Wind River Systems, Inc.’s IxWorks*. IxWorks
provides for the elements of the I O standard: an event-driven driver framework, host message
2
protocols, and executive modules for configuration and control. IxWorks also allows for the
writing of basic device drivers and provides NOS-to-driver independence. TORNADO for I O
2
provides a visual environment for building, testing and debugging of I O drivers.
2
1.3.2
1.3.3
TORNADO Build Tools
TORNADO for I O includes a collection of supporting tools that provide a complete development
2
tool chain. These include the compiler, assembler, linker and binary utilities. Also provided is an
I O module builder, which creates I O-loadable modules.
2
2
TORNADO Test and Debug Tools
TORNADO for I O test and debug tools include the dynamic loader, the CrossWind∗ debugger, the
2
WindSh* interactive shell, and a system browser.
The dynamic loader allows for interactive loading, testing, and replacement of individual object
modules that comprise a driver.
CrossWind is an extended version of GDB960. Using it you can debug I O drivers by setting
2
breakpoints on desired I O components. A variety of windows display source code, registers,
2
locals, stack frame, memory and so on.
WindSh allows you to communicate to the IQ80960RM/RN platform via an RS-232 serial port.
The IQ80960RM/RN platform supports port speeds from 300 to 115,200 bps. The shell can be
used to:
• control and monitor I O drivers
2
• format, send and receive driver messages
• examine hardware registers
• run automated I O test suites
2
The shell also provides essential debugging capabilities; including breakpoints, single stepping,
stack checking, and disassembly.
1-4
IQ80960RM/RN Evaluation Board Manual
Introduction
1.4
CTOOLS Software Development Toolset
Intel’s i960 processor software development toolset, CTOOLS, features advanced
C/C++ - language compilers for the i960 processor family. CTOOLS development toolset is
available for Windows* 95/NT-based systems and a variety of UNIX workstation hosts. These
products provide execution profiling and instruction scheduling optimizations and include an
assembler, a linker, and utilities designed for embedded processor software development.
1.4.1
CTOOLS and the MON960 Debug Monitor
In place of IxWorks, the IQ80960RM/RN platform can be equipped with Intel’s MON960, an
on-board software monitor that allows you to execute and debug programs written for i960
2
processors in a non-I O environment. The monitor provides program download, breakpoint, single
step, memory display, and other useful functions for running and debugging a program.
The IQ80960RM/RN platform works with the source-level debuggers provided with CTOOLS,
including GDB960 (command line version) and GDB960V (GUI version).
1.4.1.1
1.4.1.2
MON960 Host Communications
MON960 allows you to communicate and download programs developed for the IQ80960RM/RN
platform across a host system’s serial port or PCI interface. The IQ80960RM/RN platform supports
two methods of communication: terminal emulation and Host Debugger Interface (HDI).
Terminal Emulation Method
Terminal emulation software on your host system can communicate to MON960 on the
IQ80960RM/RN platform via an RS-232 serial port. The IQ80960RM/RN platform supports port
speeds from 300 to 115,200 bps. Serial downloads to MON960 require that the terminal emulation
software support the XMODEM protocol.
Configure the serial port on the host system for 300-115,200 baud, 8 bits, one stop bit, no parity
with XON/XOFF flow control.
1.4.1.3
Host Debugger Interface (HDI) Method
You may use a source-level debugger, such as Intel’s GDB960 and GDB960V to establish serial or
PCI communications with the IQ80960RM/RN platform. The MON960 Host Debugger Interface
(HDI) provides a defined messaging layer between MON960 and the debugger. For more
information on this interface, see the MON960 Debug Monitor User’s Manual (484290).
HDI connection requests cannot be detected by MON960 if the user has already initiated a
connection using a terminal emulator. In this case, the IQ80960RM/RN platform must be reset
before the debugger can connect to MON960.
1.5
SPI610 JTAG Emulation System
The SPI610 JTAG Emulation System from Spectrum Digital, Inc. is included in the
IQ80960RM/RN development kit. It furnishes the default host development environment-to-
evaluation board communication link based on the i960 RM/RN I/O processor JTAG interface.
IQ80960RM/RN Evaluation Board Manual
1-5
Introduction
Refer to the SPI610 Reference Manual for JTAG emulation system installation and operation for
both the Tornado and CTOOLS environment. Optionally, evaluation board serial port
communications can be used for this communication link (see Section 1.3.3, “TORNADO Test and
1.6
About This Manual
A brief description of the contents of this manual follows.
Introduces the IQ80960RM and IQ80960RN Evaluation Board features. This
chapter also describes Intel’s CTOOLS* and WindRiver Systems IxWorks*
software development tools, and defines notational-conventions and related
documentation.
Provides step-by-step instructions for installing the IQ80960RM or IQ80960RN
platform in a host system and downloading and executing an application
program. This chapter also describes Intel’s software development tools, the
MON960 Debug Monitor, IxWORKS, software installation, and hardware
configuration.
Describes the locations of connectors, switches and LEDs on the IQ80960RM
and IQ80960RN platforms. Header pinouts and register descriptions are also
provided in this chapter.
Presents an overview of the capabilities of the i960 RM/RN I/O processor and
includes the CPU memory map.
Describes a number of features added to MON960 to support application
Shows complete parts list IQ80960RM and IQ80960RN Evaluation Platforms.
Complete set of schematics for the IQ80960RM and IQ80960RN Evaluation
Platforms.
Example PLD code used on IQ80960RM and IQ80960RN evaluation boards
for SDRAM battery backup.
Information on the RBRC program and the locations of participating recycling
centers.
1-6
IQ80960RM/RN Evaluation Board Manual
Introduction
1.7
Notational-Conventions
The following notation conventions are consistent with other i960 RM/RN I/O processor
documentation and general industry standards.
# or overbar
In code examples the pound symbol (#) is appended to a signal name to
indicate that the signal is active. Normally inverted clock signals are
indicated with an overbar above the signal name (e.g., RAS).
Bold
Indicates user entry and/or commands.
PLD signal names are in bold lowercase letters (e.g., h_off, h_on).
Italics
Indicates a reference to related documents; also used to show emphasis.
Courierfont
Asterisks (*)
Indicates codeexamples and file directories and names.
On non-Intel company and product names, a trailing asterisk indicates
the item is a trademark or registered trademark. Such brands and names
are the property of their respective owners.
UPPERCASE
In text, signal names are shown in uppercase. When several signals share
a common name, each signal is represented by the signal name followed
by a number; the group is represented by the signal name followed by a
variable (n). In code examples, signal names are shown in the case
required by the software development tool in use.
Designations for
hexadecimal and
binary numbers
In text, instead of using subscripted “base” designators (e.g., FF ) or
16
leading “0x” (e.g., 0xFF) hexadecimal numbers are represented by a
string of hex digits followed by the letter H. A zero prefix is added to
numbers that begin with A through F. (e.g., FF is shown as 0FFH.) In
examples of actual code, “0x” is used. Decimal and binary numbers are
represented by their customary notations. (e.g., 255 is a decimal number
and 1111 1111 is a binary number. In some cases, the letter B is added to
binary numbers for clarity.)
1.8
Technical Support
Up-to-date product and technical information is available electronically from:
For technical assistance, electronic mail (e-mail) provides the fastest route to reach engineers
specializing in IQ80960RM and IQ80960RN issues. Posting messages on the Embedded
Within the United States and Canada you may contact the Intel Technical Support Hotline. See
Section 1.8.1 for a list of customer support sources for the US and other geographical areas.
IQ80960RM/RN Evaluation Board Manual
1-7
Introduction
1.8.1
Intel Customer Electronic Mail Support
®
For direct support from engineers specialing in i960 Microprocessor issues send e-mail in english
Questions and other messages may be posted to the Embedded Microprocessor Forum at
1.8.2
Intel Customer Support Contacts
Contact Intel Corporation for technical assistance for the IQ80960RM/RN evaluation platform.
Country
Literature
800-548-4725
Customer Support Number
United States
Canada
Europe
800-628-8686
800-468-8118 or 303-297-7763
Contact local distributor
Contact local distributor
Contact local distributor
Contact local distributor
800-628-8686
Contact local distributor
Contact local distributor
Contact local distributor
Contact local distributor
Australia
Israel
Japan
1-8
IQ80960RM/RN Evaluation Board Manual
Introduction
1.8.3
Related Information
To order printed manuals from Intel, contact your local sales representative or Intel Literature Sales
(1-800-548-4725).
Table 1-1.
Document Information
Product
Document Name
Company/ Order #
Intel # 273000
All
Developers’ Insight CD-ROM
i960® RM/RN I/O Processor Developer’s Manual
80960RM I/O Processor Data Sheet
80960RN I/O Processor Data Sheet
Intel # 273158
Intel # 273156
Intel # 273157
Intel # 273139
Intel #484290
80960RM/RN
i960® RM/RN I/O Processor Design Guide
MON960 Debug Monitor User’s Guide
PCI Special Interest Group
1-800-433-5177
PCI Local Bus Specification Revision 2.1
Wind River Systems, Inc.
#DOC-1173-8D-02
Writing I2O Device Drivers in IxWorks
Wind River Systems, Inc.
#DOC-1173-8D-03
IxWorks Reference Manual
VxWorks Programmer’s Guide
Tornado User’s Guide
Wind River Systems, Inc.
#DOC-11045-ZD-01
Wind River Systems, Inc.
#DOC-1116-8D-01
Wind River Systems, Inc.
#DOC-12381-8D-00
Tornado for I2O
Tornado for I2O Compact Disk Rev. 1.0
SP610 Emulation System Reference Manual
#TDK-12380-ZC-00
Spectrum Digital Inc.
# 503715
Contact Cyclone Microsystems for additional information about their products and literature:
Table 1-2.
Cyclone Contacts
Phone: 203-786-5536
Cyclone Microsystems
FAX: 203-786-5025
25 Science Park
New Haven CT 06511
e-mail: [email protected]
IQ80960RM/RN Evaluation Board Manual
1-9
Getting Started
2
This chapter contains instructions for installing the IQ80960RM/RN platform in a host system and,
how to download and execute an application program using Wind River System’s IxWorks∗ or
Intel’s CTOOLS software development toolsets.
2.1
Pre-Installation Considerations
This section provides a general overview of the components required to develop and execute a
program on the IQ80960RM/RN platform. IQ80960RM/RN evaluation boards support two
software development toolsets, Wind River System’s IxWorks and Intel’s CTOOLS.
IxWorks is a complete toolset featuring an integrated development environment including a
compiler, assembler, linker, and debugger. It also features a real-time operating system. If you are
using the IxWorks operating system with the TORNADO* development environment, refer to the
CTOOLS is a complete C/C++-language software-development toolset for developing embedded
applications to run on i960 processors. It contains a C/C++ compiler, the gcc960 and ic960 compiler
driver programs, an assembler, runtime libraries, a collection of software-development tools and
utilities, and printed and on-line documentation. The MON960 Debug Monitor User’s Guide fully
describes the components of MON960, including MON960 commands, the Host Debugger Interface
Library (HDIL), and the MONDB.EXE utility. If you are using MON960 and the CTOOLS toolset,
The IQ80960RM/RN evaluation boards are supplied with IxWorks intelligent real-time operating
system pre-loaded into the on-board Flash. You also have the option of installing the MON960
debug monitor, which is required if you are using the CTOOLS debugging tools, GDB960,
you to load MON960 onto the platform or re-load IxWorks.
2.2
Software Installation
2.2.1
Installing Software Development Tools
If you haven’t done so already, install your development software as described in its manuals. All
references in this manual to CTOOLS or CrossWind assume that the default directories were
selected during installation. If this is not the case, substitute the appropriate path for the default
path wherever file locations are referenced in this manual.
IQ80960RM/RN Evaluation Board Manual
2-1
Getting Started
2.3
Hardware Installation
Follow these instructions to get your new IQ80960RM/RN platform running. Be sure all items on
the checklist were provided with your IQ80960RM/RN.
Warning: Static charges can severely damage the IQ80960RM/RN platforms. Be sure you are properly
grounded before removing the IQ80960RM/RN platform from the anti-static bag.
2.3.1
Battery Backup
Battery backup is provided to save any information in SDRAM during a power failure. The
IQ80960RM/RN platform contains four AA NiCd batteries, a charging circuit and a regulator
circuit. The batteries installed in the IQ80960RM/RN platform are rated at 600 mA/Hr.
SDRAM technology provides a simple way of enabling data preservation through the self-refresh
command. When the processor receives an active Primary PCI reset it issues the self-refresh
command and drives the SCKE signals low. Upon seeing this condition, a PAL on the
IQ80960RM/RN platform holds SCKE low before the processor loses power. The batteries
maintain power to the SDRAM and the PAL to ensure self-refresh mode. When the PAL detects
PRST# returning to inactive state, the PAL releases the hold on SCKE.
The battery circuit can be disabled by removing the batteries. LED CR4 indicates when the SDRAMs
have sufficient power. If the batteries remain in the evaluation platform when it is depowered and/or
removed from the chassis, the batteries will maintain the SDRAM for approximately 30 hours. Once
power is again applied, the batteries will be fully charged in about 4 hours.
2.3.2
2.3.3
Installing the IQ80960RM/RN Platforms in the Host System
If you are installing the IQ80960RM/RN platform for the first time, visually inspect the board for
any damage that may have occurred during shipment. If there are visible defects, return the board
for replacement. Follow the host system manufacturer’s instructions for installing a PCI adapter.
The IQ80960RM/RN platform is a full-length PCI adapter and requires a PCI slot that is free from
obstructions. The IQ80960RM/RN platform is taller than specified in the PCI Local Bus
Specification Revision 2.1. The extended height of the board will require you to keep the cover off
of your PC. Refer to Chapter 3 for physical dimensions of the board.
Verify IQ80960RM/RN Platform is Functional
These instructions assume that you have already installed the IQ80960RM/RN platform in the host
1. To connect the serial port for communicating with and downloading to the IQ80960RM/RN
platform, connect the RS-232 cable (provided with the IQ80960RM/RN) from a free serial
port on the host system to the phone jack-style connector on the IQ80960RM/RN platform.
2. Upon power-up, the red FAIL LED turns off, indicating that the processor has passed its self-test.
3. If you have IxWorks installed in the flash ROM, the user LEDs display the binary pattern 99H.
In the IxWorks development environment, raw serial input/output is not used. Instead, the
Wind DeBug (WDB) protocol is run over the serial port, to allow communication with
Tornado development tools. If the terminal emulation package is running at 115,200 baud, the
letters “WDB_READY” display prior to launching in the WDB serial protocol.
2-2
IQ80960RM/RN Evaluation Board Manual
Getting Started
4. If you have MON960 installed in the flash ROM, press <ENTER> on a terminal connected to
the IQ80960RM/RN platform to bring up the MON960 prompt. MON960 automatically
adjusts its baud rate to match that of the terminal at start-up. At baud rates other than 9600, it
may be necessary to press <ENTER> several times.
2.4
Creating and Downloading Executable Files
To download code to the IQ80960RM/RN platform running IxWorks, consult Wind River
documentation on the supplied TORNADO for I O CD-ROM. To download code to the
2
IQ80960RM/RN platform, your compiler produces an ELF-format object file.
To download code to the IQ80960RM/RN platform running CTOOLS, consult the CTOOLS
documentation for information regarding compiling, linking, and downloading applications.
During a download, MON960 checks the link address stored in the ELF file, and stores the file at
that location on the IQ80960RM/RN platform. If the executable file is linked to an invalid address
on the IQ80960RM/RN platform, MON960 aborts the download.
2.4.1
Sample Download and Execution Using GDB960
This example shows you how to use GBD960 to download and execute a file named myappvia
the serial port.
• Invoke GDB960. From a Windows 95/NT command prompt, issue the command:
gdb960 -r com2 myapp
This command establishes communication and downloads the file myapp.
• To execute the program, enter the command from the GDB960 command prompt:
(gdb960) run
More information on the GDB960 commands mentioned in this section can be found in the
GDB960 User’s Manual.
IQ80960RM/RN Evaluation Board Manual
2-3
Hardware Reference
3
3.1
Power Requirements
The IQ80960RM/RN platform draws power from the PCI bus. The power requirements of the
power required by a PCI card(s) mounted on one or more of the IQ80960RM/RN platforms’ four
expansion slots.
Table 3-1.
IQ80960RN Platform Power Requirements
Voltage
Typical Current
Maximum Current
+3.3 V
+5 V
0 V*
1.45 A
286 mA
1 mA
0 V*
1.96 A
485 mA
1 mA
+12 V
-12 V
NOTE: Does not include the power required by a PCI card(s) mounted on the IQ80960RN platform.
* +3.3V for 80960RN Processor created on board from +5V.
Table 3-2.
IQ80960RM Platform Power Requirements
Voltage
Typical Current
Maximum Current
+3.3 V
+5 V
0 V*
1.32 A
284 mA
1 mA
0 V*
1.86 A
485 mA
1 mA
+12 V
-12 V
NOTE: Does not include the power required by a PCI card(s) mounted on the IQ80960RM platform.
* +3.3V for 80960RM Processor created on board from +5V.
3.2
SDRAM
The IQ80960RM/RN platform is equipped with a 168-pin DIMM socket formatted to accept +3.3V
synchronous DRAM with or without Error Correction Code (ECC). The socket will accept SDRAM
from 8 Mbytes to 128 Mbytes. 128 Mbyte SDRAMs are available in both x64 and x72 configurations.
Note that 8 Mbyte SDRAMs are only for x64 or non-ECC memory. The SDRAM is accessible from
either of the PCI buses, via the ATUs, and the local bus on the IQ80960RM/RN platform.
IQ80960RM/RN Evaluation Board Manual
3-1
Hardware Reference
3.2.1
SDRAM Performance
The IQ80960RM/RN platform uses 72-bit SDRAM with ECC or 64-bit SDRAM without ECC.
SDRAM allows zero data-to-data wait state operation at 66 MHz. The memory controller unit
®
(MCU) of the i960 RM/RN I/O processor supports SDRAM burst lengths of four. A burst length
of four enables seamless read/write bursting of long data streams, as long as the MCU does not
cross the page boundary. Page boundaries are naturally aligned 2 Kbyte blocks. 72-bit SDRAM
with ECC allows a maximum throughput of 528 Mbytes per second.
Both 16 Mbit and 64 Mbit SDRAM devices are supported. The MCU keeps two pages per bank
open simultaneously for 16 Mbit devices and 4 pages per bank for 64 Mbit devices. Simultaneously
open pages allow for greater performance for sequential access, distributed across multiple internal
multiple 40 byte access.
Table 3-3.
SDRAM Performance
Cycle Type
Table Clocks
Performance Bandwidth
Read Page Hit (8 bytes)
Read Page Miss (8 bytes)
Read Page Hit (40 bytes)
Read Page Miss (40 bytes)
Write Page Hit (8 bytes)
Write Page Miss (8 bytes)
Write Page Hit (40 bytes)
Write Page Miss (40 bytes)
7
12
11
16
4
76 Mbytes/sec
44 Mbytes/sec
240 Mbytes/sec
165 Mbytes/sec
132 Mbytes/sec
66 Mbytes/sec
330 Mbytes/sec
220 Mbytes/sec
8
8
12
Note that if ECC is enabled and you attempt a partial write — less than 64 bits — you will incur a
penalty. Because ECC is enabled, the MCU will translate the write into a read-modify-write
transaction. Therefore, for a single byte write the clock count will be 11.
3-2
IQ80960RM/RN Evaluation Board Manual
Hardware Reference
3.2.2
Upgrading SDRAM
The IQ80960RM/RN is equipped with 16 Mbytes of SDRAM with ECC inserted in the 168-pin
DIMM socket. The memory may be expanded by inserting up to a 128 Mbyte module into the
SDRAM modules with or without ECC rated at 10 ns should be used on the IQ80960RM/RN
platform. The column labeled ECC determines if that particular memory configuration can be used
with ECC.
Table 3-4.
SDRAM Configurations
SDRAM
Technology Arrangement
SDRAM
Total Memory
SIze
# Banks
Row
11
Column
ECC
1
2
1
2
1
2
1
2
Yes
Yes
No
16 Mbytes
32 Mbytes
8 Mbytes
2M x 8
16 Mbit
9
8
9
8
1M x 16
11
No
16 Mbytes
64 Mbytes
128 Mbytes
32 Mbytes
64 Mbytes
Yes
Yes
No
8M x 8
64 Mbit
12
4M x 16
12
No
3.3
Flash ROM
An E28F016S5 (2 Mbytes) Flash ROM is included on the IQ80960RM/RN platform. This Flash
ROM contains IxWorks* and may be used to store user applications.
3.3.1
Flash ROM Programming
Two types of Flash ROM programming exist on the IQ80960RM/RN platform. The first is normal
application development programming. This occurs using IxWorks to download new software and
the 80960JT core to write the new code to the Flash ROM. During this time the boot sectors
(containing IxWorks) are write protected.
The second type of Flash ROM programming is loading the boot sectors. You will not be required
to load the boot sectors except:
• To load MON960
• To load a new release of IxWorks
• To change between the check build and the free build of IxWorks
The following steps are required to program the Flash ROM boot sectors:
1. Set switch S1 #’s 1 and 2 to the on position.
2. Reset the board by cycling power on the workstation.
3. Run the Intel DOS-based flash utility to program the Flash ROM boot sectors.
4. Set switch S1 #’s 1 and 2 to the off position.
5. Reset the board by cycling power on the workstation.
IQ80960RM/RN Evaluation Board Manual
3-3
Hardware Reference
3.4
Console Serial Port
The console serial port on the IQ80960RM/RN platform, based on a 16C550 UART, is capable of
operation from 300 to 115,200 bps. The port is connected to a phone jack-style plug on the
IQ80960RM/RN platform. The DB25 to RJ-45 cable included with the IQ80960RM/RN can be
used to connect the console port to any standard RS-232 port on the host system.
The UART on the IQ80960RM/RN platform is clocked with a 1.843 MHz clock, and may be
programmed to use this clock with its internal baud rate counters. The UART register addresses are
shown in Table 3-5; refer to the 16C550 device data book for a detailed description of the registers
and device operation. Note that some UART addresses refer to different registers depending on
whether a read or a write is being performed.
Table 3-5.
UART Register Addresses
Address
Read Register
Write Register
E000 0000H
E000 0001H
E000 0002H
E000 0003H
E000 0014H
E000 0015H
E000 0016H
E000 0017H
Receive Holding Register
Unused
Transmit Holding Register
Interrupt Enable Register
FIFO Control Register
Line Control Register
Modem Control Register
Unused
Interrupt Status Register
Unused
Unused
Line Status Register
Modem Status Register
Scratchpad Register
Unused
Scratchpad Register
3.5
Secondary PCI Bus Expansion Connectors
Four PCI Expansion Slots are available on the IQ80960RM/RN platform. The IQ80960RM
supports 32-bit PCI expansion and the IQ80960RN supports 64-bit PCI expansion. The slots are
designed for +5V PCI signalling and accommodate PCI cards with +5V or universal signalling
capabilities.
3.5.1
PCI Slots Power Availability
Power from the Primary PCI bus, +3.3V, +5V, +12V, and –12V, is routed to the Secondary PCI bus
expansion slots. +3.3V is only available at the secondary PCI slots if the host system makes +3.3V
available on the Primary PCI slots. LED CR5 indicates if this power is available.
3-4
IQ80960RM/RN Evaluation Board Manual
Hardware Reference
3.5.2
Interrupt and IDSEL Routing
Table 3-6.
Secondary PCI Bus Interrupt and IDSEL Routing
Connector
IDSEL
INTA#
INTB#
INTC#
INTD#
J11
J12
J13
J14
SAD16
SAD17
SAD18
SAD19
SINTA#
SINTB#
SINTC#
SINTD#
SINTB#
SINTC#
SINTD#
SINTA#
SINTC#
SINTD#
SINTA#
SINTB#
SINTD#
SINTA#
SINTB#
SINTC#
3.6
Battery Backup
Battery backup is provided to save any information in SDRAM during a power failure. The
IQ80960RM/RN platform contains four AA NiCd batteries, a charging circuit and a regulator
circuit. The batteries installed in the IQ80960RM/RN platform are rated at 600 mA/Hr.
SDRAM technology provides a simple way of enabling data preservation though the self-refresh
command. When the processor receives an active Primary PCI reset it will issue the self-refresh
command and drive the SCKE signals low. Upon seeing this condition a PAL on the
IQ80960RM/RN platform will hold SCKE low before the processor loses power. The batteries will
maintain power to the SDRAM and the PAL to ensure self-refresh mode. When the PAL sees
PRST# returning to inactive state the PAL will release the hold on SCKE.
The battery circuit can be disabled by removing the batteries. LED CR4 indicates when the
SDRAMs have sufficient power. If the batteries remain in the evaluation platform when it is
depowered and/or removed from the chassis, the batteries will maintain the SDRAM for
approximately 30 hours. Once power is again applied, the batteries will be fully charged in about
four hours.
3.7
Loss of Fan Detect
The i960 RM/RN I/O processor can be cooled by an active heat sink mounted on top. The fan
provides a square wave output that is monitored by a comparator circuit on the IQ80960RM/RN
platform. The frequency of the fan output is approximately 9K RPM. If the frequency falls below
approximately 8K RPM the circuit will provide an interrupt to the processor. This is an evaluation
board feature intended as an example of system hardware monitoring, since the IQ80960RM/RN
platform does not ship with a heatsink.
Note: When using a passive heat sink, the processor never sees an interrupt from not having a fan.
IQ80960RM/RN Evaluation Board Manual
3-5
Hardware Reference
3.8
Logic Analyzer Headers
There are five logic analyzer connectors on the IQ80960RM/RN platform. The connectors are
Mictor type, AMP part # 767054-1. Hewlett-Packard and Tektronix manufacture and sell interfaces
to these connectors. The logic analyzer connectors allow for interfacing to the SDRAM and ROM
assignments for each.
Table 3-7.
Logic Analyzer Header Definitions
PIN
J9
J11
J12
J10
J8
3
SDRAMCLK
SDQM7
SDQM6
SDQM5
SDQM4
SDQM3
SDQM2
SDQM1
SDQM0
SCB7
SCB6
SCB5
SCB4
SCB3
SCB2
SCB1
SCB0
SA0
4
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
RAD15
RAD14
RAD13
RAD12
RAD11
RAD10
RAD9
RAD8
RAD7
RAD6
RAD5
RAD4
RAD3
RAD2
RAD1
RAD0
RAD16
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
SCE0#
SCE1#
DQ2
DQ1
SBA1
DQ0
SBA0
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
SREQ0#
SREQ1#
SREQ2#
SREQ3#
SREQ4#
SREQ5#
SGNT0#
SGNT1#
SGNT2#
SGNT3#
SGNT4#
SGNT5#
SA1
SA2
SA3
RALE
RCE0#
RCE1#
ROE#
RWE#
SA4
SA5
SA6
SA7
SA8
SA9
I_RST#
SA10
SA11
SWE#
SCAS#
SRAS#
P_PCICLK
RALE
3-6
IQ80960RM/RN Evaluation Board Manual
Hardware Reference
3.9
JTAG Header
The JTAG header allows debugging hardware to be quickly and easily connected to some of the
IQ80960RM/RN processor’s logic signals.
The JTAG header is a 16-pin header. A 3M connector (part number 2516-6002UG) is required to
connector are keyed using a tab on the connector and a slot on the header to ensure proper installation.
Each signal in the JTAG header is paired with its own ground connection to avoid the noise problems
®
associated with long ribbon cables. Signal descriptions are found in the i960 RM/RN I/O Processor
Developer’s Manual, 80960RM I/O Processor Data Sheet and the 80960RN I/O Processor Data Sheet.
Table 3-8.
JTAG Header Pinout
Pin
Signal
Input/Output to 80960RM/RN
Pin
Signal
1
3
TRST#
TDI
IN
IN
2
4
GND
GND
GND
GND
GND
GND
GND
GND
5
TDO
OUT
IN
6
7
TMS
8
9
TCK
IN
10
12
14
16
11
13
15
LCDINIT#
I_RST#
PWRVLD
IN
OUT
OUT
configurations.
Table 3-9.
Switch S1 Settings
Position
Name
Description
Default
Determines if the processor is to be held in reset.
ON = hold in rest
S1-1
RST_MODE#
OFF
OFF = allows processor initialization
Determines if the Primary PCI interface will be disabled.
ON = allows Primary PCI configuration cycles to occur
OFF = retries all Primary PCI configuration cycles
S1-2
S1-3
S1-4a
RETRY
OFF
OFF
OFF
Notifies Memory Controller of the SDRAM width.
32BITMEM_EN# ON = Memory Controller utilizes 32-bit SDRAM access protocol
OFF = Memory Contoller utilizes 64-bit SDRAM access protocol
Determines whether Secondary PCI bus is a 32- or 64-bit bus.
32BITPCI_EN# ON = indicates Secondary PCI bus is a 32-bit bus
OFF = indicates Secondary PCI bus is a 64-bit bus
a.
This switch is active for IQ80960RN ONLY.
IQ80960RM/RN Evaluation Board Manual
3-7
Hardware Reference
3.10
User LEDs
The IQ80960RM/RN platform has a bank of eight user-programmable LEDs, located on the upper edge of
the adapter board. These LEDs are controlled by a write-only register and used as a debugging aid during
development. Software can control the state of the user LEDs by writing to the LED Register, located at
E004 0000H. Each of the eight bits of this register correspond to one of the user LEDs. Clearing a bit in the
LED Register by writing a “0” to it turns the corresponding LED “on”, while setting a bit by writing a “1”
to it turns the corresponding LED “off”. Resetting the IQ80960RM/RN platform results in clearing the
The user LEDs are numbered in descending order from left to right, with LED7 being on the left
when looking at the component side of the adapter.
Figure 3-1. LED Register Bitmap
7
6
5
4
3
2
1
0
User LED 7
User LED 6
User LED 5
User LED 4
User LED 3
User LED 2
User LED 1
User LED 0
3.10.1
User LEDs During Initialization
MON960 indicates the progress of its hardware initialization on the user LEDs. In the event that
initialization should fail for some reason, the number of lit LEDs can be used to determine the
Table 3-10. Start-up LEDs MON960
LEDs
Tests
LED 0
LED 1
LED 2
LED 3
LED 4
LED 5
LED 6
LED 7
SDRAM serial EEPROM checksum validated
UART walking ones test passed
DRAM walking ones test passed
DRAM multiword test passed
Hardware initialization started
Flash ROM initialized
PCI-to-PCI Bridge initialized
UART internal loopback test passed
3-8
IQ80960RM/RN Evaluation Board Manual
Hardware Reference
Table 3-11.
IQ80960RM/RN Connectors and LEDs
Item
Description
Secondary PCI bus expansion connector
J1-J4
J5
168-pin SDRAM DIMM socket
JTAG connector
J6
J7
Serial port connector
J8
Logic analyzer connector for flash ROM bus
J10
Logic analyzer connector for Secondary PCI bus arbitration signals
Logic analyzer connector for access to SDRAM bus
Active heatsink connector for example fan monitor circuit
Eight user LEDs
J9, J11, J12
J13
CR1, CR2
CR3
CR4
CR5
S1
Self-test fail LED
Battery backup SDRAM, 3.3 V available
Indicates host system providing 3.3 V to Secondary PCI bus connectors
IQ80960RM/RN Evaluation Board Manual
3-9
i960® RM/RN I/O Processor Overview 4
This chapter describes the features and operation of the processor on the IQ80960RM/RN
®
platform. For more detail, refer to the i960 RM/RN I/O Processor Developer’s Manual.
®
Figure 4-1. i960 RM/RN I/O Processor Block Diagram
Local Memory
(SDRAM, Flash)
I2C Serial Bus
80960 Core
Processor
Memory
Controller
Bus
Interface
Unit
I2C Bus
Interface
Internal
Arbitration
Application
Accelerator
64-bit Internal Bus
Address
Translation
Unit
Address
Translation
Unit
Messaging
Unit
One DMA
Channel
Two DMA
Channels
PCI to PCI
Bridge
64-bit/32-bit Primary PCI Bus
64-bit/32-bit Secondary PCI Bus
Performance
Monitoring
Unit
Secondary
PCI
Arbitration
IQ80960RM/RN Evaluation Board Manual
4-1
i960® RM/RN I/O Processor Overview
4.1
CPU Memory Map
9002 0000H on the IQ80960RM/RN platform are reserved for various functions of the i960
RM/RN I/O processor, as shown on the memory map. Documentation for these areas, as well as the
®
processor memory mapped registers at FF00 0000H and the IBR, can be found in the i960 RM/RN
I/O Processor Developer’s Manual.
Figure 4-2. IQ80960RM/RN Platform Memory Map
Processor
Memory Mapped
Registers
Flash ROM
and
Processor Registers
FF00 0000H
FEE0 0000H
F000 0000H
Flash ROM
Reserved
F000 0000H
On-board Devices
E000 0000H
Reserved
LED Register
(write only)
E004 0000H
E000 0000H
B000 0000H
DRAM
UART
A000 0000H
Reserved
9002 0000H
ATU Outbound
Translation Windows
8000 0000H
ATU Outbound
Direct Addressing Window
0000 2000H
Reserved
0000 1900H
Peripheral
Memory Mapped Registers
0000 0800H
Reserved
0000 0400H
Processor Internal Data RAM
0000 0000H
4-2
IQ80960RM/RN Evaluation Board Manual
i960® RM/RN I/O Processor Overview
4.2
Local Interrupts
The i960 RM/RN I/O processor is built around an 80960JT core, which has seven external interrupt
lines designated XINT0# through XINT5# and NMI#. In the i960 RM/RN I/O processor, these
interrupt lines are not directly connected to external interrupts, but pass through a layer of internal
interrupt routing logic. Figure 4-3 shows the interrupt connections on the i960 RM/RN I/O processor.
XINT0# through XINT3# on the 80960JT core can be used to receive PCI interrupts from the
secondary PCI bus, or these interrupts can be passed through to the primary PCI interface,
depending on the setting of the XINT Select bit of the PCI Interrupt Routing Select Register in the
i960 RM/RN I/O processor. On the IQ80960RM/RN platform, XINT0# through XINT3# are
configured to receive interrupts from the secondary PCI bus.
XINT4# and XINT5# on the i960 RM/RN I/O processor may be connected to interrupt sources
external to the processor. On the IQ80960RM/RN platform, XINT4# is connected to the loss of fan
detect and XINT5# is connected to the 16C550 UART.
XINT6#, XINT7# receive interrupts from internal sources. NMI# receives interrupts from internal
sources and from an external source. Since all of these interrupts accept signals from multiple
sources, a status register is provided for each of them to allow service routines to identify the
source of the interrupt. Each of the possible interrupt sources is assigned a bit position in the status
platform, the NMI# interrupt is not connected to any external interrupt source and receives
interrupts only from the internal devices on the i960 RM/RN I/O processor. Note that all error
conditions result in an NMI# interrupt.
IQ80960RM/RN Evaluation Board Manual
4-3
i960® RM/RN I/O Processor Overview
®
Figure 4-3. i960 RM/RN I/O Processor Interrupt Controller Connections
®
i960 RN/RM I/O Processor
80960 Outbound Doorbell 0
80960 Outbound Doorbell 1
80960 Outbound Doorbell 2
80960 Outbound Doorbell 3
S_INTD# Select bit
S_INTC# Select bit
S_INTB# Select bit
S_INTA# Select bit
m
u
XINT0#
XINT1#
XINT2#
S_INTA#/XINT0#
S_INTB#/XINT1#
x
i960 Core
Processor
m
u
x
XINT3#
XINT4#
XINT5#
XINT6#
XINT7#
NMI#
m
u
S_INTC#/XINT2#
S_INTD#/XINT3#
x
m
u
x
XINT4#
(Loss of Fan)
XINT5# (UART)
DMA Channel 0 Interrupt Pending
DMA Channel 1 Interrupt Pending
DMA Channel 2 Interrupt Pending
Performance Monitor Unit Interrupt Pending
Application Accelerator Interrupt Pending
I2C Bus Interface Unit Interrupt Pending
Messaging Unit Interrupt Pending
Primary ATU/Start BIST Interrupt Pending
Bus Interface Unit Error
Primary PCI Bridge Interface Error
Secondary PCI Bridge Interface Error
Primary ATU Error
Secondary ATU Error
Memory Controller Unit Error
DMA Channel 0 Error
DMA Channel 1 Error
DMA Channel 2 Error
Messaging Unit Error
Application Accelerator Unit Error
NMI# (N/C)
4-4
IQ80960RM/RN Evaluation Board Manual
i960® RM/RN I/O Processor Overview
4.3
4.4
CPU Counter/Timers
The i960 RM/RN I/O processor is equipped with two on-chip counter/timers which are clocked
with the i960 RM/RN I/O processor clock signal. The i960 RM/RN I/O processor receives its clock
from the primary PCI interface clock, generated by the motherboard. Most motherboards generate
a 33 MHz clock signal, although the PCI specification requires a clock frequency between 0 and
33 MHz. The timers can be programmed for single-shot or continuous mode, and can generate
interrupts to the processor when the countdown expires.
Primary PCI Interface
The primary PCI interface on the IQ80960RM/RN platform provides the i960 RM/RN I/O
processor with a connection to the PCI bus on the host system. Only the PCI-to-PCI bridge unit on
the i960 RM/RN I/O processor is directly connected to the primary PCI interface. Devices installed
on the expansion slots are connected to the PCI bus via the bridge unit on the i960 RM/RN I/O
processor. The PCI-to-PCI bridge accepts Type 1 configuration cycles destined for devices on the
secondary bus, and will forward them as Type 0 or Type 1 configuration cycles, or as special
cycles. The IQ80960RN platform interfaces to a 64-bit PCI bus and the IQ80960RM platform
interfaces to a 32-bit PCI bus.
4.5
Secondary PCI Interface
The secondary PCI interface provided by the i960 RM/RN I/O processor is used to connect PCI
cards via the expansion slots to the host system’s PCI bus. PCI cards are attached to the
IQ80960RM/RN platform with a standard PCI connector and may contain up to four separate PCI
devices. The i960 RM/RN I/O processor provides PCI-to-PCI bridge functionality to map installed
PCI devices onto the host PCI bus, and supports transaction forwarding in both directions across
the bridge. PCI devices connected via the expansion slots can therefore act as masters or slaves on
the host system’s PCI bus. Additional PCI-to-PCI bridge devices are supported by the i960 RM/RN
I/O processor on its secondary PCI interface and can be designed into add-on PCI cards. In
addition, the i960 RM/RN I/O processor supports “private” PCI devices on its secondary bus.
Private devices are hidden from initialization code on the host system, and are configured and
accessed directly by the i960 RM/RN I/O processor. These devices are not part of the normal PCI
address space, but they can act as PCI bus masters and transfer data to and from other PCI devices
in the system.
Unless designated as private devices, PCI devices installed on the secondary PCI interface of the
IQ80960RM/RN platform are mapped into the system-wide PCI address space by configuration
software running on the host system. No logical distinction is made at the system level between
devices on the primary PCI bus and devices on secondary buses; all transaction forwarding is
handled transparently by the PCI-to-PCI bridge. Configuration cycles and read and write accesses
from the host are forwarded through the PCI-to-PCI bridge unit of the i960 RM/RN I/O processor.
Master read and write cycles from devices on the secondary PCI bus are also forwarded to the host
bus by the PCI-to-PCI bridge unit.
IxWORKS allows secondary PCI devices to be configured as Public or Private. Public devices are
configured by the PCI host. Private devices are configured by the IxWORKS kernel and the
device-specific HDM.
IQ80960RM/RN Evaluation Board Manual
4-5
i960® RM/RN I/O Processor Overview
4.6
DMA Channels
The i960 RM/RN I/O processor features three independent DMA channels, two of which operate
on the primary PCI interface, whereas the remaining one operates on the secondary PCI interface.
All three of the DMA channels connect to the i960 RM/RN I/O processor’s local bus and can be
used to transfer data from PCI devices to memory on the IQ80960RM/RN platform. Support for
chaining, and scatter/gather is built into all three channels. The DMA can address the entire 264
bytes of address space on the PCI bus and 232 bytes of address space on the internal bus.
®
Figure 4-4. i960 RM/RN I/O Processor DMA Controller
Primary PCI Bus
DMA Channel 0
80960
DMA Channel 1
DMA Channel 2
Local Bus
PCI to PCI Bridge
Secondary PCI Bus
4.7
Application Accelerator Unit
The Application Accelerator provides low-latency, high-throughput data transfer capability
between the AA unit and 80960 local memory. It executes data transfers to and from 80960 local
memory and also provides the necessary programming interface. The Application Accelerator
performs the following functions:
• Transfers data (read) from memory controller
• Performs an optional boolean operation (XOR) on read data
• Transfers data (write) to memory controller
The AA unit features:
• 128-byte, arranged as 8-byte x 16-deep store queue
• Utilization of the 80960RN/RM processor memory controller interface
32
• 2 addressing range on the 80960 local memory interface
• Hardware support for unaligned data transfers for the internal bus
• Full programmability from the i960 core processor
• Support for automatic data chaining for gathering and scattering of data blocks
4-6
IQ80960RM/RN Evaluation Board Manual
i960® RM/RN I/O Processor Overview
Figure 4-5 shows a simplified connection of the Application Accelerator to the i960 RM/RN I/O
Processor Internal Bus.
Figure 4-5. Application Accelerator Unit
Application Accelerator Unit
Packing/
Unpacking
Unit
Boolean Unit
Data Queue
80960
64-bit
Bus Interface
Internal Bus
4.8
Performance Monitor Unit
The Performance Monitoring features aid in measuring and monitoring various system parameters
that contribute to the overall performance of the processor. The monitoring facility is generically
referred to as PMON – Performance Monitoring. The facility is model specific, not architectural;
its intended use is to gather performance measurements that can be used to retune/refine code for
better system level performance.
The PMON facility provided on the i960 RM/RN I/O processor comprises:
• One dedicated global Time Stamp counter, and
• Fourteen (14) Programmable Event counters
The global time stamp counter is a dedicated, free running 32-bit counter.
The programmable event counters are 32-bits wide. Each counter can be programmed to observe
an event from a defined set of events. An event consists of a set of parameters which define a start
condition and a stop condition. The monitored events are selected by programming an event select
register (ESR).
IQ80960RM/RN Evaluation Board Manual
4-7
MON960 Support for IQ80960RM/RN 5
This chapter discusses a number of additions that have been made to MON960 to support the
2
IQ80960RM/RN in an optional non-I O capacity. For complete documentation on the operation of
MON960, see the MON960 Debug Monitor User’s Guide. The IQ80960RM/RN evaluation
platform ships with IxWorks* from Wind River Systems installed in flash firmware. To use
CTOOLS and MON960 instead of IxWorks, you need to download MON960 into the onboard
descriptions of both IxWorks and CTOOLS.
5.1
5.2
Secondary PCI Bus Expansion Connectors
The IQ80960RM/RN platform contains four secondary PCI bus expansion connectors to give users
®
access to the secondary PCI bus of the i960 RM/RN I/O processor. Extensions to MON960
perform secondary PCI bus initialization including the establishment of a secondary PCI bus
address map. Routines compatible with the PCI Local Bus Specification Revision 2.1 allow the
software on the IQ80960RM/RN platform to search for devices on the secondary PCI bus and read
and write the configuration space of those devices.
MON960 Components
The remaining sections of this chapter assume that MON960 is installed in the onboard Flash,
replacing IxWorks. The IQ80960RM/RN optional MON960 debug monitor consists of four main
components:
• Initialization firmware
• MON960 extensions
• MON960 kernel
• Diagnostics/example code
These four components together are referred to as MON960.
5.2.1
MON960 Initialization
At initialization, MON960 puts the IQ80960RM/RN platform into a known, functional state that
allows the host processor to perform PCI initialization. Once in this state, the MON960 kernel and
the MON960 extensions can load and execute correctly. Initialization is performed after a RESET
condition. MON960 initialization encompasses all major portions of the i960 RM/RN I/O
processor and IQ80960RM/RN platform including 80960JT core initialization, Memory Controller
initialization, SDRAM initialization, Primary PCI Address Translation Unit (ATU) initialization,
and PCI-to-PCI Bridge Unit initialization.
The IQ80960RM/RN platform is designed to use the Configuration Mode of the i960 RM/RN I/O
processor. Configuration Mode allows the 80960JT core to initialize and control the initialization process
before the PCI host configures the i960 RM/RN I/O processor. By utilizing Configuration Mode, the user
IQ80960RM/RN Evaluation Board Manual
5-1
MON960 Support for IQ80960RM/RN
is given the ability to initialize the PCI configuration registers to values other than the default power-up
values. Configuration Mode gives the user maximum flexibility to customize the way in which the i960
RM/RN I/O processor and IQ80960RM/RN platform appear to the PCI host configuration software.
5.2.2
80960JT Core Initialization
The 80960JT core begins the initialization process by reading its Initial Memory Image (IMI) from
a fixed address in the boot ROM (FEFF FF30H in the i960 address space). The IMI includes the
Initialization Boot Record (IBR), the Process Control Block (PRCB), and several system data
structures. The IBR provides initial configuration information for the core and integrated
peripherals, pointers to the system data structures and the first instruction to be executed after
processor initialization, and checksum words that the processor uses in its self-test routine. In
addition to the IBR and PRCB, the required data structures are the:
• System Procedure Table
• Control Table
• Interrupt Table
• Fault Table
• User Stack (application dependent)
• Supervisor Stack
• Interrupt Stack
5.2.3
5.2.4
Memory Controller Initialization
Since the i960 RM/RN I/O processor Memory Controller is integral to the design and operation of
the IQ80960RM/RN platform, the operational parameters for Bank 0 and Bank 1 are established
immediately after processor core initialization. Memory Bank 0 is associated with the ROM on the
IQ80960RM/RN platform. Memory Bank 1 is associated with the UART and the LED Control
Register. Parameters such as Bank Base Address, Read Wait States, and Write Wait States must be
established to ensure the proper operation of the IQ80960RM/RN platform. The Memory
Controller is initialized so as to be consistent with the IQ80960RM/RN platform memory map
SDRAM Initialization
SDRAM initialization includes setting operational parameters for the SDRAM controller, and sizing
and clearing the installed SDRAM configuration. To configure the system properly, Presence Detect
2
data is read from the EEPROM of the SDRAM module, using the 80960RM/RN I C Bus Interface
Unit. Presence Detect data includes the number and size of SDRAM banks present on the installed
module. On power-up, 64 bytes of Presence Detect data are read and validated. The SDRAM
controller is then configured by setting the base address of SDRAM, the boundary limits for each
SDRAM bank, the refresh cycle interval, and the output buffer drive strength. Once the SDRAM
controller is configured, the SDRAM is cleared in preparation for the C language runtime
environment. The actual SDRAM size is stored for later use (e.g., to establish the size of the
IQ80960RM/RN platform PCI Slave image). The SDRAM controller is initialized to be consistent
5-2
IQ80960RM/RN Evaluation Board Manual
MON960 Support for IQ80960RM/RN
5.2.5
Primary PCI Interface Initialization
The IQ80960RM/RN platform is a multi-function PCI device. On the primary PCI bus, two
functions (from a PCI Configuration Space standpoint) are supported.
• Function 0 is the PCI-to-PCI Bridge of the i960 RM/RN I/O processor, which optionally
provides access capability between the primary PCI bus and the secondary PCI bus.
• Function 1 is the Primary ATU which provides access capability between the primary PCI bus
and the local i960 bus.
The platform can be initialized into one of four modes. Modes 0 and 3 are described below.
Table 5-1.
Initialization Modes
RST_MODE#/ RETRY/
Initialization
Mode
i960 Core
Processor
Primary PCI Interface
SW1-1
SW1-2
0/ON
0/ON
0/ON
1/OFF
0/ON
Mode 0
Mode 1
Accepts Transactions
Retries All Configuration Transactions
Accepts Transactions
Held in Reset
Held in Reset
Initializes
1/OFF
1/OFF
Mode 2
1/OFF
Mode 3 (default)
Retries All Configuration Transactions
Initializes
When the IQ80960RM/RN is operating in Mode 0, the processor core is held in reset, allowing
register defaults to be used on the Primary PCI interface. This mode is used to program the onboard
Flash with either IxWORKS* or MON960.
When the IQ80960RM/RN platform is operating in Mode 3, the Configuration Cycle Disable bit in
the Extended Bridge Control Register (EBCR) is set after IQ80960RM/RN processor reset. In this
mode, the IQ80960RM/RN platform sends PCI Retries when the PCI host attempts to access the
platform’s Configuration Space. This mode allows the IQ80960RM/RN processor time to initialize
its internal registers. The processor remains in this mode until the Configuration Cycle Disable bit
in the Extended Bridge Control Register (EBCR) is cleared. For this reason, and to prevent PCI
host problems, Primary PCI initialization occurs at the earliest possible opportunity after Memory
and SDRAM controller initialization.
5.2.6
Primary ATU Initialization
Primary ATU (Bridge) initialization includes initialization by the 80960JT core and initialization
by the PCI host processor. Local initialization occurs first and consists mainly of establishing the
operational parameters for access to the local IQ80960RM/RN platform bus. The Primary Inbound
ATU Limit Register (PIALR) is initialized to establish the block size of memory required by the
Primary ATU. The PIALR value is based on the installed SDRAM configuration. The Primary
Inbound ATU Translate Value Register (PIATVR) is initialized to establish the translation value for
PCI-to-Local accesses. The PIATVR value is set to reference the base of local SDRAM. The
Primary Outbound Memory Window Value Register (POMWVR) is initialized to establish the
translation value for Local-to-PCI accesses. The POMWVR value remains at its default value of
“0” to allow the IQ80960RM/RN platform to access the start of the PCI Memory address map,
which is typically occupied by PCI host memory. Likewise, the Primary Outbound I/O Window
Value Register (POIOWVR) remains at its default value of “0” to allow the IQ80960RM/RN
platform to access the start of the PCI I/O address map. PCI Doorbell-related parameters are also
established to allow for communication between the IQ80960RM/RN platform and a PCI bus
master using the doorbell mechanism.
IQ80960RM/RN Evaluation Board Manual
5-3
MON960 Support for IQ80960RM/RN
By default, Primary Outbound Configuration Cycle parameters are not established. The ATU
Configuration Register (ATUCR) is initialized to establish the operational parameters for the
Doorbell Unit and ATU interrupts (both primary and secondary), and to enable the primary and
secondary ATUs. The PCI host is responsible for allocating PCI address space (Memory, Memory
Mapped I/O, and I/O), and assigning the PCI Base addresses for the IQ80960RM/RN platform.
5.2.7
PCI-to-PCI Bridge Initialization
PCI-to-PCI Bridge initialization includes initialization by the 80960JT core and initialization by the
PCI host processor. Local initialization occurs first and consists mainly of establishing the operational
parameters for the secondary PCI interface of the PCI-to-PCI bridge. On the IQ80960RM/RN
platform, the secondary PCI bus is configured to consist of private devices (not visible to PCI host
configuration cycles). To support a private secondary PCI bus, the Secondary IDSEL Select Register
(SISR) is initialized to prevent the secondary PCI address bits [20:16] from being asserted during
conversion of PCI Type 1 configuration cycles on the primary PCI bus to PCI Type 0 configuration
cycles on the secondary PCI bus. Secondary PCI bus masters are prevented from initiating
transactions that will be forwarded to the primary PCI interface. The PCI host is responsible for
assigning and initializing the PCI bus numbers, allocating PCI address space (Memory, Memory
Mapped I/O, and I/O), and assigning the IRQ numbers to valid interrupt routing values.
5.2.8
Secondary ATU Initialization
Secondary ATU (Bridge) initialization consists mainly of establishing the operational parameters
for access between the local IQ80960RM/RN platform bus and the secondary PCI devices. The
Secondary Inbound ATU Base Address Register (SIABAR) is initialized to establish the PCI base
address of IQ80960RM/RN platform local memory from the secondary PCI bus. By convention,
the secondary PCI base address for access to IQ80960RM/RN platform local memory is “0”. The
Secondary Inbound ATU Limit Register (SIALR) is initialized to establish the block size of
memory required by the secondary ATU. The SIALR value is based on the installed SDRAM
configuration. The Secondary Inbound ATU Translate Value Register (SIATVR) is initialized to
establish the translation value for Secondary PCI-to-Local accesses. The SIATVR value is set to
reference the base of local SDRAM. The Secondary Outbound Memory Window Value Register
(SOMWVR) is initialized to establish the translation value for Local-to-Secondary PCI accesses.
The SOMWVR value is left at its default value of “0” to allow the IQ80960RM/RN platform to
access the start of the PCI Memory address map. Likewise, the Secondary Outbound I/O Window
Value Register (SOIOWVR) is left at its default value of “0” to allow the IQ80960RM/RN
platform to access the start of the PCI I/O address map.
On the secondary PCI bus, the IQ80960RM/RN platform assumes the duties of PCI host and, as
such, is required to configure the devices of the secondary PCI bus. Secondary Outbound
Configuration Cycle parameters are established during secondary PCI bus configuration.
Secondary PCI bus configuration is accomplished via MON960 Extension routines.
5-4
IQ80960RM/RN Evaluation Board Manual
MON960 Support for IQ80960RM/RN
5.3
MON960 Kernel
The MON960 Kernel (monitor) provides the IQ80960RM/RN user with a software platform on
which application software can be developed and run. The monitor provides several features available
to the IQ80960RM/RN user to speed application development. Among the available features are:
• Communication with a terminal or terminal emulation package on a host computer through a
serial cable with automatic baud rate detection
• Communication with a software debugger such as GDB960 (available from Intel) using the
Host Debugger Interface (HDI) software interface
• Communication with the host computer via the primary PCI bus
• Downloads of ELF object files via the primary PCI bus or via the serial console port at rates up
to 115,200 baud
• Downloads of ELF object files via the primary PCI bus
• On-board erasure and programming of Intel 28F016S5 Flash ROM
• Memory display and modification capability
• Breakpoint and single-step capability to support debugging of user code
• Disassembly of i960 processor instructions
5.4
MON960 Extensions
The monitor has been extended to include the secondary PCI bus initialization and also the BIOS
routines which are contained in the PCI BIOS Specification Revision 2.1.
5.4.1
Secondary PCI Initialization
MON960 extensions are responsible for initializing the devices on the secondary PCI bus of the
IQ80960RM/RN platform. Secondary PCI initialization involves allocating address spaces
(Memory, Memory Mapped I/O, and I/O), assigning PCI base addresses, assigning IRQ values, and
enabling PCI mastership. MON960 does not support devices containing PCI-to-PCI bridges and
hierarchical buses.
IQ80960RM/RN Evaluation Board Manual
5-5
MON960 Support for IQ80960RM/RN
5.4.2
PCI BIOS Routines
MON960 includes PCI BIOS routines to aid application software initialization of the secondary
PCI bus. The supported BIOS functions are described in the subsections that follow.
sysPCIBIOSPresent
sysFindPCIDevice
sysFINDPCIClassCode
sysGenerateSpecialCycle
sysReadConfigByte
sysReadConfigWord
sysReadConfigDword
sysWriteConfigByte
sysWriteConfigWord
sysWriteConfigDword
sysGetIrqRoutingOptions
sysSetPCIIrq
These functions preserve, as closely as possible, the parameters and return values described in the
PCI Local Bus Specification Revision 2.1. Functions that return multiple values do so by filling in
the fields of a structure passed by the calling routine.
You can access these functions via a callsinstruction. The system call indices are defined in the
MON960 source file PCI_BIOS.H. The function prototypes are defined in the IQRP_ASM.H
file.
5.4.2.1
sysPCIBIOSPresent
This function allows the caller to determine whether the PCI BIOS interface function set is present,
and the current interface version level. It also provides information about the hardware mechanism
used for accessing configuration space and whether or not the hardware supports generation of PCI
Special Cycles.
Calling convention:
int sysPCIBIOSPresent (
PCI_BIOS_INFO *info
);
Return values:
This function always returns SUCCESSFUL.
5-6
IQ80960RM/RN Evaluation Board Manual
MON960 Support for IQ80960RM/RN
5.4.2.2
sysFindPCIDevice
This function returns the location of PCI devices that have a specific Device ID and Vendor ID.
Given a Vendor ID, a Device ID, and an Index, the function returns the Bus Number, Device
Number, and Function Number of the Nth Device/Function whose Vendor ID and Device ID match
the input parameters.
Calling software can find all devices having the same Vendor ID and Device ID by making
successive calls to this function starting with the index set to “0”, and incrementing the index until
the function returns DEVICE_NOT_FOUND. A return value of BAD_VENDOR_ID indicates that
the Vendor ID value passed had a value of all “1”s.
Calling convention:
int sysFindPCIDevice (
int device_id,
int vendor_id,
int index
);
Return values:
This function returns SUCCESSFUL if the indicated device is located, DEVICE_NOT_FOUND if
the indicated device cannot be located, or BAD_VENDOR_ID if the vendor_id value is illegal.
5.4.2.3
sysFindPCIClassCode
This function returns the location of PCI devices that have a specific Class Code. Given a Class
Code and an Index, the function returns the Bus Number, Device Number, and Function Number of
the Nth Device/Function whose Class Code matches the input parameters.
Calling software can find all devices having the same Class Code by making successive calls to
this function starting with the index set to “0”, and incrementing the index until the function returns
DEVICE_NOT_FOUND.
Calling convention:
int sysFindPCIClassCode (
int
class_code,
index
int
);
Return values:
This function returns SUCCESSFUL when the indicated device is located, or
DEVICE_NOT_FOUND when the indicated device cannot be located.
IQ80960RM/RN Evaluation Board Manual
5-7
MON960 Support for IQ80960RM/RN
5.4.2.4
sysGenerateSpecialCycle
This function allows for generation of PCI Special Cycles. The generated special cycle is broadcast
on a specific PCI Bus in the system.
PCI Special Cycles are not supported on the IQ80960RM/RN platform secondary PCI bus.
Calling convention:
int sysGenerateSpecialCycle (
int bus_number,
int special_cycle_data
);
Return values:
Since PCI Special Cycles are not supported by the IQ80960RM/RN platform, this function always
returns FUNC_NOT_SUPPORTED.
5.4.2.5
sysReadConfigByte
This function allows the caller to read individual bytes from the configuration space of a specific
device.
Calling convention:
int sysReadConfigByte (
int
bus_number,
device_number,
function_number,
register_number,
*data
int
int
int
UINT8
/* 0,1,2,...,255 */
);
Return values:
This function returns SUCCESSFUL when the indicated byte was read correctly, or ERROR when
there is a problem with the parameters.
5-8
IQ80960RM/RN Evaluation Board Manual
MON960 Support for IQ80960RM/RN
5.4.2.6
sysReadConfigWord
This function allows the caller to read individual shorts (16 bits) from the configuration space of a
specific device. The Register Number parameter must be a multiple of two (i.e., bit 0 must be set to “0”).
Calling convention:
int sysReadConfigWord (
int
bus_number,
device_number,
function_number,
register_number,
*data
int
int
int
/* 0,2,4,...,254 */
UINT16
);
Return values:
This function returns SUCCESSFUL when the indicated word was read correctly, or ERROR when
there is a problem with the parameters.
5.4.2.7
sysReadConfigDword
This function allows the caller to read individual longs (32 bits) from the configuration space of a
specific device. The Register Number parameter must be a multiple of four (i.e., bits 0 and 1 must
be set to “0”).
Calling convention:
int sysReadConfigDword (
int
int
int
int
bus_number,
device_number,
function_number,
register_number,
/* 0,4,8,...,252 */
UINT32 *data
);
Return values:
This function returns SUCCESSFUL when the indicated long was read correctly, or ERROR when
there is a problem with the parameters.
IQ80960RM/RN Evaluation Board Manual
5-9
MON960 Support for IQ80960RM/RN
5.4.2.8
sysWriteConfigByte
This function allows the caller to write individual bytes to the configuration space of a specific device.
Calling convention:
int sysWriteConfigByte (
int
bus_number,
device_number,
function_number,
register_number,
*data
int
int
int
UINT8
/* 0,1,2,...,255 */
);
Return values:
This function returns SUCCESSFUL when the indicated byte was written correctly, or ERROR
when there is a problem with the parameters.
5.4.2.9
sysWriteConfigWord
This function allows the caller to write individual shorts (16 bits) to the configuration space of a specific
device. The Register Number parameter must be a multiple of two (i.e., bit 0 must be set to “0”).
Calling convention:
int sysWriteConfigWord (
int
bus_number,
device_number,
function_number,
register_number,
*data
int
int
int
/* 0,2,4,...,254 */
UINT16
);
Return values:
This function returns SUCCESSFUL when the indicated word was written correctly, or ERROR
when there is a problem with the parameters.
5-10
IQ80960RM/RN Evaluation Board Manual
MON960 Support for IQ80960RM/RN
5.4.2.10
sysWriteConfigDword
This function allows the caller to write individual longs (32 bits) to the configuration space of a
specific device. The Register Number parameter must be a multiple of four (i.e., bits 0 and 1 must
be set to “0”).
Calling convention:
int sysWriteConfigDword (
int
bus_number,
device_number,
function_number,
register_number,
*data
int
int
int
/* 0,4,8,...,252 */
UINT32
);
Return values:
This function returns SUCCESSFUL when the indicated long was written correctly, or ERROR
when there is a problem with the parameters.
5.4.2.11
sysGetIrqRoutingOptions
The PCI Interrupt routing fabric on the IQ80960RM/RN platform is not reconfigurable (fixed
mapping relationships); therefore, this function is not supported.
Calling convention:
int sysGetIrqRoutingOptions (
PCI_IRQ_ROUTING_TABLE *table
);
Return values:
This function always returns FUNC_NOT_SUPPORTED.
IQ80960RM/RN Evaluation Board Manual
5-11
MON960 Support for IQ80960RM/RN
5.4.2.12
sysSetPCIIrq
The PCI Interrupt routing fabric on the IQ80960RM/RN platform is not reconfigurable (fixed
mapping relationships); therefore, this function is not supported.
Calling convention:
int sysSetPCIIrq (
int
int
int
);
int_pin,
irq_num,
bus_dev
Return values:
This function always returns FUNC_NOT_SUPPORTED.
5.4.3
Additional MON960 Commands
The following commands have been added to the UI interface of MON960 to support the
IQ80960RM/RN platform.
5.4.3.1
print_pci Utility
A print_pci command to MON960 is accessed through the MON960 command prompt. This command
displays the contents of the PCI configuration space on a selected adapter on the secondary PCI interface or
on the i960 RM/RN I/O processor itself. For more information on the meaning of the fields in PCI
configuration space, refer to the PCI Local Bus Specification Revision 2.1. The syntax of this command is:
pp <bus number> <device number> <function number>
5.5
Diagnostics / Example Code
IQ80960RM/RN platform diagnostic routines serve a twofold purpose: to verify proper hardware operation
and to provide example code for users who need similar functions in their applications. Diagnostic routines
fall into two categories: board level diagnostics and PCI expansion module diagnostics.
5.5.1
Board Level Diagnostics
Board level diagnostics exercise all basic areas of the IQ80960RM/RN platform. Diagnostic routines
include SDRAM tests, UART tests, LED tests, internal timer tests, I2C bus tests, and primary PCI bus tests.
Primary PCI bus tests exercise the primary ATU, the PCI Doorbell unit, and the PCI DMA controller.
Interrupts from both local and PCI sources are generated and handled. The PCI bus tests require an external
test suite running on a PC to verify complete functionality of the IQ80960RM/RN platform.
5.5.2
Secondary PCI Diagnostics
Secondary PCI diagnostics exercise the secondary PCI bus, thereby confirming hardware
functionality, as well as illustrating the use of the PCI BIOS routines present in MON960.
5-12
IQ80960RM/RN Evaluation Board Manual
Bill of Materials
A
8
Table A-1. IQ80960RN Bill of Materials (Sheet 1 of 4)
Item Qty
Location
U13
Part Description
Manufacturer
Manufacturer Part #
National
Semiconductor
1
2
3
4
5
6
7
1
1
1
2
1
1
1
IC/SM 74ALS32 SOIC-14
DM74ALS32M
National
Semiconductor
U6
IC/SM 74ALS04 SOIC
IC/SM 74ABT273 SOIC
IC/SM 74ABT573 SOIC
IC/SM 74ALS08 SOIC
IC / SM 1488A SOIC
IC / SM 1489A SOIC
DM74ALS04BM
SN74ABT273DW
SN74ABT573DW
DM74ALS08M
DS1488M
Texas
Instruments
U3
Texas
Instruments
U1,U2
U16
U5
National
Semiconductor
National
Semiconductor
National
Semiconductor
U7
DS1489AM
8
9
1
1
Q1
U9
IC/SM Si9430DY SOIC-8
Siliconix
Motorola
Si9430DY
MPC9140
IC/SM LVCMOS Fanout Buffr SSOP
National
Semiconductor
10
1
U10
IC/SM LM339 SOIC-14
LM339M
11
12
13
14
1
1
1
1
U8
IC/SM MAX1651CSA SOIC-8
IC/SM MAX712CSE SOIC-16
IC/SM MAX767CAP SOIC
Maxim
Maxim
Maxim
Intel
MAX1651CSA
MAX712CSE
MAX767CAP
U14
U17
U15
PROCESSOR (from Intel) 80960RN
Texas
Instruments
15
16
1
1
U12
C65
VLSI I/O UART 16C550 PLCC
TL16C550AFN
CAP SM, 0.47 µF (1206) Philips
Philips
12062F474Z9BB0
C2, C3,
C10, C11,
C18, C19,
C26, C27,
C55, C58,
C61, C68,
C77, C83,
C96
17
15
CAP SM, 0.01 µF (0805)
Kemet
C0805C103K5RAC
IQ80960RM/RN Evaluation Board Manual
A-1
Bill of Materials
Table A-1. IQ80960RN Bill of Materials (Sheet 2 of 4)
Item Qty
Location
Part Description
Manufacturer
Manufacturer Part #
C1, C4, C5,
C6, C7, C8,
C9, C12,
C13, C14,
C15, C16,
C17, C20,
C21, C22,
C23, C24,
C25, C28,
C29, C30,
C31, C32,
C33, C34,
C35, C36,
C37, C38,
C39, C40,
C41, C42,
C43, C44,
C45, C46,
C48, C49,
C50, C51,
C53, C59,
C62, C66,
C67, C69,
C70, C71,
C73, C79,
C80, C81,
C85, C86,
C87, C94,
C95, C97,
C98, C99,
C100,C101,
C102,C103,
C104,C105,
C106,C107,
C108,C109,
C111, C112,
C113, C115,
C116, C114,
C117, C120,
C121
18
81
CAP SM, 0.1 µF (0805)
Philips
08052R104K8BB2
19
20
21
1
2
1
C110
CAP SM, 18 pF (0805)
Kemet
Dale
C0805C180J5GAC
CRCW0805100JT
CRCW08051000JT
R27, R28
R60
R/SM 1/10 W 5% 1 ohm (0805)
R/SM 1/10 W 5% 10 ohm (0805)
Dale
R25, R61,
R62
22
23
3
4
R/SM 1/10 W 5% 1 Kohm (0805)
R/SM 1/10 W 5% 10 Kohm (0805)
Dale
Dale
CRCW08051001FRT
CRCW08051002FRT
R35, R39,
R58, R59
24
25
2
1
R24, R32
R20
R/SM 1/10 W 5% 100 Kohm (0805)
R/SM 1/10 W 1% 150 ohm (0805)
Dale
Dale
CRCW08051003FRT
CRCW08051500FRT
R14, R41,
R42
26
3
R/SM 1/10 W 5% 1.5 Kohm (0805)
Dale
CRCW0805152JT
27
28
29
30
1
2
1
1
R18
R/SM 1/10 W 5% 1.6 Kohm (0805)
R/SM 1/10 W 5% 22 ohm (0805)
R/SM 1/10 W 5% 22 Kohm (0805)
R/SM 1/10 W 5% 24 ohm (0805)
Dale
Dale
Dale
Dale
CRCW0805162JT
CRCW0805220JT
CRCW0805223JT
CRCW0805240JT
R50, R51
R34
R37
A-2
IQ80960RM/RN Evaluation Board Manual
Bill of Materials
Table A-1. IQ80960RN Bill of Materials (Sheet 3 of 4)
Item Qty
Location
R47
Part Description
Manufacturer
Manufacturer Part #
31
32
33
34
35
36
37
38
1
2
1
1
1
2
1
1
R/SM 1/10 W 5% 2.4 Kohm (0805)
R/SM 1/10 W 5% 2.7 Kohm (0805)
R/SM 1/10 W 5% 330 ohm (0805)
R/SM 1/10 W 5% 36 ohm (0805)
R/SM 1/10 W 5% 470 ohm (0805)
R/SM 1/10 W 1% 4.7 Kohm (0805)
R/SM 1/10 W 5% 47 Kohm (0805)
R/SM 1/10 W 5% 68 Kohm (0805)
Dale
Dale
Dale
Dale
Dale
Dale
Dale
Dale
CRCW0805242JT
CRCW0805272JT
CRCW0805331JT
CRCW0805360JT
CRCW 0805 471JT
CRCW08054701FRT
CRCW0805473JT
CRCW0805683JT
R2, R57
R19
R29
R17
R48, R49
R53
R26
R30, R43,
R54, R56
39
40
41
4
5
4
R/SM 1/8 W 5% 10 ohm chip 1206
CONN SM/TH Mictor 43P Recptcl
CONN PCI 64BIT 5 V/PCB ThruHole
Dale
AMP
AMP
CRCW1206100FT
767054-1
J8, J9, J10,
J11, J12
J1, J2, J3,
J4
145166-4
42
43
44
45
1
1
1
1
J5
CONN DIMM 168P/RAng/Socket/TH
CONN TJ6 PCB 6/6 LP thru hole
CONN/FAN ASSY/Socket/ThruHole
CONN Hdr 16 pin/w shell, pcb
Molex
KYCON
AMP
73790-0059
GM-N-66
J7
J13
J6
173981-03
103308-3
AMP
Z1, Z2, Z3,
Z4
46
4
Jumper JUMP2X1
Molex
22-54-1402
47
48
49
50
51
1
1
1
1
1
L1
Inductor/SM 47µH 20%
Coilcraft
Coilcraft
Mors
D03340P-473
D03316P-332
DHS-4S
L2
Inductor/SM 3.3 µH 20%
S1
U4
U18
Switch/SM DIP4 Mors# DHS-4S
OSC 1.8432 MHz 1/2 - Thru hole
Clock Chip CY7B9910-7SC
Kyocera
Cypress
KH0HC1CSE 1.843
CY7B9910-7SC
Hewlett
Packard
52
53
54
1
1
1
CR5
CR3
CR4
LED Green
LED-Red
HLMP-3507$010
HLMP3301$010
HLMP4740#010
Hewlett
Packard
Hewlett
Packard
LED Green LP
55
56
57
58
2
2
1
1
CR1, CR2
Q2, Q3
Q4
LED-Red-Small Group
Dialight
Harris
555-4001
Transistor/SM N-Channel
RFD16N05LSM
2N6109
Transistor 2N6109 (Thru Hole)
SOCKET PLCC20 LP Surface Mount
Motorola
AMP
U19
822269-1
BT1, BT2,
BT3, BT4,
BT5, BT6,
BT7, BT8
60
8
Battery Clips/PC/Snap-In/AA
Keystone
#92
61
62
1
1
U19
U11
PALLV16V8Z-20JI
AMD
Intel
PALLV16V8Z-20JI
E28F016S5-090
MEM Flash E28F016S5-090 TSOP
IQ80960RM/RN Evaluation Board Manual
A-3
Bill of Materials
Table A-1. IQ80960RN Bill of Materials (Sheet 4 of 4)
Item Qty
Location
Part Description
Manufacturer
Manufacturer Part #
BT1, BT2,
BT3, BT4,
BT5, BT6,
BT7, BT8
63
8
Battery AA NiCd @ 600 mA/Hour
SAFT
NIC-AA-600-SAFT
64
65
1
1
U15
C84
HeatSink/Fan Assy 80960RM/RN
Panasonic
Philips
UDQFNBEOIF
CAP SM, 0.22 µF (1206)
12062E224M9BB2
C60, C75,
C78
66
3
CAP TANT SM 220 µF, 10 V (7343)
AVX
TPSE227K010R010
C89, C90,
C91, C93
67
68
69
4
1
4
CAP TANT SM 47 µF, 16 V (7343)
CAP TANT SM 33 µF, 10 V (7343)
CAP TANT SM 4.7 µF, 35 V (7343)
AVX
TPSD476K016R015
293D336X9016D2T
293D475X9035D2T
C63
Sprague
Sprague
C57, C76,
C88, C92
70
71
72
73
74
1
1
2
1
1
C47
CAP TANT SM 22 µF, 20 V (7343)
CAP TANT SM 1 µF, 16 V (3216)
CAP TANT SM 10 µF, 25/35 V
Sprague
Sprague
Sprague
AVX
293D226X9020D2T
293D105X0016A2T
293D1060025D2T
C74
C52, C54
C56
CAP TANT SM 100 µF 10 V (7343)
CAP TANT SM 330 µF 6.3 V (7343
TPSD107K010R0100
TPSE337K063R0100
C64
AVX
C82, C118,
C119
75
3
CAP SM, 0.047 µF (0805)
Kemet
C0805C473K5RAC
76
77
78
1
1
1
R46
R21
R52
Res/SM 1 W 1% 0.012 ohm (2512)
Res/SM 1 W 1% 0.05 ohm (2512)
Resistor/SM 1/2 W 5% 100 ohm
Dale
WSL-2512-R012
WSL-2512-R050
BCR 1/2 101 JT
Dale
Beckmen
R1, R3, R4,
R5, R6, R7,
R8, R9,
79
16
R10, R11,
R12, R33,
R36, R38,
R44, R45,
Resistor Pk SM RNC4R8P 2.7 Kohm
CTS
742083272JTR
80
81
82
83
2
2
1
2
R40, R55
R15, R16
R13
Resistor Pk SM RNC4R8P 22 ohm
Resistor Pk SM RNC4R8P 470 ohm
Resistor Pk SM RNC4R8P 1.5 Kohm
Resistor Pk SM RNC4R8P 30 ohm
CTS
CTS
CTS
CTS
742083220JTR
742083471JTR
742083152JTR
742083300JTR
R22, R23
Central
Semiconductor
84
85
86
87
88
1
2
1
1
2
CR9
Diode CMPSH3 Surface Mount
Diode SM / MBRS340T3
CMPSH3
CR6, CR7
CR8
Motorola
MBRS340T3
CMR1-02
Central
Semiconductor
Diode/SM 1N4001 (CMR1-02)
SDRAM, DIMM, ECC, 2Mx72, 16 MB
IC/SM TL7702BCD
J5
Unigen
UG52S7408GSG
TL7702BCD
Texas
Instruments
U20, U21
A-4
IQ80960RM/RN Evaluation Board Manual
Bill of Materials
Table A-2. IQ80960RM Bill of Materials (Sheet 1 of 5)
Item Qty
Location
U13
Part Description
Manufacturer
Manufacturer Part #
National
Semiconductor
1
2
3
4
5
6
7
1
1
1
2
1
1
1
IC/SM 74ALS32 SOIC-14
DM74ALS32M
National
Semiconductor
U6
IC/SM 74ALS04 SOIC
IC/SM 74ABT273 SOIC
IC/SM 74ABT573 SOIC
IC/SM 74ALS08 SOIC
IC / SM 1488A SOIC
IC / SM 1489A SOIC
DM74ALS04BM
SN74ABT273DW
SN74ABT573DW
DM74ALS08M
DS1488M
Texas
Instruments
U3
Texas
Instruments
U1, U2
U16
U5
National
Semiconductor
National
Semiconductor
National
Semiconductor
U7
DS1489AM
8
9
1
1
Q1
U9
IC/SM Si9430DY SOIC-8
Siliconix
Motorola
Si9430DY
MPC9140
IC/SM LVCMOS Fanout Buffr SSOP
National
Semiconductor
10
1
U10
IC/SM LM339 SOIC-14
LM339M
11
12
13
14
1
1
1
1
U8
IC/SM MAX1651CSA SOIC-8
IC/SM MAX712CSE SOIC-16
IC/SM MAX767CAP SOIC
Maxim
Maxim
Maxim
Intel
MAX1651CSA
MAX712CSE
MAX767CAP
U14
U17
U15
PROCESSOR (frm Intel) i960RM
Texas
Instruments
15
16
1
1
U12
C65
VLSI I/O UART 16C550 PLCC
TL16C550AFN
CAP SM, 0.47 µF (1206) Philips
Philips
12062F474Z9BB0
C2, C3,
C10, C11,
C18, C19,
C26, C27,
C55, C58,
C61, C68,
C77, C83,
C96
17
15
CAP SM, 0.01 µF (0805)
Kemet
C0805C103K5RAC
IQ80960RM/RN Evaluation Board Manual
A-5
Bill of Materials
Table A-2. IQ80960RM Bill of Materials (Sheet 2 of 5)
Item Qty
Location
Part Description
Manufacturer
Manufacturer Part #
C1, C4, C5,
C6, C7, C8,
C9, C12,
C13, C14,
C15, C16,
C17, C20,
C21, C22,
C23, C24,
C25, C28,
C29, C30,
C31, C32,
C33, C34,
C35, C36,
C37, C38,
C39, C40,
C41, C42,
C43, C44,
C45, C46,
C48, C49,
C50, C51,
C53, C59,
C62, C66,
C67, C69,
C70, C71,
C73, C79,
C80, C81,
C85, C86,
C87, C94,
C95, C97,
C98, C99,
C100,C101,
C102,C103,
C104,C105,
C106,C107,
C108,C109,
C111, C112,
C113, C114,
C115, C116,
C117, C120,
C121
18
81
CAP SM, 0.1 µF (0805)
Philips
08052R104K8BB2
19
20
21
1
2
1
C110
CAP SM, 18 pF(0805)
Kemet
Dale
C0805C180J5GAC
CRCW0805100JT
CRCW08051000JT
R27, R28
R60
R/SM 1/10 W 5% 1 ohm (0805)
R/SM 1/10 W 5% 10 ohm (0805)
Dale
R25, R61,
R62
22
3
R/SM 1/10 W 5% 1 Kohm (0805)
Dale
Dale
CRCW08051001FRT
R5, R6, R7
R8, R9,
R10, R11,
R12, R35,
R39, R58,
R59
23
12
R/SM 1/10 W 5% 10 Kohm (0805)
CRCW08051002FRT
24
25
2
1
R24, R32
R20
R/SM 1/10 W 5% 100 Kohm (0805)
R/SM 1/10 W 1% 150 ohm (0805)
Dale
Dale
CRCW08051003FRT
CRCW08051500FRT
R14, R41,
R42
26
27
3
1
R/SM 1/10 W 5% 1.5 Kohm (0805)
R/SM 1/10 W 5% 1.6 Kohm (0805)
Dale
Dale
CRCW0805152JT
CRCW0805162JT
R18
A-6
IQ80960RM/RN Evaluation Board Manual
Bill of Materials
Table A-2. IQ80960RM Bill of Materials (Sheet 3 of 5)
Item Qty
Location
Part Description
Manufacturer
Manufacturer Part #
28
29
30
31
32
33
34
35
36
37
38
2
1
1
1
1
1
1
1
2
1
1
R50, R51
R34
R/SM 1/10 W 5% 22 ohm (0805)
R/SM 1/10 W 5% 22 Kohm (0805)
R/SM 1/10 W 5% 24 ohm (0805)
R/SM 1/10 W 5% 2.4 Kohm (0805)
R/SM 1/10 W 5% 2.7 Kohm (0805)
R/SM 1/10 W 5% 330 ohm (0805)
R/SM 1/10 W 5% 36 ohm (0805)
R/SM 1/10 W 5% 470 ohm (0805)
R/SM 1/10 W 1% 4.7 Kohm (0805)
R/SM 1/10 W 5% 47 Kohm (0805)
R/SM 1/10 W 5% 68 Kohm (0805)
Dale
Dale
Dale
Dale
Dale
Dale
Dale
Dale
Dale
Dale
Dale
CRCW0805220JT
CRCW0805223JT
CRCW0805240JT
CRCW0805242JT
CRCW0805272JT
CRCW0805331JT
CRCW0805360JT
CRCW 0805 471JT
CRCW08054701FRT
CRCW0805473JT
CRCW0805683JT
R37
R47
R57
R19
R29
R17
R48, R49
R53
R26
R30, R43,
R54, R56
39
40
41
4
5
4
R/SM 1/8 W 5% 10 ohm chip 1206
CONN SM/TH Mictor 43P Recptcl
CONN PCI Slot 5V/PCB ThruHole
Dale
AMP
AMP
CRCW1206100FT
767054-1
J8, J9, J10,
J11, J12
J1, J2, J3,
J4
145154-4
42
43
44
45
1
1
1
1
J5
CONN DIMM 168P/RAng/Socket/TH
CONN TJ6 PCB 6/6 LP thru hole
CONN/FAN ASSY/Socket/ThruHole
CONN Hdr 16 pin/w shell, pcb
Molex
KYCON
AMP
73790-0059
GM-N-66
J7
J13
J6
173981-03
103308-3
AMP
Z1, Z2, Z3,
Z4
46
4
Jumper JUMP2X1
Molex
22-54-1402
47
48
49
50
51
1
1
1
1
1
L1
Inductor/SM 47 µH 20%
Coilcraft
Coilcraft
Mors
D03340P-473
D03316P-332
DHS-4S
L2
Inductor/SM 3.3 µH 20%
S1
U4
U18
Switch/SM DIP4 Mors# DHS-4S
OSC 1.8432 MHz 1/2 - Thru hole
Clock Chip CY7B9910-7SC
Kyocera
Cypress
KH0HC1CSE 1.843
CY7B9910-7SC
Hewlett
Packard
52
53
54
1
1
1
CR5
CR3
CR4
LED Green
LED-Red
HLMP-3507$010
HLMP3301$010
HLMP4740#010
Hewlett
Packard
Hewlett
Packard
LED Green LP
55
56
57
58
60
2
2
1
1
1
CR1, CR2
Q2, Q3
Q4
LED-Red-Small Group
Dialight
Harris
555-4001
Transistor/SM N-Channel
RFD16N05LSM
2N6109
Transistor 2N6109 (Thru Hole)
SOCKET PLCC20 LP Surface Mount
SOCKET / SM / TSOP / 40 pin
Motorola
AMP
U19
822269-1
U11
Meritec
980020-40-02
IQ80960RM/RN Evaluation Board Manual
A-7
Bill of Materials
Table A-2. IQ80960RM Bill of Materials (Sheet 4 of 5)
Item Qty
Location
Part Description
Manufacturer
Manufacturer Part #
BT1, BT2,
BT3, BT4,
BT5, BT6,
BT7, BT8
61
8
Battery Clips/PC/Snap-In/AA
Keystone
#92
62
63
1
1
U19
U11
PALLV16V8Z-20JI
AMD
Intel
PALLV16V8Z-20JI
E28F016S5-090
MEM Flash E28F016S5-090 TSOP
BT1, BT2,
BT3, BT4,
BT5, BT6,
BT7, BT8
64
8
Battery AA NiCd @ 600 mA/Hour
SAFT
NIC-AA-600-SAFT
65
66
1
3
U15
C84
HeatSink/Fan Assy 80960RN/RM
Panasonic
Philips
UDQFNBEOIF
CAP SM, 0.22 µF (1206)
12062E224M9BB2
C60, C75,
C78
67
3
CAP TANT SM 220 µF, 10 V (7343)
AVX
TPSE227K010R010
C89, C90,
C91, C93
68
69
70
4
1
4
CAP TANT SM 47 µF, 16 V (7343)
CAP TANT SM 33 µF, 10 V (7343)
CAP TANT SM 4.7 µF, 35 V (7343)
AVX
TPSD476K016R015
293D336X9016D2T
293D475X9035D2T
C63
Sprague
Sprague
C57, C76,
C88, C92
71
72
73
74
75
1
1
2
1
1
C47
CAP TANT SM 22 µF, 20 V (7343)
CAP TANT SM 1 µF, 16 V (3216)
CAP TANT SM 10 µF, 25/35 V
Sprague
Sprague
Sprague
AVX
293D226X9020D2T
293D105X0016A2T
293D1060025D2T
C74
C52, C54
C56
CAP TANT SM 100 µF 10 V (7343)
CAP TANT SM 330 µF 6.3 V (7343)
TPSD107K010R0100
TPSE337K063R0100
C64
AVX
C82, C118,
C119
76
3
CAP SM, 0.047 µF (0805)
Kemet
C0805C473K5RAC
77
78
79
1
1
1
R46
R21
R52
Res/SM 1 W 1% 0.012 ohm (2512)
Res/SM 1 W 1% 0.05 ohm (2512)
Resistor/SM 1/2 W 5% 100 ohm
Dale
WSL-2512-R012
WSL-2512-R050
BCR 1/2 101 JT
Dale
Beckmen
R1, R31,
R33, R36,
R38, R44,
R45
80
7
Resistor Pk SM RNC4R8P 2.7 Kohm
CTS
742083272JTR
81
82
83
84
2
2
1
2
R40, R55
R15, R16
R13
Resistor Pk SM RNC4R8P 22 ohm
Resistor Pk SM RNC4R8P 470 ohm
Resistor Pk SM RNC4R8P 1.5 Kohm
Resistor Pk SM RNC4R8P 30 ohm
CTS
CTS
CTS
CTS
742083220JTR
742083471JTR
742083152JTR
742083300JTR
R22, R23
Central
Semiconductor
85
86
87
88
1
2
1
1
CR9
Diode CMPSH3 Surface Mount
Diode SM / MBRS340T3
CMPSH3
CR6, CR7
CR8
Motorola
MBRS340T3
CMR1-02
Central
Semiconductor
Diode/SM 1N4001 (CMR1-02)
SDRAM, DIMM, ECC, 2Mx72, 16 MB
J5
Unigen
UG52S7408GSG
A-8
IQ80960RM/RN Evaluation Board Manual
Bill of Materials
Table A-2. IQ80960RM Bill of Materials (Sheet 5 of 5)
Item Qty
89
Location
Part Description
IC/SM TL7702BCD
Manufacturer
Manufacturer Part #
Texas
Instruments
2
U20, U21
TL7702BCD
IQ80960RM/RN Evaluation Board Manual
A-9
Bill of Materials
A-10
IQ80960RM/RN Evaluation Board Manual
Schematics
B
Table B-1. IQ80960RN Schematics List
Page
Schematic Title
B-2
B-3
Decoupling and 3.3V Power
Primary PCI Interface
Memory Controller
B-4
B-5
Flash ROM, UART, & LEDs
Logic Analyzer I/F
B-6
B-7
SDRAM 168-Pin DIMM
Secondary PCI/960 Core
Secondary PCI Bus 1/2
Secondary PCI Bus 3/4
SPCI Pull-ups
B-8
B-9
B-10
B-11
B-12
Battery/Monitor
IQ80960RM/RN Evaluation Board Manual
B-1
2 2 0 u F
C A P T 7 3 4 3
2
2
1
C 7 8
2 2 0 u F
C A P T 7 3 4 3
1
C 7 5
1
C O I L - S M T 2
3 . 3 u H
L 2
C 8 6
1
2
2
1
C A P 0 8 0 5
0 . 1 u F
R 5 4
1
2
1 / 8 W 5 %
1 0
R 3 9
1
2
1 / 1 0 W 5 %
1 0 K
C 8 9
2
2
1
C A P T 7 3 4 3
4 7 u F
C 9 4
1
R 5 8
1
2
1 / 1 0 W 5 %
C A P 0 8 0 5
0 . 1 u F
1 0 K
C 9 5
2
1
C A P 0 8 0 5
0 . 1 u F
C 1 0 4
P _ A D 3 2
P _ A D 3 3
P _ A D 3 4
P _ A D 3 5
P _ A D 3 6
P _ A D 3 7
P _ A D 3 8
P _ A D 3 9
P _ A D 4 0
P _ A D 4 1
P _ A D 4 2
P _ A D 4 3
P _ A D 4 4
P _ A D 4 5
P _ A D 4 6
P _ A D 4 7
P _ A D 4 8
P _ A D 4 9
P _ A D 5 0
P _ A D 5 1
P _ A D 5 2
P _ A D 5 3
P _ A D 5 4
P _ A D 5 5
P _ A D 5 6
P _ A D 5 7
P _ A D 5 8
P _ A D 5 9
P _ A D 6 0
P _ A D 6 1
P _ A D 6 2
P _ A D 6 3
P _ A D 0
U 1
P A D 3 2 A G 2
P A D 3 3 A G 3
P A D 3 4 A F 1
P A D 3 5 A F 3
P A D 3 6 A F 4
P A D 3 7 A F 5
P A D 3 8 A E 1
P A D 3 9 A E 2
P A D 4 0 A E 3
P A D 4 1 A E 5
P A D 4 2 A D 1
P A D 4 3 A D 3
P A D 4 4 A D 4
P A D 4 5 A D 5
P A D 4 6 A C 1
P A D 4 7 A C 2
P A D 4 8 A C 3
P A D 4 9 A C 5
P A D 5 0 A B 1
P A D 5 1 A B 3
P A D 5 2 A B 4
P A D 5 3 A B 5
P A D 5 4 A A 1
P A D 5 5 A A 2
P A D 5 6 A A 3
P A D 5 7 A A 5
P A D 5 8 Y 1
P A D 0
P _ A D 1
2
2
2
2
2
2
1
U 2
P A D 1
C A P 0 8 0 5
0 . 1 u F
C 1 0 2
P _ A D 2
U 3
P A D 2
P _ A D 3
T 1
P A D 3
P _ A D 4
T 3
P A D 4
1
P _ A D 5
T 4
P A D 5
C A P 0 8 0 5
0 . 1 u F
C 1 0 1
P _ A D 6
T 5
P A D 6
P _ A D 7
R 1
P A D 7
1
P _ A D 8
R 3
P A D 8
C A P 0 8 0 5
0 . 1 u F
C 1 0 0
P _ A D 9
R 5
P A D 9
P _ A D 1 0
P 1
P A D 1 0
P A D 1 1
P A D 1 2
P A D 1 3
P A D 1 4
P A D 1 5
P A D 1 6
P A D 1 7
P A D 1 8
P A D 1 9
P A D 2 0
P A D 2 1
P A D 2 2
P A D 2 3
P A D 2 4
P A D 2 5
P A D 2 6
P A D 2 7
P A D 2 8
P A D 2 9
P A D 3 0
P A D 3 1
P _ A D 1 1
1
P 3
C A P 0 8 0 5
0 . 1 u F
C 9 8
P _ A D 1 2
P 4
P _ A D 1 3
P 5
P _ A D 1 4
N 1
1
P _ A D 1 5
N 2
C A P 0 8 0 5
0 . 1 u F
C 9 7
P _ A D 1 6
K 3
P _ A D 1 7
K 4
1
P _ A D 1 8
K 5
C A P 0 8 0 5
0 . 1 u F
P _ A D 1 9
J 1
P _ A D 2 0
J 2
P _ A D 2 1
J 3
P _ A D 2 2
J 5
P _ A D 2 3
H 1
P _ A D 2 4
H 5
P _ A D 2 5
G 1
P _ A D 2 6
G 2
P _ A D 2 7
P A D 5 9 Y 3
G 3
P _ A D 2 8
E 5
P A D 6 0 Y 4
P _ A D 2 9
P A D 6 1 Y 5
A 6
P _ A D 3 0
C 6
P A D 6 2 W 1
P A D 6 3 W 2
P _ A D 3 1
D 6
R 5 7
1
2
1 / 1 0 W 5 %
2 . 7 K
R 4 1
1
2
1 / 1 0 W 5 %
1 . 5 K
R 4 2
1
2
1 / 1 0 W 5 %
1 . 5 K
1
D Q 3 2
D Q 3 3
D Q 3 4
D Q 3 5
D Q 3 6
D Q 3 7
D Q 3 8
D Q 3 9
D Q 4 0
D Q 4 1
D Q 4 2
D Q 4 3
D Q 4 4
D Q 4 5
D Q 4 6
D Q 4 7
D Q 4 8
D Q 4 9
D Q 5 0
D Q 5 1
D Q 5 2
D Q 5 3
D Q 5 4
D Q 5 5
D Q 5 6
D Q 5 7
D Q 5 8
D Q 5 9
D Q 6 0
D Q 6 1
D Q 6 2
D Q 6 3
D Q 0
D Q 1
D Q 3 2
E 2 2
D 2 2
D Q 0
D Q 1
D Q 3 3
D Q 3 4
D Q 3 5
D Q 3 6
D Q 3 7
D Q 3 8
D Q 3 9
D Q 4 0
D Q 4 1
D Q 4 2
D Q 4 3
D Q 4 4
D Q 4 5
D Q 4 6
D Q 4 7
D Q 4 8
D Q 4 9
D Q 5 0
D Q 5 1
D Q 5 2
D Q 5 3
D Q 5 4
D Q 5 5
D Q 5 6
D Q 5 7
D Q 5 8
D Q 5 9
D Q 6 0
D Q 6 1
D Q 6 2
D Q 6 3
B 2 3
A 2 3
D Q 2
C 2 3
E 2 3
D Q 2
D Q 3
C 2 4
A 2 4
D Q 3
D Q 4
D 2 4
E 2 4
D Q 4
D Q 5
B 2 5
A 2 5
D Q 5
D Q 6
C 2 5
E 2 5
D Q 6
D Q 7
C 2 6
A 2 6
D Q 7
D Q 8
E 2 6
A 2 7
D Q 8
D Q 9
C 2 7
B 2 7
D Q 9
D Q 1 0
E 2 7
A 2 8
D Q 1 0
D Q 1 1
D Q 1 2
D Q 1 3
D Q 1 4
D Q 1 5
D Q 1 6
D Q 1 7
D Q 1 8
A A 3 2 D Q 1 9
D Q 1 1
G 3 2
H 3 1
C 2 8
D Q 1 2
H 3 2
D Q 1 3
H 2 8
H 3 0
D Q 1 4
J 3 2
J 3 0
D Q 1 5
J 2 8
J 2 9
D Q 1 6
W 2 9
W 2 8
Y 3 1
D Q 1 7
Y 3 2
D Q 1 8
Y 3 0
Y 2 8
D Q 1 9
D Q 2 0
D Q 2 1
D Q 2 2
D Q 2 3
D Q 2 4
D Q 2 5
D Q 2 6
D Q 2 7
D Q 2 8
D Q 2 9
D Q 3 0
D Q 3 1
A A 3 0
A A 2 8
A B 3 1
A B 2 8
A C 3 0
A C 2 8
A D 3 1
A D 2 8
A E 3 0
A E 2 8
A F 3 1
A F 2 8
A H 3 2
A A 2 9
A B 3 2
A B 3 0
D Q 2 0
D Q 2 1
D Q 2 2
A C 3 2 D Q 2 3
A C 2 9 D Q 2 4
A D 3 2 D Q 2 5
A D 3 0 D Q 2 6
A E 3 2
A E 2 9
A F 3 2
A F 3 0
D Q 2 7
D Q 2 8
D Q 2 9
D Q 3 0
A G 3 2 D Q 3 1
C 1 1 0
2
1
C A P 0 8 0 5
1 8 p F
9
1 2
C R 1
4 7 0
R 1 5
2
4
6
8
1
L E D 0
L E D 1
L E D 2
L E D 3
L E D 4 S M
C R 1
4
3
2
1
5
6
7
8
3
L E D 4 S M
C R 1
5
L E D 4 S M
C R 1
R N C 4 R 8 P
7
L E D 4 S M
4 7 0
R 1 6
C R 2
2
4
6
8
1
L E D 4
L E D 5
L E D 6
L E D 7
L E D 4 S M
C R 2
4
3
2
1
5
6
7
8
3
L E D 4 S M
C R 2
2
5
5
L E D 4 S M
C R 2
R N C 4 R 8 P
7
L E D 4 S M
R 5 9
1
2
1 / 1 0 W 5 %
1 0 K
C 1 2 0
C 1 2 1
2
1
2
1
C A P 0 8 0 5
C A P 0 8 0 5
0 . 1 u F
0 . 1 u F
C 1 1 8
C 1 1 9
2
1
2
1
C A P 0 8 0 5
0 . 0 4 7 u F
C A P 0 8 0 5
0 . 0 4 7 u F
R 1 4
1
2
1 / 1 0 W 5 %
1 . 5 K
C 7 6
C 9 2
1
C A P T 7 3 4 3
4 . 7 u F
C 5 7
1
C A P T 7 3 4 3
4 . 7 u F
2
2
1
2
2
2
2
C A P T 7 3 4 3
4 . 7 u F
C 7 7
C 9 6
1
C 6 1
1
1
C A P 0 8 0 5
0 . 0 1 u F
C A P 0 8 0 5
0 . 0 1 u F
C A P 0 8 0 5
0 . 0 1 u F
S _ A D 3 2
S _ A D 3 3
S _ A D 3 4
S _ A D 3 5
S _ A D 3 6
S _ A D 3 7
S _ A D 3 8
S _ A D 3 9
S _ A D 4 0
S _ A D 4 1
S _ A D 4 2
S _ A D 4 3
S _ A D 4 4
S _ A D 4 5
S _ A D 4 6
S _ A D 4 7
S _ A D 4 8
S _ A D 4 9
S _ A D 5 0
S _ A D 5 1
S _ A D 5 2
S _ A D 5 3
S _ A D 5 4
S _ A D 5 5
S _ A D 5 6
S _ A D 5 7
S _ A D 5 8
S _ A D 5 9
S _ A D 6 0
S _ A D 6 1
S _ A D 6 2
S _ A D 6 3
S _ A D 0
A H 1 4
S A D 3 2
S A D 3 3
S A D 3 4
S A D 3 5
S A D 3 6
S A D 3 7
S A D 3 8
S A D 3 9
S A D 4 0
S A D 4 1
S A D 4 2
S A D 4 3
S A D 4 4
S A D 4 5
S A D 4 6
S A D 4 7
S A D 4 8
S A D 4 9
S A D 5 0
S A D 5 1
S A D 5 2
S A D 5 3
S A D 5 4
S A D 5 5
S A D 5 6
S A D 5 7
S A D 5 8
S A D 5 9
S A D 6 0
S A D 6 1
S A D 6 2
S A D 6 3
A H 1
A H 3
A H 4
A J 2
S A D 0
S _ A D 1
A K 1 4
S A D 1
S _ A D 2
A L 1 4
S A D 2
S _ A D 3
A M 1 4
S A D 3
S _ A D 4
A H 1 5
A J 5
S A D 4
S _ A D 5
A K 5
A M 5
A H 6
A K 6
A L 6
A J 1 5
S A D 5
S _ A D 6
A K 1 5
S A D 6
S _ A D 7
A M 1 5
S A D 7
S _ A D 8
A J 1 7
S A D 8
S _ A D 9
A K 1 7
S A D 9
S _ A D 1 0
A M 1 7
A M 6
A H 7
A J 7
S A D 1 0
S A D 1 1
S A D 1 2
S A D 1 3
S A D 1 4
S A D 1 5
S A D 1 6
S A D 1 7
S A D 1 8
S A D 1 9
S A D 2 0
S A D 2 1
S A D 2 2
S A D 2 3
S A D 2 4
S A D 2 5
S A D 2 6
S A D 2 7
S A D 2 8
S A D 2 9
S A D 3 0
S A D 3 1
S _ A D 1 1
A H 1 8
S _ A D 1 2
A K 1 8
S _ A D 1 3
A K 7
A M 7
A H 8
A K 8
A L 8
A L 1 8
S _ A D 1 4
A M 1 8
S _ A D 1 5
A H 1 9
S _ A D 1 6
A H 2 2
S _ A D 1 7
A K 2 2
S _ A D 1 8
A L 2 2
A M 8
A H 9
A J 9
S _ A D 1 9
A M 2 2
S _ A D 2 0
A H 2 3
S _ A D 2 1
A K 9
A M 9
A H 1 0
A K 1 0
A L 1 0
A M 1 0
A H 1 1
A J 1 1
A K 1 1
A M 1 1
A H 1 2
A J 2 3
S _ A D 2 2
A K 2 3
S _ A D 2 3
A M 2 3
S _ A D 2 4
A K 2 4
S _ A D 2 5
A L 2 4
S _ A D 2 6
A M 2 4
S _ A D 2 7
A H 2 5
S _ A D 2 8
A J 2 5
S _ A D 2 9
A K 2 5
S _ A D 3 0
A M 2 5
S _ A D 3 1
A H 2 6
C 6 3
2
2
1
C A P T 7 3 4 3
3 3 u F
3 3 0 u F
C A P T 7 3 4 3 H
1
C 6 4
1 0 0 u F
C A P T 7 3 4 3 H
2
2
1
C 5 6
C 5 3
4 7 u H
L 1
1
C A P 0 8 0 5
0 . 1 u F
R 2 1
3
2
1
7
6
5
2
1
2
1
1 W 1 %
0 . 0 5
R 4 7
1
2
1 / 1 0 W 5 %
C 5 1
1
2 . 4 K
2
C A P 0 8 0 5
0 . 1 u F
C 5 2
2
1
C A P T 7 3 4 3
1 0 u F
C 6 5
1
2
1
2
1
2
1
2
2
1
C A P 1 2 0 6
0 . 4 7 u F
C R 8
C 4 7
1
C A P T 7 3 4 3
2 2 u F
R 3 5
1
R 3 2
1
1
2
1
2
1
2
1
2
1
2
2
2
2
C M R 1 - 0 2
1 / 1 0 W 5 %
1 / 1 0 W 5 %
1 0 K
1 0 0 K
2
Q 4
1
2 N 6 1 0 9
R 2 0
3
C 8 2
1
C A P 0 8 0 5
0 . 0 4 7 u F
R 4 9
R 4 8
2
1
1 / 1 0 W 5 %
1 5 0
2
2
2
1
2
2
1 / 1 0 W 5 %
4 . 7 K
C 5 5
R 2 4
2
1
C A P 0 8 0 5
0 . 0 1 u F
1
1
1 / 1 0 W 5 %
1 / 1 0 W 5 %
4 . 7 K
1 0 0 K
R 5 3
1
C 5 8
1
C A P 0 8 0 5
0 . 0 1 u F
R 2 5
C 6 8
1
C A P 0 8 0 5
0 . 0 1 u F
2
2
1
1 / 1 0 W 5 %
2
R 3 4
1
1 / 1 0 W 5 %
4 7 K
1 K
R 2 6
1
2
2
1 u F
1
1 / 1 0 W 5 %
1 / 1 0 W 5 %
C A P T 3 2 1 6
R 2 8
1
R 2 7
1
6 8 K
2 2 K
2
2
2
1 / 1 0 W 5 % 1 / 1 0 W 5 %
1
C 7 4
1 0 u F
C A P T 7 3 4 3
1
R 6 0
2
1
2
1
1 / 1 0 W 5 %
C 5 4
1 0
Schematics
Table B-2. IQ80960RM Schematics List
Page
Schematic Title
B-14
B-15
B-16
B-17
B-18
B-19
B-20
B-21
B-22
B-23
Decoupling and 3.3V Power
Primary PCI Interface
Memory Controller
Flash ROM, UART, & LEDs
Logic Analyzer I/F
SDRAM 168-Pin DIMM
Secondary PCI/960 Core
Secondary PCI Bus 1/2
Secondary PCI Bus 3/4
Battery/Monitor
IQ80960RM/RN Evaluation Board Manual
B-13
2 2 0 u F
C A P T 7 3 4 3
2
2
1
C 7 8
2 2 0 u F
C A P T 7 3 4 3
1
C 7 5
1
C O I L - S M T 2
3 . 3 u H
L 2
C 8 6
2
1
2
1
C A P 0 8 0 5
0 . 1 u F
R 5 4
1
2
1 / 8 W 5 %
1 0
R 3 9
1
2
1 / 1 0 W 5 %
1 0 K
R 5 8
1
2
1 / 1 0 W 5 %
1 0 K
C 8 9
2
2
1
C A P T 7 3 4 3
4 7 u F
C 9 4
1
C A P 0 8 0 5
0 . 1 u F
C 9 5
2
1
C A P 0 8 0 5
0 . 1 u F
C 1 0 4
P _ A D 0
U 1
P A D 0
P _ A D 1
2
2
2
2
2
2
1
U 2
P A D 1
C A P 0 8 0 5
P _ A D 2
U 3
P A D 2
0 . 1 u F
P _ A D 3
T 1
P A D 3
C 1 0 2
P _ A D 4
T 3
P A D 4
1
P _ A D 5
T 4
P A D 5
C A P 0 8 0 5
0 . 1 u F
P _ A D 6
T 5
P A D 6
C 1 0 1
P _ A D 7
R 1
P A D 7
1
P _ A D 8
R 3
P A D 8
C A P 0 8 0 5
P _ A D 9
0 . 1 u F
R 5
P A D 9
C 1 0 0
P _ A D 1 0
P 1
P A D 1 0
P A D 1 1
P A D 1 2
P A D 1 3
P A D 1 4
P A D 1 5
P A D 1 6
P A D 1 7
P A D 1 8
P A D 1 9
P A D 2 0
P A D 2 1
P A D 2 2
P A D 2 3
P A D 2 4
P A D 2 5
P A D 2 6
P A D 2 7
P A D 2 8
P A D 2 9
P A D 3 0
P A D 3 1
P _ A D 1 1
1
P 3
C A P 0 8 0 5
P _ A D 1 2
P 4
0 . 1 u F
C 9 8
P _ A D 1 3
P 5
P _ A D 1 4
N 1
1
P _ A D 1 5
N 2
C A P 0 8 0 5
0 . 1 u F
C 9 7
P _ A D 1 6
K 3
P _ A D 1 7
K 4
1
P _ A D 1 8
K 5
C A P 0 8 0 5
0 . 1 u F
P _ A D 1 9
J 1
P _ A D 2 0
J 2
P _ A D 2 1
J 3
P _ A D 2 2
J 5
P _ A D 2 3
H 1
P _ A D 2 4
H 5
P _ A D 2 5
G 1
P _ A D 2 6
G 2
P _ A D 2 7
G 3
P _ A D 2 8
E 5
P _ A D 2 9
A 6
P _ A D 3 0
C 6
P _ A D 3 1
D 6
R 5 7
1
2
1 / 1 0 W 5 %
2 . 7 K
R 4 1
1
2
1 / 1 0 W 5 %
1 . 5 K
R 4 2
1
2
1 / 1 0 W 5 %
1 . 5 K
1
D Q 3 2
D Q 3 3
D Q 3 4
D Q 3 5
D Q 3 6
D Q 3 7
D Q 3 8
D Q 3 9
D Q 4 0
D Q 4 1
D Q 4 2
D Q 4 3
D Q 4 4
D Q 4 5
D Q 4 6
D Q 4 7
D Q 4 8
D Q 4 9
D Q 5 0
D Q 5 1
D Q 5 2
D Q 5 3
D Q 5 4
D Q 5 5
D Q 5 6
D Q 5 7
D Q 5 8
D Q 5 9
D Q 6 0
D Q 6 1
D Q 6 2
D Q 6 3
D Q 0
D Q 1
D Q 3 2
D Q 3 3
D Q 3 4
D Q 3 5
D Q 3 6
D Q 3 7
D Q 3 8
D Q 3 9
D Q 4 0
D Q 4 1
D Q 4 2
D Q 4 3
D Q 4 4
D Q 4 5
D Q 4 6
D Q 4 7
D Q 4 8
D Q 4 9
D Q 5 0
D Q 5 1
D Q 5 2
D Q 5 3
D Q 5 4
D Q 5 5
D Q 5 6
D Q 5 7
D Q 5 8
D Q 5 9
D Q 6 0
D Q 6 1
D Q 6 2
D Q 6 3
E 2 2
D 2 2
D Q 0
D Q 1
B 2 3
A 2 3
D Q 2
C 2 3
E 2 3
D Q 2
D Q 3
C 2 4
A 2 4
D Q 3
D Q 4
D 2 4
E 2 4
D Q 4
D Q 5
B 2 5
A 2 5
D Q 5
D Q 6
C 2 5
E 2 5
D Q 6
D Q 7
C 2 6
A 2 6
D Q 7
D Q 8
E 2 6
A 2 7
D Q 8
D Q 9
C 2 7
B 2 7
D Q 9
D Q 1 0
E 2 7
A 2 8
D Q 1 0
D Q 1 1
D Q 1 2
D Q 1 3
D Q 1 4
D Q 1 5
D Q 1 6
D Q 1 7
D Q 1 8
A A 3 2 D Q 1 9
D Q 1 1
G 3 2
H 3 1
C 2 8
D Q 1 2
H 3 2
D Q 1 3
H 2 8
H 3 0
D Q 1 4
J 3 2
J 3 0
D Q 1 5
J 2 8
J 2 9
D Q 1 6
W 2 9
W 2 8
Y 3 1
D Q 1 7
Y 3 2
D Q 1 8
Y 3 0
Y 2 8
D Q 1 9
D Q 2 0
D Q 2 1
D Q 2 2
D Q 2 3
D Q 2 4
D Q 2 5
D Q 2 6
D Q 2 7
D Q 2 8
D Q 2 9
D Q 3 0
D Q 3 1
A A 3 0
A A 2 8
A B 3 1
A B 2 8
A C 3 0
A C 2 8
A D 3 1
A D 2 8
A E 3 0
A E 2 8
A F 3 1
A F 2 8
A H 3 2
A A 2 9
A B 3 2
A B 3 0
D Q 2 0
D Q 2 1
D Q 2 2
A C 3 2 D Q 2 3
A C 2 9 D Q 2 4
A D 3 2 D Q 2 5
A D 3 0 D Q 2 6
A E 3 2
A E 2 9
A F 3 2
A F 3 0
D Q 2 7
D Q 2 8
D Q 2 9
D Q 3 0
A G 3 2 D Q 3 1
C 1 1 0
2
1
C A P 0 8 0 5
1 8 p F
9
1 2
C R 1
4 7 0
R 1 5
2
4
6
8
1
L E D 0
L E D 1
L E D 2
L E D 3
L E D 4 S M
C R 1
4
3
2
1
5
6
7
8
3
L E D 4 S M
C R 1
5
L E D 4 S M
C R 1
R N C 4 R 8 P
7
L E D 4 S M
4 7 0
R 1 6
C R 2
2
4
6
8
1
L E D 4
L E D 5
L E D 6
L E D 7
L E D 4 S M
C R 2
4
3
2
1
5
6
7
8
3
L E D 4 S M
C R 2
2
5
5
L E D 4 S M
C R 2
R N C 4 R 8 P
7
L E D 4 S M
R 5 9
1
2
1 / 1 0 W 5 %
1 0 K
C 1 2 0
C 1 2 1
2
1
2
1
C A P 0 8 0 5
C A P 0 8 0 5
0 . 1 u F
0 . 1 u F
C 1 1 8
C 1 1 9
2
1
2
1
C A P 0 8 0 5
0 . 0 4 7 u F
C A P 0 8 0 5
0 . 0 4 7 u F
R 1 4
1
2
1 / 1 0 W 5 %
1 . 5 K
C 7 6
C 9 2
1
C A P T 7 3 4 3
4 . 7 u F
C 5 7
1
C A P T 7 3 4 3
4 . 7 u F
2
2
1
2
2
2
2
C A P T 7 3 4 3
4 . 7 u F
C 7 7
C 9 6
1
C 6 1
1
1
C A P 0 8 0 5
0 . 0 1 u F
C A P 0 8 0 5
0 . 0 1 u F
C A P 0 8 0 5
0 . 0 1 u F
S _ A D 0
A H 1 4
S A D 0
S _ A D 1
A K 1 4
S A D 1
S _ A D 2
A L 1 4
S A D 2
S _ A D 3
A M 1 4
S A D 3
S _ A D 4
A H 1 5
S A D 4
S _ A D 5
A J 1 5
S A D 5
S _ A D 6
A K 1 5
S A D 6
S _ A D 7
A M 1 5
S A D 7
S _ A D 8
A J 1 7
S A D 8
S _ A D 9
A K 1 7
S A D 9
S _ A D 1 0
A M 1 7
S A D 1 0
S A D 1 1
S A D 1 2
S A D 1 3
S A D 1 4
S A D 1 5
S A D 1 6
S A D 1 7
S A D 1 8
S A D 1 9
S A D 2 0
S A D 2 1
S A D 2 2
S A D 2 3
S A D 2 4
S A D 2 5
S A D 2 6
S A D 2 7
S A D 2 8
S A D 2 9
S A D 3 0
S A D 3 1
S _ A D 1 1
A H 1 8
S _ A D 1 2
A K 1 8
S _ A D 1 3
A L 1 8
S _ A D 1 4
A M 1 8
S _ A D 1 5
A H 1 9
S _ A D 1 6
A H 2 2
S _ A D 1 7
A K 2 2
S _ A D 1 8
A L 2 2
S _ A D 1 9
A M 2 2
S _ A D 2 0
A H 2 3
S _ A D 2 1
A J 2 3
S _ A D 2 2
A K 2 3
S _ A D 2 3
A M 2 3
S _ A D 2 4
A K 2 4
S _ A D 2 5
A L 2 4
S _ A D 2 6
A M 2 4
S _ A D 2 7
A H 2 5
S _ A D 2 8
A J 2 5
S _ A D 2 9
A K 2 5
S _ A D 3 0
A M 2 5
S _ A D 3 1
A H 2 6
C 6 3
2
2
1
C A P T 7 3 4 3
3 3 u F
3 3 0 u F
C A P T 7 3 4 3 H
1
C 6 4
1 0 0 u F
C A P T 7 3 4 3 H
2
2
1
C 5 6
C 5 3
4 7 u H
L 1
1
C A P 0 8 0 5
0 . 1 u F
R 2 1
3
2
1
7
6
5
2
1
2
1
1 W 1 %
0 . 0 5
R 4 7
1
2
1 / 1 0 W 5 %
C 5 1
1
2 . 4 K
2
C A P 0 8 0 5
0 . 1 u F
C 5 2
2
1
C A P T 7 3 4 3
1 0 u F
C 6 5
1
2
1
2
1
2
1
2
2
1
C A P 1 2 0 6
0 . 4 7 u F
C R 8
C 4 7
1
C A P T 7 3 4 3
2 2 u F
R 3 5
1
R 3 2
1
1
2
1
2
1
2
1
2
1
2
2
2
2
C M R 1 - 0 2
1 / 1 0 W 5 %
1 / 1 0 W 5 %
1 0 K
1 0 0 K
2
Q 4
1
2 N 6 1 0 9
R 2 0
3
C 8 2
1
C A P 0 8 0 5
0 . 0 4 7 u F
R 4 9
R 4 8
2
1
1 / 1 0 W 5 %
1 5 0
2
2
2
1
2
2
1 / 1 0 W 5 %
4 . 7 K
C 5 5
R 2 4
2
1
C A P 0 8 0 5
0 . 0 1 u F
1
1
1 / 1 0 W 5 %
1 / 1 0 W 5 %
4 . 7 K
1 0 0 K
R 5 3
1
C 5 8
1
C A P 0 8 0 5
0 . 0 1 u F
R 2 5
C 6 8
1
C A P 0 8 0 5
0 . 0 1 u F
2
2
1
1 / 1 0 W 5 %
2
R 3 4
1
1 / 1 0 W 5 %
4 7 K
1 K
R 2 6
1
2
2
1 u F
1
1 / 1 0 W 5 %
1 / 1 0 W 5 %
C A P T 3 2 1 6
R 2 8
1
R 2 7
1
6 8 K
2 2 K
2
2
2
1 / 1 0 W 5 % 1 / 1 0 W 5 %
1
C 7 4
1
2
R 6 0
C 5 4
1
2
1
1 / 1 0 W 5 %
C A P T 7 3 4 3
1 0 u F
1 0
PLD Code
C
MODULE BATT
//TITLE
SDRAM Battery Backup Enable
101-1809-01
//PATTERN
//REVISION
//AUTHOR
//COMPANY
//DATE
J. Neumann
Cyclone Microsystems Inc.
10/30/97
//CHIP
PALLV16V8Z-20JI
// 1/20/98 Modify target device to PALLV16V8Z-20JI
//Initial release.
PRSTn
SCKE0
SCKE1
OUT0
OUT1
PIN 9;//Primary PCI reset
PIN 13; //SDRAM bank 0 clock enable
PIN 16; //SDRAM bank 1 clock enable
PIN 14; //SCKE0 output enable
PIN 17; //SCKE1 output enable
EQUATIONS
// If SDRAM clock enable goes low, SDRAM clock enable
// must be held low to ensure that the SDRAM is held in auto refresh mode.
// Reset going high will release the hold on SCKE.
OUT0 = SCKE0.PIN & PRSTn
# SCKE0.PIN & OUT0.PIN
# !SCKE0.PIN & PRSTn;
//SCKE is the set term, PRSTn is the reset term
SCKE0 = 0;
SCKE0.OE = !OUT0;
//When OUT = 0, SCKE is grounded
//When OUT = 1, SCKE is high impedance
OUT1 = SCKE1.PIN & PRSTn
# SCKE1.PIN & OUT1.PIN
# !SCKE1.PIN & PRSTn;
SCKE1 = 0;
SCKE1.OE = !OUT1;
END
IQ80960RM/RN Evaluation Board Manual
C-1
Recycling the Battery
D
The IQ80960RM/RN platform contains four AA NiCd batteries. Each battery has the logo of the
Rechargeable Battery Recycling Corporation (RBRC) stamped on it. The recycling fees have been
prepaid on these batteries. Do not dispose of a rechargeable battery with regular trash in a landfill.
Rechargeable batteries contain toxic chemicals and metals that are harmful to the environment.
Improperly disposing of rechargeable batteries is also illegal. The RBRC logo on a battery is a
verification that recycling fees have been prepaid to the RBRC and such a battery can be recycled
at no additional cost to the user. The RBRC is a non-profit corporation that promotes the recycling
of rechargeable batteries, including NiCd batteries.
Information on the RBRC program and the locations of participating recycling centers can be
obtained by telephoning 1-800-8-BATTERY (in the USA), and following the recorded instructions.
The information obtained from this telephone number is updated frequently, since the RBRC
program is growing, the new recycling locations are being added regularly.
IQ80960RM/RN Evaluation Board Manual
D-1
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