SMSC Switch USB2512Ai User Manual
USB2512Ai  
Industrial Temperature Rated  
USB 2.0 Hi-Speed 2-Port Hub  
Controller  
Datasheet  
PRODUCT FEATURES  
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Programmable USB differential-pair pin location:  
Ease PCB layout by aligning USB signal lines directly  
to connectors  
Programmable USB signal drive strength: Recover  
USB signal integrity due to compromised system  
environment using 2-level driving strength resolution  
Select the presence of a permanently hardwired USB  
peripheral device on a port-by-port basis  
Configure the delay time for filtering the over-current  
sense inputs  
Configure the delay time for turning on downstream  
port power  
Indicate the maximum current that the 2-port Hub  
consumes from the USB upstream port  
Indicate the maximum current required for the Hub  
controller  
General Description  
The SMSC 2-Port Hub is a low power, OEM  
configurable, STT (single transaction translator) Hub  
controller IC with 2 downstream ports for embedded  
USB solutions. The 2-port Hub is fully compliant with  
the USB 2.0 Specification and will attach to an upstream  
port as a Full-Speed Hub or as a Full-/Hi-Speed Hub.  
The 2-Port Hub supports Low-Speed, Full-Speed, and  
Hi-Speed (if operating as a Hi-Speed Hub) downstream  
devices on all of the enabled downstream ports.  
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General Features  
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Hub Controller IC with 2 downstream ports  
Enhanced OEM configuration options available  
„
2
through either a single serial I C EEPROM, or  
Pin Selectable Option for Default Configuration:  
Select Downstream Ports as Non-Removable Ports  
SMBus Slave Port  
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„
36-pin (6x6mm) QFN lead-free RoHS compliant  
Applications  
package  
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LCD monitors and TVs  
Multi-function USB peripherals  
PC motherboards  
Set-top boxes, DVD players, DVR/PVR  
Printers and scanners  
PC media drive bay  
Portable Hub boxes  
Mobile PC docking  
Embedded systems  
Supports industrial temperature range of -40ºC to  
85ºC  
Hardware Features  
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Low power operation  
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Full power management with individual or ganged  
power control of each downstream port  
On-chip Power-On Reset (POR)  
Internal 1.8V Voltage Regulator  
Fully integrated USB termination and Pull-up/Pull-  
down resistors  
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On Board 24MHz Crystal Driver, Resonator, or  
External 24MHz clock input  
Enhanced EMI rejection and ESD protection  
performance  
OEM Selectable Features  
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Customizable Vendor ID, Product ID, and Device ID  
Select whether the Hub is part of a compound device:  
When any downstream port is permanently hardwired  
to a USB peripheral device, the Hub is part of a  
compound device  
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Flexible port mapping and disable sequence: Ports  
can be disabled or reordered in any order to support  
multiple product SKUs. The Hub will automatically  
reorder the remaining ports to match the Host  
controller's numbering scheme.  
SMSC USB2512Ai  
DATASHEET  
Revision 1.97 (08-11-08)  
Download from Www.Somanuals.com. All Manuals Search And Download.  
Industrial Temperature Rated USB 2.0 Hi-Speed 2-Port Hub Controller  
Datasheet  
Table of Contents  
Chapter 1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
Chapter 2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Chapter 3 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
3.1  
3.2  
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Buffer Type Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Chapter 4 Configuration Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
4.1  
2-Port Hub . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
4.1.1  
4.1.2  
Hub Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
VBus Detect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
4.2  
EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
4.2.1  
4.2.2  
4.2.3  
Internal Register Set (Common to EEPROM and SMBus) . . . . . . . . . . . . . . . . . . . . . . . 13  
I C EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24  
In-Circuit EEPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25  
2
4.3  
SMBus Slave Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25  
4.3.1  
4.3.2  
4.3.3  
4.3.4  
4.3.5  
4.3.6  
4.3.7  
4.3.8  
Bus Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25  
Invalid Protocol Response Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
General Call Address Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
Slave Device Time-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
Stretching the SCLK Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
SMBus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
Bus Reset Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
SMBus Alert Response Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
4.4  
4.5  
4.6  
Default Configuration Option: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
Default Strapping Options: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
4.6.1  
4.6.2  
4.6.3  
Internal POR Hardware Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
External Hardware RESET_N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28  
USB Bus Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30  
Chapter 5 DC Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32  
5.1  
5.2  
Maximum Guaranteed Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32  
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33  
Chapter 6 AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36  
6.1  
Oscillator/Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36  
6.1.1  
6.1.2  
6.1.3  
SMBus Interface: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36  
I C EEPROM: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36  
USB 2.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36  
2
Chapter 7 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37  
SMSC USB2512Ai  
3
Revision 1.97 (08-11-08)  
DATASHEET  
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Industrial Temperature Rated USB 2.0 Hi-Speed 2-Port Hub Controller  
Datasheet  
List of Figures  
Figure 1.1 USB2512Ai 36-Pin QFN (Embedded Footprint). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
Figure 2.1 USB2512Ai Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Figure 4.1 Block Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
Figure 4.2 Block Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
Figure 4.3 Reset_N Timing for Default/Strap Option Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28  
Figure 4.4 Reset_N Timing for EEPROM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29  
Figure 4.5 Reset_N Timing for SMBus Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30  
Figure 5.1 Supply Rise Time Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32  
Figure 6.1 Typical Crystal Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36  
Figure 6.2 Formula to find value of C1 and C2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36  
Figure 7.1 36-Pin QFN, 6x6mm Body, 0.5mm Pitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37  
Revision 1.97 (08-11-08)  
4
SMSC USB2512Ai  
DATASHEET  
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Industrial Temperature Rated USB 2.0 Hi-Speed 2-Port Hub Controller  
Datasheet  
List of Tables  
Table 3.1 USB2512Ai Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Table 3.2 SMBus or EEPROM Interface Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
Table 3.3 Power, Ground, and No Connect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
Table 3.4 Buffer Type Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Table 4.1 Internal Default, EEPROM and SMBus Register Memory Map. . . . . . . . . . . . . . . . . . . . . . . . 13  
Table 4.2 Port Remap Register for Ports 1 & 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
Table 4.3 Reset_N Timing for Default/Strap Option Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28  
Table 4.4 Reset_N Timing for EEPROM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29  
Table 4.5 Reset_N Timing for SMBus Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30  
Table 5.1 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33  
Table 5.2 Pin Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35  
SMSC USB2512Ai  
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Industrial Temperature Rated USB 2.0 Hi-Speed 2-Port Hub Controller  
Datasheet  
Chapter 1 Pin Configuration  
SUSP_IND/LOCAL_PWR/NON_REM0  
NC  
28  
29  
30  
31  
32  
33  
34  
35  
36  
18  
17  
16  
15  
14  
13  
12  
11  
10  
VDDA33  
USBUP_DM  
USBUP_DP  
XTAL2  
OCS2_N  
PRTPWR2  
VDD33CR  
VDD18  
SMSC  
USB2512Ai  
Embedded Footprint  
(Top View QFN-36)  
XTAL1/CLKIN  
VDD18PLL  
RBIAS  
OCS1_N  
PRTPWR1  
TEST  
Thermal Slug  
(must be connected to VSS)  
VDD33PLL  
VDDA33  
Indicates pins on the bottom of the device.  
Figure 1.1 USB2512Ai 36-Pin QFN (Embedded Footprint)  
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Industrial Temperature Rated USB 2.0 Hi-Speed 2-Port Hub Controller  
Datasheet  
Chapter 2 Block Diagram  
To Upstream  
VBUS  
Upstream USB  
Data  
To EEPROM or  
SMBus Master  
24 MHz Crystal  
SD  
SCK  
3.3V  
1.8V  
PLL  
Serial  
Bus-Power  
Detect/VBUS  
Pulse  
Interface  
Upstream  
PHY  
1.8V Reg  
SIE  
Controller  
Repeater  
Port  
Controller  
TT  
Routing & Port Re-Ordering Logic  
Port #1  
OC  
Port #2  
OC  
Sense  
Sense  
Switch  
Driver  
LED  
PHY#1  
PHY#2  
Switch  
Driver  
LED  
Drivers  
Drivers  
OC Sense  
Switch/LED  
Drivers  
OC Sense  
Switch/LED  
Drivers  
USB Data  
Downstream  
USB Data  
Downstream  
Figure 2.1 USB2512Ai Block Diagram  
SMSC USB2512Ai  
7
Revision 1.97 (08-11-08)  
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Industrial Temperature Rated USB 2.0 Hi-Speed 2-Port Hub Controller  
Datasheet  
Chapter 3 Pin Descriptions  
3.1  
Pin Descriptions  
This section provides a detailed description of each signal. The signals are arranged in functional  
groups according to their associated interface.  
The “N” symbol in the signal name indicates that the active, or asserted, state occurs when the signal  
is at a low voltage level. When “N” is not present before the signal name, the signal is asserted when  
at the high voltage level.  
The terms assertion and negation are used exclusively. This is done to avoid confusion when working  
with a mixture of “active low” and “active high” signals. The term assert, or assertion, indicates that a  
signal is active, independent of whether that level is represented by a high or low voltage. The term  
negate, or negation, indicates that a signal is inactive.  
Table 3.1 USB2512Ai Pin Descriptions  
QFN-36  
EMB  
BUFFER  
TYPE  
SYMBOL  
DESCRIPTION  
UPSTREAM USB INTERFACES  
USBUP_DP  
USBUP_DM  
31  
30  
IO-U  
USB Bus Data  
These pins connect to the upstream USB bus data signals such  
as the Host port or upstream Hub.  
VBUS_DET  
27  
I/O12  
Detect Upstream VBUS Power  
Detects state of Upstream VBUS power. The SMSC Hub  
monitors VBUS_DET to determine when to assert the internal  
D+ pull-up resistor which signals a connect event.  
When designing a detachable Hub, this pin must be connected  
to the VBUS power pin of the USB port that is upstream from  
the Hub.  
For self-powered applications with a permanently attached  
host, this pin must be connected to 3.3V (typically VDD33).  
DOWNSTREAM 2-PORT USB 2.0 INTERFACE  
USBDN[2:1]_DP/  
&
4
2
IO-U  
O12  
IPU  
Hi-Speed USB Data  
These pins connect to the downstream USB peripheral devices  
attached to the Hub’s port.  
3
1
USBDN[2:1]_DM/  
PRTPWR[2:1]  
16  
12  
USB Power Enable  
Enables power to USB peripheral devices downstream.  
Note:  
The Hub supports active high power controllers only!  
OCS[2:1]_N  
17  
13  
Over-Current Sense  
Input from external current monitor indicating an over-current  
condition.  
{Note: Contains internal pull-up to 3.3V supply}  
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Industrial Temperature Rated USB 2.0 Hi-Speed 2-Port Hub Controller  
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Table 3.1 USB2512Ai Pin Descriptions (continued)  
QFN-36 BUFFER  
SYMBOL  
EMB  
TYPE  
DESCRIPTION  
RBIAS  
35  
I-R  
USB Transceiver Bias  
A 12.0kΩ (+/- 1%) resistor is attached from ground to this pin  
to set the transceiver’s internal bias settings.  
SERIAL PORT INTERFACE  
SDA/  
SMBDATA/  
NON_REM1  
22  
I/OSD12  
Serial Data / SMB Data & Port Non-removable Strap Option  
NON_REM1: Non-removable port strap option.  
If this strap is enabled by package and configuration settings  
(see Table 3.2, "SMBus or EEPROM Interface Behavior"), this  
pin will be sampled (in conjunction with LOCAL_PWR/  
SUSP_IND/NON_REM0) at RESET_N negation to determine if  
ports [2:1] contain permanently attached (non-removable)  
devices:  
NON_REM[1:0] = ‘00’, All ports are removable.  
NON_REM[1:0] = ‘01’, Port 1 is non-removable.  
NON_REM[1:0] = ‘10’, Ports 1 & 2 are non-removable.  
NON_REM[1:0] = ‘11’, Ports 1 & 2 are non-removable.  
Serial Clock (SCL)  
SCL/  
24  
I/OSD12  
SMBus Clock (SMBCLK)  
SMBCLK/  
CFG_SEL0  
Configuration Select_SEL0: The logic state of this multifunction  
pin is internally latched on the rising edge of RESET_N  
(RESET_N negation), and will determine the Hub configuration  
method as described in Table 3.2, "SMBus or EEPROM  
Interface Behavior".  
HS_IND/  
CFG_SEL1  
25  
I/O12  
Hi-Speed Upstream port indicator & Configuration  
Programming Select  
HS_IND: Hi-Speed Indicator for upstream port connection  
speed.  
The active state of the LED will be determined as follows:  
CFG_SEL1 = ‘0’,  
HS_IND is active high,  
CFG_SEL1 = ‘1’,  
HS_IND is active low,  
‘Asserted’ = Hub is connected at HS  
‘Negated’ = Hub is connected at FS  
CFG_SEL1: The logic state of this pin is internally latched on  
the rising edge of RESET_N (RESET_N negation), and will  
determine the Hub configuration method as described in  
Table 3.2, "SMBus or EEPROM Interface Behavior".  
MISC  
XTAL1/  
CLKIN  
33  
ICLKx  
Crystal Input/External Clock Input  
24MHz crystal or external clock input.  
This pin connects to either one terminal of the crystal or to an  
external 24MHz clock when a crystal is not used.  
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Industrial Temperature Rated USB 2.0 Hi-Speed 2-Port Hub Controller  
Datasheet  
Table 3.1 USB2512Ai Pin Descriptions (continued)  
QFN-36  
EMB  
BUFFER  
TYPE  
SYMBOL  
DESCRIPTION  
XTAL2  
32  
OCLKx  
Crystal Output  
24MHz Crystal  
This is the other terminal of the crystal, or a NO CONNECT  
when an external clock source is used to drive XTAL1/CLKIN.  
Note:  
This output must not be used to drive any external  
circuitry other than the crystal circuit.  
RESET_N  
26  
IS  
RESET Input  
The system can reset the chip by driving this input low. The  
minimum active low pulse is 1 μs.  
When the RESET_N pin is pulled to VDD33, the internal POR  
(Power-on Reset) is enabled and no external reset circuitry is  
required. The internal POR holds the internal logic in reset until  
the power supplies are stable.  
SUSP_IND/  
LOCAL_PWR/  
NON_REM0  
28  
I/O  
Active/Suspend status LED or Local-Power & Non-removable  
Strap Option  
Suspend Indicator: Indicates USB state of the Hub.  
‘negated’ = Unconfigured, or configured and in USB Suspend  
‘asserted’ = Hub is configured, and is active (i.e., not in  
suspend)  
Local Power: Detects availability of local self-power source.  
Low = Self/local power source is NOT available (i.e., Hub gets  
all power from Upstream USB VBus).  
High = Self/local power source is available.  
NON_REM0 Strap Option:  
If this strap is enabled by package and configuration settings  
(see Table 3.2, "SMBus or EEPROM Interface Behavior"), this  
pin will be sampled (in conjunction with NON_REM1) at  
RESET_N negation to determine if ports [2:1] contain  
permanently attached (non-removable) devices. Also, the  
active state of the LED will be determined as follows:  
NON_REM[1:0] = ‘00’, All ports are removable, and the LED is  
active high  
NON_REM[1:0] = ‘01’, Port 1 is non-removable, and the LED  
is active low  
NON_REM[1:0] = ‘10’, Ports 1 & 2 are non-removable, and the  
LED is active high  
NON_REM[1:0] = ‘11’, Ports 1 & 2 are non-removable, and the  
LED is active low  
TEST  
11  
IPD  
TEST pin  
XNOR continuity tests all signal pins on the Hub. Please  
contact your SMSC representative for a detailed description of  
how this test mode is enabled and utilized.  
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Table 3.2 SMBus or EEPROM Interface Behavior  
CFG_SEL0 SMBUS OR EEPROM INTERFACE BEHAVIOR  
CFG_SEL1  
0
0
1
Internal Default Configuration  
Strap Options Enabled  
„
0
Configured as an SMBus slave for external download of user-defined  
descriptors  
„
„
„
SMBus slave address 58 (0101100x)  
Strap Options Disabled  
All Settings Controlled by Registers  
1
1
0
1
Internal Default Configuration  
„
Strap Options Enabled  
„
Bus Power Operation  
2
2-Wire I C EEPROMS are supported  
„
Strap Options Disabled  
„
All Settings Controlled by Registers  
Table 3.3 Power, Ground, and No Connect  
PACKAGE SYMBOL 36-QFN EMB FUNCTION  
VDD18  
14  
VDD Core  
This pin must have a 1.0μF (or greater) ±20% (ESR <0.1Ω) capacitor to  
VSS.  
VDD33PLL  
36  
VDD 3.3 PLL Regulator Reference  
+3.3V power supply for the PLL. If the internal PLL 1.8V regulator  
is enabled, then this pin acts as the regulator input.  
VDD18PLL  
34  
VDD PLL  
This pin must have a 1.0μF (or greater) ±20% (ESR <0.1Ω) capacitor to  
VSS.  
VDDA33  
5
10  
29  
VDD Analog I/O  
+3.3V Filtered analog PHY power, shared between adjacent ports.  
VDD33/VDD33CR  
23  
15  
VDDIO/VDD 3.3 Core Regulator Reference  
+3.3V power supply for the Digital I/O - If the internal core regulator is  
enabled, then VDD33CR acts as the regulator input.  
NC  
6
7
No Connect  
No trace or signal should be routed or attached to these pins.  
8
9
18  
19  
20  
21  
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3.2  
Buffer Type Descriptions  
Table 3.4 Buffer Type Descriptions  
DESCRIPTION  
BUFFER  
I/O  
IPD  
Input/Output.  
Input with internal weak pull-down resistor.  
Input with internal weak pull-up resistor.  
Input with Schmitt trigger.  
IPU  
IS  
O12  
Output 12mA.  
I/O12  
I/OSD12  
Input/Output buffer with 12mA sink and 12mA source.  
2
Open drain with Schmitt trigger and 12mA sink. Must meet I C-Bus Specification  
Version 2.1 requirements.  
ICLKx  
OCLKx  
I-R  
XTAL clock input.  
XTAL clock output.  
RBIAS.  
I/O-U  
Analog Input/Output Defined in USB specification.  
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Chapter 4 Configuration Options  
4.1  
2-Port Hub  
SMSC’s USB 2.0 2-Port Hub is fully specification compliant to the Universal Serial Bus Specification  
Revision 2.0 April 27, 2000 (12/7/2000 and 5/28/2002 Errata). Please reference Chapter 10 (Hub  
Specification) for general details regarding Hub operation and functionality.  
The 2-Port Hub provides 1 Transaction Translator (TT) that is shared by both downstream ports  
(defined as Single-TT configuration), The TT contains 4 non-periodic buffers.  
4.1.1  
Hub Configuration Options  
The SMSC Hub supports a large number of features (some are mutually exclusive), and must be  
configured in order to correctly function when attached to a USB host controller. There are three  
principal ways to configure the hub: SMBus, EEPROM, or by internal default settings (with or without  
pin strapping option over-rides). In all cases, the configuration method will be determined by the  
CFG_SEL1 and CFG_SEL0 pins immediately after RESET_N negation.  
4.1.1.1  
Power Switching Polarity  
The hub only supports “active high” port power controllers.  
4.1.2  
VBus Detect  
According to Section 7.2.1 of the USB 2.0 Specification, a downstream port can never provide power  
to its D+ or D- pull-up resistors unless the upstream port’s VBUS is in the asserted (powered) state.  
The VBUS_DET pin on the Hub monitors the state of the upstream VBUS signal and will not pull-up  
the D+ resistor if VBUS is not active. If VBUS goes from an active to an inactive state (Not Powered),  
the Hub will remove power from the D+ pull-up resistor within 10 seconds.  
4.2  
EEPROM Interface  
2
The SMSC Hub can be configured via a 2-wire (I C) EEPROM (256x8). (Please see Table 3.1 for  
2
specific details on how to enable configuration via an I C EEPROM).  
The Internal state-machine will (when configured for EEPROM support) read the external EEPROM for  
configuration data. The hub will then “attach” to the upstream USB host.  
Note: The Hub does not have the capacity to write, or “Program,” an external EEPROM. The Hub only  
has the capability to read external EEPROMs. The external eeprom will be read (even if it is blank or  
non-populated), and the hub will be “configured” with the values that are read.  
Please see Internal Register Set (Common to EEPROM and SMBus) for a list of data fields available.  
4.2.1  
Internal Register Set (Common to EEPROM and SMBus)  
Table 4.1 Internal Default, EEPROM and SMBus Register Memory Map  
SMBUS AND  
REG  
ADDR  
INTERNAL  
DEFAULT ROM  
EEPROM OR  
VALUES  
R/W  
REGISTER NAME  
ABBR  
00h  
01h  
02h  
R/W  
R/W  
R/W  
VID LSB  
VID MSB  
PID LSB  
VIDL  
VIDM  
PIDL  
24h  
04h  
12h  
0x00  
0x00  
0x00  
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Table 4.1 Internal Default, EEPROM and SMBus Register Memory Map (continued)  
SMBUS AND  
EEPROM OR  
VALUES  
REG  
ADDR  
INTERNAL  
DEFAULT ROM  
R/W  
REGISTER NAME  
ABBR  
03h  
04h  
05h  
06h  
07h  
08h  
09h  
0Ah  
0Bh  
0Ch  
0Dh  
0Eh  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
PID MSB  
DID LSB  
PIDM  
DIDL  
25h  
A0h  
0Ah  
8Bh  
10h  
00h  
00h  
00h  
00h  
01h  
32h  
01h  
0x00  
0x00  
0x00  
0x00  
0x00  
0x00  
0x00  
0x00  
0x00  
0x00  
0x00  
0x00  
DID MSB  
DIDM  
CFG1  
CFG2  
CFG3  
NRD  
Config Data Byte 1  
Config Data Byte 2  
Config Data Byte 3  
Non-Removable Devices  
Port Disable (Self)  
Port Disable (Bus)  
Max Power (Self)  
Max Power (Bus)  
PDS  
PDB  
MAXPS  
MAXPB  
HCMCS  
Hub Controller Max Current  
(Self)  
0Fh  
R/W  
Hub Controller Max Current  
(Bus)  
HCMCB  
32h  
0x00  
10h  
11h-F5h  
F6h  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Power-on Time  
Reserved  
PWRT  
N/A  
32h  
01h  
00h  
00h  
00h  
00h  
00h  
00h  
00h  
00h  
0x00  
0x00  
0x00  
0x00  
0x00  
0x00  
0x00  
0x00  
0x00  
0x00  
Boost_Up  
BOOSTUP  
N/A  
F7h  
Reserved  
F8h  
Boost_2:0  
Reserved  
BOOST20  
N/A  
F9h  
FAh  
Port Swap  
Port Remap 12  
Reserved  
PRTSP  
PRTR12  
N/A  
FBh  
FC-FEh  
FFh  
Status/Command  
Note: SMBus register only  
STCD  
4.2.1.1  
Register 00h: Vendor ID (LSB)  
BIT NAME  
BIT  
NUMBER  
DESCRIPTION  
7:0  
VID_LSB  
Least Significant Byte of the Vendor ID. This is a 16-bit value that uniquely  
identifies the Vendor of the user device (assigned by USB-Interface Forum).  
This field is set by the OEM using either the SMBus or EEPROM interface  
options.  
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4.2.1.2  
Register 01h: Vendor ID (MSB)  
BIT NAME  
BIT  
NUMBER  
DESCRIPTION  
7:0  
VID_MSB  
Most Significant Byte of the Vendor ID. This is a 16-bit value that uniquely  
identifies the Vendor of the user device (assigned by USB-Interface Forum).  
This field is set by the OEM using either the SMBus or EEPROM interface  
options.  
4.2.1.3  
Register 02h: Product ID (LSB)  
BIT NAME  
BIT  
NUMBER  
DESCRIPTION  
7:0  
PID_LSB  
Least Significant Byte of the Product ID. This is a 16-bit value that the Vendor  
can assign that uniquely identifies this particular product (assigned by OEM).  
This field is set by the OEM using either the SMBus or EEPROM interface  
options.  
4.2.1.4  
Register 03h: Product ID (MSB)  
BIT NAME  
BIT  
NUMBER  
DESCRIPTION  
7:0  
PID_MSB  
Most Significant Byte of the Product ID. This is a 16-bit value that the Vendor  
can assign that uniquely identifies this particular product (assigned by OEM).  
This field is set by the OEM using either the SMBus or EEPROM interface  
options.  
4.2.1.5  
Register 04h: Device ID (LSB)  
BIT NAME  
BIT  
NUMBER  
DESCRIPTION  
7:0  
DID_LSB  
Least Significant Byte of the Device ID. This is a 16-bit device release  
number in BCD format (assigned by OEM). This field is set by the OEM  
using either the SMBus or EEPROM interface options.  
4.2.1.6  
Register 05h: Device ID (MSB)  
BIT NAME  
BIT  
NUMBER  
DESCRIPTION  
7:0  
DID_MSB  
Most Significant Byte of the Device ID. This is a 16-bit device release  
number in BCD format (assigned by OEM). This field is set by the OEM  
using either the SMBus or EEPROM interface options.  
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4.2.1.7  
Register 06h: CONFIG_BYTE_1  
BIT NAME  
BIT  
NUMBER  
DESCRIPTION  
7
SELF_BUS_PWR  
Self or Bus Power: Selects between Self- and Bus-Powered operation.  
The Hub is either Self-Powered (draws less than 2mA of upstream bus  
power) or Bus-Powered (limited to a 100mA maximum of upstream power  
prior to being configured by the host controller).  
When configured as a Bus-Powered device, the SMSC Hub consumes less  
than 100mA of current prior to being configured. After configuration, the Bus-  
Powered SMSC Hub (along with all associated hub circuitry, any embedded  
devices if part of a compound device, and 100mA per externally available  
downstream port) must consume no more than 500mA of upstream VBUS  
current. The current consumption is system dependent, and the OEM must  
ensure that the USB 2.0 specifications are not violated.  
When configured as a Self-Powered device, <1mA of upstream VBUS  
current is consumed and all ports are available, with each port being capable  
of sourcing 500mA of current.  
This field is set by the OEM using either the SMBus or EEPROM interface  
options.  
Please see the description under Dynamic Power for the self/bus power  
functionality when dynamic power switching is enabled.  
0 = Bus-Powered operation  
1 = Self-Powered operation  
Note: If Dynamic Power Switching is enabled, this bit is ignored and the  
LOCAL_PWR pin is used to determine if the hub is operating from self or  
bus power.  
6
5
Reserved  
Reserved  
HS_DISABLE  
Hi-Speed Disable: Disables the capability to attach as either a Hi-/Full-Speed  
device, and forces attachment as Full-Speed only (i.e. no Hi-Speed support).  
0 = Hi-/Full-Speed  
1 = Full-Speed-Only (Hi-Speed disabled!)  
4
3
Reserved  
Reserved  
EOP_DISABLE  
EOP Disable: Disables EOP generation of EOF1 when in Full-Speed mode.  
During FS operation only, this permits the Hub to send EOP if no  
downstream traffic is detected at EOF1. See Section 11.3.1 of the USB 2.0  
Specification for additional details. Note: generation of an EOP at the EOF1  
point may prevent a Host controller (operating in FS mode) from placing the  
USB bus in suspend.  
0 = EOP generation is normal  
1 = EOP generation is disabled  
2:1  
CURRENT_SNS  
Over-Current Sense: Selects current sensing on a port-by-port basis, all  
ports ganged, or none (only for bus-powered hubs). The ability to support  
current sensing on a port or ganged basis is hardware implementation  
dependent.  
00 = Ganged sensing (all ports together)  
01 = Individual port-by-port  
1x = Over-current sensing not supported (must only be used with Bus-  
Powered configurations!)  
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BIT  
NUMBER  
BIT NAME  
DESCRIPTION  
0
PORT_PWR  
Port Power Switching: Enables power switching on all ports simultaneously  
(ganged), or port power is individually switched on and off on a port- by-port  
basis (individual). The ability to support power enabling on a port or ganged  
basis is hardware implementation dependent.  
0 = Ganged switching (all ports together)  
1 = Individual port-by-port switching  
4.2.1.8  
Register 07h: Configuration Data Byte 2  
BIT NAME  
BIT  
NUMBER  
DESCRIPTION  
7
DYNAMIC  
Dynamic Power Enable: Controls the ability of the Hub to automatically  
change from Self-Powered operation to Bus-Powered operation if the local  
power source is removed or is unavailable (and from Bus-Powered to Self-  
Powered if the local power source is restored). {Note: If the local power  
source is available, the Hub will always switch to Self-Powered operation.}  
When Dynamic Power switching is enabled, the Hub detects the availability  
of a local power source by monitoring the external LOCAL_PWR pin. If the  
Hub detects a change in power source availability, the Hub immediately  
disconnects and removes power from all downstream devices and  
disconnects the upstream port. The Hub will then re-attach to the upstream  
port as either a Bus-Powered Hub (if local-power is unavailable) or a Self-  
Powered Hub (if local power is available).  
0 = No Dynamic auto-switching  
1 = Dynamic Auto-switching capable  
6
Reserved  
Reserved  
5:4  
OC_TIMER  
OverCurrent Timer: Over-current Timer delay.  
00 = 0.1 ms  
01 = 4.0 ms  
10 = 8.0 ms  
11 = 16.0 ms  
3
COMPOUND  
Compound Device: Allows OEM to indicate that the Hub is part of a  
compound (see the USB Specification for definition) device. The  
applicable port(s) must also be defined as having a "Non-Removable  
Device".  
Note:  
When configured via strapping options, declaring a port as non-  
removable automatically causes the hub controller to report that it  
is part of a compound device.  
0 = No  
1 = Yes, Hub is part of a compound device  
2:0  
Reserved  
Reserved  
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4.2.1.9  
Register 08h: Configuration Data Byte 3  
BIT  
NUMBER  
BIT NAME  
DESCRIPTION  
7:4  
3
Reserved  
Reserved  
PRTMAP_EN  
Port Re-mapping enable: Selects the method used by the hub to assign port  
numbers and disable ports.  
‘0’ = Standard Mode  
‘1’ = Port Re-map mode  
Reserved  
2:0  
Reserved  
4.2.1.10  
Register 09h: Non-Removable Device  
BIT NAME  
BIT  
NUMBER  
DESCRIPTION  
7:0  
NR_DEVICE  
Non-removable Device: Indicates which port(s) include non-removable  
devices. ‘0’ = port is removable, ‘1’ = port is non-removable.  
Informs the Host if one of the active ports has a permanent device that is  
undetachable from the Hub. (Note: The device must provide its own  
descriptor data.)  
When using the internal default option, the NON_REM[1:0] pins will  
designate the appropriate ports as being non- removable.  
Bit 7= Reserved, always = ‘0’  
Bit 6= Reserved, always = ‘0’  
Bit 5= Reserved, always = ‘0’  
Bit 4= Reserved, always = ‘0’  
Bit 3= Reserved, always = ‘1’  
Bit 2= 1; Port 2 non-removable  
Bit 1= 1; Port 1 non removable  
Bit 0= Reserved, always = ‘0’  
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4.2.1.11  
Register 0Ah: Port Disable For Self-Powered Operation  
BIT  
NUMBER  
BIT NAME  
DESCRIPTION  
7:0  
PORT_DIS_SP  
Port Disable Self-Powered: Disables 1 or more contiguous ports. ‘0’ = port  
is available, ‘1’ = port is disabled.  
During Self-Powered operation when remapping mode is disabled  
(PRTMAP_EN='0'), this selects the ports which will be permanently  
disabled, and are not available to be enabled or enumerated by a Host  
Controller. The ports can be disabled in any order, the internal logic will  
automatically report the correct number of enabled ports to the USB Host,  
and will reorder the active ports in order to ensure proper function.  
Bit 7= Reserved, always = ‘0’  
Bit 6= Reserved, always = ‘0’  
Bit 5= Reserved, always = ‘0’  
Bit 4= Reserved, always = ‘0’  
Bit 3= Reserved, always = ‘1’  
Bit 2= 1; Port 2 is disabled  
Bit 1= 1; Port 1 is disabled  
Bit 0= Reserved, always = ‘0’  
4.2.1.12  
Register 0Bh: Port Disable For Bus-Powered Operation  
BIT  
NUMBER  
BIT NAME  
DESCRIPTION  
7:0  
PORT_DIS_BP  
Port Disable Bus-Powered: Disables 1 or more contiguous ports. ‘0’ = port  
is available, ‘1’ = port is disabled.  
During Self-Powered operation when remapping mode is disabled  
(PRTMAP_EN='0'), this selects the ports which will be permanently  
disabled, and are not available to be enabled or enumerated by a Host  
Controller. The ports can be disabled in any order, the internal logic will  
automatically report the correct number of enabled ports to the USB Host,  
and will reorder the active ports in order to ensure proper function.  
When using the internal default option, the PRT_DIS[1:0] pins will disable the  
appropriate ports.  
Bit 7= Reserved  
Bit 6= Reserved  
Bit 5= Reserved  
Bit 4= Reserved  
Bit 3= Reserved, always = ‘1’  
Bit 2= 1; Port 2 is disabled  
Bit 1= 1; Port 1 is disabled  
Bit 0 is Reserved, always = ‘0’  
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4.2.1.13  
Register 0Ch: Max Power For Self-Powered Operation  
BIT  
NUMBER  
BIT NAME  
DESCRIPTION  
7:0  
MAX_PWR_SP  
Max Power Self_Powered: Value in 2mA increments that the Hub consumes  
from an upstream port (VBUS) when operating as a self-powered hub. This  
value includes the hub silicon along with the combined power consumption  
(from VBUS) of all associated circuitry on the board. This value also includes  
the power consumption of a permanently attached peripheral if the hub is  
configured as a compound device, and the embedded peripheral reports  
0mA in its descriptors.  
Note:  
The USB 2.0 Specification does not permit this value to exceed  
100mA  
4.2.1.14  
Register 0Dh: Max Power For Bus-Powered Operation  
BIT  
NUMBER  
BIT NAME  
DESCRIPTION  
7:0  
MAX_PWR_BP  
Max Power Bus_Powered: Value in 2mA increments that the Hub consumes  
from an upstream port (VBUS) when operating as a bus-powered hub. This  
value includes the hub silicon along with the combined power consumption  
(from VBUS) of all associated circuitry on the board. This value also includes  
the power consumption of a permanently attached peripheral if the hub is  
configured as a compound device, and the embedded peripheral reports  
0mA in its descriptors.  
4.2.1.15  
Register 0Eh: Hub Controller Max Current For Self-Powered Operation  
BIT  
NUMBER  
BIT NAME  
DESCRIPTION  
7:0  
HC_MAX_C_SP  
Hub Controller Max Current Self-Powered: Value in 2mA increments that the  
Hub consumes from an upstream port (VBUS) when operating as a self-  
powered hub. This value includes the hub silicon along with the combined  
power consumption (from VBUS) of all associated circuitry on the board.  
This value does NOT include the power consumption of a permanently  
attached peripheral if the hub is configured as a compound device.  
Note:  
The USB 2.0 Specification does not permit this value to exceed  
100mA  
A value of 50 (decimal) indicates 100mA, which is the default value.  
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4.2.1.16  
Register 0Fh: Hub Controller Max Current For Bus-Powered Operation  
BIT  
NUMBER  
BIT NAME  
DESCRIPTION  
7:0  
HC_MAX_C_BP  
Hub Controller Max Current Bus-Powered: Value in 2mA increments that the  
Hub consumes from an upstream port (VBUS) when operating as a bus-  
powered hub. This value will include the hub silicon along with the combined  
power consumption (from VBUS) of all associated circuitry on the board.  
This value will NOT include the power consumption of a permanently  
attached peripheral if the hub is configured as a compound device.  
A value of 50 (decimal) would indicate 100mA, which is the default value.  
4.2.1.17  
Register 10h: Power-On Time  
BIT NAME  
BIT  
NUMBER  
DESCRIPTION  
7:0  
POWER_ON_TIME  
Power-On Time: The length of time that it takes (in 2 ms intervals) from the  
time the host initiated power-on sequence begins on a port until power is  
adequate on that port.  
4.2.1.18  
Register F6h: Boost_Up  
BIT NAME  
BIT  
NUMBER  
DESCRIPTION  
7:2  
1:0  
Reserved  
Reserved  
BOOST_IOUT  
USB electrical signaling drive strength Boost Bit for the Upstream Port.  
‘00’ = Normal electrical drive strength = No boost  
‘01’ = Elevated electrical drive strength = Low (approximately 4% boost)  
‘10’ = Elevated electrical drive strength = Medium (approximately 8% boost)  
‘11’ = Elevated electrical drive strength = High (approximately 12% boost)  
Note:  
“Boost” could result in non-USB Compliant parameters (one  
example would be Test J/K levels), OEM should use a ‘00’ value  
unless specific implementation issues require additional signal  
boosting to correct for degraded USB signalling levels.  
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4.2.1.19  
Register F8h: Boost_2:0  
BIT NAME  
BIT  
NUMBER  
DESCRIPTION  
7:4  
3:2  
Reserved  
Reserved  
BOOST_IOUT_2  
USB electrical signaling drive strength Boost Bit for Downstream Port ‘2’.  
‘00’ = Normal electrical drive strength = No boost  
‘01’ = Elevated electrical drive strength = Low (approximately 4% boost)  
‘10’ = Elevated electrical drive strength = Medium (approximately 8% boost)  
‘11’ = Elevated electrical drive strength = High (approximately 12% boost)  
Note:  
“Boost” could result in non-USB Compliant parameters (one  
example would be Test J/K levels), OEM should use a ‘00’ value  
unless specific implementation issues require additional signal  
boosting to correct for degraded USB signalling levels.  
1:0  
BOOST_IOUT_1  
USB electrical signaling drive strength Boost Bit for Downstream Port ‘1’.  
‘00’ = Normal electrical drive strength = No boost  
‘01’ = Elevated electrical drive strength = Low (approximately 4% boost)  
‘10’ = Elevated electrical drive strength = Medium (approximately 8% boost)  
‘11’ = Elevated electrical drive strength = High (approximately 12% boost)  
Note:  
“Boost” could result in non-USB Compliant parameters (one  
example would be Test J/K levels), OEM should use a ‘00’ value  
unless specific implementation issues require additional signal  
boosting to correct for degraded USB signalling levels.  
4.2.1.20  
Register FAh: Port Swap  
BIT NAME  
BIT  
NUMBER  
DESCRIPTION  
7:0  
PRTSP  
Port Swap: Swaps the Upstream and Downstream USB DP and DM Pins for  
ease of board routing to devices and connectors.  
‘0’ = USB D+ functionality is associated with the DP pin and D- functionality  
is associated with the DM pin.  
‘1’ = USB D+ functionality is associated with the DM pin and D- functionality  
is associated with the DP pin.  
Bit 7= Reserved  
Bit 6= Reserved  
Bit 5= Reserved  
Bit 4= Reserved  
Bit 3= Reserved  
Bit 2= ‘1’; Port 2 DP/DM is Swapped.  
Bit 1= ‘1’: Port 1 DP/DM is Swapped.  
Bit 0= ‘1’:Upstream Port DP/DM is Swapped  
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4.2.1.21  
Register FBh: Port Remap 12  
BIT NAME  
BIT  
NUMBER  
DESCRIPTION  
7:0  
PRTR12  
Port remap register for ports 1 & 2.  
When a hub is enumerated by a USB Host Controller, the hub is only  
permitted to report how many ports it has; the hub is not permitted to select  
a numerical range or assignment. The Host Controller will number the  
downstream ports of the hub starting with the number '1', up to the number  
of ports that the hub reported having.  
The host's port number is referred to as "Logical Port Number" and the  
physical port on the hub is the “Physical Port Number". When remapping  
mode is enabled (see PRTMAP_EN in Register 08h: Configuration Data  
Byte 3) the hub's downstream port numbers can be remapped to different  
logical port numbers (assigned by the host).  
Note:  
OEM must ensure that Contiguous Logical Port Numbers are used,  
starting from #1 up to the maximum number of enabled ports; this  
ensures that the hub's ports are numbered in accordance with the  
way a Host will communicate with the ports.  
Table 4.2 Port Remap Register for Ports 1 & 2  
Bit [7:4]  
‘0000’  
‘0001’  
‘0010’  
Physical Port 2 is Disabled  
Physical Port 2 is mapped to Logical Port 1  
Physical Port 2 is mapped to Logical Port 2  
Illegal; Do Not Use  
‘0011’  
to  
‘1111’  
Bit [3:0]  
‘0000’  
‘0001’  
‘0010’  
Physical Port 1 is Disabled  
Physical Port 1 is mapped to Logical Port 1  
Physical Port 1 is mapped to Logical Port 2  
Illegal; Do Not Use  
‘0011’  
to  
‘1111’  
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4.2.1.22  
Register FFh: Status/Command  
BIT NAME  
BIT  
NUMBER  
DESCRIPTION  
7:3  
2
Reserved  
Reserved  
INTF_PW_DN  
SMBus Interface Power Down  
‘0’ = Interface is active  
‘1’ = Interface power down after ACk has completed  
1
0
RESET  
Reset the SMBus Interface and internal memory back to RESET_N  
assertion default settings.  
‘0’ = Normal Run/Idle State  
‘1’ = Force a reset of registers to their default state  
USB_ATTACH  
USB Attach (and write protect)  
‘0’ = SMBus slave interface is active  
‘1’ = Hub will signal a USB attach event to an upstream device, and the  
internal memory (address range 00h-FEh) is “write-protected” to prevent  
unintentional data corruption.  
2
4.2.2  
I C EEPROM  
2
2
The I C EEPROM interface implements a subset of the I C Master Specification (Please refer to the  
2
2
2
Philips Semiconductor Standard I C-Bus Specification for details on I C bus protocols). The Hub’s I C  
EEPROM interface is designed to attach to a single “dedicated” I C EEPROM, and it conforms to the  
Standard-mode I C Specification (100kbit/s transfer rate and 7-bit addressing) for protocol and  
2
2
electrical compatibility.  
2
Note: Extensions to the I C Specification are not supported.  
The Hub acts as the master and generates the serial clock SCL, controls the bus access (determines  
which device acts as the transmitter and which device acts as the receiver), and generates the START  
and STOP conditions.  
4.2.2.1  
4.2.2.2  
Implementation Characteristics  
The Hub will only access an EEPROM using the Sequential Read Protocol.  
Pull-Up Resistor  
The Circuit board designer is required to place external pull-up resistors (10KΩ recommended) on the  
SDA/SMBDATA & SCL/SMBCLK/CFG_SELO lines (per SMBus 1.0 Specification, and EEPROM  
manufacturer guidelines) to Vcc in order to assure proper operation.  
2
4.2.2.3  
I C EEPROM Slave Address  
Slave address is 1010000.  
Note: 10-bit addressing is NOT supported.  
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4.2.3  
In-Circuit EEPROM Programming  
The EEPROM can be programmed via ATE by pulling RESET_N low (which tri-states the Hub’s  
EEPROM interface and allows an external source to program the EEPROM).  
4.3  
SMBus Slave Interface  
Instead of loading User-Defined Descriptor data from an external EEPROM, the SMSC Hub can be  
configured to receive a code load from an external processor via an SMBus interface. The SMBus  
interface shares the same pins as the EEPROM interface; if CFG_SEL1 & CFG_SEL0 activates the  
SMBus interface, external EEPROM support is no longer available (and the user-defined descriptor  
data must be downloaded via the SMBus). Due to system issues, the SMSC Hub waits indefinitely for  
the SMBus code load to complete and only “appears” as a newly connected device on USB after the  
code load is complete.  
The Hub’s SMBus implementation is a subset of the SMBus interface to the host. The device is a  
slave-only SMBus device. The implementation in the device is a subset of SMBus since it only supports  
two protocols.  
The Write Block and Read Block protocols are the only valid SMBus protocols for the Hub. The Hub  
responds to other protocols as described in Section 4.3.2, "Invalid Protocol Response Behavior," on  
page 26. Reference the System Management Bus Specification, Rev 1.0.  
The SMBus interface is used to read and write the registers in the device. The register set is shown  
in Section 4.2.1, "Internal Register Set (Common to EEPROM and SMBus)," on page 13.  
4.3.1  
Bus Protocols  
Typical Write Block and Read Block protocols are shown below. Register accesses are performed  
using 7-bit slave addressing, an 8-bit register address field, and an 8-bit data field. The shading  
indicates the Hub driving data on the SMBDATA line; otherwise, host data is on the SDA/SMBDATA  
line.  
The slave address is the unique SMBus Interface Address for the Hub that identifies it on SMBus. The  
register address field is the internal address of the register to be accessed. The register data field is  
the data that the host is attempting to write to the register or the contents of the register that the host  
is attempting to read.  
Note: Data bytes are transferred MSB first (msb first).  
4.3.1.1  
Block Read/Write  
The Block Write begins with a slave address and a write condition. After the command code, the host  
issues a byte count which describes how many more bytes will follow in the message. If a slave had  
20 bytes to send, the first byte would be the number 20 (14h), followed by the 20 bytes of data. The  
byte count may not be 0. A Block Read or Write is allowed to transfer a maximum of 32 data bytes.  
Note: For the following SMBus tables:  
Denotes Master-to-Slave  
Denotes Slave-to-Master  
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1
7
1
1
8
1
S
Slave Address  
Wr  
A
Register Address  
A
...  
8
1
8
1
8
1
8
1
1
Byte Count = N  
A
Data byte 1  
A
Data byte 2  
A
Data byte N  
A
P
Block Write  
Figure 4.1 Block Write  
Block Read  
2
A Block Read differs from a block write in that the repeated start condition exists to satisfy the I C  
specification’s requirement for a change in the transfer direction.  
1
7
1
1
8
1
1
7
1
1
S
Slave Address  
Wr  
A
Register Address  
A
S
Slave Address Rd  
A
...  
8
1
8
1
8
1
8
1
1
Byte Count = N  
A
Data byte 1  
A
Data byte 2  
A
Data byte N  
A
P
Block Read  
Figure 4.2 Block Read  
4.3.2  
Invalid Protocol Response Behavior  
Registers that are accessed with an invalid protocol are not updated. A register is only updated  
following a valid protocol. The only valid protocols are Write Block and Read Block, which are  
described above.  
The Hub only responds to the hardware selected Slave Address.  
Attempting to communicate with the Hub over SMBus with an invalid slave address or invalid protocol  
results in no response, and the SMBus Slave Interface returns to the idle state.  
The only valid registers that are accessible by the SMBus slave address are the registers defined in  
the Registers Section. See Section 4.3.3 for the response to undefined registers.  
4.3.3  
4.3.4  
General Call Address Response  
The Hub does not respond to a general call address of 0000_000b.  
Slave Device Time-Out  
According to the SMBus Specification, V1.0 devices in a transfer can abort the transfer in progress  
and release the bus when any single clock low interval exceeds 25ms (T  
). Devices that  
TIMEOUT, MIN  
have detected this condition must reset their communication and be able to receive a new START  
condition no later than 35ms (T ).  
TIMEOUT, MAX  
Note: Some simple devices do not contain a clock low drive circuit; this simple kind of device typically  
resets its communications port after a start or stop condition. The Slave Device Time-Out must  
be implemented.  
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4.3.5  
4.3.6  
4.3.7  
Stretching the SCLK Signal  
The Hub supports stretching of the SCLK by other devices on the SMBus. The Hub does not stretch  
the SCLK.  
SMBus Timing  
The SMBus Slave Interface complies with the SMBus AC Timing Specification. See the SMBus timing  
in the “Timing Diagram” section.  
Bus Reset Sequence  
The SMBus Slave Interface resets and returns to the idle state upon a START field followed  
immediately by a STOP field.  
4.3.8  
SMBus Alert Response Address  
The SMBALERT# signal is not supported by the Hub.  
4.3.8.1  
Undefined Registers  
The registers shown in Table 4.1 are the defined registers in the Hub. Reads to undefined registers  
return 00h. Writes to undefined registers have no effect and do not return an error.  
4.3.8.2  
Reserved Registers  
Unless otherwise instructed, only a ‘0’ may be written to all reserved registers or bits.  
4.4  
Default Configuration Option:  
The SMSC Hub can be configured via its internal default configuration. (please see Section 4.2.1,  
"Internal Register Set (Common to EEPROM and SMBus)" for specific details on how to enable default  
configuration.)  
Please refer to Table 4.1 for the internal default values that are loaded when this option is selected.  
4.5  
Default Strapping Options:  
The USB2512Ai can be configured via a combination of internal default values and pin strap options.  
Please see Table 3.1 and Table 3.2 for specific details on how to enable the default/pin-strap  
configuration option.  
The strapping option pins only cover a limited sub-set of the configuration options. The internal default  
values will be used for the bits & registers that are not controlled by a strapping option pin. Please  
refer to Table 4.1 for the internal default values that are loaded when this option is selected.  
4.6  
Reset  
There are two different resets that the Hub experiences. One is a hardware reset (either from the  
internal POR reset circuit or via the RESET_N pin) and the second is a USB Bus Reset.  
4.6.1  
Internal POR Hardware Reset  
All reset timing parameters are guaranteed by design.  
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4.6.2  
External Hardware RESET_N  
A valid hardware reset is defined as assertion of RESET_N for a minimum of 1us after all power  
supplies are within operating range. While reset is asserted, the Hub (and its associated external  
circuitry) consumes less than 500μA of current from the upstream USB power source.  
Assertion of RESET_N (external pin) causes the following:  
1. All downstream ports are disabled, and PRTPWR power to downstream devices is removed.  
2. The PHYs are disabled, and the differential pairs will be in a high-impedance state.  
3. All transactions immediately terminate; no states are saved.  
4. All internal registers return to the default state (in most cases, 00(h)).  
5. The external crystal oscillator is halted.  
6. The PLL is halted.  
The Hub is “operational” 500μs after RESET_N is negated.  
Once operational, the Hub immediately reads OEM-specific data from the external EEPROM (if the  
SMBus option is not disabled).  
4.6.2.1  
RESET_N for Strapping Option Configuration  
Drive Strap  
Outputs to  
inactive  
Start  
completion  
request  
Hardware  
reset  
asserted  
Attach  
USB  
Upstream  
Read Strap  
Options  
USB Reset  
recovery  
Idle  
levels  
response  
t7  
t8  
t1  
t2  
t5  
t6  
t3  
RESET_N  
VSS  
t4  
Strap Pins  
VSS  
Don’t Care  
Valid  
Driven by Hub if strap is an output.  
Don’t Care  
Figure 4.3 Reset_N Timing for Default/Strap Option Mode  
Table 4.3 Reset_N Timing for Default/Strap Option Mode  
NAME  
DESCRIPTION  
MIN  
TYP  
MAX  
UNITS  
t1  
t2  
t3  
t4  
t5  
t6  
RESET_N Asserted.  
1
μsec  
nsec  
nsec  
μsec  
msec  
msec  
Strap Setup Time  
16.7  
16.7  
Strap Hold Time.  
1400  
2
hub outputs driven to inactive logic states  
USB Attach (See Note).  
1.5  
100  
Host acknowledges attach and signals USB  
Reset.  
100  
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Table 4.3 Reset_N Timing for Default/Strap Option Mode (continued)  
NAME  
DESCRIPTION  
MIN  
TYP  
MAX  
UNITS  
t7  
t8  
USB Idle.  
undefined  
msec  
msec  
Completion time for requests (with or without data  
stage).  
5
Notes:  
„
When in Bus-Powered mode, the Hub and its associated circuitry must not consume more than  
100mA from the upstream USB power source during t1+t5.  
„
All Power Supplies must have reached the operating levels mandated in Chapter 5, DC  
Parameters, prior to (or coincident with) the assertion of RESET_N.  
4.6.2.2  
RESET_N for EEPROM Configuration  
Start  
completion  
request  
Hardware  
Read EEPROM  
+
Set Options  
Attach  
USB  
Upstream  
Read Strap  
Options  
USB Reset  
recovery  
reset  
asserted  
Idle  
response  
t4  
t1  
t5  
t6  
t7  
t2  
t3  
RESET_N  
VSS  
Figure 4.4 Reset_N Timing for EEPROM Mode  
Table 4.4 Reset_N Timing for EEPROM Mode  
NAME  
DESCRIPTION  
MIN  
TYP  
MAX  
UNITS  
t1  
t2  
t3  
t4  
t5  
RESET_N Asserted.  
1
μsec  
μsec  
msec  
msec  
msec  
Hub Recovery/Stabilization.  
EEPROM Read / Hub Config.  
USB Attach (See Note).  
500  
99.5  
100  
2.0  
Host acknowledges attach and signals USB  
Reset.  
100  
t6  
t7  
USB Idle.  
undefined  
msec  
msec  
Completion time for requests (with or without data  
stage).  
5
Notes:  
„
When in Bus-Powered mode, the Hub and its associated circuitry must not consume more than  
100mA from the upstream USB power source during t4+t5+t6+t7.  
„
All Power Supplies must have reached the operating levels mandated in Chapter 5, DC  
Parameters, prior to (or coincident with) the assertion of RESET_N.  
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4.6.2.3  
RESET_N for SMBus Slave Configuration  
Start  
completion  
request  
Hardware  
reset  
asserted  
Attach  
USB  
Upstream  
Reset  
SMBus Code  
Load  
Hub PHY  
USB Reset  
recovery  
Idle  
Negation  
Stabilization  
response  
t6  
t7  
t1  
t5  
t2  
t3  
t4  
RESET_N  
VSS  
Figure 4.5 Reset_N Timing for SMBus Mode  
Table 4.5 Reset_N Timing for SMBus Mode  
NAME  
DESCRIPTION  
MIN  
TYP  
MAX  
UNITS  
t1  
t2  
t3  
t4  
t5  
RESET_N Asserted.  
1
μsec  
μsec  
msec  
msec  
msec  
Hub Recovery/Stabilization.  
SMBus Code Load (See Note).  
Hub Configuration and USB Attach.  
500  
300  
100  
250  
Host acknowledges attach and signals USB  
Reset.  
100  
t6  
t7  
USB Idle.  
Undefined  
msec  
msec  
Completion time for requests (with or without data  
stage).  
5
Notes:  
„
For Bus-Powered configurations, the 99.5ms (MAX) is required, and the Hub and its associated  
circuitry must not consume more than 100mA from the upstream USB power source during  
t2+t3+t4+t5+t6+t7. For Self-Powered configurations, t3 MAX is not applicable and the time to load  
the configuration is determined by the external SMBus host.  
„
All Power Supplies must have reached the operating levels mandated in Chapter 5, DC  
Parameters, prior to (or coincident with) the assertion of RESET_N.  
4.6.3  
USB Bus Reset  
In response to the upstream port signaling a reset to the Hub, the Hub does the following:  
Note: The Hub does not propagate the upstream USB reset to downstream devices.  
1. Sets default address to 0.  
2. Sets configuration to: Unconfigured.  
3. Negates PRTPWR[2:1] to all downstream ports.  
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4. Clears all TT buffers.  
5. Moves device from suspended to active (if suspended).  
6. Complies with Section 11.10 of the USB 2.0 Specification for behavior after completion of the reset  
sequence.  
The Host then configures the Hub and the Hub’s downstream port devices in accordance with the USB  
Specification.  
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Chapter 5 DC Parameters  
5.1  
Maximum Guaranteed Ratings  
PARAMETER  
SYMBOL  
MIN  
MAX  
UNITS  
COMMENTS  
Storage  
Temperature  
T
-55  
150  
°C  
STOR  
Lead  
325  
2.5  
4.6  
°C  
V
Soldering < 10 seconds  
Temperature  
1.8V supply  
voltage  
V
DDA18PLL,  
V
DD18  
3.3V supply  
voltage  
V
V
DDA33,  
V
DD33PLL,  
DD33,  
DD33CR  
V
V
Voltage on any  
I/O pin  
-0.5  
-0.5  
-0.5  
5.5  
4.0  
3.6  
V
V
V
Voltage on  
XTAL1  
Voltage on  
XTAL2  
Note 5.1 Stresses above the specified parameters could cause permanent damage to the device.  
This is a stress rating only and functional operation of the device at any condition above  
those indicated in the operation sections of this specification is not implied.  
Note 5.2 When powering this device from laboratory or system power supplies, it is important that  
the Absolute Maximum Ratings not be exceeded or device failure can result. Some power  
supplies exhibit voltage spikes on their outputs when the AC power is switched on or off.  
In addition, voltage transients on the AC power line may appear on the DC output. When  
this possibility exists, it is suggested that a clamp circuit be used.  
Voltage  
tRT  
VDD33  
3.3V  
100%  
90%  
10%  
VSS  
t90%  
Time  
t10%  
Figure 5.1 Supply Rise Time Model  
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5.2  
Operating Conditions  
PARAMETER  
SYMBOL  
MIN  
MAX  
UNITS  
COMMENTS  
Operating  
Temperature  
T
-40  
85  
°C  
Ambient temperature in still air.  
A
1.8V supply voltage  
V
V
1.62  
3.0  
1.98  
3.6  
V
V
DDA18PLL  
DD18  
V
3.3V supply voltage  
V
DDA33  
DDA33PLL  
V
DD33  
V
DD33CR  
3.3V supply rise time  
Voltage on any I/O pin  
t
0
400  
5.5  
μs  
See Figure 5.1  
RT  
-0.3  
V
If any 3.3V supply voltage drops  
below 3.0V, then the MAX  
becomes:  
(3.3V supply voltage) + 0.5  
Voltage on XTAL1  
-0.3  
V
V
DDA33  
Table 5.1 DC Electrical Characteristics  
PARAMETER  
SYMBOL  
MIN  
TYP  
MAX  
UNITS  
COMMENTS  
I, IS Type Input Buffer  
Low Input Level  
V
0.8  
V
V
TTL Levels  
ILI  
IHI  
IL  
High Input Level  
V
I
2.0  
-10  
250  
Input Leakage  
+10  
350  
uA  
mV  
V
= 0 to V  
IN DD33  
Hysteresis (‘IS’ Only)  
V
HYSI  
Input Buffer with Pull-Up  
(IPU)  
Low Input Level  
V
0.8  
V
V
TTL Levels  
ILI  
High Input Level  
Low Input Leakage  
High Input Leakage  
V
2.0  
+35  
-10  
IHI  
I
+90  
+10  
uA  
uA  
V
V
= 0  
= V  
ILL  
IHL  
IN  
I
IN  
DD33  
Input Buffer with Pull-  
Down (IPD)  
Low Input Level  
V
0.8  
V
V
TTL Levels  
ILI  
High Input Level  
Low Input Leakage  
High Input Leakage  
V
2.0  
+10  
-35  
IHI  
I
-10  
-90  
uA  
uA  
V
V
= 0  
= V  
ILL  
IHL  
IN  
I
IN  
DD33  
SMSC USB2512Ai  
Revision 1.97 (08-11-08)  
DATA3S3HEET  
Download from Www.Somanuals.com. All Manuals Search And Download.  
   
Industrial Temperature Rated USB 2.0 Hi-Speed 2-Port Hub Controller  
Datasheet  
Table 5.1 DC Electrical Characteristics (continued)  
PARAMETER  
SYMBOL  
MIN  
TYP  
MAX  
UNITS  
COMMENTS  
ICLK Input Buffer  
Low Input Level  
High Input Level  
Input Leakage  
V
0.5  
V
V
ILCK  
V
1.4  
-10  
IHCK  
I
+10  
uA  
IL  
V
= 0 to V  
DD33  
IN  
O12, I/O12 &I/OSD12  
Type Buffer  
Low Output Level  
V
0.4  
V
V
I
I
= 12mA @ V  
= 3.3V  
OL  
OH  
OL  
OL  
DD33  
High Output Level  
Output Leakage  
V
2.4  
-10  
250  
= -12mA @ V  
= 3.3V  
DD33  
OH  
I
+10  
350  
uA  
mV  
V
= 0 to V  
IN DD33  
(Note 1)  
Hysteresis (‘SD’ pad only)  
V
HYSC  
IO-U  
(Note 2)  
Supply Current  
Unconfigured  
Hi-Speed Host  
Full-Speed Host  
I
75  
65  
85  
75  
mA  
mA  
CCINTHS  
I
CCINITFS  
Supply Current  
Configured  
All supplies combined  
All supplies combined  
(Hi-Speed Host)  
1 Port HS, 1 Port LS/FS  
2 Ports @ LS/FS  
2 Ports @ HS  
I
115  
105  
125  
130  
125  
190  
mA  
mA  
mA  
HCH1C1  
HCC2  
HCH2  
I
I
Supply Current  
Configured  
(Full-Speed Host)  
1 Port  
2 Ports  
I
I
95  
95  
125  
125  
mA  
mA  
FCC1  
FCC2  
Supply Current  
Suspend  
I
300  
100  
500  
200  
μA  
All supplies combined  
All supplies combined  
CSBY  
Supply Current  
Reset  
I
μA  
CRST  
Notes:  
1. Output leakage is measured with the current pins in high impedance.  
2. See USB 2.0 Specification for USB DC electrical characteristics.  
Revision 1.97 (08-11-08)  
SMSC USB2512Ai  
DATA3S4HEET  
Download from Www.Somanuals.com. All Manuals Search And Download.  
Industrial Temperature Rated USB 2.0 Hi-Speed 2-Port Hub Controller  
Datasheet  
CAPACITANCE T = 25°C; fc = 1MHz; V  
, V  
= 1.8V  
DDPLL  
A
DD18  
Table 5.2 Pin Capacitance  
LIMITS  
PARAMETER  
SYMBOL  
MIN  
TYP MAX UNIT  
TEST CONDITION  
Clock Input  
Capacitance  
C
2
pF  
All pins except USB pins (and pins under  
test tied to AC ground)  
XTAL  
Input Capacitance  
Output Capacitance  
C
10  
20  
pF  
pF  
IN  
C
OUT  
SMSC USB2512Ai  
Revision 1.97 (08-11-08)  
DATA3S5HEET  
Download from Www.Somanuals.com. All Manuals Search And Download.  
 
Industrial Temperature Rated USB 2.0 Hi-Speed 2-Port Hub Controller  
Datasheet  
Chapter 6 AC Specifications  
6.1  
Oscillator/Clock  
Crystal: Parallel Resonant, Fundamental Mode, 24 MHz ±350ppm.  
External Clock: 50% Duty cycle ± 10%, 24 MHz ± 350ppm, Jitter < 100ps rms.  
XTAL1  
(CS1 =  
CB + CXTAL  
)
C1  
1Meg  
Crystal  
CL  
C2  
XTAL2  
(CS2 =  
CB + CXTAL  
)
Figure 6.1 Typical Crystal Circuit  
equals total board/trace capacitance.  
Note:  
C
B
(C1 + CS1) x (C2 + CS2)  
(C1 + CS1 + C2 + CS2)  
CL  
=
Figure 6.2 Formula to find value of C and C  
1
2
6.1.1  
SMBus Interface:  
The SMSC Hub conforms to all voltage, power, and timing characteristics and specifications as set  
forth in the SMBus 1.0 Specification for Slave-Only devices (except as noted in Section 4.3).  
2
6.1.2  
6.1.3  
I C EEPROM:  
Clock frequency is fixed at 60KHz ± 20%.  
USB 2.0  
The SMSC Hub conforms to all voltage, power, and timing characteristics and specifications as set  
forth in the USB 2.0 Specification. Please refer to the USB 2.0 Specification for more information.  
Revision 1.97 (08-11-08)  
SMSC USB2512Ai  
DATA3S6HEET  
Download from Www.Somanuals.com. All Manuals Search And Download.  
             
Chapter 7 Package Outline  
Figure 7.1 36-Pin QFN, 6x6mm Body, 0.5mm Pitch  
Download from Www.Somanuals.com. All Manuals Search And Download.  
   

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