PBLS4004D
40 V PNP BISS loadswitch
Rev. 03 — 6 January 2009
Product data sheet
1. Product profile
1.1 General description
PNP low VCEsat Breakthrough In Small Signal (BISS) transistor and NPN Resistor-
Equipped Transistor (RET) in a SOT457 (SC-74) small Surface-Mounted Device (SMD)
plastic package.
1.2 Features
I Low VCEsat (BISS) and resistor-equipped transistor in one package
I Low threshold voltage (< 1 V) compared to MOSFET
I Low drive power required
I Space-saving solution
I Reduction of component count
1.3 Applications
I Supply line switches
I Battery charger switches
I High-side switches for LEDs, drivers and backlights
I Portable equipment
1.4 Quick reference data
Table 1.
Symbol
Quick reference data
Parameter
Conditions
Min
Typ
Max
Unit
TR1; PNP low VCEsat transistor
VCEO
IC
collector-emitter voltage
collector current
open base
-
-
-
-
−40
−1
V
-
A
RCEsat
collector-emitter saturation IC = −500 mA;
resistance
240
340
mΩ
IB = −50 mA
TR2; NPN resistor-equipped transistor
VCEO
IO
collector-emitter voltage
output current
open base
-
-
50
V
-
-
100
28.6
1.2
mA
kΩ
R1
bias resistor 1 (input)
bias resistor ratio
15.4
0.8
22
1
R2/R1
[1] Device mounted on a ceramic Printed-Circuit Board (PCB), Al2O3, standard footprint.
[2] Pulse test: tp ≤ 300 µs; δ ≤0.02.
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PBLS4004D
NXP Semiconductors
40 V PNP BISS loadswitch
Table 5.
Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
Max
250
350
400
Unit
mW
mW
mW
Ptot
total power dissipation
Tamb ≤ 25 °C
-
-
-
TR2; NPN resistor-equipped transistor
VCBO
VCEO
VEBO
VI
collector-base voltage
collector-emitter voltage
emitter-base voltage
input voltage
open emitter
open base
-
-
-
50
50
10
V
V
V
open collector
positive
-
-
-
-
-
+40
−10
100
100
200
V
negative
V
IO
output current
mA
mA
mW
ICM
peak collector current
total power dissipation
single pulse; tp ≤ 1 ms
Ptot
Tamb ≤ 25 °C
Per device
Ptot
total power dissipation
Tamb ≤ 25 °C
-
400
mW
mW
mW
°C
-
530
-
600
Tj
junction temperature
ambient temperature
storage temperature
-
150
Tamb
Tstg
−65
−65
+150
+150
°C
°C
[1] Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint.
[2] Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for collector 1 cm2.
[3] Device mounted on a ceramic PCB, Al2O3, standard footprint.
PBLS4004D_3
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Product data sheet
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PBLS4004D
NXP Semiconductors
40 V PNP BISS loadswitch
006aaa461
0.8
P
tot
(W)
(1)
(2)
0.6
(3)
0.4
0.2
0
0
40
80
120
160
(°C)
T
amb
(1) Ceramic PCB, Al2O3, standard footprint
(2) FR4 PCB, mounting pad for collector 1 cm2
(3) FR4 PCB, standard footprint
Fig 1. Power derating curves
6. Thermal characteristics
Table 6.
Thermal characteristics
Symbol
Per device
Rth(j-a)
Parameter
Conditions
Min
Typ Max Unit
thermal resistance from
junction to ambient
in free air
-
-
-
-
-
-
312
236
210
K/W
K/W
K/W
Per TR1; PNP low VCEsat transistor
Rth(j-sp)
thermal resistance from
junction to solder point
-
-
105
K/W
[1] Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint.
[2] Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for collector 1 cm2.
[3] Device mounted on a ceramic PCB, Al2O3, standard footprint.
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Product data sheet
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PBLS4004D
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40 V PNP BISS loadswitch
006aaa462
3
10
δ = 1
Z
th(j-a)
0.75
0.5
0.33
0.2
(K/W)
2
10
0.1
0.05
0.02
0.01
10
0
1
−1
10
10
−5
−4
−3
−2
−1
2
3
10
10
10
10
1
10
10
10
t
(s)
p
FR4 PCB, standard footprint
Fig 2. TR1 (PNP): Transient thermal impedance from junction to ambient as a function of pulse duration; typical
values
006aaa463
3
10
Z
th(j-a)
δ = 1
0.75
(K/W)
0.5
0.33
0.2
2
10
0.1
0.05
10
0.02
0.01
0
1
10
−5
−4
−3
−2
−1
2
3
10
10
10
10
1
10
10
10
t
(s)
p
FR4 PCB, mounting pad for collector 1 cm2
Fig 3. TR1 (PNP): Transient thermal impedance from junction to ambient as a function of pulse duration; typical
values
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PBLS4004D
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40 V PNP BISS loadswitch
006aaa464
3
10
Z
th(j-a)
δ = 1
0.75
(K/W)
0.5
0.33
0.2
2
10
0.1
0.05
10
0.02
0.01
0
1
10
−5
−4
−3
−2
−1
2
3
10
10
10
10
1
10
10
10
t
(s)
p
Ceramic PCB, Al2O3, standard footprint
Fig 4. TR1 (PNP): Transient thermal impedance from junction to ambient as a function of pulse duration; typical
values
7. Characteristics
Table 7.
Characteristics
Tamb = 25 °C unless otherwise specified.
Symbol Parameter
Conditions
Min Typ
Max
Unit
TR1; PNP low VCEsat transistor
ICBO
collector-base cut-off VCB = −40 V; IE = 0 A
-
-
-
-
−0.1
µA
current
VCB = −40 V; IE = 0 A;
Tj = 150 °C
−50
µA
ICES
IEBO
hFE
collector-emitter
cut-off current
VCE = −30 V; VBE = 0 V
-
-
-
-
−0.1
µA
emitter-base cut-off
current
VEB = −5 V; IC = 0 A
−0.1
µA
DC current gain
VCE = −5 V; IC = −1 mA
VCE = −5 V; IC = −100 mA
VCE = −5 V; IC = −500 mA
VCE = −5 V; IC = −1 A
300
-
-
300
-
800
215
-
-
-
150
-
VCEsat
collector-emitter
saturation voltage
IC = −100 mA; IB = −1 mA
IC = −500 mA; IB = −50 mA
IC = −1 A; IB = −100 mA
IC = −500 mA; IB = −50 mA
-
-
-
-
−80
−120
−220
240
−140 mV
−170 mV
−310 mV
RCEsat
VBEsat
VBEon
collector-emitter
saturation resistance
340
−1.1
−1
mΩ
base-emitter
saturation voltage
IC = −1 A; IB = −50 mA
-
-
-
-
V
base-emitter
turn-on voltage
VCE = −5 V; IC = −1 A
V
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40 V PNP BISS loadswitch
Table 7.
Characteristics …continued
Tamb = 25 °C unless otherwise specified.
Symbol Parameter Conditions
Min Typ
Max
Unit
fT
transition frequency
IC = −50 mA; VCE = −10 V;
f = 100 MHz
150
-
-
MHz
Cc
collector capacitance VCB = −10 V; IE = ie = 0 A;
-
-
12
pF
nA
f = 1 MHz
TR2; NPN resistor-equipped transistor
ICBO collector-base cut-off VCB = 50 V; IE = 0 A
-
-
100
current
ICEO
collector-emitter
cut-off current
VCE = 30 V; IB = 0 A
-
-
-
-
1
µA
VCE = 30 V; IB = 0 A;
Tj = 150 °C
50
µA
IEBO
emitter-base cut-off
current
VEB = 5 V; IC = 0 A
-
-
180
µA
hFE
DC current gain
VCE = 5 V; IC = 5 mA
60
-
-
-
-
VCEsat
collector-emitter
IC = 10 mA; IB = 0.5 mA
150
mV
saturation voltage
VI(off)
VI(on)
R1
off-state input voltage VCE = 5 V; IC = 100 µA
on-state input voltage VCE = 0.3 V; IC = 5 mA
bias resistor 1 (input)
-
1.1
1.7
0.8
-
V
2.5
V
15.4 22
28.6
1.2
2.5
kΩ
R2/R1
Cc
bias resistor ratio
0.8
-
1
-
collector capacitance VCB = 10 V; IE = ie = 0 A;
f = 1 MHz
pF
[1] Pulse test: tp ≤ 300 µs; δ ≤0.02.
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PBLS4004D
NXP Semiconductors
40 V PNP BISS loadswitch
006aaa465
006aaa469
1200
−2.4
I
(mA) = −24
I
B
C
h
FE
−21.6
(A)
−19.2
−16.8
−14.4
−12
800
−1.6
(1)
(2)
−9.6
−7.2
−4.8
400
−0.8
−2.4
(3)
0
−10
0
−1
2
3
4
−1
−10
−10
−10
−10
(mA)
0
−1
−2
−3
−4
−5
(V)
CE
I
V
C
VCE = −5 V
Tamb = 25 °C
(1) Tamb = 100 °C
(2) Tamb = 25 °C
(3) Tamb = −55 °C
Fig 5. TR1 (PNP): DC current gain as a function of
collector current; typical values
Fig 6. TR1 (PNP): Collector current as a function of
collector-emitter voltage; typical values
006aaa467
006aaa468
−1.0
−1.3
V
(V)
BE
V
BEsat
(V)
−0.8
(1)
(2)
−0.9
−0.5
−0.1
(1)
(2)
(3)
−0.6
−0.4
−0.2
(3)
−1
2
3
4
−1
2
3
4
−10
−1
−10
−10
−10
−10
(mA)
−10
−1
−10
−10
−10
−10
(mA)
I
I
C
C
VCE = −5 V
IC/IB = 20
(1) Tamb = −55 °C
(2) Tamb = 25 °C
(3) Tamb = 100 °C
(1) Tamb = −55 °C
(2) Tamb = 25 °C
(3) Tamb = 100 °C
Fig 7. TR1 (PNP): Base-emitter voltage as a function
of collector current; typical values
Fig 8. TR1 (PNP): Base-emitter saturation voltage as
a function of collector current; typical values
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PBLS4004D
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40 V PNP BISS loadswitch
006aaa466
006aaa471
−1
−10
V
CEsat
(V)
V
CEsat
−1
(V)
−1
−1
−10
−10
−10
−10
(1)
(2)
(1)
(2)
−2
(3)
(3)
−2
−3
−10
−10
−1
2
3
4
−1
2
3
4
−10
−1
−10
−10
−10
−10
−1
−10
−10
−10
−10
(mA)
I
(mA)
I
C
C
IC/IB = 20
Tamb = 25 °C
(1) Tamb = 100 °C
(2) Tamb = 25 °C
(3) Tamb = −55 °C
(1) IC/IB = 100
(2) IC/IB = 50
(3) IC/IB = 10
Fig 9. TR1 (PNP): Collector-emitter saturation
voltage as a function of collector current;
typical values
Fig 10. TR1 (PNP): Collector-emitter saturation
voltage as a function of collector current;
typical values
006aaa470
006aaa472
3
3
10
10
R
CEsat
R
CEsat
(Ω)
(Ω)
2
2
10
10
(1)
(2)
(3)
10
10
(1)
(2)
1
1
(3)
−1
−10
−1
−10
10
10
−1
2
3
4
−1
2
3
4
−1
−10
−10
−10
−10
(mA)
−1
−10
−10
−10
−10
(mA)
I
I
C
C
IC/IB = 20
Tamb = 25 °C
(1) Tamb = 100 °C
(2) Tamb = 25 °C
(3) Tamb = −55 °C
(1) IC/IB = 100
(2) IC/IB = 50
(3) IC/IB = 10
Fig 11. TR1 (PNP): Collector-emitter saturation
resistance as a function of collector current;
typical values
Fig 12. TR1 (PNP): Collector-emitter saturation
resistance as a function of collector current;
typical values
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PBLS4004D
NXP Semiconductors
40 V PNP BISS loadswitch
006aaa038
006aaa039
3
−1
10
10
h
FE
(1)
(2)
(1)
(2)
(3)
V
CEsat
(V)
2
10
(3)
10
−2
1
10
10
−1
2
2
1
10
10
1
10
10
I
(mA)
I
(mA)
C
C
VCE = 5 V
IC/IB = 20
(1) Tamb = 150 °C
(2) Tamb = 25 °C
(3) Tamb = −40 °C
(1) Tamb = 100 °C
(2) Tamb = 25 °C
(3) Tamb = −40 °C
Fig 13. TR2 (NPN): DC current gain as a function of
collector current; typical values
Fig 14. TR2 (NPN): Collector-emitter saturation
voltage as a function of collector current;
typical values
006aaa040
006aaa041
10
10
V
I(on)
V
I(off)
(V)
(V)
(1)
(2)
(1)
(2)
(3)
1
1
(3)
−1
10
−1
10
10
10
−1
2
−2
−1
1
1
10
10
10
1
10
I
(mA)
I
(mA)
C
C
VCE = 0.3 V
VCE = 5 V
(1) Tamb = −40 °C
(2) Tamb = 25 °C
(3) Tamb = 100 °C
(1) Tamb = −40 °C
(2) Tamb = 25 °C
(3) Tamb = 100 °C
Fig 15. TR2 (NPN): On-state input voltage as a
function of collector current; typical values
Fig 16. TR2 (NPN): Off-state input voltage as a
function of collector current; typical values
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40 V PNP BISS loadswitch
8. Package outline
3.1
2.7
1.1
0.9
6
5
4
0.6
0.2
3.0 1.7
2.5 1.3
pin 1 index
1
2
3
0.26
0.10
0.40
0.25
0.95
1.9
Dimensions in mm
04-11-08
Fig 17. Package outline SOT457 (SC-74)
9. Packing information
Table 8.
Packing methods
Type number Package
Description
Packing quantity
3000
-115
-125
10000
-135
PBLS4004D
SOT457
4 mm pitch, 8 mm tape and reel; T1
4 mm pitch, 8 mm tape and reel; T2
-165
[2] T1: normal taping
[3] T2: reverse taping
PBLS4004D_3
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40 V PNP BISS loadswitch
10. Soldering
3.45
1.95
0.55
(6×)
solder lands
solder resist
0.45
(6×)
0.95
0.95
3.3 2.825
solder paste
occupied area
0.7
Dimensions in mm
(6×)
0.8
(6×)
2.4
sot457_fr
Fig 18. Reflow soldering footprint SOT457 (SC-74)
5.3
1.5
(4×)
solder lands
1.475
1.475
solder resist
occupied area
0.45
(2×)
5.05
Dimensions in mm
preferred transport
direction during soldering
1.45
(6×)
2.85
sot457_fw
Fig 19. Wave soldering footprint SOT457 (SC-74)
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40 V PNP BISS loadswitch
11. Revision history
Table 9.
Revision history
Document ID
PBLS4004D_3
Modifications:
Release date
Data sheet status
Change notice
Supersedes
20090106
Product data sheet
-
PBLS4004D_2
• The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
PBLS4004D_2
PBLS4004D_1
20050719
Product data sheet
-
-
PBLS4004D_1
-
20041109
Objective data sheet
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40 V PNP BISS loadswitch
12. Legal information
12.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
12.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
12.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
12.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
13. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
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40 V PNP BISS loadswitch
14. Contents
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For sales office addresses, please send an email to: [email protected]
Date of release: 6 January 2009
Document identifier: PBLS4004D_3
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