LPC2917/19
ARM9 microcontroller with CAN and LIN
Rev. 1.01 — 15 November 2007
Preliminary data sheet
1. Introduction
1.1 About this document
This document lists detailed information about the LPC2917/19 device. It focuses on
factual information like pinning, characteristics etc. Short descriptions are used to outline
the concept of the features and functions. More details and background on developing
explicit references are made to the User Manual.
1.2 Intended audience
This document is written for engineers evaluating and/or developing systems, hard-
and/or software for the LPC2917/19. Some basic knowledge of ARM processors and
2. General description
2.1 Architectural overview
The LPC2917/19 consists of:
• An ARM968E-S processor with real-time emulation support
• An AMBA multi-layer Advanced High-performance Bus (AHB) for interfacing to the
on-chip memory controllers
• Two DTL buses (a universal NXP interface) for interfacing to the interrupt controller
and the Power, Clock and Reset Control cluster (also called subsystem)
• Three VLSI Peripheral Buses (VPB - a compatible superset of ARM's AMBA
advanced peripheral bus) for connection to on-chip peripherals clustered in
subsystems.
The LPC2917/19 configures the ARM968E-S processor in little-endian byte order. All
peripherals run at their own clock frequency to optimize the total system power
consumption. The AHB2VPB bridge used in the subsystems contains a write-ahead buffer
one transaction deep. This implies that when the ARM968E-S issues a buffered write
action to a register located on the VPB side of the bridge, it continues even though the
actual write may not yet have taken place. Completion of a second write to the same
subsystem will not be executed until the first write is finished.
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LPC2917/19
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
2.4 On-chip static RAM
In addition to the two 16 kB TCMs the LPC2917/19 includes two static RAM memories:
one of 32 kB and one of 16 kB. Both may be used for code and/or data storage. Each
internal SRAM has its own controller, so both memories can be accessed simultaneously
from different AHB system bus layers.
3. Features
3.1 General
„ ARM968E-S processor at 80 MHz maximum
„ Multi-layer AHB system bus at 80 MHz with three separate layers
„ On-chip memory:
‹ Two Tightly Coupled Memories (TCM), 16 kB Instruction (ITCM), 16 kB Data TCM
(DTCM)
‹ Two separate internal Static RAM (SRAM) instances; 32 kB SRAM and 16 kB
SRAM
‹ Up to 768 kB flash-program memory
„ Two-channel CAN controller supporting Full-CAN and extensive message filtering
„ Two LIN master controllers with full hardware support for LIN communication
„ Two 550 UARTs with 16-byte Tx and Rx FIFO depths
„ Three full-duplex Q-SPIs with four slave-select lines; 16 bits wide; 8 locations deep; Tx
FIFO and Rx FIFO
„ Four 32-bit timers each containing four capture-and-compare registers linked to I/Os
„ 32-bit watchdog with timer change protection, running on safe clock.
„ Up to 108 general-purpose I/O pins with programmable pull-up, pull-down or bus
keeper
„ Vectored Interrupt Controller (VIC) with 16 priority levels
„ Two 8-channel 10-bit ADCs provide a total of up to 16 analog inputs, with conversion
times as low as 2.44 μs per channel. Each channel provides a compare function to
minimize interrupts
„ Up to 24 level-sensitive external interrupt pins, including CAN and LIN wake- up
features
„ External Static Memory Controller (SMC) with eight memory banks; up to 32-bit data
bus; up to 24-bit address bus
„ Processor wake-up from power-down via external interrupt pins; CAN or LIN activity
„ Flexible Reset Generator Unit (RGU) able to control resets of individual modules
„ Flexible Clock-Generation Unit (CGU) able to control clock frequency of individual
modules
‹ On-chip very low-power ring oscillator; fixed frequency of 0.4 MHz; always on to
provide a Safe_Clock source for system monitoring
‹ On-chip crystal oscillator with operating range from 10 MHz to 50 MHz - max. PLL
input 15 MHz
‹ On-chip PLL allows CPU operation up to a maximum CPU rate of 80 MHz
‹ Generation of up to 10 base clocks
‹ Seven fractional dividers
LPC2917_19_1
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Preliminary data sheet
Rev. 1.01 — 15 November 2007
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„ Highly configurable system Power Management Unit (PMU),
‹ clock control of individual modules
‹ allows minimization of system operating power consumption in any configuration
„ Standard ARM test and debug interface with real-time in-circuit emulator
„ Boundary-scan test supported
„ Dual power supply:
‹ CPU operating voltage: 1.8 V ± 5%
‹ I/O operating voltage: 2.7 V to 3.6 V; inputs tolerant up to 5.5 V
„ 144-pin LQFP package
„
−40 °C to 85 °C ambient operating temperature range
4. Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
Version
LPC2917FBD144
LPC2919FBD144
LQFP144
plastic low profile quad flat package; 144 leads; body 20 × 20 × 1.4 mm, pin SOT486-1
pitch 0.5 mm
LQFP144
plastic low profile quad flat package; 144 leads; body 20 × 20 × 1.4 mm, pin SOT486-1
pitch 0.5 mm
4.1 Ordering options
Table 2.
Part options
Type number
Flash memory
(kB)
RAM (kB)
SMC
LIN 2.0
Package
LPC2917FBD144 512
LPC2919FBD144 768
80 (incl TCMs)
80 (incl TCMs)
32-bit
32-bit
2
2
LQFP144
LQFP144
LPC2917_19_1
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5. Block diagram
ITCM
16 Kb
DTCM
16 Kb
ARM968E-S
m
LPC2917/19
s
IEEE 1149.1 JTAG TEST and
DEBUG INTERFACE
s
Vectored Interrupt
Controller (VIC)
s
External Static Memory
Embedded
FLASH Memory
512/768 Kb
Controller (SMC)
s
Embedded
FLASH Memory Controller (FMC)
SRAM Memory 16 Kb
s
SRAM Controller #1
Embedded
SRAM Memory 32 Kb
Timer 0, 1 (MTMR)
PWM 0, 1, 2, 3
ADC 1, 2
s
SRAM Controller #0
s
Chip Feature ID (CFID)
s
System Control Unit (SCU)
Event Router (ER)
CAN Controller
0, 1
s
GLOBAL ACCEPTANCE
FILTER
General Purpose IO (GPIO)
0, 1, 2, 3
2 Kbyte Static RAM
LIN MASTER 0/1
Timer (TMR)
0, 1, 2, 3
s
SPI 0, 1, 2
UART 0, 1
Watchdog Timer (WDT)
Clock Generation Unit (CGU)
s
Reset Generation Unit (RGU)
Power Management Unit (PMU)
Multi-layer AHB
system bus
m = master port
s = slave port
Fig 1. LPC2917/19 block diagram
LPC2917_19_1
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Preliminary data sheet
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6. Pinning information
6.1 Pinning
1
108
LPC2917FBD144
LPC2919FBD144
36
73
144PINS
Fig 2. Pin configuration for SOT486-1 (LQFP144)
6.2 Pin description
6.2.1 General description
The LPC2917/19 has up to four ports: two of 32 pins each, one of 28 pins and one of 16
pins. The pin to which each function is assigned is controlled by the SFSP registers in the
SCU. The functions combined on each port pin are shown in the pin description tables in
this section.
6.2.2 LQFP144 pin assignment
Table 3.
Symbol
LQFP144 pin assignment
Pin
Description
Function 0 (default) Function 1
IEEE 1149.1 test data out
Function 2
Function 3
TDO
1
P2.21
P0.24
P0.25
P0.26
P0.27
P0.28
P0.29
VDD(IO)
P2.22
P2.23
P3.6
2
GPIO 2, pin 21
GPIO 0, pin 24
GPIO 0, pin 25
GPIO 0, pin 26
GPIO 0, pin 27
GPIO 0, pin 28
GPIO 0, pin 29
-
PWM2 CAP1
CAN1 TxD
CAN1 RxD
-
EXTBUS D19
SPI2 SCS0
SPI2 SDO
3
UART1 TxD
4
UART1 RxD
5
-
-
-
-
SPI2 SDI
6
-
SPI2 SCK
7
TIMER0 CAP0
TIMER0 CAP1
TIMER0 MAT0
TIMER0 MAT1
8
9
3.3 V power supply for I/O
10
11
12
13
14
15
GPIO 2, pin 22
GPIO 2, pin 23
GPIO 3, pin 6
GPIO 3, pin 7
GPIO 0, pin 30
GPIO 0, pin 31
-
PWM2 CAP2
PWM3 CAP0
PWM1 MAT0
PWM1 MAT1
TIMER0 CAP2
TIMER0 CAP3
EXTBUS D20
EXTBUS D21
LIN1 TxD
-
SPI0 SCS3
P3.7
SPI2 SCS1
LIN1 RxD
P0.30
P0.31
-
-
TIMER0 MAT2
TIMER0 MAT3
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Table 3.
Symbol
LQFP144 pin assignment …continued
Pin
Description
Function 0 (default) Function 1
Function 2
Function 3
P2.24
16
17
18
19
20
21
22
23
24
25
GPIO 2, pin 24
GPIO 2, pin 25
-
-
PWM3 CAP1
PWM3 CAP2
EXTBUS D22
EXTBUS D23
P2.25
VDD(CORE)
VSS(CORE)
P1.31
1.8 V power supply for digital core
ground for digital core
GPIO 1, pin 31
ground for I/O
GPIO 1, pin 30
GPIO 3, pin 8
GPIO 3, pin 9
GPIO 1, pin 29
TIMER0 CAP1
TIMER0 MAT1
EXTINT5
VSS(IO)
P1.30
TIMER0 CAP0
SPI2 SCS0
SPI2 SDO
TIMER0 MAT0
PWM1 MAT2
PWM1 MAT3
PWM TRAP0
EXTINT4
P3.8
-
P3.9
-
P1.29
TIMER1 CAP0, EXT
START
PWM3 MAT5
P1.28
26
GPIO 1, pin 28
TIMER1 CAP1, ADC1 PWM TRAP1
EXT START
PWM3 MAT4
P2.26
P2.27
P1.27
27
28
29
GPIO 2, pin 26
GPIO 2, pin 27
GPIO 1, pin 27
TIMER0 CAP2
TIMER0 CAP3
TIMER0 MAT2
TIMER0 MAT3
EXTINT6
EXTINT7
TIMER1 CAP2, ADC2 PWM TRAP2
EXT START
PWM3 MAT3
P1.26
VDD(IO)
P1.25
P1.24
P1.23
P1.22
TMS
30
31
32
33
34
35
36
37
38
GPIO 1, pin 26
PWM2 MAT0
PWM TRAP3
PWM3 MAT2
3.3 V power supply for I/O
GPIO 1, pin 25
GPIO 1, pin 24
GPIO 1, pin 23
GPIO 1, pin 22
PWM1 MAT0
-
-
-
-
PWM3 MAT1
PWM3 MAT0
EXTBUS CS5
EXTBUS CS4
PWM0 MAT0
UART0 RxD
UART0 TxD
IEEE 1149.1 test mode select, pulled up internally.
IEEE 1149.1 test clock
TCK
P1.21
GPIO 1, pin 21
TIMER3 CAP3
TIMER1 CAP3,
MSCSS PAUSE
EXTBUS D7
P1.20
P1.19
P1.18
P1.17
VSS(IO)
P1.16
P2.0
39
40
41
42
43
44
45
46
47
48
49
50
51
52
GPIO 1, pin 20
GPIO 1, pin 19
GPIO 1, pin 18
GPIO 1, pin 17
ground for I/O
GPIO 1, pin 16
GPIO 2, pin 0
GPIO 2, pin 1
GPIO 3, pin 10
GPIO 3, pin 11
GPIO 1, pin 15
GPIO 1, pin 14
GPIO 1, pin 13
GPIO 1, pin 12
TIMER3 CAP2
TIMER3 CAP1
TIMER3 CAP0
TIMER2 CAP3
SPI0 SCS1
SPI0 SCS2
SPI0 SDO
SPI0 SDI
EXTBUS D6
EXTBUS D5
EXTBUS D4
EXTBUS D3
TIMER2 CAP2
TIMER2 MAT0
TIMER2 MAT1
SPI2 SDI
SPI0 SCK
PWM TRAP3
PWM TRAP2
PWM1 MAT4
PWM1 MAT5
SPI0 SCS0
SPI0 SCS3
-
EXTBUS D2
EXTBUS D8
EXTBUS D9
-
P2.1
P3.10
P3.11
P1.15
P1.14
P1.13
P1.12
SPI2 SCK
-
TIMER2 CAP1
TIMER2 CAP0
EXTINT3
EXTBUS D1
EXTBUS D0
EXTBUS WEN
EXTBUS OEN
EXTINT2
-
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Table 3.
Symbol
LQFP144 pin assignment …continued
Pin
Description
Function 0 (default) Function 1
3.3 V power supply for I/O
Function 2
Function 3
VDD(IO)
P2.2
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
GPIO 2, pin 2
TIMER2 MAT2
TIMER2 MAT3
SPI1 SCK
PWM TRAP1
EXTBUS D10
EXTBUS D11
EXTBUS CS3
EXTBUS CS2
-
P2.3
GPIO 2, pin 3
PWM TRAP0
P1.11
P1.10
P3.12
VSS(CORE)
VDD(CORE)
P3.13
P2.4
GPIO 1, pin 11
GPIO 1, pin 10
GPIO 3, pin 12
ground for digital core
-
SPI1 SDI
-
SPI1 SCS0
EXTINT4
1.8 V power supply for digital core
GPIO 3, pin 13
GPIO 2, pin 4
GPIO 2, pin 5
GPIO 1, pin 9
ground for I/O
GPIO 1, pin 8
GPIO 1, pin 7
GPIO 1, pin 6
GPIO 2, pin 6
GPIO 1, pin 5
GPIO 1, pin 4
SPI1 SDO
EXTINT5
EXTINT0
EXTINT1
LIN1 RxD
-
TIMER1 MAT0
TIMER1 MAT1
SPI1 SDO
EXTBUS D12
EXTBUS D13
EXTBUS CS1
P2.5
P1.9
VSS(IO)
P1.8
SPI1 SCS0
SPI1 SCS3
SPI1 SCS2
TIMER1 MAT2
SPI1 SCS1
SPI2 SCS2
LIN1 TxD
EXTBUS CS0
EXTBUS A7
EXTBUS A6
EXTBUS D14
EXTBUS A5
EXTBUS A4
P1.7
UART1 RxD
UART1 TxD
EXTINT2
P1.6
P2.6
P1.5
PWM3 MAT5
PWM3 MAT4
P1.4
TRSTN
RSTN
VSS(OSC)
XOUT_OSC
XIN_OSC
VDD(OSC)
VSS(PLL)
P2.7
IEEE 1149.1 test reset NOT; active LOW; pulled up internally
asynchronous device reset; active LOW; pulled up internally
ground for oscillator
crystal out for oscillator
crystal in for oscillator
1.8 V supply for oscillator
ground for PLL
GPIO 2, pin 7
GPIO 3, pin 14
GPIO 3, pin 15
TIMER1 MAT3
SPI1 SDI
EXTINT3
EXTINT6
EXTINT7
EXTBUS D15
CAN0 TxD
P3.14
P3.15
VDD(IO)
P2.8
SPI1 SCK
CAN0 RxD
3.3 V power supply for I/O
GPIO 2, pin 8
GPIO 2, pin 9
GPIO 1, pin 3
GPIO 1, pin 2
GPIO 1, pin 1
ground for digital core
-
PWM0 MAT0
PWM0 MAT1
PWM3 MAT3
PWM3 MAT2
PWM3 MAT1
SPI0 SCS2
SPI0 SCS1
EXTBUS A3
EXTBUS A2
EXTBUS A1
P2.9
-
P1.3
SPI2 SCS1
SPI2 SCS3
EXTINT1
P1.2
P1.1
VSS(CORE)
VDD(CORE)
P1.0
1.8 V power supply for digital core
GPIO 1, pin 0
GPIO 2, pin 10
GPIO 2, pin 11
EXTINT0
PWM3 MAT0
PWM0 MAT2
PWM0 MAT3
EXTBUS A0
SPI0 SCS0
SPI0 SCK
P2.10
P2.11
-
-
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Table 3.
Symbol
LQFP144 pin assignment …continued
Pin
Description
Function 0 (default) Function 1
Function 2
Function 3
P0.0
93
GPIO 0, pin 0
ground for I/O
GPIO 0, pin 1
GPIO 0, pin 2
GPIO 0, pin 3
GPIO 3, pin 0
GPIO 3, pin 1
GPIO 2, pin 12
GPIO 2, pin 13
GPIO 0, pin 4
GPIO 0, pin 5
-
CAN0 TxD
EXTBUS D24
VSS(IO)
P0.1
94
95
-
-
-
-
-
-
-
-
-
CAN0 RxD
EXTBUS D25
EXTBUS D26
EXTBUS D27
EXTBUS CS6
EXTBUS CS7
SPI0 SDI
P0.2
96
PWM0 MAT0
PWM0 MAT1
PWM2 MAT0
PWM2 MAT1
PWM0 MAT4
PWM0 MAT5
PWM0 MAT2
PWM0 MAT3
P0.3
97
P3.0
98
P3.1
99
P2.12
P2.13
P0.4
100
101
102
103
104
105
106
107
108
SPI0 SDO
EXTBUS D28
EXTBUS D29
P0.5
VDD(IO)
P0.6
3.3 V power supply for I/O
GPIO 0, pin 6
GPIO 0, pin 7
-
-
PWM0 MAT4
PWM0 MAT5
EXTBUS D30
EXTBUS D31
P0.7
VDD(A3V3)
JTAGSEL
3.3 V power supply for AD Converters
TAP controller select input; LOW-level selects the ARM debug mode; HIGH-level selects
boundary scan and flash programming; pulled up internally
NC
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
-
VREFP
VREFN
P0.8
HIGH reference for AD Converters
LOW reference for AD Converters
GPIO 0, pin 8
GPIO 0, pin 9
GPIO 0, pin 10
GPIO 0, pin 11
GPIO 2, pin 14
GPIO 2, pin 15
GPIO 3, pin 2
ground for I/O
GPIO 3, pin 3
GPIO 0, pin 12
GPIO 0, pin 13
GPIO 0, pin 14
GPIO 0, pin 15
GPIO 0, pin 16
GPIO 0, pin 17
ADC1 IN0
ADC1 IN1
ADC1 IN2
ADC1 IN3
-
LIN0 TxD
EXTBUS A20
EXTBUS A21
EXTBUS A8
EXTBUS A9
EXTBUS BLS0
EXTBUS BLS1
-
P0.9
LIN0 RxD
P0.10
P0.11
P2.14
P2.15
P3.2
PWM1 MAT0
PWM1 MAT1
PWM0 CAP0
PWM0 CAP1
PWM2 MAT2
-
TIMER3 MAT0
VSS(IO)
P3.3
TIMER3 MAT1
ADC1 IN4
ADC1 IN5
ADC1 IN6
ADC1 IN7
ADC2 IN0
ADC2 IN1
PWM2 MAT3
PWM1 MAT2
PWM1 MAT3
PWM1 MAT4
PWM1 MAT5
UART0 TXD
UART0 RXD
-
P0.12
P0.13
P0.14
P0.15
P0.16
P0.17
VDD(CORE)
VSS(CORE)
P2.16
P2.17
VDD(IO)
EXTBUS A10
EXTBUS A11
EXTBUS A12
EXTBUS A13
EXTBUS A22
EXTBUS A23
1.8 V power supply for digital core
ground for digital core
GPIO 2, pin 16
GPIO 2, pin 17
UART1 TxD
UART1 RxD
PWM0 CAP2
PWM1 CAP0
EXTBUS BLS2
EXTBUS BLS3
3.3 V power supply for I/O
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Table 3.
Symbol
LQFP144 pin assignment …continued
Pin
Description
Function 0 (default) Function 1
Function 2
Function 3
P0.18
P0.19
P3.4
132
133
134
135
136
137
138
139
140
141
142
143
144
GPIO 0, pin 18
GPIO 0, pin 19
GPIO 3, pin 4
GPIO 3, pin 5
GPIO 2, pin 18
GPIO 2, pin 19
GPIO 0, pin 20
GPIO 0, pin 21
GPIO 0, pin 22
ground for I/O
GPIO 0, pin 23
GPIO 2, pin 20
ADC2 IN2
ADC2 IN3
TIMER3 MAT2
TIMER3 MAT3
-
PWM2 MAT0
PWM2 MAT1
PWM2 MAT4
PWM2 MAT5
PWM1 CAP1
PWM1 CAP2
PWM2 MAT2
PWM2 MAT3
PWM2 MAT4
EXTBUS A14
EXTBUS A15
CAN1 TxD
P3.5
CAN1 RxD
P2.18
P2.19
P0.20
P0.21
P0.22
VSS(IO)
P0.23
P2.20
TDI
EXTBUS D16
EXTBUS D17
EXTBUS A16
EXTBUS A17
EXTBUS A18
-
ADC2 IN4
ADC2 IN5
ADC2 IN6
ADC2 IN7
-
PWM2 MAT5
PWM2 CAP0
EXTBUS A19
EXTBUS D18
IEEE 1149.1 data in, pulled up internally.
7. Functional description
7.1 Reset, debug, test and power description
7.1.1 Reset and power-up behavior
The LPC2917/19 contains external reset input and internal power-up reset circuits. This
ensures that a reset is extended internally until the oscillators and flash have reached a
the reset pin.
Table 4.
Symbol
RSTN
Reset pin
Direction
in
Description
external reset input, active LOW; pulled up internally
At activation of the RSTN pin the JTAGSEL pin is sensed as logic LOW. If this is the case
the LPC2917/19 is assumed to be connected to debug hardware, and internal circuits
re-program the source for the BASE_SYS_CLK to be the crystal oscillator instead of the
Low-Power Ring Oscillator (LP_OSC). This is required because the clock rate when
running at LP_OSC speed is too low for the external debugging environment.
7.1.2 Reset strategy
The LPC2917/19 contains a central module, the Reset Generator Unit (RGU) in the
Power, Clock and Reset Control Subsystem (PCRSS), which controls all internal reset
signals towards the peripheral modules. The RGU provides individual reset control as well
as the monitoring functions needed for tracing a reset back to source.
1. Only for 1.8 V power sources
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7.1.3 IEEE 1149.1 interface pins (JTAG boundary-scan test)
The LPC2917/19 contains boundary-scan test logic according to IEEE 1149.1, also
referred to in this document as Joint Test Action Group (JTAG). The boundary-scan test
pins can be used to connect a debugger probe for the embedded ARM processor. Pin
boundary- scan test pins.
Table 5.
Symbol
JTAGSEL
IEEE 1149.1 boundary-scan test and debug interface
Description
TAP controller select input. LOW level selects ARM debug mode and HIGH level
selects boundary scan and flash programming; pulled up internally
TRSTN
TMS
TDI
test reset input; pulled up internally (active LOW)
test-mode select input; pulled up internally
test data input, pulled up internally
test data output
TDO
TCK
test clock input
7.1.4 Power supply pins description
Table 6.
Symbol
VDD(CORE)
VSS(CORE)
VDD(IO)
Power supplies
Description
digital core supply 1.8 V
digital core ground (digital core, ADC 1)
I/O pins supply 3.3 V
I/O pins ground
VSS(IO)
VDD(OSC)
VSS(OSC)
VDD(A3V3)
VSS(PLL)
oscillator and PLL supply
oscillator ground
ADC 3.3 V supply
PLL ground
7.2 Clocking strategy
7.2.1 Clock architecture
The LPC2917/19 contains several different internal clock areas. Peripherals like Timers,
SPI, UART, CAN and LIN have their own individual clock sources called Base Clocks. All
base clocks are generated by the Clock Generator Unit (CGU). They may be unrelated in
frequency and phase and can have different clock sources within the CGU.
The system clock for the CPU and AHB Multilayer Bus infrastructure has its own base
clock. This means most peripherals are clocked independently from the system clock. See
Within each clock area there may be multiple branch clocks, which offers very flexible
control for power-management purposes. All branch clocks are outputs of the Power
Management Unit (PMU) and can be controlled independently. Branch clocks derived
more details of clock and power control within the device.
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ITCM
16 Kb
DTCM
16 Kb
ARM968E-S
LPC2917/19
s
m
SYS_CLK
IEEE 1149.1 JTAG TEST and
DEBUG INTERFACE
s
Vectored Interrupt
Controller (VIC)
s
External Static Memory
Controller (SMC)
Embedded
FLASH Memory
512 - 768 Kb
s
Embedded
FLASH Memory Controller (FMC)
SRAM Memory 16 Kb
s
SRAM Controller #1
Modulation and Sampling
Control Subsystem
Embedded
SRAM Memory 32 Kb
MSCSS_CLK
ADC_CLK
Timer 0, 1 (MTMR)
PWM 0, 1, 2, 3
ADC 1, 2
s
SRAM Controller #0
s
General Subsystem
Chip Feature ID (CFID)
s
System Control Unit (SCU)
Event Router (ER)
CAN Controller
0, 1
IVNSS_CLK
GLOBAL ACCEPTANCE
FILTER
s
Peripheral Subsystem
2 Kbyte Static RAM
General Purpose IO (GPIO)
0, 1, 2, 3
LIN MASTER 0/1
Timer (TMR)
0, 1, 2, 3
TMR_CLK
s
SPI_CLK
UART_CLK
SAFE_CLK
SPI 0, 1, 2
UART 0, 1
Watchdog Timer (WDT)
Power Clock Reset
Control Subsystem
Clock Generation Unit (CGU)
Reset Generation Unit (RGU)
Power Management Unit (PMU)
PCR_CLK
s
Fig 3. LPC2917/19 block diagram, overview of clock areas
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7.2.2 Base clock and branch clock relationship
The next table contains an overview of all the base blocks in the LPC2917/19 and their
derived branch clocks. A short description is given of the hardware parts that are clocked
with the individual branch clocks. In relevant cases more detailed information can be
found in the specific subsystem description. Some branch clocks have special protection
since they clock vital system parts of the device and should (for example) not be switched
Table 7.
Base clock and branch clock overview
Branch clock name
Base clock
Parts of the device clocked by Remark
this branch clock
[1]
BASE_SAFE_CLK
BASE_SYS_CLK
CLK_SAFE
Watchdog Timer
CLK_SYS_CPU
CLK_SYS_SYS
CLK_SYS_PCRSS
CLK_SYS_FMC
CLK_SYS_RAM0
ARM968E-S and TCMs
AHB Bus infrastructure
AHB side of bridge in PCRSS
Flash-Memory Controller
Embedded SRAM Controller 0
(32 KByte)
CLK_SYS_RAM1
CLK_SYS_SMC
Embedded SRAM Controller 1
(16 KByte)
External Static-Memory
Controller
CLK_SYS_GESS
CLK_SYS_VIC
General Subsystem
Vectored Interrupt Controller
[2] [4]
CLK_SYS_PESS
CLK_SYS_GPIO0
CLK_SYS_GPIO1
CLK_SYS_GPIO2
CLK_SYS_GPIO3
CLK_SYS_IVNSS_A
CLK_PCR_SLOW
Peripheral Subsystem
GPIO bank 0
GPIO bank 1
GPIO bank 2
GPIO bank 3
AHB side of bridge of IVNSS
BASE_PCR_CLK
PCRSS, CGU, RGU and PMU
logic clock
BASE_IVNSS_CLK
CLK_IVNSS_VPB
CLK_IVNSS_CANCA
CLK_IVNSS_CANC0
CLK_IVNSS_CANC1
CLK_IVNSS_LIN0
CLK_IVNSS_LIN1
VPB side of the IVNSS
CAN controller Acceptance Filter
CAN channel 0
CAN channel 1
LIN channel 0
LIN channel 1
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Table 7.
Base clock and branch clock overview …continued
Base clock
Branch clock name
Parts of the device clocked by Remark
this branch clock
BASE_MSCSS_CLK
CLK_MSCSS_VPB
VPB side of the MSCSS
CLK_MSCSS_MTMR0 Timer 0 in the MSCSS
CLK_MSCSS_MTMR1 Timer 1 in the MSCSS
CLK_MSCSS_PWM0
CLK_MSCSS_PWM1
CLK_MSCSS_PWM2
CLK_MSCSS_PWM3
PWM 0
PWM 0
PWM 0
PWM 0
CLK_MSCSS_ADC1_V VPB side of ADC 1
PB
CLK_MSCSS_ADC2_V VPB side of ADC 2
PB
BASE_UART_CLK
BASE_SPI_CLK
CLK_UART0
CLK_UART1
CLK_SPI0
UART 0 interface clock
UART 1 interface clock
SPI 0 interface clock
CLK_SPI1
SPI 1 interface clock
CLK_SPI2
SPI 2 interface clock
BASE_TMR_CLK
BASE_ADC_CLK
CLK_TMR0
CLK_TMR1
CLK_TMR2
CLK_TMR3
CLK_ADC1
Timer 0 clock for counter part
Timer 1 clock for counter part
Timer 2 clock for counter part
Timer 3 clock for counter part
Control of ADC 1, capture sample
result
CLK_ADC2
Control of ADC 2, capture sample
result
BASE_CLK_TESTSHELL CLK_TESTSHELL_IP
[1] This clock is always on (cannot be switched off for system safety reasons)
[2] In the peripheral subsystem parts of the Timers, Watchdog Timer, SPI and UART have their own clock
[3] In the Power Clock and Reset Control subsystem parts of the CGU, RGU PMU have their own clock
[4] The clock should remain activated when system wake-up on timer or UART is required.
8. Block description
8.1 Flash memory controller
8.1.1 Overview
The Flash Memory Controller (FMC) interfaces to the embedded flash memory for two
tasks:
• Providing memory data transfer
• Memory configuration via triggering, programming and erasing
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The flash memory has a 128-bit wide data interface and the flash controller offers two
128-bit buffer lines to improve system performance. The flash has to be programmed
initially via JTAG. In-system programming must be supported by the boot loader.
In-application programming is possible. Flash memory contents can be protected by
disabling JTAG access. Suspension of burning or erasing is not supported.
The key features are:
• Programming by CPU via AHB
• Programming by external programmer via JTAG
• JTAG access protection
• Burn-finished and erase-finished interrupt
8.1.2 Description
initialization flash access is not possible and AHB transfers to flash are stalled, blocking
the AHB bus.
During flash initialization the index sector is read to identify the status of the JTAG access
protection and sector security. If JTAG access protection is active the flash is not
accessible via JTAG. ARM debug facilities are disabled to protect the flash-memory
contents against unwanted reading out externally. If sector security is active only the
concerned sections are read.
Flash can be read synchronously or asynchronously to the system clock. In synchronous
operation the flash goes into standby after returning the read data. Started reads cannot
be stopped, and speculative reading and dual buffering are therefore not supported.
With asynchronous reading, transfer of the address to the flash and of read data from the
flash is done asynchronously, giving the fastest possible response time. Started reads can
be stopped, so speculative reading and dual buffering are supported.
Buffering is offered because the flash has a 128-bit wide data interface while the AHB
interface has only 32 bits. With buffering a buffer line holds the complete 128-bit flash
word, from which four words can be read. Without buffering every AHB data port read
starts a flash read. A flash read is a slow process compared to the minimum AHB cycle
time, so with buffering the average read time is reduced. This can improve system
performance.
With single buffering the most recently read flash word remains available until the next
flash read. When an AHB data-port read transfer requires data from the same flash word
as the previous read transfer, no new flash read is done and the read data is given without
wait cycles.
When an AHB data-port read transfer requires data from a different flash word to that
involved in the previous read transfer, a new flash read is done and wait states are given
until the new read data is available.
With dual buffering a secondary buffer line is used, the output of the flash being
considered as the primary buffer. On a primary buffer hit data can be copied to the
secondary buffer line, which allows the flash to start a speculative read of the next flash
word.
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Both buffer lines are invalidated after:
• Initialization
• Configuration-register access
• Data-latch reading
• Index-sector reading
Table 8.
Flash read modes
Synchronous timing
No buffer line
for single (non-linear) reads; one flash-word read per word read
Single buffer line
default mode of operation; most recently read flash word is kept until
another flash word is required
Asynchronous timing
No buffer line
one flash-word read per word read
Single buffer line
most recently read flash word is kept until another flash word is
required
Dual buffer line, single
speculative
on a buffer miss a flash read is done, followed by at most one
speculative read; optimized for execution of code with small loops
(less than eight words) from flash
Dual buffer line, always
speculative
most recently used flash word is copied into second buffer line; next
flash-word read is started; highest performance for linear reads
8.1.3 Flash memory controller pin description
The flash memory controller has no external pins. However, the flash can be programmed
8.1.4 Flash memory controller clock description
8.1.5 Flash layout
The ARM processor can program the flash for ISP (In-System Programming) and IAP (In-
Application Programming). Note that the flash always has to be programmed by ‘flash
words’ of 128 bits (four 32-bit AHB bus words, hence 16 bytes).
The flash memory is organized into eight ‘small’ sectors of 8 kB each and up to 11 ‘large’
sectors of 64 kB each. The number of large sectors depends on the device type. A sector
must be erased before data can be written to it. The flash memory also has sector-wise
protection. Writing occurs per page which consists of 4096 bits (32 flash words). A small
sector contains 16 pages; a large sector contains 128 pages.
Table 9.
Flash sector overview
Sector number
Sector size (kB)
Sector base address
0000 0000h
0
1
2
8
8
8
0000 2000h
0000 4000h
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Table 9.
Flash sector overview …continued
Sector number
Sector size (kB)
Sector base address
0000 6000h
0000 8000h
0000 A000h
0000 C000h
0000 E000h
0001 0000h
0002 0000h
0003 0000h
0004 0000h
0005 0000h
0006 0000h
0007 0000h
0008 0000h
0009 0000h
000A 0000h
000B 0000h
3
8
4
8
5
8
6
8
7
8
8
64
64
64
64
64
64
64
64
64
64
64
9
10
11
12
13
14
15[1]
16[1]
17[1]
18[1]
[1] Availability of sector 15 to sector 18 depends on device type, see Section 4 “Ordering information”.
The index sector is a special sector in which the JTAG access protection and sector
security are located. The address space becomes visible by setting the FS_ISS bit and
overlaps the regular flash sector’s address space.
Note that the index sector cannot be erased, and that access to it has to be performed via
code outside the flash.
8.1.6 Flash bridge wait-states
To eliminate the delay associated with synchronizing flash-read data, a predefined
number of wait-states must be programmed. These depend on flash-memory response
time and system clock period. The minimum wait-states value can be calculated with the
following formulas:
Synchronous reading:
tacc(clk)
------------------
WST >
– 1
tt
tclk(sys)
Asynchronous reading:
tacc(addr)
---------------------
ttclk(sys)
WST >
– 1
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Remark: If the programmed number of wait-states is more than three, flash-data reading
cannot be performed at full speed (i.e. with zero wait-states at the AHB bus) if speculative
reading is active.
8.2 External static memory controller
8.2.1 Overview
The LPC2917/19 contains an external Static Memory Controller (SMC) which provides an
interface for external (off-chip) memory devices.
Key features are:
• Supports static memory-mapped devices including RAM, ROM, flash, burst ROM and
external I/O devices
• Asynchronous page-mode read operation in non-clocked memory subsystems
• Asynchronous burst-mode read access to burst-mode ROM devices
• Independent configuration for up to eight banks, each up to 16 MB
• Programmable bus-turnaround (idle) cycles (one to 16)
• Programmable read and write wait states (up to 32), for static RAM devices
• Programmable initial and subsequent burst-read wait state for burst-ROM devices
• Programmable write protection
• Programmable burst-mode operation
• Programmable external data width: 8-bit, 16-bit or 32-bit
• Programmable read-byte lane enable control
8.2.2 Description
The SMC simultaneously supports up to eight independently configurable memory banks.
Each memory bank can be 8, 16 or 32 bits wide and is capable of supporting SRAM,
ROM, burst-ROM memory or external I/O devices.
A separate chip-select output is available for each bank. The chip-select lines are
configurable to be active HIGH or LOW. Memory-bank selection is controlled by memory
memory base addresses, chip selects and bank internal addresses.
Table 10. External memory-bank address bit description
32 bit
Symbol
Description
System
Address Bit
field
31 to 29
BA[2:0]
external static-memory base address (three most significant bits);
field contains ’010’ when addressing an external memory bank.
28 to 26
25 and 24
23 to 0
CS[2:0]
-
chip-select address space for eight memory banks; see [1]
always ’00’; other values are ’mirrors’ of the 16 MByte bank address
16-MByte memory banks address space
A[23:0]
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Table 11. External static-memory controller banks
CS[2:0]
Bank
000
001
010
011
100
101
110
111
bank 0
bank 1
bank 2
bank 3
bank 4
bank 5
bank 6
bank 7
8.2.3 External static-memory controller pin description
The external static-memory controller module in the LPC2917/19 has the following pins,
shows the external memory controller pins.
Table 12. External memory controller pins
Symbol
Direction
out
Description
EXTBUS CSx
EXTBUS BLSy
memory-bank x select, x runs from 0 to 7
byte-lane select input y, y runs from 0 to 3
write enable (active LOW)
output enable (active LOW)
address bus
out
EXTBUS WE_N out
EXTBUS OE_N out
EXTBUS A[23:0] out
EXTBUS D[31:0] in/out
data bus
8.2.4 External static-memory controller clock description
8.2.5 External memory timing diagrams
between the wait-state settings is indicated with arrows.
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CLK(SYS)
CS
OE_N
ADDR
DATA
WSTOEN
WST1
WSTOEN=3, WST1=7
Fig 4. Reading from external memory
between wait-state settings is indicated with arrows.
CLK(SYS)
CS
WE_N / BLS
ADDR
DATA
WSTWEN
WST2
WSTWEN=3, WST2=7
Fig 5. Writing to external memory
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are added between a read and a write cycle in the same external memory device.
CLK(SYS)
CS
WE_N / BLS
OE_N
ADDR
DATA
WSTOEN
WST1
WSTWEN
WST2
IDCY
WSTOEN=5, WSTWEN=5, WST1=7, WST2=6, IDCY=5
Fig 6. Reading/writing external memory
Address pins on the device are shared with other functions. When connecting external
memories, check that the I/O pin is programmed for the correct function. Control of these
settings is handled by the SCU.
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8.3 General subsystem
8.3.1 General subsystem clock description
8.3.2 Chip and feature identification
8.3.2.1 Overview
The key features are:
• Identification of product
• Identification of features enabled
8.3.2.2 Description
The Chip/Feature ID (CFID) module contains registers which show and control the
functionality of the chip. It contains an ID to identify the silicon, and also registers
containing information about the features enabled or disabled on the chip.
8.3.2.3 CFID pin description
The CFID has no external pins.
8.3.3 System Control Unit (SCU)
8.3.3.1 Overview
The system control unit takes care of system-related functions.The key feature is
configuration of the I/O port-pins multiplexer.
8.3.3.2 Description
The system control unit defines the function of each I/O pin of the LPC2917/19. The I/O
pin configuration should be consistent with peripheral function usage.
8.3.3.3 SCU pin description
The SCU has no external pins.
8.3.4 Event router
8.3.4.1 Overview
The event router provides bus-controlled routing of input events to the vectored interrupt
controller for use as interrupt or wake-up signals.
Key features:
• Up to 24 level-sensitive external interrupt pins, including CAN, LIN and RxD wake-up
features plus three internal event sources
• Input events can be used as interrupt source either directly or latched (edge-detected)
• Direct events disappear when the event becomes inactive
• Latched events remain active until they are explicitly cleared
• Programmable input level and edge polarity
• Event detection maskable
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• Event detection is fully asynchronous, so no clock is required
8.3.4.2 Description
The event router allows the event source to be defined, its polarity and activation type to
be selected and the interrupt to be masked or enabled. The event router can be used to
start a clock on an external event.
The vectored interrupt-controller inputs are active HIGH.
8.3.4.3 Event-router pin description and mapping to register bit positions
The event router module in the LPC2917/19 is connected to the pins listed below. The
shows the pins connected to the event router, and also the corresponding bit position in
the event-router registers and the default polarity.
Table 13. Event-router pin connections
Symbol
Direction
Bit position
Description
Default
polarity
EXTINT0
EXTINT1
EXTINT2
EXTINT3
EXTINT4
EXTINT5
EXTINT6
EXTINT7
CAN0 RXD
CAN1 RXD
-
in
in
in
in
in
in
in
in
in
in
-
0
external interrupt input 0
external interrupt input 1
external interrupt input 2
external interrupt input 3
external interrupt input 4
external interrupt input 5
external interrupt input 6
external interrupt input 7
CAN0 receive data input wake-up
CAN1 receive data input wake-up
reserved
1
1
1
1
1
1
1
1
0
0
-
1
2
3
4
5
6
7
8
9
13 - 10
14
LIN0 RXD
LIN1 RXD
-
in
in
-
LIN0 receive data input wake-up
LIN1 receive data input wake-up
reserved
0
0
-
15
21 - 16
22
-
na
na
na
-
CAN interrupt (internal)
VIC FIQ (internal)
1
1
1
-
-
23
-
24
VIC IRQ (internal)
-
26 - 25
reserved
8.4 Peripheral subsystem
8.4.1 Peripheral subsystem clock description
The peripheral subsystem is clocked by a number of different clocks:
• CLK_SYS_PESS
• CLK_UART0/1
• CLK_SPI0/1/2
• CLK_TMR0/1/2/3
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8.4.2 Watchdog timer
8.4.2.1 Overview
The purpose of the watchdog timer is to reset the ARM9 processor within a reasonable
amount of time if the processor enters an error state. The watchdog generates a system
reset if the user program fails to trigger it correctly within a predetermined amount of time.
Key features:
• Internal chip reset if not periodically triggered
• Timer counter register runs on always-on safe clock
• Optional interrupt generation on watchdog timeout
• Debug mode with disabling of reset
• Watchdog control register change-protected with key
• Programmable 32-bit watchdog timer period with programmable 32-bit prescaler.
8.4.2.2 Description
The watchdog timer consists of a 32-bit counter with a 32-bit prescaler.
The watchdog should be programmed with a time-out value and then periodically
restarted. When the watchdog times out it generates a reset through the RGU.
To generate watchdog interrupts in watchdog debug mode the interrupt has to be enabled
via the interrupt enable register. A watchdog-overflow interrupt can be cleared by writing
to the clear-interrupt register.
Another way to prevent resets during debug mode is via the Pause feature of the
Watchdog Timer. The watchdog is stalled when the ARM9 is in debug mode and the
PAUSE_ENABLE bit in the Watchdog Timer Control register is set.
The Watchdog Reset output is fed to the Reset Generator Unit (RGU). The RGU contains
a reset source register to identify the reset source when the device has gone through a
8.4.2.3 Pin description
The watchdog has no external pins.
8.4.2.4 Watchdog timer clock description
The Watchdog Timer is clocked by two different clocks; CLK_SYS_PESS and
by CLK_SYS_PESS. The timer and prescale counters are clocked by CLK_SAFE which
is always on.
8.4.3 Timer
8.4.3.1 Overview
The LPC2917/19 contains six identical timers: four in the peripheral subsystem and two in
the Modulation and Sampling Control SubSystem (MSCSS) located at different peripheral
base addresses. This section describes the four timers in the peripheral subsystem. Each
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timer has four capture inputs and/or match outputs. Connection to device pins depends on
the configuration programmed into the port function-select registers. The two timers
located in the MSCSS have no external capture or match pins, but the memory map is
function.
The key features are:
• 32-bit timer/counter with programmable 32-bit prescaler
• Up to four 32-bit capture channels per timer. These take a snapshot of the timer value
when an external signal connected to the TIMERx CAPn input changes state. A
capture event may also optionally generate an interrupt
• Four 32-bit match registers per timer that allow:
– Continuous operation with optional interrupt generation on match
– Stop timer on match with optional interrupt generation
– Reset timer on match with optional interrupt generation
• Up to four external outputs per timer corresponding to match registers, with the
following capabilities:
– Set LOW on match
– Set HIGH on match
– Toggle on match
– Do nothing on match
• Pause input pin (MSCSS timers only)
8.4.3.2 Description
The timers are designed to count cycles of the clock and optionally generate interrupts or
perform other actions at specified timer values, based on four match registers. They also
include capture inputs to trap the timer value when an input signal changes state,
optionally generating an interrupt. The core function of the timers consists of a 32 bit
‘prescale counter’ triggering the 32 bit ‘timer counter’. Both counters run on clock
CLK_TMRx (x runs from 0 to 3) and all time references are related to the period of this
clock. Note that each timer has its individual clock source within the Peripheral
SubSystem. In the Modulation and Sampling SubSystem each timer also has its own
clocks.
8.4.3.3 Pin description
The four timers in the peripheral subsystem of the LPC2917/19 have the pins described
below. The two timers in the modulation and sampling subsystem have no external pins
timers and their associated pins. The timer pins are combined with other functions on the
runs from 0 to 3).
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Table 14. Timer pins
Symbol Direction
Description
TIMERx CAP[0] IN
TIMERx CAP[1] IN
TIMERx CAP[2] IN
TIMERx CAP[3] IN
TIMERx MAT[0] OUT
TIMERx MAT[1] OUT
TIMERx MAT[2] OUT
TIMERx MAT[3] OUT
TIMER x capture input 0
TIMER x capture input 1
TIMER x capture input 2
TIMER x capture input 3
TIMER x match output 0
TIMER x match output 1
TIMER x match output 2
TIMER x match output 3
8.4.3.4 Timer clock description
The timer modules are clocked by two different clocks; CLK_SYS_PESS and CLK_TMRx
power management. The frequency of all these clocks is identical as they are derived
from the same base clock BASE_CLK_TMR. The register interface towards the system
bus is clocked by CLK_SYS_PESS. The timer and prescale counters are clocked by
CLK_TMRx.
8.4.4 UARTs
8.4.4.1 Overview
The LPC2917/19 contains two identical UARTs located at different peripheral base
addresses. The key features are:
• 16-byte receive and transmit FIFOs
• Registers conform to industry standard 550
• Receiver FIFO trigger points at 1 byte, 4 bytes, 8 bytes and 14 bytes
• Built-in baud-rate generator
8.4.4.2 Description
The UART is commonly used to implement a serial interface such as RS232. The
LPC2917/19 contains two industry-standard 550 UARTs with 16-byte transmit and receive
FIFOs, but they can also be put into 450 mode without FIFOs.
8.4.4.3 UART pin description
The two UARTs in the LPC2917/19 have the following pins. The UART pins are combined
runs from 0 to 1).
Table 15. UART pins
Symbol
Direction
Description
UARTx TXD out
UARTx RXD in
UART channel x transmit data output
UART channel x receive data input
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8.4.4.4 UART clock description
The UART modules are clocked by two different clocks; CLK_SYS_PESS and
branch clock for power management. The frequency of all CLK_UARTx clocks is identical
since they are derived from the same base clock BASE_CLK_UART. The register
interface towards the system bus is clocked by CLK_SYS_PESS. The baud generator is
clocked by the CLK_UARTx.
8.4.5 Serial peripheral interface
8.4.5.1 Overview
The LPC2917/19 contains three Serial Peripheral Interface modules (SPIs) to allow
synchronous serial communication with slave or master peripherals.
The key features are:
• Master or slave operation
• Supports up to four slaves in sequential multi-slave operation
• Supports timer-triggered operation
• Programmable clock bit rate and prescale based on SPI source clock
(BASE_SPI_CLK), independent of system clock
• Separate transmit and receive FIFO memory buffers; 16 bits wide, 32 locations deep
• Programmable choice of interface operation: Motorola SPI or Texas Instruments
Synchronous Serial Interfaces
• Programmable data-frame size from 4 to 16 bits
• Independent masking of transmit FIFO, receive FIFO and receive overrun interrupts
• Serial clock-rate master mode: fserial_clk ≤ fCLK(SPI)*/2
• Serial clock-rate slave mode: fserial_clk = fCLK(SPI)*/4
• Internal loopback test mode
8.4.5.2 Functional description
The SPI module is a master or slave interface for synchronous serial communication with
peripheral devices that have either Motorola SPI or Texas Instruments Synchronous
Serial Interfaces.
The SPI module performs serial-to-parallel conversion on data received from a peripheral
device. The transmit and receive paths are buffered with FIFO memories (16 bits wide x
32 words deep). Serial data is transmitted on SPI_TxD and received on SPI_RxD.
The SPI module includes a programmable bit-rate clock divider and prescaler to generate
the SPI serial clock from the input clock CLK_SPIx.
The SPI module’s operating mode, frame format, and word size are programmed through
the SLVn_SETTINGS registers.
A single combined interrupt request SPI_INTREQ output is asserted if any of the
interrupts are asserted and unmasked.
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Depending on the operating mode selected, the SPI_CS_OUT outputs operate as an
active-HIGH frame synchronization output for Texas Instruments synchronous serial
frame format or an active-LOW chip select for SPI.
Each data frame is between four and 16 bits long, depending on the size of words
programmed, and is transmitted starting with the MSB.
There are two basic frame types that can be selected:
• Texas Instruments synchronous serial
• Motorola Serial Peripheral Interface
8.4.5.3 Modes of operation
The SPI module can operate in:
• Master mode:
– Normal transmission mode
– Sequential slave mode
• Slave mode
8.4.5.4 SPI pin description
The three SPI modules in the LPC2917/19 have the pins listed below. The pins are
Table 16. SPI pins
Symbol
Direction
in/out
in/out
in
Description
SPIx SCSy
SPIx SCK
SPIx SDI
SPIx SDO
SPIx clock[1]
SPIx data input
SPIx data output
out
[1] Direction of SPIx SCS and SPIx SCK pins depends on master or slave mode. These pins are output in
master mode, input in slave mode.
[2] In slave mode there is only one chip-select input pin, SPIx SCS0. The other chip selects have no function in
slave mode.
8.4.5.5 SPI clock description
The SPI modules are clocked by two different clocks; CLK_SYS_PESS and CLK_SPIx (x
power management. The frequency of all clocks CLK_SPIx is identical as they are derived
from the same base clock BASE_CLK_SPI. The register interface towards the system bus
is clocked by CLK_SYS_PESS. The serial-clock rate divisor is clocked by CLK_SPIx.
The SPI clock frequency can be controlled by the CGU. In master mode the SPI clock
frequency (CLK_SPIx) must be set to at least twice the SPI serial clock rate on the
interface. In slave mode CLK_SPIx must be set to four times the SPI serial clock rate on
the interface.
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8.4.6 General-purpose I/O
8.4.6.1 Overview
The LPC2917/19 contains four general-purpose I/O ports located at different peripheral
base addresses. In the 144-pin package all four ports are available. All I/O pins are
bi-directional, and the direction can be programmed individually. The I/O pad behavior
depends on the configuration programmed in the port function-select registers.
The key features are:
• General-purpose parallel inputs and outputs
• Direction control of individual bits
• Synchronized input sampling for stable input-data values
• All I/O defaults to input at reset to avoid any possible bus conflicts
8.4.6.2 Description
The general-purpose I/O provides individual control over each bi-directional port pin.
There are two registers to control I/O direction and output level. The inputs are
synchronized to achieve stable read-levels.
To generate an open-drain output, set the bit in the output register to the desired value.
Use the direction register to control the signal. When set to output, the output driver
actively drives the value on the output: when set to input the signal floats and can be
pulled up internally or externally.
8.4.6.3 GPIO pin description
The five GPIO ports in the LPC2917/19 have the pins listed below. The GPIO pins are
GPIO pins.
Table 17. GPIO pins
Symbol
Direction
Description
GPIO0 pin[31:0] in/out
GPIO1 pin[31:0] in/out
GPIO2 pin[27:0] in/out
GPIO3 pin[15:0] in/out
GPIO port x pins 31 to 0
GPIO port x pins 31 to 0
GPIO port x pins 27 to 0
GPIO port x pins 15 to 0
8.4.6.4 GPIO clock description
The GPIO modules are clocked by several clocks, all of which are derived from
Note that each GPIO has its own CLK__SYS_GPIOx branch clock for power
management. The frequency of all clocks CLK_SYS_GPIOx is identical to
CLK_SYS_PESS since they are derived from the same base clock BASE_SYS_CLK.
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8.5 CAN gateway
8.5.1 Overview
Controller Area Network (CAN) is the definition of a high-performance communication
protocol for serial data communication. The two CAN controllers in the LPC2917/19
provide a full implementation of the CAN protocol according to the CAN specification
version 2.0B. The gateway concept is fully scalable with the number of CAN controllers,
and always operates together with a separate powerful and flexible hardware acceptance
filter.
The key features are:
• Supports 11-bit as well as 29-bit identifiers
• Double receive buffer and triple transmit buffer
• Programmable error-warning limit and error counters with read/write access
• Arbitration-lost capture and error-code capture with detailed bit position
• Single-shot transmission (i.e. no re-transmission)
• Listen-only mode (no acknowledge; no active error flags)
• Reception of ‘own’ messages (self-reception request)
• Full CAN mode for message reception
8.5.2 Global acceptance filter
The global acceptance filter provides look-up of received identifiers - called acceptance
filtering in CAN terminology - for all the CAN controllers. It includes a CAN ID look-up table
memory, in which software maintains one to five sections of identifiers. The CAN ID
look-up table memory is 2 kB large (512 words, each of 32 bits). It can contain up to 1024
standard frame identifiers (SFF) or 512 extended frame identifiers (EFF) or a mixture of
both types. It is also possible to define identifier groups for standard and extended
message formats.
8.5.3 CAN pin description
The two CAN controllers in the LPC2917/19 have the pins listed below. The CAN pins are
CAN pins (x runs from 0 to 1).
Table 18. CAN pins
Symbol
Direction
Description
CANx TXDC out
CANx RXDC in
CAN channel x transmit data output
CAN channel x receive data input
8.6 LIN
8.6.1 Overview
The LPC2917/19 contain two LIN 2.0 master controllers. These can be used as dedicated
LIN 2.0 master controllers with additional support for sync break generation and with
hardware implementation of the LIN protocol according to spec 2.0.
The key features are:
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• Complete LIN 2.0 message handling and transfer
• One interrupt per LIN message
• Slave response time-out detection
• Programmable sync-break length
• Automatic sync-field and sync-break generation
• Programmable inter-byte space
• Hardware or software parity generation
• Automatic checksum generation
• Fault confinement
• Fractional baud-rate generator
8.6.2 LIN pin description
The two LIN 2.0 master controllers in the LPC2917/19 have the pins listed below. The LIN
controller.
Table 19. LIN controller pins
Symbol
Direction
Description
LIN0/1 TXDL out
LIN0/1 RXDL in
LIN channel 0/1 transmit data output
LIN channel 0/1 receive data input
8.7 Modulation and sampling control subsystem
8.7.1 Overview
The Modulation and Sampling Control Subsystem (MSCSS) in the LPC2917/19 includes
four Pulse-Width Modulators (PWMs), three10-bit successive approximation
Analog-to-Digital Converters (ADCs) and two timers.
The key features of the MSCSS are:
• Two 10-bit, 400 ksamples/s, 8-channel ADCs with 3.3 V inputs and various trigger-
start options
• Four 6-channel PWMs (Pulse-Width Modulators) with capture and trap functionality
• Two dedicated timers to schedule and synchronize the PWMs and ADCs
8.7.2 Description
The MSCSS contains Pulse-Width Modulators (PWMs), Analog-to-Digital Converters
(ADCs) and timers.
communication with the AHB system bus. Two internal timers are dedicated to this
subsystem. MSCSS timer 0 can be used to generate start pulses for the ADCs and the
first PWM. The second timer (MSCSS timer 1) is used to generate ‘carrier’ signals for the
PWMs. These carrier patterns can be used, for example, in applications requiring current
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control. Several other trigger possibilities are provided for the ADCs (external, cascaded
or following a PWM). The capture inputs of both timers can also be used to capture the
start pulse of the ADCs.
The PWMs can be used to generate waveforms in which the frequency, duty cycle and
rising and falling edges can be controlled very precisely. Capture inputs are provided to
measure event phases compared to the main counter. Depending on the applications,
these inputs can be connected to digital sensor motor outputs or digital external signals.
Interrupt signals are generated on several events to closely interact with the CPU.
The ADCs can be used for any application needing accurate digitized data from analog
sources. To support applications like motor control, a mechanism to synchronize several
PWMs and ADCs is available (sync_in and sync_out).
Note that the PWMs run on the PWM clock and the ADCs on the ADC clock, see
ADC2 IN[7:0]
ADC2_EXT_START
ADC1 IN[7:0]
ADC1_EXT_START
ADC clock
MSCSS
TIMER 0
ADC
CONTROL
ADC
1
ADC
2
3.3 V
AHB
system bus
VPB sub system bus
(to all sub blocks)
SYNCS
3.3 V
AHB2VPB
BRIDGE
PWM0 MAT[5:0]
PWM1 MAT[5:0]
PWM2 MAT[5:0]
PWM3 MAT[5:0]
MSCSS
TIMER 1
PWM
0
PWM
1
PWM
CONTROL
PWM
2
PWM
3
CARRIERS
PWM0 TRAP
PWM0 CAP[2:0]
PWM1 TRAP
PWM1 CAP[2:0]
PWM2 TRAP
PWM2 CAP[2:0]
PWM3 TRAP
PWM3 CAP[2:0]
002aad348
Fig 7. Modulation and sampling control subsystem block diagram
8.7.2.1 Synchronization and trigger features of the MSCSS
The MSCSS contains two internal timers to generate synchronization and carrier pulses
PWM modules.
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Each ADC module has four start inputs. An ADC conversion is started when one of the
start ADC conditions is valid:
• start 0: ADC external start input pin; can be triggered at a positive or negative edge.
Note that this signal is captured in the ADC clock domain
• start 1: If the ‘preceding’ ADC conversion is ended, the sync_out signal starts an ADC
conversion. This signal is captured in the MSCSS subsystem clock domain, see
start 1 input of ADC2 and the sync_out of ADC2 is connected to the start 1 input of
ADC1.
• start 2: The PWM sync_out can start an ADC conversion. The sync_out signal is
synchronized to the ADC clock in the ADC module. This signal is captured in the
MSCSS subsystem clock domain.
• start 3: The match outputs from MSCSS timer 0 are connected to the start 3 inputs of
the ADCs. This signal is captured in the ADC clock domain.
The PWM_sync and trans_enable_in of PWM 0 are connected to the 4th match output of
MSCSS timer 0 to start the PWM after a pre-programmed delay. This sync signal is
cascaded through all PWMs, allowing a programmable delay offset between subsequent
PWMs. The sync delay of each PWM can be programmed synchronously or with a
different phase for spreading the power load.
The match outputs of MSCSS timer 1 (PWM control) are connected to the corresponding
carrier inputs of the PWM modules. The carrier signal is modulated with the PWM-
generated waveforms.
The pause input of MSCSS timer 1 (PWM Control) is connected to an external input pin.
Generation of the carrier signal is stopped by asserting the pause of this timer.
The pause input of MSCSS timer 0 (ADC Control) is connected to a ‘NOR’ of the
PWM_sync outputs (start 2 input on the ADCs). If the pause feature of this timer is
enabled the timer only counts when one of the PWM_sync outputs is active HIGH. This
feature can be used to start the ADC once every x PWM cycles, where x corresponds to
the value in the match register of the timer. In this case the start 3 input of the ADC should
be enabled (start on match output of MSCSS timer 0).
The signals connected to the capture inputs of the timers (both MSCSS timer 0 and
MSCSS timer 1) are intended for debugging.
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ADC2_EXT_START
ADC1_EXT_START
pause_0
pause
(2)
ADC1
(1)
MSCSS
st0
st1
st2
st3
(2)
so
TIMER 0
ADC2
c0
m0
st0
st1
st2
st3
so0
so
c1
c2
c3
m1
m2
m3
so1
so2
pause_0
(3)
PWM0
s_i
TE_i
(1)
(3)
MSCSS
TIMER 1
c0
PWM1
s_i
TE_i
s_o
TE_o
c_i
trap
(3)
PWM2
m0
m1
m2
s_o
TE_o
s_i
c_i
trap
(3)
PWM3
s_i
c1
c2
TE_i
s_o
TE_o
c_i
TE_i
trap
s_o
TE_o
c_i
trap
c3
m3
pause
MSCSS PAUSE
PWM0 TRAP
PWM1 TRAP
PWM2 TRAP
PWM3 TRAP
002aad347
(1) Timers:
c0 to c3 = capture in 0 to capture in 3
m0 to m3 = match out 0 to match out 3
(2) ADCs:
st0 to st3 = start 0 to start 3 inputs
s0 to s3 = sync_out 0 to sync_out 3
(3) PWMs:
c_i = carrier in
s_i = sync_in
s_o = sync_out
TE_i = trans_enable_in
TE_o = trans_enable_out
Fig 8. Modulation and sampling-control subsystem synchronization and triggering
8.7.3 MSCSS pin description
The pins of the LPC2917/19 MSCSS associated with the two ADC modules are described
8.7.4 MSCSS clock description
The MSCSS is clocked from a number of different sources:
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• CLK_SYS_MSCSS_A clocks the AHB side of the AHB-to-VPB bus bridge
• CLK_MSCSS_VPB clocks the subsystem VPB bus
• CLK_MSCSS_MTMR0/1 clocks the timers
• CLK_MSCSS_PWM0..3 clocks the PWMs.
Each ADC has two clock areas; a VPB part clocked by CLK_MSCSS_ADCx_VPB (x = 1
or 2) and a control part for the analog section clocked by CLK_ADCx = 1 or 2), see
All clocks are derived from the BASE_MSCSS_CLK, except for CLK_SYS_MSCSS_A
which is derived form BASE_SYS_CLK, and the CLK_ADCx clocks which are derived
from BASE_CLK_ADC. If specific PWM or ADC modules are not used their corresponding
clocks can be switched off.
8.7.5 Analog-to-digital converter
8.7.5.1 Overview
The MSCSS in the LPC2917/19 includes two 10-bit successive-approximation
analog-to-digital converters.
The key features of the ADC interface module are:
• ADC1 and ADC2: Eight analog inputs; time-multiplexed; measurement range up to
3.3 V
• External reference-level inputs
• 400 ksamples per second at 10-bit resolution up to 1500 ksamples per second at 2-bit
resolution
• Programmable resolution from 2-bit to 10-bit
• Single analog-to-digital conversion scan mode and continuous analog-to-digital
conversion scan mode
• Optional conversion on transition on external start input, timer capture/match signal,
PWM_sync or ‘previous’ ADC
• Converted digital values are stored in a register for each channel
• Optional compare condition to generate a ‘less than’ or an ‘equal to or greater than’
compare-value indication for each channel
• Power-down mode
8.7.5.2 Description
functionality is divided into two major parts; one part running on the MSCSS Subsystem
clock, the other on the ADC clock. This split into two clock domains affects the behavior
from a system-level perspective. The actual analog-to-digital conversions take place in the
ADC clock domain, but system control takes place in the system clock domain.
A mechanism is provided to modify configuration of the ADC and control the moment at
which the updated configuration is transferred to the ADC domain.
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The ADC clock is limited to 4.5 MHz maximum frequency and should always be lower
than or equal to the system clock frequency. To meet this constraint or to select the
desired lower sampling frequency the clock generation unit provides a programmable
fractional system-clock divider dedicated to the ADC clock. Conversion rate is determined
by the ADC clock frequency divided by the number of resolution bits plus one. Accessing
ADC registers requires an enabled ADC clock, which is controllable via the clock
Each ADC has four start inputs. Note that start 0 and start 2 are captured in the system
clock domain while start 1 and start 3 are captured in the ADC domain. The start inputs
CLK_ADCx
(ADC clock)
(upto 4.5 MHz)
CLK_ADCx_VPB
(MSCSS SubSystem clock)
VPB SubSystem
domain
ADC domain
update
Conversion data
Config data
IRQ
ADC
control
&
ADC
control
&
3.3 V
Analog
to
Digital
convertor
Analog
inputs
ADC1: 8
ADC2: 8
VPB
system
bus
Analog
mux
registers
registers
ADC
IRQ
Start 0
Start 2
Start 1
Start 3
Sync_out
001aad331 **
Fig 9. ADC block diagram
8.7.5.3 ADC pin description
The two ADC modules in the MSCSS have the pins described below. The ADCx input
pins are combined with other functions on the port pins of the LPC2917/19. The VREFN
Table 20. Analog to digital converter pins
Symbol
Direction
Description
ADCn IN[7:0]
in
analog input for ADCn, channel 7 to channel 0 (n is 1 or 2)
ADC external start-trigger input (n is 1 or 2)
ADC LOW reference level
ADCn_EXT_START in
VREFN
VREFP
in
in
ADC HIGH reference level
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8.7.5.4 ADC clock description
The ADC modules are clocked from two different sources; CLK_MSCSS_ADCx_VPB and
and CLK_MSCSS_ADCx_VPB branch clocks for power management. If an ADC is
unused both its CLK_MSCSS_ADCx_VPB and CLK_ADCx can be switched off.
The frequency of all the CLK_MSCSS_ADCx_VPB clocks is identical to
CLK_MSCSS_VPB since they are derived from the same base clock
BASE_MSCSS_CLK. Likewise the frequency of all the CLK_ADCx clocks is identical
since they are derived from the same base clock BASE_ADC_CLK.
The register interface towards the system bus is clocked by CLK_MSCSS_ADCx_VPB.
Control logic for the analog section of the ADC is clocked by CLK_ADCx, see also
8.7.6 PWM
8.7.6.1 Overview
The MSCSS in the LPC2917/19 includes four PWM modules with the following features.
• Six pulse-width modulated output signals
• Double edge features (rising and falling edges programmed individually)
• Optional interrupt generation on match (each edge)
• Different operation modes: continuous or run-once
• 16-bit PWM counter and 16-bit prescale counter allow a large range of PWM periods
• A protective mode (TRAP) holding the output in a software-controllable state and with
optional interrupt generation on a trap event
• Three capture registers and capture trigger pins with optional interrupt generation on
a capture event
• Interrupt generation on match event, capture event, PWM counter overflow or trap
event
• A burst mode mixing the external carrier signal with internally generated PWM
• Programmable sync-delay output to trigger other PWM modules (master/slave
behavior)
8.7.6.2 Description
The ability to provide flexible waveforms allows PWM blocks to be used in multiple
applications; e.g. automotive dimmer/lamp control and fan control. Pulse-width
modulation is the preferred method for regulating power since no additional heat is
generated and it is energy-efficient when compared with linear-regulating voltage control
networks.
The PWM delivers the waveforms/pulses of the desired duty cycles and cycle periods. A
very basic application of these pulses can be in controlling the amount of power
transferred to a load. Since the duty cycle of the pulses can be controlled, the desired
amount of power can be transferred for a controlled duration. Two examples of such
applications are:
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• Automotive dimmer controller: The flexibility of providing waves of a desired duty
cycle and cycle period allows the PWM to control the amount of power to be
transferred to the load. The PWM functions as a dimmer controller in this application
• Motor controller: The PWM provides multi-phase outputs, and these outputs can be
controlled to have a certain pattern sequence. In this way the force/torque of the
motor can be adjusted as desired. This makes the PWM function as a motor drive.
Sync_in Transfer_enable_in
VPB domain
PWM domain
update
PWM
Counter,
prescale
counter
&
Match outputs
Capture inputs
Capture data
PWM
control
&
VPB system bus
PWM counter value
registers
Config data
IRQ’s
shadow
registers
IRQ pwm
IRQ capt_match
Trap input
Carier inputs
Sync_out Transfer_enable_out
Fig 10. PWM block diagram
functionality is split into two major parts, a VPB domain and a PWM domain, both of which
run on clocks derived from the BASE_MSCSS_CLK. This split into two domains affects
behavior from a system-level perspective. The actual PWM and prescale counters are
located in the PWM domain but system control takes place in the VPB domain.
The actual PWM consists of two counters; a 16-bit prescale counter and a 16-bit PWM
counter. The position of the rising and falling edges of the PWM outputs can be
programmed individually. The prescale counter allows high system bus frequencies to be
scaled down to lower PWM periods. Registers are available to capture the PWM counter
values on external events.
Note that in the Modulation and Sampling SubSystem, each PWM has its individual clock
source CLK_MSCSS_PWMx (x runs from 0 to 3). Both the prescale and the timer
counters within each PWM run on this clock CLK_MSCSS_PWMx, and all time references
these clocks.
8.7.6.3 Synchronizing the PWM counters
A mechanism is included to synchronize the PWM period to other PWMs by providing a
sync input and a sync output with programmable delay. Several PWMs can be
synchronized using the trans_enable_in/trans_enable_out and sync_in/sync_out ports.
in the LPC2917/19. PWM 0 can be master over PWM 1; PWM 1 can be master over
PWM 2, etc.
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8.7.6.4 Master and slave mode
A PWM module can provide synchronization signals to other modules (also called Master
mode). The signal sync_out is a pulse of one clock cycle generated when the internal
PWM counter (re)starts. The signal trans_enable_out is a pulse synchronous to sync_out,
generated if a transfer from system registers to PWM shadow registers occurred when the
PWM counter restarted. A delay may be inserted between the counter start and
generation of trans_enable_out and sync_out.
A PWM module can use input signals trans_enable_in and sync_in to synchronize its
internal PWM counter and the transfer of shadow registers (Slave mode).
8.7.6.5 PWM pin description
Each of the four PWM modules in the MSCSS has the following pins. These are combined
PWM3 pins.
Table 21. PWM pins
Symbol
Direction
Description
PWMn CAP[0]
PWMn CAP[1]
PWMn CAP[2]
PWMn MAT[0]
PWMn MAT[1]
PWMn MAT[2]
PWMn MAT[3]
PWMn MAT[4]
PWMn MAT[5]
PWMn TRAP
in
PWM n capture input 0
PWM n capture input 1
PWM n capture input 2
PWM n match output 0
PWM n match output 1
PWM n match output 2
PWM n match output 3
PWM n match output 4
PWM n match output 5
PWM n trap input
in
in
out
out
out
out
out
out
in
8.7.6.6 PWM clock description
Note that each PWM has its own CLK_MSCSS_PWMx branch clock for power
management. The frequency of all these clocks is identical to CLK_MSCSS_VPB since
they are derived from the same base clock BASE_MSCSS_CLK.
Also note that unlike the timer modules in the Peripheral SubSystem, the actual timer
counter registers of the PWM modules run at the same clock as the VPB system interface
CLK_MSCSS_VPB. This clock is independent of the AHB system clock.
If a PWM module is not used its CLK_MSCSS_PWMx branch clock can be switched off.
8.7.7 Timers in the MSCSS
8.7.7.1 Overview
The two timers in the MSCSS are functionally identical to the timers in the peripheral
the timers in the peripheral subsystem, but the capture inputs and match outputs are not
available on the device pins. These signals are instead connected to the ADC and PWM
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8.7.7.2 Description
8.7.7.3 MSCSS timer-pin description
MSCSS timer 0 has no external pins.
MSCSS timer 1 has a PAUSE pin available as external pin. The PAUSE pin is combined
timer 1 external pin.
Table 22. MSCSS timer 1 pin
Symbol
Direction
Description
MSCSS PAUSE
in
pause pin for MSCSS timer 1
8.7.7.4 MSCSS timer-clock description
The Timer modules in the MSCSS are clocked by CLK_MSCSS_MTMRx (x = 0-1), see
power management. The frequency of all these clocks is identical to CLK_MSCSS_VPB
since they are derived from the same base clock BASE_MSCSS_CLK.
Note that, unlike the timer modules in the Peripheral SubSystem, the actual timer counter
registers run at the same clock as the VPB system interface CLK_MSCSS_VPB. This
clock is independent of the AHB system clock.
If a timer module is not used its CLK_MSCSS_MTMRx branch clock can be switched off.
8.8 Power, clock and reset control subsystem
8.8.1 Overview
The Power, Clock and Reset Control Subsystem (PCRSS) in the LPC2917/19 includes a
Clock Generator Unit (CGU), a Reset Generator Unit (RGU) and a Power Management
Unit (PMU).
8.8.2 Description
communication with the AHB system bus.
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Power, Clock & Reset
CGU
PMU
Xtal Oscillator
PLL
base
out0
out1
…
clocks
branch
clocks
Low Power
Ring Oscillator
(Ringo)
out9
AHB Master
Disable Grant
FDIV[6:0]
CGU
registers
AHB Master
Disable Req
AHB2DTL
Bridge
wakeup_a
RGU
AHB_RST
RGU
...
registers
...
SCU_RST
Reset Output
Delay Logic
WARM_RST
COLD_RST
PCR_RST
RGU_RST
POR_RST
Input Deglitch/
Sync
POR
RSTN (device pin)
Reset from Watchdog counter
Fig 11. PCRSS block diagram
8.8.3 PCR subsystem clock description
The PCRSS is clocked by a number of different clocks. CLK_SYS_PCRSS clocks the
AHB side of the AHB to DTL bus bridge and CLK_PCR_SLOW clocks the CGU, RGU and
BASE_SYS_CLK, which can be switched off in low-power modes. CLK_PCR_SLOW is
derived from BASE_PCR_CLK and is always on in order to be able to wake up from
low-power modes.
8.8.4 Clock Generation Unit (CGU)
8.8.4.1 Overview
The key features are:
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• Generation of 10 and 2 test-base clocks, selectable from several embedded clock
sources
• Crystal oscillator with power-down
• Control PLL with power-down
• Very low-power ring oscillator, always on to provide a ’safe clock’
• Seven fractional clock dividers with L/D division
• Individual source selector for each base clock, with glitch-free switching
• Autonomous clock-activity detection on every clock source
• Protection against switching to invalid or inactive clock sources
• Embedded frequency counter
• Register write-protection mechanism to prevent unintentional alteration of clocks
Remark: Any clock-frequency adjustment has a direct impact on the timing of on-board
peripherals such as the UARTs, SPI, watchdog, timers, CAN controller, LIN master
controller, ADCs or flash-memory interface.
8.8.4.2 Description
Table 23. CGU base clocks
Number Name
Frequency
(MHz) [1]
Description
0
1
2
3
4
5
6
7
8
BASE_SAFE_CLK
0.4
Base safe clock (always on)
Base system clock
BASE_SYS_CLK
BASE_PCR_CLK
BASE_IVNSS_CLK
BASE_MSCSS_CLK
BASE_UART_CLK
BASE_SPI_CLK
80
0.4 [2]
80
Base PCR subsystem clock
Base IVNSS subsystem clock
Base MSCSS subsystem clock
Base UART clock
80
80
40
Base SPI clock
BASE_TMR_CLK
BASE_ADC_CLK
80
Base timers clock
4.5
Base ADCs clock
[1] Maximum frequency that guarantees stable operation of the LPC2917/19.
[2] Fixed to low-power oscillator.
For generation of these base clocks, the CGU consists of primary and secondary clock
generators and one output generator for each base clock.
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Clock Source Bus
LP_OSC
Xtal
PLL
FDIV0
FDIV1
OUT 0
OUT 1
Oscilator
FDIV6
OUT 9
Frequency
Monitor
Clock
Detection
DTL MMIO Interface
Fig 12. Block diagram of the CGU
There are two primary clock generators: a low-power ring oscillator (LP_OSC) and a
LP_OSC is the source for the BASE_PCR_CLK that clocks the CGU itself and for
BASE_SAFE_CLK that clocks a minimum of other logic in the device (like the watchdog
timer). To prevent the device from losing its clock source LP_OSC cannot be put into
power-down. The crystal oscillator can be used as source for high-frequency clocks or as
an external clock input if a crystal is not connected.
Secondary clock generators are a PLL and seven fractional dividers (FDIV0..6). The PLL
has three clock outputs: normal, 120° phase-shifted and 240° phase-shifted.
Configuration of the CGU: For every output generator - generating the base clocks - a
choice can be made from the primary and secondary clock generators according to
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OSC1M
XO50M
FDIV0..6
PLL160M
clkout /
clkout120 /
clkout240
Output
Control
Clock
outputs
Fig 13. Structure of the clock generation scheme
Any output generator (except for BASE_SAFE_CLK and BASE_PCR_CLK) can be
connected to either a fractional divider (FDIV0..6) or to one of the outputs of the PLL or to
LP_OSC/crystal oscillator directly. BASE_SAFE_CLK and BASE_PCR_CLK can use only
LP_OSC as source.
The fractional dividers can be connected to one of the outputs of the PLL or directly to
LP_OSC/crystal Oscillator.
The PLL can be connected to the crystal oscillator.
In this way every output generating the base clocks can be configured to get the required
clock. Multiple output generators can be connected to the same primary or secondary
clock source, and multiple secondary clock sources can be connected to the same PLL
output or primary clock source.
Invalid selections/programming - connecting the PLL to an FDIV or to one of the PLL
outputs itself for example - will be blocked by hardware. The control register will not be
written, the previous value will be kept, although all other fields will be written with new
data. This prevents clocks being blocked by incorrect programming.
Default Clock Sources: Every secondary clock generator or output generator is
connected to LP_OSC at reset. In this way the device runs at a low frequency after reset.
It is recommended to switch BASE_SYS_CLK to a high-frequency clock generator as
(one of) the first step(s) in the boot code after verifying that the high-frequency clock
generator is running.
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Clock Activity Detection: Clocks that are inactive are automatically regarded as invalid,
and values of ’CLK_SEL’ that would select those clocks are masked and not written to the
control registers. This is accomplished by adding a clock detector to every clock
generator. The RDET register keeps track of which clocks are active and inactive, and the
appropriate ‘CLK_SEL’ values are masked and unmasked accordingly. Each clock
detector can also generate interrupts at clock activation and deactivation so that the
system can be notified of a change in internal clock status.
Clock detection is done using a counter running at the BASE_PCR_CLK frequency. If no
positive clock edge occurs before the counter has 32 cycles of BASE_PCR_CLK the clock
is assumed to be inactive. As BASE_PCR_CLK is slower than any of the clocks to be
detected, normally only one BASE_PCR_CLK cycle is needed to detect activity. After
reset all clocks are assumed to be ‘non-present’, so the RDET status register will be
correct only after 32 BASE_PCR_CLK cycles.
Note that this mechanism cannot protect against a currently-selected clock going from
active to inactive state. Therefore an inactive clock may still be sent to the system under
special circumstances, although an interrupt can still be generated to notify the system.
Glitch-Free Switching: Provisions are included in the CGU to allow clocks to be
switched glitch-free, both at the output generator stage and also at secondary source
generators.
In the case of the PLL the clock will be stopped and held low for long enough to allow the
PLL to stabilize and lock before being re-enabled. For all non-PLL Generators the switch
will occur as quickly as possible, although there will always be a period when the clock is
held low due to synchronization requirements.
If the current clock is high and does not go low within 32 cycles of BASE_PCR_CLK it is
assumed to be inactive and is asynchronously forced low. This prevents deadlocks on the
interface.
8.8.4.3 PLL functional description
analog section. This block compares the phase and frequency of the inputs and generates
the main clock2. These clocks are either divided by 2*P by the programmable post divider
to create the output clock, or sent directly to the output. The main output clock is then
divided by M by the programmable feedback divider to generate the feedback clock. The
output signal of the analog section is also monitored by the lock detector to signal when
the PLL has locked onto the input clock.
2. Generation of the main clock is restricted by the frequency range of the PLL clock input. See Table 31, Dynamic characteristics.
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PSEL
P23EN
clkout120 /
clkout240
Input clock
CCO
/ 2PDIV
P23
clkout
Bypass
Direct
/ MDIV
MSEL
Fig 14. PLL block diagram
Triple output phases
For applications that require multiple clock phases two additional clock outputs can be
enabled by setting register P23EN to ’1’, thus giving three clocks with a 120° phase
difference. In this mode all three clocks generated by the analog section are sent to the
output dividers. When the PLL has not yet achieved lock the second and third phase
output dividers run unsynchronized, which means that the phase relation of the output
clocks is unknown. When the PLL LOCK register is set the second and third phase of the
output dividers are synchronized to the main output clock CLKOUT PLL, thus giving three
clocks with a 120° phase difference.
Direct output mode
In normal operating mode (with DIRECT set to ’0’) the CCO clock is divided by 2, 4, 8 or
16 depending on the value on the PSEL[1:0] input, giving an output clock with a 50% duty
cycle. If a higher output frequency is needed the CCO clock can be sent directly to the
output by setting DIRECT to ’1’. Since the CCO does not directly generate a 50% duty
cycle clock, the output clock duty cycle in this mode can deviate from 50%.
Power-down control
A power-down mode has been incorporated to reduce power consumption when the PLL
clock is not needed. This is enabled by setting the PD control register bit. In this mode the
analog section of the PLL is turned off, the oscillator and the phase-frequency detector are
stopped and the dividers enter a reset state. While in power-down mode the LOCK output
is low, indicating that the PLL is not in lock. When power-down mode is terminated by
clearing the PD control-register bit the PLL resumes normal operation, and makes the
LOCK signal high once it has regained lock on the input clock.
8.8.4.4 CGU pin description
Table 24. CGU pins
Symbol
Direction
Description
XOUT_OSC
XIN_OSC
out
in
Oscillator crystal output
Oscillator crystal input or external clock input
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8.8.5 Reset Generation Unit (RGU)
8.8.5.1 Overview
The key features of the Reset Generation Unit (RGU) are:
• Reset controlled individually per subsystem
• Automatic reset stretching and release
• Monitor function to trace resets back to source
• Register write-protection mechanism to prevent unintentional resets
8.8.5.2 Description
The RGU controls all internal resets.
Each reset output is defined as a (combination of) reset input sources including the
listed in this table form a sort of cascade to provide the multiple levels of impact that a
reset may have. The combined input sources are logically OR-ed together so that
activating any of the listed reset sources causes the output to go active.
Table 25. Reset output configuration
Reset Output
POR_RST
Reset Source
parts of the device reset when activated
LP_OSC; is source for RGU_RST
power-on reset module
POR_RST, RSTN pin
RGU_RST
RGU internal; is source for PCR_RST
PCR_RST
RGU_RST, WATCHDOG PCR internal; is source for COLD_RST
COLD_RST
WARM_RST
SCU_RST
PCR_RST
parts with COLD_RST as reset source below
parts with WARM_RST as reset source below
SCU
COLD_RST
COLD_RST
COLD_RST
COLD_RST
COLD_RST
COLD_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
CFID_RST
CFID
FMC_RST
embedded Flash-Memory Controller (FMC)
embedded SRAM-Memory Controller
external Static-Memory Controller (SMC)
GeSS AHB-to-VPB bridge
PeSS AHB-to-VPB bridge
all GPIO modules
EMC_RST
SMC_RST
GESS_A2V_RST
PESS_A2V_RST
GPIO_RST
UART_RST
all UART modules
TMR_RST
all Timer modules in PeSS
all SPI modules
SPI_RST
IVNSS_A2V_RST
IVNSS_CAN_RST
IVNSS_LIN_RST
MSCSS_A2V_RST
IVNSS AHB-to-VPB bridge
all CAN modules including Acceptance filter
all LIN modules
MSCSS AHB to VPB bridge
all PWM modules
MSCSS_PWM_RST WARM_RST
MSCSS_ADC_RST WARM_RST
MSCSS_TMR_RST WARM_RST
all ADC modules
all Timer modules in MSCSS
Vectored Interrupt Controller (VIC)
CPU and AHB Multilayer Bus infrastructure
VIC_RST
AHB_RST
WARM_RST
WARM_RST
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8.8.5.3 RGU pin description
pins.
Table 26. RGU pins
Symbol
Directio Description
n
RSTN
IN
external reset input, Active LOW; pulled up internally
8.8.6 Power Management Unit (PMU)
8.8.6.1 Overview
This module enables software to actively control the system’s power consumption by
disabling clocks not required in a particular operating mode.
Using the base clocks from the CGU as input, the PMU generates branch clocks to the
rest of the LPC2917/19. Output clocks branched from the same base clock are phase-
and frequency-related. These branch clocks can be individually controlled by software
programming.
The key features are:
• Individual clock control for all LPC2917/19 sub-modules
• Activates sleeping clocks when a wake-up event is detected
• Clocks can be individually disabled by software
• Supports AHB master-disable protocol when AUTO mode is set
• Disables wake-up of enabled clocks when power-down mode is set
• Activates wake-up of enabled clocks when a wake-up event is received
• Status register is available to indicate if an input base clock can be safely switched off
(i.e. all branch clocks are disabled)
8.8.6.2 Description
The PMU controls all internal clocks of the device for power-mode management. With
some exceptions, each branch clock can be switched on or off individually under control of
software register bits located in its individual configuration register. Some branch clocks
control bits are supported by each branch clock.
By programming the configuration register the user can control which clocks are switched
on or off, and which clocks are switched off when entering power-down mode.
Note that the standby-wait-for-interrupt instructions of the ARM968E-S processor (putting
the ARM CPU into a low-power state) are not supported. Instead putting the ARM CPU
into power-down should be controlled by disabling the branch clock for the CPU.
Remark: For any disabled branch clocks to be re-activated their corresponding base
clocks must be running (controlled by the CGU).
Every branch clock is related to one particular base clock: it is not possible to switch the
source of a branch clock in the PMU.
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Table 27. Branch clock overview
Legend:
"1" Indicates that the related register bit is tied off to logic HIGH, all writes are ignored
"0" Indicates that the related register bit is tied off to logic LOW, all writes are ignored
“+” Indicates that the related register bit is readable and writable
Branch Clock Name
Base Clock
Implemented Switch On/Off
Mechanism
WAKEUP
AUTO
0
RUN
1
CLK_SAFE
BASE_SAFE_CLK
BASE_SYS_CLK
BASE_SYS_CLK
BASE_SYS_CLK
BASE_SYS_CLK
BASE_SYS_CLK
BASE_SYS_CLK
BASE_SYS_CLK
BASE_SYS_CLK
BASE_SYS_CLK
BASE_SYS_CLK
BASE_SYS_CLK
BASE_SYS_CLK
BASE_SYS_CLK
BASE_SYS_CLK
BASE_SYS_CLK
BASE_SYS_CLK
BASE_SYS_CLK
BASE_SYS_CLK
BASE_PCR_CLK
BASE_IVNSS_CLK
BASE_IVNSS_CLK
BASE_IVNSS_CLK
BASE_IVNSS_CLK
BASE_IVNSS_CLK
BASE_MSCSS_CLK
BASE_MSCSS_CLK
BASE_MSCSS_CLK
BASE_MSCSS_CLK
BASE_MSCSS_CLK
BASE_MSCSS_CLK
BASE_MSCSS_CLK
0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
CLK_SYS_CPU
+
1
CLK_SYS
+
1
CLK_SYS_PCR
+
1
CLK_SYS_FMC
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
1
CLK_SYS_RAM0
CLK_SYS_RAM1
CLK_SYS_SMC
+
+
+
CLK_SYS_GESS
CLK_SYS_VIC
+
+
CLK_SYS_PESS
CLK_SYS_GPIO0
CLK_SYS_GPIO1
CLK_SYS_GPIO2
CLK_SYS_GPIO3
CLK_SYS_IVNSS_A
CLK_SYS_MSCSS_A
CLK_SYS_CHCA
CLK_SYS_CHCB
CLK_PCR_SLOW
CLK_IVNSS_VPB
CLK_IVNSS_CANC0
CLK_IVNSS_CANC1
CLK_IVNSS_LIN0
CLK_IVNSS_LIN1
CLK_MSCSS_VPB
CLK_MSCSS_MTMR0
CLK_MSCSS_MTMR1
CLK_MSCSS_PWM0
CLK_MSCSS_PWM1
CLK_MSCSS_PWM2
CLK_MSCSS_PWM3
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
CLK_MSCSS_ADC1_VPB BASE_MSCSS_CLK
CLK_MSCSS_ADC2_VPB BASE_MSCSS_CLK
+
+
CLK_UART0
CLK_UART1
BASE_UART_CLK
BASE_UART_CLK
+
+
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Table 27. Branch clock overview …continued
Legend:
"1" Indicates that the related register bit is tied off to logic HIGH, all writes are ignored
"0" Indicates that the related register bit is tied off to logic LOW, all writes are ignored
“+” Indicates that the related register bit is readable and writable
Branch Clock Name
Base Clock
Implemented Switch On/Off
Mechanism
WAKEUP
AUTO
RUN
+
CLK_SPI0
BASE_SPI_CLK
BASE_SPI_CLK
+
+
+
+
+
+
+
+
+
0
+
+
+
+
+
+
+
+
+
0
CLK_SPI1
+
CLK_SPI2
BASE_SPI_CLK
+
CLK_TMR0
CLK_TMR1
CLK_TMR2
CLK_TMR3
CLK_ADC1
CLK_ADC2
CLK_TESTSHELL_IP
BASE_TMR_CLK
BASE_TMR_CLK
BASE_TMR_CLK
BASE_TMR_CLK
BASE_ADC_CLK
BASE_ADC_CLK
BASE_CLK_TESTSHELL
+
+
+
+
+
+
1
8.8.6.3 PMU pin description
The PMU has no external pins.
8.9 Vectored interrupt controller
8.9.1 Overview
The LPC2917/19 contains a very flexible and powerful Vectored Interrupt Controller (VIC)
to interrupt the ARM processor on request.
The key features are:
• Level-active interrupt request with programmable polarity
• 56 interrupt-request inputs
• Software-interrupt request capability associated with each request input
• Observability of interrupt-request state before masking
• Software-programmable priority assignments to interrupt requests up to 15 levels
• Software-programmable routing of interrupt requests towards the ARM-processor
inputs IRQ and FIQ
• Fast identification of interrupt requests through vector
• Support for nesting of interrupt service routines
8.9.2 Description
The Vectored Interrupt Controller routes incoming interrupt requests to the ARM
processor. The interrupt target is configured for each interrupt request input of the VIC.
The targets are defined as follows:
• Target 0 is ARM processor FIQ (fast interrupt service)
• Target 1 is ARM processor IRQ (standard interrupt service)
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Interrupt-request masking is performed individually per interrupt target by comparing the
priority level assigned to a specific interrupt request with a target-specific priority
threshold. The priority levels are defined as follows:
• Priority level 0 corresponds to ‘masked’ (i.e. interrupt requests with priority 0 never
lead to an interrupt)
• Priority 1 corresponds to the lowest priority
• Priority 15 corresponds to the highest priority
Software interrupt support is provided and can be supplied for:
• Testing RTOS interrupt handling without using device-specific interrupt service
routines
• Software emulation of an interrupt-requesting device, including interrupts
8.9.3 VIC pin description
The VIC module in the LPC2917/19 has no external pins.
8.9.4 VIC clock description
9. Limiting values
Table 28. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
Supply pins
Ptot
[1]
Total power dissipation.
Core supply voltage.
W
V
VDD(CORE)
VDD(OSC_PLL)
−0.5
−0.5
+2.0
+2.0
Oscillator and PLL supply
voltage.
V
VDD(ADC3V3)
VDD(IO)
IDD
3.3 V ADC supply voltage.
I/O digital supply voltage.
Supply current.
−0.5
−0.5
+4.6
+4.6
98
V
V
[2]
[2]
Average value per supply
pin.
mA
ISS
Ground current.
Average value per ground
pin.
98
mA
Input pins and I/O pins
VXIN_OSC
VXIN_RTC
VI(IO)
Voltage on pin XIN_OSC.
−0.5
−0.5
−0.5
−0.5
−0.5
−0.5
+2.0
V
Voltage on pin XIN_RTC.
I/O input voltage.
+2.0
V
[4][5]
VDD(IO) + 3.0
V
VI(ADC)
VVREFP
VVREFN
II(ADC)
ADC input voltage.
I/O port 0.
VDD(ADC3V3) + 0.5
V
Voltage on pin VREFP.
Voltage on pin VREFN.
ADC input current.
+3.6
+3.6
35
V
V
[2]
Average value per input pin.
mA
Output pins and I/O pins configured as output
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Table 28. Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
[9]
[9]
IOHS
HIGH-state short-circuit
output current.
Drive HIGH, output shorted
to VSS(IO).
-
−33
mA
IOLS
LOW-state short-circuit
output current.
Drive LOW, output shorted
to VDD(IO).
-
+38
mA
General
Tstg
Storage temperature.
−40
−40
−40
+150
+85
°C
°C
°C
Tamb
Ambient temperature.
Virtual junction temperature.
[6]
Tvj
+125
Memory
nendu(fl)
tret(fl)
Endurance of flash memory.
-
-
100000
20
cycle
year
Flash memory retention
time.
Electrostatic discharge
Vesd Electrostatic discharge
voltage.
On all pins.
[7]
[8]
Human body model.
Machine model.
−2000
−200
−500
+2000
+200
+500
V
V
V
Charged device model.
On corner pins.
Charged device model.
-750
+750
V
[1] Based on package heat transfer, not device power consumption.
[2] Peak current must be limited at 25 times average current.
[3] For I/O Port 0, the maximum input voltage is defined by VI(ADC)
.
[4] Only when VDD(IO) is present.
[5] Note that pull-up should be off. With pull-up do not exceed 3.6 V.
[6] In accordance with IEC 60747-1. An alternative definition of the virtual junction temperature is: Tvj = Tamb + Ptot × Rth(j-a) where Rth(j-a) is
a fixed value; see Section 10. The rating for Tvj limits the allowable combinations of power dissipation and ambient temperature.
[7] Human-body model: discharging a 100 pF capacitor via a 10 kΩ series resistor.
[8] Machine model: discharging a 200 pF capacitor via a 0.75 μH series inductance and 10 Ω resistor.
[9] 112 mA per VDD(IO) or VSS(IO) should not be exceeded.
10. Thermal characteristics
Table 29. Thermal characteristics
Symbol
Parameter
Conditions
in free air
package;
LQFP144
Value
Unit
Rth(j-a)
thermal resistance from
junction to ambient
62
K/W
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11. Static characteristics
Table 30. Static characteristics
VDD(CORE) = VDD(OSC_PLL) ; VDD(IO) = 2.7 V to 3.6 V; VDD(A3V3) = 3.0 V to 3.6 V; Tvj = -40 °C to +125 °C; all voltages are
measured with respect to ground; positive currents flow into the IC; unless otherwise specified.[1]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Supplies
Core supply
VDD(CORE)
IDDD(CORE)
Core supply voltage.
Core supply current.
1.71
-
1.80
1.1
1.89
2.5
V
ARM9 and all
mA/
peripherals active at
max clock speeds.
MHz
[2]
All clocks off.
30
-
450
3.6
μA
V
I/O supply
VDD(IO)
I/O digital supply voltage.
2.7
1.71
Oscillator supply
VDD(OSC_PLL) Oscillator and PLL supply
voltage.
1.80
1.89
V
IDDD(OSC_PLL) Oscillator and PLL supply start-up
current.
1.5
-
-
-
3
1
2
mA
mA
μA
Normal mode
Power-down mode
-
-
Analog-to-digital converter supply
VDD(A3V3) 3.3 V ADC supply voltage
IDDA(A3V3) 3.3 V ADC analog supply Normal mode
current.
Input pins and I/O pins configured as input
3.0
3.3
3.6
1.9
4
V
-
-
-
-
mA
μA
Power-down mode
[7][8]
VI
Input voltage.
All port pins and VDD(IO)
applied except port 0
pins 16 to 31.
-
+ 5.5
V
see Section 9
[8]
Port 0 pins 16 to 31.
VVREFP
+3.6
All port pins and VDD(IO)
not applied.
-0.5
-0.5
-
-
V
V
All other I/O pins,
RESET_N, TRST_N,
TDI, JTAGSEL, TMS,
TCK.
VDD(IO)
VIH
VIL
HIGH-state input voltage. All port pins, RESET_N,
TRST_N, TDI,
2.0
-
-
-
-
V
V
JTAGSEL, TMS, TCK.
LOW-state input voltage. All port pins, RESET_N,
TRST_N, TDI,
0.8
JTAGSEL, TMS, TCK.
Vhys
ILIH
Hysteresis voltage.
0.4
-
-
-
-
V
HIGH-state input leakage
current.
1
μA
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Table 30. Static characteristics …continued
VDD(CORE) = VDD(OSC_PLL) ; VDD(IO) = 2.7 V to 3.6 V; VDD(A3V3) = 3.0 V to 3.6 V; Tvj = -40 °C to +125 °C; all voltages are
measured with respect to ground; positive currents flow into the IC; unless otherwise specified.[1]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
ILIL
LOW-state input leakage
current.
-
-
1
μA
II(pd)
II(pu)
Pull-down input current.
All port pins, VI = 3.3 V;
VI = 5.5 V.
25
50
100
μA
Pull-up input current.
All port pins, RESET_N,
TRST_N, TDI,
−25
−50
−100
μA
JTAGSEL, TMS: VI = 0
V; VI > 3.6 V is not
allowed.
[3]
Ci
Input capacitance.
8
pF
Output pins and I/O pins configured as output
VO
Output voltage.
0
-
-
VDD(IO)
-
V
V
VOH
HIGH-state output
voltage.
IOH = −4 mA
VDD(IO) – 0.4
VOL
CL
LOW-state output voltage. IOL = 4 mA
Load capacitance.
-
-
-
-
0.4
25
V
pF
Analog-to-digital converter supply
VVREFN
VVREFP
VI(ADC)
Voltage on pin VREFN.
Voltage on pin VREFP.
0
-
-
-
VVREFP − 2
VDD(A3V3)
VVREFP
V
V
V
VVREFN + 2
VVREFN
ADC input voltage on
port 0 pins
Port 0.
Zi
Input impedance.
Between VREFN and
VREFP
4.4
-
-
-
kΩ
Between VREFN and
VDD(A5V)
13.7
23.6
kΩ
FSR
Full scale range.
2
-
-
-
-
-
10
bit
INL
Integral non-linearity.
Differential non-linearity.
Offset error voltage.
Full-scale error voltage.
−1
+1
LSB
LSB
mV
mV
DNL
−1
+1
Verr(offset)
Verr(FS)
−20
−20
+20
+20
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Table 30. Static characteristics …continued
VDD(CORE) = VDD(OSC_PLL) ; VDD(IO) = 2.7 V to 3.6 V; VDD(A3V3) = 3.0 V to 3.6 V; Tvj = -40 °C to +125 °C; all voltages are
measured with respect to ground; positive currents flow into the IC; unless otherwise specified.[1]
Symbol
Oscillator
Rs(xtal)
Parameter
Conditions
Min
Typ
Max
Unit
[5]
Crystal series resistance. fosc = 10 MHz to 15 MHz
Cxtal = 10 pF;
Cext = 18 pF
-
-
-
-
160
60
Ω
Ω
Cxtal = 20 pF;
Cext = 39 pF
[5]
[9]
fosc = 15 MHz to 20 MHz
Cxtal = 10 pF;
Cext = 18 pF
-
-
80
Ω
Ci
Input capacitance of
XIN_OSC.
pF
Power-up reset
[6]
[6]
[6]
Vtrip(high)
Vtrip(low)
Vtrip(dif)
High trip-level voltage.
1.4
1.3
120
1.6
1.5
180
V
Low trip-level voltage.
V
Difference between high
and low trip-level
voltages.
mV
[1] All parameters are guaranteed over the virtual junction temperature range by design. Pre-testing is performed at Tamb = 125 °C on wafer
level. Cased products are tested at Tamb = 25 °C (final testing). Both pre-testing and final testing use correlated test conditions to cover
the specified temperature and power-supply voltage range.
[2] Leakage current is exponential to temperature; worst-case value is at 125 C Tvj. All clocks off. Analog modules and FLASH powered
down.
[3] For Port 0, pin 0 to pin 15 add maximum 1.5 pF for input capacitance to ADC. For Port 0, pin 16 to pin 31 add maximum 1.0 pF for input
capacitance to ADC.
[4] This value is the minimum drive capability. Maximum short-circuit output current is 33 mA (drive HIGH-level, shorted to ground) or
−38 mA. (drive LOW-level, shorted to VDD(IO)). The device will be damaged if multiple outputs are shorted.
[5] Cxtal is crystal load capacitance and Cext are the two external load capacitors.
[6] The power-up reset has a time filter: VDD(CORE) must be above Vtrip(high) for 2 μs before reset is de-asserted; VDD(CORE) must be below
V
trip(low) for 11 μs before internal reset is asserted.
[7] Not 5 V-tolerant when pull-up is on.
[8] For I/O Port 0, the maximum input voltage is defined by VI(ADC)
.
[9] This parameter is not part of production testing or final testing, hence only a typical value is stated. Maximum and minimum values are
based on simulation results.
12. Dynamic characteristics
Table 31. Dynamic characteristics
VDD(CORE) = VDD(OSC_PLL) ; VDD(IO) = 2.7 V to 3.6 V; VDD(A3V3) = 3.0 V to 3.6 V; Tvj = −40 °C; all voltages are measured with
respect to ground; positive currents flow into the IC; unless otherwise specified.
Symbol
I/O pins
tTHL
Parameter
Conditions
Min
Typ
Max
Unit
HIGH-to-LOW
transition time.
CL = 30 pF
CL = 30 pF
4
4
-
-
13.8
13.8
ns
ns
tTLH
LOW-to-HIGH
transition time.
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Table 31. Dynamic characteristics …continued
VDD(CORE) = VDD(OSC_PLL) ; VDD(IO) = 2.7 V to 3.6 V; VDD(A3V3) = 3.0 V to 3.6 V; Tvj = −40 °C; all voltages are measured with
respect to ground; positive currents flow into the IC; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Internal clock
fclk(sys)
System clock
frequency. See
10
-
80
MHz
Tclk(sys)
System clock period.
12.5
-
100
ns
Low-Power Ring Oscillator
fref(RO) RO reference
0.36
-
0.4
6
0.42
100
MHz
frequency.
tstartup
Start-up time.
At maximum frequency
μs
[2]
Oscillator
fi(osc)
Oscillator input
frequency.
Maximum frequency is
the clock input of an
external clock source
applied to the Xin pin.
10
-
-
80
-
MHz
tstartup
Start-up time.
At maximum frequency.
500
μs
PLL
fi(PLL)
fo(PLL)
PLL input frequency.
PLL output frequency.
10
-
-
-
25
MHz
MHz
MHz
10
160
320
CCO; direct mode.
156
Analog-to-digital converter
fi(ADC) ADC input frequency.
fs(max)
[4]
4
-
4.5
MHz
Maximum sampling
rate.
fi(ADC) = 4.5 MHz;
fs = fi(ADC)/(n+1) with
n = resolution
resolution 2 bit
resolution 10 bit
-
-
-
-
1500
400
11
ksample/s
ksample/s
cycles
-
tconv
Conversion time.
In number of ADC clock
cycles.
3
In number of bits.
2
-
10
bits
Flash memory
tinit
Initialization time.
Page write time.
-
-
150
1.05
105
70
μs
ms
ms
ns
ns
ns
twr(pg)
0.95
1
ter(sect)
Sector erase time.
Flash word BIST time.
clock access time
address access time
95
-
100
38
-
tfl(BIST)
tacc(clk)
-
63.4
60.3
tacc(addr)
-
-
external static memory controller
ta(R)int
Internal read-access
time.
-
-
20.5
ns
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Table 31. Dynamic characteristics …continued
VDD(CORE) = VDD(OSC_PLL) ; VDD(IO) = 2.7 V to 3.6 V; VDD(A3V3) = 3.0 V to 3.6 V; Tvj = −40 °C; all voltages are measured with
respect to ground; positive currents flow into the IC; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
ta(W)int
Internal write-access
time.
-
-
24.9
ns
UART
fUART
SPI
1
UART frequency.
⁄65024fclk(uart)
-
1⁄2fclk(uart) MHz
1
1
fSPI
SPI operating
frequency.
Master operation.
Slave operation.
⁄
65024fclk(spi)
65024fclk(spi)
-
-
1⁄2fclk(spi) MHz
1⁄4fclk(spi) MHz
⁄
Jitter Specification
[2]
CANtjit(cc)(p-p)
CAN TXD pin
-
0.4
1
ns
Cycle-to-cycle jitter
(peak-to-peak value).
[1] All parameters are guaranteed over the virtual junction temperature range by design. Pre-testing is performed at Tamb = 125 °C ambient
temperature on wafer level. Cased products are tested at Tamb = 25 °C (final testing). Both pre-testing and final testing use correlated
test conditions to cover the specified temperature and power supply voltage range.
[2] This parameter is not part of production testing or final testing, hence only a typical value is stated.
[3] Oscillator start-up time depends on the quality of the crystal. For most crystals it takes about 1000 clock pulses until the clock is fully
stable.
[4] Duty cycle clock should be as close as possible to 50%.
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13. Package outline
LQFP144: plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm
SOT486-1
y
X
A
108
109
73
72
Z
E
e
H
A
E
2
A
E
(A )
3
A
1
θ
w M
p
L
p
b
L
pin 1 index
detail X
37
144
1
36
v M
Z
A
w M
D
b
p
e
D
B
H
v M
B
D
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
θ
1
2
3
p
E
p
D
E
max.
7o
0o
0.15 1.45
0.05 1.35
0.27 0.20 20.1 20.1
0.17 0.09 19.9 19.9
22.15 22.15
21.85 21.85
0.75
0.45
1.4
1.1
1.4
1.1
mm
1.6
0.25
1
0.2 0.08 0.08
0.5
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
00-03-14
03-02-20
SOT486-1
136E23
MS-026
Fig 15. Package outline SOT486-1 (LQFP144)
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14. Soldering
14.1 Introduction
There is no soldering method that is ideal for all surface mount IC packages. Wave
soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is recommended.
14.2 Through-hole mount packages
14.2.1 Soldering by dipping or by solder wave
Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 °C
or 265 °C, depending on solder material applied, SnPb or Pb-free respectively.
The total contact time of successive solder waves must not exceed 5 seconds.
The device may be mounted up to the seating plane, but the temperature of the plastic
body must not exceed the specified maximum storage temperature (Tstg(max)). If the
printed-circuit board has been pre-heated, forced cooling may be necessary immediately
after soldering to keep the temperature within the permissible limit.
14.2.2 Manual soldering
Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the
seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is
less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is
between 300 °C and 400 °C, contact may be up to 5 seconds.
14.3 Surface mount packages
14.3.1 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 16) than a PbSn process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 32 and 33
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Table 32. SnPb eutectic process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
≥ 350
220
< 2.5
235
220
≥ 2.5
220
Table 33. Lead-free process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
260
350 to 2000
> 2000
260
< 1.6
260
250
245
1.6 to 2.5
> 2.5
260
245
250
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 16.
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 16. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
14.3.2 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices
(SMDs) or printed-circuit boards with a high component density, as solder bridging and
non-wetting can present major problems.
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To overcome these problems the double-wave soldering method was specifically
developed.
If wave soldering is used the following conditions must be observed for optimal results:
• Use a double-wave soldering method comprising a turbulent wave with high upward
pressure followed by a smooth laminar wave.
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be
parallel to the transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the
transport direction of the printed-circuit board.
The footprint must incorporate solder thieves at the downstream end.
• For packages with leads on four sides, the footprint must be placed at a 45° angle to
the transport direction of the printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
During placement and before soldering, the package must be fixed with a droplet of
adhesive. The adhesive can be applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the adhesive is cured.
Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 °C
or 265 °C, depending on solder material applied, SnPb or Pb-free respectively.
A mildly-activated flux will eliminate the need for removal of corrosive residues in most
applications.
14.3.3 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage
(24 V or less) soldering iron applied to the flat part of the lead. Contact time must be
limited to 10 seconds at up to 300 °C.
When using a dedicated tool, all other leads can be soldered in one operation within
2 seconds to 5 seconds between 270 °C and 320 °C.
14.4 Package related soldering information
Table 34. Suitability of IC packages for wave, reflow and dipping soldering methods
Mounting
Package[1]
Soldering method
Wave
Reflow[2]
Dipping
Through-hole mount
CPGA, HCPGA
suitable
−
−
DBS, DIP, HDIP, RDBS, SDIP, SIL suitable[3]
−
suitable
Through-hole-surface
mount
PMFP[4]
not suitable
not suitable
−
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Table 34. Suitability of IC packages for wave, reflow and dipping soldering methods …continued
Mounting
Package[1]
Soldering method
Wave
Reflow[2]
Dipping
Surface mount
BGA, HTSSON..T[5], LBGA,
LFBGA, SQFP, SSOP..T[5],
TFBGA, VFBGA, XSON
not suitable
suitable
−
DHVQFN, HBCC, HBGA, HLQFP, not suitable[6]
HSO, HSOP, HSQFP, HSSON,
HTQFP, HTSSOP, HVQFN,
suitable
−
HVSON, SMS
PLCC[7], SO, SOJ
suitable
suitable
−
−
−
−
LQFP, QFP, TQFP
not recommended[7][8]
not recommended[9]
not suitable
suitable
SSOP, TSSOP, VSO, VSSOP
CWQCCN..L[10], WQCCN..L[10]
suitable
not suitable
[1] For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your NXP
Semiconductors sales office.
[2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with
respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of
the moisture in them (the so called popcorn effect).
[3] For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.
[4] Hot bar soldering or manual soldering is suitable for PMFP packages.
[5] These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed
through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 °C ± 10 °C
measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible.
[6] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate
between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the
heatsink surface.
[7] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint
must incorporate solder thieves downstream and at the side corners.
[8] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for
packages with a pitch (e) equal to or smaller than 0.65 mm.
[9] Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely
not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
[10] Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil.
However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate
soldering profile can be provided on request.
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15. Abbreviations
Table 35. Abbreviations list
Abbreviation
Description
AHB
BCL
Advanced High-performance Bus
Buffer Control List
BDL
Buffer Descriptor List
CISC
DTL
Complex Instruction Set Computers
Device Transaction Level
SFSP
SCL
SCU Function Select Port x,y (use without the P if there are no x,y)
Slot Control List
BEL
Buffer Entry List
CCO
BIST
RISC
UART
VPB
Current Controlled Oscillator
Built-In Self Test
Reduced Instruction Set Computer
Universal Asynchronous Receiver Transmitter
VLSI Peripheral bus
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16. References
[1] UM — LPC2917/19 user manual
[2] ARM — ARM web site
[3] ARM-SSP — ARM primecell synchronous serial port (PL022) technical reference
manual
[4] CAN — ISO 11898-1: 2002 road vehicles - Controller Area Network (CAN) - part 1:
data link layer and physical signalling
[5] LIN — LIN specification package, revision 2.0
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17. Revision history
Table 36. Revision history
Document ID
LPC2917_19_1.01
Modifications
Release date
<tbd>
Data sheet status
Change notice
Supersedes
Preliminary data sheet
LPC2915_17_19_1
• Part LPC2915 removed
• Editorial updates
20070917 Preliminary data sheet
LPC2915_17_19_1
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18. Legal information
18.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
result in personal injury, death or severe property or environmental damage.
18.2 Definitions
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
18.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
18.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of a NXP Semiconductors product can reasonably be expected to
I2C-bus — logo is a trademark of NXP B.V.
19. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: [email protected]
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20. Contents
1
8.3.2
Event-router pin description and mapping to
8.3.2.1
8.3.2.2
8.3.2.3
8.3.3
8.3.3.1
8.3.3.2
8.3.3.3
8.3.4
2
3
4
5
8.3.4.1
8.3.4.2
8.3.4.3
register bit positions. . . . . . . . . . . . . . . . . . . . 23
8.4.2
6
8.4.2.1
8.4.2.2
8.4.2.3
8.4.2.4
8.4.3
8.4.3.1
8.4.3.2
8.4.3.3
8.4.3.4
8.4.4
8.4.4.1
8.4.4.2
8.4.4.3
8.4.4.4
8.4.5
8.4.5.1
8.4.5.2
8.4.5.3
8.4.5.4
8.4.5.5
8.4.6
8.4.6.1
8.4.6.2
8.4.6.3
8.4.6.4
8.5
8.5.1
8.5.2
8.5.3
8.6
7
7.1.3
IEEE 1149.1 interface pins (JTAG boundary-scan
test). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
8
External static-memory controller pin
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
External static-memory controller clock
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8.2.3
8.2.4
8.6.1
8.6.2
continued >>
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8.7.2.1
Synchronization and trigger features of the
14.2
MSCSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9
11
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2007.
All rights reserved.
For sales office addresses, please send an email to: [email protected]
Date of release: 15 November 2007
Document identifier: LPC2917_19_1
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