STK14CA8
128Kx8 AutoStore™ nvSRAM
Features
Description
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25, 35, 45 ns Read Access and Read/Write Cycle Time
Unlimited Read/Write Endurance
The Cypress STK14CA8 is a 1 Mb fast static RAM with a nonvol-
atile QuantumTrap™ storage element included with each
memory cell. This SRAM provides fast access and cycle times,
ease of use, and unlimited read and write endurance of a normal
SRAM.
Automatic Nonvolatile STORE on Power Loss
Nonvolatile STORE Under Hardware or Software Control
Automatic RECALL to SRAM on Power Up
Unlimited RECALL Cycles
Data transfers automatically to the nonvolatile storage cells
when power loss is detected (the STORE operation). On power
up, data is automatically restored to the SRAM (the RECALL
operation). Both STORE and RECALL operations are also
available under software control.
200K STORE Cycles
The Cypress nvSRAM is the first monolithic nonvolatile memory
to offer unlimited writes and reads. It is the highest performing
and most reliable nonvolatile memory available.
20-Year Nonvolatile Data Retention
Single 3.0V + 20%, -10% Operation
Commercial and Industrial Temperatures
Small Footprint SOIC and SSOP Packages (RoHS Compliant)
Logic Block Diagram
VCC
VCAP
Quantum Trap
1024 X 1024
A5
A6
A7
A8
POWER
CONTROL
STORE
RECALL
STORE/
RECALL
CONTROL
STATIC RAM
ARRAY
A9
A12
A13
A14
A15
A16
HSB
1024 X 1024
SOFTWARE
DETECT
A15 – A0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
COLUMN I/O
COLUMN DEC
A0 A1 A2 A3 A4 A10 A11
G
E
W
Cypress Semiconductor Corporation
Document Number: 001-51592 Rev. **
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 04, 2009
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STK14CA8
NF (SOP-32) PACKAGE THERMAL CHARACTERISTICS
θjc 5.4 C/W; θja 44.3 [0fpm], 37.9 [200fpm], 35.1 C/W [500fpm].
RF (SSOP-48) PACKAGE THERMAL CHARACTERISTICS
θjc 6.2 C/W; θja 51.1 [0fpm], 44.7 [200fpm], 41.8 C/W [500fpm].
Absolute Maximum Ratings
Voltage on Input Relative to Ground.................–0.5V to 4.1V
Voltage on Input Relative to VSS...........–0.5V to (VCC + 0.5V)
Voltage on DQ0-7 or HSB......................–0.5V to (VCC + 0.5V)
Temperature under Bias ............................... –55°C to 125°C
Junction Temperature................................... –55°C to 140°C
Storage Temperature.................................... –65°C to 150°C
Power Dissipation............................................................. 1W
DC Output Current (1 output at a time, 1s duration).... 15mA
Maximum Ratings may cause permanent damage to the device.
This is a stress rating only, and functional operation of the device
at conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
DC Characteristics
(VCC = 2.7V to 3.6V)
Commercial
Industrial
Symbol
Parameter
Units
Notes
Min
Max
Min
Max
ICC
Average VCC Current
65
55
50
70
60
55
mA tAVAV = 25 ns
mA tAVAV = 35 ns
1
mA
tAVAV = 45 ns
Dependent on output loading and cycle
rate. Values obtained without output loads.
ICC
Average VCC Current during
STORE
3
3
mA All Inputs Don’t Care, VCC = max
Average current for duration of STORE
2
cycle (tSTORE
)
ICC
Average VCC Current at tAVAV
200 ns
3V, 25°C, Typical
=
10
10
mA
W
≥
(V CC– 0.2V)
3
All Other Inputs Cycling at CMOS Levels
Dependent on output loading and cycle
rate. Values obtained without output loads.
ICC
Average VCAP Current during
AutoStore Cycle
3
3
3
3
mA All Inputs Don’t Care
4
Average current for duration of STORE
cycle (tSTORE
≥ (VCC -0.2V)
All Others VIN≤ 0.2V or
)
ISB
VCC Standby Current
(Standby, Stable CMOS Levels)
mA
E
≥
(VCC-0.2V)
Standby current level after nonvolatile
cycle complete
IILK
Input Leakage Current
±1
±1
±1
±1
μA VCC = max
V
IN = VSS to VCC
IOLK
Off-State Output Leakage
Current
μA VCC = max
VIN = VSS to VCC, E or G
≥
VIH
VIH
Input Logic “1” Voltage
Input Logic “0” Voltage
Output Logic “1” Voltage
Output Logic “0” Voltage
Operating Temperature
Operating Voltage
2.0
VSS–0.5
2.4
VCC+0.3
0.8
2.0
VSS–0.5
2.4
VCC+0.3
0.8
V
V
V
V
All Inputs
VIL
All Inputs
VOH
VOL
TA
IOUT =– 2 mA
IOUT = 4 mA
0.4
70
0.4
85
0
–40
2.7
17
°C
VCC
VCAP
NVC
2.7
17
3.6
120
3.6
120
V
3.3V + 0.3V
Storage Capacitance
μF Between VCAP pin and VSS, 5V rated.
Nonvolatile STORE operations
200
20
200
20
K
DATAR Data Retention
Years At 55
°C
Note The HSB pin has IOUT=-10 uA for VOH of 2.4 V, this parameter is characterized but not tested.
Document Number: 001-51592 Rev. **
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STK14CA8
AC Test Conditions
Input Pulse Levels ....................................................0V to 3V
Input Rise and Fall Times ................................................. ≤ 5 ns
Input and Output Timing Reference Levels .................... 1.5V
Capacitance
(TA = 25°C, f = 1.0 MHz)
Symbol
CIN
Input Capacitance
Output Capacitance
Max Units
Conditions
ΔV = 0 to 3V
ΔV = 0 to 3V
7
7
pF
pF
COUT
Figure 4. AC Output Loading
3.0V
577 Ohms
OUTPUT
30 pF
789 Ohms
INCLUDING
SCOPE AND
FIXTURE
Figure 5. AC Output Loading for Tristate Specifications
(tHZ, tLZ, tWLQZ, tWHQZ, tGLQX, tGHQZ
)
3.0V
577 Ohms
OUTPUT
5 pF
789 Ohms
INCLUDING
SCOPE AND
FIXTURE
Note
2. These parameters are guaranteed but not tested.
Document Number: 001-51592 Rev. **
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STK14CA8
SRAM READ Cycles #1 and #2
Symbols
NO.
STK14CA8-25 STK14CA8-35 STK14CA8-45
Parameter
Units
#1
#2
tELQV
Alt.
tACS
Min
Max
Min
Max
Min
Max
Chip Enable Access Time
Read Cycle Time
25
35
45
ns
ns
ns
ns
ns
ns
1
2
3
4
5
6
[3]
[3]
tAVAV
tELEH
tRC
tAA
tOE
tOH
tLZ
25
35
45
[4]
[4]
tAVQV
tAVQV
Address Access Time
25
12
35
15
45
20
tGLQV
tAXQX
tELQX
Output Enable to Data Valid
Output Hold after Address Change
[4]
[4]
[5]
[5]
tAXQX
3
3
3
3
3
3
Address Change or Chip Enable to
Output Active
tEHQZ
tHZ
Address Change or Chip Disable to
Output Inactive
10
13
15
ns
7
tGLQX
tOLZ
tOHZ
tPA
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
0
0
0
0
0
0
ns
ns
ns
ns
8
9
tGHQZ
10
25
13
35
15
45
[2]
tELICCH
tEHICCL
10
11
[2]
tPS
AVAV
t
ADDRESS
AVQV
t
t
AXQX
DQ (DATA OUT)
DATA VALID
Notes
3. W must be high during SRAM READ cycles.
4. Device is continuously selected with E and G both low
5. Measured ± 200mV from steady state output voltage.
6. HSB must remain high during READ and WRITE cycles
Document Number: 001-51592 Rev. **
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STK14CA8
SRAM WRITE Cycles #1 and #2
Symbols
NO.
STK14CA8-25 STK14CA8-35 STK14CA8-45
Parameter
Units
#1
#2
Alt.
Min
25
20
20
10
0
Max
Min
35
25
25
12
0
Max
Min
45
30
30
15
0
Max
tAVAV
tAVAV
tWC Write Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
12
13
14
15
16
17
18
19
20
21
tWLWH
tELWH
tDVWH
tWHDX
tAVWH
tAVWL
tWHAX
tWLEH
tELEH
tDVEH
tEHDX
tAVEH
tAVEL
tEHAX
tWP Write Pulse Width
tCW Chip Enable to End of Write
tDW Data Setup to End of Write
tDH Data Hold after End of Write
tAW Address Setup to End of Write
tAS Address Setup to Start of Write
tWR Address Hold after End of Write
tWZ Write Enable to Output Disable
tOW Output Active after End of Write
20
0
25
0
30
0
0
0
0
tWLQZ
tWHQX
10
13
15
3
3
3
AVAV
t
ADDRESS
E
WHAX
ELWH
t
t
AVWH
t
AVWL
t
WLWH
t
W
DVWH
WHDX
t
t
DATA IN
DATA IN
DATA VALID
WLQZ
t
WHQX
t
HIGH IMPEDANCE
DATA OUT
PREVIOUS DATA
AVAV
t
ADDRESS
AVEL
ELEH
EHAX
t
t
E
AVEH
t
WLEH
t
W
DVEH
EHDX
t
t
DATA IN
DATA VALID
HIGH IMPEDANCE
DATA OUT
Notes
7. If W is low when E goes low, the outputs remain in the high impedance state.
8. E or W must be ≥ VIH during address transitions.
Document Number: 001-51592 Rev. **
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STK14CA8
AutoStore/POWER UP RECALL
Symbols
NO.
STK14CA8
Min Max
20
Parameter
Power up RECALL Duration
Units
Notes
Standard Alternate
tHRECALL
tSTORE
VSWITCH
VCCRISE
ms
ms
V
22
23
24
25
tHLHZ
STORE Cycle Duration
Low Voltage Trigger Level
VCC Rise Time
12.5
2.65
150
μs
t
Figure 10. AutoStore/POWER UP RECALL
Note Read and Write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH.
Notes
9.
t
starts from the time V rises above V
HRECALL CC SWITCH
10. If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE takes place
11. Industrial Grade devices require maximum 15 ms.
Document Number: 001-51592 Rev. **
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STK14CA8
Software Controlled STORE/RECALL Cycle
Symbols
STK14CA8-35 STK14CA8-35 STK14CA8-45
NO.
Units Notes
E Cont G Cont Alt
Min
Max
Min
Max
Min
Max
tAVAV
tAVAV
tRC
STORE/RECALL Initiation Cycle
Time
25
35
45
ns
26
tAVEL
tELEH
tEHAX
tAVGL
tGLGH tCW
tGHAX
tAS
Address Setup Time
Clock Pulse Width
Address Hold Time
RECALL Duration
0
20
1
0
25
1
0
30
1
ns
ns
ns
μs
27
28
29
30
tRECALL tRECALL
50
50
50
Notes
12. The software sequence is clocked on the falling edge of E controlled READs or G controlled READs
13. The six consecutive addresses must be read in the order listed in the Software STORE/RECALL Mode Selection Table. W must be high during all six consecutive cycles.
Document Number: 001-51592 Rev. **
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STK14CA8
Hardware STORE Cycle
Symbols
NO.
STK14CA8
Parameter
Units
Notes
Standard Alternate
Min
1
Max
tDELAY
tHLHX
tHLQZ
Hardware STORE to SRAM Disabled
Hardware STORE Pulse Width
70
μs
14
31
32
15
ns
Figure 13. Hardware STORE Cycle
Soft Sequence Commands
Symbols
NO.
Parameter
STK14CA8 Units
Min Max
Notes
Standard
tSS
Soft Sequence Processing Time
70
μs
33
Figure 14. Software Sequence Commands
Notes
14. On a hardware STORE initiation, SRAM operation continues to be enabled for time t
to allow read/write cycles to complete.
DELAY
15. This is the amount of time that it takes to take action on a soft sequence command. Vcc power must remain high to effectively register command.
16. Commands such as Store and Recall lock out I/O until operation is complete which further increases this time. See specific command.
Document Number: 001-51592 Rev. **
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STK14CA8
Mode Selection
E
H
L
W
X
H
L
G
X
L
A16-A0
Mode
I/O
Power
Standby
Active
Notes
X
X
X
Not Selected
Read SRAM
Write SRAM
Output High Z
Output Data
Input Data
L
X
L
Active
L
H
0x04E38
0x0B1C7
0x083E0
0x07C1F
0x0703F
0x08B45
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active
AutoStore Disable
L
L
H
H
L
L
0x04E38
0x0B1C7
0x083E0
0x07C1F
0x0703F
0x04B46
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active
AutoStore Enable
0x04E38
0x0B1C7
0x083E0
0x07C1F
0x0703F
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Active
0x08FC0
Nonvolatile Store
Output High Z
ICC2
L
H
L
0x04E38
0x0B1C7
0x083E0
0x07C1F
0x0703F
0x04C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
Nonvolatile Recall
Notes
17. The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle.
18. While there are 17 addresses on the STK14CA8, only the lower 16 are used to control software modes
19. I/O state depends on the state of G. The I/O table shown assumes G low
Document Number: 001-51592 Rev. **
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STK14CA8
pin is driven to 5V by a charge pump internal to the chip. A pull
up should be placed on W to hold it inactive during power up.
nvSRAM Operation
nvSRAM
To reduce unneeded nonvolatile stores, AutoStore and
Hardware Store operations are ignored unless at least one
WRITE operation has taken place since the most recent STORE
or RECALL cycle. Software initiated STORE cycles are
performed regardless of whether a WRITE operation has taken
place. The HSB signal can be monitored by the system to detect
an AutoStore cycle is in progress.
The STK14CA8 nvSRAM has two functional components paired
in the same physical cell. These are the SRAM memory cell and
a nonvolatile QuantumTrap cell. The SRAM memory cell
operates similar to a standard fast static RAM. Data in the SRAM
can be transferred to the nonvolatile cell (the STORE operation),
or from the nonvolatile cell to SRAM (the RECALL operation).
This unique architecture allows all cells to be stored and recalled
in parallel. During the STORE and RECALL operations, SRAM
READ and WRITE operations are inhibited. The STK14CA8
supports unlimited read and writes similar to a typical SRAM. In
addition, it provides unlimited RECALL operations from the
nonvolatile cells and up to 200K STORE operations.
Figure 15. AutoStore Mode
VCC
VCAP
VCC
SRAM READ
The STK14CA8 performs a READ cycle whenever E and G are
low while W and HSB are high. The address specified on pins
W
A
0-16 determine which of the 131,072 data bytes are accessed.
When the READ is initiated by an address transition, the outputs
are valid after a delay of tAVQV (READ cycle #1). If the READ is
initiated by E and G, the outputs are valid at tELQV or at tGLQV
,
whichever is later (READ cycle #2). The data outputs repeatedly
responds to address changes within the tAVQV access time
without the need for transitions on any control input pins, and
remains valid until another address change or until E or G is
brought high, or W and HSB is brought low.
SRAM WRITE
Hardware STORE (HSB) Operation
A WRITE cycle is performed whenever E and W are low and HSB
is high. The address inputs must be stable prior to entering the
WRITE cycle and must remain stable until either E or W goes
high at the end of the cycle. The data on the common I/O pins
DQ0-7 are written into memory if it is valid tDVWH before the end
of a W controlled WRITE or tDVEH before the end of an E
controlled WRITE.
The STK14CA8 provides the HSB pin for controlling and
acknowledging the STORE operations. The HSB pin is used to
request a hardware STORE cycle. When the HSB pin is driven
low, the STK14CA8 conditionally initiates a STORE operation
after tDELAY. An actual STORE cycle only begins if a WRITE to
the SRAM took place since the last STORE or RECALL cycle.
The HSB pin has a very resistive pull up and is internally driven
low to indicate a busy condition while the STORE (initiated by
any means) is in progress. This pin should be externally pulled
up if it is used to drive other inputs.
It is recommended that G be kept high during the entire WRITE
cycle to avoid data bus contention on common I/O lines. If G is
left low, internal circuitry turns off the output buffers tWLQZ after
W goes low.
SRAM READ and WRITE operations that are in progress when
HSB is driven low by any means are given time to complete
before the STORE operation is initiated. After HSB goes low, the
AutoStore Operation
The STK14CA8 stores data to nvSRAM using one of three
storage operations. These three operations are Hardware Store
(activated by HSB), Software Store (activated by an address
sequence), and AutoStore (on power down).
STK14CA8 continues to allow SRAM operations for tDELAY
.
During tDELAY, multiple SRAM READ operations may take place.
If a WRITE is in progress when HSB is pulled low, it is allowed a
time tDELAY to complete. However, any SRAM WRITE cycles
requested after HSB goes low are inhibited until HSB returns
high.
AutoStore operation is a unique feature of Cypress Quantum
Trap technology is enabled by default on the STK14CA8.
If HSB is not used, it should be left unconnected.
During normal operation, the device draws current from VCC to
charge a capacitor connected to the VCAP pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the VCC pin drops below VSWITCH, the part
automatically disconnects the VCAP pin from VCC. A STORE
operation is initiated with power provided by the VCAP capacitor.
Hardware RECALL (Power Up)
During power up or after any low power condition
(VCC<VSWITCH), an internal RECALL request is latched. When
VCC again exceeds the sense voltage of VSWITCH, a RECALL
cycle is automatically initiated and takes tHRECALL to complete.
Figure 15 shows the proper connection of the storage capacitor
Document Number: 001-51592 Rev. **
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STK14CA8
Software STORE
Data Protection
Data can be transferred from the SRAM to the nonvolatile
memory by a software address sequence. The STK14CA8
software STORE cycle is initiated by executing sequential E
controlled or G controlled READ cycles from six specific address
locations in exact order. During the STORE cycle, previous data
is erased and then the new data is programmed into the nonvol-
atile elements. After a STORE cycle is initiated, further memory
inputs and outputs are disabled until the cycle is completed.
The STK14CA8 protects data from corruption during low voltage
conditions by inhibiting all externally initiated STORE and
WRITE operations. The low voltage condition is detected when
VCC<VSWITCH.
If the STK14CA8 is in a WRITE mode (both E and W low) at
power up, after a RECALL, or after a STORE, the WRITE is
inhibited until a negative transition on E or W is detected. This
protects against inadvertent writes during power up or brown out
conditions.
To initiate the software STORE cycle, the following READ
sequence must be performed:
Noise Considerations
Read Address
Read Address
Read Address
Read Address
Read Address
Read Address
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8FC0
Valid READ
The STK14CA8 is a high speed memory and so must have a high
frequency bypass capacitor of approximately 0.1 µF connected
between VCC and VSS, using leads and traces that are a short
as possible. As with all high speed CMOS ICs, careful routing of
power, ground, and signals reduce circuit noise.
Valid READ
Valid READ
Valid READ
Valid READ
Best Practices
Initiate STORE Cycle
nvSRAM products have been used effectively for over 15 years.
While ease-of-use is one of the product’s main system values,
experience gained working with hundreds of applications has
resulted in the following suggestions as best practices:
When the sixth address in the sequence is entered, the STORE
cycle commences and the chip is disabled. It is important that
READ cycles and not WRITE cycles be used in the sequence
and that G is active. After the tSTORE cycle time is fulfilled, the
SRAM is again activated for READ and WRITE operation.
■
The nonvolatile cells in an nvSRAM are programmed on the
test floor during final test and quality assurance. Incoming
inspection routines at customer or contract manufacturer’s
sites sometimes reprograms these values. Final NV patterns
are typically repeating patterns of AA, 55, 00, FF, A5, or 5A.
End product’s firmware should not assume an NV array is in a
set programmed state. Routines that check memory content
values to determine first time system configuration, cold or
warm boot status, etc. should always program a unique NV
pattern (for example, complex 4-byte pattern of 46 E6 49 53
hex or more random bytes) as part of the final system manufac-
turing test to ensure these system routines work consistently.
Software RECALL
Data can be transferred from the nonvolatile memory to the
SRAM by a software address sequence. A software RECALL
cycle is initiated with a sequence of READ operations in a
manner similar to the software STORE initiation. To initiate the
RECALL cycle, the following sequence of E controlled or G
controlled READ operations must be performed:
Read Address
Read Address
Read Address
Read Address
Read Address
Read Address
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4C63
Valid READ
Valid READ
■
Power up boot firmware routines should rewrite the nvSRAM
into the desired state such as AutoStore enabled. While the
nvSRAM is shipped in a preset state, best practice is to again
rewrite the nvSRAM into the desired state as a safeguard
against events that might flip the bit inadvertently (program
bugs, incoming inspection routines, and so on.)
Valid READ
Valid READ
Valid READ
Initiate RECALL Cycle
■
■
IfAutoStoreisfirmwaredisabled, itdoesnotresetto“AutoStore
enabled”oneverypowerdowneventcapturedbythenvSRAM.
The application firmware should re-enable or re-disable
AutoStore on each reset sequence based on the behavior
desired.
Internally, RECALL is a two-step procedure. First, the SRAM
data is cleared, and second, the nonvolatile information is trans-
ferred into the SRAM cells. After the tRECALL cycle time, the
SRAM is again ready for READ or WRITE operations. The
RECALL operation in no way alters the data in the nonvolatile
storage elements.
The Vcap value specified in this data sheet includes a minimum
and a maximum value size. Best practice is to meet this
requirement and not exceed the max Vcap value because the
nvSRAM internal algorithm calculates Vcap charge time based
on this max Vcap value. Customers that want to use a larger
Vcap value to make sure there is extra store charge and store
time should discuss their Vcap size selection with Cypress to
understand any impact on the Vcap voltage level at the end of
a tRECALL period.
Document Number: 001-51592 Rev. **
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STK14CA8
Low Average Active Power
Preventing AutoStore
CMOS technology provides the STK14CA8 with the benefit of
power supply current that scales with cycle time. Less current is
drawn as the memory cycle time becomes longer than 50 ns.
READ/WRITE cycle time. Worst case current consumption is
shown for commercial temperature range, VCC=3.6V, and chip
enable at maximum frequency. Only standby current is drawn
when the chip is disabled. The overall average current drawn by
the STK14CA8 depends on the following items:
The AutoStore function can be disabled by initiating an
AutoStore Disable sequence. A sequence of READ operations
is performed in a manner similar to the software STORE initi-
ation. To initiate the AutoStore Disable sequence, the following
sequence of E controlled or G controlled READ operations must
be performed:
Read Address
Read Address
Read Address
Read Address
Read Address
Read Address
0x4E38
0xB1C7 Valid READ
0x83E0 Valid READ
0x7C1F Valid READ
Valid READ
1. The duty cycle of chip enable
2. The overall cycle rate for operations
3. The ratio of READs to WRITEs
4. The operating temperature
5. The VCC Level
0x703F
0x8B45
Valid READ
AutoStore Disable
6. I/O Loading
The AutoStore can be re-enabled by initiating an AutoStore
Enable sequence. A sequence of READ operations is performed
in a manner similar to the software RECALL initiation. To initiate
the AutoStore Enable sequence, the following sequence of E
controlled or G controlled READ operations must be performed:
Figure 16. Current vs Cycle Time
Read Address
Read Address
Read Address
Read Address
Read Address
Read Address
0x4E38
0xB1C7 Valid READ
0x83E0 Valid READ
0x7C1F Valid READ
Valid READ
0x703F
0x4B46
Valid READ
AutoStore Enable
If the AutoStore function is disabled or re-enabled, a manual
STORE operation (Hardware or Software) must be issued to
save the AutoStore state through subsequent power down
cycles. The part comes from the factory with AutoStore enabled.
Document Number: 001-51592 Rev. **
Page 13 of 16
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STK14CA8
Ordering Information
STK14CA8-R F 45 ITR
Packing Option
Blank=Tube
TR=Tape and Reel
Temperature Range
Blank=Commercial (0 to +70 C)
I= Industrial (-45 to +85 C)
Access Time
25=25 ns
35=35 ns
45=45 ns
Lead Finish
F=100% Sn (Matte Tin) RoHS Compliant
Package
N=Plastic 32-pin 300 mil SOIC (50 mil pitch)
R=Plastic 48-pin 300 mil SSOP (25 mil pitch)
Ordering Codes
Part Number
Description
Access Times Temperature
STK14CA8-NF25
3V 128Kx8 AutoStore nvSRAM SOP32-300
3V 128Kx8 AutoStore nvSRAM SOP32-300
25 ns
35 ns
45 ns
25 ns
35 ns
45 ns
25 ns
35 ns
45 ns
25 ns
35 ns
45 ns
25 ns
35 ns
45 ns
25 ns
35 ns
45 ns
25 ns
35 ns
45 ns
25 ns
35 ns
45 ns
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Industrial
STK14CA8-NF35
STK14CA8-NF45
3V 128Kx8 AutoStore nvSRAM SOP32-300
3V 128Kx8 AutoStore nvSRAM SOP32-300
3V 128Kx8 AutoStore nvSRAM SOP32-300
3V 128Kx8 AutoStore nvSRAM SOP32-300
3V 128Kx8 AutoStore nvSRAM SSOP48-300
3V 128Kx8 AutoStore nvSRAM SSOP48-300
3V 128Kx8 AutoStore nvSRAM SSOP48-300
3V 128Kx8 AutoStore nvSRAM SSOP48-300
3V 128Kx8 AutoStore nvSRAM SSOP48-300
3V 128Kx8 AutoStore nvSRAM SSOP48-300
3V 128Kx8 AutoStore nvSRAM SOP32-300
3V 128Kx8 AutoStore nvSRAM SOP32-300
3V 128Kx8 AutoStore nvSRAM SOP32-300
3V 128Kx8 AutoStore nvSRAM SOP32-300
3V 128Kx8 AutoStore nvSRAM SOP32-300
3V 128Kx8 AutoStore nvSRAM SOP32-300
3V 128Kx8 AutoStore nvSRAM SSOP48-300
3V 128Kx8 AutoStore nvSRAM SSOP48-300
3V 128Kx8 AutoStore nvSRAM SSOP48-300
3V 128Kx8 AutoStore nvSRAM SSOP48-300
3V 128Kx8 AutoStore nvSRAM SSOP48-300
3V 128Kx8 AutoStore nvSRAM SSOP48-300
STK14CA8-NF25TR
STK14CA8-NF35TR
STK14CA8-NF45TR
STK14CA8-RF25
STK14CA8-RF35
STK14CA8-RF45
STK14CA8-RF25TR
STK14CA8-RF35TR
STK14CA8-RF45TR
STK14CA8-NF25I
STK14CA8-NF35I
STK14CA8-NF45I
STK14CA8-NF25ITR
STK14CA8-NF35ITR
STK14CA8-NF45ITR
STK14CA8-RF25I
STK14CA8-RF35I
STK14CA8-RF45I
STK14CA8-RF25ITR
STK14CA8-RF35ITR
STK14CA8-RF45ITR
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Document Number: 001-51592 Rev. **
Page 14 of 16
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STK14CA8
Document History Page
Document Title: STK14CA8 128Kx8 AutoStore™ nvSRAM
Document Number: 001-51592
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
**
2665610
GVCH/PYRS
02/04/09 New data sheet
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© Cypress Semiconductor Corporation, 2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical
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application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
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Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-51592 Rev. **
Revised March 04, 2009
Page 16 of 16
AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor Corporation. All other products and company names mentioned in this document may be the trademarks of their
respective holders.
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