Intel® LXD972M Transceiver
Demo Board (Board Rev A1)
Preliminary User’s Guide
October 2004
Document Number: 303125
Revision Number: 002
Revision Date: October 22, 2004
Contents
Contents
1.0 Introduction......................................................................................................................................5
Related Documents ..............................................................................................................5
Features of Intel® LXD972M Demo Board............................................................................6
2.0 Using the Intel® LXD972M Demo Board .........................................................................................7
Equipment Requirements .....................................................................................................7
Typical Test Setup ................................................................................................................8
Configurations.....................................................................................................................11
2.4.2 Power Supply Voltage Source and Clock Options.................................................12
2.4.3 MDIO Configuration Options..................................................................................13
2.4.4 LED Configuration Options ....................................................................................13
2.4.5 CFG Pin Configuration Options .............................................................................14
JTAG Test Signals..............................................................................................................14
3.0 Intel® LXD972M Demo Board Schematics....................................................................................15
4.0 Bill of Materials ..............................................................................................................................20
Figures
Typical Test Setup .......................................................................................................................8
Intel® LXD972M Transceiver Demo Board ................................................................................10
Optional Test Setup ...................................................................................................................11
Schematic: Intel® LXD972M Transceiver Demo Board Power Control ......................................16
Schematic: Intel® LXD972M Transceiver Demo Board MII Port.................................................17
Schematic: Intel® LXD972M Transceiver Demo Board Twisted-Pair Port..................................18
Schematic: Intel® LXD972M Transceiver Demo Board Configuration........................................19
Tables
Quick-Start Checklist for Jumper Settings....................................................................................9
Power Supply Voltage Source Connector Options.....................................................................12
Magnetic Center-Tap Voltage Source Configuration Options.....................................................12
Analog Power Supply (VCCA) Configuration Options ................................................................12
Clock Configuration Options.......................................................................................................13
MDIO Configuration Options.......................................................................................................13
Jumper Configuration Settings for LED/CFG Pins......................................................................14
10 JTAG Test Signal Descriptions...................................................................................................14
11 Bill of Materials ...........................................................................................................................20
Preliminary User’s Guide
3
Document Number: 303125
Revision Number: 002
Revision Date: October 22, 2004
Contents
Revision History
Revision Number 002
Revision Date: October 2004
Page
Description
Revision Number 001
Revision Date: July 2004
Page
Description
Initial release.
4
Preliminary User’s Guide
Document Number: 303125
Revision Number: 002
Revision Date: October 22, 2004
Intel® LXD972M Transceiver Demo Board (Board Rev A1)
1.0
Introduction
This document describes the typical hardware set-up procedures for the Intel® LXD972M
Transceiver Demo Board (called hereafter the LXD972M Demo Board). The LXD972M Demo
Board is a platform for evaluation of the Intel LXT972M Single-Port 10/100 Mbps PHY
Transceiver (called hereafter the LXT972M Transceiver).
The LXD972M Demo Board allows system designers to test the following:
• 10 Mbps and 100 Mbps link performance
• Auto-negotiation
• Register functionality
The LXD972M Demo Board requires only a single 3.3V power supply.
1.1
1.2
About this Demo Board Kit
This Demo Board kit includes the following:
• LXD972M Demo Board
• Intel® LXD972M Transceiver Demo Board (Board Rev A1) User’s Guide
Related Documents
Table 1. Related Documents
Document
Document Number
Intel® LXT972M Single-Port 10/100 Mbps PHY Transceiver Datasheet
302875
Intel® LXT971A, LXT972A, LXT972M Single-Port 10/100 Mbps PHY Transceivers
Specification Update
249354
Preliminary User’s Guide
5
Document Number: 303125
Revision Number: 002
Revision Date: October 22, 2004
Intel® LXD972M Transceiver Demo Board (Board Rev A1)
1.3
Features of Intel® LXD972M Demo Board
• 3.3V operation, with option for 2.5V I/O voltage
• Low power consumption (300 mW typical)
• Quick setup and clear visibility of application settings for complete system demonstration
• Auto-negotiation protocol compliant. Compatible with systems not supporting auto-
negotiation.
• LED indicators for major functions
• JTAG boundary scan port
• Configurable through MDIO port or hardware jumpers
• Standard half-duplex or full-duplex operation at 10 Mbps or 100 Mbps
6
Preliminary User’s Guide
Document Number: 303125
Revision Number: 002
Revision Date: October 22, 2004
Intel® LXD972M Transceiver Demo Board (Board Rev A1)
2.0
Using the Intel® LXD972M Demo Board
This document includes information on the following items concerning using the LXD972M Demo
Board:
2.1
Equipment Requirements
The LXD972M Demo Board is populated with all components needed for twisted-pair evaluation.
However, the following additional equipment is also required:
• SmartBits Advanced Multi-port Performance Test Box configured with firmware version 4.39
or newer
• PC with Smart Windows (version 6.0 or newer) installed
• One MII Cable (male to male)
• One external NIC card
• One Category 5 Unshielded Twisted-Pair (UTP) crossover cable
• External power supply
Preliminary User’s Guide
7
Document Number: 303125
Revision Number: 002
Revision Date: October 22, 2004
Intel® LXD972M Transceiver Demo Board (Board Rev A1)
2.2
Typical Test Setup
Figure 1 shows a typical test setup for standard operation of the LXD972M Demo Board.
The LXD972M Demo Board plugs into a SmartBits Advanced Performance Test Box through a
standard 40-pin MII cable (not included with the LXD972M Demo Board). The LXD972M Demo
Board RJ-45 jack connects to the RJ-45 card in the SmartBits test box through a Twisted-Pair
cable. Operation can be set for evaluation of 10 Mbps, 100 Mbps, and auto-negotiation capabilities.
Figure 1. Typical Test Setup
Computer with
Smart Windows
SmartBits
Advanced Multi-port
RS-232
Performance
Tester
RJ-45 Card
or
External NIC Cards
MII
Cards
MII Cables
MII
Connectors
Twisted Pair
Crossover
Cable
LXD972M
LXT972M
B3570-03
8
Preliminary User’s Guide
Document Number: 303125
Revision Number: 002
Revision Date: October 22, 2004
Intel® LXD972M Transceiver Demo Board (Board Rev A1)
2.3
Quick-Start Checklists
Use the quick-start checklists in this section to set up the LXD972M Demo Board, shown in Figure
The following quick-start setup procedure sets all ports to the default condition, which includes
Auto-Negotiation enabled, advertising dual-speed, and full-duplex/half-duplex capabilities.
The following jumpers are defined as follows: LED1 has the functionality of LED/CFG1,
LED2 has the functionality of LED/CFG2, and CFG has the functionality of LED/CFG3 as
defined by the LXT972M Transceiver datasheet.
3. Connect the MII port of the LXD972M Demo Board to the Smartbits test box through the MII
connector/cable. A male-to-male cable is required to interface the Smartbits test box to the
LXD972M Demo Board and is available from Newark* (.5m cable - Newark 91F9746).
4. Connect the twisted-pair port through a Twisted-Pair crossover cable to the RJ-45 card in the
SmartBits test box.
5. Power up the Smartbits test box.
6. When the LXD972M Demo Board is configured according to desired test settings, apply the
and Clock Options” on page 12 and press Reset switch S2.
7. Proceed with testing.
Table 2. Quick-Start Checklist for Jumper Settings
Jumper
Label
Setting
Configuration
JP1,
JP2,
JP3
LED1,
LED2,
CFG
"Sets Port Configuration to 111 for Auto-Negotiation,
Pins 1, 2
Routes power from VCCD connector (BN4) through
JP12 to the VCCA input.
JP12
VCCA
Jumpered
JP16
JP17
MDIO
MDC
Pins 2, 3
Pins 2, 3
Pins 1, 2
Jumper Routes MDIO through MII 40-pin Connector P1.
Jumper Routes MDC through MII 40-pin Connector P1.
Open
Disables output of clock oscillator Y2.
JP18
JP19
Clock Select
Reset
Pins 3, 4
Pins 5, 6
Jumper
Jumper
Connects crystal across XI and XO to enable Y1.
Pins 1,2
Jumper Connects reset button
Table 3. Quick-Start Checklist for Switch Settings
Switch / Label
SW1-1 / ID EN
Setting
Configuration
Off
Off
Off
Off
Not applicable for LXT972M Transceiver.
Sets ADDR0 = 0 (“Off” position)
SW1-2 / ADDR0
SW1-3 / ADDR1
Sets ADDR1 = 0 (“Off” position)
SW1-4 / LINKHOLD / RBIAS
Not applicable for LXT972M Transceiver.
Preliminary User’s Guide
9
Document Number: 303125
Revision Number: 002
Revision Date: October 22, 2004
Intel® LXD972M Transceiver Demo Board (Board Rev A1)
Figure 2. Intel® LXD972M Transceiver Demo Board
SILKSCREEN TOP
BOARD ID
SERIAL #
B3798-001
one of the following:
• For leaded: LXD972M Rev.A1
• For lead-free: LXD972MLF Rev.A1
either one of the following:
• For leaded: 972M-xxxx-A1
• For lead-free: 972MLF-xxxx-A1
10
Preliminary User’s Guide
Document Number: 303125
Revision Number: 002
Revision Date: October 22, 2004
Intel® LXD972M Transceiver Demo Board (Board Rev A1)
2.4
Configurations
2.4.1
Optional Test Setup, Using Two Intel® LXD972M Demo Boards
Figure 3 shows an optional test setup using two LXD972M Demo Boards. Each Demo Board plugs
into a SmartBits Advanced Performance Test Box through standard 40-pin MII cables. The two
LXD972M Demo Boards are linked through a Twisted-Pair crossover cable connected to the RJ-45
jack on each board. Operation can be set for evaluation of 10 Mbps, 100 Mbps, and auto-
negotiation capabilities.
Figure 3. Optional Test Setup
Computer with
Smart Windows
SmartBits
Advanced Multi-port
RS-232
Performance
Tester
MII
Cards
MII Cable
MII
MII
Connector
Connector
LXD972M
LXD972M
LXT972M
LXT972M
RJ-45
RJ-45
Twisted-Pair
Crossover
Cable
B3572-05
Preliminary User’s Guide
11
Document Number: 303125
Revision Number: 002
Revision Date: October 22, 2004
Intel® LXD972M Transceiver Demo Board (Board Rev A1)
2.4.2
Power Supply Voltage Source and Clock Options
Table 4. Power Supply Voltage Source Connector Options
Reference
Designators
Signal
Supply Description
+3.3V.
BN1
BN2
BN3
VCC
GND
For components on the LXD972M Demo Board other than LXT972M Transceiver.
Ground
+3.3V or +2.5V.
VCCIO
I/O voltage for the LXT972M Transceiver.
+3.3V.
BN4
VCCD
LXT972M digital power. If JP12 jumper is on, analog power is provided for the
LXT972M Transceiver.
transmit magnetic center-tap voltage.
Table 5. Magnetic Center-Tap Voltage Source Configuration Options
Desired
Power Supply Source
Setting
Description
3.3V Power Supply from
VCCA
Jumper
JP4
Use Jumper JP4 to apply 3.3V power from VCCA for center-tap
operation.
Ope n
JP4
Use Jumper JP4 to supply either 2.5V or 3.3V power supply for
center-tap operation. Connect the power supply to pin 2 of JP4.
Alternate Power Supply
Table 6. Analog Power Supply (VCCA) Configuration Options
Desired
Configuration
Setting
Description
3.3V Power
Supply to VCCA
Jumper Use Jumper JP12 to route power from the VCCD Power Connector
JP12
(BN4) through JP12 to the VCCA input of the LXT972M Transceiver.
1. Remove jumper from JP12 to disable for VCCA input.
2. Apply external power from an alternate power supply through
pin 2 of JP12. For power supply requirements, see the LXT972M
Transceiver datasheet.
Analog
External Power
Supply to VCCA
Open
JP12
12
Preliminary User’s Guide
Document Number: 303125
Revision Number: 002
Revision Date: October 22, 2004
Intel® LXD972M Transceiver Demo Board (Board Rev A1)
Table 7. Clock Configuration Options
Desired
JP18 Settings
Configuration
Description
Remove jumper from pins 1 and 2 to disable the clock oscillator Y2
output.
Pins 11, 2
Open
Enable Crystal
Oscillator Y1
Pins 3, 4
Pins 5, 6
Place a jumper on pins 3 and 4 and pins 5 and 6, which connects a
crystal across XI and XO to enable Y1.
Jumper
Place a jumper on pins 1 and 2, which enables the output of clock
oscillator Y2.
Pins 1, 2 Jumper
Enable Clock
Oscillator Y2
Pins 3, 4
Open
Pins 5, 6
Remove jumper from pins 3 and 4, and remove jumper from pins 5
and 6, which disables a crystal connection across XI and XO to Y1.
1. Pin 1 is located on the lower-right corner of JP18.
2.4.3
MDIO Configuration Options
The default configuration of the MDIO and MDC signals is to route the MDIO through the MII
connector to the SmartBits Test Box by installing jumpers JP16 and JP17.
Note: The RJ-11 feature is not supported. As a result, do not jumper the MDIO and MDC signals to the
RJ-11 connector.
Table 8. MDIO Configuration Options
Desired Configuration
Jumper
Setting
Description
JP16
JP17
JP16
JP17
Jumper Pins 2, 3
Jumper Pins 2, 3
Jumper Pins 1, 2
Jumper Pins 1, 2
Routes MDIO through 40-pin MII Connector P1
Routes MDC through 40-pin MII Connector P1
Routes MDIO through RJ-11 Connector J2
Routes MDC through RJ-11 Connector J2
Route MDIO and MDC
through MII
Route MDIO and MDC
through RJ-11
2.4.4
LED Configuration Options
The LXD972M Demo Board provides three programmable LEDs. Each LED can display one of
several available status conditions as selected by the LED Configuration Register (Address 20).
Programmable LEDs (LED/CFG1, LED/CFG2, LED/CFG3) are set in default mode and are
programmable with the MDIO pin. Register address 20 also provides optional LED pulse
stretching up to 100 ms. Register bits 20.3:2 select one of three possible stretch times. (For details,
see the LXT972M Transceiver datasheet.)
Note: The active LED state is determined by the CFG pin function. When the LED/CFG pin is pulled
High, the LED becomes active Low. When the LED/CFG pin is pulled Low, the LED becomes
active High.
Preliminary User’s Guide
13
Document Number: 303125
Revision Number: 002
Revision Date: October 22, 2004
Intel® LXD972M Transceiver Demo Board (Board Rev A1)
2.4.5
CFG Pin Configuration Options
Three control jumpers pull the associated port configuration pins High or Low to select the desired
mode (auto-negotiation, speed, and duplex). When auto-negotiation is enabled with LED/CFG1
(JP1) = 1, then LED/CFG2 (JP2), and LED/CFG3 (JP3) are used to configure default advertising
characteristics of the LXD972M Demo Board. The desired modes and jumper configuration
Transceiver datasheet.
Table 9. Jumper Configuration Settings for LED/CFG Pins
Mode
Jumper Settings
JP1
LED/CFG1
Setting
JP2
LED/CFG2
Setting
JP3
LED/CFG3
Setting
Auto-
Negotiation
Speed Duplex
Half
Pins 2 & 3
Pins 2 & 3
Pins 2 & 3
Pins 1 & 2
Pins 1 & 2
Pins 2 & 3
10
Full
Pins 2 & 3
Pins 2 & 3
Pins 2 & 3
Pins 1 & 2
Pins 1 & 2
Pins 2 & 3
Pins 1 & 2
Pins 2 & 3
Disabled
Half
100
Full
Half
Pins 2 & 3
Pins 2 & 3
Pins 1 & 2
Pins 1 & 2
Jumper
Jumper
Jumper
100
Full /
Half
Pins 1 & 2
Pins 1 & 2
Pins 1 & 2
Pins 1 & 2
Pins 2 & 3
Pins 1 & 2
Enabled
Half
10/100
Full /
Half
2.5
JTAG Test Signals
JTAG test signal descriptions.
Table 10. JTAG Test Signal Descriptions
JP14 Pin
Symbol
Number
Description
1
3
5
7
8
TRST_L Test Reset. Test reset input sourced by testing device.
TCK
TMS
TDO
TDI
Test Clock. Test clock input sourced by testing device.
Test Mode Select.
Test Data Output. Test data driven with respect to the falling edge of TCK.
Test Data Input. Test data sampled with respect to the rising edge of TCK.
14
Preliminary User’s Guide
Document Number: 303125
Revision Number: 002
Revision Date: October 22, 2004
Intel® LXD972M Transceiver Demo Board (Board Rev A1)
3.0
Intel® LXD972M Demo Board Schematics
This section includes schematics for the LXD972M Demo Board:
Note: Page 1 of 5 of the schematics is not included (the title page of the schematics).
Preliminary User’s Guide
15
Document Number: 303125
Revision Number: 002
Revision Date: October 22, 2004
Intel® LXD972M Transceiver Demo Board (Board Rev A1)
Figure 4. Schematic: Intel® LXD972M Transceiver Demo Board Power Control
1
1
C V C A
1
1
C V C A
C V C D
G N D A
1 3
1 6
3 9
G N D D
3 8
O
O
C V C I
C V C I
O
O
O
G N D I
G N D I
G N D I
2 9
6
3 0
9
5
1
16
Preliminary User’s Guide
Document Number: 303125
Revision Number: 002
Revision Date: October 22, 2004
Intel® LXD972M Transceiver Demo Board (Board Rev A1)
Figure 5. Schematic: Intel® LXD972M Transceiver Demo Board MII Port
1
T P 4 3
1
T P 4 2
1
T P 4 1
X
X
X
X
X
R 8 1
R 8 0
R 7 9
R 7 8
R 7 7
1
T P 2 2
1
T P 2 1
1
T P 2 0
1
T P 1 9
1
T P 1 8
1
T P 3 0
1
1
T P 1 7
T P 2 9
T P 2 8
1
1
T P 1 6
1
T P 2 7
1
1
T P 1 5
T P 2 6
1
T P 2 5
1
T P 2 4
C
V C
G N D
1 0
2 0
C
V C
G N D
1 0
2 0
Preliminary User’s Guide
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Document Number: 303125
Revision Number: 002
Revision Date: October 22, 2004
Intel® LXD972M Transceiver Demo Board (Board Rev A1)
4.0
Bill of Materials
Table 11. Bill of Materials (Sheet 1 of 3)
Board Reference
Description
Manufacturer
Part Number
Quantity
Designator
CONN BANANA NUT
SILVER (BANANA_NUT)
BN1-4
EF JOHNSON
108-0740-001
4
C1, C2, C5, C8, C9, C11,
C13, C38-C42, C45, C46
LABELS NOT USED IN SCHEMATIC.
C3, C6, C10, C14-16,
C50-51
HEADER 3X1 (SIP\3P)
BERG
BERG
AVX
08055C104KATMA
ECU-V1H102JCX
08055C103KATMA
X
8
4
2
1
5
4
HEADER 4X2
(HEADER2X4)
C4, C7, C12, C52
C17, C49
CAP 0.01uF X7R 10%
(0805)
C53 (NOT INSTALLED)
C18, C47-48, C58-59
C31, C34, C54, C56
NOT INSTALLED
CAP 1000pF 20% 2KV X7R
(1812)
AVX
1812GC102KAT1A
ECS-TOJY106R
CAP 10uF 6.3V TANT
(CASEA)
PANASONIC
C32-33
CAP 18pF 50V 5% (0805)
CAP 100uF 6.3V (CASED)
CAP 20PF 50V 5% (1206)
CAP 270pF NPO (1206)
PANASONIC
PANASONIC
PANASONIC
AVX
ECU-V1H180JCN
ECE-V0JA101P
ECU-V1H200JCM
12061A271JATTA
2
3
1
2
C36, C55, C57
C37
C43-44
DIODE RECTIFIER DL4001
1A 50V MELF SMD
D1
DIODES INC.
DL4001-13
1
DIODE LED GREEN SS
TYPE LOW CUR SMD
(LED\SMD\SS)
D2-D8
PANASONIC
BERG
LNJ308G8LRA
68000-240-2
7
7
DTP1-4, JP4, JP12, JP19
FB1, FB2
HEADER 2X1 (SIP\2P)
LABELS NOT USED IN SCHEMATIC.
FBEAD 60 OHM@100MHZ
0.10OHM@DC 1.5A (1210) STEWARD
(BEAD3225)
FB3-5
MI1210K600R-00
3
FB6 (NOT INSTALLED)
J1
NOT INSTALLED
X
1
1
CONN MOD JACK 8-8
AMP
555164-1
LOW PROFILE
CONN MOD JACK 6-6
J2
J3
RJ11 UNSHIELDED
BLOCK RJ11-6L-B
CORCOM
RJ11-6L-B
1
1
CONN SMB VERTICAL PC JOHNSON
MOUNT (SMB\SM) COMPONENTS
131-3711-201
20
Preliminary User’s Guide
Document Number: 303125
Revision Number: 002
Revision Date: October 22, 2004
Intel® LXD972M Transceiver Demo Board (Board Rev A1)
Table 11. Bill of Materials (Sheet 2 of 3)
Board Reference
Designator
Description
Manufacturer
Part Number
Quantity
JP5-JP11, JP13, JP15
LABELS NOT USED IN SCHEMATIC.
JP1-3, JP16-17
HEADER 3X1 (SIP\3P)
BERG
BERG
BERG
AMP
68000-240-3
C9192-280-4
C9192-280-3
787171-4
5
1
1
1
HEADER 4X2
(HEADER2X4)
JP14
JP18
P1
HEADER 3X2
CONN MII 40 PIN FEMALE
R/A (CON40F\RT\4ROW)
RES 182 OHM 1/8W 1%
(1206) SMD
R1-3
PANASONIC
PANASONIC
ERJ-8ENF1820V
ERJ-8ENF49R9V
3
R4-9, R12-13, R23-25,
R27, R29, R31, R33, R35,
R40-44, R46-47, R70,
R76, R82, R83
RES 49.9 1/8W 1% (1206)
27
R26, R28, R30, R32, R34, RES 22 OHM 1/8W 1%
9C08052A22R0FK
HFT
YAGEO AMERICA
PANASONIC
10
5
R36-38, R45, R48
(0805)
R58, R60-62, R66
RES 4.7K 1/8W 5% (1206)
ERJ-8GEYJ472V
ERJ-8ENF1003V
RES 100K 1/8W 1% (1206)
SMD
R65
R67
PANASONIC
1
RES 10K 1/8W 1% (1206)
NOTE: R3 is shown as 180
Ohm resistor in
PANASONIC
PANASONIC
ERJ-8ENF1002V
1
schematic.
RES 100 OHM 1/8W 1%
(1206)
R68
R69
R72
ERJ-8ENF1000V
ERJ-8ENF2212V
ERJ-8GEYJ221V
1
1
1
RES 22.1K 1/8W 1% (1206) PANASONIC
RES 220 OHM 1/8W 5%
PANASONIC
(1206)
R73, R75, R77-R82 (NOT
INSTALLED)
NOT INSTALLED
X
8
R10, R11, R14-22, R39,
R49-57, R59, R63-64, R71
LABELS NOT USED IN SCHEMATIC.
RES 0 OHM 1/8W 5%
PANASONIC
R74
S2
ERJ-8GEY0R00V
KT11P2JM
1
1
(1206) SMD
SWITCH PB MOM KEY J-
C&K
LEAD SMD
COMPONENTS
(SWITCH\RESET\SM)
SWITCH DIP 4 POS THRU
SW1
T1
HOLE SEALED BLACK
(SWITCH\8)
AMP
4-435166-9
1
IC XFMR TG110-S050N2
16 PIN SOIC
HALO
BERG
TG110-S050N2
68000-240-1
1
TP2-5, TP15-22, TP24-30,
TP34-43
HEADER 1X1
29
Preliminary User’s Guide
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Document Number: 303125
Revision Number: 002
Revision Date: October 22, 2004
Intel® LXD972M Transceiver Demo Board (Board Rev A1)
Table 11. Bill of Materials (Sheet 3 of 3)
Board Reference
Designator
Description
Manufacturer
Part Number
Quantity
TP1, TP6-14, TP23,
TP31-33
LABELS NOT USED IN SCHEMATIC.
IC LOGIC 74LVC244 LOW
TEXAS
U1, U3
VOLTAGE BUFFER 20 PIN
SN74LVC244ADW
LXT977/LXT972M
2
1
INSTRUMENTS
SOIC
IC PHY LXT977/LXT972M
DUAL PORT (LQFP48C)
U2
U4
INTEL
LABELS NOT USED IN SCHEMATIC.
IC LOGIC 74LVX14 HEX
SCHMITT TRIG INV 14 PIN TOSHIBA
SOIC
U5
TC74LVX14FN
1
CRYSTAL 25.000MHZ
(HC49)
Y1
Y2
CTS
MP250
1
1
OSC 25.000MHZ FULL
SIZE ( )
CTS
MX045-25.0000
22
Preliminary User’s Guide
Document Number: 303125
Revision Number: 002
Revision Date: October 22, 2004
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