Cypress Perform CY62167E MoBL User Manual

CY62167E MoBL®  
16-Mbit (1M x 16 / 2M x 8) Static RAM  
(CE HIGH, or CE LOW, or both BHE and BLE are HIGH).  
Features  
1
2
The input and output pins (IO through IO ) are placed in a  
0
15  
• Configurable as 1M x 16 or as 2M x 8 SRAM  
• Very high speed: 45 ns  
high impedance state when:  
• The device is deselected (CE HIGH or CE LOW)  
1
2
• Wide voltage range: 4.5V–5.5V  
• Outputs are disabled (OE HIGH)  
• Ultra low standby power  
• Both Byte High Enable and Byte Low Enable are disabled  
(BHE, BLE HIGH) or  
— Typical standby current: 1.5 µA  
— Maximum standby current: 12 µA  
• Ultra low active power  
• A write operation is in progress (CE LOW, CE HIGH, and  
1
2
WE LOW)  
To write to the device, take Chip Enables (CE LOW and CE  
1
2
— Typical active current: 2.2 mA @ f = 1 MHz  
• Easy memory expansion with CE , CE , and OE features  
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable  
(BLE) is LOW, then data from IO pins (IO through IO ), is  
0
7
1
2
written into the location specified on the address pins (A  
0
• Automatic power down when deselected  
• CMOS for optimum speed and power  
• Offered in 48-pin TSOP I package  
through A ). If Byte High Enable (BHE) is LOW, then data  
19  
from the IO pins (IO through IO ) is written into the location  
8
15  
specified on the address pins (A through A ).  
0
19  
To read from the device, take Chip Enables (CE LOW and  
Functional Description[1]  
1
CE HIGH) and Output Enable (OE) LOW while forcing the  
2
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,  
then data from the memory location specified by the address  
The CY62167E is a high performance CMOS static RAM  
organized as 1M words by 16 bits/2M words by 8 bits. This  
device features advanced circuit design to provide an ultra low  
active current. This is ideal for providing More Battery Life™  
pins appears on IO to IO . If Byte High Enable (BHE) is LOW,  
0
7
then data from memory appears on IO to IO . See the “Truth  
8
15  
Table” on page 10 for a complete description of read and write  
modes.  
®
(MoBL ) in portable applications such as cellular telephones.  
The device also has an automatic power down feature that  
reduces power consumption by 99% when addresses are not  
toggling. Place the device into standby mode when deselected  
Logic Block Diagram  
DATA IN DRIVERS  
A
A
A
A
A
A
A
10  
9
8
7
6
1M × 16 / 2M x 8  
5
4
3
2
1
0
IO –IO  
0
7
RAM ARRAY  
A
IO –IO  
8
15  
A
A
A
COLUMN DECODER  
BYTE  
BHE  
WE  
CE2  
CE2  
CE  
1
POWER DOWN  
CIRCUIT  
CE  
1
OE  
BHE  
BLE  
BLE  
Note  
1. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.  
Cypress Semiconductor Corporation  
Document #: 001-15607 Rev. *A  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised June 07, 2007  
 
CY62167E MoBL®  
DC Input Voltage  
........................................–0.5V to 6.0V  
Maximum Ratings  
Output Current into Outputs (LOW) ............................ 20 mA  
Exceeding the maximum ratings may shorten the battery life  
of the device. User guidelines are not tested.  
Static Discharge Voltage........................................... >2001V  
(MIL-STD-883, Method 3015)  
Storage Temperature ................................65°C to + 150°C  
Latch Up Current .....................................................>200 mA  
Ambient Temperature with  
Power Applied............................................55°C to + 125°C  
Operating Range  
Supply Voltage to Ground  
Ambient  
Potential........................................................... –0.5V to 6.0V  
Device  
Range  
V
CC  
Temperature  
DC Voltage Applied to Outputs  
CY62167ELL  
Industrial –40°C to+85°C 4.5V to 5.5V  
in High-Z State  
........................................... –0.5V to 6.0V  
Electrical Characteristics  
Over the Operating Range  
45 ns  
Parameter  
Description  
Test Conditions  
= –1.0 mA  
Unit  
Min  
Typ  
Max  
V
Output HIGH Voltage  
Output LOW Voltage  
Input HIGH Voltage  
Input LOW Voltage  
I
I
2.4  
V
V
OH  
OL  
IH  
OH  
V
V
V
I
= 2.1mA  
0.4  
OL  
V
V
= 4.5V to 5.5V  
= 4.5V to 5.5V  
2.2  
–0.5  
–1  
V
+ 0.5V  
V
CC  
CC  
CC  
0.7  
+1  
V
IL  
Input Leakage Current  
Output Leakage Current  
GND < V < V  
CC  
µA  
µA  
mA  
mA  
IX  
I
I
I
GND < V < V , Output Disabled  
–1  
+1  
30  
OZ  
O
CC  
V
Operating Supply  
f = f  
= 1/t  
V
= V (max)  
= 0 mA  
25  
CC  
CC  
MAX  
RC  
CC  
CC  
Current  
I
OUT  
f = 1 MHz  
2.2  
4.0  
CMOS levels  
Automatic CE Power Down CE > V – 0.2V or CE < 0.2V,  
1.5  
12  
µA  
I
1
CC  
2
SB2  
Current—CMOS Inputs  
V
> V – 0.2V or V < 0.2V,  
IN  
CC  
CC  
IN  
f = 0, V  
=
V
CC(max)  
Capacitance[10]  
Parameter  
Description  
Test Conditions  
Max  
10  
Unit  
C
C
Input Capacitance  
Output Capacitance  
T = 25°C, f = 1 MHz,  
pF  
pF  
IN  
A
V
= V  
CC  
CC(typ)  
10  
OUT  
Thermal Resistance[10]  
Parameter  
Description  
Test Conditions  
TSOP I  
Unit  
Θ
Thermal Resistance  
(junction to ambient)  
Still air, soldered on a 3 × 4.5 inch, two-layer printed circuit  
board  
60  
°C/W  
JA  
Θ
Thermal Resistance  
(junction to case)  
4.3  
°C/W  
JC  
Notes  
5. V (min) = –2.0V for pulse durations less than 20 ns.  
IL  
6.  
V
(max) = V + 0.75V for pulse durations less than 20 ns.  
IH CC  
7. Full Device AC operation is based on a 100 µs ramp time from 0 to V (min) and 200 µs wait time after V stabilization.  
CC  
CC  
8. Under DC conditions the device meets a V of 0.8V. However, in dynamic conditions Input LOW Voltage applied to the device must not be higher than 0.7V.  
IL  
9. Only chip enables (CE and CE ), byte enables (BHE and BLE) and BYTE need to be tied to CMOS levels to meet the I / I spec. Other inputs can be  
SB2 CCDR  
1
2
left floating.  
10. Tested initially and after any design or process changes that may affect these parameters.  
Document #: 001-15607 Rev. *A  
Page 3 of 12  
           
CY62167E MoBL®  
AC Test Loads and Waveforms  
R1  
ALL INPUT PULSES  
90%  
10%  
V
V
CC  
CC  
90%  
OUTPUT  
10%  
GND  
FALL TIME= 1 V/ns  
R2  
30 pF  
RISE TIME= 1 V/ns  
INCLUDING  
JIG AND  
SCOPE  
EQUIVALENT TO: THÉVENIN EQUIVALENT  
R
TH  
OUTPUT  
V
Parameters  
Values  
Unit  
R1  
R2  
1800  
990  
R
639  
TH  
V
1.77  
V
TH  
Data Retention Characteristics  
Over the Operating Range  
Parameter  
Description  
for Data Retention  
CC  
Conditions  
Min  
Typ  
Max  
Unit  
V
V
I
V
2.0  
DR  
[9]  
Data Retention Current  
V
= V  
DR  
12  
µA  
CCDR  
CC  
CE > V – 0.2V, CE < 0.2V,  
1
CC  
2
V
> V – 0.2V or V < 0.2V  
IN  
CC  
IN  
t
t
Chip Deselect to Data  
Retention Time  
0
ns  
ns  
CDR  
Operation Recovery  
Time  
t
RC  
R
Data Retention Waveform[12]  
DATA RETENTION MODE  
V
(min)  
> 2.0 V  
V
V
t
(min)  
CC  
V
CC  
DR  
CC  
t
CDR  
R
CE  
or  
1
.
BHE BLE  
or  
CE  
2
Notes  
11. Full device operation requires linear V ramp from V to V (min) > 100 µs or stable at V (min) > 100 µs.  
CC  
DR  
CC  
CC  
12. BHE. BLE is the AND of BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling BHE and BLE.  
Document #: 001-15607 Rev. *A  
Page 4 of 12  
     
CY62167E MoBL®  
Switching Characteristics  
Over the Operating Range  
45 ns  
Unit  
Parameter  
Description  
Min  
45  
Max  
READ CYCLE  
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
RC  
Address to Data Valid  
45  
AA  
Data Hold from Address Change  
CE LOW and CE HIGH to Data Valid  
10  
OHA  
ACE  
DOE  
LZOE  
HZOE  
LZCE  
HZCE  
PU  
45  
22  
1
2
OE LOW to Data Valid  
OE LOW to LOW-Z  
5
10  
0
OE HIGH to High-Z  
CE LOW and CE HIGH to Low-Z  
18  
18  
1
2
CE HIGH and CE LOW to High-Z  
1
2
CE LOW and CE HIGH to Power Up  
1
2
CE HIGH and CE LOW to Power Down  
45  
45  
PD  
1
2
BLE/BHE LOW to Data Valid  
DBE  
LZBE  
HZBE  
BLE/BHE LOW to Low-Z  
10  
BLE/BHE HIGH to HIGH-Z  
18  
WRITE CYCLE  
t
t
t
t
t
t
t
t
t
t
t
Write Cycle Time  
45  
35  
35  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
WC  
CE LOW and CE HIGH to Write End  
SCE  
AW  
1
2
Address Setup to Write End  
Address Hold from Write End  
Address Setup to Write Start  
WE Pulse Width  
HA  
0
SA  
35  
35  
25  
0
PWE  
BW  
BLE/BHE LOW to Write End  
Data Setup to Write End  
Data Hold from Write End  
SD  
HD  
WE LOW to High-Z  
18  
HZWE  
LZWE  
WE HIGH to Low-Z  
10  
Notes  
13. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 V/ns, timing reference levels of V (typ)/2, input pulse levels  
CC  
of 0 to V (typ), and output loading of the specified I /I as shown in “AC Test Loads and Waveforms” on page 4.  
CC  
OL OH  
14. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification.  
15. At any temperature and voltage condition, t is less than t , t is less than t , t is less than t , and t is less than t for any device.  
HZCE  
LZCE HZBE  
LZBE HZOE  
LZOE  
HZWE  
LZWE  
16. t  
, t  
, t  
, and t  
transitions are measured when the outputs enter a high impedance state.  
HZOE HZCE HZBE  
HZWE  
17. The internal write time of the memory is defined by the overlap of WE, CE = V , BHE or BLE or both = V , and CE = V . All signals must be active to initiate  
1
IL  
IL  
2
IH  
a write and any of these signals can terminate a write by going inactive. The data input setup and hold timing should be referenced to the edge of the signal that  
terminates the write.  
Document #: 001-15607 Rev. *A  
Page 5 of 12  
         
CY62167E MoBL®  
Switching Waveforms  
Figure 1 shows address transition controlled read cycle waveforms.  
Figure 1. Read Cycle No. 1  
t
RC  
ADDRESS  
DATA OUT  
t
AA  
t
OHA  
PREVIOUS DATA VALID  
DATA VALID  
Figure 2 shows OE controlled read cycle waveforms.  
Figure 2. Read Cycle No. 2  
ADDRESS  
tRC  
CE1  
CE2  
tPD  
t
HZCE  
tACE  
BHE/BLE  
OE  
tDBE  
tHZBE  
tLZBE  
tHZOE  
tDOE  
tLZOE  
HIGH  
IMPEDANCE  
HIGH IMPEDANCE  
DATA OUT  
VCC  
SUPPLY  
CURRENT  
DATA VALID  
tLZCE  
ICC  
ISB  
tPU  
50%  
50%  
Notes  
18. The device is continuously selected. OE, CE = V , BHE, BLE or both = V , and CE = V .  
IH  
1
IL  
IL  
2
19. WE is HIGH for read cycle.  
20. Address valid before or similar to CE , BHE, BLE transition LOW and CE transition HIGH.  
1
2
Document #: 001-15607 Rev. *A  
Page 6 of 12  
         
CY62167E MoBL®  
Switching Waveforms (continued)  
Figure 3 shows WE controlled write cycle waveforms.  
Figure 3. Write Cycle No. 1  
tWC  
ADDRESS  
CE1  
tSCE  
CE2  
tAW  
tHA  
tSA  
tPWE  
WE  
tBW  
BHE/BLE  
OE  
tHD  
tSD  
DATA IO  
VALID DATA  
tHZOE  
Notes  
21. Data IO is high impedance if OE = V  
.
IH  
22. If CE goes HIGH and CE goes LOW simultaneously with WE = V , the output remains in a high impedance state.  
1
2
IH  
23. During this period the IOs are in output state and input signals must not be applied.  
Document #: 001-15607 Rev. *A  
Page 7 of 12  
       
CY62167E MoBL®  
Switching Waveforms (continued)  
Figure 4 shows CE or CE controlled write cycle waveforms.  
1
2
Figure 4. Write Cycle No. 2  
tWC  
ADDRESS  
CE1  
tSCE  
CE2  
tSA  
tAW  
tHA  
tPWE  
WE  
tBW  
BHE/BLE  
OE  
tHD  
tSD  
DATA IO  
VALID DATA  
tHZOE  
Figure 5 shows WE controlled, OE LOW write cycle waveforms.  
Figure 5. Write Cycle No. 3  
tWC  
ADDRESS  
CE1  
tSCE  
CE2  
tBW  
BHE/BLE  
tAW  
tHA  
tSA  
tPWE  
WE  
tSD  
tHD  
DATA IO  
VALID DATA  
tLZWE  
t
HZWE  
Document #: 001-15607 Rev. *A  
Page 8 of 12  
   
CY62167E MoBL®  
Switching Waveforms (continued)  
Figure 6 shows BHE/BLE controlled, OE LOW write cycle waveforms.  
Figure 6. Write Cycle No. 4  
tWC  
ADDRESS  
CE1  
CE2  
tSCE  
tAW  
tHA  
tBW  
BHE/BLE  
WE  
tSA  
tPWE  
tSD  
VALID DATA  
tHD  
DATA IO  
Document #: 001-15607 Rev. *A  
Page 9 of 12  
 
CY62167E MoBL®  
Truth Table  
CE  
H
X
CE  
WE  
X
OE  
X
BHE  
X
BLE  
X
Inputs Outputs  
High-Z  
Mode  
Power  
1
2
X
Deselect/Power Down  
Deselect/Power Down  
Deselect/Power Down  
Read  
Standby (I  
Standby (I  
Standby (I  
)
SB  
L
X
X
X
X
High-Z  
High-Z  
)
SB  
X
X
X
X
H
H
)
SB  
L
H
H
H
L
L
L
Data Out (IO –IO  
)
Active (I  
Active (I  
)
CC  
0
15  
L
H
L
H
L
Data Out (IO –IO );  
Read  
)
CC  
0
7
High-Z (IO –IO  
)
8
15  
L
H
H
L
L
H
High-Z (IO –IO );  
Read  
Active (I  
)
CC  
0
7
Data Out (IO –IO  
)
8
15  
L
L
L
L
L
H
H
H
H
H
H
H
H
L
H
H
H
X
X
L
H
L
H
L
L
L
L
High-Z  
High-Z  
High-Z  
Output Disabled  
Output Disabled  
Output Disabled  
Write  
Active (I  
Active (I  
Active (I  
Active (I  
Active (I  
)
CC  
)
CC  
)
CC  
L
Data In (IO –IO  
)
)
CC  
0
15  
L
H
Data In (IO –IO );  
High-Z (IO –IO  
Write  
)
CC  
0
7
)
8
15  
L
H
L
X
L
H
High-Z (IO –IO );  
Write  
Active (I  
)
CC  
0
7
Data In (IO –IO  
)
8
15  
Ordering Information  
Speed  
(ns)  
Package  
Diagram  
Operating  
Range  
Package Type  
Ordering Code  
45  
CY62167ELL-45ZXI  
51-85183 48-pin TSOP I (Pb-free)  
Industrial  
Document #: 001-15607 Rev. *A  
Page 10 of 12  
 
CY62167E MoBL®  
Package Diagram  
Figure 7. 48-Pin TSOP I (12 mm x 18.4 mm x 1.0 mm), 51-85183  
DIMENSIONS IN INCHES[MM] MIN.  
MAX.  
JEDEC # MO-142  
0.037[0.95]  
0.041[1.05]  
N
1
0.020[0.50]  
TYP.  
0.472[12.00]  
0.007[0.17]  
0.011[0.27]  
0.002[0.05]  
0.006[0.15]  
0.724 [18.40]  
0.787[20.00]  
0.047[1.20]  
MAX.  
0.004[0.10]  
0.008[0.21]  
0.010[0.25]  
GAUGE PLANE  
0.020[0.50]  
0.028[0.70]  
51-85183-*A  
0°-5°  
Document #: 001-15607 Rev. *A  
Page 11 of 12  
© Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be  
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its  
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their  
respective holders.  
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and  
foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create  
derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only  
in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except  
as specified above is prohibited without the express written permission of Cypress.  
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WAR-  
RANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein.  
Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in  
life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application  
implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Use may be limited by and subject to the applicable Cypress software license agreement.  
CY62167E MoBL®  
Document History Page  
®
Document Title: CY62167E MoBL 16-Mbit (1M x 16 / 2M x 8) Static RAM  
Document Number: 001-15607  
Orig. of  
REV.  
ECN NO. Issue Date  
Change  
Description of Change  
New Data Sheet  
**  
1103145  
1138903  
See ECN  
See ECN  
VKN  
*A  
VKN  
Converted from preliminary to final  
Changed I  
Changed I  
Changed I  
spec from 2.8 mA to 4.0 mA for f=1MHz  
CC(max)  
spec from 22 mA to 25 mA for f=f  
CC(typ)  
max  
spec from 25 mA to 30 mA for f=f  
CC(max)  
max  
Added footnote# 8 related to V  
IL  
Changed I  
spec from 10 µA to 12 µA  
CCDR  
Added footnote# 14 related to AC timing parameters  
Document #: 001-15607 Rev. *A  
Page 12 of 12  

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