MoBL®,CY62126EV30
1-Mbit (64K x 16) Static RAM
Features
Functional Description
■ High speed: 45 ns
The CY62126EV30 is a high performance CMOS static RAM
organized as 64K words by 16 bits . This device features
■ Temperature ranges
❐ Industrial: –40°C to +85°C
❐ Automotive: –40°C to +125°C
advanced circuit design to provide ultra low active current. This
®
is ideal for providing More Battery Life™ (MoBL ) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption when addresses are not toggling. Placing the
device in standby mode reduces power consumption by more
than 99 percent when deselected (CE HIGH). The input and
■ Wide voltage range: 2.2V to 3.6V
■ Pin compatible with CY62126DV30
■ Ultra low standby power
❐ Typical standby current: 1 μA
❐ Maximum standby current: 4 μA
output pins (IO through IO ) are placed in a high impedance
0
15
state when:
■ Deselected (CE HIGH)
■ Ultra low active power
❐ Typical active current: 1.3 mA at f = 1 MHz
■ Outputs are disabled (OE HIGH)
■ Both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH)
■ Easy memory expansion with CE and OE features
■ Automatic power down when deselected
■ CMOS for optimum speed and power
■ Write operation is active (CE LOW and WE LOW)
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from IO pins (IO through IO ) is written into the location
■ Offered in Pb-free 48-ball VFBGA and 44-pin TSOP II
packages
0
7
specified on the address pins (A through A ). If Byte High
0
15
Enable (BHE) is LOW, then data from IO pins (IO through IO
)
8
15
is written into the location specified on the address pins (A
0
through A ).
15
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appear on IO to IO . If
0
7
Byte High Enable (BHE) is LOW, then data from memory
8
15
complete description of read and write modes.
Logic Block Diagram
Note
1. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.
Cypress Semiconductor Corporation
Document #: 38-05486 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 5, 2009
MoBL®, CY62126EV30
DC Input Voltage
...............−0.3V to 3.6V (V
+ 0.3V)
Maximum Ratings
CCmax
Output Current into Outputs (LOW)............................. 20 mA
Exceeding maximum ratings may shorten the battery life of the
device. These user guidelines are not tested.
Static Discharge Voltage.......................................... > 2001V
(MIL-STD-883, Method 3015)
Storage Temperature ................................. –65°C to +150°C
Latch up Current.................................................... > 200 mA
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Operating Range
Supply Voltage to Ground
Ambient
Potential.................................–0.3V to 3.6V (V
+ 0.3V)
+ 0.3V)
[6]
V
CC
CCmax
CCmax
Device
Range
Temperature
DC Voltage Applied to Outputs
CY62126EV30LL Industrial
–40°C to +85°C 2.2V to
3.6V
in High-Z State
................–0.3V to 3.6V (V
Automotive –40°C to +125°C
Electrical Characteristics (Over the Operating Range)
45 ns (Industrial)
55 ns (Automotive)
Parameter
Description
Test Conditions
= –0.1 mA
Unit
[1]
Min Typ
2.0
Max
Min Typ
2.0
Max
V
Output HIGH Voltage
I
I
I
I
V
V
OH
OL
IH
OH
OH
OL
OL
= –1.0 mA, V > 2.70V
2.4
2.4
CC
V
V
V
I
Output LOW Voltage
Input HIGH Voltage
= 0.1 mA
0.4
0.4
0.4
0.4
V
= 2.1mA, V > 2.70V
V
CC
V
V
V
V
= 2.2V to 2.7V
= 2.7V to 3.6V
= 2.2V to 2.7V
= 2.7V to 3.6V
1.8
2.2
V
V
+ 0.3 1.8
V
V
+ 0.3
V
CC
CC
CC
CC
CC
CC
CC
CC
+ 0.3 2.2
+ 0.3
V
Input LOW
Voltage
–0.3
–0.3
–1
0.6
0.8
–0.3
–0.3
–4
0.6
V
IL
0.8
+4
+4
V
Input Leakage Current GND < V < V
CC
+1
+1
μA
μA
IX
I
I
Output Leakage
Current
GND < V < V , Output
–1
–4
OZ
O
CC
Disabled
I
V
Operating Supply f = f
= 1/t
V
= V
CCmax
= 0 mA
11
16
11
35
mA
CC
CC
max
RC
CC
Current
I
OUT
f = 1 MHz
1.3
2.0
1.3
4.0
CMOS levels
I
Automatic CE Power CE > V − 0.2V,
1
4
4
1
35
30
μA
SB1
CC
down Current
V
f = f
> V – 0.2V, V < 0.2V)
CC IN
IN
—CMOS Inputs
(Address and Data Only),
max
f = 0 (OE, BHE, BLE and WE),
= 3.60V
V
CC
I
Automatic CE Power CE > V – 0.2V,
1
1
μA
SB2
CC
down Current
—CMOS Inputs
V
> V – 0.2V or V < 0.2V,
CC IN
IN
f = 0, V = 3.60V
CC
Capacitance
For all packages. Tested initially and after any design or process changes that may affect these parameters.
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
T = 25°C, f = 1 MHz, V = V
CC(typ)
Max
10
Unit
pF
C
C
IN
OUT
A
CC
10
pF
Notes
4.
5.
V
V
= –2.0V for pulse durations less than 20 ns.
IL(min)
= V +0.75V for pulse durations less than 20 ns.
IH(max)
CC
6. Full device AC operation assumes a 100 μs ramp time from 0 to V (min) and 200 μs wait time after V stabilization.
cc
cc
7. Only chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the I
/ I
spec. Other inputs can be left floating.
SB2 CCDR
Document #: 38-05486 Rev. *E
Page 3 of 13
MoBL®, CY62126EV30
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
VFBGA
Package
TSOP II
Package
Parameter
Description
Test Conditions
Unit
Θ
Θ
Thermal Resistance
(Junction to Ambient)
Still Air, soldered on a 4.25 x 1.125 inch,
two-layer printed circuit board
58.85
28.2
3.4
°C/W
JA
Thermal Resistance
(Junction to Case)
17.01
°C/W
JC
Figure 3. AC Test Loads and Waveforms
R1
ALL INPUT PULSES
V
CC
V
CC
90%
10%
OUTPUT
90%
10%
GND
R2
30 pF
Rise Time = 1 V/ns
Fall Time = 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to: THÉVENIN EQUIVALENT
R
TH
OUTPUT
2.2V - 2.7V
V
TH
Parameters
2.7V - 3.6V
1103
Unit
Ohms
Ohms
Ohms
Volts
R1
R2
16600
15400
8000
1.2
1554
R
V
645
TH
TH
1.75
Data Retention Characteristics
Over the Operating Range
Parameter
Description
Conditions
Min
Typ
Max
Unit
V
V
V
for Data Retention
1.5
DR
CC
[7]
I
Data Retention Current
V
V
= V , CE > V – 0.2V,
Industrial
3
μA
μA
ns
CCDR
CC
DR
CC
> V – 0.2V or V < 0.2V
IN
CC
IN
Automotive
30
t
t
Chip Deselect to Data
Retention Time
0
CDR
R
Operation Recovery Time
t
ns
RC
Figure 4. Data Retention Waveform
DATA RETENTION MODE
V
V
CC(min)
CC(min)
V
> 1.5V
VCC
CE
DR
t
t
R
CDR
Notes
8. Tested initially and after any design or process changes that may affect these parameters.
9. Full device AC operation requires linear V ramp from V to V > 100 μs.
CC
DR
CC(min)
Document #: 38-05486 Rev. *E
Page 4 of 13
MoBL®, CY62126EV30
Switching Characteristics
Over the Operating Range
45 ns (Industrial)
55 ns (Automotive)
Parameter
Description
Unit
Min
Max
Min
Max
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
45
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
45
55
AA
10
10
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
45
22
55
25
OE LOW to Low Z
5
10
0
5
10
0
OE HIGH to High Z
18
18
20
20
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power Up
CE HIGH to Power Down
BHE / BLE LOW to Data Valid
45
22
55
25
PD
DBE
LZBE
HZBE
BHE / BLE LOW to Low Z
5
5
BHE / BLE HIGH to High Z
18
20
Write Cycle
t
Write Cycle Time
45
55
ns
WC
t
t
t
t
CE LOW to Write End
35
35
0
40
40
0
ns
ns
ns
ns
SCE
AW
HA
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
0
0
SA
t
t
t
t
WE Pulse Width
35
35
25
0
40
40
25
0
ns
ns
ns
ns
PWE
BW
SD
BHE / BLE Pulse Width
Data Setup to Write End
Data Hold from Write End
HD
t
t
WE LOW to High Z
18
20
ns
ns
HZWE
WE HIGH to Low Z
10
10
LZWE
Notes
10. Test conditions assume signal transition time of 3 ns or less, timing reference levels of V
/2, input pulse levels of 0 to V
, and output loading of the
CC(typ)
CC(typ)
specified I /I and 30-pF load capacitance.
OL OH
11. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification.
12. At any temperature and voltage condition, t is less than t , t is less than t , t is less than t , and t is less than t for any device.
HZCE
LZCE HZBE
LZBE HZOE
LZOE
HZWE
LZWE
13. t
, t
, t
, and t
transitions are measured when the outputs enter a high impedance state.
HZOE HZCE HZBE
HZWE
14. The internal write time of the memory is defined by the overlap of WE, CE = V , BHE, BLE or both = V . All signals must be active to initiate a write and any of
IL
IL
these signals can terminate a write by going inactive. The data input setup and hold timing must refer to the edge of signal that terminates write.
Document #: 38-05486 Rev. *E
Page 5 of 13
MoBL®, CY62126EV30
Switching Waveforms
Figure 5. Read Cycle No. 1(Address transition controlled)
t
RC
ADDRESS
t
AA
t
OHA
PREVIOUS DATA VALID
DATA VALID
DATA OUT
Figure 6. Read Cycle No. 2 (OE controlled)
ADDRESS
CE
t
RC
t
PD
HZCE
t
t
ACE
OE
t
HZOE
t
DOE
t
LZOE
BHE/BLE
t
HZBE
t
DBE
t
LZBE
HIGH
IMPEDANCE
HIGHIMPEDANCE
DATA VALID
DATA OUT
t
LZCE
t
PU
V
50%
50%
CC
I
SUPPLY
SB
CURRENT
Notes
15. The device is continuously selected. OE, CE = V , BHE, BLE, or both = V .
IL
IL
16. WE is HIGH for read cycle.
17. Address valid before or similar to CE and BHE, BLE transition LOW.
Document #: 38-05486 Rev. *E
Page 6 of 13
MoBL®, CY62126EV30
Switching Waveforms (continued)
Figure 7. Write Cycle No. 1 (WE controlled)
t
WC
ADDRESS
CE
tSCE
t
t
HA
AW
t
SA
t
PWE
WE
t
BW
BHE/BLE
OE
t
HD
t
SD
NOTE 20
DATAIN
DATA IO
t
HZOE
Figure 8. Write Cycle No. 2 (CE controlled)
t
WC
ADDRESS
CE
t
SCE
t
SA
t
t
HA
AW
tPWE
WE
t
BW
BHE/BLE
OE
t
t
SD
HD
DATAIN
DATA IO
t
HZOE
Notes
18. Data IO is high impedance if OE = V
.
IH
19. If CE goes HIGH simultaneously with WE = V , the output remains in a high impedance state.
IH
20. During this period, the IOs are in output state. Do not apply input signals.
Document #: 38-05486 Rev. *E
Page 7 of 13
MoBL®, CY62126EV30
Switching Waveforms (continued)
[19]
Figure 9. Write Cycle No. 3 (WE controlled, OE LOW
t
WC
ADDRESS
CE
t
SCE
t
BW
BHE/BLE
t
t
HA
AW
t
SA
t
PWE
WE
t
HD
t
SD
DATA IO
DATAIN
t
LZWE
t
HZWE
Figure 10. Write Cycle No. 4 (BHE/BLE controlled, OE LOW)
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
tBW
BHE/BLE
WE
t
SA
tPWE
tHZWE
t
HD
t
SD
NOTE 20
DATAIN
DATA IO
tLZWE
Document #: 38-05486 Rev. *E
Page 8 of 13
MoBL®, CY62126EV30
Truth Table
CE
H
L
WE
X
OE
X
BHE
X
BLE
X
Inputs/Outputs
High Z
High Z
Data Out (IO –IO
Mode
Deselect/Power Down
Output Disabled
Read
Power
Standby (I
)
SB
X
X
H
H
Active (I
Active (I
Active (I
)
)
)
CC
CC
CC
L
H
L
L
L
)
15
0
L
H
L
H
L
Data Out (IO –IO );
Read
0
7
IO –IO in High Z
8
15
L
H
L
L
H
Data Out (IO –IO );
Read
Active (I
)
8
15
CC
IO –IO in High Z
0
7
L
L
L
L
L
H
H
H
L
H
H
H
X
X
L
H
L
L
L
H
L
L
High Z
Output Disabled
Output Disabled
Output Disabled
Write
Active (I
Active (I
Active (I
Active (I
Active (I
)
)
)
)
)
CC
CC
CC
CC
CC
High Z
High Z
L
Data In (IO –IO
)
15
0
L
H
Data In (IO –IO );
Write
0
7
IO –IO in High Z
8
15
L
L
X
L
H
Data In (IO –IO );
Write
Active (I
)
8
15
CC
IO –IO in High Z
0
7
Ordering Information
Speed
(ns)
Package
Diagram
Operating
Range
Package Type
Ordering Code
45
CY62126EV30LL-45BVXI 51-85150 48-ball Very Fine Pitch Ball Grid Array (Pb-free)
CY62126EV30LL-45ZSXI 51-85087 44-pin Thin Small Outline Package II (Pb-free)
Industrial
55
CY62126EV30LL-55BVXE 51-85150 48-ball Very Fine Pitch Ball Grid Array (Pb-free)
CY62126EV30LL-55ZSXE 51-85087 44-pin Thin Small Outline Package II (Pb-free)
Automotive
Contact your local Cypress sales representative for availability of other parts.
Document #: 38-05486 Rev. *E
Page 9 of 13
MoBL®, CY62126EV30
Package Diagrams
Figure 11. 48-Ball VFBGA (6 x 8 x 1 mm) (51-85150)
BOTTOM VIEW
A1 CORNER
TOP VIEW
Ø0.05 M C
Ø0.25 M C A B
Ø0.30 0.05(48X)
A1 CORNER
1
2
3
4
5
6
6
5
4
3
2
1
A
A
B
C
D
B
C
D
E
E
F
F
G
G
H
H
1.875
A
A
0.75
B
6.00 0.10
3.75
B
6.00 0.10
0.15(4X)
SEATING PLANE
C
51-85150-*D
Document #: 38-05486 Rev. *E
Page 10 of 13
MoBL®, CY62126EV30
Package Diagrams (continued)
Figure 12. 44-Pin TSOP II (51-85087)
51-85087-*A
Document #: 38-05486 Rev. *E
Page 11 of 13
MoBL®, CY62126EV30
Document History Page
®
Document Title: MoBL CY62126EV30, 1-Mbit (64K x 16) Static RAM
Document Number: 38-05486
Submission
Date
Orig. of
Change
Rev.
ECN No.
Description of Change
**
202760
300835
See ECN
See ECN
AJU
SYT
New data sheet
*A
Converted from Advance Information to Preliminary
Specified Typical standby power in the Features Section
Changed E3 ball from DNU to NC in the Pin Configuration for the FBGA Package
and removed the footnote associated with it on page #2
Changed t
Changed t
Changed t
from 6 ns to 10 ns for both 35- and 45-ns speed bins, respectively
OHA
, t from 15 to 18 ns for 35-ns speed bin
DOE SD
, t
, t
from 12 and 15 ns to 15 and 18 ns for the 35- and
HZOE HZBE HZWE
45-ns speed bins, respectively
Changed t from 12 and 15 ns to 18 and 22 ns for the 35- and 45-ns speed
HZCE
bins, respectively
Changed t ,t
from 25 and 40 ns to 30 and 35 ns for the 35- and 45-ns speed
SCE BW
bins, respectively
Changed t from 25 to 30 ns and 40 to 35 ns for 35 and 45-ns speed bins respec-
AW
tively
Changed t
from 35 and 45 ns to 18 and 22 ns for the 35 and 45 ns speed bins
DBE
respectively
Removed footnote that read “BHE.BLE is the AND of both BHE and BLE. Chip can
be deselected by either disabling the chip enable signals or by disabling both BHE
and BLE” on page # 4
Removed footnote that read “If both BHE and BLE are toggled together, then t
LZBE
is 10 ns” on page # 5
Added Pb-free package information
*B
461631
See ECN
NXR
Converted from Preliminary to Final
Removed 35 ns Speed Bin
Removed “L” version of CY62126EV30
Changed I
Changed I
Changed I
Changed I
Changed I
from 8 mA to 11 mA and I
from 12 mA to 16 mA for f = f
CC (max) max
CC (Typ)
from 1.5 mA to 2.0 mA for f = 1 MHz
CC (max)
, I
, I
from 1 μA to 4 μA
SB1 SB2 (max)
from 0.5 μA to 1 μA
SB1 SB2 (Typ)
from 1.5 μA to 3 μA
CCDR (max)
Changed the AC Test load Capacitance value from 50 pF to 30 pF
Changed t
Changed t
Changed t
Changed t
Changed t
from 3 to 5 ns
from 6 to 10 ns
from 22 to 18 ns
from 6 to 5 ns
from 30 to 35 ns
LZOE
LZCE
HZCE
LZBE
PWE
Changed t from 22 to 25 ns
SD
Changed t
from 6 to 10 ns
LZWE
Updated the Ordering Information table.
*C
*D
*E
925501
1045260
2631771
See ECN
See ECN
01/07/09
VKN
VKN
Added footnote #7 related to I and I
Added footnote #11 related AC timing parameters
SB2
CCDR
Added Automotive information
Updated Ordering Information table
NXR/PYRS Changed CE condition from X to L in Truth table for Output Disable mode
Updated template
Document #: 38-05486 Rev. *E
Page 12 of 13
MoBL®, CY62126EV30
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
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© Cypress Semiconductor Corporation, 2008-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-05486 Rev. *E
Revised January 5, 2009
Page 13 of 13
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All products and company names mentioned in this document may be the trademarks of their respective
holders.
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