CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
FLEx18™ 3.3V 64K/128K x 36 and
128K/256K x 18 Synchronous Dual-Port RAM
Features
Functional Description
■
True Dual-Ported Memory Cells that Allow Simultaneous
Access of the Same Memory Location
The FLEx18™ family includes 512 Kbit, 1 Mbit, 2 Mbit, 4 Mbit,
and 9 Mbit pipelined, synchronous, true dual port static RAMs
that are high speed, low power 3.3V CMOS. Two ports are
provided, permitting independent, simultaneous access to any
location in memory. The result of writing to the same location by
more than one port at the same time is undefined. Registers on
control, address, and data lines allow for minimal setup and hold
time.
■
■
■
■
■
■
Synchronous Pipelined Operation
Family of 512 Kbit, 1 Mbit, 2 Mbit, 4 Mbit, and 9 Mbit Devices
Pipelined Output Mode Allows Fast Operation
0.18 micron CMOS for Optimum Speed and Power
High Speed Clock to Data Access
During a Read operation, data is registered for decreased cycle
time. Each port contains a burst counter on the input address
register. After externally loading the counter with the initial
address, the counter increments the address internally (more
details to follow). The internal Write pulse width is independent
of the duration of the R/W input signal. The internal Write pulse
is self-timed to allow the shortest possible cycle times.
3.3V Low Power
❐
Active as Low as 225 mA (typ)
Standby as Low as 55 mA (typ)
❐
■
■
■
■
■
■
■
■
■
Mailbox Function for Message Passing
Global Master Reset
A HIGH on CE0 or LOW on CE1 for one clock cycle powers down
the internal circuitry to reduce the static power consumption. One
cycle with chip enables asserted is required to reactivate the
outputs.
Separate Byte Enables on Both Ports
Commercial and Industrial Temperature Ranges
IEEE 1149.1 Compatible JTAG Boundary Scan
144-Ball FBGA (13 mm × 13 mm) (1.0 mm pitch)
120 TQFP (14 mm x 14 mm x 1.4 mm)
Pb-Free Packages Available
Additional features include: readback of burst-counter internal
address value on address lines, counter-mask registers to
control the counter wrap around, counter interrupt (CNTINT)
flags, readback of mask register value on address lines,
retransmit functionality, interrupt flags for message passing,
JTAG for boundary scan, and asynchronous Master Reset
(MRST).
Counter Wrap Around Control
The CY7C0833AV device in this family has limited features. See
for details.
❐
❐
❐
Internal Mask Register Controls Counter Wrap Around
Counter-Interrupt Flags to Indicate Wrap Around
Memory Block Retransmit Operation
■
■
■
Counter Readback on Address Lines
Mask Register Readback on Address Lines
Dual Chip Enables on Both Ports for Easy Depth Expansion
Table 1. Product Selection Guide
512 Kbit
1 Mbit
2 Mbit
4 Mbit
9 Mbit
Density
(32K x 18)
CY7C0837AV
167
(64K x 18)
(128K x 18)
(256K x 18)
(512K x 18)
Part Number
CY7C0830AV
CY7C0831AV
Maximum Speed (MHz)
167
4.0
167
4.0
167
4.0
133
4.4
133
4.7
Maximum Access Time -
Clock to Data (ns)
4.0
Typical Operating
Current (mA)
225
225
225
225
225
270
Package
144 FBGA
120 TQFP
144 FBGA
120 TQFP
144 FBGA
120 TQFP
144 FBGA
120 TQFP
144 FBGA
Note
1. CY7C0832AV and CY7C0832BV are functionally identical.
Cypress Semiconductor Corporation
Document #: 38-06059 Rev. *S
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 03, 2009
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Pin Configurations
Figure 1. 144-Ball BGA (Top View)
CY7C0837AV / CY7C0830AV / CY7C0831AV / CY7C0832AV / CY7C0833AV
1
2
3
4
5
6
7
DQ9
NC
8
9
10
11
12
A
B
C
D
E
F
DQ17
DQ16
DQ14
DQ12
DQ13
DQ10
DQ9
DQ10
DQ12
DQ13
INT
DQ14
DQ16
DQ17
R
L
L
L
L
L
L
L
L
R
R
R
R
R
R
R
A0
L
A1
L
DQ15
CE1
DQ11
MRST
DQ11
DQ15
CE1
A1
R
A0
R
L
R
ADS
L
[8]
ADS
[8]
CNTINTL
CNTINTR
L
R
R
A2
L
A3
L
INT
L
A3
R
A2
R
R
[7]
[7]
CE0
[8]
CE0
[8]
L
R
A4
L
A5
L
NC
NC
VDD
VDD
VSS
VSS
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VDD
TMS
VDD
VDD
VSS
VSS
VDD
VDD
NC
A5
R
A4
R
A6
L
A7
L
B1
VSS
VSS
VSS
VSS
VDD
TCK
NC
NC
B1
A7
R
A6
R
L
R
A8
L
A9
L
C
NC
C
A9
R
A8
R
L
R
A10
A11
L
B0
NC
NC
B0
A11
A10
R
G
H
J
L
L
L
R
R
A12
A14
A13
OE
NC
NC
OE
A13
A12
A14
L
L
L
R
R
R
R
A15
[3]
A15
[3]
RW
NC
NC
RW
R
L
L
L
R
R
A16
[4]
A17
[5]
A17
[5]
A16
[4]
CNT/MSKL
[7]
CNTRSTL
CNTRSTR
CNT/MSKR
L
R
TDO
DQ4
TDI
DQ4
K
L
A18
[6]
A18
[6]
CNTENL
CNTENR
[8]
L
R
NC
DQ6
L
DQ2
L
DQ2
R
DQ6
R
NC
L
R
M
DQ8
DQ7
DQ5
L
DQ3
DQ1
L
DQ0
L
DQ0
R
DQ1
R
DQ3
DQ5
R
DQ7
DQ8
R
L
L
L
R
R
Notes
3. Leave this ball unconnected for CY7C0837AV.
4. Leave this ball unconnected for CY7C0837AV and CY7C0830AV.
5. Leave this ball unconnected for CY7C0837AV, CY7C0830AV and CY7C0831AV.
6. Leave this ball unconnected for CY7C0837AV, CY7C0830AV, CY7C0831AV, and CY7C0832AV.
7. These balls are not applicable for CY7C0833AV device. They must be tied to VDD.
8. These balls are not applicable for CY7C0833AV device. They must be tied to VSS.
9. These balls are not applicable for CY7C0833AV device. They must not be connected.
Document #: 38-06059 Rev. *S
Page 3 of 28
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Pin Configurations
Figure 2. 120-Pin Thin Quad Flat Pack (TQFP) (Top View)
CY7C0830AV / CY7C0831AV / CY7C0832AV / CY7C0832BV
A
90
89
2L
1
2
A
A
V
2R
3R
SS
A
3L
V
V
SS
88
87
3
4
DD
V
A
A
A
A
DD
4R
A
86
85
84
83
4L
5L
6L
5
6
7
8
A
A
5R
6R
7R
A
CE
B
7L
1L
0L
1L
82
81
9
10
CE
1R
B
B
0R
1R
B
80
79
78
11
12
13
OE
L
OE
R
CE
V
0L
CE
0R
77
76
DD
14
15
V
V
R/W
R
DD
SS
V
SS
R/W
75
74
73
16
17
18
L
L
CLK
V
CLK
MRST
ADS
R
SS
ADS
L
L
L
L
72
71
19
20
R
CNTEN
CNTEN
R
CNTRST
70
69
68
67
21
22
23
24
CNTRST
CNT/MSK
R
CNT/MSK
A
R
8L
9L
A
A
8R
A
9R
A
A
A
10L
11L
12L
66
65
25
26
A
A
A
V
V
A
10R
11R
12R
SS
64
63
62
61
27
28
29
30
V
SS
V
DD
DD
A
13L
13R
Notes
10. Leave this pin unconnected for CY7C0830AV.
11. Leave this pin unconnected for CY7C0830AV and CY7C0831AV.
Document #: 38-06059 Rev. *S
Page 4 of 28
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Pin Definitions
Left Port
Right Port
Description
[2]
[2]
A0L–A18L
A0R–A18R
Address Inputs.
[8]
[8]
ADSL
ADSR
Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW for
the part using the externally supplied address on the address pins and for loading this address
into the burst address counter.
[8]
CE0L
CE0R
CE1R
CLKR
Active LOW Chip Enable Input.
[7]
CE1L
Active HIGH Chip Enable Input.
CLKL
Clock Signal. Maximum clock input rate is fMAX.
[8]
[8]
CNTENL
CNTENR
Counter Enable Input. Asserting this signal LOW increments the burst address counter of its
respective port on each rising edge of CLK. The increment is disabled if ADS or CNTRST are
asserted LOW.
[7]
[7]
CNTRSTL
CNTRSTR
Counter Reset Input. Asserting this signal LOW resets to zero the unmasked portion of the
burst address counter of its respective port. CNTRST is not disabled by asserting ADS or
CNTEN.
[7]
[7]
CNT/MSKL
CNT/MSKR
Address Counter Mask Register Enable Input. Asserting this signal LOW enables access to
the mask register. When tied HIGH, the mask register is not accessible and the address counter
operations are enabled based on the status of the counter control signals.
DQ0L–DQ17L
OEL
DQ0R–DQ17R
OER
Data Bus Input/Output.
Output Enable Input. This asynchronous signal must be asserted LOW to enable the DQ data
pins during Read operations.
INTL
INTR
Mailbox Interrupt Flag Output. The mailbox permits communications between ports. The
upper two memory locations are used for message passing. INTL is asserted LOW when the
right port writes to the mailbox location of the left port, and vice versa. An interrupt to a port is
deasserted HIGH when it reads the contents of its mailbox.
[9]
[9]
CNTINTL
CNTINTR
Counter Interrupt Output. This pin is asserted LOW when the unmasked portion of the counter
is incremented to all ‘1s.’
R/WL
R/WR
Read/Write Enable Input. Assert this pin LOW to write to, or HIGH to Read from the dual port
memory array.
B0L–B1L
B0R–B1R
Byte Select Inputs. Asserting these signals enables Read and Write operations to the corre-
sponding bytes of the memory array.
MRST
Master Reset Input. MRST is an asynchronous input signal and affects both ports. Asserting
MRST LOW performs all of the reset functions as described in the text. A MRST operation is
required at power up.
TMS
JTAG Test Mode Select Input. It controls the advance of JTAG TAP state machine. State
machine transitions occur on the rising edge of TCK.
TDI
TCK
TDO
JTAG Test Data Input. Data on the TDI input is shifted serially into selected registers.
JTAG Test Clock Input.
JTAG Test Data Output. TDO transitions occur on the falling edge of TCK. TDO is normally
three-stated except when captured data is shifted out of the JTAG TAP.
VSS
VDD
Ground Inputs.
Power Inputs.
Byte Select Operation
Control Pin
Effect
B0
B1
DQ0–8 Byte Control
DQ9–17 Byte Control
Document #: 38-06059 Rev. *S
Page 5 of 28
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
The counter register contains the address used to access the
RAM array. It is changed only by the Counter Load, Increment,
Counter Reset, and by master reset (MRST) operations.
Master Reset
The FLEx18 family devices undergo a complete reset by taking
its MRST input LOW. The MRST input can switch asynchro-
nously to the clocks. An MRST initializes the internal burst
counters to zero, and the counter mask registers to all ones
(completely unmasked). MRST also forces the Mailbox Interrupt
(INT) flags and the Counter Interrupt (CNTINT) flags HIGH.
MRST must be performed on the FLEx18 family devices after
power up.
The mask register value affects the Increment and Counter
Reset operations by preventing the corresponding bits of the
counter register from changing. It also affects the counter
interrupt output (CNTINT). The mask register is changed only by
the Mask Load and Mask Reset operations and by the MRST.
The mask register defines the counting range of the counter
register. It divides the counter register into two regions: zero or
more ‘0s’ in the most significant bits define the masked region,
one or more ‘1s’ in the least significant bits define the unmasked
region. Bit 0 may also be ‘0,’ masking the least significant counter
bit and causing the counter to increment by two instead of one.
Mailbox Interrupts
The upper two memory locations may be used for message
shows the interrupt operation for both ports of CY7C0833AV.
The highest memory location, 7FFFF is the mailbox for the right
to set the INTR flag, a Write operation by the left port to address
7FFFF asserts INTR LOW. At least one byte has to be active for
a Write to generate an interrupt. A valid Read of the 7FFFF
location by the right port resets INTR HIGH. At least one byte
must be active for a Read to reset the interrupt. When one port
Writes to the other port’s mailbox, the INT of the port that the
mailbox belongs to is asserted LOW. The INT is reset when the
owner (port) of the mailbox Reads the contents of the mailbox.
The interrupt flag is set in a flow-through mode (that is, it follows
the clock edge of the writing port). Also, the flag is reset in a
flow-through mode (that is, it follows the clock edge of the
reading port).
The mirror register is used to reload the counter register on
contains the value last loaded into the counter register, and is
changed only by the Counter Load, and by the MRST instruc-
registers and the required input control signals. The MRST
control signal is asynchronous. All the other control signals in
synchronized to the port’s CLK. All these counter and mask
operations are independent of the port’s chip enable inputs (CE0
and CE1).
Counter enable (CNTEN) inputs are provided to stall the
operation of the address input and use the internal address
generated by the internal counter for fast, interleaved memory
applications. A port’s burst counter is loaded when the port’s
address strobe (ADS) and CNTEN signals are LOW. When the
port’s CNTEN is asserted and the ADS is deasserted, the
address counter increments on each LOW to HIGH transition of
that port’s clock signal. This reads and writes one word from and
to each successive address location until CNTEN s deasserted.
The counter can address the entire memory array, and loops
back to the start. Counter reset (CNTRST) is used to reset the
unmasked portion of the burst counter to I/0s. A counter-mask
register is used to control the counter wrap.
Each port can read the other port’s mailbox without resetting the
interrupt. And each port can write to its own mailbox without
setting the interrupt. If an application does not require message
passing, INT pins should be left open.
Address Counter and Mask Register Operations [16]
This section describes the features only apply to 512 Kbit,1 Mbit,
2 Mbit, and 4 Mbit devices. It does not apply to 9 Mbit device.
Each port of these devices has a programmable burst address
counter. The burst counter contains three registers: a counter
register, a mask register, and a mirror register.
FUNCTION
LEFT PORT
RIGHT PORT
R/WL
CEL
L
A0L–A18L
3FFFF
X
INTL
X
R/WR
CER
X
A0R–A18R
INTR
Set Right INTR Flag
L
X
X
H
L
X
H
L
X
3FFFF
3FFFE
X
L
H
X
X
L
Reset Right INTR Flag
Set Left INTL Flag
X
X
L
X
X
L
L
Reset Left INTL Flag
Set Right INTR Flag
L
3FFFE
3FFFF
H
X
X
X
L
X
X
X
Notes
12. CE is internal signal. CE = LOW if CE = LOW and CE = HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of the CLK and
0
1
can be deasserted after that. Data is out after the following CLK edge and is three-stated after the next CLK edge.
13. OE is “Don’t Care” for mailbox operation.
14. At least one of BE0, BE1 must be LOW.
15. A18x is a NC for CY7C0832AV/CY7C0832BV, therefore the Interrupt Addresses are 3FFFF and 3FFFE. A18x and A17x are NC for CY7C0831AV, therefore the Interrupt
addresses are 1FFFF and 1FFFE; A18x, A17x and A16x are NC for CY7C0830AV, therefore the Interrupt Addresses are FFFF and FFFE;A18x, A17x, A16x and A15x
are NC for CY7C0837AV, therefore the Interrupt Addresses are 7FFF and 7FFE.
16. This section describes the CY7C0832AV/CY7C0832BV, CY7C0831AV, CY7C0830AV and CY7C0837AV having 18, 17, 16 and 15 address bits.
17. “X” = “Don’t Care,” “H” = HIGH, “L” = LOW.
Document #: 38-06059 Rev. *S
Page 6 of 28
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
address counter is then loaded with an initial value of 8h. The
base address bits (in this case, the 6th address through the 16th
address) are loaded with an address value but do not increment
after the counter is configured for increment operation. The
counter address starts at address 8h. The counter increments its
internal address value until it reaches the mask register value of
3Fh. The counter wraps around the memory block to location 8h
at the next count. CNTINT is issued when the counter reaches
its maximum value
Counter Reset Operation
All unmasked bits of the counter are reset to ‘0.’ All masked bits
remain unchanged. The mirror register is loaded with the value
of the burst counter. A Mask Reset followed by a Counter Reset
resets the counter and mirror registers to 00000, as does master
reset (MRST).
Counter Load Operation
The address counter and mirror registers are both loaded with
the address value presented at the address lines.
Counter Hold Operation
The value of all three registers can be constantly maintained
unchanged for an unlimited number of clock cycles. Such
operation is useful in applications where wait states are needed,
or when address is available a few cycles ahead of data in a
shared bus interface.
Counter Increment Operation
When the address counter register is initially loaded with an
external address, the counter can internally increment the
address value, potentially addressing the entire memory array.
Only the unmasked bits of the counter register are incremented.
The corresponding bit in the mask register must be a ‘1’ for a
counter bit to change. The counter register is incremented by 1
if the least significant bit is unmasked, and by 2 if it is masked. If
all unmasked bits are ‘1,’ the next increment wraps the counter
back to the initially loaded value. If an Increment results in all the
unmasked bits of the counter being ‘1s,’ a counter interrupt flag
(CNTINT) is asserted. The next Increment returns the counter
register to its initial value, which was stored in the mirror register.
The counter address can instead be forced to loop to 00000 by
results in one or more of the unmasked bits of the counter being
‘0’ deasserts the counter interrupt flag. The example in Figure 4
on page 10 shows the counter mask register loaded with a mask
value of 0003Fh unmasking the first 6 bits with bit ‘0’ as the LSB
and bit ‘16’ as the MSB. The maximum value the mask register
can be loaded with is 3FFFFh. Setting the mask register to this
value allows the counter to access the entire memory space. The
Counter Interrupt
The counter interrupt (CNTINT) is asserted LOW when an
increment operation results in the unmasked portion of the
counter register being all ‘1s.’ It is deasserted HIGH when an
Increment operation results in any other value. It is also
de-asserted by Counter Reset, Counter Load, Mask Reset and
Mask Load operations, and by MRST.
Counter Readback Operation
The internal value of the counter register can be read out on the
address lines. Readback is pipelined; the address is valid tCA2
after the next rising edge of the port’s clock. If address readback
occurs while the port is enabled (CE0 LOW and CE1 HIGH), the
block diagram of the operation.
CLK MRST CNT/MSK
CNTRST
ADS
CNTEN
Operation
Description
X
L
X
X
X
X
Master Reset
Reset address counter to all 0s and mask
register to all 1s.
H
H
H
H
L
X
L
X
L
Counter Reset
Counter Load
Reset counter unmasked portion to all 0s.
H
Load counter with external address value
presented on address lines.
H
H
H
L
H
Counter Readback Read out counter internal value on address
lines.
H
H
H
H
H
H
H
H
L
Counter Increment Internally increment address counter value.
H
Counter Hold
Constantly hold the address value for multiple
clock cycles.
H
H
L
L
L
X
L
X
L
Mask Reset
Mask Load
Reset mask register to all 1s.
H
Load mask register with value presented on
the address lines.
H
H
L
L
H
H
L
H
X
Mask Readback
Reserved
Read out mask register value on address
lines.
H
Operation undefined
Notes
18. Counter operation and mask register operation is independent of chip enables.
19. CNTINT and CNTRST specs are guaranteed by design to operate properly at speed grade operating frequency when tied together.
Document #: 38-06059 Rev. *S
Page 7 of 28
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Retransmit
Mask Readback Operation
Retransmit is a feature that allows the Read of a block of memory
more than once without the need to reload the initial address.
This eliminates the need for external logic to store and route
data. It also reduces the complexity of the system design and
saves board space. An internal mirror register is used to store
the initially loaded address counter value. When the counter
unmasked portion reaches its maximum value set by the mask
register, it wraps back to the initial value stored in this mirror
register. If the counter is continuously configured in increment
mode, it increments again to its maximum value and wraps back
to the value initially stored into the mirror register. Thus, the
repeated access of the same data is allowed without the need
for any external logic.
The internal value of the mask register can be read out on the
address lines. Readback is pipelined; the address is valid tCM2
after the next rising edge of the port’s clock. If mask readback
occurs while the port is enabled (CE0 LOW and CE1 HIGH), the
block diagram of the operation.
Counting by Two
When the least significant bit of the mask register is ‘0,’ the
counter increments by two. This may be used to connect the x18
devices as a 36-bit single port SRAM in which the counter of one
port counts even addresses and the counter of the other port
counts odd addresses. This even-odd address scheme stores
one half of the 36-bit data in even memory locations, and the
other half in odd memory locations.
Mask Reset Operation
The mask register is reset to all ‘1s,’ which unmasks every bit of
the counter. Master reset (MRST) also resets the mask register
to all ‘1s’.
Mask Load Operation
The mask register is loaded with the address value presented at
the address lines. Not all values permit correct increment opera-
tions. Permitted values are of the form 2n – 1 or 2n – 2. From the
most significant bit to the least significant bit, permitted values
have zero or more ‘0s,’ one or more ‘1s,’ or one ‘0.’ Thus 3FFFF,
003FE, and 00001 are permitted values, but 3F0FF, 003FC, and
00000 are not.
Document #: 38-06059 Rev. *S
Page 8 of 28
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Figure 3. Counter, Mask, and Mirror Logic Block Diagram [1]
CNT/MSK
CNTEN
ADS
Decode
Logic
CNTRST
MRST
Bidirectional
Address
Lines
Mask
Register
Counter/
Address
Register
Address
Decode
RAM
Array
CLK
Load/Increment
17
17
From
Address
Lines
Mirror
Counter
To Readback
and Address
Decode
1
0
1
0
From
Increment
Logic
Mask
Register
17
Wrap
17
17
17
Bit 0
From
Mask
From
Counter
+1
+2
Wrap
Detect
Wrap
To
1
0
17
1
0
Counter
Document #: 38-06059 Rev. *S
Page 9 of 28
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
CNTINT
H
Example:
Load
Counter-Mask
Register = 3F
0
0
0s
0
1
1
1
1
1
1
216 215
26 25 24 23 22 21 20
Unmasked Address
Mask
Register
bit-0
Masked Address
Load
Address
Counter = 8
H
L
X
X
Xs
Xs
Xs
X
0
0
1
0
0
0
216 215
26 25 24 23 22 21 20
Address
Counter
bit-0
Max
Address
Register
X
X
X
1
1
1
1
1
1
216 215
26 25 24 23 22 21 20
Max + 1
Address
Register
H
X
X
X
0
0
1
0
0
0
216 215
26 25 24 23 22 21 20
IEEE 1149.1 Serial Boundary Scan (JTAG) [21]
Boundary Scan Hierarchy for 9-Mbit Device
Internally, the CY7C0833AV have two DIEs. Each DIE contain all
the circuitry required to support boundary scan testing. The
circuitry includes the TAP, TAP controller, instruction register,
and data registers. The circuity and operation of the DIE
boundary scan are described in detail below. The scan chain of
each DIE are connected serially to form the scan chain of the
are connected in parallel to each DIE to drive all TAP controllers
in unison. In many cases, each DIE is supplied with the same
instruction. In other cases, it might be useful to supply different
instructions to each DIE. One example would be testing the
device ID of one DIE while bypassing the others.
The FLEx18 family devices incorporate an IEEE 1149.1 serial
boundary scan test access port (TAP). The TAP controller
functions in a manner that does not conflict with the operation of
other devices using 1149.1 compliant TAPs. The TAP operates
using JEDEC-standard 3.3V I/O logic levels. It is composed of
three input connections and one output connection required by
the test logic defined by the standard.
Performing a TAP Reset
A reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This reset does not affect the operation of the
devices, and may be performed while the device is operating. An
MRST must be performed on the devices after power up.
Each pin of FLEx18 family is typically connected to multiple DIEs.
For connectivity testing with the EXTEST instruction, it is
desirable to check the internal connections between DIEs and
the external connections to the package. This is accomplished
by merging the netlist of the devices with the netlist of the user’s
circuit board. To facilitate boundary scan testing of the devices,
Cypress provides the BSDL file for each DIE, the internal netlist
of the device, and a description of the device scan chain. The
user can use these materials to easily integrate the devices into
the board’s boundary scan environment. Further information is
found in the Cypress application note Using JTAG Boundary
Scan For System in a Package (SIP) Dual-Port SRAMs.
Performing a Pause/Restart
When a SHIFT-DR PAUSE-DR SHIFT-DR is performed the scan
chain outputs the next bit in the chain twice. For example, if the
value expected from the chain is 1010101, the device outputs a
11010101. This extra bit causes some testers to report an
erroneous failure for the devices in a scan test. Therefore the
tester should be configured to never enter the PAUSE-DR state.
Notes
20. The “X” in this diagram represents the counter upper bits
21. Boundary scan is IEEE 1149.1-compatible. See Performing a Pause/Restart on page 10 for deviation from strict 1149.1 compliance
Document #: 38-06059 Rev. *S
Page 10 of 28
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Figure 5. Scan Chain for 9 Mb Device
TDO
TDO
D2
TDI
TDO
D1
TDI
TDI
Table 4. Identification Register Definitions
Instruction Field
Revision Number (31:28)
Cypress Device ID (27:12)
Value
Description
0h
Reserved for version number.
C090h
C091h
C093h
C094h
034h
1
Defines Cypress part number for CY7C0832AV/CY7C0832BV
Defines Cypress part number for CY7C0831AV
Defines Cypress part number for CY7C0830AV
Defines Cypress part number for CY7C0837AV.
Allows unique identification of the DP family device vendor.
Indicates the presence of an ID register.
Cypress JEDEC ID (11:1)
ID Register Presence (0)
Table 5. Scan Registers Sizes
Register Name
Instruction
Bit Size
4
1
Bypass
Identification
Boundary Scan
32
n[22]
Table 6. Instruction Identification Codes
Instruction
EXTEST
Code
Description
0000
1111
1011
0111
0100
Captures the Input/Output ring contents. Places the BSR between the TDI and TDO.
Places the BYR between TDI and TDO.
BYPASS
IDCODE
HIGHZ
Loads the IDR with the vendor ID code and places the register between TDI and TDO.
Places BYR between TDI and TDO. Forces all device output drivers to a High-Z state.
Controls boundary to 1/0. Places BYR between TDI and TDO.
CLAMP
SAMPLE/PRELOAD 1000
Captures the input/output ring contents. Places BSR between TDI and TDO.
Resets the non-boundary scan logic. Places BYR between TDI and TDO.
NBSRST
1100
RESERVED
All other codes Other combinations are reserved. Do not use other than the above.
Note
22. See details in the device BSDL file.
Document #: 38-06059 Rev. *S
Page 11 of 28
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage........................................... > 2000V
(JEDEC JESD22-A114-2000B)
Maximum Ratings
device. These user guidelines are not tested.
Latch Up Current.................................................... > 200 mA
Storage Temperature................................. –65°C to +150°C
Ambient Temperature with
Operating Range
Power Applied ............................................ –55°C to +125°C
Supply Voltage to Ground Potential................–0.5V to +4.6V
Ambient
Range
VDD
Temperature
0°C to +70°C
–40°C to +85°C
Commercial
Industrial
3.3V±165 mV
3.3V±165 mV
DC Voltage Applied to
Outputs in High-Z State ......................... –0.5V to VDD + 0.5V
Electrical Characteristics
Over the Operating Range
-167
-133
-100
Parameter
Description
Unit
Min Typ Max Min Typ Max Min Typ Max
VOH
VOL
VIH
VIL
Output HIGH Voltage (VDD = Min., IOH= –4.0 mA)
Output LOW Voltage (VDD = Min., IOL= +4.0 mA)
Input HIGH Voltage
2.4
2.4
2.4
V
V
0.4
0.8
0.4
0.4
2.0
2.0
2.0
V
Input LOW Voltage
0.8
10
10
0.8
10
10
V
IOZ
IIX1
IIX2
ICC
Output Leakage Current
–10
–10
–0.1
10 –10
10 –10
1.0 –0.1
–10
–10
μA
μA
Input Leakage Current Except TDI, TMS, MRST
Input Leakage Current TDI, TMS, MRST
1.0 –0.1
225 300
1.0 mA
mA
Operating Current for
CY7C0837AV
225 300
(VDD = Max., IOUT = 0 mA), Outputs CY7C0830AV
Disabled
CY7C0831AV
CY7C0832AV
CY7C0832BV
CY7C0833AV
270 400
90 115
200 310 mA
[25]
ISB1
Standby Current (Both Ports TTL Level)
90 115
160 210
90
160 210 mA
55 75 mA
160 210 mA
115 mA
CEL and CER ≥ VIH, f = fMAX
[25]
ISB2
Standby Current (One Port TTL Level)
160 210
55 75
160 210
70 100
CEL | CER ≥ VIH, f = fMAX
[25]
ISB3
Standby Current (Both Ports CMOS Level)
55
75
CEL and CER ≥ VDD – 0.2V, f = 0
[25]
ISB4
Standby Current (One Port CMOS Level)
160 210
CEL | CER ≥ VIH, f = fMAX
ISB5
Operating Current (VDD = Max, IOUT CY7C0833AV
= 0 mA, f = 0) Outputs Disabled
70
100 mA
Capacitance
Part Number [26]
Parameter
Description
Test Conditions Max
Unit
CY7C0837AV/CY7C0830AV/CY7C0831AV
CY7C0832AV/CY7C0832BV
CIN
Input Capacitance
TA = 25°C,
f = 1 MHz,
VDD = 3.3V
13
pF
COUT
Output Capacitance
10
pF
CY7C0833AV
CIN
Input Capacitance
Output Capacitance
22
20
pF
pF
COUT
Notes
23. The voltage on any input or I/O pin can not exceed the power pin during power up.
24. Pulse width < 20 ns.
25. I
, I
, I
and I
are not applicable for CY7C0833AV because it can not be powered down by using chip enable pins.
SB1 SB2 SB3
SB4
26. C
also references C
.
I/O
OUT
Document #: 38-06059 Rev. *S
Page 12 of 28
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Figure 6. AC Test Load and Waveforms
3.3V
Z = 50
Ω
R = 50Ω
0
OUTPUT
R1 = 590
R2 = 435
Ω
Ω
OUTPUT
C = 10 pF
C = 5 pF
V
= 1.5V
TH
(a) Normal Load (Load 1)
(b) Three-state Delay (Load 2)
3.0V
90%
10%
90%
10%
ALL INPUT PULSES
Vss
< 2 ns
< 2 ns
Switching Characteristics
Over the Operating Range
-167
-133
CY7C0837AV
CY7C0830AV
-100
CY7C0837AV
CY7C0830AV
CY7C0831AV
CY7C0832AV
Parameter
Description
CY7C0831AV CY7C0833AV CY7C0833AV Unit
CY7C0832AV
CY7C0832BV
Min
Max
Min
Max
Min
Max
Min
Max
fMAX2
tCYC2
tCH2
Maximum Operating Frequency
Clock Cycle Time
167
133
133
100
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6.0
2.7
2.7
7.5
3.0
3.0
7.5
3.0
3.0
10
4.0
4.0
Clock HIGH Time
tCL2
Clock LOW Time
tR
Clock Rise Time
2.0
2.0
2.0
2.0
2.0
2.0
3.0
3.0
tF
Clock Fall Time
tSA
Address Setup Time
Address Hold Time
Byte Select Setup Time
Byte Select Hold Time
Chip Enable Setup Time
Chip Enable Hold Time
R/W Setup Time
2.3
0.6
2.3
0.6
2.3
0.6
2.3
0.6
2.3
0.6
2.3
0.6
2.3
0.6
2.3
0.6
2.3
2.5
0.6
2.5
0.6
2.5
0.6
2.5
0.6
2.5
0.6
2.5
0.6
2.5
0.6
2.5
0.6
2.5
2.5
0.6
2.5
0.6
NA
NA
2.5
0.6
2.5
0.6
NA
NA
NA
NA
NA
NA
NA
3.0
0.6
3.0
0.6
NA
NA
3.0
0.6
3.0
0.6
NA
NA
NA
NA
NA
NA
NA
tHA
tSB
tHB
tSC
tHC
tSW
tHW
tSD
R/W Hold Time
Input Data Setup Time
Input Data Hold Time
ADS Setup Time
tHD
tSAD
tHAD
tSCN
tHCN
tSRST
tHRST
tSCM
ADS Hold Time
CNTEN Setup Time
CNTEN Hold Time
CNTRST Setup Time
CNTRST Hold Time
CNT/MSK Setup Time
Note
27. Except JTAG signals (t and t < 10 ns [max.]).
r
f
Document #: 38-06059 Rev. *S
Page 13 of 28
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Switching Characteristics (continued)
Over the Operating Range
-167
-133
CY7C0837AV
CY7C0830AV
-100
CY7C0837AV
CY7C0830AV
CY7C0831AV
CY7C0832AV
Parameter
Description
CY7C0831AV CY7C0833AV CY7C0833AV Unit
CY7C0832AV
CY7C0832BV
Min
Max
Min
Max
Min
Max
Min
Max
tHCM
tOE
CNT/MSK Hold Time
0.6
0.6
NA
NA
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Output Enable to Data Valid
OE to Low Z
4.0
4.4
4.7
5.0
tOLZ
0
0
0
0
tOHZ
OE to High Z
4.0
4.0
4.0
4.0
4.4
4.4
4.4
4.4
4.7
4.7
NA
NA
5.0
5.0
NA
NA
tCD2
tCA2
tCM2
tDC
Clock to Data Valid
Clock to Counter Address Valid
Clock to Mask Register Readback Valid
Data Output Hold After Clock HIGH
Clock HIGH to Output High Z
Clock HIGH to Output Low Z
Clock to INT Set Time
1.0
0
1.0
0
1.0
1.0
tCKHZ
4.0
4.0
6.7
6.7
5.0
5.0
4.4
4.4
7.5
7.5
5.7
5.7
4.7
4.7
7.5
7.5
NA
NA
5.0
5.0
10
tCKLZ
1.0
0.5
0.5
0.5
0.5
1.0
0.5
0.5
0.5
0.5
1.0
0.5
0.5
NA
NA
1.0
0.5
0.5
NA
NA
tSINT
tRINT
Clock to INT Reset Time
Clock to CNTINT Set Time
Clock to CNTINT Reset time
10
tSCINT
tRCINT
NA
NA
Port to Port Delays
tCCS
Clock to Clock Skew
5.2
6.0
6.0
8.0
ns
Master Reset Timing
tRS
Master Reset Pulse Width
7.0
6.0
6.0
7.5
6.0
7.5
7.5
6.0
7.5
10
8.5
10
ns
ns
ns
ns
ns
tRS
Master Reset Setup Time
tRSR
Master Reset Recovery Time
Master Reset to Outputs Inactive
tRSF
10.0
10.0
10.0
10.0
10.0
NA
10.0
NA
tRSCNTINT
Master Reset to Counter Interrupt Flag
Reset Time
Notes
28. This parameter is guaranteed by design, but is not production tested.
29. Test conditions used are Load 2.
Document #: 38-06059 Rev. *S
Page 14 of 28
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
JTAG Timing and Switching Waveforms
CY7C0837AV/CY7C0830AV
CY7C0831AV/CY7C0832AV
CY7C0832BV/CY7C0833AV
Parameter
Description
Unit
Min
Max
fJTAG
tTCYC
tTH
Maximum JTAG TAP Controller Frequency
TCK Clock Cycle Time
10
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
100
40
40
10
10
10
10
TCK Clock HIGH Time
tTL
TCK Clock LOW Time
tTMSS
tTMSH
tTDIS
tTDIH
tTDOV
tTDOX
TMS Setup to TCK Clock Rise
TMS Hold After TCK Clock Rise
TDI Setup to TCK Clock Rise
TDI Hold After TCK Clock Rise
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
30
0
Figure 7. JTAG Switching Waveform
tTH
tTL
Test Clock
TCK
tTCYC
tTMSS
tTMSH
Test Mode Select
TMS
tTDIS
tTDIH
Test Data-In
TDI
Test Data-Out
TDO
tTDOX
tTDOV
Document #: 38-06059 Rev. *S
Page 15 of 28
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Switching Waveforms
Figure 8. Master Reset
tRS
MRST
tRSF
ALL
ADDRESS/
DATA
tRSS
INACTIVE
LINES
tRSR
ALL
OTHER
INPUTS
ACTIVE
TMS
CNTINT
INT
TDO
tCYC2
tCH2
tCL2
CLK
CE
tSC
tHC
tSC
tHC
tSB
tHB
BE0–BE1
R/W
tSW
tSA
tHW
tHA
ADDRESS
DATAOUT
An
An+1
An+2
An+3
tDC
1 Latency
tCD2
Qn
Qn+1
Qn+2
tOHZ
tCKLZ
tOLZ
OE
t
OE
Notes
30. OE is asynchronously controlled; all other inputs (excluding MRST and JTAG) are synchronous to the rising clock edge.
31. ADS = CNTEN = LOW, and MRST = CNTRST = CNT/MSK = HIGH.
32. The output is disabled (high-impedance state) by CE = V following the next rising edge of the clock.
IH
33. Addresses need not be accessed sequentially because ADS = CNTEN = V with CNT/MSK = V constantly loads the address on the rising edge of the CLK.
IL
IH
Numbers are for reference only.
Document #: 38-06059 Rev. *S
Page 16 of 28
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Switching Waveforms (continued)
t
CYC2
t
t
CL2
CH2
CLK
t
t
t
HA
SA
A
A
4
ADDRESS
A
5
A
A
A
3
(B1)
0
1
2
t
HC
SC
CE
(B1)
t
t
t
t
CKHZ
t
t
t
CD2
CD2
CD2
HC
CKHZ
SC
Q
Q
Q
1
3
DATA
0
OUT(B1)
t
t
HA
SA
t
t
t
CKLZ
DC
DC
A
A
4
A
ADDRESS
A
0
A
A
3
5
(B2)
1
2
t
t
HC
SC
CE
(B2)
t
t
t
CD2
t
CD2
CKHZ
t
SC
HC
DATA
OUT(B2)
Q
Q
4
2
t
t
CKLZ
CKLZ
tCYC2
tCH2
tCL2
CLK
CE
tSC
tHC
tSW
tHW
R/W
tSW
tHW
An
An+1
An+2
An+2
An+3
An+4
ADDRESS
DATAIN
tSD tHD
tSA
tHA
Dn+2
tCD2
tCD2
tCKHZ
Qn
Qn+3
DATAOUT
tCKLZ
READ
NO OPERATION
WRITE
READ
Notes
34. In this depth-expansion example, B1 represents Bank #1 and B2 is Bank #2; each bank consists of one Cypress FLEx18 device from this data sheet. ADDRESS
(B1)
= ADDRESS
.
(B2)
35. ADS = CNTEN= BE0 – BE1 = OE = LOW; MRST = CNTRST = CNT/MSK = HIGH.
36. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals.
37. During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
38. CE = OE = BE0 – BE1 = LOW; CE = R/W = CNTRST = MRST = HIGH.
0
1
39. CE = BE0 – BE1 = R/W = LOW; CE = CNTRST = MRST = CNT/MSK = HIGH. When R/W first switches low, because OE = LOW, the Write operation cannot be
0
1
completed (labelled as no operation). One clock cycle is required to three-state the I/O for the Write operation on the next rising edge of CLK.
Document #: 38-06059 Rev. *S
Page 17 of 28
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Switching Waveforms (continued)
tCYC2
tCH2
tCL2
CLK
CE
tSC
tHC
tHW
tSW
R/W tSW
tHW
An
An+1
An+2
An+3
An+4
An+5
ADDRESS
tSA
tHA
tSD tHD
Dn+2
DATAIN
Dn+3
tCD2
tCD2
DATAOUT
Qn
Qn+4
tOHZ
OE
READ
WRITE
READ
tCYC2
tCL2
tCH2
CLK
tSA
tHA
ADDRESS
An
tSAD
tHAD
ADS
tSAD
tHAD
CNTEN
tSCN
tHCN
tSCN
tHCN
tCD2
Qx–1
Qx
tDC
Qn
Qn+1
COUNTER HOLD
Qn+2
DATAOUT
Qn+3
READ
READ WITH COUNTER
READ WITH COUNTER
EXTERNAL
ADDRESS
Document #: 38-06059 Rev. *S
Page 18 of 28
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Switching Waveforms (continued)
tCYC2
tCL2
tCH2
CLK
tSA
tHA
An
ADDRESS
INTERNAL
ADDRESS
An
An+1
An+2
An+3
An+4
tSAD
tHAD
ADS
CNTEN
DATAIN
tSCN
tHCN
Dn
Dn+1
Dn+1
Dn+2
Dn+3
Dn+4
tSD
tHD
WRITE EXTERNAL
ADDRESS
WRITE WITH WRITE COUNTER
COUNTER HOLD
WRITE WITH COUNTER
t
CYC2
t
t
CL2
CH2
CLK
t
HA
t
SA
A
p
A
m
A
n
ADDRESS
INTERNAL
ADDRESS
A
p
A
x
A
n
1
0
A
m
t
t
HW
SW
R/W
ADS
CNTEN
CNTRST
t
t
HRST
SRST
t
t
SD
HD
DATA
IN
D
0
t
t
CD2
CD2
DATA
Q
0
Q
n
OUT
Q
1
t
CKLZ
READ
ADDRESS 0
READ
ADDRESS 1
READ
ADDRESS A
COUNTER
RESET
WRITE
ADDRESS 0
READ
ADDRESS A
m
n
Notes
40. CE = BE0 – BE1 = LOW; CE = MRST = CNT/MSK = HIGH.
0
1
41. No dead cycle exists during counter reset. A Read or Write cycle may be coincidental with the counter reset.
42. Retransmit happens if the counter remains in increment mode after it wraps to initially loaded value.
Document #: 38-06059 Rev. *S
Page 19 of 28
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Switching Waveforms (continued)
t
CYC2
t
t
CL2
CH2
CLK
t
or t
CM2
t
t
CA2
SA
HA
EXTERNAL
ADDRESS
A
A
n*
n
A –A
0
16
INTERNAL
ADDRESS
An+4
An+1
An+2
An+3
An
t
t
t
SAD
HAD
ADS
t
SCN
HCN
CNTEN
t
t
t
CD2
CKHZ
CKLZ
DATA
OUT
Q
n+1
Q
Q
Q
Q
Qn+3
x-1
n+2
x-2
n
LOAD
EXTERNAL
ADDRESS
READBACK
COUNTER
INTERNAL
ADDRESS
INCREMENT
Notes
43. CE = OE = BE0 – BE1 = LOW; CE = R/W = CNTRST = MRST = HIGH.
0
1
44. Address in output mode. Host must not be driving address bus after t
in next clock cycle.
CKLZ
45. Address in input mode. Host can drive address bus after t
.
CKHZ
46. An * is the internal value of the address counter (or the mask register depending on the CNT/MSK level) being Read out on the address lines.
Document #: 38-06059 Rev. *S
Page 20 of 28
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Switching Waveforms (continued)
tCYC2
tCL2
tCH2
CLKL
tHA
tSA
L_PORT
ADDRESS
An
tSW
tHW
R/WL
tCKHZ
tSD
tHD
tCKLZ
L_PORT
DATAIN
Dn
tCCS
tCYC2
tCL2
CLKR
tCH2
tSA
tHA
R_PORT
ADDRESS
An
R/WR
tCD2
R_PORT
DATAOUT
Qn
tDC
Notes
47. CE = OE = ADS = CNTEN = BE0 – BE1 = LOW; CE = CNTRST = MRST = CNT/MSK = HIGH.
0
1
48. This timing is valid when one port is writing, and other port is reading the same location at the same time. If t
is violated, indeterminate data is Read out.
CCS
49. If t
< minimum specified value, then R_Port is Read the most recent data (written by L_Port) only (2 * t
+ t
) after the rising edge of R_Port's clock. If t
CCS
CYC2
CD2 CCS
> minimum specified value, then R_Port is Read the most recent data (written by L_Port) (t
+ t
) after the rising edge of R_Port's clock.
CYC2
CD2
Document #: 38-06059 Rev. *S
Page 21 of 28
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Switching Waveforms (continued)
t
CYC2
t
t
CH2
CL2
CLK
tSCM
tHCM
CNT/MSK
ADS
CNTEN
COUNTER
INTERNAL
ADDRESS
3FFFE
3FFFC
Last_Loaded
3FFFD
3FFFF
Last_Loaded +1
t
t
RCINT
SCINT
CNTINT
Notes
50. CE = OE = BE0 – BE1 = LOW; CE = R/W = CNTRST = MRST = HIGH.
0
1
51. CNTINT is always driven.
52. CNTINT goes LOW when the unmasked portion of the address counter is incremented to the maximum value.
53. The mask register assumed to have the value of 3FFFFh.
Document #: 38-06059 Rev. *S
Page 22 of 28
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Switching Waveforms (continued)
tCYC2
tCL2
tCH2
CLKL
tSA tHA
7FFFF
L_PORT
ADDRESS
An+1
An
An+2
An+3
tSINT
tRINT
INTR
tCYC2
tCL2
tCH2
CLKR
tSA tHA
Am
R_PORT
ADDRESS
Am+1
7FFFF
Am+3
Am+4
Inputs
Outputs
DQ0 – DQ17
High-Z
Operation
OE
CLK
CE0
CE1
R/W
X
H
X
X
Deselected
Deselected
Write
X
X
L
X
L
L
L
L
H
H
H
X
L
High-Z
DIN
H
X
DOUT
High-Z
Read
H
X
Outputs Disabled
Notes
54. CE = OE = ADS = CNTEN = LOW; CE = CNTRST = MRST = CNT/MSK = HIGH.
0
1
55. Address “7FFFF” is the mailbox location for R_Port of the 9Mb device.
56. L_Port is configured for Write operation, and R_Port is configured for Read operation.
57. At least one byte enable (BE0 – BE1) is required to be active during interrupt operations.
58. Interrupt flag is set with respect to the rising edge of the Write clock, and is reset with respect to the rising edge of the Read clock.
59. OE is an asynchronous input signal.
60. When CE changes state, deselection and Read happen after one cycle of latency.
61. CE = OE = LOW; CE = R/W = HIGH.
0
1
Document #: 38-06059 Rev. *S
Page 23 of 28
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Ordering Information
512K
×
18 (9M) 3.3V Synchronous CY7C0833AV Dual-Port SRAM
Package
Speed
(MHz)
Operating
Range
Ordering Code
Package Type
Diagram
133 CY7C0833AV-133BBC
CY7C0833AV-133BBI
51-85141 144-Ball Grid Array (13 x 13 x 1.6 mm) with 1 mm pitch
51-85141 144-Ball Grid Array (13 x 13 x 1.6 mm) with 1 mm pitch
51-85141 144-Ball Grid Array (13 x 13 x 1.6 mm) with 1 mm pitch
51-85141 144-Ball Grid Array (13 x 13 x 1.6 mm) with 1 mm pitch
Commercial
Industrial
100 CY7C0833AV-100BBC
CY7C0833AV-100BBI
Commercial
Industrial
256K
×
18 (4M) 3.3V Synchronous CY7C0832AV/CY7C0832BV Dual-Port SRAM
Speed
(MHz)
Package
Diagram
Operating
Range
Ordering Code
Package Type
167 CY7C0832AV-167BBC
CY7C0832AV-167AC
51-85141 144-Ball Grid Array (13 x 13 x 1.6 mm) with 1 mm pitch
51-85100 120-Pin Thin Quad Flat Pack (14 x 14 x 1.4 mm)
120-Pin Thin Quad Flat Pack (14 x 14 x 1.4 mm) (Pb-Free)
51-85141 144-Ball Grid Array (13 x 13 x 1.6 mm) with 1 mm pitch
51-85100 120-Pin Thin Quad Flat Pack (14 x 14 x 1.4 mm)
120-Pin Thin Quad Flat Pack (14 x 14 x 1.4 mm) (Pb-Free)
51-85141 144-Ball Grid Array (13 x 13 x 1.6 mm) with 1 mm pitch
51-85100 120-Pin Thin Quad Flat Pack (14 x 14 x 1.4 mm)
120-Pin Thin Quad Flat Pack (14 x 14 x 1.4 mm) (Pb-Free)
Commercial
Commercial
Industrial
CY7C0832AV-167AXC
133 CY7C0832AV-133BBC
CY7C0832AV-133AC
CY7C0832AV-133AXC
CY7C0832AV-133BBI
CY7C0832BV-133AI
CY7C0832AV-133AXI
128K
×
18 (2M) 3.3V Synchronous CY7C0831AV Dual-Port SRAM
Speed
(MHz)
Package
Diagram
Operating
Range
Ordering Code
Package Type
167 CY7C0831AV-167BBC
CY7C0831AV-167AC
51-85141 144-Ball Grid Array (13 x 13 x 1.6 mm) with 1 mm pitch
51-85100 120-Pin Thin Quad Flat Pack (14 x 14 x 1.4 mm)
120-Pin Thin Quad Flat Pack (14 x 14 x 1.4 mm) (Pb-Free)
51-85141 144-Ball Grid Array (13 x 13 x 1.6 mm) with 1 mm pitch
144-Ball Grid Array (13 x 13 x 1.6 mm) with 1 mm pitch (Pb-Free)
51-85100 120-Pin Thin Quad Flat Pack (14 x 14 x 1.4 mm)
120-Pin Thin Quad Flat Pack (14 x 14 x 1.4 mm) (Pb-Free)
51-85141 144-Ball Grid Array (13 x 13 x 1.6 mm) with 1 mm pitch
144-Ball Grid Array (13 x 13 x 1.6 mm) with 1 mm pitch (Pb-Free)
51-85100 120-Pin Thin Quad Flat Pack (14 x 14 x 1.4 mm)
120-Pin Thin Quad Flat Pack (14 x 14 x 1.4 mm) (Pb-Free)
Commercial
CY7C0831AV-167AXC
133 CY7C0831AV-133BBC
CY7C0831AV-133BBXC
CY7C0831AV-133AC
Commercial
CY7C0831AV-133AXC
CY7C0831AV-133BBI
CY7C0831AV-133BBXI
CY7C0831AV-133AI
Industrial
CY7C0831AV-133AXI
64K
×
18 (1M) 3.3V Synchronous CY7C0830AV Dual-Port SRAM
Speed
(MHz)
Package
Diagram
Operating
Range
Ordering Code
Package Type
167 CY7C0830AV-167BBC
CY7C0830AV-167AC
51-85141 144-Ball Grid Array (13 x 13 x 1.6 mm) with 1 mm pitch
51-85100 120-Pin Thin Quad Flat Pack (14 x 14 x 1.4 mm)
51-85141 144-Ball Grid Array (13 x 13 x 1.6 mm) with 1 mm pitch
51-85100 120-Pin Thin Quad Flat Pack (14 x 14 x 1.4 mm)
51-85141 144-Ball Grid Array (13 x 13 x 1.6 mm) with 1 mm pitch
51-85100 120-Pin Thin Quad Flat Pack (14 x 14 x 1.4 mm)
Commercial
Commercial
Industrial
133 CY7C0830AV-133BBC
CY7C0830AV-133AC
CY7C0830AV-133BBI
CY7C0830AV-133AI
Document #: 38-06059 Rev. *S
Page 24 of 28
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Ordering Information
32K
×
18 (512K) 3.3V Synchronous CY7C0837AV Dual-Port SRAM
Package
Speed
(MHz)
Operating
Range
Ordering Code
Package Type
Diagram
167 CY7C0837AV-167BBC
133 CY7C0837AV-133BBC
CY7C0837AV-133BBI
51-85141 144-Ball Grid Array (13 x 13 x 1.6 mm) with 1 mm pitch
51-85141 144-Ball Grid Array (13 x 13 x 1.6 mm) with 1 mm pitch
51-85141 144-Ball Grid Array (13 x 13 x 1.6 mm) with 1 mm pitch
Commercial
Commercial
Industrial
Package Diagrams
Figure 20. 144-Ball FBGA (13 x 13 x 1.6 mm) (51-85141)
TOP VIEW
BOTTOM VIEW
Ø0.05 M C
Ø0.25 M C A B
+0.10
A1 CORNER
Ø0.50 (144X)
-0.05
1
2
3
4
5
6
7
8
9
10
11 12
12 11 10
9
8
7
6
5
3
2
1
4
A
B
A
B
C
D
E
C
D
E
F
G
F
G
H
J
H
J
K
K
L
L
M
M
5.50
A
A
1.00
13.00 0.10
B
11.00
13.00 0.10
B
0.15(4X)
DIMENSIONS IN MILLIMETERS
REFERENCE JEDEC: PUBLICATION 95
DESIGN GUIDE 4.14D
PKG. WEIGHT: 0.53 gms
SEATING PLANE
C
51-85141-*B
Document #: 38-06059 Rev. *S
Page 25 of 28
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Package Diagrams
Figure 21. 120-Pin Thin Quad Flatpack (14 x 14 x 1.4 mm) (51-85100)
51-85100-**
Document #: 38-06059 Rev. *S
Page 26 of 28
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Document History Page
Document Title: CY7C0837AV/CY7C0830AV/CY7C0831AV/CY7C0832AV/CY7C0832BV/CY7C0833AV, FLEx18™ 3.3V
64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM
Document Number: 38-06059
Orig. of
Change
Submission
Date
Rev.
ECN No.
Description of Change
**
111473
111942
DSG
JFU
11/27/01
12/21/01
Change from Spec number: 38-01056 to 38-06059
*A
Updated capacitance values
Updated switching parameters and ISB3
Updated “Read-to-Write-to-Read (OE Controlled)” waveform
Revised static discharge voltage
Revised footnote regarding ISB3
*B
113741
KRE
04/02/02
Updated Isb values
Updated ESD voltage
Corrected 0853 pins L3 and L12
*C
*D
*E
*F
*G
114704
115336
122307
123636
126053
KRE
KRE
RBI
04/24/02
07/01/02
12/27/02
1/27/03
Added discussion of Pause/Restart for JTAG boundary scan
Revised speed offerings for all densities
Power up requirements added to Maximum Ratings Information
Revise tcd2, tOE, tOHZ, tCKHZ, tCKLZ for the CY7C0853V to 4.7 ns
KRE
SPN
08/11/03
Separated out 4M and 9M data sheets
Updated Isb and ICC values
*H
*I
129443
231993
RAZ
YDT
11/03/03
See ECN
Updated Isb and ICC values
Removed “A particular port can write to a certain location while another port is
reading that location.” from Functional Description.
*J
231813
WWZ
See ECN
Removed x36 devices (CY7C0852/CY7C0851) from this datasheet. Added
0.5M, 1M and 9M x18 devices to it. Changed title to FLEx18 3.3V
32K/64K/128K/256K/512K x18 Synchronous Dual-Port RAM. Changed
datasheet to accommodate the removals and additions. Removed general
JTAG description. Updated JTAG ID codes for all devices. Added 144FBGA
package for all devices. Updated selection guide table and moved to the front
page. Updated block diagram to reflect x18 configuration. Added preliminary
status back due to the addition of the new devices.
*K
*L
311054
329111
RYQ
SPN
See ECN
See ECN
Minor Change: Correct the revision indicated on the footer.
Updated Marketing part numbers
Updated tRSF
*M
*N
330561
375198
RUY
YDT
See ECN
See ECN
Added Byte Select Operation Table
Removed Preliminary status
Added ISB5
Changed tRSCNTINT to 10ns
*O
*P
391525
414109
SPN
LIJ
See ECN
See ECN
Updated Counter reset section to reflect what is loaded into the mirror register
Corrected Ordering Codes for 0831 devices in the 133 Mhz speed bin.
Added CY7C0833AV-133BBI.
*Q
461113
YDT
SEE ECN
Changed VDDIO to VDD (typo)
Added lead(Pb)-free parts
Corrected typo in DC table
*R
*S
2544945 VKN/AESA
2668478 VKN/PYRS
07/29/08
02/04/09
Updated Template. Updated ordering information
Added CY7C0832BV part
Added footnote #1
Updated Ordering information table
Document #: 38-06059 Rev. *S
Page 27 of 28
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
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© Cypress Semiconductor Corporation, 2001-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
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for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
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United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
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the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-06059 Rev. *S
Revised March 03, 2009
Page 28 of 28
FLEx18 is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders.
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