Samsung FLEX MUXONENAND KFN8GH6Q4M User Manual

Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
.
KFM4GH6Q4M  
KFN8GH6Q4M  
KFKAGH6Q4M  
4Gb Flex-MuxOneNAND M-die  
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,  
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.  
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,  
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,  
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL  
INFORMATION IN THIS DOCUMENT IS PROVIDED  
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.  
1. For updates or additional information about Samsung products, contact your nearest Samsung office.  
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar  
applications where Product failure could result in loss of life or personal or physical harm, or any military or  
defense application, or any governmental procurement to which special terms or provisions may apply.  
Flex-MuxOneNAND‚ is a trademark of Samsung Electronics Company, Ltd. Other names and brands may be  
claimed as the property of their rightful owners.  
* Samsung Electronics reserves the right to change products or specification without notice.  
- 1 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
Revision History  
Revision No.  
History  
Draft Date  
Remark  
0.2  
1. Corrected errata.  
Oct. 30, 2007  
Preliminary  
2. Chapter 2.1 Detailed Product Description revised.  
3. Chapter 2.2 Definitions revised.  
4. Chapter 2.8.3 Device ID Register F001h(R) revised.  
5. Chapter 2.8.8 Technology Register F006h(R) revised.  
6. Chapter 2.8.10 Start Address2 Register F101h(R/W) revised.  
7. Chapter 2.8.16 Start Address8 Register F107h(R/W) revised.  
8. Chapter 2.8.18 Command Register F220h(R/W) revised.  
9. Chapter 2.8.22 Interrupt Status Register F241h(R/W) revised.  
10. Chapter 3.1 Command Based Operation revised.  
11. Chapter 3.3 Reset Mode Operation revised.  
12. Chapter 3.4.3 NAND Array Write Protection States revised.  
13. Chapter 3.4.3.1 Unlocked NAND Array Write Protection State revised.  
14. Chapter 3.4.3.3 Locked-tight NAND Array Write Protection State  
revised.  
15. Chapter 3.4.4 NAND Flash Array Write Protection State Diagram  
revised.  
16. Chapter 3.6.2 LSB Page Recovery Read revised.  
17. Chapter 3.7.2 Synchronous Read Mode Operation revised.  
18. Chapter 3.7.2.1 Continuous Linear Burst Read Operation revised.  
19. Chapter 3.9 Program Operation revised.  
20. Chapter 3.9.1 Cache Program Operation revised.  
21. Chapter 3.9.2 Interleave Cache Program Operation revised.  
22. Chapter 3.11.1 Block Erase Operation revised.  
23. Chapter 3.11.2 Erase Suspend / Erase Resume Operation revised.  
24. Chapter 3.12 Partition Information (PI) Block(SLC Only) revised.  
25. Chapter 3.12.1 PI Block Boundary Information setting revised.  
26. Chapter 3.12.1.1 PI Block Access mode entry revised.  
27. Chapter 3.12.1.2 PI Block Erase revised.  
28. Chapter 3.12.1.3 PI Block Program Operation revised.  
29. Chapter 3.12.1.4 PI Update revised.  
30. Chapter 3.13 OTP Operation (SLC only) revised.  
31. Chapter 3.13.1 OTP Block Load Operation revised.  
32. Chapter 3.16.2 Invalid Block Replacement Operation revised.  
33. Chapter 5.5 AC Characteristics for Asynchronous Read revised.  
34. Chapter 6.3 Asynchronous Read(VA Transition Before AVD Low) tOEH  
removed.  
35. Chapter 6.4 Asynchronous Read(VA Transition After AVD Low) tOEH  
removed.  
36. Chapter 7.4 DDP and QDP Description inserted.  
1.0  
1.1  
1. New Format(font size, color etc.)  
2. Corrected errata.  
Feb. 04, 2008  
Final  
Final  
3. Added a comment(Chapter 3.11.1 & 3.12.1.2 & 3.12.1.3 & 3.12.1.4)  
4. Chapter 2.8.17 Start Buffer Register F200h (R/W) revised.  
5. Chapter 3.1.2 Load Data Into Buffer Command revised.  
6. Chapter 3.12.2 PI Block Load Operation revised.  
7. Chapter 4.3 DC Characteristics revised.  
1. Chapter 3.6.2 LSB Page Recovery read flow chart revised.  
2. Chapter 3.9.1 Cache Program Operation revised.  
3. Chapter 3.13.1 OTP Block Read Operation Flow Chart revised.  
4. Chapter 3.13.2 OTP Block Program Operation Flow Chart revised.  
5. Chapter 3.13.3 OTP Block Lock Operation Flow Chart revised.  
6. Chapter 3.13.4 1st Block OTP Lock Operation revised.  
7. Chapter 3.13.5 OTP and 1st Block OTP Lock Operation Flow Chart  
revised.  
Aug. 07, 2008  
- 3 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
1.0 INTRODUCTION  
This specification contains information about the Samsung Electronics Company Flex-MuxOneNAND‚ Flash memory product family. Sec-  
tion 1.0 includes a general overview, revision history, and product ordering information.  
Section 2.0 describes the Flex-MuxOneNAND device. Section 3.0 provides information about device operation. Electrical specifications and  
timing waveforms are in Sections 4.0 through 6.0. Section 7.0 provides additional application and technical notes pertaining to use of the Flex-  
MuxOneNAND. Package dimensions are found in Section 8.0  
Density  
4Gb  
Part No.  
VCC(core & IO)  
1.8V(1.7V~1.95V)  
1.8V(1.7V~1.95V)  
1.8V(1.7V~1.95V)  
Temperature  
Extended  
PKG  
KFM4GH6Q4M-DEBx  
KFN8GH6Q4M-DEBX  
KFKAGH6Q4M-DEBX  
63FBGA(LF)  
63FBGA(LF)  
63FBGA(LF)  
8Gb  
Extended  
16Gb(TBD)  
Extended  
1.1 Ordering Information  
K F x x H 6 Q 4 M - D E x x  
Samsung  
OneNAND Memory  
Speed  
6 : 66MHz  
8 : 83MHz  
Device Type  
M : Mux type Single Chip  
N : Mux type Dual Chip  
K: Mux type Quad Chip  
Product Line designator  
B : Include Bad Block  
D : Daisy Sample  
Density  
4G : 4Gb  
8G : 8Gb  
Operating Temperature Range  
AG : 16Gb(TBD)  
E = Extended Temp. (-30 °C to 85 °C)  
Package  
D : FBGA(Lead Free)  
Technology  
H : Flex  
Version  
1st Generation  
Organization  
6: x16 Organization  
Operating Voltage Range  
Page Architecture  
Q : 1.8V(1.7 V to 1.95V)  
4: 4KB Page  
- 4 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
1.2 General Overview  
Flex-MuxOneNANDis a monolithic integrated circuit with a NAND Flash array using a NOR Flash interface.  
The chip integrates system features including:  
A BootRAM(1KB) and bootloader  
4KB DataRAM buffers  
A High-Speed x16 Host Interface  
On-chip Error Correction  
On-chip NOR interface controller  
This on-chip integration enables system designers to reduce external system logic and use high-density NAND Flash in applications that  
would otherwise have to use more NOR components.  
Flex-MuxOneNAND takes advantage of the higher performance NAND program time, low power, and high density and combines it with the  
synchronous read performance of NOR. The NOR Flash host interface makes Flex-MuxOneNAND an ideal solution for mobile applications  
that have large, advanced multimedia applications and operating systems and need high performance.  
When integrated into a Samsung Multi-Chip-Package with Samsung Mobile DDR SDRAM, designers can complete a high-performance, small  
footprint solution.  
The device operates up to a maximum host-driven clock frequency of 66MHz / 83MHz for synchronous reads at Vcc(or Vccq. Refer to chapter  
4.2) with 4~7-clock latency. Appropriate wait cycles are determined by programmable read latency.  
Flex-MuxOneNAND provides for multiple sector read operations by assigning the number of sectors to be read in the sector counter register.  
The device includes one block-sized OTP (One Time Programmable) area and user-controlled 1st block OTP(Block 0) that can be used to  
increase system security or to provide identification capabilities.  
- 5 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
1.3 Product Features  
Device Architecture  
Design Technology:  
Supply Voltage:  
Host Interface:  
M die  
1.8V (1.7V ~ 1.95V)  
16 bit  
5KB Internal BufferRAM:  
NAND Array:  
1KB BootRAM, 4KB DataRAM  
SLC : (4K+128)B Page Size  
(256K+8K)B Block Size (64pages)  
MLC : (4K+128)B Page Size  
(512K+16K)B Block Size (128pages)  
Device Performance  
Host Interface Type:  
Synchronous Burst Read  
- Up to 66MHz / 83MHz clock frequency  
- Linear Burst 4-, 8-, 16-, 32-words with wrap around  
- Continuous 1K words Sequential Burst  
Synchronous Write  
- Up to 66MHz / 83MHz clock frequency  
- Linear Burst 4-, 8-, 16-, 32-, 1K-words with wrap around  
- Continuous 1K words Sequential Burst  
Asynchronous Random Read  
- 76ns access time  
Asynchronous Random Write  
Programmable Burst Read Latency:  
Latency 3,4(Default),5,6 and 7  
1~40MHz : Latency 3 available  
1~66MHz : Latency 4,5,6 and 7 available  
Over 66MHz : Latency 6,7 available  
Cold/Warm/Hot/NAND Flash Core Reset  
Typical Power,  
Multiple Reset Modes:  
Low Power Dissipation:  
- Standby current : 10uA (Single)  
- Synchronous Burst Read current(66MHz/83MHz, single) : 20/25mA  
- Synchronous Burst Write current(66MHz/83MHz, single) : 20/25mA  
- Load current : 50mA  
- Program current : 35mA  
- Erase current : 40mA  
Reliable CMOS Floating-Gate Technology  
- Endurance : 50K Program/Erase Cycles (SLC)  
10K Program/Erase Cycles (MLC)  
- Data Retention : 10 Years(SLC) /10 Years(MLC)  
System Hardware  
Voltage detector generating internal reset signal from Vcc  
Hardware reset input (RP)  
Data Protection Modes  
- Write Protection for BootRAM  
- Write Protection for NAND Flash Array  
- Write Protection during power-up  
- Write Protection during power-down  
User-controlled One Time Programmable(OTP) area  
Internal 4bit ECC  
Internal Bootloader supports Booting Solution in system  
Handshaking Feature  
- INT pin indicates Ready / Busy  
- Polling the interrupt register status bit  
- by ID register  
Detailed chip information  
Package size  
4G products  
8G products  
16G products(TBD)  
63ball, 10mm x 13mm x max 1.0mmt , 0.8mm ball pitch FBGA  
63ball, 10mm x 13mm x max 1.2mmt , 0.8mm ball pitch FBGA  
63ball, 10mm x 13mm x max 1.4mmt , 0.8mm ball pitch FBGA (TBD)  
- 6 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
2.0 DEVICE DESCRIPTION  
2.1 Detailed Product Description  
The Flex-MuxOneNAND is an advanced generation, high-performance MLC NAND-based Flash memory(Which can be programmed as both  
SLC and MLC).  
It integrates on-chip a convertible(SLC and MLC) NAND Flash Array memory with two independent data buffers, boot RAM buffer, a page  
buffer for the Flash array, and a one-time-programmable block.  
The combination of these memory areas enable high-speed pipelining of reads from host, BufferRAM, Page Buffer, and NAND Flash Array.  
Clock speeds up to 66MHz / 83MHz with a x16 wide I/O yields a 83MByte/second in SLC and 71MByte/second in MLC read bandwidth  
The Flex-MuxOneNAND also includes a Boot RAM and boot loader. This enables the device to efficiently load boot code at device startup  
from the NAND Array without the need for off-chip boot device.  
One block of the NAND Array is set aside as an OTP memory area, and 1st Block (Block 0) can be used as OTP area. This area, available to  
the user, can be configured and locked with secured user information.  
On-chip controller interfaces enable the device to operate in systems without NAND Host controllers.  
2.2 Definitions  
B (capital letter)  
W (capital letter)  
b (lower-case letter)  
ECC  
Byte, 8bits  
Word, 16bits  
Bit  
Error Correction Code  
Calculated ECC  
Written ECC  
BufferRAM  
ECC that has been calculated during a load or program access  
ECC that has been stored as data in the NAND Flash array or in the BufferRAM  
On-chip internal buffer consisting of BootRAM and DataRAM  
A 1KB portion of the BufferRAM reserved for Boot Code buffering  
A 4KB portion of the BufferRAM reserved for Data buffering (2KB x2)  
Part of a Page of which 512B is the main data area and 16B is the spare data area.  
BootRAM  
DataRAM  
Sector  
Possible data unit to be read from memory to BufferRAM or to be programmed to memory.  
- 4224B of which 4096 is in main area and 128B in spare area  
Data unit  
DDP  
QDP  
OTP  
Dual Die Package  
Quad Die Package  
One Time Programmable  
- 7 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
2.3 Pin Configuration  
2.3.1 4Gb (KFM4GH6Q4M) / 8Gb (KFN8GH6Q4M)  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
VSS  
OE  
VSS  
WE  
RP  
ADQ1  
ADQ2  
VCC  
Core  
ADQ3  
ADQ7 ADQ14  
ADQ6  
VCC  
IO  
ADQ8 ADQ11  
ADQ4  
ADQ15  
ADQ13  
AVD  
ADQ5 ADQ12  
NC  
ADQ0  
NC  
ADQ10 ADQ9  
CLK  
NC  
CE  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
INT  
NC  
NC  
NC  
NC  
RDY  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
(TOP VIEW, Balls Facing Down)  
63ball FBGA Flex-MuxOneNAND Chip  
63ball, 10mm x 13mm x max 1.0mmt , 0.8mm ball pitch FBGA(4Gb)  
63ball, 10mm x 13mm x max 1.2mmt , 0.8mm ball pitch FBGA (8Gb)  
- 8 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
2.3.2 16Gb Product (KFKAGH6Q4M) (TBD)  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
VSS  
OE  
VSS  
WE  
RP  
ADQ1  
ADQ2  
VCC  
Core  
ADQ3  
ADQ7 ADQ14  
ADQ6  
VCC  
IO  
ADQ8 ADQ11  
ADQ4  
ADQ15  
ADQ13  
AVD  
ADQ5 ADQ12  
NC  
ADQ0  
NC  
ADQ10 ADQ9  
CLK  
NC  
CE1  
NC  
INT2  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
INT1  
RDY  
NC  
NC  
NC  
NC  
NC  
CE2  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
(TOP VIEW, Balls Facing Down)  
63ball FBGA OneNAND Chip  
63ball, 10mm x 13mm x max 1.4mmt , 0.8mm ball pitch FBGA  
- 9 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
2.4 Pin Description  
Pin Name  
Type  
Nameand Description  
Host Interface  
Multiplexed Address/Data bus  
- Inputs for addresses during read operation, which are for addressing BufferRAM & Register.  
- Inputs data during program and commands for all operations, outputs data during memory array/  
register read cycles.  
ADQ15~ADQ0  
INT / INT1  
I/O  
Data pins float to high-impedance when the chip is deselected or outputs are disabled.  
Interrupt  
Notifies the Host when a command is completed. After power-up, it is at hi-z condition. Once IOBE is set to 1, it does not float  
to hi-z condition even when CE is disabled or OE is disabled. Especially, only when reset(Cold, Warm, Hot, NAND Flash  
Core) command in DDP are issued, it operates as open drain output with internal resistor (~50Kohm). The INT is the interrupt  
for Single or DDP device. The INT1 is the interrupt for the first DDP device(KFN8GH6Q4M) in QDP(KFKAGH6Q4M)  
O
Interrupt  
INT2  
RDY  
O
O
The INT2 is the interrupt for the second DDP device(KFN8GH6Q4M) in QDP(KFKAGH6Q4M)  
Ready  
Indicates data valid in synchronous read modes and is activated while CE is low  
Clock  
CLK  
WE  
I
I
CLK synchronizes the device to the system bus frequency in synchronous read mode.  
The first rising edge of CLK in conjunction with AVD low latches address input.  
Write Enable  
WE controls writes to the bufferRAM and registers. Datas are latched on the WE pulse’s rising edge  
Address Valid Detect  
Indicates valid address presence on address inputs. During asynchronous read operation, all addresses are valid while AVD  
is low, and during synchronous read operation, all addresses are latched on CLK’s rising edge while AVD is held low for one  
AVD  
RP  
I
clock cycle.  
> Low : for asynchronous mode, indicates valid address; for burst mode, causes starting address to be latched on rising edge  
on CLK  
> High : device ignores address inputs  
Reset Pin  
I
I
When low, RP resets internal operation of Flex-MuxOneNAND. RP status is do not care during power-up  
and bootloading. When high, RP level must be equivalent to Vcc-IO / Vccq level.  
Chip Enable  
CE-low activates internal control logic, and CE-high deselects the device, places it in standby state,  
and places DQ in Hi-Z.  
The CE input enables device for Single or DDP .  
CE / CE1  
CE2  
The CE1 input enables the first DDP device(KFN8GH6Q4M) in QDP(KFKAGH6Q4M)  
Chip Enable  
I
I
The CE2 input enables the second DDP device(KFN8GH6Q4M) in QDP(KFKAGH6Q4M)  
Output Enable  
OE  
OE-low enables the device’s output data buffers during a read cycle.  
Power Supply  
VCC-Core  
/ Vcc  
Power for Flex-MuxOneNAND Core  
This is the power supply for Flex-MuxOneNAND Core.  
Power for Flex-MuxOneNAND I/O  
This is the power supply for Flex-MuxOneNAND I/O  
Vcc-IO / Vccq is internally separated from Vcc-Core / Vcc.  
VCC-IO  
/ Vccq  
VSS  
Ground for Flex-MuxOneNAND  
etc.  
Do Not Use  
DNU  
Leave it disconnected. These pins are used for testing.  
No Connection  
Lead is not internally connected.  
NC  
NOTE :  
Do not leave power supply(Vcc-Core/Vcc-IO, VSS) disconnected.  
- 10 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
2.5 Block Diagram  
BufferRAM  
1st Block OTP  
(Block 0)  
Bootloader  
ADQ15~ADQ0  
BootRAM  
StateMachine  
CLK  
CE / CE1  
DataRAM0  
DataRAM1  
CE2  
OE  
NAND Flash  
Array  
WE  
RP  
Error  
Correction  
Logic  
AVD  
Internal Registers  
INT/INT1  
(Address/Command/Configuration  
/Status Registers)  
INT2  
RDY  
OTP  
(One Block)  
2.6 Memory Array Organization  
The Flex-MuxOneNAND architecture integrates several memory areas on a single chip.  
2.6.1 Internal (NAND Array) Memory Organization  
The on-chip internal memory is a convertible(SLC and MLC) NAND array used for data storage and code. The internal memory is divided into  
a main area and a spare area.  
Main Area  
The main area is the primary memory array. A block incorporates 64pages(SLC) or 128pages(MLC). A main page size is 4KB and a main  
page is comprised of 8 sectors each size of which is 512Byte.  
Spare Area  
The spare area is used for invalid block information and ECC storage. Spare area internal memory is associated with corresponding main area  
memory. A spare page size is 128B and a spare page is comprised of 8 sectors each size of which is 16Byte.  
- 11 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
Internal Memory Array Information  
Area  
Block  
256KB  
512KB  
8KB  
Page  
Sector  
Main(SLC)  
Main(MLC)  
Spare(SLC)  
Spare(MLC)  
4KB  
512B  
128B  
16B  
16KB  
Internal Memory Array Organization  
Sector  
Main Area  
512B  
Spare Area  
16B  
Page  
Main Area  
Spare Area  
Sector0 Sector1  
Sector2  
Sector4 Sector5  
Sector2  
Sector7  
Sector3  
Sector6 Sector7  
Sector0 Sector1  
Sector3 Sector4 Sector5 Sector6  
4KB(512Bx8)  
128B(16Bx8)  
Block(MLC)  
Main Area  
Spare Area  
4KB Page0  
128B Page0  
Page 0  
4KB Page127  
512KB  
128B Page127  
16KB  
Page 127  
Block(SLC)  
Main Area  
Spare Area  
4KB Page0  
128B Page0  
Page 0  
4KB Page63  
256KB  
128B Page63  
8KB  
Page 63  
- 12 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
2.6.2 External (BufferRAM) Memory Organization  
The on-chip external memory is comprised of 3 buffers used for Boot Code storage and data buffering.  
The BootRAM is a buffer that receives Boot Code from the internal memory and makes it available to the host at start up.  
There are 4KB bi-directional data buffers(2KB x2), DataRAM0 and DataRAM1. During Boot Up, the BootRam is used by the host to initialize  
the main memory, and deliver boot code from NAND Flash core to host.  
Internal (Nand Array)  
External (BufferRAM)  
Memory  
Memory  
Boot code  
BootRAM (1KB)  
Nand Array  
Host  
DataRAM0 (2KB)  
DataRAM1 (2KB)  
OTP Block  
The external memory is divided into a main area and a spare area. Each buffer is the equivalent size of a Sector.  
The main area data is 512B. The spare area data is 16B.  
External Memory Array Information  
Area  
BootRAM  
1KB+32B  
2
DataRAM0  
2KB+64B  
4
DataRAM1  
2KB+64B  
4
Total Size  
Number of Sectors  
Main  
Spare  
512B  
512B  
512B  
Sector  
16B  
16B  
16B  
External Memory Array Organization  
Spare area data  
(16B)  
Main area data  
(512B)  
BootRAM 0  
BootRAM 1  
Sector: (512 + 16) Byte  
BootRAM  
DataRAM 0_0  
DataRAM 0_1  
DataRAM 0_2  
DataRAM 0_3  
DataRAM0  
4KByte  
DataRAM 1_0  
DataRAM 1_1  
DataRAM 1_2  
DataRAM 1_3  
DataRAM1  
- 13 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
2.7 Memory Map  
The following tables are the memory maps for the Flex-MuxOneNAND.  
2.7.1 Internal (NAND Array) Memory Organization  
The following tables show the Internal Memory address map in word order.  
Block Address  
[F100h]  
Page Address  
[F107h]  
Block Address  
[F100h]  
Page Address  
Size  
Block  
Size  
Block  
[F107h]  
Block0  
Block1  
0000h  
0001h  
0002h  
0003h  
0004h  
0005h  
0006h  
0007h  
0008h  
0009h  
000Ah  
000Bh  
000Ch  
000Dh  
000Eh  
000Fh  
0010h  
0011h  
0012h  
0013h  
0014h  
0015h  
0016h  
0017h  
0018h  
0019h  
001Ah  
001Bh  
001Ch  
001Dh  
001Eh  
001Fh  
0000h~00FCh  
256KB  
Block32  
Block33  
Block34  
Block35  
Block36  
Block37  
Block38  
Block39  
Block40  
Block41  
Block42  
Block43  
Block44  
Block45  
Block46  
Block47  
Block48  
Block49  
Block50  
Block51  
Block52  
Block53  
Block54  
Block55  
Block56  
Block57  
Block58  
Block59  
Block60  
Block61  
Block62  
Block63  
0020h  
0021h  
0022h  
0023h  
0024h  
0025h  
0026h  
0027h  
0028h  
0029h  
002Ah  
002Bh  
002Ch  
002Dh  
002Eh  
002Fh  
0030h  
0031h  
0032h  
0033h  
0034h  
0035h  
0036h  
0037h  
0038h  
0039h  
003Ah  
003Bh  
003Ch  
003Dh  
003Eh  
003Fh  
Block2  
Block3  
Block4  
Block5  
Block6  
Block7  
Block8  
Block9  
Block10  
Block11  
Block12  
Block13  
Block14  
Block15  
Block16  
Block17  
Block18  
Block19  
Block20  
Block21  
Block22  
Block23  
Block24  
Block25  
Block26  
Block27  
Block28  
Block29  
Block30  
Block31  
SLC:  
SLC:  
SLC:  
0000h~00FCh*,  
SLC:  
256KB,  
0000h~00FCh*,  
256KB,  
MLC:  
MLC:  
MLC:  
0000h~01FCh*  
MLC:  
512KB  
0000h~01FCh*  
512KB  
* Only four sectors are addressable, see Start Address Register .  
- 14 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
Block Address  
[F100h]  
Page Address  
[F107h]  
Block Address  
[F100h]  
Page Address  
Size  
Block  
Size  
Block  
[F107h]  
Block64  
Block65  
Block66  
Block67  
Block68  
Block69  
Block70  
Block71  
Block72  
Block73  
Block74  
Block75  
Block76  
Block77  
Block78  
Block79  
Block80  
Block81  
Block82  
Block83  
Block84  
Block85  
Block86  
Block87  
Block88  
Block89  
Block90  
Block91  
Block92  
Block93  
Block94  
Block95  
0040h  
0041h  
0042h  
0043h  
0044h  
0045h  
0046h  
0047h  
0048h  
0049h  
004Ah  
004Bh  
004Ch  
004Dh  
004Eh  
004Fh  
0050h  
0051h  
0052h  
0053h  
0054h  
0055h  
0056h  
0057h  
0058h  
0059h  
005Ah  
005Bh  
005Ch  
005Dh  
005Eh  
005Fh  
Block96  
Block97  
0060h  
0061h  
0062h  
0063h  
0064h  
0065h  
0066h  
0067h  
0068h  
0069h  
006Ah  
006Bh  
006Ch  
006Dh  
006Eh  
006Fh  
0070h  
0071h  
0072h  
0073h  
0074h  
0075h  
0076h  
0077h  
0078h  
0079h  
007Ah  
007Bh  
007Ch  
007Dh  
007Eh  
007Fh  
Block98  
Block99  
Block100  
Block101  
Block102  
Block103  
Block104  
Block105  
Block106  
Block107  
Block108  
Block109  
Block110  
Block111  
Block112  
Block113  
Block114  
Block115  
Block116  
Block117  
Block118  
Block119  
Block120  
Block121  
Block122  
Block123  
Block124  
Block125  
Block126  
Block127  
SLC:  
0000h~00FCh,  
SLC:  
256KB,  
SLC:  
0000h~00FCh,  
SLC:  
256KB,  
MLC:  
0000h~01FCh  
MLC:  
512KB  
MLC:  
0000h~01FCh  
MLC:  
512KB  
- 15 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
Block Address  
[F100h]  
Page Address  
[F107h]  
Block Address  
[F100h]  
Page Address  
Size  
Block  
Size  
Block  
[F107h]  
Block128  
Block129  
Block130  
Block131  
Block132  
Block133  
Block134  
Block135  
Block136  
Block137  
Block138  
Block139  
Block140  
Block141  
Block142  
Block143  
Block144  
Block145  
Block146  
Block147  
Block148  
Block149  
Block150  
Block151  
Block152  
Block153  
Block154  
Block155  
Block156  
Block157  
Block158  
Block159  
0080h  
0081h  
0082h  
0083h  
0084h  
0085h  
0086h  
0087h  
0088h  
0089h  
008Ah  
008Bh  
008Ch  
008Dh  
008Eh  
008Fh  
0090h  
0091h  
0092h  
0093h  
0094h  
0095h  
0096h  
0097h  
0098h  
0099h  
009Ah  
009Bh  
009Ch  
009Dh  
009Eh  
009Fh  
Block160  
Block161  
Block162  
Block163  
Block164  
Block165  
Block166  
Block167  
Block168  
Block169  
Block170  
Block171  
Block172  
Block173  
Block174  
Block175  
Block176  
Block177  
Block178  
Block179  
Block180  
Block181  
Block182  
Block183  
Block184  
Block185  
Block186  
Block187  
Block188  
Block189  
Block190  
Block191  
00A0h  
00A1h  
00A2h  
00A3h  
00A4h  
00A5h  
00A6h  
00A7h  
00A8h  
00A9h  
00AAh  
00ABh  
00ACh  
00ADh  
00AEh  
00AFh  
00B0h  
00B1h  
00B2h  
00B3h  
00B4h  
00B5h  
00B6h  
00B7h  
00B8h  
00B9h  
00BAh  
00BBh  
00BCh  
00BDh  
00BEh  
00BFh  
SLC:  
0000h~00FCh,  
SLC:  
256KB,  
SLC:  
0000h~00FCh,  
SLC:  
256KB,  
MLC:  
0000h~01FCh  
MLC:  
512KB  
MLC:  
0000h~01FCh  
MLC:  
512KB  
- 16 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
Block Address  
[F100h]  
Page Address  
[F107h]  
Block Address  
[F100h]  
Page Address  
Size  
Block  
Size  
Block  
[F107h]  
Block192  
Block193  
Block194  
Block195  
Block196  
Block197  
Block198  
Block199  
Block200  
Block201  
Block202  
Block203  
Block204  
Block205  
Block206  
Block207  
Block208  
Block209  
Block210  
Block211  
Block212  
Block213  
Block214  
Block215  
Block216  
Block217  
Block218  
Block219  
Block220  
Block221  
Block222  
Block223  
00C0h  
00C1h  
00C2h  
00C3h  
00C4h  
00C5h  
00C6h  
00C7h  
00C8h  
00C9h  
00CAh  
00CBh  
00CCh  
00CDh  
00CEh  
00CFh  
00D0h  
00D1h  
00D2h  
00D3h  
00D4h  
00D5h  
00D6h  
00D7h  
00D8h  
00D9h  
00DAh  
00DBh  
00DCh  
00DDh  
00DEh  
00DFh  
Block224  
Block225  
Block226  
Block227  
Block228  
Block229  
Block230  
Block231  
Block232  
Block233  
Block234  
Block235  
Block236  
Block237  
Block238  
Block239  
Block240  
Block241  
Block242  
Block243  
Block244  
Block245  
Block246  
Block247  
Block248  
Block249  
Block250  
Block251  
Block252  
Block253  
Block254  
Block255  
00E0h  
00E1h  
00E2h  
00E3h  
00E4h  
00E5h  
00E6h  
00E7h  
00E8h  
00E9h  
00EAh  
00EBh  
00ECh  
00EDh  
00EEh  
00EFh  
00F0h  
00F1h  
00F2h  
00F3h  
00F4h  
00F5h  
00F6h  
00F7h  
00F8h  
00F9h  
00FAh  
00FBh  
00FCh  
00FDh  
00FEh  
00FFh  
SLC:  
0000h~00FCh,  
SLC:  
256KB,  
SLC:  
0000h~00FCh,  
SLC:  
256KB,  
MLC:  
0000h~01FCh  
MLC:  
512KB  
MLC:  
0000h~01FCh  
MLC:  
512KB  
- 17 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
Block Address  
[F100h]  
Page Address  
[F107h]  
Block Address  
[F100h]  
Page Address  
Size  
Block  
Size  
Block  
[F107h]  
Block256  
Block257  
Block258  
Block259  
Block260  
Block261  
Block262  
Block263  
Block264  
Block265  
Block266  
Block267  
Block268  
Block269  
Block270  
Block271  
Block272  
Block273  
Block274  
Block275  
Block276  
Block277  
Block278  
Block279  
Block280  
Block281  
Block282  
Block283  
Block284  
Block285  
Block286  
Block287  
0100h  
0101h  
0102h  
0103h  
0104h  
0105h  
0106h  
0107h  
0108h  
0109h  
010Ah  
010Bh  
010Ch  
010Dh  
010Eh  
010Fh  
0110h  
0111h  
0112h  
0113h  
0114h  
0115h  
0116h  
0117h  
0118h  
0119h  
011Ah  
011Bh  
011Ch  
011Dh  
011Eh  
011Fh  
Block288  
Block289  
Block290  
Block291  
Block292  
Block293  
Block294  
Block295  
Block296  
Block297  
Block298  
Block299  
Block300  
Block301  
Block302  
Block303  
Block304  
Block305  
Block306  
Block307  
Block308  
Block309  
Block310  
Block311  
Block312  
Block313  
Block314  
Block315  
Block316  
Block317  
Block318  
Block319  
0120h  
0121h  
0122h  
0123h  
0124h  
0125h  
0126h  
0127h  
0128h  
0129h  
012Ah  
012Bh  
012Ch  
012Dh  
012Eh  
012Fh  
0130h  
0131h  
0132h  
0133h  
0134h  
0135h  
0136h  
0137h  
0138h  
0139h  
013Ah  
013Bh  
013Ch  
013Dh  
013Eh  
013Fh  
SLC:  
0000h~00FCh,  
SLC:  
256KB,  
SLC:  
0000h~00FCh,  
SLC:  
256KB,  
MLC:  
0000h~01FCh  
MLC:  
512KB  
MLC:  
0000h~01FCh  
MLC:  
512KB  
- 18 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
Block Address  
[F100h]  
Page Address  
[F107h]  
Block Address  
[F100h]  
Page Address  
Size  
Block  
Size  
Block  
[F107h]  
Block320  
Block321  
Block322  
Block323  
Block324  
Block325  
Block326  
Block327  
Block328  
Block329  
Block330  
Block331  
Block332  
Block333  
Block334  
Block335  
Block336  
Block337  
Block338  
Block339  
Block340  
Block341  
Block342  
Block343  
Block344  
Block345  
Block346  
Block347  
Block348  
Block349  
Block350  
Block351  
0140h  
0141h  
0142h  
0143h  
0144h  
0145h  
0146h  
0147h  
0148h  
0149h  
014Ah  
014Bh  
014Ch  
014Dh  
014Eh  
014Fh  
0150h  
0151h  
0152h  
0153h  
0154h  
0155h  
0156h  
0157h  
0158h  
0159h  
015Ah  
015Bh  
015Ch  
015Dh  
015Eh  
015Fh  
Block352  
Block353  
Block354  
Block355  
Block356  
Block357  
Block358  
Block359  
Block360  
Block361  
Block362  
Block363  
Block364  
Block365  
Block366  
Block367  
Block368  
Block369  
Block370  
Block371  
Block372  
Block373  
Block374  
Block375  
Block376  
Block377  
Block378  
Block379  
Block380  
Block381  
Block382  
Block383  
0160h  
0161h  
0162h  
0163h  
0164h  
0165h  
0166h  
0167h  
0168h  
0169h  
016Ah  
016Bh  
016Ch  
016Dh  
016Eh  
016Fh  
0170h  
0171h  
0172h  
0173h  
0174h  
0175h  
0176h  
0177h  
0178h  
0179h  
017Ah  
017Bh  
017Ch  
017Dh  
017Eh  
017Fh  
SLC:  
0000h~00FCh,  
SLC:  
256KB,  
SLC:  
0000h~00FCh,  
SLC:  
256KB,  
MLC:  
0000h~01FCh  
MLC:  
512KB  
MLC:  
0000h~01FCh  
MLC:  
512KB  
- 19 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
Block Address  
[F100h]  
Page Address  
[F107h]  
Block Address  
[F100h]  
Page Address  
Size  
Block  
Size  
Block  
[F107h]  
Block384  
Block385  
Block386  
Block387  
Block388  
Block389  
Block390  
Block391  
Block392  
Block393  
Block394  
Block395  
Block396  
Block397  
Block398  
Block399  
Block400  
Block401  
Block402  
Block403  
Block404  
Block405  
Block406  
Block407  
Block408  
Block409  
Block410  
Block411  
Block412  
Block413  
Block414  
Block415  
0180h  
0181h  
0182h  
0183h  
0184h  
0185h  
0186h  
0187h  
0188h  
0189h  
018Ah  
018Bh  
018Ch  
018Dh  
018Eh  
018Fh  
0190h  
0191h  
0192h  
0193h  
0194h  
0195h  
0196h  
0197h  
0198h  
0199h  
019Ah  
019Bh  
019Ch  
019Dh  
019Eh  
019Fh  
Block416  
Block417  
Block418  
Block419  
Block420  
Block421  
Block422  
Block423  
Block424  
Block425  
Block426  
Block427  
Block428  
Block429  
Block430  
Block431  
Block432  
Block433  
Block434  
Block435  
Block436  
Block437  
Block438  
Block439  
Block440  
Block441  
Block442  
Block443  
Block444  
Block445  
Block446  
Block447  
01A0h  
01A1h  
01A2h  
01A3h  
01A4h  
01A5h  
01A6h  
01A7h  
01A8h  
01A9h  
01AAh  
01ABh  
01ACh  
01ADh  
01AEh  
01AFh  
01B0h  
01B1h  
01B2h  
01B3h  
01B4h  
01B5h  
01B6h  
01B7h  
01B8h  
01B9h  
01BAh  
01BBh  
01BCh  
01BDh  
01BEh  
01BFh  
SLC:  
0000h~00FCh,  
SLC:  
256KB,  
SLC:  
0000h~00FCh,  
SLC:  
256KB,  
MLC:  
0000h~01FCh  
MLC:  
512KB  
MLC:  
0000h~01FCh  
MLC:  
512KB  
- 20 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
Block Address  
[F100h]  
Page Address  
[F107h]  
Block Address  
[F100h]  
Page Address  
Size  
Block  
Size  
Block  
[F107h]  
Block448  
Block449  
Block450  
Block451  
Block452  
Block453  
Block454  
Block455  
Block456  
Block457  
Block458  
Block459  
Block460  
Block461  
Block462  
Block463  
Block464  
Block465  
Block466  
Block467  
Block468  
Block469  
Block470  
Block471  
Block472  
Block473  
Block474  
Block475  
Block476  
Block477  
Block478  
Block479  
01C0h  
01C1h  
01C2h  
01C3h  
01C4h  
01C5h  
01C6h  
01C7h  
01C8h  
01C9h  
01CAh  
01CBh  
01CCh  
01CDh  
01CEh  
01CFh  
01D0h  
01D1h  
01D2h  
01D3h  
01D4h  
01D5h  
01D6h  
01D7h  
01D8h  
01D9h  
01DAh  
01DBh  
01DCh  
01DDh  
01DEh  
01DFh  
Block480  
Block481  
Block482  
Block483  
Block484  
Block485  
Block486  
Block487  
Block488  
Block489  
Block490  
Block491  
Block492  
Block493  
Block494  
Block495  
Block496  
Block497  
Block498  
Block499  
Block500  
Block501  
Block502  
Block503  
Block504  
Block505  
Block506  
Block507  
Block508  
Block509  
Block510  
Block511  
01E0h  
01E1h  
01E2h  
01E3h  
01E4h  
01E5h  
01E6h  
01E7h  
01E8h  
01E9h  
01EAh  
01EBh  
01ECh  
01EDh  
01EEh  
01EFh  
01F0h  
01F1h  
01F2h  
01F3h  
01F4h  
01F5h  
01F6h  
01F7h  
01F8h  
01F9h  
01FAh  
01FBh  
01FCh  
01FDh  
01FEh  
01FFh  
SLC:  
0000h~00FCh,  
SLC:  
256KB,  
SLC:  
0000h~00FCh,  
SLC:  
256KB,  
MLC:  
0000h~01FCh  
MLC:  
512KB  
MLC:  
0000h~01FCh  
MLC:  
512KB  
- 21 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
Block Address  
[F100h]  
Page Address  
[F107h]  
Block Address  
[F100h]  
Page Address  
Size  
Block  
Size  
Block  
[F107h]  
Block512  
Block513  
Block514  
Block515  
Block516  
Block517  
Block518  
Block519  
Block520  
Block521  
Block522  
Block523  
Block524  
Block525  
Block526  
Block527  
Block528  
Block529  
Block530  
Block531  
Block532  
Block533  
Block534  
Block535  
Block536  
Block537  
Block538  
Block539  
Block540  
Block541  
Block542  
Block543  
0200h  
0201h  
0202h  
0203h  
0204h  
0205h  
0206h  
0207h  
0208h  
0209h  
020Ah  
020Bh  
020Ch  
020Dh  
020Eh  
020Fh  
0210h  
0211h  
0212h  
0213h  
0214h  
0215h  
0216h  
0217h  
0218h  
0219h  
021Ah  
021Bh  
021Ch  
021Dh  
021Eh  
021Fh  
Block544  
Block545  
Block546  
Block547  
Block548  
Block549  
Block550  
Block551  
Block552  
Block553  
Block554  
Block555  
Block556  
Block557  
Block558  
Block559  
Block560  
Block561  
Block562  
Block563  
Block564  
Block565  
Block566  
Block567  
Block568  
Block569  
Block570  
Block571  
Block572  
Block573  
Block574  
Block575  
0220h  
0221h  
0222h  
0223h  
0224h  
0225h  
0226h  
0227h  
0228h  
0229h  
022Ah  
022Bh  
022Ch  
022Dh  
022Eh  
022Fh  
0230h  
0231h  
0232h  
0233h  
0234h  
0235h  
0236h  
0237h  
0238h  
0239h  
023Ah  
023Bh  
023Ch  
023Dh  
023Eh  
023Fh  
SLC:  
0000h~00FCh,  
SLC:  
256KB,  
SLC:  
0000h~00FCh,  
SLC:  
256KB,  
MLC:  
0000h~01FCh  
MLC:  
512KB  
MLC:  
0000h~01FCh  
MLC:  
512KB  
- 22 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
Block Address  
[F100h]  
Page Address  
[F107h]  
Block Address  
[F100h]  
Page Address  
Size  
Block  
Size  
Block  
[F107h]  
Block576  
Block577  
Block578  
Block579  
Block580  
Block581  
Block582  
Block583  
Block584  
Block585  
Block586  
Block587  
Block588  
Block589  
Block590  
Block591  
Block592  
Block593  
Block594  
Block595  
Block596  
Block597  
Block598  
Block599  
Block600  
Block601  
Block602  
Block603  
Block604  
Block605  
Block606  
Block607  
0240h  
0241h  
0242h  
0243h  
0244h  
0245h  
0246h  
0247h  
0248h  
0249h  
024Ah  
024Bh  
024Ch  
024Dh  
024Eh  
024Fh  
0250h  
0251h  
0252h  
0253h  
0254h  
0255h  
0256h  
0257h  
0258h  
0259h  
025Ah  
025Bh  
025Ch  
025Dh  
025Eh  
025Fh  
Block608  
Block609  
Block610  
Block611  
Block612  
Block613  
Block614  
Block615  
Block616  
Block617  
Block618  
Block619  
Block620  
Block621  
Block622  
Block623  
Block624  
Block625  
Block626  
Block627  
Block628  
Block629  
Block630  
Block631  
Block632  
Block633  
Block634  
Block635  
Block636  
Block637  
Block638  
Block639  
0260h  
0261h  
0262h  
0263h  
0264h  
0265h  
0266h  
0267h  
0268h  
0269h  
026Ah  
026Bh  
026Ch  
026Dh  
026Eh  
026Fh  
0270h  
0271h  
0272h  
0273h  
0274h  
0275h  
0276h  
0277h  
0278h  
0279h  
027Ah  
027Bh  
027Ch  
027Dh  
027Eh  
027Fh  
SLC:  
0000h~00FCh,  
SLC:  
256KB,  
SLC:  
0000h~00FCh,  
SLC:  
256KB,  
MLC:  
0000h~01FCh  
MLC:  
512KB  
MLC:  
0000h~01FCh  
MLC:  
512KB  
- 23 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
Block Address  
[F100h]  
Page Address  
[F107h]  
Block Address  
[F100h]  
Page Address  
Size  
Block  
Size  
Block  
[F107h]  
Block640  
Block641  
Block642  
Block643  
Block644  
Block645  
Block646  
Block647  
Block648  
Block649  
Block650  
Block651  
Block652  
Block653  
Block654  
Block655  
Block656  
Block657  
Block658  
Block659  
Block660  
Block661  
Block662  
Block663  
Block664  
Block665  
Block666  
Block667  
Block668  
Block669  
Block670  
Block671  
0280h  
0281h  
0282h  
0283h  
0284h  
0285h  
0286h  
0287h  
0288h  
0289h  
028Ah  
028Bh  
028Ch  
028Dh  
028Eh  
028Fh  
0290h  
0291h  
0292h  
0293h  
0294h  
0295h  
0296h  
0297h  
0298h  
0299h  
029Ah  
029Bh  
029Ch  
029Dh  
029Eh  
029Fh  
Block672  
Block673  
Block674  
Block675  
Block676  
Block677  
Block678  
Block679  
Block680  
Block681  
Block682  
Block683  
Block684  
Block685  
Block686  
Block687  
Block688  
Block689  
Block690  
Block691  
Block692  
Block693  
Block694  
Block695  
Block696  
Block697  
Block698  
Block699  
Block700  
Block701  
Block702  
Block703  
02A0h  
02A1h  
02A2h  
02A3h  
02A4h  
02A5h  
02A6h  
02A7h  
02A8h  
02A9h  
02AAh  
02ABh  
02ACh  
02ADh  
02AEh  
02AFh  
02B0h  
02B1h  
02B2h  
02B3h  
02B4h  
02B5h  
02B6h  
02B7h  
02B8h  
02B9h  
02BAh  
02BBh  
02BCh  
02BDh  
02BEh  
02BFh  
SLC:  
0000h~00FCh,  
SLC:  
256KB,  
SLC:  
0000h~00FCh,  
SLC:  
256KB,  
MLC:  
0000h~01FCh  
MLC:  
512KB  
MLC:  
0000h~01FCh  
MLC:  
512KB  
- 24 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
Block Address  
[F100h]  
Page Address  
[F107h]  
Block Address  
[F100h]  
Page Address  
Size  
Block  
Size  
Block  
[F107h]  
Block704  
Block705  
Block706  
Block707  
Block708  
Block709  
Block710  
Block711  
Block712  
Block713  
Block714  
Block715  
Block716  
Block717  
Block718  
Block719  
Block720  
Block721  
Block722  
Block723  
Block724  
Block725  
Block726  
Block727  
Block728  
Block729  
Block730  
Block731  
Block732  
Block733  
Block734  
Block735  
02C0h  
02C1h  
02C2h  
02C3h  
02C4h  
02C5h  
02C6h  
02C7h  
02C8h  
02C9h  
02CAh  
02CBh  
02CCh  
02CDh  
02CEh  
02CFh  
02D0h  
02D1h  
02D2h  
02D3h  
02D4h  
02D5h  
02D6h  
02D7h  
02D8h  
02D9h  
02DAh  
02DBh  
02DCh  
02DDh  
02DEh  
02DFh  
Block736  
Block737  
Block738  
Block739  
Block740  
Block741  
Block742  
Block743  
Block744  
Block745  
Block746  
Block747  
Block748  
Block749  
Block750  
Block751  
Block752  
Block753  
Block754  
Block755  
Block756  
Block757  
Block758  
Block759  
Block760  
Block761  
Block762  
Block763  
Block764  
Block765  
Block766  
Block767  
02E0h  
02E1h  
02E2h  
02E3h  
02E4h  
02E5h  
02E6h  
02E7h  
02E8h  
02E9h  
02EAh  
02EBh  
02ECh  
02EDh  
02EEh  
02EFh  
02F0h  
02F1h  
02F2h  
02F3h  
02F4h  
02F5h  
02F6h  
02F7h  
02F8h  
02F9h  
02FAh  
02FBh  
02FCh  
02FDh  
02FEh  
02FFh  
SLC:  
0000h~00FCh,  
SLC:  
256KB,  
SLC:  
0000h~00FCh,  
SLC:  
256KB,  
MLC:  
0000h~01FCh  
MLC:  
512KB  
MLC:  
0000h~01FCh  
MLC:  
512KB  
- 25 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
Block Address  
[F100h]  
Page Address  
[F107h]  
Block Address  
[F100h]  
Page Address  
Size  
Block  
Size  
Block  
[F107h]  
Block768  
Block769  
Block770  
Block771  
Block772  
Block773  
Block774  
Block775  
Block776  
Block777  
Block778  
Block779  
Block780  
Block781  
Block782  
Block783  
Block784  
Block785  
Block786  
Block787  
Block788  
Block789  
Block790  
Block791  
Block792  
Block793  
Block794  
Block795  
Block796  
Block797  
Block798  
Block799  
0300h  
0301h  
0302h  
0303h  
0304h  
0305h  
0306h  
0307h  
0308h  
0309h  
030Ah  
030Bh  
030Ch  
030Dh  
030Eh  
030Fh  
0310h  
0311h  
0312h  
0313h  
0314h  
0315h  
0316h  
0317h  
0318h  
0319h  
031Ah  
031Bh  
031Ch  
031Dh  
031Eh  
031Fh  
Block800  
Block801  
Block802  
Block803  
Block804  
Block805  
Block806  
Block807  
Block808  
Block809  
Block810  
Block811  
Block812  
Block813  
Block814  
Block815  
Block816  
Block817  
Block818  
Block819  
Block820  
Block821  
Block822  
Block823  
Block824  
Block825  
Block826  
Block827  
Block828  
Block829  
Block830  
Block831  
0320h  
0321h  
0322h  
0323h  
0324h  
0325h  
0326h  
0327h  
0328h  
0329h  
032Ah  
032Bh  
032Ch  
032Dh  
032Eh  
032Fh  
0330h  
0331h  
0332h  
0333h  
0334h  
0335h  
0336h  
0337h  
0338h  
0339h  
033Ah  
033Bh  
033Ch  
033Dh  
033Eh  
033Fh  
SLC:  
0000h~00FCh,  
SLC:  
256KB,  
SLC:  
0000h~00FCh,  
SLC:  
256KB,  
MLC:  
0000h~01FCh  
MLC:  
512KB  
MLC:  
0000h~01FCh  
MLC:  
512KB  
- 26 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
Block Address  
[F100h]  
Page Address  
[F107h]  
Block Address  
[F100h]  
Page Address  
Size  
Block  
Size  
Block  
[F107h]  
Block832  
Block833  
Block834  
Block835  
Block836  
Block837  
Block838  
Block839  
Block840  
Block841  
Block842  
Block843  
Block844  
Block845  
Block846  
Block847  
Block848  
Block849  
Block850  
Block851  
Block852  
Block853  
Block854  
Block855  
Block856  
Block857  
Block858  
Block859  
Block860  
Block861  
Block862  
Block863  
0340h  
0341h  
0342h  
0343h  
0344h  
0345h  
0346h  
0347h  
0348h  
0349h  
034Ah  
034Bh  
034Ch  
034Dh  
034Eh  
034Fh  
0350h  
0351h  
0352h  
0353h  
0354h  
0355h  
0356h  
0357h  
0358h  
0359h  
035Ah  
035Bh  
035Ch  
035Dh  
035Eh  
035Fh  
Block864  
Block865  
Block866  
Block867  
Block868  
Block869  
Block870  
Block871  
Block872  
Block873  
Block874  
Block875  
Block876  
Block877  
Block878  
Block879  
Block880  
Block881  
Block882  
Block883  
Block884  
Block885  
Block886  
Block887  
Block888  
Block889  
Block890  
Block891  
Block892  
Block893  
Block894  
Block895  
0360h  
0361h  
0362h  
0363h  
0364h  
0365h  
0366h  
0367h  
0368h  
0369h  
036Ah  
036Bh  
036Ch  
036Dh  
036Eh  
036Fh  
0370h  
0371h  
0372h  
0373h  
0374h  
0375h  
0376h  
0377h  
0378h  
0379h  
037Ah  
037Bh  
037Ch  
037Dh  
037Eh  
037Fh  
SLC:  
0000h~00FCh,  
SLC:  
256KB,  
SLC:  
0000h~00FCh,  
SLC:  
256KB,  
MLC:  
0000h~01FCh  
MLC:  
512KB  
MLC:  
0000h~01FCh  
MLC:  
512KB  
- 27 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
Block Address  
[F100h]  
Page Address  
[F107h]  
Block Address  
[F100h]  
Page Address  
Size  
Block  
Size  
Block  
[F107h]  
Block896  
Block897  
Block898  
Block899  
Block900  
Block901  
Block902  
Block903  
Block904  
Block905  
Block906  
Block907  
Block908  
Block909  
Block910  
Block911  
Block912  
Block913  
Block914  
Block915  
Block916  
Block917  
Block918  
Block919  
Block920  
Block921  
Block922  
Block923  
Block924  
Block925  
Block926  
Block927  
0380h  
0381h  
0382h  
0383h  
0384h  
0385h  
0386h  
0387h  
0388h  
0389h  
038Ah  
038Bh  
038Ch  
038Dh  
038Eh  
038Fh  
0390h  
0391h  
0392h  
0393h  
0394h  
0395h  
0396h  
0397h  
0398h  
0399h  
039Ah  
039Bh  
039Ch  
039Dh  
039Eh  
039Fh  
Block928  
Block929  
Block930  
Block931  
Block932  
Block933  
Block934  
Block935  
Block936  
Block937  
Block938  
Block939  
Block940  
Block941  
Block942  
Block943  
Block944  
Block945  
Block946  
Block947  
Block948  
Block949  
Block950  
Block951  
Block952  
Block953  
Block954  
Block955  
Block956  
Block957  
Block958  
Block959  
03A0h  
03A1h  
03A2h  
03A3h  
03A4h  
03A5h  
03A6h  
03A7h  
03A8h  
03A9h  
03AAh  
03ABh  
03ACh  
03ADh  
03AEh  
03AFh  
03B0h  
03B1h  
03B2h  
03B3h  
03B4h  
03B5h  
03B6h  
03B7h  
03B8h  
03B9h  
03BAh  
03BBh  
03BCh  
03BDh  
03BEh  
03BFh  
SLC:  
0000h~00FCh,  
SLC:  
256KB,  
SLC:  
0000h~00FCh,  
SLC:  
256KB,  
MLC:  
0000h~01FCh  
MLC:  
512KB  
MLC:  
0000h~01FCh  
MLC:  
512KB  
- 28 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
Block Address  
[F100h]  
Page Address  
[F107h]  
Block Address  
[F100h]  
Page Address  
Size  
Block  
Size  
Block  
[F107h]  
Block960  
Block961  
Block962  
Block963  
Block964  
Block965  
Block966  
Block967  
Block968  
Block969  
Block970  
Block971  
Block972  
Block973  
Block974  
Block975  
Block976  
Block977  
Block978  
Block979  
Block980  
Block981  
Block982  
Block983  
Block984  
Block985  
Block986  
Block987  
Block988  
Block989  
Block990  
Block991  
03C0h  
03C1h  
03C2h  
03C3h  
03C4h  
03C5h  
03C6h  
03C7h  
03C8h  
03C9h  
03CAh  
03CBh  
03CCh  
03CDh  
03CEh  
03CFh  
03D0h  
03D1h  
03D2h  
03D3h  
03D4h  
03D5h  
03D6h  
03D7h  
03D8h  
03D9h  
03DAh  
03DBh  
03DCh  
03DDh  
03DEh  
03DFh  
Block992  
Block993  
03E0h  
03E1h  
03E2h  
03E3h  
03E4h  
03E5h  
03E6h  
03E7h  
03E8h  
03E9h  
03EAh  
03EBh  
03ECh  
03EDh  
03EEh  
03EFh  
03F0h  
03F1h  
03F2h  
03F3h  
03F4h  
03F5h  
03F6h  
03F7h  
03F8h  
03F9h  
03FAh  
03FBh  
03FCh  
03FDh  
03FEh  
03FFh  
Block994  
Block995  
Block996  
Block997  
Block998  
Block999  
Block1000  
Block1001  
Block1002  
Block1003  
Block1004  
Block1005  
Block1006  
Block1007  
Block1008  
Block1009  
Block1010  
Block1011  
Block1012  
Block1013  
Block1014  
Block1015  
Block1016  
Block1017  
Block1018  
Block1019  
Block1020  
Block1021  
Block1022  
Block1023  
SLC:  
0000h~00FCh,  
SLC:  
256KB,  
SLC:  
0000h~00FCh,  
SLC:  
256KB,  
MLC:  
0000h~01FCh  
MLC:  
512KB  
MLC:  
0000h~01FCh  
MLC:  
512KB  
- 29 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
2.7.2 Internal Memory Spare Area Assignment  
The figure below shows the assignment of the spare area in the Internal Memory NAND Array.  
Main  
area  
Main  
area  
Main  
area  
Main  
area  
Main  
area  
Main  
area  
Main  
area  
Main  
area  
SpareSpareSpareSpareSpareSpareSpareSpare  
area area area area area area area area  
8W 8W 8W 8W 8W 8W 8W 8W  
256W 256W 256W 256W 256W 256W 256W 256W  
Note1 Note1 Note2 Note2 Note2 Note2 Note3 Note3  
Note3 Note3 Note3  
Note3 Note3 Note3 Note3 Note3  
LSB  
MSB  
LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB  
1st W  
2nd  
W
3rd W  
4th W  
5th W  
6th W  
7th W  
8th W  
Spare Area Assignment in the Internal Memory NAND Array Information  
Word  
Byte  
LSB  
MSB  
LSB  
MSB  
LSB  
MSB  
LSB  
MSB  
LSB  
MSB  
LSB  
MSB  
LSB  
MSB  
LSB  
MSB  
Note  
Description  
1
1
Invalid Block information in 1st and 2nd page of an invalid block  
Managed by internal ECC logic for Logical Sector Number area  
2
3
4
5
6
7
8
2
4bit ECC parity values  
3
- 30 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
2.7.3 External Memory (BufferRAM) Address Map  
The following table shows the External Memory address map in Word and Byte Order.  
Note that the data output is unknown while host reads a register bit of reserved area and dual buffering is not applicable.  
Address  
(word order)  
Address  
(byte order)  
Size  
(total 128KB)  
Division  
Usage  
Description  
Main area  
(64KB)  
0000h~00FFh  
0100h~01FFh  
0200h~02FFh  
0300h~03FFh  
0400h~04FFh  
0500h~05FFh  
0600h~06FFh  
0700h~07FFh  
0800h~08FFh  
0900h~09FFh  
0A00h~7FFFh  
8000h~8007h  
8008h~800Fh  
8010h~8017h  
8018h~801Fh  
8020h~8027h  
8028h~802Fh  
8030h~8037h  
8038h~803Fh  
8040h~8047h  
8048h~804Fh  
8050h~8FFFh  
00000h~001FEh  
00200h~003FEh  
00400h~005FEh  
00600h~007FEh  
00800h~009FEh  
00A00h~00BFEh  
00C00h~00DFEh  
00E00h~00FFEh  
01000h~011FEh  
01200h~013FEh  
01400h~0FFFEh  
10000h~1000Eh  
10010h~1001Eh  
10020h~1002Eh  
10030h~1003Eh  
10040h~1004Eh  
10050h~1005Eh  
10060h~1006Eh  
10070h~1007Eh  
10080h~1008Eh  
10090h~1009Eh  
100A0h~11FFEh  
512B  
BootM 0  
BootM 1  
BootRAM, Main, block0/page0/sector0  
BootRAM, Main, block0/page0/sector1  
DataRAM, Main, nth page/sector0  
DataRAM, Main, nth page/sector1  
DataRAM, Main, nth page/sector2  
DataRAM, Main, nth page/sector3  
DataRAM, Main, nth page/sector4  
DataRAM, Main, nth page/sector5  
DataRAM, Main, nth page/sector6  
DataRAM, Main, nth page/sector7  
Reserved  
1KB  
4KB  
R
512B  
512B  
512B  
512B  
512B  
512B  
512B  
512B  
512B  
59K  
DataM 0_0  
DataM 0_1  
DataM 0_2  
DataM 0_3  
DataM 1_0  
DataM 1_1  
DataM 1_2  
DataM 1_3  
Reserved  
BootS 0  
R/W  
59K  
32B  
-
Spare area  
(8KB)  
16B  
BootRAM, Spare, block0/page0/sector0  
BootRAM, Spare, block0/page0/sector1  
DataRAM, Spare, nth page/sector0  
DataRAM, Spare, nth page/sector1  
DataRAM, Spare, nth page/sector2  
DataRAM, Spare, nth page/sector3  
DataRAM, Spare, nth page/sector4  
DataRAM, Spare, nth page/sector5  
DataRAM, Spare, nth page/sector6  
DataRAM, Spare, nth page/sector7  
Reserved  
R
16B  
BootS 1  
16B  
DataS 0_0  
DataS 0_1  
DataS 0_2  
DataS 0_3  
DataS 1_0  
DataS 1_1  
DataS 1_2  
DataS 1_3  
Reserved  
16B  
16B  
16B  
128B  
R/W  
16B  
16B  
16B  
16B  
8032B  
8032B  
24KB  
-
-
Reserved  
(24KB)  
9000h~BFFFh  
C000h~CFFFh  
12000h~17FFEh  
18000h~19FFEh  
24KB  
8KB  
Reserved  
Reserved  
Reserved  
Registers  
Reserved  
Reserved  
Reserved  
Registers  
Reserved  
(8KB)  
8KB  
16KB  
8KB  
-
-
Reserved  
(16KB)  
D000h~EFFFh 1A000h~1DFFEh  
F000h~FFFFh 1E000h~1FFFEh  
16KB  
8KB  
Registers  
(8KB)  
R or  
R/W  
- 31 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
2.7.4 External Memory Map Detail Information  
The tables below show Word Order Address Map information for the BootRAM and DataRAM main and spare areas.  
BootRAM(Main area)  
-0000h~01FFh: 2(sector) x 512byte(NAND main area) = 1KB  
0000h~00FFh(512B)  
BootM 0  
0100h~01FFh(512B)  
BootM 1  
(sector 0 of page 0/block 0)  
(sector 1 of page 0/block 0)  
DataRAM(Main area)  
-0200h~09FFh: 8(sector) x 512byte(NAND main area) = 4KB  
0200h~02FFh(512B)  
DataM 0_0  
0300h~03FFh(512B)  
DataM 0_1  
0400h~04FFh(512B)  
0500h~05FFh(512B)  
DataM 0_3  
DataM 0_2  
(sector 0 of nth page)  
(sector 1 of nth page)  
(sector 2 of nth page)  
(sector 3 of nth page)  
0600h~06FFh(512B)  
DataM 1_0  
0700h~07FFh(512B)  
DataM 1_1  
0800h~08FFh(512B)  
DataM 1_2  
0900h~09FFh(512B)  
DataM 1_3  
(sector 4 of nth page)  
(sector 5 of nth page)  
(sector 6 of nth page)  
(sector 7 of nth page)  
BootRAM(Spare area)  
-8000h~800Fh: 2(sector) x 16byte(NAND spare area) = 32B  
8000h~8007h(16B)  
BootS 0  
8008h~800Fh(16B)  
BootS 1  
(sector 0 of page 0/block 0)  
(sector 1 of page 0/block 0)  
DataRAM(Spare area)  
-8010h~804Fh: 8(sector) x 16byte(NAND spare area) = 128B  
8010h~8017h(16B)  
DataS 0_0  
8018h~801Fh(16B)  
DataS 0_1  
8020h~8027h(16B)  
8028h~802Fh(16B)  
DataS 0_3  
DataS 0_2  
(sector 0 of nth page)  
(sector 1 of nth page)  
(sector 2 of nth page)  
(sector 3 of nth page)  
8030h~8037h(16B)  
DataS 1_0  
8038h~803Fh(16B)  
DataS 1_1  
8040h~8047h(16B)  
DataS 1_2  
8048h~804Fh(16B)  
DataS 1_3  
(sector 4 of nth page)  
(sector 5 of nth page)  
(sector 6 of nth page)  
(sector 7 of nth page)  
*NAND Flash array consists of 4KB page size and 256KB(SLC)/512KB(MLC) block size.  
- 32 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
2.7.5 External Memory Spare Area Assignment  
Equivalent to 1word of NAND Flash  
Word  
Address  
Byte  
Address  
Buf.  
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
BootS 0  
8000h  
8001h  
8002h  
8003h  
8004h  
8005h  
8006h  
8007h  
8008h  
8009h  
800Ah  
800Bh  
800Ch  
800Dh  
800Eh  
800Fh  
8010h  
8011h  
8012h  
8013h  
8014h  
8015h  
8016h  
8017h  
8018h  
8019h  
801Ah  
801Bh  
801Ch  
801Dh  
801Eh  
801Fh  
10000h  
10002h  
10004h  
10006h  
10008h  
1000Ah  
1000Ch  
1000Eh  
10010h  
10012h  
10014h  
10016h  
10018h  
1001Ah  
1001Ch  
1001Eh  
10020h  
10022h  
10024h  
10026h  
10028h  
1002Ah  
1002Ch  
1002Eh  
10030h  
10032h  
10034h  
10036h  
10038h  
1003Ah  
1003Ch  
1003Eh  
BI(Bad block Information )  
Managed by internal ECC logic  
4bit ECC parity values  
BootS 1  
BI(Bad block Information )  
Managed by internal ECC logic  
4bit ECC parity values  
DataS  
0_0  
BI(Bad block Information )  
Managed by internal ECC logic  
4bit ECC parity values  
DataS  
0_1  
BI(Bad block Information )  
Managed by internal ECC logic  
4bit ECC parity values  
- 33 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
Word  
Address Address  
Byte  
Buf.  
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
DataS 0_2  
8020h  
8021h  
8022h  
8023h  
8024h  
8025h  
8026h  
8027h  
8028h  
8029h  
802Ah  
802Bh  
802Ch  
802Dh  
802Eh  
802Fh  
8030h  
8031h  
8032h  
8033h  
8034h  
8035h  
8036h  
8037h  
8038h  
8039h  
803Ah  
803Bh  
803Ch  
803Dh  
803Eh  
803Fh  
8040h  
8041h  
8042h  
8043h  
8044h  
8045h  
8046h  
8047h  
10040h  
10042h  
10044h  
10046h  
10048h  
1004Ah  
1004Ch  
1004Eh  
10050h  
10052h  
10054h  
10056h  
10058h  
1005Ah  
1005Ch  
1005Eh  
10060h  
10062h  
10064h  
10066h  
10068h  
1006Ah  
1006Ch  
1006Eh  
10070h  
10072h  
10074h  
10076h  
10078h  
1007Ah  
1007Ch  
1007Eh  
10080h  
10082h  
10084h  
10086h  
10088h  
1008Ah  
1008Ch  
1008Eh  
BI(Bad block Information )  
Managed by internal ECC logic  
4bit ECC parity values  
DataS 0_3  
DataS 1_0  
DataS 1_1  
DataS 1_2  
BI(Bad block Information )  
Managed by internal ECC logic  
4bit ECC parity values  
BI(Bad block Information )  
Managed by internal ECC logic  
4bit ECC parity values  
BI(Bad block Information )  
Managed by internal ECC logic  
4bit ECC parity values  
BI(Bad block Information )  
Managed by internal ECC logic  
4bit ECC parity values  
- 34 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
Equivalent to 1word of NAND Flash  
Word  
Address Address  
Byte  
Buf.  
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
DataS 1_3  
8048h  
8049h  
804Ah  
804Bh  
804Ch  
804Dh  
804Eh  
804Fh  
10090h  
10092h  
10094h  
10096h  
10098h  
1009Ah  
1009Ch  
1009Eh  
BI(Bad block Information )  
Managed by internal ECC logic  
4bit ECC parity values  
NOTE :  
In case of ‘with ECC’ mode, Flex-MuxOneNAND automatically generates ECC code for both main and spare data of memory during program operation, but does  
not update ECC code to spare bufferRAM during load operation.  
- 35 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
2.8 Registers  
Section 2.8 of this specification provides information about the Flex-MuxOneNAND4G registers.  
2.8.1 Register Address Map  
This map describes the register addresses, register name, register description, and host accessibility.  
Address  
(word order)  
Address  
(byte order)  
Host  
Access  
Name  
Description  
Manufacturer identification  
F000h  
F001h  
F002h  
F003h  
F004h  
1E000h  
1E002h  
1E004h  
1E006h  
1E008h  
Manufacturer ID  
Device ID  
R
R
R
R
R
Device identification  
N/A  
Version ID  
Data Buffer size  
Boot Buffer size  
Data buffer size  
Boot buffer size  
Amount of  
buffers  
F005h  
1E00Ah  
R
Amount of data/boot buffers  
F006h  
1E00Ch  
Technology  
Reserved  
R
-
Info about technology  
Reserved for user  
F007h~F0FFh  
1E00Eh~1E1FEh  
Chip address for selection of NAND  
Core in DDP & Block address  
F100h  
1E200h  
Start address 1  
R/W  
F101h  
F102h~F106h  
F107h  
1E202h  
1E204h~1E20Ch  
1E20Eh  
Start address 2  
Reserved  
R/W  
Chip address for selection of BufferRAM in DDP  
Reserved for user  
-
R/W  
-
Start address 8  
Reserved  
NAND Flash Page & Sector Address  
Reserved for user  
F108h~F1FFh  
1E210h~1E3FEh  
Sector Number for the page data transfer from the memory  
and the BufferRAM  
F200h  
1E400h  
Sector Count  
R/W  
F201h~F21Fh  
F220h  
1E402h~1E43Eh  
1E440h  
Reserved  
Command  
-
Reserved for vendor specific purposes  
R/W  
Host control and memory operation commands  
System  
Configuration 1  
F221h  
1E442h  
R, R/W memory and Host Interface Configuration  
F222h~F22Fh  
F230h~F23Fh  
F240h  
1E444h~1E45Eh  
1E460h~1E47Eh  
1E480h  
Reserved  
Reserved  
-
Reserved for user  
-
R
Reserved for vendor specific purposes  
Controller Status and result of memory operation  
Memory Command Completion Interrupt Status  
Reserved for user  
Controller Status  
Interrupt  
F241h  
1E482h  
R/W  
-
F242h~F24Bh  
1E484h~1E496h  
Reserved  
Start  
Block Address  
F24Ch  
F24Dh  
1E498h  
1E49Ah  
R/W  
Start memory block address in Write Protection mode  
Reserved for user  
Reserved  
-
R
-
Write Protection  
Status  
Current memory Write Protection status  
(unlocked/locked/tight-locked)  
F24Eh  
1E49Ch  
F24Fh~FEFFh  
FF00h  
1E49Eh~1FDFEh  
1FE00h  
Reserved  
Reserved for user  
ECC Status  
Register 1  
R
ECC status of sector0 and sector 1  
ECC Status  
Register 2  
FF01h  
FF02h  
1FE02h  
1FE04h  
R
R
ECC status of sector2 and sector 3  
ECC status of sector4 and sector 5  
ECC Status  
Register 3  
ECC Status  
Register 4  
FF03h  
1FE06h  
R
-
ECC status of sector6 and sector 7  
FF04h~FFFFh  
1FE08h~1FFFEh  
Reserved  
Reserved for vendor specific purposes  
- 36 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
2.8.2 Manufacturer ID Register F000h (R)  
This Read register describes the manufacturer's identification.  
Samsung Electronics Company manufacturer's ID is 00ECh.  
F000h, default = 00ECh  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
ManufID  
2.8.3 Device ID Register F001h (R)  
This Read register describes the device.  
F001h, see table for default.  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
DeviceID  
Device Identification  
Device Identification  
Description  
DeviceID [1:0] Vcc  
DeviceID [2] Muxed/Demuxed  
DeviceID [3] Single/DDP  
00 = 1.8V, 01 = 3.3V, 10/11 = reserved  
0 = Muxed, 1 = Demuxed  
0 = Single, 1 = DDP/QDP  
0000 = 128Mb, 0001 = 256Mb, 0010 = 512Mb,  
0011 = 1Gb, 0100 = 2Gb, 0101=4Gb, 0110=8Gb, 0111=16Gb  
DeviceID [7:4] Density  
DeviceID [9:8] Separation  
10=Flex[SLC&MLC], 01=MLC, 00=SLC, 11=reserved  
Device ID Default  
Device  
DeviceID[15:0]  
0250h  
KFM4GH6Q4M  
KFN8GH6Q4M  
KFKAGH6Q4M  
0268h  
0268h1)  
NOTE :  
1) The base density of all the three device is 4Gb, DDP and QDP use 2 and 4 multiplexed chips respectively, hence DDP and QDP device ID is same.  
- 37 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
2.8.4 Version ID Register F002h  
This register is reserved for future use.  
2.8.5 Data Buffer Size Register F003h (R)  
This Read register describes the size of the Data Buffer.  
F003h, default = 0800h  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
DataBufSize  
- 38 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
2.8.6 Boot Buffer Size Register F004h (R)  
This Read register describes the size of the Boot Buffer.  
F004h, default = 0200h  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
BootBufSize  
Register Information  
Description  
Total boot buffer size in Words equal to 1 buffer of 512 Words  
(1 x 512 = 29) in the memory interface  
BootBufSize  
2.8.7 Amount of Buffers Register F005h (R)  
This Read register describes the number of each Buffer.  
F005h, default = 0201h  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
DataBufAmount  
BootBufAmount  
Number of Buffers Information  
Register Information  
DataBufAmount  
Description  
The number of data buffers = 2 (2N, N=1)  
The number of boot buffers = 1 (2N, N=0)  
BootBufAmount  
2.8.8 Technology Register F006h (R)  
This Read register describes the internal NAND array technology.  
F006h, default = 0001h  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
Tech  
Technology Information  
Technology  
Register Setting  
0000h  
NAND SLC  
NAND MLC  
0001h  
Reserved  
0002h ~ FFFFh  
NOTE :  
Flex-OneNAND has underlying MLC technology.  
- 39 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
2.8.9 Start Address1 Register F100h (R/W)  
This Read/Write register describes the NAND Flash block address which will be loaded, programmed, or erased.  
F100h, default = 0000h  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
DFS  
Reserved(00000)  
FBA  
Device  
Number of Block  
FBA  
4Gb  
1024  
2048  
FBA[9:0]  
8Gb DDP  
DFS[15] & FBA[9:0]  
NOTE :  
For QDP, See Section 7.4  
Start Address1 Information  
Register Information  
Description  
NAND Flash Block Address  
Flash Core of DDP (Device Flash Core Select)  
FBA  
DFS  
2.8.10 Start Address2 Register F101h (R/W)  
This Read/Write register describes the method to select the BufferRAM of DDP (Device BufferRAM Select)  
F101h, default = 0000h  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
DBS  
Reserved(000000000000000)  
Start Address2 Information  
Register Information  
Description  
BufferRAM and Register of DDP (Device BufferRAM Select)  
DBS  
>DBS should be set to 1 when accessing the BufferRAM of the second chip(MSB chip) in a DDP.  
>Since DDP chip has 2 BufferRAMs multiplexed, the BufferRAM which corresponds to the Flash core that is intended to be  
accessed must be selected using DBS.  
>Data in BufferRAM of one chip is not accessible to the Flash Core of the other chip in a DDP See Section 7.4.  
2.8.11~15 Start Address3~7 Register F102h~F106h  
This Register is reserved for future use.  
- 40 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
2.8.16 Start Address8 Register F107h (R/W)  
This Read/Write register describes the NAND Flash start page address in a block for a page load, program operation and the NAND Flash  
start sector address in a page for a load, or program operation.  
F107h, default = 0000h  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
Reserved (0000000)  
FPA  
FSA  
Start Address8 Information  
Item  
Description  
Default Value  
Range  
0000000 ~ 1111111,  
7 bits for 128 pages1)  
FPA  
NAND Flash Page Address  
NAND Flash Sector Address  
0000000  
00 (sector0), 01 (sector1),  
10 (Sector2) , 11 (sector3)  
FSA  
00  
NOTE :  
1) Only 6bits must be used for 64pages in SLC area. (SLC:64pages, MLC:128pages)  
2) Sectors 4-7 in a page are not directly addessable using FSA. However, they can be accessed using BSA and BSC (See Below).FSA must be 00  
in program operation.  
2.8.17 Start Buffer Register F200h (R/W)  
This Buffer Sector Count(BSC) specifies the number of sectors to be loaded.  
F200h, default = 0000h  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
BSA1)  
Reserved(0000)  
Reserved(00000)  
BSC  
The BufferRAM Sector Address (BSA) is the sector 0~3 address in the internal BootRAM and DataRAM where data is placed.  
NOTE :  
1) In case of ‘Program’ and ‘Load’, Internally BSA fix first sector of DataRAM0(BSA=1000).  
Item  
Description  
BSC Value  
000 (Default)  
001  
Number of Sectors  
8 sectors  
1 sectors  
2 sectors  
3 sectors  
4 sectors  
5 sectors  
6 sectors  
7 sectors  
1 sectors  
2 sectors  
3 sectors  
1 sectors  
2 sectors  
010  
011  
BSC  
Buffer Sector Count  
(CASE1 : FSA=00)  
100  
101  
110  
111  
001  
BSC  
Buffer Sector Count  
010  
(CASE2 : FSA=01)  
011  
001  
BSC  
Buffer Sector Count  
Buffer Sector Count  
(CASE3 : FSA=10)  
010  
BSC  
001  
1 sectors  
(CASE4 : FSA=11)  
NOTE :  
1) BSC is used only on load operation.  
2) Operation not guaranteed for cases not defined in above table(CASE1, CASE2, CASE3,CASE4).  
- 41 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
Sector allocation according to BSC(CASE1 : FSA=00)  
BSC = 000  
BSC = 001  
Sector0  
Sector0  
Sector0  
Sector0  
Sector0  
Sector0  
Sector0  
Sector0  
Sector1  
Sector2  
Sector6  
Sector3  
Sector4  
Sector5  
Sector7  
Sector1  
Sector1  
Sector1  
Sector1  
Sector1  
Sector1  
BSC = 010  
BSC = 011  
Sector2  
Sector2  
Sector2  
Sector2  
Sector2  
Sector3  
Sector3  
Sector3  
Sector3  
BSC = 100  
BSC = 101  
BSC = 110  
BSC =111  
Sector4  
Sector4  
Sector4  
Sector5  
Sector5  
Sector6  
Sector allocation according to BSC(CASE2 : FSA=01)  
BSC = 001  
Sector1  
Sector1  
Sector1  
BSC = 010  
BSC = 011  
Sector2  
Sector2  
Sector3  
Sector allocation according to BSC(CASE3 : FSA=10)  
BSC = 001  
BSC = 010  
Sector2  
Sector2  
Sector3  
Sector allocation according to BSC(CASE4 : FSA=11)  
BSC = 001  
Sector3  
* The first sector from Flash(The first sector is determined by FSA. In case of FSA=01[CASE2], the first sector is Sector1.)  
is transferred to the 1st sector(sector0) of DataRAM0, and the other sectors are transferred sequentially.  
- 42 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
2.8.18 Command Register F220h (R/W)  
Command can be issued by two following methods, and user may select one way or the other to issue appropriate command;  
1. Write command into Command Register when INT is at ready state. INT will automatically turn to busy state as command is issued. Once  
the desired operation is completed, INT will go back ready state.  
2. Write 0000h to INT bit of Interrupt Status Register, and then write command into Command Register. Once the desired operation is com-  
pleted, INT will go back to ready state.  
(00F0h and 00F3h may be accepted during busy state of some operations. Refer to the right most column of the command register table  
below.)  
F220h, default = 0000h  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
Command  
Acceptable  
command  
CMD  
Operation  
during busy  
0000h  
0003h  
Load a page unit into buffer  
00F0h, 00F3h  
00F0h, 00F3h  
Superload a page unit from buffer  
LSB page recovery Read 1)  
PI update 2)  
0005h  
0080h  
00F0h, 00F3h  
00F0h, 00F3h  
Program a page unit from buffer &  
Finish Program operation at Cache Program operation  
Cache Program operation  
Unlock NAND array a block  
Lock NAND array a block  
Lock-tight NAND array a block  
All Block Unlock  
007Fh  
0023h  
002Ah  
002Ch  
0027h  
0094h  
00B0h  
0030h  
00F0h  
00F3h  
0065h  
0066h  
00F0h, 00F3h  
00F0h, 00F3h  
00F0h, 00F3h  
00F0h, 00F3h  
00F0h, 00F3h  
00F0h, 00F3h  
00F0h, 00F3h  
00F0h, 00F3h  
-
Block Erase  
Erase Suspend  
Erase Resume  
Reset NAND Flash Core  
Reset Flex-MuxOneNAND 3)  
OTP Access  
-
00F0h, 00F3h  
00F0h, 00F3h  
Access to Partition Information(PI) Block  
NOTE :  
1) LSB page recovery Read command can always be issued but not in the PI Block access mode.  
2) In PI Block Access mode, PI update can be issued.  
3) ‘Reset Flex-MuxOneNAND’(=Hot reset) command makes the registers and NAND Flash core into default state.  
- 43 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
2.8.18.1 Two Methods to Clear Interrupt Register in Command Input  
To clear Interrupt Register in command input, user may select one from either following methods.  
First method is to turn INT to low by manually writing 0000h to INT bit of Interrupt Register. 1)  
Second method is to input command while INT is high, and the device will automatically turn INT to low.1)  
(Second method is equivalent with method used in general NAND Flash)  
User may choose the desirable method to clear Interrupt Register.  
Method 1: Manually set INT=0 before writing command into Command Register: Manual INT Mode  
(1) Clear Interrupt Register (F241h) by writing 0000h into INT bit of Interrupt Register. This operation will make INT pin turn low. 1)  
(2) Write command into Command Register. This will make the device to perform the designated operation.  
(3) INT pin will turn back to high once the operation is completed. 1)  
INT pin1)  
INT bit  
Write command into  
Command Register  
Write 0 into  
INT bit of  
INT will automatically turn to high  
when designated operation is completed.  
Interrupt Register  
NOTE : 1) INT pin polarity is based on ‘IOBE=1 and INT pol=1 (default)’ setting  
Method 2: Write command into Command Register at INT ready state: Auto INT Mode  
(1) Write command into Command Register. This will automatically turn INT from high to low. 1)  
(2) INT pin will turn back to high once the operation is completed. 1)  
INT pin1)  
INT bit  
INT will automatically  
turn to Busy State  
Write command into  
Command Register  
INT will automatically turn back to ready state  
when designated operation in completed.  
NOTE : 1) INT pin polarity is based on ‘IOBE=1 and INT pol=1 (default)’ setting  
- 44 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
2.8.19 System Configuration 1 Register F221h (R, R/W)  
This Read/Write register describes the system configuration.  
F221h, default =40C0h  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R
R/W  
R/W  
R
RDY  
pol  
INT  
pol  
RDY Reserv  
Conf ed  
RM  
BRWL  
BL  
ECC  
IOBE  
HF  
WM  
BWPS  
Read Mode (RM)  
RM  
0
Read Mode  
Asynchronous read(default)  
Synchronous read  
1
Read Mode Information[15]  
Item  
Definition  
Description  
Selects between asynchronous read mode and  
synchronous read mode  
RM  
Read Mode  
Burst Read Write Latency (BRWL)  
BRWL  
Latency Cycles (Read/Write)  
under 40MHz  
(HF=0)  
40MHz~66MHz  
(HF=0)  
over 66MHz  
(HF=1)  
000~010  
011  
Reserved  
3(up to 40MHz. min)  
3(N/A)  
3(N/A)  
4(N/A)  
5(N/A)  
6(min.)  
7
100 (default)  
101  
4
5
6
7
4(min.)  
5
6
7
110  
111  
* Default value of BRWL and HF value is BRWL=4, HF=0.  
For host frequency over 66MHz, BRWL should be 6 or 7 while HF is 1.  
For host frequency range of 40MHz~66MHz, BRWL should be set to 4~7 while HF is 0.  
For host frequency under 40MHz, BRWL should be set to 3~7 while HF is 0.  
Burst Read Write Latency (BRWL) Information[14:12]  
Item  
Definition  
Description  
Burst Read Latency /  
Burst Write Latency  
Specifies the access latency in the burst  
read / write transfer for the initial access  
BRWL  
- 45 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
Burst Length (BL)  
Host must follow burst length set by BL when reading data in synchronous burst read.  
BL  
000  
Burst Length(Main)  
Burst Length(Spare)  
Continuous(Default)1)  
4 words  
001  
010  
8 words  
011  
16 words  
100  
32 words  
N/A  
101~111  
Reserved  
NOTE :  
1) In case of BootRAM : Main=512word, Spare=16word  
In case of DataRAM : Main=1Kword, Spare=32word  
Burst Length (BL) Information[11:9]  
Item  
Definition  
Burst Length  
Description  
Specifies the size of the burst length during a synchronous  
linear burst read and wrap around. And also burst length during a  
synchronous linear burst write  
BL  
Error Correction Code (ECC) Information[8]  
Item  
Definition  
Error Correction Code Operation  
Description  
0 = with correction (default)  
1 = without correction (bypassed)  
ECC  
RDY Polarity (RDYpol) Information[7]  
Item  
Definition  
Description  
1 = high for ready (default)  
0 = low for ready  
RDYpol  
RDY signal polarity  
INT Polarity (INTpol) Information[6]  
INTpol  
INT bit of Interrupt Status Register  
INT Pin output  
0 (busy)  
1 (ready)  
0 (busy)  
1 (ready)  
High  
Low  
Low  
High  
0
1 (default)  
- 46 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
I/O Buffer Enable (IOBE)  
IOBE is the I/O Buffer Enable for the INT and RDY signals. At startup, INT and RDY outputs are High-Z. Bits 6 and 7 become valid after IOBE  
is set to "1". IOBE can be reset by a Cold Reset or by writing "0" to bit 5 of System Configuration1 Register.  
I/O Buffer Enable Information[5]  
Item  
Definition  
Description  
I/O Buffer Enable for INT and  
RDY signals  
0 = disable (default)  
1 = enable  
IOBE  
RDY Configuration (RDY conf)  
RDY Configuration Information[4]  
Item  
Definition  
Description  
0=active with valid data (default)  
1=active one clock before valid data  
RDY conf  
RDY configuration  
HF Enable (HF)  
HF  
0
Description  
HF Disable (default, under 66MHz)  
HF Enable (over 66MHz)  
1
HF Information[2]  
Item  
Definition  
Description  
Selects between HF Disable and  
HF Enable  
HF  
High Frequency  
- 47 -  
   
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
Write Mode (WM)  
WM  
Write Mode  
0
1
Asynchronous Write(default)  
Synchronous Write  
Write Mode Information[1]  
Item  
Definition  
Description  
Selects between asynchronous Write Mode and  
synchronous Write Mode  
WM  
Write Mode  
MRS(Mode Register Setting) Description  
RM  
0
WM  
0
Mode Description  
Asynch Read & Asynch Write (Default)  
1
0
Sync Read & Asynch Write  
Sync Read & Synch Write  
1
1
Reserved1)  
Other Cases  
NOTE :  
1) Operation not guaranteed for cases not defined in above table.  
Boot Buffer Write Protect Status(BWPS)  
Boot Buffer Write Protect Status Information[0]  
Item  
Definition  
Description  
0=locked(fixed)  
BWPS  
Boot Buffer Write Protect Status  
- 48 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
2.8.20 System Configuration 2 Register F222h  
This register is reserved for future use.  
2.8.21 Controller Status Register F240h (R)  
This Read register shows the overall internal status of the Flex-MuxOneNAND and the controller.  
F240h, default = 0000h  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
Reser  
ved(0)  
Reser  
ved(0)  
TO  
(0)  
OTPBL  
OnGo  
Reserved(0000)  
Error  
PIL  
OTPL  
Reserved(00)  
Previous Current  
OnGo  
This bit shows the overall internal status of the Flex-MuxOneNAND device.  
In Cache Program Operation, OnGo bit shows the overall status of Cache Program process.  
OnGo Information[15]  
Item  
Definition  
Description  
0 = ready  
1 = busy  
OnGo  
Internal Device Status  
Error  
This bit shows the overall Error status.  
In case of Cache Program, Error bit will show the accumulative error status of Cache Program operation, so that if an error occurs during  
Cache Program, this bit will stay as Fail status, until the end of Cache Program.  
Error Information[10]  
Error  
Load Program, Cache Program, and Erase Result  
0
1
Pass  
Fail  
PI Lock Status (PIL)  
This bit shows whether the PI block is locked or unlocked. Locking the PI has the effect of a 'Program/Erase protect' to guard against  
accidental re-programming of data stored in the PI block.  
The PI status bit is automatically updated at power-on and PI update operation by PI Update command.  
- 49 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
OTP Lock Status (OTPL)  
This bit shows whether the OTP block is locked or unlocked. Locking the OTP has the effect of a 'write-protect' to guard against  
accidental re-programming of data stored in the OTP block.  
The OTPL status bit is automatically updated at power-on.  
OTP Lock Information[6]  
OTPL  
OTP Locked/Unlocked Status  
OTP Block Unlock Status(Default)  
0
1
OTP Block Lock Status(Disable OTP Program/Erase)  
1st Block OTP Lock Status (OTPBL  
)
This bit shows whether the 1st Block OTP is locked or unlocked.  
Locking the 1st Block OTP has the effect of a 'Program/Erase protect' to guard against accidental re-programming of data stored in the 1st  
block.  
The OTPBL status bit is automatically updated at power-on.  
OTP Lock Information[5]  
OTPBL  
1st Block OTP Locked/Unlocked Status  
1st Block OTP Unlock Status(Default)  
0
1
1st Block OTPLock Status(Disable 1st Block OTP Program/Erase)  
Previous Cache Program status (Previous)  
This bit shows the previous program status of Cache Program. This value is invalid only at the first ‘Read Controller Status Register’ step of  
Cache Program operation. (Refer to 6.12 and 6.13)  
Previous [2]  
Previous  
Status of previous program  
0
1
Pass  
Fail  
Current Cache Program Status (Current)  
This bit shows the current program status only at Final Cache Program.  
Current Information[1]  
Current  
Status of current program  
0
1
Pass  
Fail  
Time Out (TO)  
This bit determines if there is a time out for load, program, and erase operations. It is fixed at 'no time out'.  
TO Information[0]  
Item  
Definition  
Description  
TO  
Time Out  
0 = no time out  
- 50 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
Controller Status Register Output Modes  
Controller Status Register [15:0]  
[15]  
[14] [13] [12] [11]  
Reserved  
[10]  
[9]  
[8]  
[7]  
[6]  
[5]  
[4]  
3)  
Reserved Previous Current  
OTPB  
L
[3]  
[2]  
[1]  
[0]  
Mode  
Reser  
ved  
Reser  
ved  
1)  
2)  
OnGo  
Error  
TO  
PI  
OTP  
L
L
Operation Ongoing  
Operation OK  
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0/1  
0/1  
0/1  
0/1  
0/1  
0/1  
0/1  
0/1  
0/1  
0/1  
0/1  
0/1  
0/1  
0/1  
0/1  
0/1  
0/1  
0/1  
0/1  
0/1  
0/1  
0
0
0
0
0
0
0
0
0
0
0
Operation Fail  
0
0
Program fail on Cache Program  
Previous program fail during Cache Program  
Program fail after Finish Cache Program  
Reset during Program/Erase/Load  
0
1
1
(Note 4)  
0
0
(Note 4)  
0
0000  
0
0
00  
Program/Erase to the locked block,  
Load to the BootRAM  
0
1
0/1  
0/1  
0/1  
0
0
0
OTP Program Fail(Lock)  
OTP Program Fail  
0
0
1
1
0/1  
0/1  
1
0
1
0
0
0
0
0
0
0
NOTE :  
1) "1" for PI Block Lock, "0" for PI Block Unlock.  
L
L
2) "1" for 1st Block OTP Lock, "0" for 1st Block OTP Unlock.  
3) "1" for OTP Block Lock, "0" for OTP Block Unlock.  
4) After Finish Cache Program operation, pass/fail status of Current Cache Program and Previous Cache Program will be updated.  
2.8.22 Interrupt Status Register F241h (R/W)  
This Read/Write register shows status of the Flex-MuxOneNAND interrupts.  
F241h, defaults = 8080h after Cold Reset; 8010h after Warm/Hot Reset  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
INT  
Reserved(0000000)  
RI  
WI  
EI  
RSTI  
Reserved(0000)  
Interrupt (INT)  
This is the master interrupt bit. The INT bit is wired directly to the INT pin on the chip. Upon writing '0' to the INT bit, the INT pin goes low if  
INTpol is high and goes high if INTpol is low.  
INT Interrupt [15]  
Default State  
Cold  
Valid  
State  
Interrupt  
Function  
Status  
Conditions  
Warm/hot  
1
1
0
off  
Commands in the command table in page43 (Refer  
to Chapter 2.8.18) are completed.  
sets itself to ‘1’  
clears to ‘0’  
01  
Pending  
‘0’ is written to this bit,  
Cold/Warm/Hot reset is being performed, or  
command is written to Command Register in INT  
auto mode  
off  
10  
- 51 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
Read Interrupt (RI)  
This is the Read interrupt bit.  
RI Interrupt [7]  
Default State  
Cold  
Valid  
State  
Interrupt  
Function  
Status  
Conditions  
Warm/hot  
1
0
0
off  
At the completion of a Load, Superload or LSB Page  
Recovery Read Operation.  
sets itself to ‘1’  
clears to ‘0’  
Pending  
01  
(0000h, 0003h or 0005h)  
‘0’ is written to this bit,  
Cold/Warm/Hot reset is being performed, or  
command is written to Command Register in INT auto  
mode  
off  
10  
Write Interrupt (WI)  
This is the Write interrupt bit.  
WI Interrupt [6]  
Status  
Default State  
Valid  
State  
Interrupt  
Function  
Conditions  
Cold  
Warm/hot  
0
0
0
off  
At the completion of an Program Operation  
(0080h and 007Fh)  
sets itself to ‘1’  
Pending  
01  
‘0’ is written to this bit,  
Cold/Warm/Hot reset is being performed, or com-  
mand is written to Command Register in INT auto  
mode  
clears to ‘0’  
off  
10  
Erase Interrupt (EI)  
This is the Erase interrupt bit.  
EI Interrupt [5]  
Status  
Default State  
Valid  
State  
Interrupt  
Function  
Conditions  
Cold  
Warm/hot  
0
0
0
off  
At the completion of an Erase Operation  
(0094h and 0030h)  
sets itself to ‘1’  
01  
Pending  
‘0’ is written to this bit,  
Cold/Warm/Hot reset is being performed, or com-  
mand is written to Command Register in INT auto  
mode  
clears to ‘0’  
off  
10  
- 52 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
Reset Interrupt (RSTI)  
This is the Reset interrupt bit.  
RSTI Interrupt [4]  
Default State  
Valid  
State  
Interrupt  
Function  
Status  
Conditions  
Cold  
Warm/hot  
0
1
0
off  
At the completion of an Reset Operation  
(00B0h, 00F0h, 00F3h or  
sets itself to ‘1’  
clears to ‘0’  
Pending  
01  
warm reset is released)  
‘0’ is written to this bit, or  
command is written to Command Register in INT  
auto mode  
10  
off  
2.8.23 Start Block Address Register F24Ch (R/W)  
This Read/Write register shows the NAND Flash block address in the Write Protection mode. Setting this register precedes a 'Lock Block'  
command, 'Unlock Block' command, or ‘Lock-Tight' Command.  
F24Ch, default = 0000h  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
Reserved(000000)  
SBA  
Device  
Number of Block  
SBA  
4Gb  
1024  
[9:0]  
2.8.24 Start Block Address Register F24Dh (R/W)  
This register is reserved for future use.  
2.8.25 NAND Flash Write Protection Status Register F24Eh (R)  
This Read register shows the Write Protection Status of the NAND Flash memory array.  
To read the write protection status, FBA(DFS and DBS also in case of DDP) has to be set before reading the register.  
F24Eh, default = 0002h  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
Reserved(0000000000000)  
US  
LS  
LTS  
Write Protection Status Information[2:0]  
Item  
Bit  
Definition  
Description  
US  
2
Unlocked Status  
1 = current NAND Flash block is unlocked  
1 = current NAND Flash block is locked  
LS  
1
0
Locked Status  
Or First Block of NAND Flash Array is Locked to be OTP  
1 = current NAND Flash block is locked-tight  
LTS  
Locked-Tight Status  
- 53 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
2.8.26 ECC Status Register 1 FF00h (R)  
This Read register shows the Error Correction Status. The Flex-MuxOneNAND can correct up to 4-bit errors.  
ECC can be performed on the NAND Flash main and spare memory areas. The ECC status register can also show the number of errors in a  
sector as a result of an ECC check in during a load operation. ECC status bits are also updated during a boot loading operation.  
FF00h, default = 0000h  
15  
14  
13  
12  
11  
10  
9
9
9
9
8
8
8
8
7
7
7
7
6
5
5
5
5
4
4
4
4
3
3
3
3
2
1
1
1
1
0
0
0
0
Reserved  
ER1  
Reserved  
ER0  
2.8.27 ECC Status Register 2 FF01h (R)  
FF01h, default = 0000h  
15  
14  
13  
12  
11  
10  
6
2
Reserved  
ER3  
Reserved  
ER2  
2.8.28 ECC Status Register 3 FF02h (R)  
FF02h, default = 0000h  
15  
14  
13  
12  
11  
10  
6
2
Reserved  
ER5  
Reserved  
ER4  
2.8.29 ECC Status Register 4 FF03h (R)  
FF03h, default = 0000h  
15  
14  
13  
12  
11  
10  
6
2
Reserved  
ER7  
Reserved  
ER6  
Error Status  
ER  
ECC Status  
No Error  
00000  
00001  
00010  
00100  
01000  
10000  
1bit error(correctable)  
2bit error(correctable)  
3bit error(correctable)  
4bit error(correctable)  
Uncorrectable  
ECC location Information  
Item  
ER0  
ER1  
ER2  
ER3  
ER4  
ER5  
ER6  
ER7  
Definition  
Error status of 1st selected sector (Main and Spare area)  
Error status of 2nd selected sector (Main and Spare area)  
Error status of 3rd selected sector (Main and Spare area)  
Error status of 4th selected sector (Main and Spare area)  
Error status of 5th selected sector (Main and Spare area)  
Error status of 6th selected sector (Main and Spare area)  
Error status of 7th selected sector (Main and Spare area)  
Error status of 8th selected sector (Main and Spare area)  
- 54 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
3.0 DEVICE OPERATION  
This section of the data sheet discusses the operation of the Flex-MuxOneNAND device. It is followed by AC/DC  
Characteristics and Timing Diagrams which may be consulted for further information.  
The Flex-MuxOneNAND supports a limited command-based interface in addition to a register-based interface for performing operations on  
the device.  
3.1 Command Based Operation  
Flex-OneNAND supports a limited command based interface. The address range of BootRAM ([0000h - 01FFh, 8000h - 800Fh]), called the  
Boot Partition is actually a read only area. This is because it contains bootloader code which must not be overwritten.  
Therefore any attempt of data write to the Boot Partition is interpreted by Flex-OneNAND as a "Command based operation".  
Commands can only be written with a Boot Partition address. Thus, the command-based interface is active only in the boot partition.  
The remaining address range, except for the boot area, (address range [0200h - FFFFh]) can be used as a read/write data buffer.(with a few  
exceptions like ID registers). Writes outside the boot partition are treated as normal writes to the buffers or registers.  
The command consists of one or more cycles depending on the command. After completion of the command the device starts its execution.  
Writing incorrect information including address and data to the boot partition or writing an improper command will terminate the previous com-  
mand sequence and make the device enter the ready status.  
The defined valid command sequences are stated in Command Sequences Table. Command based operations are mainly used when Flex-  
MuxOneNAND is used as Booting device, and all command based operations only supports asynchronous reads and writes. With DDP, com-  
mand based operation except reset is applicable only on chip1.  
Command Sequences  
Command Definition  
Cycles  
1st cycle  
2nd cycle  
BP1)  
00F0h  
BP  
Add  
Data  
Add  
Reset Flex-MuxOneNAND  
1
BP  
Load Data into Buffer2)  
2
2
0000h3)  
XXXXh4)  
Data  
Data  
Add  
00E0h  
BP  
Read Identification Data 5)  
Data  
0090h  
NOTE :  
1) BP(Boot Partition) : BootRAM Area [0000h ~ 01FFh, 8000h ~ 800Fh].  
2) Load Data into Buffer operation is available within a block(128KB(SLC), 256KB(MLC)) (Chip1 only in case of DDP)  
3) Load 4KB unit into DataRAM0, DataRAM1. Current Start address(FPA) is automatically incresed by 4KB unit after the load.  
4) 0000h -> Data is Manufacturer ID (Chip1 only in case of DDP)  
0001h -> Data is Device ID (Chip1 only in case of DDP)  
0002h -> Current Block Write Protection Status (Chip1 only in case of DDP)  
5) WE toggling can terminate ’Read Identification Data’ operation.  
- 55 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
3.1.1 Reset Flex-MuxOneNAND Command  
The Reset command is given by writing 00F0h to the boot partition address. Reset will return all default values into the device.  
3.1.2 Load Data Into Buffer Command  
Load Data into Buffer command is a two-cycle command. Two sequential designated command activates this operation. Sequentially writing  
00E0h and 0000h to the boot partition [0000h~01FFh, 8000h~800Fh] will load one page to DataRAM0 and DataRAM1. This operation refers  
to FBA. FSA must be 00 and BSA must be 1000.  
At the end of this operation, FPA will be automatically increased by 1. So continuous issue of this command will sequentially load data in next  
page to DataRAM0, DataRAM1. This page address increment is restricted within a block.  
The default value of FBA and FPA is 0. Therefore, initial issue of this command after power on will load the first page of memory, which is usu-  
ally boot code.  
3.1.3 Read Identification Data Command  
The Read Identification Data command consists of two cycles. It gives out the devices identification data according to the given address. The  
first cycle is 0090h to the boot partition address and second cycle is read from the addresses specified in Identification Data Description Table.  
Identification Data Description  
Address  
0000h  
Data Out  
Manufacturer ID (00ECh)  
Device ID1)  
0001h  
Current Block Write Protection Status2)  
0002h  
NOTE :  
1) Refer to Device ID Register (Chapter 2.8.3)  
2) To read the write protection status, FBA has to be set before issuing this command.  
- 56 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
3.2 Device Bus Operation  
The device bus operations are shown in the table below.  
Operation  
Standby  
CE  
H
OE  
X
WE  
X
ADQ0~15  
High-Z  
RP  
H
CLK  
X
AVD  
X
Warm Reset  
X
X
X
High-Z  
L
X
X
Add. In /Data  
In  
Asynchronous Write  
Asynchronous Read  
Start Initial Burst Read  
L
L
L
H
L
L
H
H
H
H
H
L
L
Add. In /Data  
Out  
H
Add. In  
Burst Data  
Out  
H
Burst Read  
L
L
H
H
Terminate Burst Read  
Cycle  
H
X
X
X
H
X
High-Z  
High-Z  
H
L
X
X
X
X
Terminate Burst Read  
Cycle via RP  
Terminate Current Burst  
Read Cycle and Start  
New Burst Read Cycle  
L
H
H
Add In  
H
Start Initial Burst Write  
Burst Write  
L
L
H
H
H
X
L
X
X
X
Add In  
Data In  
High-Z  
High-Z  
H
H
H
L
H
X
X
Terminate Burst Write  
Cycle  
H
X
X
X
Terminate Burst Write  
Cycle via RP  
Terminate Current Burst  
Write Cycle and Start  
New Burst Write Cycle  
H
L
Add In  
H
NOTE :  
1) L=VIL (Low), H=VIH (High), X=Don’t Care.  
- 57 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
3.3 Reset Mode Operation  
The Flex-MuxOneNAND has 4 reset modes: Cold/Warm/Hot Reset, and NAND Flash Array Reset. Section 3.3 discusses the operation of  
these reset modes.  
The Register Reset Table shows the which registers are affected by the various types of Reset operations.  
Internal Register Reset Table  
Hot  
Reset  
(00F3h) (BP-F0h)  
00ECh  
N/A  
Hot  
Reset  
NAND Flash  
Core Reset  
(00F0h)  
Cold Reset  
(Default)  
Warm Reset  
(RP)  
Internal Registers  
Manufacturer ID Register (R)  
F000h  
F001h  
F002h  
F003h  
F004h  
F005h  
F006h  
F100h  
F101h  
F107h  
F200h  
F220h  
F221h  
F240h  
F241h  
00ECh  
(Note 3)  
N/A  
00EC  
N/A  
00ECh  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
Device ID Register (R): Flex-MuxOneNAND  
Version ID Register (R)  
N/A  
N/A  
Data Buffer size Register (R)  
0800h  
0200h  
0201h  
0001h  
0000h  
0000h  
0000h  
0000h  
0000h  
40C0h  
0000h  
8080h  
0000h  
0002h  
0000h  
0000h  
0000h  
0000h  
N/A  
N/A  
Boot Buffer size Register (R)  
N/A  
N/A  
Amount of Buffers Register (R)  
N/A  
N/A  
Technology Register (R)  
N/A  
N/A  
Start Address1 Register (R/W): DFS, FBA  
Start Address2 Register (R/W): DBS  
Start Address8 Register (R/W): FPA  
Start Buffer Register (R/W): BSC, BSA  
Command Register (R/W)  
0000h  
0000h  
0000h  
0000h  
0000h  
(Note 1a)  
0000h  
8010h  
0000h  
0002h  
0000h  
0000h  
0000h  
0000h  
0000h  
0000h  
0000h  
0000h  
0000h  
(Note 1a)  
0000h  
8010h  
N/A  
System Configuration 1 Register (R/W)  
Controller Status Register (R) (Note 1b) (Note 4)  
Interrupt Status Register (R/W)  
F24Ch Start Block Address (R/W)  
F24Eh NAND Flash Write Protection Status (R) (Note 5)  
FF00h ECC Status Register 1 (R) (Note 2)  
FF01h ECC Status Register 2 (R) (Note 2)  
FF02h ECC Status Register 3 (R) (Note 2)  
FF03h ECC Status Register 4 (R) (Note 2)  
N/A  
0000h  
0000h  
0000h  
0000h  
NOTE :  
1a) RDYpol, RDYconf, INTpol, IOBE are reset by Cold reset. The other bits are reset by cold/warm/hot reset  
1b) The other bits except OTPL and OTPBL are reset by cold/warm/hot reset.  
2) ECC Status Register 1~4 are reset when any command is issued.  
3) Refer to Device ID Register F001h.  
4) Resetting during IDLE state, this is valid. But resetting during BUSY state, refer to Chapter 2.8.21.  
5) To read NAND Flash Write Protection status, Block Address register must be written before.  
- 58 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
3.3.1 Cold Reset Mode Operation  
See Timing Diagram 6.15  
At system power-up, the voltage detector in the device detects the rising edge of Vcc and releases an internal power-up reset signal. This trig-  
gers boot code loading. Bootcode loading means that the boot loader in the device copies designated sized data (1KB) from the beginning of  
memory into the BootRAM. This sequence is the Cold Reset of Flex-MuxOneNAND.  
The POR(Power On Reset) triggering level is typically 1.5V. Boot code copy operation activates 400us after POR.  
Therefore, the system power should reach 1.7V within 400us from the POR triggering level for bootcode data to be valid.  
It takes approximately 250us to copy 1KB of boot code. Upon completion of loading into the BootRAM, it is available to be read by the host.  
The INT pin is not available until after IOBE = 1 and IOBE bit can be changed by host.  
3.3.2 Warm Reset Mode Operation  
See Timing Diagrams 6.16  
A Warm Reset means that the host resets the device by using the RP pin. When the a RP low is issued, the device logic stops all current oper-  
ations and executes internal reset operation and resets current NAND Flash core operation synchronized with the  
falling edge of RP.  
During an Internal Reset Operation, the device initializes internal registers and makes output signals go to default status.  
The BufferRAM data is kept unchanged after Warm/Hot reset operations.  
The device guarantees the logic reset operation in case RP pulse is longer than tRP min(200ns).  
The device may reset if tRP < tRP min(200ns), but this is not guaranteed.  
Warm reset will abort the current NAND Flash core operation. During a warm reset, the content of memory cells being altered is no longer  
valid as the data will be partially programmed or erased.  
Warm reset has no effect on contents of BootRAM and DataRAM.  
3.3.3 Hot Reset Mode Operation  
See Timing Diagrams 6.17  
A Hot Reset means that the host resets the device by Reset command. The reset command can be either Command based or Register  
Based. Upon receiving the Reset command, the device logic stops all current operation and executes an internal reset operation and resets  
the current NAND Flash core operation.  
During an Internal Reset Operation, the device initializes internal registers and makes output signals go to default status. The BufferRAM data  
is kept unchanged after Warm/Hot reset operations.  
Hot reset has no effect on contents of BootRAM and DataRAM.  
3.3.4 NAND Flash Core Reset Mode Operation  
See Timing Diagrams 6.18  
The Host can reset the NAND Flash Core operation by issuing a NAND Flash Core reset command. NAND Flash core reset will abort the cur-  
rent NAND Flash core operation. During a NAND Flash core reset, the content of memory cells being altered is no longer valid as the data will  
be partially programmed or erased.  
NAND Flash Core Reset has an effect on neither contents of BootRAM and DataRAM nor register values.  
- 59 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
3.4 Write Protection Operation  
The Flex-MuxOneNAND can be write-protected to prevent re-programming or erasure of data.  
The areas of write-protection are the BootRAM, and the NAND Flash Array.  
3.4.1 BootRAM Write Protection Operation  
At system power-up, voltage detector in the device detects the rising edge of Vcc and releases the internal power-up reset signal which trig-  
gers boot code loading. And the designated size data(1KB) is copied from the first page of the first block in the NAND flash array to the  
BootRAM.  
After the bootcode loading is completed, the BootRAM is always locked to protect the boot code from the accidental write.  
3.4.2 NAND Flash Array Write Protection Operation  
The device has both hardware and software write protection of the NAND Flash array.  
Hardware Write Protection Operation  
The hardware write protection operation is implemented by executing a Cold or Warm Reset. On power up, the NAND Flash Array is in its  
default, locked state. The entire NAND Flash array goes to a locked state after a Cold or Warm Reset.  
Software Write Protection Operation  
The software write protection operation is implemented by writing a Lock command (002Ah) or a Lock-tight command (002Ch) to command  
register (F220h).  
Lock (002Ah) and Lock-tight (002Ch) commands write protects the block defined in the Start Block Address Register F24Ch.  
3.4.3 NAND Array Write Protection States  
There are three lock states in the NAND Array: unlocked, locked, and locked-tight. On power up, all blocks in the NAND array go to Locked  
state. The lock status is maintained for each block in the NAND array. Any changes made to lock status of blocks are lost when Cold/warm  
reset occurs.  
Flex-MuxOneNAND supports 4 commands for changing Write Protection states of the blocks: lock/unlock/lock-tight by one block, and All  
Block Unlock at once.  
All Block Unlock command fails if there are lock-tight blocks in flash.  
Write Protection Status  
The current block Write Protection status can be read in NAND Flash Write Protection Status Register(F24Eh). There are three bits - US, LS,  
LTS -, which are not cleared by hot reset and NAND Flash Core Reset. These Write Protection status registers are updated when FBA is set,  
and when Write Protection command is entered.  
The followings summarize locking status.  
By default, [2:0] values are 010. For example:  
-> If host executes unlock block operation, then [2:0] values turn to 100.  
-> If host executes lock-tight block operation, then [2:0] values turn to 001.  
- 60 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
3.4.3.1 Unlocked NAND Array Write Protection State  
An Unlocked block can be programmed or erased. The status of an unlocked block can be changed to locked or locked-tight using the appro-  
priate software command(Locked-tight state can be achieved in 2 steps. First, the block should be locked via the lock command. Then, Lock  
tight command must be issued.).  
Only one block can be released from lock state to unlock state with Unlock command and addresses. The unlocked block can be changed  
with new lock command. Therefore, each block has its own lock/unlock/lock-tight state.  
Unlocked  
Unlock Command Sequence:  
Start block address+Unlock block command (0023h)  
Unlocked  
All Block Unlock Command Sequence:  
Start block address(000h)+All Block Unlock command (0027h)  
NOTE :  
Even though SBA is fixed to 000h, Unlock will be done for all block. All block unlock is not valid if there is a lock-tight block. With DDP, all block unlock command  
must be issued on each chip.  
3.4.3.2 Locked NAND Array Write Protection State  
A Locked block cannot be programmed or erased. All blocks default to a locked state following a Cold or Warm Reset. Unlocked blocks can be  
changed to locked using the Lock block command. The status of a locked block can be changed to unlocked or locked-tight using the appro-  
priate software command.  
Locked  
Lock Command Sequence:  
Start block address+Lock block command (002Ah)  
- 61 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
3.4.3.3 Locked-tight NAND Array Write Protection State  
A block that is in a locked-tight state can only be changed to locked state after a Cold or Warm Reset. Unlock and Lock command sequences  
will not affect its state. This is an added level of write protection security.  
A block must first be set to a locked state before it can be changed to locked-tight using the Lock-tight command. locked-tight blocks will revert  
to a locked state following a Cold or Warm Reset.  
When there are Lock-tight blocks in the flash array, All Block Unlock Command will fail and there will be no change in the lock status of the  
blocks of the Flash array.  
Thus, All Block Unlock command succeeds only when there are no tightly-locked blocks in Flash.  
Locked-tight  
Lock-Tight Command Sequence:  
Start block address+Lock-tight block command (002Ch)  
3.4.4 NAND Flash Array Write Protection State Diagram  
unlock  
RP pin: High  
&
Start block address (000h)  
+All Block Unlock Command  
RP pin: High  
&
Start block address  
Lock block Command  
or  
Lock  
unlock  
Lock  
RP pin: High  
&
Start block address  
+Unlock block Command  
Cold reset or  
Warm reset  
Power On  
Lock  
RP pin: High  
&
Start block address  
Cold reset or  
Warm reset  
+Lock-tight block Command  
Lock  
Lock-tight  
Lock  
*NOTE : If the 1st Block is set to be OTP, Block 0 will always be Lock Status  
- 62 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
Data Protection Operation Flow Diagram  
Start  
Write ‘DFS*’, of Flash  
Add: F100h DQ=DFS*  
Select DataRAM for DDP  
Add: F101h DQ=DBS*  
Write ‘SBA’ of Flash  
Add: F24Ch DQ=SBA  
Write 0 to interrupt register1)  
Add: F241h DQ=0000h  
Write ‘lock/unlock/lock-tight’  
Command  
Add: F220h  
DQ=002Ah/0023h/002Ch  
Wait for INT register  
low to high transition  
Add: F241h DQ[15]=INT  
Read Controller Status  
Register  
* DBS, DFS is for DDP  
Add: F240h  
DQ[10]=Error  
DQ[10]=0?  
YES  
NO  
Lock/Unlock/Lock-Tight  
completed  
Error  
* Samsung strongly recommends to follow the above flow chart  
NOTE :  
1) ‘Write 0 to interrupt register’ step may be ignored when using INT auto mode. Refer to chapter 2.8.18.1  
- 63 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
All Block Unlock Flow Diagram  
Start  
Write ‘DFS*, of Flash  
Add: F100h DQ=DFS*  
Select DataRAM for DDP  
Add: F101h DQ=DBS*  
Write ‘SBA’ of Flash  
Add: F24Ch DQ=SBA(000h)  
Write 0 to interrupt register1)  
Add: F241h DQ=0000h  
Write ‘All Block Unlock’  
Command  
Add: F220h  
DQ=0027h  
Wait for INT register  
low to high transition  
Add: F241h DQ[15]=INT  
Read Controller Status  
Register  
Add: F240h  
DQ[10]=Error  
* DBS, DFS is for DDP  
DQ[10]=0?  
YES  
NO  
All Block Unlock Failed2)  
All Block Unlock  
completed  
*Samsung strongly recommends to follow the above flow chart  
NOTE :  
1) ‘Write 0 to interrupt register’ step may be ignored when using INT auto mode. Refer to chapter 2.8.18.1  
2) All Block Unlock command fails if there are lock-tight blocks in flash.  
- 64 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
3.5 Data Protection During Power Down Operation  
See Timing Diagrams 6.19  
The device is designed to offer protection from any involuntary program/erase during power-transitions.  
RP pin which provides hardware protection is recommended to be kept at VIL before Vcc drops to 1.5V.  
3.6 Load Operation  
See Timing Diagrams 6.9  
The Load operation is initiated by setting up the start address from which the data is to be loaded. The Load command is issued in order to ini-  
tiate the load.  
During a Load operation, the device:  
-Transfers the data from NAND Flash array into the BufferRAM  
-ECC is checked and any detected and corrected error is reported in the status response as well as  
any unrecoverable error.  
Once the BufferRAM has been filled, an interrupt is issued to the host so that the contents of the BufferRAM can be read. The read from the  
BufferRAM can be an asynchronous read mode or synchronous read mode. The status information related to load operation can be checked  
by the host if required.  
Load Operation Flow Chart Diagram  
Start  
Write ‘DFS*, FBA’ of Flash  
Add: F100h DQ=DFS, FBA  
Write ‘Load’ Command  
Add: F220h DQ=0000h  
Host reads data from  
DataRAM  
Select DataRAM for DDP  
Add: F101h DQ=DBS  
Wait for INT register  
low to high transition  
Read completed  
Add: F241h DQ[15]=INT  
Write ‘FPA, FSA’ of Flash  
Add: F107h DQ=FPA, FSA  
Read ECC Status Register1  
Add: FF00h DQ=ER1[12:8], ER0[4:0]  
Write ‘BSA1), BSC’ of DataRAM  
Add: F200h DQ=0800h  
Read ECC Status Register2  
Add: FF01h DQ=ER3[12:8], ER2[4:0]  
Write System Configuration  
Register  
Read ECC Status Register3  
Add: F221h DQ=ECC  
Add: FF02h DQ=ER5[12:8], ER4[4:0]  
Write 0 to interrupt register2)  
Add: F241h DQ=0000h  
Read ECC Status Register4  
Add: FF03h DQ=ER7[12:8], ER6[4:0]  
* DBS, DFS is for DDP  
NOTE :  
1) BSA must be 1000.  
2) ‘Write 0 to interrupt register’ step may be ignored when using INT auto mode. Refer to chapter 2.8.18.1  
- 65 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
3.6.1 Superload Operation  
See Timing Diagrams 6.10  
The Superload operation is used to read multiple pages. During Superload operation, up to 4bit errors are corrected.  
Once the first data is loaded, an interrupt status returns to ready. The data in DataRAM should be read after next Superload command is  
issued. Data is being loaded from NAND to page buffer until whole data in DataRAM is read. The read from the DataRAM can be only syn-  
chronous read mode. The status information related to load operation can be checked by the host if required. When host accesses DataRAM,  
the address of DataRAM must be a multiple of 4.  
Superload operation must be utilized within a same area partitioned as SLC or MLC.  
Superload Operation Flow Chart Diagram  
Read ECC Status Register1  
Start  
Add: FF00h DQ=ER1[12:8], ER0[4:0]  
Write ‘DFS, FBA’ of Flash  
Add: F100h DQ=DFS*, FBA  
Read ECC Status Register2  
Add: FF01h DQ=ER3[12:8], ER2[4:0]  
Select DataRAM for DDP  
Add: F101h DQ=DBS*  
Read ECC Status Register3  
Read ECC Status Register1  
Add: FF02h DQ=ER5[12:8], ER4[4:0]  
Add: FF00h DQ=ER1[12:8], ER0[4:0]  
Write ‘FPA, FSA’ of Flash  
Add: F107h DQ=FPA, FSA1)  
Read ECC Status Register4  
Read ECC Status Register2  
Add: FF03h DQ=ER7[12:8], ER6[4:0]  
Add: FF01h DQ=ER3[12:8], ER2[4:0]  
2)  
3)  
Write ‘BSA , BSC’ of DataRAM  
Write ‘DFS, FBA’ of Flash  
Add: F100h DQ=FBA  
Read ECC Status Register3  
Add: F200h DQ=0800h  
Add: FF02h DQ=ER5[12:8], ER4[4:0]  
Write System Configuration  
Register  
Write ‘FPA, FSA’ of Flash  
Add: F107h DQ=FPA, FSA  
Read ECC Status Register4  
Add: F221h DQ=ECC  
Add: FF03h DQ=ER7[12:8], ER6[4:0]  
Write 0 to INT register or PIN4)  
Add: F241h DQ=0000h  
Write 0 to INT register or PIN4)  
Add: F241h DQ=0000h  
NO  
Finished to load  
final page?  
Write Superload Command  
Add=F220h DQ=0003h  
YES  
Write Load Command  
Add=F220h DQ=0000h5)  
Host reads data from  
DataRAM 0,15)  
Host reads data from  
DataRAM 0,16)  
Wait for INT register or PIN  
low to high transition  
Superload Completed  
Add: F241h DQ[15]=INT  
Wait for INT register or PIN  
high to low transition  
* DBS, DFS is for DDP  
Add: F241h DQ[15]=INT  
NOTE :  
1) FSA must be 00 and BSC must be 000 always for Superload operation.  
2) BSA must be 1000.  
3) In case of Superload operation, the number of sectors to be loaded is 8 sectors.  
4) ‘Write 0 to interrupt register’ step may be ignored when using INT auto mode. Refer to chapter 2.8.18  
5) For the first load, hosts must issue ‘Load(0000h)’ command.  
6) In case of Superload operation, only synchronous read mode is valid.  
Host should read data out until end of DataRAM(804FH).  
After Reading out the last data(Add:804F), Additional clock should not be asserted.  
- 66 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
3.6.2 LSB Page Recovery Read  
MLC NAND Flash cell has paired pages - LSB page and MSB page. LSB page has lower page address and MSB page has higher page  
address in paired pages. If power off occurs during MSB page program, the paired LSB page data can become corrupt. LSB page recovery  
read is a way to read LSB page though page data are corrupted. When uncorrectable error occurrs as a result of LSB page read after power  
up, issue LSB page recovery read. Its command is ‘0005h’. Flow chart below shows LSB page read sequence.  
LSB Page Recovery read flow chart  
Start  
NO  
Write ‘DFS, FBA’ of Flash  
Add: F100h DQ=DFS*, FBA  
DQ[10]=0?  
Write ‘DFS, FBA’ of Flash  
Add: F100h DQ=DFS*, FBA  
YES  
Read ECC Status Register1  
Read ECC Status Register1  
Select DataRAM for DDP  
Add: F101h DQ=DBS*  
Add: FF00h DQ=ER1[12:8],  
ER0[4:0]  
Add: FF00h DQ=ER1[12:8],  
ER0[4:0]  
Select DataRAM for DDP  
Add: F101h DQ=DBS*  
Write ‘FPA, FSA’ of Flash  
Add: F107h DQ=FPA, FSA  
Read ECC Status Register2  
Read ECC Status Register2  
Write ‘FPA, FSA’ of Flash  
Add: F107h DQ=FPA, FSA  
Add: FF01h DQ=ER3[12:8],  
ER2[4:0]  
Add: FF01h DQ=ER3[12:8],  
ER2[4:0]  
,
Write ‘BSA BSC’ of DataRAM  
Add: F200h DQ=0800h  
Read ECC Status Register3  
Read ECC Status Register3  
1)  
Write ‘BSA , BSC’ of DataRAM  
Add: F200h DQ=0800h  
Add: FF02h DQ=ER5[12:8],  
ER4[4:0]  
Add: FF02h DQ=ER5[12:8],  
ER4[4:0]  
Write System Configuration  
Register  
Add: F221h DQ=ECC  
Write System Configuration  
Register  
Read ECC Status Register4  
Read ECC Status Register4  
Add: FF03h DQ=ER7[12:8],  
ER6[4:0]  
Add: FF03h DQ=ER7[12:8],  
ER6[4:0]  
Add: F221h DQ=ECC  
Write 0 to INT register  
Add: F241h DQ=0000h  
Write 0 to INT register2)  
Add: F241h DQ=0000h  
Host reads data from  
DataRAM  
Host reads data from  
DataRAM  
Write ‘LSB Page Recovery Read’  
Command  
Add=F220h DQ=0005h  
Write ‘Load’ Command  
Add=F220h DQ=0000h  
Read Completed  
Read Completed  
Wait for INT register  
low to high transition  
* DBS, DFS is for DDP  
Wait for INT register  
low to high transition  
Add: F241h DQ[15]=INT  
Add: F241h DQ[15]=INT  
Read Controller status register  
Add: F240h DQ[10]=Error  
Read Controller status register  
Add: F240h DQ[10]=Error  
NO  
YES  
Load Error  
DQ[10]=0?  
NOTE :  
1) BSA must be 1000.  
2) ‘Write 0 to interrupt register’ step may be ignored when using INT auto mode. Refer to chapter 2.8.18.1  
- 67 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
3.7 Read Operation  
See Timing Diagrams 6.1,6.2, 6.3 and 6.4.  
The device has two read modes; Asynchronous Read and Synchronous Burst Read.  
The initial state machine automatically sets the device into the Asynchronous Read Mode (RM=0) to prevent the spurious altering of memory  
content upon device power up or after a Hardware reset. No commands are required to retrieve data in Asynchronous Read Mode.  
The Synchronous Read Mode is enabled by setting RM bit of System Configuration1 Register (F221h) to Synchronous Read Mode (RM=1).  
See section 2.8.19 for more information about System Configuration1 Register.  
3.7.1 Asynchronous Read Mode Operation (RM=0, WM=0)  
See Timing Diagrams 6.3 and 6.4  
In an Asynchronous Read Mode, data is output with respect to a logic input, AVD.  
Output data will appear on DQ15-DQ0 when a valid address is asserted on A15-A0 while driving AVD and CE to VIL. WE is held at VIH. The  
function of the AVD signal is to latch the valid address.  
Address access time from AVD low (tAA) is equal to the delay from valid addresses to valid output data.  
The Chip Enable access time (tCE) is equal to the delay from the falling edge of CE to valid data at the outputs.  
The Output Enable access time (tOE) is the delay from the falling edge of OE to valid data at the output.  
3.7.2 Synchronous Read Mode Operation (RM=1, WM=X)  
See Timing Diagrams 6.1and 6.2  
In a Synchronous Read Mode, data is output with respect to a clock input.  
The device is capable of a continuous linear burst operation and a fixed-length linear burst operation of a preset length. Burst address  
sequences for continuous and fixed-length burst operations are shown in the table below.  
Burst Address Sequences  
Burst Address Sequence(Decimal)  
Start  
Addr.  
Continuous Burst  
0-1-2-3-4-5-6...  
1-2-3-4-5-6-7...  
2-3-4-5-6-7-8...  
4-word Burst  
0-1-2-3-0...  
1-2-3-0-1...  
2-3-0-1-2...  
8-word Burst  
16-word Burst  
32-word Burst  
0
1
2
0-1-2-3-4-5-6-7-0...  
1-2-3-4-5-6-7-0-1...  
2-3-4-5-6-7-0-1-2...  
0-1-2-3-4-....-13-14-15-0...  
1-2-3-4-5-....-14-15-0-1...  
2-3-4-5-6-....-15-0-1-2...  
0-1-2-3-4-....-29-30-31-0...  
1-2-3-4-5-....-30-31-0-1...  
2-3-4-5-6-....-31-0-1-2...  
Wrap  
around  
.
.
.
.
.
.
.
.
.
.
.
.
In the burst mode, the initial word will be output asynchronously, regardless of BRWL. While the following words will be determined by BRWL  
value.  
The latency is determined by the host based on the BRWL bit setting in the System Configuration 1 Register. The default BRWL is 4 latency  
cycles. At clock frequencies of 40MHz or lower, latency cycles can be reduced to 3. BRWL can be set up to 7 latency cycles.  
The BRWL registers in System Configuration 1 Register can be read during a burst read mode by using the AVD signal with the address  
F221h.  
- 68 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
3.7.2.1 Continuous Linear Burst Read Operation  
See Timing Diagram 6.2  
First Clock Cycle  
The initial word is output at tIAA after the rising edge of the first CLK cycle. The RDY output indicates the initial word is ready to the system by  
pulsing high. If the device is accessed synchronously while it is set to Asynchronous Read Mode, the first data can still be read out.  
Subsequent Clock Cycles  
Subsequent words are output (Burst Access Time from Valid Clock to Output) tBA after the rising edge of each successive clock cycle, which  
automatically increments the internal address counter.  
Terminating Burst Read  
The device will continue to output sequential burst data until the system asserts CE high, or RP low, wrapping around until it reaches the des-  
ignated address (see section 2.7.3 for address map information). Alternately, a Cold/Warm/Hot Reset, or a WE low pulse will terminate the  
burst read operation.  
Synchronous Read Boundary  
Division  
Add.map(word order)  
0000h~01FFh  
0200h~05FFh  
0600h~09FFh  
0A00h~7FFFh  
8000H~800Fh  
8010h~802Fh  
8030h~804Fh  
8050h~8FFFh  
9000h~EFFFh  
F000h~FFFFh  
BootRAM Main(0.5KW)  
BufferRAM0 Main(1KW)  
BufferRAM1 Main(1KW)  
Reserved Main*  
Not Supported  
Not Supported  
Not Supported  
BootRAM Spare(16W)  
BufferRAM0 Spare(32W)  
BufferRAM1 Spare(32W)  
Reserved Spare*  
Not Supported  
Not Supported  
Reserved Register*  
Register(4KW)  
* Reserved area is not available on Synchronous read  
NOTE :  
Continuous burst read should be done, with in the address range of the selected buffer RAM, dataRAM0 or DataRAM1.  
3.7.2.2 4-, 8-, 16-, 32-Word Linear Burst Read Operation  
See Timing Diagram 6.1  
An alternate Burst Read Mode enables a fixed number of words to be read from consecutive address.  
The device supports a burst read from consecutive addresses of 4-, 8-, 16-, and 32-words with a linear-wrap around. When the last word in  
the burst has been reached, assert CE and OE high to terminate the operation.  
In this mode, the start address for the burst read can be any address of the address map with one exception. The device does not support a  
32-word linear burst read on the spare area of the BufferRAM.  
- 69 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
3.7.2.3 Programmable Burst Read Latency Operation  
See Timing Diagrams 6.1 and 6.2  
Upon power up, the number of initial clock cycles from Valid Address (AVD) to initial data defaults to four clocks.  
The number of clock cycles (n) which are inserted after the clock which is latching the address. The host can read the first data with the  
(n+1)th rising edge.  
The number of total initial access cycles is programmable from three to seven cycles. After the number of programmed burst clock cycles is  
reached, the rising edge of the next clock cycle triggers the next burst data.  
Four Clock Burst Read Latency (BRWL=4 case)  
Rising edge of the clock cycle following last read latency  
triggers next burst data  
CE  
CLK  
-1  
0
1
2
3
4
AVD  
tBA  
Valid  
A/DQ0:  
A/DQ15  
D6  
D7  
D0  
D1  
D2  
D3  
D7  
D0  
Address  
tIAA  
OE  
tRDYS  
Hi-Z  
Hi-Z  
tRDYA  
RDY  
*NOTE :  
BRWL=4, HF=0 is recommended for 40MHz~66MHz. For frequency over 66MHz, BRWL should be 6 or 7 while HF=1.  
Also, for frequency under 40MHz, BRWL can be reduced to 3, and HF=0.  
3.7.3 Handshaking Operation  
The handshaking feature allows the host system to simply monitor the RDY signal from the device to determine when the initial word of burst  
data is ready to be read.  
To set the number of initial cycles for optimal burst mode, the host should use the programmable burst read latency configuration (see section  
2.8.19, "System Configuration1 Register").  
The rising edge of RDY which is derived at one cycle prior of data fetch clock indicates the initial word of valid burst data.  
3.7.4 Output Disable Mode Operation  
When the CE or OE input is at VIH, output from the device is disabled.  
The outputs are placed in the high impedance state.  
- 70 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
3.8 Synchronous Write(RM=1, WM=1)  
See Timing Diagram 6.6, 6.7 and 6.8  
Burst mode operations enable high-speed synchronous read and write operations. Burst operations consist of a multi-clock sequence that  
must be performed in an ordered fashion. After CE goes low, the address to access is latched on the next rising edge of clk that ADV is low.  
During this first clock rising edge, WE indicates whether the operation is going to be a read (WE = high) or write (WE = low). The size of a  
burst can be specified in the BL as either a fixed length or continuous. Fixed-length bursts consist of 4, 8, 16, and 32 words. Continuous burst  
write has the ability to start at a specified address and burst within the designated DataRAM. The latency count stored in the BRWL defines  
the number of clock cycles that elapse before the initial data value is transferred between the processor and Flex-MuxOneNAND device.  
The RDY output will be asserted as soon as a burst is initiated, and will be de-asserted to indicate when data is to be transferred into (or out  
of) the memory. The processor can access other devices without incurring the timing penalty of the initial latency for a new burst by suspend-  
ing burst mode. Bursts are suspended by stopping clk. clk can be stopped high or low. Note that the RDY output will continue to be active, and  
as a result no other devices should directly share the RDY connection to the controller.  
To continue the burst sequence, clk is restarted after valid data is available on the bus.  
Same as the normal burst mode, the latency is determined by the host based on the BRWL bit setting in the System Configuration 1 Register.  
The default BRWL is 4 latency cycles. At clock frequencies of 40MHz or lower, latency cycles can be reduced to 3, at frequency range from  
40MHz to 66MHz, latency cycle should be over 4. Over clock frequency of 66MHz, latency cycle should be over 6.  
For BufferRAMs, both ‘Start Initial Burst Write’ and ‘Burst Write’ is supported. (Refer to Chapter 3.2) However, for Register Access, only ‘Start  
Initial Burst Write’ is supported. Therefore, Synchronous Burst Write on Register is prohibited.(Refer to Chapter 3.2 and 6.8)  
- 71 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
3.9 Program Operation  
See Timing Diagrams 6.11  
The Program operation is used to program data from the on-chip BufferRAMs into the NAND FLASH memory array.  
The device has two 2KB data buffers, 1 Page (4KB + 128B) in size. A page has 8 sectors of 512B each main area and 16B spare area. The  
device can be programmed in units of 8 sectors at once.  
Addressing for program operation  
Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of the block to MSB (most significant  
bit) pages of the block. Random page address programming is prohibited. Once users start to write data on a certain page, the page is a LSB  
page, therefore LSB page does not have to always be a page 0.  
MLC Block  
(128)  
(128)  
Page 127  
Page 31  
Page 127  
Page 31  
:
:
(1)  
:
(32)  
:
(3)  
(2)  
(1)  
Page 2  
Page 1  
Page 0  
(3)  
(32)  
(2)  
Page 2  
Page 1  
Page 0  
Data register  
Data register  
From the LSB page to MSB page  
DATA IN: Data (1)  
Ex.) Random page program (Prohibition)  
DATA IN: Data (1)  
Data (128)  
Data (128)  
SLC Block  
(64)  
(64)  
Page 63  
Page 63  
:
:
(1)  
:
(32)  
Page 31  
Page 31  
:
(3)  
(2)  
(1)  
Page 2  
Page 1  
Page 0  
(3)  
(32)  
(2)  
Page 2  
Page 1  
Page 0  
Data register  
Data register  
From the LSB page to MSB page  
DATA IN: Data (1)  
Ex.) Random page program (Prohibition)  
DATA IN: Data (1)  
Data (64)  
Data (64)  
NOTE :  
The figure explains the order of page programming in a block. (x) indicates that the corresponding  
page is the Xth page to be written in the block.  
- 72 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
Paired Page Address Information  
In case of MLC partition, when Program, Cache Program, Interleave cache program, Copy-back with random data in operations are abnor-  
mally aborted(eg. power-down), not only page data under program but also paired page data may be damaged.  
Paired Page Address  
Paired Page Address  
00h  
02h  
06h  
0Ah  
0Eh  
12h  
16h  
1Ah  
1Eh  
22h  
26h  
2Ah  
2Eh  
32h  
36h  
3Ah  
3Eh  
42h  
46h  
4Ah  
4Eh  
52h  
56h  
5Ah  
5Eh  
62h  
66h  
6Ah  
6Eh  
72h  
76h  
7Ah  
04h  
08h  
0Ch  
10h  
14h  
18h  
1Ch  
20h  
24h  
28h  
2Ch  
30h  
34h  
38h  
3Ch  
40h  
44h  
48h  
4Ch  
50h  
54h  
58h  
5Ch  
60h  
64h  
68h  
6Ch  
70h  
74h  
78h  
7Ch  
7Eh  
01h  
03h  
07h  
0Bh  
0Fh  
13h  
17h.  
1Bh  
1Fh  
23h  
27h  
2Bh  
2Fh  
33h  
37h  
3Bh  
3Fh  
43h  
47h  
4Bh  
4Fh  
53h  
57h  
5Bh  
5Fh  
63h  
67h  
6Bh  
6Fh  
73h  
77h  
7Bh  
05h  
09h  
0Dh  
11h  
15h  
19h  
1Dh  
21h  
25h  
29h  
2Dh  
31h  
35h  
39h  
3Dh  
41h  
45h  
49h  
4Dh  
51h  
55h  
59h  
5Dh  
61h  
65h  
69h  
6Dh  
71h  
75h  
79h  
7Dh  
7Fh  
- 73 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
Pairing of pages in MLC block:  
10  
8
0
78  
79  
11  
12  
13  
14  
15  
16  
17  
9
A
B
C
D
E
F
1
2
7A  
7B  
7C  
7D  
7E  
7F  
3
. . .  
4
5
6
7
Represents a Page number XX in an MLC block  
Represents Pairing of pages in an MLC block  
XX  
- 74 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
Program Operation Flow Diagram  
Write 0 to interrupt register6)  
Start  
Add: F241h DQ=0000h  
Select DataRAM for DDP1)  
Add: F101h DQ=DBS*  
Write ‘Program’ Command  
Add: F220h  
DQ=0080h  
Write Data into DataRAM2)  
ADD: DataRAM DQ=Data(4KB)  
Wait for INT register  
low to high transition  
NO  
Data Input  
Add: F241h DQ[15]=INT  
Completed?  
Read Controller  
Status Register  
YES  
Write ‘DFS*, FBA’ of Flash  
Add: F100h DQ=DFS*, FBA  
Add: F240h DQ[10]=Error  
Read Write Protection Status  
Add: F24Eh DQ=US,LS,LTS  
DQ[10]=0?  
YES  
NO  
Program completed  
Program Error  
Write ‘FPA, FSA’ of Flash  
Add: F107h DQ=FPA, FSA3)  
Write ‘BSA, BSC’ of DataRAM  
Add: F200h DQ=0800h4)  
Write System Configuration  
Register5)  
Add: F221h DQ=ECC  
: If program operation results in an error, map out  
the block including the page in error and copy the  
target data to another block.  
*
* DBS, DFS is for DDP  
NOTE :  
1) DBS must be set before data input.  
2) Data input could be done anywhere between "Start" and "Write Program Command".  
3) FSA must be 00 within program operation.  
4) BSA must be 1000 and BSC must be 000.  
5) Writing System Configuration Register is optional.  
6) ‘Write 0 to interrupt register’ step may be ignored when using INT auto mode. Refer to chapter 2.8.18.1  
During the execution of the Internal Program Routine, the host is not required to provide any further controls or timings. Furthermore, all com-  
mands, except a Reset command, will be ignored. A reset during a program operation will cause data corruption at the corresponding location.  
If a program error is detected at the completion of the Internal Program Routine, map out the block, including the page in error, and copy the  
target data to another block. An error is signaled if DQ10 = "1" of Controller Status Register(F240h).  
If Power off occurs during a Program operation, the page that is being programmed might be corrupted. Data from paired pages may be  
affected.  
- 75 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
Program Interleave(@DDP) Flow Chart  
Start  
NO  
Has Final Program  
command been issued?  
Select DataRAM for DDP1)  
Add: F101h DQ=DBS*  
Select DataRAM for DDP1)  
Add: F101h DQ=DBS*  
YES  
(Final Program status check)  
Select DataRAM for DDP1)  
Add: F101h DQ=DBS*  
Write Data into DataRAM  
Write Data into DataRAM  
Add: DataRAM, DQ=Data(4KB)  
Add: DataRAM, DQ=Data(4KB)  
Wait for INT register  
low to high transition  
3
*
Write ‘DFS*, FBA’ of Flash  
Add: F100h DQ=DFS*, FBA  
Write ‘DFS*, FBA’ of Flash  
Add: F100h DQ=DFS*, FBA  
Add: F241h DQ[6]=WI  
}
Read Controller status register  
Add: F240h DQ[10]=Error  
Read Write Protection Status  
Add: F24Eh DQ=US,LS,LTS  
Read Write Protection Status  
Add: F24Eh DQ=US,LS,LTS  
NO(Program Fail)  
Write ‘FPA, FSA’ of Flash  
Add: F107h DQ=FPA, FSA2)  
Write ‘FPA, FSA’ of Flash  
Add: F107h DQ=FPA, FSA2)  
DQ[10]=0?  
YES(Program Pass)  
Write ‘BSA, BSC’ of DataRAM  
Add: F200h DQ=08003)  
Write ‘BSA, BSC’ of DataRAM  
Add: F200h DQ=08003)  
Program completed  
Write Program command  
Add: F220h DQ=0080h  
Write Program command  
Add: F220h DQ=0080h  
Program Error  
Select DataRAM for DDP1)  
Add: F101h DQ=DBS*  
Select DataRAM for DDP1)  
Add: F101h DQ=DBS*  
* DBS, DFS is for DDP  
1
*
Check for INT register high  
Wait for INT register  
low to high transition  
{
Add: F241h DQ[15]=INT  
INT=1(Ready)  
2
*
Add: F241h DQ[6]=WI  
{
Read Controller status register  
Add: F240h DQ[10]=Error  
YES(Program Pass)  
DQ[10]=0?  
NO(Program Fail)  
Program Error  
Program Interleave can work in Auto INT  
Mode.  
Interrupt register must not be written.  
*
1
*
Check the chip status before command issues.  
Previous Program Status Check  
DBS must be changed to indicate chip.  
2
*
Program has been issued prior to current program ongoing  
3
*
Final Program Status Check  
NOTE :  
1) DBS must be set before data input.  
2) FSA must be 00 and BSC must be 000 within program operation  
3) BSA must be 1000 and BSC must be 000.  
- 76 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
3.9.1 Cache Program Operation  
See Timing Diagram 6.12  
The Cache Program is to enhance the performance of Program Operation. Employing Cache Program operation, transfer time from Host to  
DataRAM can be shadowed, therefore write performance will increase.  
In Cache Program, since 4KB data is to be programmed into NAND Flash Array in another advanced way.  
1. 4KB Data write from host to DataRAMs.  
2. Cache Program command issue. This will turn INT pin to busy state1), OnGo bit sets to ‘1’.  
(Note that before issuing ‘Cache Program Command’, host should make sure that the target blocks are unlocked.)  
3. 4KB data will be sequentially transferred to a page buffer in NAND Flash Array.  
4. When this transfer operation is complete, programming into NAND Flash Array will automatically start, and at the same time, INT bit will turn  
to ‘1’ to indicate that DataRAMs are now ready to be written with next 4KB data.  
5. When second 4KB is written to two DataRAMs, another Cache Program command is issued and INT bit will go to ‘0’1).  
If host wants to program data less than 8 sectors, unwanted area to be programmed must be written to all ‘1’s.  
When INT bit goes to ‘1’ after second data transfer from DataRAMs to Page Buffers are complete, user may check the Status Register to  
check the Cache program status. During Cache Program, Error bit shows the status of previous program operation.  
For the final 4KB program of Cache Program scheme, host should issue Program Command(0080h). And when the final page is programmed,  
INT bit will turn to ‘1’ and OnGo status bit - which indicates the overall Cache Program ongoing status - will go to ‘0’. At the completion of  
Cache Program operation, Error bit will show the pass/fail status overall status of program, and previous ~ current bit will show where the error  
occurred accordingly (Refer to the below diagram.)  
Note that Cache Program command cannot be performed on OTP block and 1st block OTP.  
Cache Program operation must be utilized within a same area partitioned as SLC or MLC.  
DataRAM0  
1) Write to DataRAM (Page A)  
2) Wait for INT bit = 1  
3) Write to DataRAM (Page B)  
Page A  
Page B  
Sector0  
Sector7  
3’) Program Page Buffer  
(4 KB)  
DataRAM1  
2’) Copy to  
Page Buffer  
4 KB  
NOTE :  
2 and 2’ are concurrent; 3 and 3’ are concurrent  
- 77 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
Cache Program Operation Flow Diagram  
NO  
Start  
Last PGM?  
Select DataRAM for DDP1)  
Write Data into DataRAM0,1  
Write Data into DataRAM0,1  
Add: DataRAM DQ=Data(4KB)  
Add: DataRAM DQ=Data(4KB)  
Add: F101h DQ=DBS  
Write ‘DFS, FBA’ of Flash  
Add: F100h DQ=DFS, FBA  
Write ‘DFS, FBA’ of Flash  
Add: F100h DQ=DFS, FBA  
Write Data into DataRAM0,1  
Add: DataRAM DQ=Data(4KB)  
Read Write Protection Status  
Add: F24Eh DQ=US,LS,LTS  
Read Write Protection Status  
Add: F24Eh DQ=US,LS,LTS  
Write ‘DFS, FBA’ of Flash  
Add: F100h DQ=DFS, FBA  
Write ‘FPA, FSA’ of Flash  
Write ‘FPA, FSA’ of Flash  
Read Write Protection Status  
Add: F24Eh DQ=US,LS,LTS  
2)  
2)  
Add: F107h DQ=FPA, FSA  
Add: F107h DQ=FPA, FSA  
Write System Configuration  
Write ‘FPA, FSA’ of Flash  
Write System Configuration  
4)  
Register  
4)  
2)  
Register  
Add: F107h DQ=FPA, FSA  
Add: F221h DQ=ECC  
Add: F221h DQ=ECC  
3)  
Write ‘BSA , BSC’ of DataRAM  
Write 0 to interrupt register5)  
Add: F241h DQ=0000h  
2)  
Write 0 to interrupt register5)  
Add: F241h DQ=0000h  
Add: F200h DQ=0800h  
Write System Configuration  
4)  
Register  
Write Cache PGM CMD  
Add: F220h DQ=007Fh  
Write Finish PGM CMD  
Add: F220h DQ=0080h  
Add: F221h DQ=ECC  
Wait for INT register  
low to high transition  
Wait for INT register  
low to high transition  
Write 0 to interrupt register5)  
Add: F241h DQ=0000h  
Add: F241h DQ=8040h  
Add: F241h DQ=8040h  
Write Cache PGM CMD  
Add: F220h DQ=007Fh  
Read Controller  
Status Register  
Read Controller  
Status Register  
Add: F240h DQ[10]=Error  
Add: F240h DQ[10]=Error  
Wait for INT register  
low to high transition  
NO  
Add: F241h DQ=8040h  
NO  
DQ[10]=0?  
DQ[10]=0?  
YES  
YES  
complete  
* DBS, DFS is for DDP  
: If program operation results in an error, map out  
the block including the page in error and copy the  
target data to another block.  
Program Error  
*
NOTE :  
1) DBS must be set before data input.  
2) FSA must be 00 and BSC must be 000 within program operation.  
3) BSA must be 1000.  
4) Writing System Configuration Register is optional.  
5) ‘Write 0 to interrupt register’ step may be ignored when using INT auto mode. Refer to chapter 2.8.18.1  
.
- 78 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
3.9.2 Interleave Cache Program Operation  
The Interleave Cache Program is available only on DDP. Host can write data on a chip while programming another chip with this operation.  
Interleave Cache Program is executing as following:  
1. 4KB Data are written from host to DataRAMs in Chip1.  
2. Cache Program command issue. This will turn INT bit to busy state1), OnGo bit sets to ‘1’.  
(Note that before issuing ‘Interleave Cache Program Command’, host should make sure that the target blocks are unlocked.)  
3. 4KB data will be sequentially transferred to each page buffer in NAND Flash Array.  
4. While these data are transferring, Host can write another 4KB Data to DataRAM in Chip2.  
5. When the transfer operation is completed, programming into NAND Flash Array will automatically start, and at the same time, INT bit will  
turn to ‘1’ to indicate that DataRAMs are now ready to be written with next 4KB data.  
6. Second 4KB is writable on Chip1 when INT1 goes to ‘1’.  
7. When second 4KB is written to two DataRAMs of Chip1, another Cache Program command is issued and INT1 bit will go to ‘0’1) again.  
When INT bit goes to ‘1’ after second data transfer from DataRAMs to Page Buffers are complete, user may check the Status Register to  
check the Cache program status. During Cache Program, previous bit shows the status of previous program operation.  
For the final 4KB program of Interleave Cache Program scheme, host should issue Program Command(0080h) on each chip. If host issues  
0080h on only a chip, another chip will be on operation as it is not finished. Ongo status bit will show the ongoing status of each chip. Its oper-  
ation is same as Cache Program operation on each chip. Error bit will show the pass/fail status of each chip of Interleave Cache program, and  
previous ~ current bit will show where the error occurred accordingly .  
Note that OTP block and 1st block OTP cannot be Interleave Cache Programmed.  
Interleave Cache Program operation must be utilized within a same area partitioned as SLC or MLC.  
1) Data Write, Issue Program Command (Page A)  
3) Check for INT bit = 1, then Data write (Page B)  
DataRAM0  
Page A  
Page B  
Sector0  
Sector7  
3’) Program Page Buffer  
(4 KB)  
DataRAM1  
4 KB  
2’) Copy to  
Page Buffer  
2) Data Write, Issue Program Command (Page A)  
4) Check for INT bit = 1, then Data write (Page B)  
DataRAM0  
Page A  
Page B  
Sector0  
Sector7  
4’) Program Page Buffer  
(4 KB)  
DataRAM1  
4 KB  
3’’) Copy to  
Page Buffer  
NOTE :  
2 and 2’ are concurrent; 3, 3’ and 3’’ are concurrent; 4 and 4’ are concurrent.  
- 79 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
Interleave Cache Program Operation Flow Diagram  
Start  
Select a chip for DDP1)  
Add: F100h DQ=DFS  
Add: F101h DQ=DBS  
Select a chip for DDP1)  
Add: F100h DQ=DFS  
Add: F101h DQ=DBS  
Select DataRAM for DDP1)  
Add: F101h DQ=DBS  
NO  
DQ[10]=0?  
YES  
Check INT register  
if it is ready3)  
Select DataRAM for DDP1)  
Add: F101h DQ=DBS  
Write Data into DataRAM0,1  
Add: DataRAM DQ=Data(4KB)  
Check INT register  
if it is ready5)  
Add: F241h DQ=8040h  
Add: F241h DQ=8040h  
Check INT register  
if it is ready5)  
Write ‘DFS, FBA’ of Flash  
Add: F100h DQ=DFS, FBA  
Read Controller  
Status Register  
Read Controller  
Status Register  
Add: F241h DQ=8040h  
Add: F240h  
DQ[2]=Previous  
Add: F240h  
DQ[2]=Previous  
Read Write Protection Status  
Add: F24Eh DQ=US,LS,LTS  
Read Controller  
Status Register7)  
NO  
NO  
NO  
DQ[4] | DQ[2] = 0?  
YES  
DQ[4] | DQ[2] = 0?  
YES  
Add: F240h DQ[10]=Error  
Write ‘FPA, FSA’ of Flash  
2)  
Add: F107h DQ=FPA, FSA  
NO  
Write Data into DataRAM0,1  
Add: DataRAM DQ=Data(4KB)  
Last PGM  
for a chip?  
DQ[10]=0?  
YES  
3)  
Write ‘BSA , BSC’ of DataRAM  
Add: F200h DQ=0800h2)  
YES  
Write ‘DFS, FBA’ of Flash  
Add: F100h DQ=DFS, FBA  
Write Data into DataRAM0,1  
Add: DataRAM DQ=Data(4KB)  
complete  
Write System Configuration  
Register4)  
Read Write Protection Status  
Add: F24Eh DQ=US,LS,LTS  
Add: F221h DQ=ECC  
Write ‘DFS, FBA’ of Flash  
Add: F100h DQ=DFS, FBA  
Write ‘FPA, FSA’ of Flash  
Write Cache PGM CMD  
Add: F220h DQ=007Fh  
2)  
Add: F107h DQ=FPA, FSA  
Read Write Protection Status  
Add: F24Eh DQ=US,LS,LTS  
Write System Configuration  
Register4)  
NO  
Is it first input  
for a chip  
Write ‘FPA, FSA’ of Flash  
2)  
Add: F221h DQ=ECC  
Add: F107h DQ=FPA, FSA  
YES  
Write PGM CMD6)  
Add: F220h DQ=0080h  
Write System Configuration  
Register4)  
Add: F221h DQ=ECC  
Wait for INT register  
low to high transition5)  
* DBS, DFS is for DDP  
Add: F241h DQ=8040h  
Write PGM CMD6)  
Add: F220h DQ=0080h  
If program operation  
results in an error,  
map out the block  
including the page in  
error and copy the  
target data to another  
block.  
*
Read Controller  
Status Register7)  
Add: F240h DQ[10]=Error  
Program Error  
NOTE :  
1) DBS must be set before data input.  
2) FSA must be 00 and BSC must be 000 within program operation.  
3) BSA must be 1000.  
4) Writing System Configuration Register is optional.  
5) Host is strongly recommended to see the INT register(F241h) of each chip.  
6) Once ‘PGM command’ is issued onto a chip, the same command(PGM) must be issued onto another chip. If not, Samsung cannot gurantee the following oper-  
ation.  
7) If error bit is set at this step, DQ[1]~[4] shoulde be checked in order to find where the error occurred.  
- 80 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
3.10 Copy-Back Program Operation with Random Data Input  
The Copy-Back Program Operation with Random Data Input in Flex-MuxOneNAND consists of 3 phases, Load data into DataRAM, Modify  
data and program into designated page. Data from the source page is saved in one of the on-chip DataRAM buffers and modified by the host,  
then programmed into the destination page.  
As shown in the flow chart, data modification is possible upon completion of load operation. ECC is also available at the end of load operation.  
Therefore, using hardware ECC of Flex-MuxOneNAND, accumulation of 4 bit error can be avoided.  
Copy-Back Program Operation with Random Data Input will be effectively utilized at modifying certain bit, byte, word, or sector of source page  
to destination page while it is being copied.  
Copy-Back Program Operation with Random Data Input Flow Chart  
Start  
Read ECC Status Register1  
Write System Configuration  
Register3)  
Add: FF00h DQ=ER1[12:8], ER0[4:0]  
Write ‘DFS*, FBA’ of Flash  
Add: F100h DQ=DFS, FBA  
Add: F221h DQ=ECC  
Read ECC Status Register2  
Write 0 to interrupt register4)  
Add: F241h DQ=0000h  
Add: FF01h DQ=ER3[12:8], ER2[4:0]  
Select DataRAM for DDP  
Add: F101h DQ=DBS  
Read ECC Status Register3  
Write ‘Program’ Command  
Add: FF02h DQ=ER5[12:8], ER4[4:0]  
Write ‘FPA, FSA’ of Flash  
Add: F107h DQ=FPA, FSA  
Add: F220h  
DQ=0080h  
Read ECC Status Register4  
Write ‘BSA1), BSC’ of DataRAM  
Add: F200h DQ=0800h2)  
Add: FF03h DQ=ER7[12:8], ER6[4:0]  
Wait for INT register  
low to high transition  
NO  
DQ[10]=0?  
Add: F241h DQ[15]=INT  
Write System Configuration  
Register3)  
YES  
Add: F221h DQ=ECC  
Read Controller  
Status Register  
Random Data Input  
Add: Random Address in  
Selected DataRAM  
DQ=Data  
Add: F240h DQ[10]=Error  
Write 0 to interrupt register4)  
Add: F241h DQ=0000h  
NO  
DQ[10]=0?  
Write ‘DFS, FBA’ of Flash  
Add: F100h DQ=DFS, FBA  
Write ‘Load’ Command  
Add: F220h DQ=0000h  
YES  
Copy back completed  
Read Write Protection Status  
Add: F24Eh DQ=US,LS,LTS  
Wait for INT register  
low to high transition  
Write ‘FPA, FSA’ of Flash  
Add: F107h DQ=FPA, FSA2)  
Add: F241h DQ[15]=INT  
Copy back Error  
Write ‘BSA1), BSC’ of DataRAM  
Add: F200h DQ=0800h2)  
* DBS, DFS is for DDP  
Map Out  
NOTE :  
1) BSA must be 1000.  
2) FSA must be 00 and BSC must be 000 within program operation.  
3) Writing System Configuration Register is optional.  
4) ‘Write 0 to interrupt register’ step may be ignored when using INT auto mode. Refer to chapter 2.8.18.1  
- 81 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
3.11 Erase Operation  
3.11.1 Block Erase Operation  
See Timing Diagram 6.14  
The device can be erased one block at a time. To erase a block is to write all 1's into the desired memory block by executing the Internal Erase  
Routine. All previous data is lost.  
Block Erase Operation Flow Chart  
Start  
Write ‘DFS*, FBA’ of Flash  
Add: F100h DQ=DFS*, FBA  
Select DataRAM for DDP  
Add: F101h DQ=DBS*  
Read Write Protection Status  
Add: F24Eh DQ=US,LS,LTS  
Write 0 to interrupt register1)  
Add: F241h DQ=0000h  
Write ‘Erase’ Command  
Add: F220h DQ=0094h  
Wait for INT register  
low to high transition  
Add: F241h DQ=[15]=INT  
Read Controller  
Status Register  
Add: F240h DQ[10]=Error  
DQ[10]=0?  
YES  
NO  
Erase completed  
Erase Error  
* DBS, DFS is for DDP  
: If erase operation results in an error, map out  
the failing block and replace it with another block.  
*
NOTE :  
1) ‘Write 0 to interrupt register’ step may be ignored when using INT auto mode. Refer to chapter 2.8.18.1  
In order to perform the Internal Erase Routine, the following command sequence is necessary.  
The Host selects Flash Core of DDP chip.  
The Host sets the block address of the memory location.  
The Erase Command initiates the Internal Erase Routine. During the execution of the Routine, the host is  
not required to provide further controls or timings. During the Internal erase routine, all commands, except  
the Reset command and Erase Suspend Command, written to the device will be ignored.  
A reset or power off during an erase operation will cause data corruption at the corresponding location Block.  
- 82 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
1)  
Erase Interleave (@DDP) Flow Chart  
Start  
NO  
Has Final Erase  
command been issued?  
Select DataRAM for DDP  
Add: F101h DQ=DBS*  
Write ‘DFS*, FBA’ of Flash  
Add: F100h DQ=DFS*, FBA  
YES  
(Final Erase status check)  
Select DataRAM for DDP  
Add: F101h DQ=DBS*  
Wait for INT register  
low to high transition  
Select DataRAM for DDP  
Add: F101h DQ=DBS*  
2
*
Add: F241h DQ=[5]=EI  
Wait for INT register  
low to high transition  
{
Write ‘Erase’ Command  
Add: F220h DQ=0094h  
3
*
Read Controller status register  
Add: F240 DQ[10]=Error  
Add: F241h DQ[5]=EI  
}
YES(Erase Pass)  
DQ[10]=0?  
Select DataRAM for DDP  
Add: F101h DQ=DBS*  
Read Controller status register  
Add: F240h DQ[10]=Error  
NO(Erase Fail)  
1
*
NO(Erase Fail)  
Check for INT register high  
{
DQ[10]=0?  
Add: F241h DQ[15]=INT  
INT=1(Ready)  
YES(Erase Pass)  
Erase Error  
Erase completed  
Write ‘DFS*, FBA’ of Flash  
Add: F100h DQ=DFS*, FBA  
Select DataRAM for DDP  
Add: F101h DQ=DBS*  
Write ‘Erase’ Command  
Add: F220h DQ=0094h  
Erase Interleave can work in Auto INT Mode.  
Interrupt register must not be written.  
*
1
*
Check the chip status before command issues.  
Previous Erase Status Check  
2*  
DBS must be changed to indicate chip.  
Erase has been issued prior to current erase ongoing  
Final Erase Status Check  
3
*
NOTE :  
1) Erase Suspend and Erase Resume Operations are not supported in Erase Interleave(@DDP).  
- 83 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
3.11.2 Erase Suspend / Erase Resume Operation  
The Erase Suspend/Erase Resume Commands interrupt and restart a Block Erase operation so that user may perform another urgent opera-  
tion on the block that is not being designated by Erase Operation.  
Erase Suspend During a Block Erase Operation  
When Erase Suspend command is written during a Block Erase operation, the device requires a maximum of 500us to suspend erase opera-  
tion. Erase Suspend Command issue during Block Address latch sequence is prohibited.  
After the erase operation has been suspended, the device is ready for the next operation including a load, program, Lock, Unlock, Lock-tight,  
Hot Reset, NAND Flash Core Reset, Command Based Reset, or OTP Access.  
The subsequent operation can be to any block that was NOT being erased.  
A special case arises in Erase Suspend operation pertaining to the OTP. A Reset command is used to exit from the OTP Access mode. If the  
Reset-triggered exit from the OTP Access Mode happens after an Erase Suspend Operation, the erase routine could fail. Therefore to exit  
from the OTP Access Mode without causing the erase suspend/resume operation to fail, a 'NAND Flash Core Reset' command should be  
issued.  
For the duration of the Erase Suspend period the following commands are not accepted:  
Block Erase/Erase Suspend  
Erase Suspend and Erase Resume Operation Flow Chart  
Write DFS of Flash  
Add: F100h DQ=DFS**  
Start  
Write 0 to interrupt register1)  
Add: F241h DQ=0000h  
Select DataRAM for DDP  
Add: F101h DQ=DBS**  
Select DataRAM for DDP  
Add: F101h DQ=DBS**  
Write 0 to interrupt register1)  
Add: F241h DQ=0000h  
Write ‘Erase Suspend  
Command’  
Write ‘Erase Resume  
Command’  
Add: F220h DQ=00B0h  
Add: F220h DQ=0030h  
Wait for INT register  
low to high transition for 500us  
Wait for INT register  
low to high transition  
* Another Operation ;  
Load, Program, OTP Access2),  
Hot Reset, Flash Reset, CMD Reset,  
Lock,Lock-tight, Unlock  
Add: F241h DQ=[15]=INT  
Another Operation *  
Add: F241h DQ=[15]=INT  
Check Controller Status Register  
in case of Block Erase  
** DBS, DFS is for DDP  
NOTE :  
1) ‘Write 0 to interrupt register’ step may be ignored when using INT auto mode. Refer to chapter 2.8.18.1  
2) If OTP access mode exit happens with Reset operation during Erase Suspend mode, Reset operatin could hurt the erase operation. So if a user wants to exit  
from OTP access mode without the erase operation stop, Reset NAND Flash Core command should be used.  
Erase Resume  
When the Erase Resume command is executed, the Block Erase will restart. The Erase Resume operation does not actually resume the  
erase, but starts it again from the beginning.  
When an Erase Suspend or Erase Resume command is executed, the addresses are in Don't Care state.  
- 84 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
3.12 Partition Information (PI) Block (SLC Only)  
One Block of the SLC NAND Flash Array memory is reserved for Partition Information (PI) Block.  
The block can be read, programmed and erased using the same operations as any other NAND Flash Array memory block.  
Only Load, Erase and Program can be performed. PI Block is not able to cover with internal ECC Engine in OneNAND, so it has to be  
accessed under ECC off mode.  
PI block is guaranteed to be a valid block up to 1K program/erase cycles.  
Entering the PI Block  
The PI block is separately accessible from the rest of the NAND Flash Array by using the PI Access command instead of the Flash Block  
Address (FBA).  
Exiting the PI Block  
To exit the PI Access Mode, a Cold-, Warm-, Hot-, or NAND Flash Core Reset operation is performed.  
Exiting the PI Block during an Erase Operation  
If the Reset-triggered exit from the PI Access Mode happens after during an Erase Suspend Operation, the erase routine could fail. Therefore  
to exit from the PI Access Mode without causing the erase operation to fail, a 'NAND Flash Core Reset' command should be issued.  
PI Block Page Allocation Information  
This is located at the 1st word of sector0 of page0 of main area in the Block.  
The allocated word in 1st page is programed with data FC00h initially after shipment, whole block is set as MLC except Block 0.  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
Lock  
Reserved(1111)  
Boundary Address (end of SLC area)  
PI Lock bits and Boundary Address.  
PI Block can be locked only by programming lock bits into [15:14] of the 1st word of sector0, page0 of the main memory area of PI.  
The first block is a SLC block. The MLC block will be defined from the next block of the block designated by boundary address programmed  
into[9:0] of the 1st word of sector0, page0 of the main memory area of PI.  
SLC area (Default)  
SLC area  
Block0  
BlockN  
Boundary  
Address  
BlockN+1  
MLC area  
Block1023  
[NAND Flash Array]  
- 85 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
3.12.1 PI Block Boundary Information setting  
It is 1st word of sector0 of page0 of main area of PI Block. The Lock bits for PI Block and Boundary address of SLC and MLC are stored. After  
shipment, it is initially programmed as data FC00h(Lock bit[15:14]: 11b(binary), Boundary address[9:0]: 000h).  
To change PI Block contents (i.e, lock bits and boundary address), Erase/Program sequence should be followed as below.  
PI Block Boundary Information setting steps  
Enter PI Block access mode(Refer to Chapter 3.12.1.1)  
Issue PI Block erase(Refer to Chapter 3.12.1.2)  
Issue PI program(Refer to Chapter 3.12.1.3)  
Exit PI Block Access mode & Update new Partition Information.  
.
.
.
PI block Access mode exit can be done through a Warm/Cold/Hot/NAND Flash Reset.  
However, PI Update can only be done by two methods: PI Update Command and Cold Reset.  
The following flow chart shows two methods for updating the PI and exiting PI access mode.  
PI Block Boundary Information setting Flow Chart  
Start  
PI Block Access mode entry1)  
PI Block Erase2)  
PI Program3)  
(Lock bit, Boundary of Address)  
PI Block Update4)  
Cold Reset  
Warm/Hot/NAND Flash Reset  
PI Block Access Mode exit  
PI Update done  
NOTE :  
1) Refer to Chapter 3.12.1.1  
2) Refer to Chapter 3.12.1.2  
3) Refer to Chapter 3.12.1.3  
4) Refer to Chapter 3.12.1.4  
- 86 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
3.12.1.1 PI Block Access mode entry  
The PI area is a separate part of the NAND Flash Array memory. It is accessed by issuing PI Access command(66h) instead of writing a Flash  
Block Address(FBA) in the StartAddress1 register.  
After being accessed through the PI Access Command, the contents of PI memory area can be programmed, erased or loaded using the  
same operations as a normal program, erase or load operation to the NAND Flash Array memory.  
PI Block Access mode entry Flow Chart  
Start  
Write ‘DFS*, FBA’ of Flash1)  
Add: F100h DQ=DFS*, FBA  
Select DataRAM for DDP  
Add: F101h DQ=DBS*  
Write 0 to interrupt register2)  
Add: F241h DQ=0000h  
Write ‘PI Access’ Command  
Add: F220h DQ=0066h  
Wait for INT register  
low to high transition  
Add: F241h DQ[15]=INT  
PI Block Access mode entry completed  
* DBS, DFS is for DDP  
NOTE :  
1) FBA(NAND Flash Block Address) could be omitted or any address.  
2) ‘Write 0 to interrupt register’ step may be ignored when using INT auto mode. Refer to chapter 2.8.18.1  
- 87 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
3.12.1.2 PI Block Erase  
The PI Block Erase Operation erases the entire PI block including Partition Information. PI Block Access mode entry must be done before  
issuing Erase operation for PI Block.  
Erasing the PI Area  
Issue the PI Access Command(Refer to Chapter 3.12.1.1).  
Issue an Erase command to erase the PI area.  
PI Block Erase Operation Flow Chart (In PI Block Access Mode)  
Start  
Write ‘FBA’ of Flash  
1)  
Add: F100h DQ=FBA  
2)  
Write 0 to interrupt register  
Add: F241h DQ=0000h  
Write Erase command  
Add: F220h  
DQ=0094h  
Wait for INT register  
low to high transition  
Add: F241h DQ[15]=INT  
Read Controller  
Status Register  
YES  
Add: F240h  
DQ[10]=1(Error)  
NO  
PI Erase Complete  
PI Erase Error  
* DBS, DFS is for DDP  
NOTE :  
1) FBA(NAND Flash Block Address) must be 0000h.  
2) ‘Write 0 to interrupt register’ step may be ignored when using INT auto mode. Refer to chapter 2.8.18.1  
- 88 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
3.12.1.3 PI Block Program Operation  
The PI Block Program Operation accesses the PI area and programs content from the DataRAM on-chip buffer to the designated page(s) of  
the PI.  
A memory location in the PI area can be program.  
The PI area is programmed using the same sequence as normal program operation after being accessed by the PI Block Access mode entry  
command (see section 3.8 for more information).  
Programming the PI Area  
Issue the PI Access Command(Refer to Chapter 3.12.1.1).  
Write data into the DataRAM  
- In case of PI Lock(Add: 0200h, DQ=3XXXh, The lower 10 bits[9:0] are boundary address) .  
- In case of PI Unlock(Add: 0200h, DQ=FXXXh, The lower 10 bits[9:0] are boundary address).  
Write 0000h into Flash Block Address (FBA), that is address of NAND Flash Array address map.  
Issue a Program command to program the data from the DataRAM into the PI.  
PI Block Program Operation Flow Chart (In PI Block Access Mode)  
Write Program command  
Add: F220h  
Start  
DQ=0080h  
Wait for INT register  
low to high transition  
Write Data into DataRAM  
Add: 0200h DQ= 1 word1)  
Add: F241h DQ[15]=INT  
Write ‘DFS, FBA’ of Flash  
Add: F100h DQ=FBA  
Read Controller  
Status Register  
2)  
YES  
Add: F240h  
DQ[10]=1(Error)  
Write ‘FPA, FSA’ of Flash  
Add: F107h DQ=0000h  
3)  
NO  
PI Programming completed  
PI Program Error  
Write ‘BSA, BSC’ of DataRAM  
Add: F200h DQ=0800h4)  
* DBS, DFS is for DDP  
5)  
Write 0 to interrupt register  
Add: F241h DQ=0000h  
Locking the PI  
Programming to PI block can be prevented by locking the PI area. Locking the PI area is accomplished by programming 3XXXh to 1st word of  
sector0 of main of the page0 memory area in the PI block(XXXh out of 3XXXh is a boundary block address that ends SLC area).  
Once Lock bits are programmed as lock status, PI block will be protected from program and erase. Boundary address is alterable before PI  
block is locked, but it is not recommended.  
At device power-up and PI Update operation, this word is updated internally. If 3XXXh is found(i.e. the status of PI is locked), Program/Erase  
operations to PI block result in an error and the device updates the Error Bit of the Controller Status Register as "1"(fail).  
NOTE :  
1) Only the 1st word of 1st page of PI block (PI block Boundary Information) can be programmed in PI Block.  
The rest of the block cannot be programmed.  
2) FBA(NAND Flash Block Address) must be 0000h.  
3) FPA must be 00h and FSA must be 00.  
4) BSA must be 1000 and BSC must be 000.  
5) ‘Write 0 to interrupt register’ step may be ignored when using INT auto mode. Refer to chapter 2.8.18.1  
- 89 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
3.12.1.4 PI Update  
Once new partition information is programmed into the PI block, an internal register that is invisible to users must be updated for the changes  
in PI to be applied. This internal register which stores partition information(i.e. the last address of SLC area and lock bits) will be automatically  
updated through cold reset. However, the internal register can also be updated by issuing Partition Information Update command(05h) after PI  
Access mode entry.  
Update the PI Area  
Issue the PI Access mode(Refer to Chapter 3.12.1.1).  
Issue the update PI command.  
PI Block Update (In PI Block Access Mode)  
Start  
Write ‘DFS, FBA’ of Flash1)  
Add: F100h DQ=DFS, FBA  
Write ‘BSA, BSC’ of DataRAM  
Add: F200h DQ=0800h2)  
Write 0 to interrupt register3)  
Add: F241h DQ=0000h  
Write ‘FPA, FSA’ of Flash  
Add: F107h DQ=0000h4)  
Write Update PI command  
Add: F220h  
DQ=0005h  
Wait for INT register  
low to high transition  
Add: F241h DQ[15]=INT  
PI updated  
* DBS, DFS is for DDP  
NOTE :  
1) FBA(NAND Flash Block Address) must be 0000h.  
2) BSA must be 1000 and BSC must be 000.  
3) ‘Write 0 to interrupt register’ step may be ignored when using INT auto mode. Refer to chapter 2.8.18.1  
4) FPA must be 00h and FSA must be 00.  
- 90 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
3.12.2 PI Block Load Operation  
A PI Block Load Operation accesses the PI area and transfers identified content from the PI to the DataRAM on-chip buffer, thus making the  
PI contents available to the Host.  
The PI area is a separate part of the NAND Flash Array memory. It is accessed by issuing PI Access command(66h).  
After being accessed with the PI Access Command, the contents of PI memory area are loaded using the same operations as a normal load  
operation to the NAND Flash Array memory (see section 3.6 for more information).  
To exit the PI access mode after an PI Block Load Operation, a Cold-, Warm-, Hot-, or NAND Flash Core Reset operation is performed.  
PI Block Read Operation Flow Chart (In PI Block Access Mode)  
Start  
Write 0 to interrupt register2)  
Add: F241h DQ=0000h  
Write ‘DFS*, FBA’ of Flash1)  
Add:F100h DQ=DFS*, FBA  
Write ‘Load’ Command  
Select DataRAM for DDP  
Add: F101h DQ=DBS*  
Add: F220h  
DQ=0000h  
Write 0 to interrupt register2)  
Add: F241h DQ=0000h  
Wait for INT register  
low to high transition  
Add: F241h DQ[15]=INT  
Write ‘PI Access’ Command  
Add: F220h DQ=0066h  
Host reads data from  
DataRAM  
Wait for INT register  
low to high transition  
Add: F241h DQ[15]=INT  
PI Reading completed  
Write ‘FPA, FSA’ of Flash  
Add: F107h DQ=FPA, FSA  
Do Cold/Warm/Hot  
/NAND Flash Core Reset  
PI Block Access mode exit  
}
Write ‘BSA, BSC’ of DataRAM  
Add: F200h DQ=BSA3), BSC  
PI Exit  
* DBS, DFS is for DDP  
NOTE :  
1) FBA(NAND Flash Block Address) could be omitted or any address.  
2) ‘Write 0 to interrupt register’ step may be ignored when using INT auto mode. Refer to chapter 2.8.18.1  
3) BSA must be 1000.  
- 91 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
3.13 OTP Operation (SLC only)  
One Block of the NAND Flash Array memory is reserved as a One-Time Programmable Block memory area.  
Also, 1st Block of NAND Flash Array can be used as OTP.  
OTP area and 1st block OTP area must be utilized as a SLC block.  
The OTP block can be read, programmed and locked using the same operations as any other NAND Flash Array memory block.  
OTP block cannot be erased. Note that Cache program and Finish Cache program cannot be performed on OTP and 1st Block OTP area.  
OTP block is fully-guaranteed to be a valid block by an internal ECC engine.  
Entering the OTP Block  
The OTP block is separately accessible from the rest of the NAND Flash Array by using the OTP Access command instead of the Flash Block  
Address (FBA).  
Exiting the OTP Block  
To exit the OTP Access Mode, a Cold-, Warm-, Hot-, or NAND Flash Core Reset operation is performed.  
Exiting the OTP Block during an Erase Operation  
If the Reset-triggered exit from the OTP Access Mode happens during an Erase Suspend Operation, the erase  
routine could fail. Therefore to exit from the OTP Access Mode without suspending the erase operation, a  
'NAND Flash Core Reset' command should be issued.  
The OTP Block Page Assignment  
OTP area is one block size (128KB+4KB, 64 Pages) and is divided into two areas. The 50-page User Area is available as an OTP storage  
area. The 14-page Manufacturer Area is programmed by the manufacturer prior to shipping the device to the user.  
OTP Block Page Allocation Information  
Area  
User  
Page  
Use  
0 ~ 49 (50 pages)  
50 ~ 63 (14 pages)  
Designated as user area  
Used by the device manufacturer  
Manufacturer  
Three Possible OTP Lock Sequence (Refer to Chapter 3.13.3~3.13.5 for more information)  
Since OTP Block and 1st Block OTP can be locked only by programming into 1st word of sector4, page49 of the main memory area of OTP,  
OTP Block and 1st Block OTP lock sequence is restricted into three following cases.  
Note that user should be careful, because locking OTP Block before locking 1st Block OTP will disable locking 1st Block OTP.  
1. OTP Block Lock Only :  
Once the OTP Block is locked, 1st Block OTP Lock is impossible.  
2. 1st Block OTP Lock Only:  
Locking 1st Block OTP does not lock the OTP block, but the OTP Block Lock cannot be performed thereafter.  
3. OTP Block Lock and 1st Block OTP Lock simultaneously:  
This simultaneous operation can be done by programming into 1st word of sector4, page49 of the main memory area of OTP.  
- 92 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
OTP Block Area Structure  
Page:4KB+128B  
Sector(main area):512B  
Manufacturer Area :  
14pages  
Sector(spare area):16B  
page 50 to page 63  
One Block:  
64pages  
256KB+8KB  
User Area :  
50pages  
page 0 to page 49  
1st Block OTP Area Structure  
Page:4KB+128B  
Sector(main area):512B  
Sector(spare area):16B  
One Block:  
64pages  
256KB+8KB  
User Area :  
64pages  
page 0 to page 63  
- 93 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
3.13.1 OTP Block Load Operation  
An OTP Block Load Operation accesses the OTP area and transfers identified content from the OTP to the DataRAM on-chip buffer,  
thus making the OTP contents available to the Host.  
The OTP area is a separate part of the NAND Flash Array memory. It is accessed by issuing OTP Access command(65h) instead of  
a Flash Block Address (FBA) value in Start Address1 Register.  
.
After being accessed with the OTP Access Command, the contents of OTP memory area are loaded using the same operations as a normal  
load operation to the NAND Flash Array memory (see section 3.6 for more information).  
To exit the OTP access mode after an OTP Block Load Operation, a Cold-, Warm-, Hot-, or NAND Flash Core Reset operation is performed.  
OTP Block Read Operation Flow Chart  
Start  
Write 0 to interrupt register2)  
Add: F241h DQ=0000h  
Write ‘DFS*, FBA’ of Flash1)  
Add: F100h DQ=DFS*, FBA  
Select DataRAM for DDP  
Add: F101h DQ=DBS*  
Write ‘Load’ Command  
Add: F220h  
DQ=0000h  
Write 0 to interrupt register2)  
Add: F241h DQ=0000h  
Wait for INT register  
low to high transition  
Add: F241h DQ[15]=INT  
Write ‘OTP Access’ Command  
Add: F220h DQ=0065h  
Host reads data from  
DataRAM  
Wait for INT register  
low to high transition  
Add: F241h DQ[15]=INT  
OTP Reading completed  
Write ‘FPA, FSA’ of Flash  
Add: F107h DQ=FPA, FSA  
Do Cold/Warm/Hot  
/NAND Flash Core Reset  
Write ‘BSA, BSC’ of DataRAM  
Add: F200h DQ=0800h3)  
OTP Exit  
* DBS, DFS is for DDP  
NOTE :  
1) FBA(NAND Flash Block Address) could be omitted or any address  
2) ‘Write 0 to interrupt register’ step may be ignored when using INT auto mode. Refer to chapter 2.8.18.1  
3) BSA must be 1000 and BSC must be 000.  
- 94 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
3.13.2 OTP Block Program Operation  
An OTP Block Program Operation accesses the OTP area and programs content from the DataRAM on-chip buffer to the designated page(s)  
of the OTP.  
A memory location in the OTP area can be programmed only one time (no erase operation permitted).  
The OTP area is programmed using the same sequence as normal program operation after being accessed by the command (see section 3.9  
for more information).  
Programming the OTP Area  
Issue the OTP Access Command  
Write data into the DataRAM (data can be input at anytime between the "Start" and "Write Program commands".  
Issue a Flash Block Address (FBA) which is 0000h of NAND Flash Array address map.  
Issue a Program command to program the data from the DataRAM into the OTP  
When the OTP Block programming is complete,  
do a Cold-, Warm-, Hot-, NAND Flash Core Reset to exit the OTP Access mode.  
- 95 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
OTP Block Program Operation Flow Chart  
Write ‘FBA’ of Flash  
Start  
Add: F100h DQ=FBA4)  
Write ‘DFS*, FBA’ of Flash1)  
Add: F100h DQ=DFS*, FBA  
Write ‘FPA, FSA’ of Flash  
Add: F107h DQ=FPA, FSA5)  
Select DataRAM for DDP  
Add: F101h DQ=DBS*  
Write ‘BSA, BSC’ of DataRAM  
Add: F200h DQ=0800h6)  
Write 0 to interrupt register2)  
Add: F241h DQ=0000h  
Write 0 to interrupt register2)  
Add: F241h DQ=0000h  
Write ‘OTP Access’ Command  
Add: F220h DQ=0065h  
Write Program command  
Add: F220h  
DQ=0080h  
Wait for INT register  
low to high transition  
Automatically  
checked  
Automatically  
updated  
NO  
Add: F241h DQ[15]=INT  
OTPL=0?  
YES  
Write Data into DataRAM3)  
Add: DP DQ=Data-in  
Update Controller  
Status Register  
Wait for INT register  
low to high transition  
Add: F240h  
DQ[14]=1(Lock), DQ[10]=1(Error)  
Add: F241h DQ[15]=INT  
NO  
Data Input  
Completed?  
Wait for INT register  
low to high transition  
Read Controller  
Status Register  
Add: F241h DQ[15]=INT  
Add: F240h DQ[10]=0(Pass)  
Read Controller  
Status Register  
* DBS, DFS is for DDP  
OTP Programming completed  
Add: F240h DQ[10]=1(Error)  
Do Cold/Warm/Hot  
/NAND Flash Core reset  
Do Cold/Warm/Hot  
/NAND Flash Core reset  
OTP Exit  
OTP Exit  
NOTE :  
1) FBA(NAND Flash Block Address) could be omitted or any address.  
2) ‘Write 0 to interrupt register’ step may be ignored when using INT auto mode. Refer to chapter 2.8.18.1  
3) Data input could be done anywhere between "Start" and "Write Program Command".  
4) FBA must be 0000.  
5) FSA must be 00 within program operation.  
6) BSA must be 1000 and BSC must be 000.  
- 96 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
3.13.3 OTP Block Lock Operation  
Even though the OTP area can only be programmed once without erase capability, it can be locked when the device starts up to prevent any  
changes from being made.  
Unlike the main area of the NAND Flash Array memory, once the OTP block is locked, it cannot be unlocked, for locking bit for both  
blocks lies in the same word of OTP area.  
Therefore, if OTP Block is locked prior to 1st Block OTP lock, 1st Block OTP cannot be locked.  
Locking the OTP  
Programming to the OTP area can be prevented by locking the OTP area. Locking the OTP area is accomplished by  
programming XXFCh to the 1st word of sector4 of main of the page49 memory area in the OTP block.  
At device power-up, this word location is checked and if XXFCh is found, the OTPL bit of the Controller Status Register is set to "1", indicating  
the OTP is locked. When the Program Operation finds that the status of the OTP is locked, the device updates the Error Bit of the Controller  
Status Register as "1" (fail).  
OTP Lock Operation Steps  
Issue the OTP Access Command  
Fill data to be programmed into DataRAM (data can be input at anytime between the "Start" and "Write Program" commands)  
Write ‘XXFCh’ data into the 1st word of sector4 of main of the page49 memory area of the DataRAM.  
Issue a Flash Block Address (FBA) which is 0000h of NAND Flash Array address map.  
Issue a Program command to program the data from the DataRAM into the OTP  
When the OTP lock is complete, do a Cold Reset to exit the OTP Access mode and update OTP lock bit[6].  
OTP lock bit[6] of the Controller Status Register will be set to "1" and the OTP will be locked.  
- 97 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
OTP Block Lock Operation Flow Chart  
Write ‘FBA’ of Flash  
Start  
Add: F100h DQ=FBA4)  
Write ‘DFS, FBA’ of Flash1)  
Add: F100h DQ=DFS, FBA  
Write ‘FPA, FSA’ of Flash  
Add: F107h DQ=0196h5)  
Select DataRAM for DDP  
Add: F101h DQ=0000h(DBS*)  
Write ‘BSA, BSC’ of DataRAM  
Add: F200h DQ=0800h6)  
Write 0 to interrupt register2)  
Add: F241h DQ=0000h  
Write 0 to interrupt register2)  
Add: F241h DQ=0000h  
Write ‘OTP Access’ Command  
Add: F220h DQ=0065h  
Write Program command  
Add: F220h  
DQ=0080h  
Wait for INT register  
low to high transition  
Wait for INT register  
low to high transition  
Add: F241h DQ[15]=INT  
Add: F241h DQ[15]=INT  
Write Data into DataRAM3)  
Add: 1st Word  
in sector4/main0/page49  
DQ=XXFCh(Locking bit)  
Do Cold reset  
Automatically  
updated  
Update Controller  
Status Register  
Add: F240h  
DQ[6]=1(OTPL)  
* DBS, DFS is for DDP  
OTP lock completed  
NOTE :  
1) FBA(NAND Flash Block Address) could be omitted or any address.  
2) ‘Write 0 to interrupt register’ step may be ignored when using INT auto mode. Refer to chapter 2.8.18.1  
3) Data input could be done anywhere between "Start" and "Write Program Command".  
4) FBA must be 0000.  
5) FSA must be 00 within program operation. The 0196h is the page49 of NAND Flash Array address map.  
6) BSA must be 1000 and BSC must be 000.  
- 98 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
3.13.4 1st Block OTP Lock Operation  
1st Block can be used as OTP, for secured booting operation.  
1st Block OTP can be accessed just as any other NAND Flash Array Blocks before it is locked, however, once 1st Block is locked to be OTP,  
1st Block OTP cannot be erased or programmed.  
Note that once OTP Block is locked, 1st Block OTP lock is impossible also OTP Block cannot be locked freely after locking 1st Block OTP.  
OTP Block and 1st Block OTP should be locked at the same time.  
Locking the 1st Block OTP  
Programming to the 1st Block OTP area can be prevented by locking the OTP area. Locking the OTP area is accomplished by  
programming XXF3h to the 1st word of sector4 of main of the page49 memory area in the OTP block.  
At device power-up, this word location is checked and if XXF3h is found, the OTPBL bit of the Controller Status Register is set to "1", indicating  
the 1st Block is locked. When the Program Operation finds that the status of the 1st Block is locked, the device updates the Error Bit of the  
Controller Status Register as "1" (fail).  
1st Block OTP Lock Operation Steps  
Issue the OTP Access Command  
Fill data to be programmed into DataRAM (data can be input at anytime between the "Start" and "Write Program" commands)  
Write ‘XXF3h’ data into the 1st word of sector4 of main of the page49 memory area of the DataRAM.  
Issue a Flash Block Address (FBA) which is 0000h of NAND Flash Array address map.  
Issue a Program command to program the data from the DataRAM into the OTP  
When the 1st Block OTP lock is complete, do a Cold Reset to exit the OTP Access mode  
and update 1st Block OTP lock bit[5].  
1st Block OTP lock bit[5] of the Controller Status Register will be set to "1" and the 1st Block will be locked.  
Even though the OTP area can only be programmed once without erase capability, it can be locked when the device starts up to prevent any  
changes from being made.  
Unlike other remaining main area of the NAND Flash Array memory, once the 1st block OTP is locked, it cannot be unlocked.  
Once 1st block is set as OTP, NAND Flash Write Protection status register(F24Eh) indicates only ‘Lock’ state although ‘Lock tight’ or ‘Unlock’  
command is issued.  
- 99 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
1st Block OTP Lock Operation Flow Chart  
Write ‘FBA’ of Flash  
Start  
Add: F100h DQ=FBA4)  
Write ‘DFS, FBA’ of Flash1)  
Add: F100h DQ=DFS, FBA  
Write ‘FPA, FSA’ of Flash  
Add: F107h DQ=0196h5)  
Select DataRAM for DDP  
Add: F101h DQ=0000h(DBS*)  
Write ‘BSA, BSC’ of DataRAM  
Add: F200h DQ=0800h6)  
Write 0 to interrupt register2)  
Add: F241h DQ=0000h  
Write 0 to interrupt register2)  
Add: F241h DQ=0000h  
Write ‘OTP Access’ Command  
Add: F220h DQ=0065h  
Write Program command  
Add: F220h  
DQ=0080h  
Wait for INT register  
low to high transition  
Wait for INT register  
low to high transition  
Add: F241h DQ[15]=INT  
Add: F241h DQ[15]=INT  
Write Data into DataRAM3)  
Add: 1st Word  
in sector4 of main of the page49  
Do Cold reset  
DQ=XXF3h(Locking bit)  
Automatically  
updated  
Update Controller  
Status Register  
Add: F240h  
DQ[5]=1(OTPBL)  
1st Block OTP lock completed  
* DBS, DFS is for DDP  
NOTE :  
1) FBA(NAND Flash Block Address) could be omitted or any address.  
2) ‘Write 0 to interrupt register’ step may be ignored when using INT auto mode. Refer to chapter 2.8.18.1  
3) Data input could be done anywhere between "Start" and "Write Program Command".  
4) FBA must be 0000.  
5) FSA must be 00 within program operation. The 0196h is the page49 of NAND Flash Array address map.  
6) BSA must be 1000 and BSC must be 000.  
- 100 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
3.13.5 OTP and 1st Block OTP Lock Operation  
OTP and 1st Block can be locked simultaneously, for locking bit lies in the same word of OTP area.  
1st Block OTP can be accessed just as any other NAND Flash Array Blocks before it is locked, however, once 1st Block is locked to be OTP,  
1st Block OTP cannot be erased or programmed. Also, OTP area can only be programmed once without erase capability, it can be locked  
when the device starts up to prevent any changes from being made.  
Locking the OTP and 1st Block OTP  
Programming to the OTP area and 1st Block OTP area can be prevented by locking the OTP area. Locking the OTP area is  
accomplished by programming XXF0h to the 1st word of sector4 of main of the page49 memory area in the OTP block.  
At device power-up, this word location is checked and if XXF0h is found, the OTPL and OTPBL bit of the Controller Status Register is set to "1",  
indicating the OTP and 1st Block is locked. When the Program Operation finds that the status of the OTP and 1st Block is locked, the device  
updates the Error Bit of the Controller Status Register as "1" (fail).  
OTP and 1st Block OTP simultaneous Lock Operation Steps  
Issue the OTP Access Command  
Fill data to be programmed into DataRAM (data can be input at anytime between the "Start" and  
"Write Program" commands)  
Write ‘XXF0h’ data into the 1st word of sector4 of main of the page49 memory area of the DataRAM.  
Issue a Flash Block Address (FBA) which is 0000h of NAND Flash Array address map.  
Issue a Program command to program the data from the DataRAM into the OTP  
When the 1st Block OTP lock is complete, do a Cold Reset to exit the OTP Access mode  
and update 1st Block OTP lock bit[5] and OTP lock bit[6].  
1st Block OTP lock bit[5] and OTP lock bit[6] of the Controller Status Register will be set to "1" and  
the OTP and 1st Block will be locked.  
Unlike other remaining main area of the NAND Flash Array memory, once the OTP block and the 1st block OTP are locked, it cannot be  
unlocked.  
- 101 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
OTP and 1st Block OTP Lock Operation Flow Chart  
Write ‘FBA’ of Flash  
Start  
Add: F100h DQ=FBA4)  
Write ‘DFS, FBA’ of Flash1)  
Add: F100h DQ=DFS, FBA  
Write ‘FPA, FSA’ of Flash  
Add: F107h DQ=0196h5)  
Select DataRAM for DDP  
Add: F101h DQ=0000h(DBS*)  
Write ‘BSA, BSC’ of DataRAM  
Add: F200h DQ=0800h6)  
Write 0 to interrupt register2)  
Add: F241h DQ=0000h  
Write 0 to interrupt register2)  
Add: F241h DQ=0000h  
Write ‘OTP Access’ Command  
Add: F220h DQ=0065h  
Write Program command  
Add: F220h  
DQ=0080h  
Wait for INT register  
low to high transition  
Wait for INT register  
low to high transition  
Add: F241h DQ[15]=INT  
Add: F241h DQ[15]=INT  
Write Data into DataRAM3)  
Add: 1st Word  
in sector4 of main of the page49  
DQ=XXF0h  
Do Cold reset  
Automatically  
updated  
Update Controller  
Status Register  
Add: F240h  
DQ[5]=1(OTPBL)  
DQ[6]=1(OTPL)  
OTP and 1st Block OTP lock completed  
* DBS, DFS is for DDP  
NOTE :  
1) FBA(NAND Flash Block Address) could be omitted or any address.  
2) ‘Write 0 to interrupt register’ step may be ignored when using INT auto mode. Refer to chapter 2.8.18.1  
3) Data input could be done anywhere between "Start" and "Write Program Command".  
4) FBA must be 0000.  
5) FSA msut be 00 within program operation. The 0196h is the page49 of NAND Flash Array address map.  
6) BSA msut be 1000 and BSC must be 000.  
- 102 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
3.14 DQ6 Toggle Bit  
The Flex-MuxOneNAND device has DQ6 Toggle bit. Toggle bit is another option to detect whether an internal load operation is in progress or  
completed. Once the BufferRAM(BootRAM, DataRAM0, DataRAM1) is at a busy state during internal load operation, DQ6 will toggle. Toggling  
DQ6 will stop after the device completes its internal load operation. The Flex-MuxOneNAND device’s DQ6 Toggle will be valid only when host  
reads BufferRAM which will be loaded by internal load operation. DQ6 toggle can be used 350ns after load command(0000h of Command  
based Operation) issue, until data sensing from the NAND Flash Array memory into Page Buffer and transferring from the Page Buffer to the  
DataRAM are finished. By reading the same address more than twice utilizing asynchronous read (Figure 6.20, 6.21), the host will read tog-  
gled value of DQ6 and the rest of DQ’s are not guaranteed to be fixed value. DQ6 toggle is only for reading status of BufferRAM which is being  
loaded by internal operation, that is, BufferRAM.  
DQ6 toggle bit can be useful at Cold Reset to determine the ready/busy state of Flex-MuxOneNAND. Since INT pin is initially at High-Z state,  
when host needs to check the completion of boot code copy operation, the host cannot judge the ready/busy status of Flex-MuxOneNAND by  
INT pin. Therefore, by checking DQ6 toggle of BootRAM, the host should detect the completion of boot code copy.  
Status  
DQ15~DQ7  
DQ6  
DQ5~DQ0  
In Progress  
Data Loading  
X (Don’t Care)  
Toggle  
X (Don’t Care)  
- 103 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
3.15 ECC Operation  
The Flex-MuxOneNAND device has on-chip ECC with the capability of correcting up to 4-bit errors in the NAND Flash Array memory main and  
spare areas (512+16)B.  
As the device transfers data from a BufferRAM to the NAND Flash Array memory Page Buffer for Program Operation, the device initiates a  
background operation which generates an Error Correction Code (ECC).  
During a Load operation from the NAND Flash Array memory Page, the on-chip ECC engine generates a new ECC. The 'Load ECC result' is  
compared to the originally programmed ECC' thus detecting the number of errors. Up to 4-bit errors are corrected.  
ECC is updated by the device automatically. After a Load Operation, the Host can determine whether there was error by reading the 'ECC Sta-  
tus Register' (Refer to section 2.8.26~2.8.29).  
Error types are divided into 'no error', 'correctable error(1bit~4bit)', and 'uncorrectable error(more than 4bit)'.  
When the device reads the NAND Flash Array memory main and spare area data with an ECC operation, the device doesn't place the newly  
generated ECC for main and spare area into the buffer. Instead it places the ECC which was generated and written during the program oper-  
ation into the buffer.  
An ECC operation is also done during the Boot Loading operation.  
3.15.1 ECC Bypass Operation  
In an ECC bypass operation, the device does not generate ECC as a background operation.  
In a Program Operation the ECC code to NAND Flash Array memory spare area is not updated.  
During a Load operation, the on-chip ECC engine does not generate a new ECC internally. Also the ECC Status Registers are invalid. The  
error is not corrected and detected by itself, so that ECC bypass operation is not recommended for host.  
ECC bypass operation is set by the 9bit of System Configuration 1 Register (see section 2.8.19)  
ECC Code and ECC Result by ECC Operation  
Program operation  
Load operation  
Operation  
ECC Code Update to NAND  
Flash Array Spare Area  
ECC Code at BufferRAM Spare  
Area  
ECC Status & Result Update  
to Registers  
1bit~4bit  
Error  
Pre-written ECC code1) loaded  
Pre-written code1) loaded  
ECC operation  
ECC bypass  
Update  
Update  
Invalid  
Correct  
Not update  
Not correct  
NOTE :  
1) Pre-written ECC code : ECC code which is previously written to NAND Flash Spare Area in program operation.  
- 104 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
3.16 Invalid Block Operation  
Invalid blocks are defined as blocks in the device's NAND Flash Array memory that contain five or more invalid bits which cause status failure  
during Program and Erase operation.  
The information regarding the invalid block(s) is called the Invalid Block Information. Devices with invalid block(s) have the same quality level  
as devices with all valid blocks and have the same AC and DC characteristics.  
An invalid block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a  
select transistor.  
The system that adopts Flash memory must be able to mask out the invalid block(s) by software. The 1st block is always fully guaranteed to  
be a valid block by an internal ECC engine.  
Due to invalid marking, during load operation for indentifying invalid block, a load error may occur.  
3.16.1 Invalid Block Identification Table Operation  
A system must be able to recognize invalid block(s) based on the original invalid block information and create an invalid block table.  
Invalid blocks are identified by erasing all address locations in the NAND Flash Array memory except locations where the invalid block(s) infor-  
mation is written prior to shipping.  
An invalid block(s) status is defined by the 1st word in the spare area. Samsung makes sure that the first page in the block either SLC partition  
or MLC partition of every invalid block has non-FFFFh data at the 1st word of sector0 of pages 0 or 1 in the spare area.  
Since the invalid block information is also erasable in most cases, it is impossible to recover the information once it has been erased. Any  
intentional erase of the original invalid block information is prohibited.  
The following suggested flow chart can be used to create an Invalid Block Table.  
- 105 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
Invalid Block Table Creation Flow Chart  
Start  
Set Block Address = 0  
Increment Block Address  
Check "FFFFh" at the 1st word of sector 0  
of spare area in the first page in the block  
either SLC partition or MLC partition  
*
No  
No  
Check  
Create (or update)  
Invalid Block(s) Table  
"FFFFh" ?  
Yes  
Last Block ?  
Yes  
End  
3.16.2 Invalid Block Replacement Operation  
Within its life time, additional invalid blocks may develop with NAND Flash Array memory. Refer to the device's qualification report for the  
actual data.  
The following possible failure modes should be considered to implement a highly reliable system.  
In the case of a status read failure after erase or program, a block replacement should be done. Program status failure  
during a page program does not affect the data of the other pages in the same block within a SLC partition, while Progrm status failure could  
contaminate the data of the paired page within a MLC partition. So, users must make sure how software handle the program failure occurrs.  
Block Failure Modes and Countermeasures  
Failure Mode  
Erase Failure  
Detection and Countermeasure sequence  
Status Read after Erase --> Block Replacement  
Status Read after Program --> Block Replacement  
Error Correction by ECC mode of the device  
Program Failure  
Four Bit Failure in Load Operation  
- 106 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
Referring to the diagram for further illustration, when an error happens in the nth page of block 'A' during program operation, copy  
the data in the 1st ~ (n-1)th page to the same location of block 'B' via DataRAM.  
Then re-program the nth page to the nth page of block 'B' or any free block.  
Do not further erase or program block 'A' but instead complete the operation by creating an 'Invalid Block Table' or other appropriate scheme.  
Block Replacement Operation Sequence  
Block A  
1st  
{
(n-1)th  
1
nth  
an error occurs.  
(page)  
Buffer memory of the controller.  
Block B  
1st  
2
{
(n-1)th  
nth  
(page)  
- 107 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
4.0 DC CHARACTERISTICS  
4.1 Absolute Maximum Ratings  
Parameter  
Voltage on any pin relative to VSS  
Symbol  
Rating  
Unit  
Vcc  
Vcc  
VIN  
-0.5 to + 2.45  
-0.5 to + 2.45  
-30 to +125  
-40 to +125  
-65 to +150  
5
V
All Pins  
Extended  
Industrial  
Temperature Under Bias  
Tbias  
°C  
Storage Temperature  
Tstg  
IOS  
°C  
Short Circuit Output Current  
mA  
TA (Extended Temp.)  
TA (Industrial Temp.)  
-30 to +85  
-40 to +85  
Recommended Operating Temperature  
°C  
NOTE :  
1) Minimum DC voltage is -0.5V on Input/ Output pins. During transitions, this level should not fall to POR level(typ. [email protected] device).  
Maximum DC voltage may overshoot to Vcc+2.0V for periods <20ns.  
2) Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions  
detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.  
4.2 Operating Conditions  
Voltage reference to GND  
KFM4GH6Q4M  
Parameter  
Symbol  
Unit  
Min  
1.7  
0
Typ.  
1.8  
0
Max  
1.95  
0
VCC-core / Vcc  
VCC- IO / Vccq  
VSS  
V
V
Supply Voltage  
NOTE :  
1) Vcc-Core (or Vcc) should reach the operating voltage level prior to or at the same time as Vcc-IO (or Vccq).  
- 108 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
4.3 DC Characteristics  
RMS Value  
Unit  
Parameter  
Input Leakage Current  
Output Leakage Current  
Symbol  
Test Conditions  
Min  
- 1.0  
- 2.0  
- 1.0  
- 2.0  
Typ  
Max  
+ 1.0  
+ 2.0  
+ 1.0  
+ 2.0  
Single  
DDP  
-
-
-
ILI  
VIN=VSS to VCC, VCC=VCCmax  
µA  
Single  
DDP  
VOUT=VSS to VCC, VCC=VCCmax,  
CE or OE=VIH(Note 1)  
ILO  
µA  
Active Asynchronous Read Current  
(Note 2)  
ICC1  
CE=VIL, OE=VIH  
-
8
15  
mA  
66MHz  
83MHz  
1MHz  
-
-
-
20  
25  
3
30  
35  
4
mA  
mA  
mA  
66MHz  
(DDP)  
-
-
-
22  
26  
3
35  
40  
4
mA  
mA  
mA  
Active Burst Read Current (Note 2)  
ICC2R  
CE=VIL, OE=VIH, WE=VIH  
83MHz  
(DDP)  
1MHz  
(DDP)  
66MHz  
83MHz  
1MHz  
-
-
-
20  
25  
3
30  
35  
4
mA  
mA  
mA  
66MHz  
(DDP)  
-
-
-
22  
26  
3
35  
40  
4
mA  
mA  
mA  
Active Burst Write Current (Note 2)  
ICC2W  
CE=VIL, OE=VIH, WE=VIL  
83MHz  
(DDP)  
1MHz  
(DDP)  
Single  
DDP  
-
8
15  
25  
mA  
mA  
mA  
mA  
mA  
Active Asynchronous Write Current  
(Note 2)  
ICC3  
CE=VIL, OE=VIH  
-
17  
50  
35  
40  
10  
20  
-
Active Load Current (Note 3)  
Active Program Current (Note 3)  
Active Erase Current (Note 3)  
ICC4  
ICC5  
ICC6  
CE=VIL, OE=VIH, WE=VIH  
CE=VIL, OE=VIH, WE=VIH  
CE=VIL, OE=VIH, WE=VIH  
-
65  
-
45  
-
50  
Single  
DDP  
-
-
50  
Standby Current  
ISB  
CE= RP=VCC ± 0.2V  
µA  
100  
0.4  
Input Low Voltage  
VIL  
VIH  
-
-
-0.5  
V
V
V
V
VCCq-  
0.4  
VCCq+0.  
4
Input High Voltage (Note 4)  
Output Low Voltage  
Output High Voltage  
-
-
-
VOL  
VOH  
IOL = 100 µA ,VCC=VCCmin , VCCq=VCCqmin  
-
0.2  
-
VCCq-  
0.1  
IOH = -100 µA , VCC=VCCmin , VCCq=VCCqmin  
NOTE :  
1) CE should be VIH for RDY. IOBE should be ‘0’ for INT.  
2) I active for Host access  
CC  
3) I active for Internal operation. (without host access)  
CC  
4) Vccq is equivalent to Vcc-IO  
- 109 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
5.0 AC CHARACTERISTICS  
5.1 AC Test Conditions  
Parameter  
Value (66MHz)  
0V to VCC  
3ns  
Value (83MHz)  
0V to VCC  
2ns  
Input Pulse Levels  
CLK  
Input Rise and Fall Times  
other inputs  
5ns  
2ns  
VCC/2  
VCC/2  
Input and Output Timing Levels  
Output Load  
CL = 30pF  
CL = 30pF  
Device  
Under  
Test  
VCC  
Input & Output  
VCC/2  
VCC/2  
Test Point  
* CL = 30pF including scope  
and Jig capacitance  
0V  
Input Pulse and Test Point  
Output Load  
5.2 Device Capacitance  
CAPACITANCE(TA = 25 °C, VCC = 1.8V, f = 1.0MHz)  
Single  
DDP  
QDP  
Unit  
Item  
Symbol  
Test Condition  
Min  
Max  
10  
Min  
Max  
20  
Min  
Max  
40  
Input Capacitance  
Control Pin Capacitance  
Output Capacitance  
INT Capacitance  
CIN1  
CIN2  
COUT  
CINT  
VIN=0V  
-
-
-
-
-
-
-
-
-
-
-
-
10  
20  
40  
VIN=0V  
VOUT=0V  
VOUT=0V  
pF  
10  
20  
40  
10  
20  
40  
NOTE :  
1) Capacitance is periodically sampled and not 100% tested.  
5.3 Valid Block Characteristics  
Parameter  
Symbol  
Min  
Typ.  
Max  
Unit  
Single  
998  
-
-
-
1024  
2048  
4096  
Valid Block Number  
DDP  
QDP  
NVB  
1996  
3993  
Blocks  
NOTE :  
1) The device may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with  
both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain five or more bad bits which cause status failure during Program and  
Erase operation. Do not erase or program factory-marked bad blocks.  
2) The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 4bit/528Byte ECC.  
- 110 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
5.4 AC Characteristics for Synchronous Burst Read  
See Timing Diagrams 6.1 and 6.2  
66MHz  
83MHz  
Parameter  
Symbol  
Unit  
Min  
1
Max  
Min  
1
Max  
Clock  
CLK  
tCLK  
tIAA  
66  
-
83  
-
MHz  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Clock Cycle  
Initial Access Time  
15  
-
12  
-
70  
11  
-
70  
9
Burst Access Time Valid Clock to Output Delay  
AVD Setup Time to CLK  
tBA  
-
-
tAVDS  
tAVDH  
tAVDO  
tACS  
tACH  
tBDH  
tOE  
5
4
-
AVD Hold Time from CLK  
2
-
2
-
AVD High to OE Low  
0
-
0
-
Address Setup Time to CLK  
Address Hold Time from CLK  
Data Hold Time from Next Clock Cycle  
Output Enable to Data  
5
-
4
-
6
-
6
-
3
-
2
-
-
20  
20  
-
20  
20  
1)  
CE Disable to Output & RDY High Z  
-
-
tCEZ  
1)  
OE Disable to Output High Z  
CE Setup Time to CLK  
CLK High or Low Time  
-
6
15  
-
-
4.5  
5
15  
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tOEZ  
tCES  
tCLKH/L  
tCLK/3  
-
-
CLK 2) to RDY valid  
CLK to RDY Setup Time  
RDY Setup Time to CLK  
CE low to RDY valid  
NOTE :  
tRDYO  
-
-
11  
11  
-
-
9
tRDYA  
tRDYS  
tCER  
-
9
4
-
3
-
15  
-
15  
1) If OE is disabled at the same time or before CE is disabled, the output will go to high-z by tOEZ.  
If CE is disabled at the same time or before OE is disabled, the output will go to high-z by tCEZ.  
If CE and OE are disabled at the same time, the output will go to high-z by tOEZ.  
2) It is the following clock of address fetch clock.  
- 111 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
5.5 AC Characteristics for Asynchronous Read  
See Timing Diagrams 6.3 and 6.4.  
KFM4GH6Q4M/  
KFN8GH6Q4M/  
KFKAGH6Q4M(TBD)  
Parameter  
Symbol  
Unit  
Min  
Max  
76  
76  
76  
-
Access Time from CE Low  
tCE  
tAA  
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Asynchronous Access Time from AVD Low  
Asynchronous Access Time from address valid  
Read Cycle Time  
tACC  
tRC  
-
76  
12  
5
6
-
AVD Low Time  
tAVDP  
tAAVDS  
tAAVDH  
tOE  
-
Address Setup to rising edge of AVD  
Address Hold from rising edge of AVD  
Output Enable to Output Valid  
CE Setup to AVD falling edge  
-
-
20  
-
tCA  
0
-
CE Disable to Output & RDY High Z1)  
tCEZ  
tOEZ  
20  
OE Disable to Output High Z1)  
AVD High to OE Low  
CE Low to RDY Valid  
WE Disable to AVD Enable  
Address to OE low  
-
0
15  
-
ns  
ns  
ns  
ns  
ns  
tAVDO  
tCER  
-
15  
-
tWEA  
15  
10  
2)  
-
tASO  
NOTE :  
1) If OE is disabled at the same time or before CE is disabled, the output will go to high-z by tOEZ.  
If CE is disabled at the same time or before OE is disabled, the output will go to high-z by tCEZ.  
If CE and OE are disabled at the same time, the output will go to high-z by tOEZ.  
These parameters are not 100% tested.  
2) This Parameter is valid at toggle bit timing in asynchronous read only. (timing diagram 6.20 and 6.21)  
5.6 AC Characteristics for Warm Reset (RP), Hot Reset and NAND Flash Core Reset  
See Timing Diagrams 6.16, 6.17 and 6.18.  
Parameter  
Symbol  
Min  
Max  
Unit  
tReady1  
(BufferRAM)  
RP & Reset Command Latch to BootRAM Access  
µs  
-
5
tReady2  
(NAND Flash Array)  
RP & Reset Command Latch(During Load Routines) to INT High (Note1)  
RP & Reset Command Latch(During Program Routines) to INT High (Note1)  
RP & Reset Command Latch(During Erase Routines) to INT High (Note1)  
RP & Reset Command Latch(NOT During Internal Routines) to INT High (Note1)  
-
-
-
10  
20  
µs  
µs  
µs  
tReady2  
(NAND Flash Array)  
tReady2  
(NAND Flash Array)  
150  
tReady2  
(NAND Flash Array)  
-
10  
-
µs  
tRP  
RP Pulse Width (Note2)  
200  
ns  
NOTE :  
1) These parameters are tested based on INT bit of interrupt register. Because the time on INT pin is related to the pull-up and pull-down resistor value.  
2) The device may reset if tRP < tRP min(200ns), but this is not guaranteed.  
- 112 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
5.7 AC Characteristics for Asynchronous Write  
See Timing Diagrams 6.5  
Parameter  
Symbol  
Min  
70  
12  
5
Max  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
WE Cycle Time  
tWC  
tAVDP  
tAAVDS  
tAAVDH  
tDS  
-
-
AVD low pulse width  
Address Setup Time  
Address Hold Time  
Data Setup Time  
-
6
-
30  
0
-
Data Hold Time  
tDH  
-
tCS  
0
-
CE Setup Time  
CE Hold Time  
tCH  
0
-
WE Pulse Width  
tWPL  
tWPH  
tWEA  
tCER  
tCEZ  
40  
30  
15  
-
-
WE Pulse Width High  
WE Disable to AVD Enable  
CE Low to RDY Valid  
-
-
15  
20  
CE Disable to Output & RDY High Z  
-
5.8 AC Characteristics for Burst Write Operation  
See Timing Diagrams 6.6, 6.7 and 6.8.  
66MHz  
83MHz  
Parameter  
Symbol  
Unit  
Min  
Max  
Min  
1
Max  
CLK1)  
Clock  
1
66  
83  
MHz  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Clock Cycle  
15  
-
12  
4
-
tCLK  
AVD Setup to CLK  
5
-
-
tAVDS  
tAVDH  
tACS  
AVD Hold Time from CLK  
Address Setup Time to CLK  
Address Hold Time from CLK  
Data Setup Time to CLK  
Data Hold Time from CLK  
WE Setup Time to CLK  
WE Hold Time from CLK  
CLK High or Low Time  
CE high pulse width  
2
-
2
-
5
-
4
-
6
-
6
-
tACH  
5
-
4
-
tWDS  
tWDH  
tWES  
tWEH  
tCLKH/L  
tCEHP  
tRDYO  
tRDYA  
tRDYS  
tCER  
2
-
2
-
5
-
4
-
6
-
6
-
tCLK/3  
-
5
-
10  
-
-
10  
-
-
CLK to RDY Valid  
11  
9
CLK to RDY Setup Time  
RDY Setup Time to CLK  
CE low to RDY valid  
-
11  
-
9
4
-
-
3
-
15  
-
15  
Clock to CE disable  
2
6
-
tCLK-4.5  
2
tCLK-4.5  
tCEH  
CE Setup Time to CLK  
CE Disable to Output & RDY High Z  
-
4.5  
-
-
tCES  
tCEZ  
20  
20  
NOTE :  
1)Target Clock frequency is 83Mhz  
- 113 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
5.9 AC Characteristics for Load/Program/Erase Performance  
See Timing Diagrams 6.9, 6.10, 6.11, 6.12, 6.13 and 6.14  
Parameter  
Symbol  
Min  
Typ  
25  
Max  
75  
Unit  
µs  
SLC  
-
Sector Load time(Note 1)  
Page Load time(Note 1)  
tRD1  
MLC  
SLC  
MLC  
SLC  
MLC  
30  
100  
400  
420  
770  
5000  
700  
700  
3
µs  
-
-
-
45  
µs  
tRD2  
50  
µs  
240  
1000  
500  
500  
2
µs  
Page Program time(Note 1)  
OTP Access Time(Note 1)  
tPGM2  
µs  
tOTP  
tLOCK  
tABU  
-
-
-
-
-
-
-
-
ns  
Lock/Unlock/Lock-tight(Note 1)  
All Block Unlock Time(Note 1)  
Erase Suspend Time(Note 1)  
Erase Resume Time(Note 1)  
ns  
µs  
tESP  
400  
0.5  
-
500  
11  
µs  
tERS1  
ms  
cycles  
cycles  
ms  
SLC  
MLC  
1
Number of Partial Program Cycles in the page (Including main and  
spare area)  
NOP  
-
1
Block Erase time (Note 1)  
tBERS1  
0.5  
11  
NOTE :  
1) These parameters are tested based on INT bit of interrupt register. Because the time on INT pin is related to the pull-up and pull-down resistor value.  
5.10 AC Characteristics for INT Auto Mode  
See Timing Diagram 6.22  
Parameter  
Symbol  
Min  
Max  
Unit  
Command Input to INT Low  
-
200  
ns  
tWB  
- 114 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
6.0 TIMING DIAGRAMS  
6.1 8-Word Linear Burst Read Mode with Wrap Around  
See AC Characteristics Table 5.4  
BRWL = 4  
tCLK  
tCES  
tCLKH  
tCLKL  
CE  
tCER  
tCEZ  
-1  
0
1
2
3
4
CLK  
AVD  
tRDYO  
tAVDS  
tAVDO  
tAVDH  
tBDH  
D2  
tBA  
tACS  
A/DQ0:  
A/DQ15  
D6  
D7  
D0  
D1  
D3  
D7  
D0  
tACH  
tOEZ  
tIAA  
tOE  
OE  
tRDYS  
Hi-Z  
tRDYA  
Hi-Z  
RDY  
6.2 Continuous Linear Burst Read Mode with Wrap Around  
See AC Characteristics Table 5.4  
BRWL = 4  
tCLK  
tCES  
CE  
tCER  
tCEZ  
CLK  
AVD  
tRDYO  
tAVDS  
tAVDO  
tAVDH  
tBDH  
tBA  
tACS  
A/DQ0:  
A/DQ15  
Da+1 Da+2 Da+3 Da+4 Da+5  
Da+n Da+n+1  
tOEZ  
Da  
tACH  
tIAA  
tOE  
OE  
tRDYS  
Hi-Z  
Hi-Z  
tRDYA  
RDY  
- 115 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
6.3 Asynchronous Read (VA Transition Before AVD Low)  
See AC Characteristics Table 5.5  
tRC  
CE  
tCER  
tOE  
OE  
tAVDO  
tCEZ  
tOEZ  
WE  
tCA  
tCE  
Hi-Z  
A/DQ0:  
A/DQ15  
VA  
Valid RD  
tAAVDH  
tAAVDS  
tWEA  
AVD  
RDY  
tAVDP  
tAA  
Hi-Z  
Hi-Z  
NOTE :  
VA=Valid Read Address, RD=Read Data.  
See timing diagram 6.20, 6.21 for tASO  
6.4 Asynchronous Read (VA Transition After AVD Low)  
See AC Characteristics Table 5.5  
tRC  
CE  
tCER  
tOE  
OE  
tCEZ  
tAVDO  
tCA  
WE  
tCE  
tOEZ  
Hi-Z  
Hi-Z  
A/DQ0:  
A/DQ15  
VA  
Valid RD  
tACC  
tAAVDH  
tAAVDS  
tWEA  
AVD  
RDY  
tAVDP  
Hi-Z  
NOTE :  
VA=Valid Read Address, RD=Read Data.  
See timing diagram 6.21, 6.22 for tASO  
- 116 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
6.5 Asynchronous Write  
See AC Characteristics Table 5.7  
VIL  
CLK  
tCS  
tCEZ  
tCH  
tWC  
CE  
tWPL  
tWPH  
WE  
OE  
tWEA  
tAAVDS tAAVDH  
RP  
AVD  
tAVDP  
ADQ15-ADQ0  
VA  
Valid WD  
tDS  
Valid WD  
VA  
tDH  
Hi-Z  
Hi-Z  
RDY  
tCER  
NOTE :  
VA=Valid Read Address, WD=Write Data.  
- 117 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
6.6 8-Word Linear Burst Write Mode  
See AC Characteristics Table 5.8  
BRWL = 4  
tCLK  
tCES  
tCLKH  
tCLKL  
tCEH  
CE  
tCER  
tCEZ  
-1  
0
1
2
3
4
CLK  
AVD  
tRDYO  
tAVDS  
tWDS  
D1  
tAVDH  
tWDH  
tACS  
tACH  
A/DQ0:  
A/DQ15  
D0  
D2  
D3  
D4  
D5  
D7  
OE  
tWES  
WE  
tWEH  
tRDYS  
Hi-Z  
tRDYA  
Hi-Z  
RDY  
6.7 Burst Write Operation followed by Burst Read  
See AC Characteristics Table 5.8  
BRWL = 4  
tCLK  
tCEHP  
tCER  
tCES  
tCES  
tCLKH  
tCLKL  
CE  
tCtER
-1  
0
1
2
3
4
CLK  
tRDYO  
tRDYO  
tAVDS  
tAVDS  
tWDS  
tWDH  
D1  
AVD  
tAVDH  
tAVDO  
tAVDH  
tBA  
D0  
tACS  
tACS  
tACH  
A/DQ0:  
A/DQ15  
D2  
D7  
D1  
D7  
tACH  
OE  
tWES  
tWEH  
WE  
tRDYS  
tRDYS  
Hi-Z  
tRDYA  
tRDYA  
Hi-Z  
RDY  
- 118 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
6.8 Start Initial Burst Write Operation  
See AC Characteristics Table 5.8  
BRWL = 4  
BRWL = 4  
tCEHP  
tCES  
tCLK  
tCLKH tCLKL  
tCEH  
CE  
tCER  
tCEZ  
-1  
0
1
2
3
4
CLK  
AVD  
tRDYO  
tAVDS  
tWDH  
D0  
tWDS  
tAVDH  
tACS  
tACH  
A/DQ0:  
A/DQ15  
D0  
OE  
tWES  
WE  
tWEH  
tRDYS  
tRDYA  
Hi-Z  
RDY  
- 119 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
6.9 Load Operation Timing  
See AC Characteristics Table 5.7 and Table 5.9  
Load Command Sequence (last two cycles)  
Read Data  
tAAVDS  
tWEA  
AVD  
tAVDP  
tAAVDH  
Da+n  
AA  
tCS  
LMA  
CA  
LCD  
SA  
Completed  
BA  
ADQ0~15  
CE  
tDS  
tDH  
tCER  
tCER  
tCH  
OE  
tWPL  
WE  
tWPH  
tRD1 or tRD2  
tWC  
VIL  
CLK  
INT  
bit  
tCEZ  
tCEZ  
Hi-Z  
RDY  
NOTE :  
1) AA = Address of address register  
CA = Address of command register  
LCD = Load Command  
LMA = Address of memory to be loaded  
BA = Address of BufferRAM to load the data  
SA = Address of status register  
2) “In progress” and “complete” refer to status register  
3) Status reads in this figure is asynchronous read, but status read in synchronous mode is also supported.  
- 120 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
6.10 Superload Operation Timing  
See AC Characteristics Table 5.7 and Table 5.9  
Superload Operation Timing Diagram  
- 121 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
6.11 Program Operation Timing  
See AC Characteristics Table 5.7 and Table 5.9  
Program Command Sequence (last two cycles)  
Read Status Data  
tAVDP  
tWEA  
AVD  
tAAVDS  
tAAVDH  
A/DQ0:  
A/DQ15  
In  
Completed  
AA  
PMA  
BA  
CA  
PCD  
SA  
SA  
BD  
Progress  
tDH  
tDS  
CE  
OE  
WE  
tCER  
tCH  
tWPL  
tWPH  
tCS  
tPGM1 or tPGM2  
tWC  
VIL  
CLK  
tCER  
INT  
bit  
tCEZ  
tCEZ  
Hi-Z  
RDY  
NOTE :  
1) AA = Address of address register  
CA = Address of command register  
PCD = Program Command  
PMA = Address of memory to be programmed  
BA = Address of BufferRAM to write the data  
BD = Program Data  
SA = Address of status register  
2) “In progress” and “complete” refer to status register  
3) Status reads in this figure is asynchronous read, but status read in synchronous mode is also supported.  
- 122 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
6.12 Cache Program Operation Timing  
See AC Characteristics Table 5.7 and Table 5.9  
- 123 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
6.13 Interleave Cache Program Operation Timing  
See AC Characteristics Table 5.7 and Table 5.9  
- 124 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
6.14 Block Erase Operation Timing  
See AC Characteristics Table 5.7 and Table 5.9  
Erase Command Sequence  
Read Status Data  
tAAVDS  
tWEA  
AVD  
tAVDP  
tAAVDH  
A/DQ0:  
In  
Completed  
AA  
tCS  
EMA  
CA  
ECD  
SA  
SA  
Progress  
A/DQ15  
tDS  
tDH  
CE  
tCER  
tCH  
OE  
tWPL  
tCER  
WE  
tWPH  
tBERS1  
tWC  
VIL  
CLK  
INT  
bit  
tCEZ  
tCEZ  
Hi-Z  
NOTE :  
1) AA = Address of address register  
CA = Address of command register  
ECD = Erase Command  
EMA = Address of memory to be erased  
SA = Address of status register  
2) For “In progress” and “complete” status, refer to status register.  
3) Status reads in this figure is asynchronous read, but status read in synchronous mode is also supported.  
- 125 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
6.15 Cold Reset Timing  
POR triggering level  
System Power  
1)  
Bootcode - copy done  
Idle  
OneNAND  
Operation  
Sleep  
Bootcode copy  
2)  
RP  
High-Z  
INT  
3)  
INT bit  
0 (default)  
1
IOBE bit  
0 (default)  
1 (default)  
1
INTpol bit  
NOTE :  
1) Bootcode copy operation starts 400us later than POR activation.  
The system power should reach Vcc after POR triggering level(typ. 1.5V) within 400us for valid boot code data.  
2) 1KB Bootcode copy and internal update operation take 250us(estimated) from sector0 and 1/page0/block0 of NAND Flash array to BootRAM.  
Host can read Bootcode in BootRAM(1K bytes) after Bootcode copy completion.  
3) INT register goes ‘Low’ to ‘High’ on the condition of ‘Bootcode-copy done’ and RP rising edge.  
If RP goes ‘Low’ to ‘High’ before ‘Bootcode-copy done’, INT register goes to ‘Low’ to ‘High’ as soon as ‘Bootcode-copy done’  
- 126 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
6.16 Warm Reset Timing  
See AC Characteristics Table 5.6  
CE, OE  
RP  
tRP  
tReady1  
High-Z  
High-Z  
RDY  
tReady2  
INT  
bit  
Operation  
Status  
1)  
2)  
3)  
4)  
1)  
Idle  
Reset Ongoing  
BootRAM Access  
INT Bit Polling  
Idle  
NOTE :  
1) The status which can accept any register based operation(Load, Program, Erase command, etc).  
2) The status where reset is ongoing.  
3) The status allows only BootRAM(BL1) read operation for Boot Sequence.(Refer to 7.2.2 Boot Sequence)  
4) To read BL2 of Boot Sequence, Host should wait INT until becomes ready. and then, Host can issue load command.  
(Refer to 7.2.2 Boot Sequence, 7.1 Methods of Determining Interrupt status)  
- 127 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
6.17 Hot Reset Timing  
See AC Characteristics Table 5.6  
AVD  
BP(Note 3)  
or F220h  
00F0h  
or 00F3h  
ADQi  
CE  
OE  
WE  
tReady2  
INT  
bit  
High-Z  
RDY  
Flex-MuxOneNAND  
Operation  
Idle  
Operation or Idle  
Flex-MuxOneNAND reset  
NOTE :  
1) Internal reset operation means that the device initializes internal registers and makes output signals go to default status and bufferRAM data are kept  
unchanged after Warm/Hot reset operations.  
2) Reset command : Command based reset or Register based reset.  
3) BP(Boot Partition): BootRAM area [0000h~01FFh, 8000h~800Fh]  
4) 00F0h for BP, and 00F3h for F220h  
- 128 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
6.18 NAND Flash Core Reset Timing  
See AC Characteristics Table 5.6  
AVD  
ADQi  
CE  
00F0h  
F220h  
OE  
WE  
tReady2  
INT  
bit  
High-Z  
RDY  
Flex-MuxOneNAND  
Operation  
Idle  
Operation or Idle  
NAND Flash Core reset  
6.19 Data Protection Timing During Power Down  
The device is designed to offer protection from any involuntary program/erase during power-transitions. RP pin provides hardware protection  
and is recommended to be kept at VIL before Vcc drops to 1.5V  
typ. 1.5V  
VCC  
0V  
RP  
INT  
Flex-MuxOneNAND  
Flex-MuxOneNAND Logic Reset & NAND Array Write Protected  
Operation  
- 129 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
6.20 Toggle Bit Timing in Asynchronous Read (VA Transition Before AVD Low)  
See AC Characteristics Table 5.5  
tRC  
CE  
tCER  
tOE  
OE  
tASO  
tAVDO  
tCEZ  
tOEZ  
WE  
tCA  
tCE  
Hi-Z  
A/DQ0:  
A/DQ15  
VA1)  
Status RD1)  
VA  
Status RD  
tAAVDS  
tAAVDH  
AVD  
tAVDP  
tAA  
Hi-Z  
RDY2)  
Hi-Z  
Note :  
NOTE :  
1) VA=Valid Read Address, RD=Read Data.  
2) Before IOBE is set to 1, RDY and INT pin are High-Z state.  
3) Refer to chapter 5.5 for tASO description and value.  
6.21 Toggle Bit Timing in Asynchronous Read (VA Transition After AVD Low)  
See AC Characteristics Table 5.5  
tRC  
CE  
tCER  
tOE  
OE  
tCEZ  
tASO  
tAVDO  
WE  
tCE  
tOEZ  
tCA  
tCA  
Hi-Z  
A/DQ0:  
A/DQ15  
VA1)  
VA  
Status RD1)  
Status RD  
tACC  
tAAVDH  
tAAVDS  
AVD  
tAVDP  
Hi-Z  
RDY2)  
Hi-Z  
NOTE :  
1) VA=Valid Read Address, RD=Read Data.  
2) Before IOBE is set to 1, RDY and INT pin are High-Z state.  
3) Refer to chapter 5.5 for tASO description and value.  
- 130 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
6.22 INT auto mode  
See AC Characteristics Table 5.10.  
tWB  
INT pin  
INT bit  
INT will automatically  
turn to Busy State  
Write command into  
Command Register  
INT will automatically turn back to ready state  
when designated operation is completed.  
WE  
. . .  
. . . . . . . . . .  
ADQ  
CMD  
NOTE :  
1) INT pin polarity is based on ‘IOBE=1 and INT pol=1 (default)’ setting  
- 131 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
7.0 TECHNICAL AND APPLICATION NOTES  
From time-to-time supplemental technical information and application notes pertaining to the design and operation of the device in a system  
are included in this section. Contact your Samsung Representative to determine if additional notes are available.  
7.1 Methods of Determining Interrupt Status  
There are two methods of determining Interrupt Status on the Flex-MuxOneNAND. Using the INT pin or monitoring the Interrupt Status Regis-  
ter Bit.  
The Flex-MuxOneNAND INT pin is an output pin function used to notify the Host when a command has been completed. This provides a hard-  
ware method of signaling the completion of a program, erase, or load operation.  
In its normal state, the INT pin is high if the INT polarity bit is default. In case of normal INT mode, before a command is written to the com-  
mand register, the INT bit must be written to ‘0’ for the INT pin transitions to a low state indicating start of the operation. In case of ‘INT auto  
mode’, INT bit is written to ‘0’ automatically right after command issued. Upon completion of the command operation by the Flex-Mux-  
OneNAND’s internal controller, INT returns to a high state.  
INT pin is a DQ-type output except ‘Reset’ and ‘Interleave Cache program’ in DDP allowing two INT outputs to be Or-tied together. In case of  
‘Reset’ and ‘Interleave Cache Program’ in DDP, INT pin operates as an open drain with 50K ohm. INT is an INT does not float to a hi-Z condi-  
tion when CE is disabled or OE is disabled. Refer to section 2.8 for additional information about INT.  
INT can be implemented by tying INT to a host GPIO or by continuous polling of the Interrupt status register.  
INT Type (Mono)  
INT Type (DDP)  
General Operation  
DQ type  
DQ type  
Reset Operation (Cold,Warm,Hot and Flash Core Reset) and  
final command of Interleave cache program  
DQ type  
Open drain (with 50K ohm)  
- 132 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
7.1.1 The INT Pin to a Host General Purpose I/O  
INT can be tied to a Host GPIO to detect the rising edge of INT, signaling the end of a command operation.  
COMMAND  
INT  
This can be configured to operate either synchronously or asynchronously as shown in the diagrams below.  
Synchronous Mode Using the INT Pin  
When operating synchronously, INT is tied directly to a Host GPIO. RDY could be connected as one of following guides.  
Host  
CE  
Flex-MuxOneNAND  
Host  
CE  
Flex-MuxOneNAND  
CE  
CE  
AVD  
CLK  
AVD  
CLK  
RDY  
OE  
AVD  
CLK  
AVD  
CLK  
RDY  
OE  
RDY(WAIT)  
OE  
OE  
GPIO  
INT  
GPIO  
INT  
Handshaking Mode  
Non-Handshaking Mode  
Asynchronous Mode Using the INT Pin  
When configured to operate in an asynchronous mode, CE, AVD and OE of the Flex-MuxOneNAND are tied to corresponding pins of the  
Host. CLK is tied to the Host Vss (Ground). RDY is tied to a no-connect. OE of the Flex-MuxOneNAND and Host are tied together and INT is  
tied to a GPIO.  
Host  
CE  
Flex-MuxOneNAND  
CE  
AVD  
Vss  
AVD  
CLK  
RDY  
OE  
OE  
GPIO  
INT  
- 133 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
7.1.2 Polling the Interrupt Register Status Bit  
An alternate method of determining the end of an operation is to continuously monitor the Interrupt Status Register Bit instead of using the INT  
pin.  
When using interrupt register instead of INT pin, INT must be unconnected  
.
Command  
INT  
This can be configured in either a synchronous mode or an asynchronous mode.  
Synchronous Mode Using Interrupt Status Register Bit Polling  
When operating synchronously, CE, AVD, CLK, RDY, OE, and DQ pins on the host and Flex-MuxOneNAND are tied together.  
RDY could be connected as one of following guides.  
Host  
CE  
Flex-MuxOneNAND  
Host  
CE  
Flex-MuxOneNAND  
CE  
CE  
AVD  
CLK  
AVD  
CLK  
RDY  
OE  
AVD  
CLK  
AVD  
CLK  
RDY  
OE  
RDY(WAIT)  
OE  
OE  
DQ  
DQ  
DQ  
DQ  
Handshaking Mode  
Non-Handshaking Mode  
Asynchronous Mode Using Interrupt Status Register Bit Polling  
When configured to operate in an asynchronous mode, CE, AVD, OE and DQ of the Flex-MuxOneNAND are tied to corresponding pins of the  
Host. CLK is tied to the Host Vss (Ground). RDY is NOT connected.  
Host  
CE  
Flex-MuxOneNAND  
CE  
AVD  
Vss  
AVD  
CLK  
RDY  
OE  
OE  
DQ  
DQ  
- 134 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
7.1.3 Determining Rp Value (DDP, QDP Only)  
For general operation, INT operates as normal output pin, so that tF is equivalent to tR (below 10ns). But since INT operates as open drain  
with 50K ohm for Reset (Cold/Hot/Warm/NAND Flash Core) operations and ‘Cache program operation’ case at DDP option, the pull-up resis-  
tor value is related to tr(INT). And appropriate value can be obtained with the following reference charts.  
INT pol = ‘High’ (Default)  
Vcc or Vccq  
Rp  
~50k ohm  
Ready Vcc  
INT  
VOH  
VOL  
Vss  
Busy State  
tf  
tr  
KFN8GH6Q4M @ Vcc = 1.8V, Ta = 25°C , CL = 30pF  
5.416  
3.952  
1.76  
3.485  
0.045  
Ibusy  
0.18  
2.912  
0.06  
0.09  
1.126  
2.192  
0.146  
0.036  
5.72  
tr[us]  
0.000  
5.98  
1K  
5.74  
10K  
5.73  
20K  
5.72  
5.72  
40K  
tf[ns]  
30K  
Open(100K)  
50K  
Rp(ohm)  
- 135 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
INT pol = ‘Low’  
Vcc or Vccq  
INT  
tf  
tr  
Ready  
Rp  
Vcc  
VOH  
Busy State  
~50k ohm  
Vss  
VOL  
KFN8GH6Q4M @ Vcc = 1.8V, Ta = 25°C , CL = 30pF  
4.129  
3.012  
1.76  
2.655  
0.045  
Ibusy  
0.18  
2.218  
0.06  
0.09  
0.959  
1.669  
0.111  
0.036  
6.92  
tf[us]  
0.000  
7.53  
1K  
6.73  
10K  
6.71  
20K  
6.74  
6.81  
40K  
tr[ns]  
30K  
Open(100K)  
50K  
Rp(ohm)  
- 136 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
7.2 Boot Sequence  
One of the best features Flex-MuxOneNAND has is that it can be a booting device itself since it contains an internally built-in boot loader  
despite the fact that its core architecture is based on NAND Flash. Thus, Flex-MuxOneNAND does not make any additional booting device  
necessary for a system, which imposes extra cost or area overhead on the overall system.  
As the system power is turned on, the boot code originally stored in the first block which is SLC area is moved to BootRAM automatically and  
then fetched by CPU through the same interface as SRAM’s or NOR Flash’s if the size of the boot code is less than 1KB. If its size is larger  
than 1KB and less than or equal to 3KB, only 1KB of it can be moved to BootRAM automatically and fetched by CPU, and the rest of it can be  
loaded into one of the DataRAMs whose size is 2KB by Load Command and CPU can take it from the DataRAM after finishing the code-fetch-  
ing job for BootRAM. If its size is larger than 3KB, the 1KB portion of it can be moved to BootRAM automatically and fetched by CPU, and its  
remaining part can be moved to DRAM through two DataRAMs and taken by CPU to reduce CPU fetch time.  
A typical boot scheme usually used to boot the system with Flex-MuxOneNAND is explained at Partition of NAND Flash Array and Flex-Mux-  
OneNAND Boot Sequence. In this boot scheme, boot code is comprised of BL1, where BL stands for Boot Loader, BL2, and BL3. Moreover,  
the size of the boot code is larger than 3KB (the 3rd case above). BL1 is called primary boot loader in other words. Here is the table of detailed  
explanations about the function of each boot loader in this specific boot scheme.  
7.2.1 Boot Loaders in Flex-MuxOneNAND  
Boot Loaders in Flex-MuxOneNAND  
Boot Loader  
BL1  
Description  
Moves BL2 from NAND Flash Array to DRAM through two DataRAMs  
Moves OS image (or BL3 optionally) from NAND Flash Array to DRAM through two DataRams  
Moves or writes the image through USB interface  
BL2  
BL3 (Optional)  
NAND Flash Array of Flex-MuxOneNAND is divided into the partitions as described at Partition of NAND Flash Array to show where each  
component of code is located and how much portion of the overall NAND Flash Array each one occupies. In addition, the boot sequence is  
listed below and depicted at Boot Sequence.  
7.2.2 Boot Sequence  
Boot Sequence :  
1. Power is on  
BL1 is loaded into BootRAM  
2. BL1 is executed in BootRAM  
BL2 is loaded into DRAM through two DataRams by BL1  
3. BL2 is executed in DRAM  
OS image is loaded into DRAM through two DataRams by BL2  
4. OS is running  
- 137 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
Block 1023  
Reservoir  
Partition 6  
Partition 5  
Sector5  
Sector6 Sector7  
Sector1 Sector2 Sector3 Sector4  
Sector0  
File System  
Page 63  
Page 62  
Block 162  
:
:
Os Image  
BL3
Partition 4  
Partition 3  
Block 2  
Block 1  
Block 0  
Page 2  
Page 1  
Page 0  
BL2  
BL1  
BL1  
Partition of NAND Flash array  
Reservoir  
File System  
step 3  
DataRam(4KB)  
Boot Ram(BL 1)  
Os Image  
Os Image  
BL 2  
BL1  
BL2  
step 2  
step 1  
NAND Flash Array  
Internal BufferRAM  
Flex-MuxOneNAND  
DRAM  
Flex-MuxOneNAND Boot Sequence  
NOTE : 1) Step 2 and Step 3 can be copied into DRAM through two DataRAMs.  
- 138 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
7.3 Partition of Flex-MuxOneNAND  
Flex-MuxOneNAND is the combo device which has SLC and MLC partition in one-chip. Generally, write intensive data require SLC-reliability  
but read and density oriented data such as music and movie satisfy with MLC-reliability. Therefore, some of the mobile phone is using both  
SLC-reliability memory and MLC-reliability memory to meet both requirements of reliability oriented and density oriented data using separate  
chip. but in case of Flex-MuxOneNAND, only one-chip of Flex-MuxOneNAND can meet the both requirement.  
And also, Flex-MuxOneNAND has internal Error Correction Circuit and common NOR interface. User can take full advantage of advances in  
NAND Flash memory capacity.  
(n-1) Block  
Last Block Address  
MLC Partition  
: {(k+1) ~ (n-1)} Blocks  
:
{
{
(K+1) Block  
k Block  
:
SLC Partition  
: {0 ~ K} Blocks  
2 Block  
1 Block  
{
First Block Address  
Data Register  
0 Block : SLC Array for Power Up  
NOTE :  
1) K is the boundary address(the end of SLC). Samsung will decide the value of K before final specification open (K=TBD).  
2) For the partitionning method, samsung will support application note and guidance code.  
- 139 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
7.4 DDP and QDP Description  
CHIP 1  
Comp  
DBS  
SRAM  
BUFFER  
Comp  
DFS  
FLASH  
CORE  
CE  
DDP_OPT  
GND  
INT  
CE  
INT  
CHIP 2  
VDD  
DDP_OPT  
INT  
CE  
SRAM  
DBS  
BUFFER  
Comp  
Comp  
DFS  
FLASH  
CORE  
DDP(Dual Die Package):  
8Gb DDP Flex-OneNAND contains two chips of 4Gb which are multiplexed such that they provide a single address range interface, with dou-  
ble the storage capacity.  
Since the address range is single, the BootRAM, the bufferRAM and the register set are multiplexed.  
BootRAM: The bootRAM of chip1 is selected always, and the contents of the block 0 of chip1 are copied to it at startup.  
DataRAM: DBS setting in Start Address2 Register(See Section 2.8.10) decides which DataRAM is selected.  
Register Set: In the case of write, both registers in chip1 and chip2 will be written(Regardless of DBS). Reading out from register of chip1/  
chip2 follows the DBS setting(See Section 2.8.10).  
QDP(Quad Die Package):  
A QDP is made up of 2 DDP chips and is effectively 2 separate Flex-OneNAND devices in the same die.  
There are 2 chip select pins (CE1 and CE2) on a QDP device, using which one of the two devices can be selected.  
Since there are separate chip-selects for the two devices, they have different address ranges and register sets which can be directly accessed  
by the processor.  
Thus each of the registers/BufferRAMs can be selected by using the CE pin, and then using the same settings that apply to a DDP chip.  
- 140 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
8.0 PACKAGE DIMENSIONS (TBD)  
#A1 INDEX  
A
10.00±0.10  
0.10 MAX  
10.00±0.10  
0.80x9=7.20  
(Datum A)  
B
6
5
4
3
2
1
#A1  
A
B
C
D
E
F
0.80  
(Datum B)  
G
H
3.60  
0.32±0.05  
0.9±0.10  
BOTTOM VIEW  
TOP VIEW  
63-  
0.45±0.05  
0.20  
M
A B  
4G product (KFM4GH6Q4M)  
#A1 INDEX  
A
10.00±0.10  
0.10 MAX  
(Datum A)  
10.00±0.10  
0.80x9=7.20  
B
6
5
4
3
2
1
#A1  
A
(Datum B)  
B
0.80  
C
D
E
F
G
H
3.60  
0.32±0.05  
1.1±0.10  
BOTTOM VIEW  
TOP VIEW  
63-  
0.45±0.05  
0.20  
M
A B  
8G product (KFN8GH6Q4M)  
- 141 -  
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)  
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)  
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)  
FLASH MEMORY  
#A1 INDEX  
A
10.00±0.10  
0.10 MAX  
10.00±0.10  
0.80x9=7.20  
(Datum A)  
B
6
5
4
3
2
1
#A1  
A
B
C
D
E
F
0.80  
(Datum B)  
G
H
3.60  
0.32±0.05  
1.3±0.10  
BOTTOM VIEW  
TOP VIEW  
63-  
0.45±0.05  
0.20  
M
A B  
16G product (KFKAGH6Q4M)  
- 142 -  

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