SMSC USB2250 User Manual

USB2250/50i/51/51i  
Ultra Fast USB 2.0 Multi-Slot  
Flash Media Controller  
Datasheet  
PRODUCT FEATURES  
GPIO configuration and polarity  
General Description  
The SMSC USB2250/50i/51/51i is a USB 2.0 compliant, high  
Up to 11 GPIOs (based on configuration) for special  
speed Mass Storage Class Peripheral Controller intended for  
reading and writing to more than 24 popular flash media  
formats from the CompactFlash® (CF), SmartMediaTM (SM), xD  
function use: LED indicators, button inputs, power  
control to memory devices, etc. The number of actual  
GPIO’s depends on the implementation configuration  
used.  
Four GPIO’s with up to 200 mA drive  
An additional 16 GPIO’s if CF is not used  
1
Picture CardTM (xD) , Memory StickTM (MS), Secure Digital  
(SD), and MultiMediaCardTM (MMC) families.  
On Board 24MHz Crystal Driver Circuit  
Optional external 24MHz clock input  
4 Independent Internal Card Power FET  
The SMSC USB2250/50i/51/51i is a fully integrated, single  
chip solution capable of ultra high performance operation.  
Average sustained transfer rates exceeding 35MB/s are  
possible if the media and host can support those rates.  
200mA each  
"Fold-back" short circuit current protected  
General Features  
8051 8-bit microprocessor  
128-pin VTQFP (14x14mm) lead-free RoHS compliant  
package  
60MHz - single cycle execution  
64KB ROM; 14KB RAM  
Targeted for applications in which single or "combo" media  
sockets are used  
Internal Regulator for 1.8V core operation  
Optimized pinout improves signal routing, easing  
implementation and allowing for improved signal integrity  
Supports multiple simultaneous card insertions  
Flexible assignment of number of LUNs and how card types  
are associated with the LUNs  
OEM Selectable Features  
Hardware-controlled data flow architecture for all self-  
mapped media  
Pipelined hardware support for access to non-self-  
mapped media  
Product name with “i” denotes the version that supports  
the industrial temperature range of -40ºC to 85ºC  
VID/PID/Language ID  
28-character Manufacturer ID and Product string  
12-hex digit (max) Serial Number string  
Customizable Vendor specific data by optional use of  
external serial EEPROM  
Bus- or Self-powered selection  
LED blink interval or duration  
Hardware Features  
Internal power FET configuration  
Single Chip Flash Media Controller with non-multiplexed  
interface for independent card sockets  
Software Features  
Flash Media Specification Revision Compliance  
Optimized for low latency interrupt handling  
Reduced memory footprint  
Device Firmware Upgrade (DFU) support of external  
EEPROM or External Flash  
Compact Flash Specification 4.1  
CF UDMA Modes 0-4  
CF PIO Modes 0-6  
Memory Stick Specification 1.43  
Memory Stick Pro Format Specification 1.02  
Memory Stick Pro-HG Duo Format Specification 1.01  
Assembly line support  
End user field upgrade support  
DFU Package consists of driver, firmware, sample DFU  
application and source code, DFU driver API  
Memory Stick, MS Duo, HS-MS, MS Pro-HG, MS Pro  
xD Picture Card 1.2  
Smart Media Specification 1.3  
Secure Digital 2.0  
Optional custom firmware with external ROM (up to 128k)  
Please see the USB2250/50i/51/51i Software Release  
Notes for additional Software Features.  
HS-SD, HC-SD, TransFlash™ and reduced form factor  
media  
Applications  
MultiMediaCard Specification 4.2  
Flash Media Card Reader/Writer  
Printers  
1/4/8 bit MMC  
SDIO and MMC Streaming Mode support  
Extended configuration options  
Desktop and Mobile PCs  
Consumer A/V  
Media Players/Viewers  
xD player mode operation  
Socket switch polarities, etc.  
TM  
Vista ReadyBoost  
Media Activity LED  
1.) xD Picture Card not applicable to USB2251.  
SMSC USB2250/50i/51/51i  
DATASHEET  
Revision 1.1 (05-29-08)  
Ultra Fast USB 2.0 Multi-Slot Flash Media Controller  
Datasheet  
Table of Contents  
SMSC USB2250/50i/51/51i  
3
Revision 1.1 (05-29-08)  
DATASHEET  
Ultra Fast USB 2.0 Multi-Slot Flash Media Controller  
Datasheet  
Chapter 1 Acronyms  
CF: Compact Flash  
CFC: Compact Flash Controller  
EEPROM: Electrically Erasable Programmable Read-Only Memory  
FET: Field Effect Transistor  
LUN: Logical Unit Number  
MMC: MultiMediaCard  
MS: Memory Stick  
MSC: Memory Stick Controller  
PLL: Phase-Locked Loop  
RoHS: Restriction of Hazardous Substances Directive  
SD: Secure Digital  
SDIO: Secure Digital Input/Output  
SDC: Secure Digital Controllerl  
SIE: Serial Interface Engine  
SM: SmartMedia  
SMC: SmartMedia Controller  
VTQFP: Very Thin Quad Flat Package  
xD: xD Picture Card  
*Note: In order to develop, make, use, or sell readers and/or other products using or incorporating any of the SMSC devices made  
the subject of this document or to use related SMSC software programs, technical information and licenses under patent and other  
intellectual property rights from or through various persons or entities, including without limitation media standard companies,  
forums, and associations, and other patent holders may be required. These media standard companies, forums, and associations  
include without limitation the following: Sony Corporation (Memory Stick, Memory Stick Pro); SD3 LLC (Secure Digital); MultiMedia  
Card Association (MultiMediaCard); the SSFDC Forum (SmartMedia); the Compact Flash Association (Compact Flash); and Fuji  
Photo Film Co., Ltd., Olympus Optical Co., Ltd., and Toshiba Corporation (xD-Picture Card). SMSC does not make such licenses  
or technical information available; does not promise or represent that any such licenses or technical information will actually be  
obtainable from or through the various persons or entities (including the media standard companies, forums, and associations), or  
with respect to the terms under which they may be made available; and is not responsible for the accuracy or sufficiency of, or  
otherwise with respect to, any such technical information.  
SMSC's obligations (if any) under the Terms of Sale Agreement, or any other agreement with any customer, or otherwise, with  
respect to infringement, including without limitation any obligations to defend or settle claims, to reimburse for costs, or to pay  
damages, shall not apply to any of the devices made the subject of this document or any software programs related to any of such  
devices, or to any combinations involving any of them, with respect to infringement or claimed infringement of any existing or future  
patents related to solid state disk or other flash memory technology or applications ("Solid State Disk Patents"). By making any  
purchase of any of the devices made the subject of this document, the customer represents, warrants, and agrees that it has  
obtained all necessary licenses under then-existing Solid State Disk Patents for the manufacture, use and sale of solid state disk  
and other flash memory products and that the customer will timely obtain at no cost or expense to SMSC all necessary licenses  
under Solid State Disk Patents; that the manufacture and testing by or for SMSC of the units of any of the devices made the subject  
of this document which may be sold to the customer, and any sale by SMSC of such units to the customer, are valid exercises of  
the customer's rights and licenses under such Solid State Disk Patents; that SMSC shall have no obligation for royalties or otherwise  
under any Solid State Disk Patents by reason of any such manufacture, use, or sale of such units; and that SMSC shall have no  
obligation for any costs or expenses related to the customer's obtaining or having obtained rights or licenses under any Solid State  
Disk Patents.  
SMSC MAKES NO WARRANTIES, EXPRESS, IMPLIED, OR STATUTORY, IN REGARD TO INFRINGEMENT OR OTHER  
VIOLATION OF INTELLECTUAL PROPERTY RIGHTS. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES  
AGAINST INFRINGEMENT AND THE LIKE.  
No license is granted by SMSC expressly, by implication, by estoppel or otherwise, under any patent, trademark, copyright, mask  
work right, trade secret, or other intellectual property right.  
**To obtain this software program the appropriate SMSC Software License Agreement must be executed and in effect. Forms of  
these Software License Agreements may be obtained by contacting SMSC.  
Revision 1.1 (05-29-08)  
6
SMSC USB2250/50i/51/51i  
DATASHEET  
 
Ultra Fast USB 2.0 Multi-Slot Flash Media Controller  
Datasheet  
Chapter 2 Block Diagram  
SD/  
AUTO_  
CBW  
MMC  
PROC  
CF/  
GPIO (16)  
USB  
Host  
FMI  
SIE  
CTL  
BUS  
INTFC  
BUS  
INTFC  
FMDU  
CTL  
PHY  
MS  
SM  
EP0 TX  
EP0 RX  
BUS  
INTFC  
RAM  
4K  
total  
EP1 RX  
EP1 TX  
EP2 RX  
EP2 TX  
XDATA BRIDGE  
+ BUS ARBITER  
PWR_FET0  
PWR_FET1  
PWR_FET2  
PWR_FET3  
GPIO8/CARD_PWR0  
GPIO9/CARD_PWR1  
GPIO10/CARD_PWR2  
GPIO11/CARD_PWR3  
GPIOs  
11 pins  
RAM  
10KB  
ADDR  
MAP  
Program Memory I/O Bus  
ROM  
64KB*  
Clock  
Generation and  
Control  
SFR  
8051  
PROCESSOR  
RAM  
*ROM is not available in USB2259  
Figure 2.1 USB2250/50i/51/51i Block Diagram  
SMSC USB2250/50i/51/51i  
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Revision 1.1 (05-29-08)  
DATASHEET  
   
Ultra Fast USB 2.0 Multi-Slot Flash Media Controller  
Datasheet  
Chapter 3 Pin Table  
3.1  
128-Pin Package  
Table 3.1 USB2250/50i/51/51i 128-Pin VTQFP Package  
COMPACTFLASH INTERFACE (28 PINS)  
CF_D0/GPIO16  
CF_D4/GPIO20  
CF_D8/GPIO24  
CF_D12/GPIO28  
CF_nIOR  
CF_D1/GPIO17  
CF_D5/GPIO21  
CF_D9/GPIO25  
CF_D13/GPIO29  
CF_nIOW  
CF_D2/GPIO18  
CF_D6/GPIO22  
CF_D3/GPIO19  
CF_D7/GPIO23  
CF_D11/GPIO27  
CF_D15/GPIO31  
CF_nRESET  
CF_D10/GPIO26  
CF_D14/GPIO30  
CF_IRQ  
CF_IORDY  
CF_nCS0  
CF_DMACK/TXD/GPIO7  
GPIO13 (CF_nCD)  
CF_SA0  
CF_SA1  
CF_SA2  
CF_DMARQ/RXD/GPIO2  
SMARTMEDIA INTERFACE (17 PINS)  
SM_D0  
SM_D4  
SM_D1  
SM_D5  
SM_D2  
SM_D6  
SM_D3  
SM_D7  
SM_ALE  
SM_nWP  
SM_nWPS  
SM_CLE  
SM_nB/R  
SM_nRE  
SM_nCE  
SM_nWE  
GPIO14 (SM_nCD)  
MEMORY STICK INTERFACE (11 PINS)  
MS_BS  
MS_D1  
MS_D5  
MS_D0/MS_SDIO  
MS_D2  
MS_SCLK  
MS_D3  
GPIO12 (MS_INS)  
MS_D4  
MS_D6  
MS_D7  
SD/MMC INTERFACE (12 PINS)  
SD_CMD  
SD_D2  
SD_CLK  
SD_D3  
SD_D5  
SD_D0  
GPIO6 (SD_WP)  
SD_D6  
SD_D1  
GPIO15 (SD_nCD)  
SD_D7  
SD_D4  
USB INTERFACE (8 PINS)  
USB+  
USB-  
RBIAS  
VDD18PLL  
REG_EN  
VDDA33  
XTAL2  
XTAL1 (CLKIN)  
Revision 1.1 (05-29-08)  
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SMSC USB2250/50i/51/51i  
DATASHEET  
     
Ultra Fast USB 2.0 Multi-Slot Flash Media Controller  
Datasheet  
Table 3.1 USB2250/50i/51/51i 128-Pin VTQFP Package (continued)  
MEMORY/IO INTERFACE (28 PINS)  
MA0/CLK_SEL0  
MA4  
MA1/CLK_SEL1  
MA5  
MA2  
MA6  
MA3  
MA7  
MA8  
MA9  
MA10  
MA14  
MD1  
MA11  
MA15  
MD2  
MA12  
MA13  
MA16  
MD0  
MD3  
MD4  
MD5  
MD6  
MD7  
nMRD  
nMWR  
nMCE  
MISC (10 PINS)  
nRESET  
GPIO3 (VBUS_DET)  
GPIO8/CARD_PWR0  
TEST  
GPIO4 (SCL/xD_ID)  
GPIO9/CARD_PWR1  
GPIO5 (SDA)  
LED1 / GPIO1  
GPIO10/CARD_PWR2  
GPIO11/CARD_PWR3  
DIGITAL, POWER (14 PINS)  
(5) VDD33  
(1) VDD18  
(8) VSS  
TOTAL 128  
SMSC USB2250/50i/51/51i  
9
Revision 1.1 (05-29-08)  
DATASHEET  
Ultra Fast USB 2.0 Multi-Slot Flash Media Controller  
Datasheet  
Chapter 4 Pin Configuration  
97  
64  
MS_D6  
GPIO12 (MS_INS)  
nRESET  
CF_D5 / GPIO21  
CF_D12 / GPIO28  
CF_D4 / GPIO20  
CF_D11 / GPIO27  
CF_D3 / GPIO19  
GPIO13 (CF_nCD)  
GPIO14 (SM_nCD)  
SM_nB/R  
SM_nRE  
SM_nCE  
SM_CLE  
SM_ALE  
VSS  
VDD33  
VDD18  
SM_nWE  
SM_nWP  
SM_D0  
SM_D1  
SM_D2  
SM_D3  
SM_D4  
SM_D5  
SM_D6  
SM_D7  
SM_nWPS  
MD0  
98  
63  
99  
62  
MS_D3  
MS_D7  
MS_SCLK  
100  
61  
101  
60  
102  
59  
VSS  
TEST  
VDD33  
GPIO6 (SD_WP)  
103  
58  
104  
57  
105  
56  
106  
55  
MA7  
MA13  
MA6  
MA8  
MA5  
MA9  
MA4  
MA11  
107  
54  
108  
53  
SMSC  
USB225X  
109  
110  
111  
112  
113  
114  
115  
116  
117  
118  
119  
120  
121  
122  
123  
124  
125  
126  
127  
128  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
MA3  
nMRD  
MA2  
128 VTQFP  
CF_DMARQ / RXD / GPIO2  
GPIO4 (SCL/xD_ID)  
CF_DMACK / TXD / GPIO7  
LED1 / GPIO1  
GPIO3 (VBUS_DET)  
VSS  
(Top View)  
XTAL2  
XTAL1 (CLKIN)  
VDD18PLL  
MD1  
MD2  
MD3  
MD7  
VSS  
RBIAS  
VDDA33  
Figure 4.1 USB2250/50i/51/51i 128-Pin VTQFP Diagram  
Revision 1.1 (05-29-08)  
10  
SMSC USB2250/50i/51/51i  
DATASHEET  
   
Ultra Fast USB 2.0 Multi-Slot Flash Media Controller  
Datasheet  
Chapter 5 Pin Descriptions  
This section provides a detailed description of each signal. The signals are arranged in functional  
groups according to their associated interface.  
The “n” symbol in the signal name indicates that the active, or asserted, state occurs when the signal  
is at a low voltage level. When “n” is not present before the signal name, the signal is asserted at the  
high voltage level.  
The terms assertion and negation are used exclusively. This is done to avoid confusion when working  
with a mixture of “active low” and “active high” signals. The term assert, or assertion, indicates that a  
signal is active, independent of whether that level is represented by a high or low voltage. The term  
negate, or negation, indicates that a signal is inactive.  
5.1  
USB2250/50i/51/51i 128-Pin VTQFP Pin Descriptions  
Table 5.1 USB2250/50i/51/51i 128-Pin VTQFP Pin Descriptions  
128-PIN  
VTQFP  
BUFFER  
TYPE  
NAME  
SYMBOL  
DESCRIPTION  
COMPACT FLASH INTERFACE  
CF Chip Select 0  
CF_nCS0  
71  
O12  
This pin is the active low chip select 0 signal  
for the task file registers of the CF ATA  
device in True IDE mode.  
CF Register  
Address  
CF_SA[2:0]  
82  
83  
84  
I/O12  
These pins are the register select address  
bits for the CF ATA device.  
CF Interrupt  
CF_IRQ  
74  
IPD  
This is the active high interrupt request  
signal from the CF device.  
This pin has an internal weak pull-down  
resistor that can be controlled by:  
CF_INTF_EN bit of CFC_ATA_MODE_CTL.  
CF Data 15-8 /  
GPIO  
CF_D[15:8] /  
GPIO[31:24]  
70  
68  
66  
62  
60  
90  
89  
87  
I/O12PD  
CF_D[15:8]: The bi-directional data signals  
CF_D15 - CF_D8 in True IDE mode data  
transfer  
In True IDE Mode, all task file register  
operations occur on the CF_D[7:0], while  
data transfer occurs on CF_D[15:0].  
The bi-directional data signal has an internal  
weak pull-down resistor.  
I/O12  
GPIO[31:24]: These pins are GPIOs if the  
CF_INTF_EN bit of the CFC_ATA_MODE  
CTL is disabled and the EXTENDED_GPIO  
bit is set in UTIL_CONFIG1 is enabled.  
SMSC USB2250/50i/51/51i  
11  
Revision 1.1 (05-29-08)  
DATASHEET  
   
Ultra Fast USB 2.0 Multi-Slot Flash Media Controller  
Datasheet  
Table 5.1 USB2250/50i/51/51i 128-Pin VTQFP Pin Descriptions (continued)  
128-PIN  
VTQFP  
BUFFER  
TYPE  
NAME  
SYMBOL  
DESCRIPTION  
CF Data 7-0 /  
GPIO  
CF_D[7:0] /  
GPIO[23:16]  
69  
67  
63  
61  
59  
88  
86  
85  
I/O12PD  
CF_D[7:0]: The bi-directional data signals  
CF_D7 - CF_D0 in True IDE mode data  
transfer. In True IDE Mode, all of the task file  
register operations occur on the CF_D[7:0],  
while data transfer occurs on CF_D[15:0].  
The bi-directional data signal has an internal  
weak pull-down resistor.  
I/O12  
IPU  
GPIO[23:16]: These Pins are GPIOs if the  
CF_INTF_EN bit of the CFC_ATA_MODE  
CTL is disabled and the EXTENDED_GPIO  
bit set in UTIL_CONFIG1 is enabled.  
IO Ready  
CF_IORDY  
80  
This pin is the active high input signal for  
IORDY.  
This pin has an internal weak pull-up resistor  
that can be controlled by:  
CF_INTF_EN bit of CFC_ATA_MODE CTL.  
CF Card  
GPIO13  
(CF_nCD)  
58  
79  
I/O12  
O12  
O12  
O12  
I
This is a GPIO designated as the Compact  
Flash card detection pin.  
Detection1  
CF Hardware  
Reset  
CF_nRESET  
This pin is an active low hardware reset  
signal to the CF device.  
CF IO Read  
CF_nIOR  
72  
This pin is an active low read strobe signal  
for the CF device.  
CF IO Write  
Strobe  
CF_nIOW  
73  
This pin is an active low write strobe signal  
for the CF device.  
CF DMA request  
CF_DMARQ /  
RXD / GPIO2  
117  
CF_DMARQ: This pin is the DMA request  
from the device to the CF controller.  
RXD: The signal can be used as input to the  
RXD of UART in the device when the  
TXD_RXD_SEL bit in UTIL_CONFIG1  
register is cleared to "0".  
I/O12  
O12  
GPIO: This pin may be used either as input,  
edge sensitive interrupt input, or output.  
CF DMA  
acknowledge  
CF_DMACK/  
TXD / GPIO  
119  
CF_nDMACK: This pin is an active low dma  
acknowledge signal for the CF device.  
TXD: GPIO7 can be used as an output TXD  
of UART in the device, when the GPIO2/TXD  
bit in UTL_CONFIG register is set to "1".  
I/O12  
GPIO: This pin may be used either as input,  
edge sensitive interrupt input, or output.  
SMART MEDIA INTERFACE  
SM Write Protect  
SM_nWP  
47  
O12PD  
This pin is an active low write protect signal  
for the SM device.  
This pin has a weak pull-down resistor that  
is permanently enabled.  
Revision 1.1 (05-29-08)  
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SMSC USB2250/50i/51/51i  
DATASHEET  
Ultra Fast USB 2.0 Multi-Slot Flash Media Controller  
Datasheet  
Table 5.1 USB2250/50i/51/51i 128-Pin VTQFP Pin Descriptions (continued)  
128-PIN  
VTQFP  
BUFFER  
TYPE  
NAME  
SYMBOL  
DESCRIPTION  
SM Address  
Strobe  
SM_ALE  
52  
O12PD  
O12PD  
I/O12PD  
This pin is an active high Address Latch  
Enable signal for the SM device.  
This pin has a weak pull-down resistor that  
is permanently enabled.  
SM Command  
Strobe  
SM_CLE  
53  
This pin is an active high Command Latch  
Enable signal for the SM device.  
This pin has a weak pull-down resistor that  
is permanently enabled.  
SM Data 7-0  
SM_D[7:0]  
39  
40  
41  
42  
43  
44  
45  
46  
These pins are the bi-directional data signals  
SM_D7-SM_D0.  
The bi-directional data signal has an internal  
weak pull-down resistor.  
SM Read Enable  
SM_nRE  
SM_nWE  
SM_nWPS  
55  
48  
38  
O12PU  
O12PU  
IPU  
This pin is an active low read strobe signal  
for the SM device.  
When using the internal FET, this pin has an  
internal weak pull-up resistor that is tied to  
the output of the internal Power FET, and is  
controlled by the SM_PU bit of the  
SMC_CTL register.  
If an external FET is used (Internal FET is  
disabled), then the internal pull-up is not  
available (external pull-ups must be used).  
SM Write Enable  
This pin is an active low write strobe signal  
for SM device.  
When using the internal FET, this pin has an  
internal weak pull-up resistor that is tied to  
the output of the internal Power FET, and is  
controlled by the SM_PU bit of the  
SMC_CTL register.  
If an external FET is used (Internal FET is  
disabled), then the internal pull-up is not  
available (external pull-ups must be used).  
SM Write Protect  
Switch  
A write-protect seal is detected when this pin  
is low.  
This pin has an internal weak pull-up resistor  
that is controlled by the SM_INTF_EN bit of  
the SMC_MODE_CTL2 register.  
SMSC USB2250/50i/51/51i  
13  
Revision 1.1 (05-29-08)  
DATASHEET  
Ultra Fast USB 2.0 Multi-Slot Flash Media Controller  
Datasheet  
Table 5.1 USB2250/50i/51/51i 128-Pin VTQFP Pin Descriptions (continued)  
128-PIN  
VTQFP  
BUFFER  
TYPE  
NAME  
SYMBOL  
DESCRIPTION  
SM Busy or Data  
Ready  
SM_nB/R  
56  
54  
57  
IPU  
This pin is connected to the BSY/RDY pin of  
the SM device.  
When using the internal FET, this pin has an  
internal weak pull-up resistor that is tied to  
the output of the internal Power FET, and is  
controlled by the SM_PU bit of the  
SMC_CTL register.  
If an external FET is used (Internal FET is  
disabled), then the internal pull-up is not  
available (external pull-ups must be used).  
SM Chip Enable  
SM_nCE  
O12PU  
This pin is the active low chip enable signal  
to the SM device.  
When using the internal FET, this pin has an  
internal weak pull-up resistor that is tied to  
the output of the internal Power FET, and is  
controlled by the SM_PU bit of the  
SMC_CTL register.  
If an external FET is used (Internal FET is  
disabled), then the internal pull-up is not  
available (external pull-ups must be used).  
SM Card  
Detection GPIO  
GPIO14  
(SM_nCD)  
I/O12  
This is a GPIO designated as the Smart  
Media card detection pin.  
MEMORY STICK INTERFACE  
MS Bus State  
MS_BS  
91  
O12  
This pin is connected to the BS pin of the MS  
device.  
It is used to control the Bus States 0, 1, 2  
and 3 (BS0, BS1, BS2 and BS3) of the MS  
device.  
MS Card  
Insertion GPIO  
GPIO12  
(MS_INS)  
98  
IPU  
This is a GPIO designated as the Memory  
Stick card detection pin.  
MS System CLK  
MS_SCLK  
101  
O12  
This pin is an output clock signal to the MS  
device.  
The clock frequency is software configurable.  
MS System Data  
In/Out  
MS_D[7:1]  
100  
97  
93  
95  
99  
96  
92  
I/O12PD  
MS_D[7:0]: These pins are the bi-directional  
data signals for the MS device. MS_D2 and  
MS_D3 have weak pull-down resistors.  
MS_D1 has a pull down resistor if it is in  
parallel mode, otherwise it is disabled. In 4-  
or 8-bit parallel mode, there is a weak pull-  
down resistor on all MS_D7~0 signals. The  
resistors are controlled by MSC_SYSTEM_0,  
MSC_MODE_CTL and MSC_PRO_HG  
registers.  
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Table 5.1 USB2250/50i/51/51i 128-Pin VTQFP Pin Descriptions (continued)  
128-PIN  
VTQFP  
BUFFER  
TYPE  
NAME  
SYMBOL  
DESCRIPTION  
MS System Data  
In/Out  
MS_D0 /  
MS_SDIO  
94  
I/O12PD  
MS_D0: This pin is one of the bi-directional  
data signals for the MS device. In serial  
mode, the most significant bit (MSB) of each  
byte is transmitted first by either MSC or the  
MS device on MS_D0, MS_D0, MS_D2, and  
MS_D3 (which have weak pull-down  
resistors). MS_D1 has a pull-down resistor  
if it is in parallel mode; Otherwise, it is  
disabled. In 4- or 8-bit parallel mode, all  
MS_D7~0 signals have a weak pull-down  
resistor. The resistors are controlled by  
MSC_SYSTEM_0, MSC_MODE_CTL and  
MSC_PRO_HG registers.  
MS_SDIO: Serial Data Bus. Responsible for  
transfer direction and types of data change  
depending on the Bus State.  
SD / MMC INTERFACE  
SD Data 7-0  
SD_D[7:0]  
13  
11  
19  
21  
22  
23  
10  
12  
I/O12PU  
These are the bi-directional data signals  
SD_D0 - SD_D7.  
The bi-directional signals should have weak  
pull-up resistors. The register can be  
controlled by the SD_MMC_INTF_EN bit of  
SDC_MODE_CTL.  
SD Clock  
SD_CLK  
SD_CMD  
18  
O12  
This is an output clock signal to the SD/MMC  
device.  
The clock frequency is software configurable.  
SD Command  
20  
I/O12PU  
This is a bi-directional signal that connects to  
the CMD signal of the SD/MMC device.  
The bi-directional signal should have an  
internal weak pull-up resistor.  
The pull-up register can be controlled by:  
SD_MMC_INTF_EN bit of SDC_MODE CTL.  
SD Write  
GPIO6  
(SD_WP)  
105  
32  
I/O12  
I/O12  
This is a GPIO designated as the Secure  
Digital card mechanical write detect pin.  
Protected GPIO  
SD Card Detect  
GPIO  
GPIO15  
(SD_nCD)  
This is a GPIO designated as the Secure  
Digital card detection pin.  
USB INTERFACE  
USB Bus Data  
USB+  
USB-  
7
8
I/O-U  
These pins connect to the USB bus data  
signals.  
USB Transceiver  
Bias  
RBIAS  
127  
I-R  
A 12.0k, 1.0% resistor is attached from  
VSSA to this pin in order to set the  
transceiver's internal bias currents.  
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Table 5.1 USB2250/50i/51/51i 128-Pin VTQFP Pin Descriptions (continued)  
128-PIN  
VTQFP  
BUFFER  
TYPE  
NAME  
Crystal  
SYMBOL  
DESCRIPTION  
XTAL1  
124  
ICLKx  
24MHz Crystal or external clock input.  
Input/External  
Clock Input  
(CLKIN)  
XTAL: This pin can be connected to one  
terminal of the crystal or it can be connected  
to an external 24/48MHz clock when a  
crystal is not used.  
Note:  
The MA[1:0] pins will be sampled  
while nRESET is asserted, and the  
value will be latched upon nRESET  
negation. This will determine the  
clock source and value.  
Crystal Output  
XTAL2  
123  
OCLKx  
24MHz Crystal.  
This is the other terminal of the crystal, or it  
is left open when an external clock source is  
used to drive XTAL1(CLKIN). It may not be  
used to drive any external circuitry other than  
the crystal circuit.  
1.8V PLL Power  
VDD18PLL  
125  
128  
This pin is the 1.8V Power for the PLL.  
If the internal regulator is enabled, then this  
pin must have a 1.0μF (or greater) ±20%  
(ESR <0.1Ω) capacitor to VSS.  
3.3V Analog  
Power  
VDDA33  
MD[7:0]  
3.3V Analog Power  
MEMORY / IO INTERFACE  
Memory Data  
Bus  
33  
29  
30  
31  
34  
35  
36  
37  
I/O12  
These signals are used to transfer data  
between the internal CPU and the external  
program memory.  
Note:  
These pins have internal weak pull-  
up resistors that are controlled by  
the MD_PU_DIS bit of the  
PWR_MGMT_CTL1 register.  
Memory Address  
Bus  
MA16  
28  
O12  
O12  
These signals address memory locations  
within the external memory. MA16 is a bit  
generated by the ROM Mapper.  
Memory Address  
Bus  
MA[15:2]  
2
4
These signals address memory locations  
within the external memory.  
107  
1
113  
24  
111  
109  
106  
108  
110  
112  
114  
116  
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Table 5.1 USB2250/50i/51/51i 128-Pin VTQFP Pin Descriptions (continued)  
128-PIN  
VTQFP  
BUFFER  
TYPE  
NAME  
SYMBOL  
DESCRIPTION  
Memory Address  
Bus  
MA1[1:0] /  
CLK_  
SEL1[1:0]  
25  
27  
O12  
MA[1:0]: These signals address memory  
locations within the external memory.  
I/O12PD  
CLK_SEL[1:0]: During nRESET assertion,  
these pins will select the operating frequency  
of the external clock, and the corresponding  
weak pull-down resistors are enabled. When  
nRESET is negated, the value on these pins  
will be internal latched and these pins will  
revert to MA[1:0] functionality; the internal  
pull-downs will be disabled.  
CLK_SEL[1:0] = '00'. 24MHz  
CLK_SEL[1:0] = '01'. RESERVED  
CLK_SEL[1:0] = '10'. RESERVED  
CLK_SEL[1:0] = '11'. 48MHz  
Note:  
If the latched value is '1', then the  
corresponding MA pin is tri-stated  
when the chip is in the powerdown  
state.  
If the latched value is '0', then the  
corresponding MA pin will function identically  
to the MA[15:3] pins at all times (other than  
during nRESET assertion).  
Memory Write  
Strobe  
nMWR  
nMRD  
nMCE  
3
O12  
O12  
O12  
Program Memory Write; active low  
Program Memory Read; active low  
Program Memory Chip Enable; active low.  
Memory Read  
Strobe  
115  
26  
Memory Chip  
Enable  
This signal is asserted when any external  
access is being done by the processor.  
This signal is held to the logic 'high' while  
nRESET is asserted.  
MISC  
General Purpose  
I/O  
LED1 / GPIO1  
120  
121  
I/O12  
GPIO: This pin may be used either as input,  
edge sensitive interrupt input, or output.  
LED: In addition, as an output, the GPIO1  
can be used output controlled by the  
LED1_GPIO1 register.  
General Purpose  
I/O  
GPIO3  
(VBUS_DET)  
I/O12  
This pin may be used either as input, edge  
sensitive interrupt input, or output.  
This pin is not 5V tolerant. An external  
resistor divider must be used when  
connected to VBUS.  
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Table 5.1 USB2250/50i/51/51i 128-Pin VTQFP Pin Descriptions (continued)  
128-PIN  
VTQFP  
BUFFER  
TYPE  
NAME  
SYMBOL  
DESCRIPTION  
General Purpose  
I/O  
GPIO4  
(SCL/xD_ID)  
118  
I/O12  
O12  
GPIO: This pin may be used either as input,  
edge sensitive interrupt input, or output.  
SCL: This is the clock output when used with  
an external EEPROM.  
I/O12  
I/O12  
xD_ID: This is the xD card detection pin only  
applicable to the USB2250/USB2250i.  
General Purpose  
I/O  
GPIO5  
(SDA)  
5
This pin may be used either as input, edge  
sensitive interrupt input, or output.  
SDA: This is the data pin when used with an  
external serial EEPROM.  
General Purpose  
I/O  
GPIO8 /  
CRD_PWR0  
14  
78  
76  
I/O12  
I/O200  
I/O12  
GPIO: This pin may be used either as input,  
edge sensitive interrupt input, or output.  
CRD_PWR: Card Power drive of 3.3V @  
either 100mA or 200mA.  
General Purpose  
I/O  
GPIO9 /  
CRD_PWR1  
GPIO: This pin may be used either as input,  
edge sensitive interrupt input, or output.  
I/O200  
I/O12  
CRD_PWR: Card Power drive of 3.3V @  
either 100mA or 200mA.  
General Purpose  
I/O  
GPIO10 /  
CRD_PWR2  
GPIO: These pins may be used either as  
input, edge sensitive interrupt input, or  
output. It is a requirement that this is the  
only FET used to power SM devices. Failure  
to do this will violate SM voltage specification  
on SM device pins.  
I/O200  
I/O12  
CRD_PWR: Card Power drive of 3.3V @  
either 100mA or 200mA.  
General Purpose  
I/O  
GPIO11 /  
CRD_PWR3  
16  
GPIO: These pins may be used either as  
input, edge sensitive interrupt input, or  
output.  
I/O200  
IS  
CRD_PWR: Card Power drive of 3.3V @  
either 100mA or 200mA.  
RESET Input  
TEST Input  
nRESET  
TEST  
64  
103  
6
This active low signal is used by the system  
to reset the chip. The active low pulse should  
be at least 1μs wide.  
I
This signal is used for testing the chip. User  
should normally tie this pin low externally, if  
the test function is not used.  
Regulator  
Enable  
REG_EN  
IPU  
This signal is used to enable the internal  
1.8V regulator.  
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Table 5.1 USB2250/50i/51/51i 128-Pin VTQFP Pin Descriptions (continued)  
128-PIN  
VTQFP  
BUFFER  
TYPE  
NAME  
SYMBOL  
DESCRIPTION  
DIGITAL POWER, and GROUND  
1.8V Digital Core  
Power  
VDD18  
49  
All VDD18 pins must be connected together  
on the circuit board.  
+1.8V Core power. If the internal regulator is  
enabled, then this pin must have a 1.0μF (or  
greater) ±20% (ESR <0.1Ω) capacitor to  
VSS.  
3.3V Power &  
Voltage  
Regulator Input  
VDD33  
VSS  
15  
50  
65  
77  
104  
3.3V Power & Voltage Regulator Input  
Ground  
9
Ground Reference.  
17  
51  
75  
81  
102  
122  
126  
Notes:  
1. Hot-insertion capable card connectors are required for all flash media. It is required for the SD  
connector to have a Write Protect switch. This allows the chip to detect the MMC card.  
2. nMCE is normally asserted except when the 8051 is in standby mode.  
3. Refer to PWR_MGMT_CTL1 register for controlling pull-up / down resistors associated with the  
pins as well as the individual card control registers.  
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5.2  
Buffer Type Descriptions  
Table 5.2 USB2250/50i/51/51i Buffer Type Descriptions  
BUFFER  
DESCRIPTION  
I
Input.  
IPU  
IPD  
IS  
Input with internal weak pull-up resistor.  
Input with internal weak pull-down resistor.  
Input with Schmitt trigger.  
I/O12  
I/O200  
Input/Output buffer with 12mA sink and 12mA source.  
Input/Output buffer 12mA with FET disabled, 100/200mA source only when the FET is  
enabled.  
I/O12PD  
Input/Output buffer with 12mA sink and 12mA source with an internal weak pull-down  
resistor.  
I/O12PU  
O12  
Input/Output buffer with 12mA sink and 12mA source with a pull-up resistor.  
Output buffer with 12mA source.  
O12PU  
O12PD  
ICLKx  
OCLKx  
I/O-U  
Output buffer with 12mA sink and 12mA source, with a pull-up resistor.  
Output buffer with 12mA sink and 12mA source, with a pull-down resistor.  
XTAL clock input.  
XTAL clock output.  
Analog Input/Output as Defined in USB specification.  
RBIAS.  
I-R  
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Datasheet  
Chapter 6 Pin Reset State Table  
Hardware  
Firmware  
Initialization  
Operational  
Voltage  
Signal (v)  
RESET  
RESET  
VDD33  
Time  
(t)  
VSS  
Figure 6.1 Pin Reset States  
LEGEND  
yes  
--  
hardware enables function  
hardware disables function  
hardware disables output driver  
hardware enables pullup  
z
pu  
pd  
hardware enables pulldown  
hw  
hardware controls function, but state is protocol dependent  
firmware controls function through registers  
hardware supplies power through pin, applicable only to CARD_PWR pins  
hardware disables pad  
(fw)  
VDD  
none  
Figure 6.2 Legend for Pin Reset States Table  
SMSC USB2250/50i/51/51i  
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DATASHEET  
     
6.1  
128-Pin Reset States  
Figure 6.3 USB2250/50i/51/51i Pin Reset States  
Post-Reset State  
xD Mode  
Post-Reset State  
SD Mode  
Post-Reset State  
MS Mode  
RESET STATE  
OUT-  
PUT  
PU/  
PD  
IN-  
OUT-  
PUT  
PU/  
PD  
IN-  
OUT-  
PUT  
PU/  
IN-  
OUT-  
PUT  
PU/  
PD  
IN-  
PUT  
PIN  
85  
86  
88  
59  
61  
63  
67  
69  
87  
89  
90  
60  
62  
66  
68  
70  
72  
PIN NAME  
FUNCTION  
GPIO  
GPIO  
GPIO  
GPIO  
GPIO  
GPIO  
GPIO  
GPIO  
GPIO  
GPIO  
GPIO  
GPIO  
GPIO  
GPIO  
GPIO  
GPIO  
CF  
FUNCTION  
CF  
FUNCTION  
GPIO  
GPIO  
GPIO  
GPIO  
GPIO  
GPIO  
GPIO  
GPIO  
GPIO  
GPIO  
GPIO  
GPIO  
GPIO  
GPIO  
GPIO  
GPIO  
FUNCTION  
PUT  
PUT  
PD  
PUT  
CF_D0/GPIO16  
CF_D1/GPIO17  
CF_D2/GPIO18  
CF_D3/GPIO19  
CF_D4/GPIO20  
CF_D5/GPIO21  
CF_D6/GPIO22  
CF_D7/GPIO23  
CF_D8/GPIO24  
CF_D9/GPIO25  
CF_D10/GPIO26  
CF_D11/GPIO27  
CF_D12/GPIO28  
CF_D13/GPIO29  
CF_D14/GPIO30  
CF_D15/GPIO31  
CF_nIOR  
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
hw  
hw  
hw  
hw  
hw  
hw  
hw  
hw  
hw  
hw  
hw  
hw  
hw  
hw  
hw  
hw  
hw  
pd  
pd  
pd  
pd  
pd  
pd  
pd  
pd  
pd  
pd  
pd  
pd  
pd  
pd  
pd  
pd  
--  
hw  
hw  
hw  
hw  
hw  
hw  
hw  
hw  
hw  
hw  
hw  
hw  
hw  
hw  
hw  
hw  
--  
(fw)  
(fw)  
(fw)  
(fw)  
(fw)  
(fw)  
(fw)  
(fw)  
(fw)  
(fw)  
(fw)  
(fw)  
(fw)  
(fw)  
(fw)  
(fw)  
(fw)  
(fw)  
(fw)  
(fw)  
(fw)  
(fw)  
(fw)  
(fw)  
(fw)  
(fw)  
(fw)  
(fw)  
(fw)  
(fw)  
(fw)  
(fw)  
(fw)  
CF  
(fw)  
(fw)  
(fw)  
(fw)  
(fw)  
(fw)  
(fw)  
(fw)  
(fw)  
(fw)  
(fw)  
(fw)  
(fw)  
(fw)  
(fw)  
CF  
CF  
CF  
CF  
CF  
CF  
CF  
CF  
CF  
CF  
CF  
CF  
CF  
CF  
z
z
--  
--  
--  
--  
CF  
   
Post-Reset State  
xD Mode  
Post-Reset State  
SD Mode  
Post-Reset State  
MS Mode  
RESET STATE  
OUT-  
PUT  
PU/  
PD  
IN-  
OUT-  
PUT  
PU/  
IN-  
OUT-  
PUT  
PU/  
IN-  
OUT-  
PUT  
PU/  
IN-  
PIN  
73  
74  
79  
80  
71  
84  
83  
82  
119  
117  
58  
46  
45  
44  
43  
42  
41  
40  
39  
PIN NAME  
CF_nIOW  
FUNCTION  
CF  
FUNCTION  
CF  
FUNCTION  
FUNCTION  
PUT  
PD  
PUT  
PD  
PUT  
PD  
PUT  
--  
z
z
z
z
z
z
z
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
hw  
z
--  
CF_nIRQ  
CF  
CF  
pd  
--  
yes  
--  
CF_nRESET  
CF_IORDY  
CF_nCS0  
CF  
CF  
(fw)  
z
CF  
CF  
pu  
(fw)  
--  
yes  
CF  
CF  
hw  
hw  
hw  
hw  
hw  
z
--  
--  
CF_SA0  
CF  
CF  
CF_SA1  
CF  
CF  
--  
--  
CF_SA2  
CF  
CF  
--  
--  
z
0
0
z
z
z
z
z
z
z
z
z
--  
--  
--  
--  
CF_DMACK/TXD/GPIO7  
CF_DMARQ/RXD/GPIO2  
GPIO13(CF_nCD)  
SM_D0  
GPIO  
GPIO  
GPIO  
SM  
CF  
--  
--  
GPIO  
GPIO  
(fw)  
(fw)  
(fw)  
(fw)  
(fw)  
(fw)  
TXD  
RXD  
hw  
z
--  
--  
yes  
CF  
pd  
(fw)  
pd  
pd  
pd  
pd  
pd  
pd  
pd  
pd  
yes  
(fw)  
yes  
yes  
yes  
yes  
yes  
yes  
yes  
yes  
(fw)  
--  
--  
GPIO  
SM  
SM  
SM  
SM  
SM  
SM  
SM  
SM  
(fw)  
hw  
hw  
hw  
hw  
hw  
hw  
hw  
hw  
pu  
pd  
pd  
pd  
pd  
pd  
pd  
pd  
pd  
yes  
--  
SM_D1  
SM  
--  
SM_D2  
SM  
--  
SM_D3  
SM  
--  
SM_D4  
SM  
--  
SM_D5  
SM  
--  
SM_D6  
SM  
--  
SM_D7  
SM  
--  
Post-Reset State  
xD Mode  
Post-Reset State  
SD Mode  
Post-Reset State  
MS Mode  
RESET STATE  
OUT-  
PUT  
PU/  
PD  
IN-  
OUT-  
PUT  
PU/  
IN-  
OUT-  
PUT  
PU/  
PD  
IN-  
PUT  
OUT-  
PUT  
PU/  
PD  
IN-  
PUT  
PIN  
52  
53  
47  
38  
57  
91  
101  
94  
92  
96  
99  
95  
93  
97  
100  
98  
20  
18  
12  
PIN NAME  
SM_ALE  
FUNCTION  
SM  
FUNCTION  
SM  
FUNCTION  
FUNCTION  
PUT  
PD  
PUT  
hw  
hw  
(fw)  
z
pd  
--  
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
pd  
pd  
pd  
--  
--  
--  
SM_CLE  
SM  
SM  
pd  
pd  
--  
SM_nWP  
SM_nWPS  
GPIO14(SM_nCD)  
MS_BS  
SM  
SM  
--  
--  
SM  
SM  
pu  
yes  
(fw)  
--  
--  
GPIO  
MS  
GPIO  
MS  
(fw)  
hw  
hw  
hw  
hw  
hw  
hw  
hw  
hw  
hw  
hw  
(fw)  
hw  
hw  
hw  
(fw)  
hw  
hw  
pd  
pu  
pd  
pd  
pd  
pd  
pd  
pd  
pd  
pd  
pd  
pd  
pu  
--  
yes  
--  
MS_SCLK  
MS_D0/MS_SDIO  
MS_D1  
MS  
MS  
--  
--  
MS  
MS  
yes  
yes  
yes  
yes  
yes  
yes  
yes  
yes  
(fw)  
yes  
yes  
yes  
--  
MS  
MS  
hw  
pd  
--  
MS_D2  
MS  
MS  
--  
MS_D3  
MS  
MS  
pd  
--  
MS_D4  
MS  
MS  
pd  
--  
MS_D5  
MS  
MS  
hw  
pd  
--  
MS_D6  
MS  
MS  
--  
MS_D7  
MS  
MS  
pd  
--  
GPIO12(MS_INS)  
SD_CMD  
SD_CLK  
GPIO  
SD  
GPIO  
SD  
(fw)  
yes  
--  
pu  
SD  
SD  
--  
--  
--  
SD_D0  
SD  
SD  
pu  
--  
--  
Post-Reset State  
xD Mode  
Post-Reset State  
SD Mode  
Post-Reset State  
MS Mode  
RESET STATE  
OUT-  
PUT  
PU/  
PD  
IN-  
OUT-  
PUT  
PU/  
IN-  
OUT-  
PUT  
PU/  
PD  
IN-  
PUT  
OUT-  
PUT  
PU/  
PD  
IN-  
PUT  
PIN  
10  
PIN NAME  
SD_D1  
FUNCTION  
SD  
FUNCTION  
SD  
FUNCTION  
FUNCTION  
PUT  
PD  
PUT  
hw  
hw  
hw  
hw  
hw  
hw  
hw  
(fw)  
(fw)  
hw  
hw  
hw  
hw  
hw  
hw  
hw  
hw  
hw  
hw  
pu  
yes  
yes  
yes  
yes  
yes  
yes  
yes  
(fw)  
(fw)  
z
z
z
z
z
z
z
0
z
z
z
z
z
0
0
0
0
0
0
--  
--  
--  
--  
23  
SD_D2  
SD  
SD  
pu  
pu  
22  
SD_D3  
SD  
SD  
--  
--  
21  
SD_D4  
SD  
SD  
pu  
--  
--  
19  
SD_D5  
SD  
SD  
pu  
--  
--  
11  
SD_D6  
SD  
SD  
pu  
--  
--  
13  
SD_D7  
SD  
SD  
pu  
--  
--  
105  
32  
GPIO6(SD_WP)  
GPIO15(SD_nCD)  
MA0/CLK_SEL0  
MA1/CLK_SEL1  
MA2  
GPIO  
GPIO  
MA  
GPIO  
GPIO  
MA  
(fw)  
(fw)  
--  
--  
pu  
pd  
pd  
pd  
pd  
--  
yes  
yes  
yes  
yes  
yes  
--  
27  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
25  
MA  
MA  
116  
114  
112  
110  
108  
106  
109  
111  
MA  
MA  
MA3  
MA  
MA  
MA4  
MA  
MA  
MA5  
MA  
MA  
--  
--  
MA6  
MA  
MA  
--  
--  
MA7  
MA  
MA  
--  
--  
MA8  
MA  
MA  
--  
--  
MA9  
MA  
MA  
--  
--  
Post-Reset State  
xD Mode  
Post-Reset State  
SD Mode  
Post-Reset State  
MS Mode  
RESET STATE  
OUT-  
PUT  
PU/  
PD  
IN-  
OUT-  
PUT  
PU/  
IN-  
OUT-  
PUT  
PU/  
IN-  
OUT-  
PUT  
PU/  
PD  
IN-  
PUT  
PIN  
24  
PIN NAME  
FUNCTION  
MA  
FUNCTION  
MA  
FUNCTION  
FUNCTION  
PUT  
PD  
PUT  
PD  
PUT  
MA10  
hw  
hw  
hw  
hw  
hw  
hw  
hw  
hw  
hw  
hw  
hw  
hw  
hw  
0
0
0
0
z
z
z
z
z
z
z
z
1
1
0
0
z
z
z
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
113  
107  
28  
MA11  
MA  
MA  
--  
--  
MA13  
MA  
MA  
--  
MA16  
MA  
MA  
--  
--  
--  
37  
MD0  
MA  
MA  
hw  
hw  
pu  
pu  
pu  
pu  
pu  
pu  
pu  
pu  
--  
36  
MD1  
MA  
MA  
hw  
hw  
hw  
hw  
hw  
hw  
hw  
--  
hw  
hw  
hw  
hw  
hw  
hw  
hw  
--  
35  
MD2  
MD3  
MA  
MA  
34  
MA  
MA  
31  
MD4  
MA  
MA  
30  
MD5  
MA  
MA  
29  
MD6  
MA  
MA  
33  
MD7  
MA  
MA  
115  
26  
nMRD  
MA  
MA  
nMCE  
MA  
MA  
--  
0
--  
--  
120  
118  
14  
LED1 / GPIO1  
GPIO4 (SCL/xD_ID)  
GPIO8/CARD_PWR0  
GPIO9/CARD_PWR1  
GPIO10/CARD_PWR2  
GPIO  
GPIO  
GPIO  
GPIO  
GPIO  
GPIO  
GPIO  
GPIO  
GPIO  
GPIO  
(fw)  
(fw)  
(fw)  
--  
(fw)  
(fw)  
(fw)  
(fw)  
(fw)  
(fw)  
(fw)  
(fw)  
(fw)  
(fw)  
(fw)  
(fw)  
--  
PWR  
PWR  
PWR  
VDD  
VDD  
VDD  
--  
--  
--  
--  
--  
--  
--  
78  
--  
76  
--  
Post-Reset State  
xD Mode  
Post-Reset State  
SD Mode  
Post-Reset State  
MS Mode  
RESET STATE  
OUT-  
PUT  
PU/  
PD  
IN-  
OUT-  
PUT  
PU/  
IN-  
OUT-  
PUT  
PU/  
IN-  
OUT-  
PUT  
PU/  
PD  
IN-  
PUT  
PIN  
16  
103  
64  
1
PIN NAME  
GPIO11/CARD_PWR3  
TEST  
FUNCTION  
GPIO  
TEST  
nRESET  
MA  
FUNCTION  
GPIO  
TEST  
nRESET  
MA  
FUNCTION  
FUNCTION  
PUT  
PD  
PUT  
PD  
PUT  
(fw)  
z
(fw)  
(fw)  
yes  
PWR  
VDD  
--  
--  
z
z
z
0
0
0
1
z
0
z
z
z
z
z
z
--  
--  
--  
--  
--  
--  
--  
--  
pu  
--  
--  
--  
--  
--  
--  
--  
yes  
yes  
--  
--  
nRESET  
z
--  
--  
yes  
--  
MA12  
hw  
4
MA14  
MA  
MA  
hw  
hw  
hw  
(fw)  
(fw)  
hw  
hw  
z
--  
--  
--  
--  
2
MA15  
MA  
MA  
--  
--  
3
nMWR  
MA  
MA  
--  
--  
--  
121  
5
GPIO3 (VBUS_DET)  
GPIO5 (SDA)  
SM_nRE  
GPIO  
GPIO  
SM  
GPIO  
GPIO  
SM  
(fw)  
(fw)  
(fw)  
(fw)  
(fw)  
(fw)  
hw  
hw  
(fw)  
(fw)  
--  
yes  
--  
55  
48  
56  
54  
7
--  
SM_nWE  
SM_nB/R  
SM_nCE  
SM  
SM  
--  
--  
SM  
SM  
yes  
--  
--  
SM  
SM  
hw  
z
--  
USB+  
USB+  
USB-  
USB+  
USB-  
hw  
hw  
--  
8
USB-  
z
--  
127  
124  
123  
6
RBIAS  
XTAL1(CLKIN)  
XTAL2  
REG_EN  
Ultra Fast USB 2.0 Multi-Slot Flash Media Controller  
Datasheet  
Chapter 7 DC Parameters  
7.1  
Maximum Guaranteed Ratings  
PARAMETER  
SYMBOL  
MIN  
MAX  
UNITS  
°C  
COMMENTS  
Storage  
Temperature  
T
-55  
150  
325  
4.0  
A
Lead  
Temperature  
°C  
V
Soldering < 10 seconds  
3.3V supply  
voltage  
V
V
-0.5  
-0.5  
DD33,  
DDA33  
Voltage on  
USB+ and  
USB- pins  
(3.3V supply voltage + 2) 6  
V
Voltage on  
GPIO8, 9, 10  
& 11  
-0.5  
V
+ 0.3  
V
When internal power FET  
operation of these pins are  
enabled, these pins may be  
simultaneously shorted to  
ground or any voltage up to  
3.63V indefinitely, without  
damage to the device as long  
DD33  
as V  
and V  
are less  
DD33  
DDA33  
than 3.63V and T is less than  
A
o
70 C.  
Voltage on any  
signal pin  
-0.5  
-0.5  
-0.5  
V
+ 0.3  
+ 0.3  
V
V
V
DD33  
Voltage on  
XTAL1  
4.0  
Voltage on  
XTAL2  
V
DD18  
Note 7.1 Stresses above the specified parameters may cause permanent damage to the device.  
This is a stress rating only and functional operation of the device at any condition above  
those indicated in the operation sections of this specification is not implied.  
Note 7.2 When powering this device from laboratory or system power supplies, it is important that  
the Absolute Maximum Ratings not be exceeded or device failure can result. Some power  
supplies exhibit voltage spikes on their outputs when the AC power is switched on or off.  
In addition, voltage transients on the AC power line may appear on the DC output. When  
this possibility exists, it is suggested that a clamp circuit be used.  
Revision 1.1 (05-29-08)  
28  
SMSC USB2250/50i/51/51i  
DATASHEET  
   
Ultra Fast USB 2.0 Multi-Slot Flash Media Controller  
Datasheet  
Voltage  
VDD33  
tRT  
3.3V  
100%  
90%  
10%  
VSS  
t90%  
Time  
t10%  
Figure 7.1 Supply Rise Time Model  
Note 7.3 When powering the device, the maximum power supply ramp time should be set at a rate  
faster than 400μs. This speed is important to ensure that the device resets properly.  
Measure rise time at 10% and 90%.  
7.2  
Recommended Operating Conditions  
PARAMETER  
SYMBOL  
MIN  
MAX  
UNITS  
COMMENTS  
Operating  
Temperature  
Commercial Part  
Industrial Part  
T
0
70  
85  
3.6  
°C  
°C  
V
A
T
-40  
3.0  
A
3.3V supply voltage  
V
V
DD33,  
DDA33  
3.3V supply rise time  
t
0
400  
5.5  
μs  
(See Figure 7.1 and Note 7.3)  
RT  
Voltage on  
USB+ and USB- pins  
-0.3  
V
If any 3.3V supply voltage drops  
below 3.0V, then the MAX  
becomes:  
(3.3V supply voltage) + 0.5 5.5  
Voltage on any signal  
pin  
-0.3  
V
V
DD33  
Voltage on XTAL1  
Voltage on XTAL2  
-0.3  
-0.3  
V
V
V
V
DDA33  
DD18  
Note 7.4 A 3.3V regulator with an output tolerance of 1% must be used if the output of the internal  
power FET’s must support a 5% tolerance.  
SMSC USB2250/50i/51/51i  
29  
Revision 1.1 (05-29-08)  
DATASHEET  
       
Ultra Fast USB 2.0 Multi-Slot Flash Media Controller  
Datasheet  
7.3  
DC Electrical Characteristics  
PARAMETER  
SYMBOL  
MIN  
TYP  
MAX  
UNITS  
COMMENTS  
I, IPU, IPD Type Input Buffer  
Low Input Level  
V
0.8  
V
V
TTL Levels  
ILI  
High Input Level  
V
2.0  
IHI  
Pull Down  
PD  
PU  
72  
58  
μA  
μA  
Pull Up  
IS Type Input Buffer  
Low Input Level  
High Input Level  
V
0.8  
V
V
TTL Levels  
ILI  
V
2.0  
IHI  
Hysteresis  
V
420  
mV  
HYSI  
ICLK Input Buffer  
Low Input Level  
High Input Level  
Input Leakage  
V
0.5  
V
V
ILCK  
V
1.4  
-10  
IHCK  
I
+10  
μA  
IL  
V
= 0 to V  
DD33  
IN  
Input Leakage  
(All I and IS buffers)  
Low Input Leakage  
I
-10  
-10  
+10  
+10  
μA  
V
V
= 0  
IL  
IN  
High Input Leakage  
I
μA  
= V  
IH  
IN  
DD33  
O12 Type Buffer  
Low Output Level  
High Output Level  
Output Leakage  
V
0.4  
V
V
I
V
= 12mA @  
OL  
OL  
OH  
OL  
= 3.3V  
DD33  
V
V
- 0.4  
I
V
= -12mA @  
OH  
DD33  
= 3.3V  
DD33  
I
-10  
+10  
μA  
V
= 0 to V  
IN DD33  
Revision 1.1 (05-29-08)  
30  
SMSC USB2250/50i/51/51i  
DATASHEET  
 
Ultra Fast USB 2.0 Multi-Slot Flash Media Controller  
Datasheet  
PARAMETER  
SYMBOL  
MIN  
TYP  
MAX  
UNITS  
COMMENTS  
I/O12, I/O12PU & I/O12PD Type  
Buffer  
Low Output Level  
High Output Level  
Output Leakage  
V
0.4  
V
V
I
V
= 12mA @  
OL  
OL  
OH  
OL  
= 3.3V  
DD33  
V
V
- 0.4  
I
V
= -12mA @  
OH  
DD33  
= 3.3V  
DD33  
I
-10  
+10  
µA  
V
= 0 to V  
IN DD33  
Pull Down  
Pull Up  
PD  
PU  
72  
58  
μA  
μA  
IO-U  
I-R  
I/O200  
Integrated Power FET for  
GPIO8, GPIO9, GPIO10, &  
GPIO11  
High Output Current Mode  
I
I
200  
100  
mA  
mA  
Vdrop  
Vdrop  
= 0.46V  
= 0.23V  
OUT  
FET  
Low Output Current Mode  
OUT  
FET  
On Resistance  
R
t
2.1  
Ω
I
= 70mA  
FET  
DSON  
Output Voltage Rise Time  
Supply Current Unconfigured  
Supply Current Active  
Full Speed  
800  
90  
μs  
C
= 10μF  
LOAD  
DSON  
I
80  
mA  
CCINIT  
V
V
, V  
DD33  
= 1.8V  
DDA  
I
110  
135  
140  
165  
mA  
mA  
DD  
DDP  
CC  
, V  
= 3.3V  
I
CC  
High Speed  
Supply Current Suspend  
I
350  
350  
750  
950  
µA  
µA  
V
V
, V  
DD  
DD33  
= 1.8V  
= 3.3V  
CSBY  
DDP  
DDA  
, V  
Industrial Temperature Suspend  
I
CSBYI  
Note 7.5 Output leakage is measured with the current pins in high impedance.  
Note 7.6 See The USB 2.0 Specification, Chapter 7, for USB DC electrical characteristics  
Note 7.7 RBIAS is a 3.3V tolerant analog pin.  
Note 7.8 Output current range is controlled by program software, software disables FET during short  
circuit condition.  
SMSC USB2250/50i/51/51i  
31  
Revision 1.1 (05-29-08)  
DATASHEET  
       
Ultra Fast USB 2.0 Multi-Slot Flash Media Controller  
Datasheet  
Note 7.9 The assignment of each Integrated Card Power FET to a designated Card Connector is  
controlled by both firmware and the specific board implementation. Firmware will default to  
Note 7.10 The 3.3V supply should be at least at 75% of its operating condition before the 1.8V supply  
is allowed to ramp up.  
7.4  
Capacitance  
T
= 25°C; fc = 1MHz; V  
V
= 1.8V  
A
DD, DDP  
Table 7.1 Pin Capacitance  
LIMITS  
PARAMETER  
SYMBOL  
MIN  
TYP  
MAX  
UNIT  
TEST CONDITION  
Clock Input Capacitance  
C
2
pF  
All pins (except USB pins  
and pins under test) are tied  
to AC ground.  
XTAL  
Input Capacitance  
Output Capacitance  
C
10  
20  
pF  
pF  
IN  
C
OUT  
Revision 1.1 (05-29-08)  
32  
SMSC USB2250/50i/51/51i  
DATASHEET  
   
Ultra Fast USB 2.0 Multi-Slot Flash Media Controller  
Datasheet  
Chapter 8 AC Specifications  
8.1  
Oscillator/Clock  
Crystal: Parallel Resonant, Fundamental Mode, 24 MHz ± 100ppm.  
External Clock: 50% Duty cycle ± 10%, 24/48 MHz ± 100ppm, Jitter < 100ps rms.  
XTAL1  
(CS1 =  
CB + CXTAL  
)
C1  
1Meg  
Crystal  
CL  
C2  
XTAL2  
(CS2 =  
CB + CXTAL  
)
Figure 8.1 Typical Crystal Circuit  
Note:  
C
equals total board/trace capacitance.  
B
(C1 + CS1) x (C2 + CS2)  
(C1 + CS1 + C2 + CS2)  
CL  
=
Figure 8.2 Formula to Find Value of C and C  
1
2
SMSC USB2250/50i/51/51i  
33  
Revision 1.1 (05-29-08)  
DATASHEET  
       
Chapter 9 Package Outline  
R EVISION HISTORY  
DESCRIPTION  
REVISION  
-
DATE  
-
REL EASED BY  
-
SEE SPECFRONTPAGE FORREVI SIONHISTORY  
D
R1  
R2  
5
D1  
3
0.25  
0°-7°  
E1/4  
GAUGE PLANE  
b
L
4
D 1/4  
3
2
E
E1  
L1  
e
DETAIL "A"  
TOP VIEW  
SEE DETAIL "A"  
C
A2  
A
SEAT ING PLANE  
A1  
c
ccc  
C
SIDE VIEW  
NO TES:  
1. ALL DIMENSIONS ARE IN MILLIMETER.  
2. TRUE POSITION SPREAD TOLERANCE OF EACH LEA D IS ± 0.035mm MAXIMUM.  
3. DIMENSIONS "D1" AND "E1" DO NOT INCLUDE MOLD PROTRUSIONS. MAXIMUM A LLOWED  
PROTRUSIO N IS 0.25 mm PER SIDE.  
4. DIMENSION "L" IS MEASURED AT THE GAUGE PLANE, 0.25mm ABOVE THE SEA TING P LANE.  
5. DETAILS ON PIN 1 IDENTIFIER ARE OPTIONAL BUT MUST BE LOCATED WITHIN THE ZONE  
INDICATE D.  
UNLESS  
OTHERWISESPECIFIED  
THI RD ANGLE PROJECT ION  
DIMENSIONS ARE INMILLIMETERS  
AND TOLERANCESARE:  
80 AR KAY DR IVE  
HAUPPAUGE, NY 11788  
USA  
DECIMAL  
ANGULAR  
±1°  
X.X  
±0.1  
X.XX ±0.05  
X.XXX ±0.025  
TITLE  
INTERPRET DIM ANDT OL PER  
ASMEY14.5 M- 1994  
NAME  
DR AWN  
DA TE  
PACKAG E OUTLINE  
128 VTQFP-14x14x1.0mmBODY-0.4mm PITCH  
MATERIAL  
-
-
S. K. ILI EV  
12/17/04  
12/17/04  
12/17/04  
3-D VIEW  
FINISH  
CH EC KE D  
DWG NUMBER  
REV  
S. K. ILI EV  
MO-128-VTQFP-14x14x1.0  
C
AP PR OVED  
SCALE  
1:1  
STD COMPLIANCE  
SHEET  
1
P RINT WITH "S CALE TO FIT"  
DO NOTSCALEDRAWING  
JE D EC : MS -0 2 6 (D )  
S. K. ILI EV  
OF 1  
Figure 9.1 USB2250/50i/51/51i 128-Pin VTQFP, 14x14x1.0mm Body, 2.0mm Pitch  
   
Ultra Fast USB 2.0 Multi-Slot Flash Media Controller  
Datasheet  
Chapter 10 GPIO Usage  
Table 10.1 USB2250/50i/51/51i GPIO Usage (ROM Rev 0x00)  
NAME  
ACTIVE LEVEL  
SYMBOL  
DESCRIPTION AND NOTE  
LED indicator  
GPIO1  
GPIO2  
H
H
LED1  
CF_DMARQ / RXD  
Compact Flash DMA request / Receive  
Port of Debugger  
GPIO3  
GPIO4  
H
H
VBUS_DET  
SCL / xD_ID  
USB Vbus detect  
Serial EEPROM clock output / xD card  
detect  
GPIO5  
GPIO6  
GPIO7  
H
L
SDA  
Serial EEPROM data  
SD Write Protect  
SD_WP  
H
CF_DMACK / TXD  
Compact Flash DMA acknowledge  
/Transmit Port of Debugger  
GPIO8  
GPIO9  
L
CRD_PWR0  
CRD_PWR1  
CRD_PWR2  
CRD_PWR3  
MS_INS  
Card Power Control  
Card Power Control  
Card Power Control  
Card Power Control  
Memory Stick Card Insertion  
Compact Flash card detect  
xD card detect  
L
GPIO10  
GPIO11  
GPIO12  
GPIO13  
GPIO14  
GPIO15  
GPIO16-32  
L
L
L
L
CF_nCD  
L
L
xD_nCD  
SD_nCD  
Secure Digital card detect  
User defined  
USER  
GPIO [32:16]  
SMSC USB2250/50i/51/51i  
35  
Revision 1.1 (05-29-08)  
DATASHEET  
     

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