Cypress Quad HOTLink II CYV15G0404RB User Manual

CYV15G0404RB  
Independent Clock Quad HOTLink II™  
Deserializing Reclocker  
and SMPTE 259 video applications. It supports signaling rates  
in the range of 195 to 1500 Mbps for each serial link. The four  
channels are independent and can simultaneously operate at  
different rates. Each receive channel accepts serial data and  
converts it to 10-bit parallel characters and presents these  
characters to an Output Register. The received serial data can  
also be reclocked and retransmitted through the reclocker  
serial outputs. Figure 1, "HOTLink II™ System Connections,"  
on page 2 illustrates typical connections between independent  
video coprocessors and corresponding CYV15G0404RB  
Reclocking Deserializer and CYV15G0403TB Serializer chips.  
Features  
®
• Second-generation HOTLink technology  
• Compliant to SMPTE 292M and SMPTE 259M video  
standards  
• Quad channel video reclocking deserializer  
— 195 to 1500 Mbps serial data signaling rate  
— Simultaneous operation at different signaling rates  
• Supportsreceptionofeither1.485or1.485/1.001Gbpsdata  
rate with the same training clock  
The CYV15G0404RB is SMPTE-259M and SMPTE-292M  
compliant according to SMPTE EG34-1999 Pathological Test  
Requirements.  
• Supports half-rate and full-rate clocking  
• Internal phase-locked loops (PLLs) with no external PLL  
components  
As  
a
second generation HOTLink device, the  
• Selectable differential PECL-compatible serial inputs  
— Internal DC restoration  
CYV15G0404RB extends the HOTLink family with enhanced  
levels of integration and faster data rates, while maintaining  
serial-link compatibility (data and BIST) with other HOTLink  
devices.  
• Synchronous LVTTL parallel interface  
• JTAG boundary scan  
Each channel of the CYV15G0404RB Quad HOTLink II device  
accepts a serial bit-stream from one of two selectable  
PECL-compatible differential line receivers, and using a  
completely integrated Clock and Data Recovery PLL, recovers  
the timing information necessary for data reconstruction. The  
device reclocks and retransmits recovered bit-stream through  
the reclocker serial outputs. It also deserializes the recovered  
serial data and presents it to the destination host system.  
• Built-In Self-Test (BIST) for at-speed link testing  
• Link Quality Indicator  
— Analog signal detect  
— Digital signal detect  
• Low-power: 3W @ 3.3V typical  
• Single 3.3V supply  
Each channel contains an independent BIST pattern checker.  
This BIST hardware enables at speed testing of the  
high-speed serial data paths in each receive section of this  
device, each transmit section of a connected HOTLink II  
device, and across the interconnecting links.  
• Thermally enhanced BGA  
• Pb-Free package option available  
• 0.25µ BiCMOS technology  
Functional Description  
The CYV15G0404RB is ideal for SMPTE applications where  
different data rates and serial interface standards are  
necessary for each channel. Some applications include  
multi-format routers, switchers, format converters, SDI  
monitors, and camera control units.  
The CYV15G0404RB Independent Clock Quad HOTLink II™  
Deserializing Reclocker is a point-to-point or point-to-multi-  
point communications building block enabling data transfer  
over a variety of high speed serial links including SMPTE 292  
Cypress Semiconductor Corporation  
Document #: 38-02102 Rev. *C  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised February 16, 2007  
CYV15G0404RB  
= Internal Signal  
RESET  
Reclocking Deserializer Path Block Diagram  
TRST  
TRGRATEA  
JTAG  
Boundary  
Scan  
TMS  
TCLK  
TDI  
x2  
TRGCLKA  
Controller  
SDASEL[2..1]A[1:0]  
LDTDEN  
TDO  
LFIA  
Receive  
Signal  
INSELA  
Monitor  
10  
RXDA[9:0]  
BISTSTA  
10  
10  
INA1+  
INA1–  
Clock &  
INA2+  
INA2–  
Data  
Recovery  
RXCLKA+  
RXCLKA–  
PLL  
÷2  
ULCA  
SPDSELA  
RXBISTA[1:0]  
RXRATEA  
RXPLLPDA  
Recovered Serial Data  
Recovered Character Clock  
ROE[2..1]A  
Reclocker  
Output PLL  
Clock Multiplier A  
ROUTA1+  
ROUTA1–  
ROE[2..1]A  
ROUTA2+  
ROUTA2–  
RECLKOA  
Character-Rate Clock A  
REPDOA  
TRGRATEB  
x2  
TRGCLKB  
LDTDEN  
SDASEL[2..1]B[1:0]  
LFIB  
Receive  
Signal  
INSELB  
Monitor  
10  
RXDB[9:0]  
BISTSTB  
10  
10  
INB1+  
INB1–  
Clock &  
Data  
Recovery  
PLL  
INB2+  
INB2–  
RXCLKB+  
RXCLKB–  
÷2  
ULCB  
SPDSELB  
RXBISTB[1:0]  
RXRATEB  
RXPLLPDB  
Recovered Serial Data  
Recovered Character Clock  
ROE[2..1]B  
Reclocker  
Output PLL  
Clock Multiplier B  
ROUTB1+  
ROUTB1–  
ROE[2..1]B  
ROUTB2+  
ROUTB2–  
RECLKOB  
REPDOB  
Character-Rate Clock B  
Document #: 38-02102 Rev. *C  
Page 3 of 27  
CYV15G0404RB  
Reclocking Deserializer Path Block Diagram (continued)  
= Internal Signal  
TRGRATEC  
x2  
TRGCLKC  
SDASEL[2..1]C[1:0]  
LDTDEN  
INSELC  
LFIC  
Receive  
Signal  
Monitor  
10  
RXDC[9:0]  
BISTSTC  
10  
10  
INC1+  
INC1–  
Clock &  
Data  
Recovery  
PLL  
INC2+  
INC2–  
RXCLKC+  
RXCLKC–  
÷2  
ULCC  
SPDSELC  
RXBISTC[1:0]  
RXRATEC  
RXPLLPDC  
Recovered Serial Data  
Recovered Character Clock  
ROE[2..1]C  
Reclocker  
Output PLL  
Clock Multiplier C  
ROUTC1+  
ROUTC1–  
ROE[2..1]C  
ROUTC2+  
ROUTC2–  
RECLKOC  
REPDOC  
Character-Rate Clock C  
TRGRATED  
x2  
TRGCLKD  
SDASEL[2..1]D[1:0]  
LDTDEN  
INSELD  
LFID  
Receive  
Signal  
Monitor  
10  
RXDD[9:0]  
BISTSTD  
10  
10  
IND1+  
IND1–  
Clock &  
Data  
Recovery  
PLL  
IND2+  
IND2–  
RXCLKD+  
RXCLKD–  
÷2  
ULCD  
SPDSELD  
RXBISTD[1:0]  
RXRATED  
RXPLLPDD  
Recovered Serial Data  
Recovered Character Clock  
ROE[2..1]D  
Reclocker  
Output PLL  
Clock Multiplier D  
ROUTD1+  
ROUTD1–  
ROE[2..1]D  
ROUTD2+  
ROUTD2–  
RECLKOD  
REPDOD  
Character-Rate Clock D  
Document #: 38-02102 Rev. *C  
Page 4 of 27  
CYV15G0404RB  
Device Configuration and Control Block Diagram  
= Internal Signal  
RXBIST[A..D]  
RXRATE[A..D]  
SDASEL[A..D][1:0]  
RXPLLPD[A..D]  
WREN  
Device Configuration  
ADDR[3:0]  
and Control Interface  
ROE[2..1][A..D]  
GLEN[11..0]  
FGLEN[2..0]  
DATA[7:0]  
Document #: 38-02102 Rev. *C  
Page 5 of 27  
CYV15G0404RB  
Pin Configuration (Top View)[1]  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
A
B
C
D
E
IN  
C1–  
ROUT  
C1–  
IN  
C2–  
ROUT  
C2–  
IN  
D1–  
ROUT  
D1–  
IN  
D2–  
ROUT  
D2–  
IN  
A1–  
ROUT  
A1–  
IN  
A2–  
ROUT  
A2–  
IN  
B1–  
ROUT  
B1–  
IN  
B2–  
ROUT  
B2–  
V
GND  
GND  
V
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
IN  
C1+  
ROUT  
C1+  
IN  
C2+  
ROUT  
C2+  
IN  
D1+  
ROUT  
D1+  
IN  
D2+  
ROUT  
D2+  
IN  
A1+  
ROUT  
A1+  
IN  
A2+  
ROUT  
A2+  
IN  
B1+  
ROUT  
B1+  
IN  
B2+  
ROUT  
B2+  
V
V
V
GND  
GND  
GND  
GND  
GND  
V
V
V
TDI  
TMS INSELC INSELB  
ULCD ULCC  
DATA  
[7]  
DATA  
[5]  
DATA  
[3]  
DATA  
[1]  
SPD  
SELD  
LDTD TRST  
EN  
TDO  
V
GND  
CC  
TCLK RESET INSELD INSELA  
ULCA  
SPD  
SELC  
DATA  
[6]  
DATA  
[4]  
DATA  
[2]  
DATA  
[0]  
ULCB  
SCAN TMEN3  
EN2  
GND GND  
NC  
V
CC  
CC  
V
V
V
V
V
V
V
V
V
V
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
F
RX  
RX  
RX  
RE  
RX  
V
CC  
DC[8] DC[9]  
DB[0] CLKOB DB[1]  
G
WREN  
GND  
SPD  
SELB  
SPD  
SELA DB[3]  
RX  
GND GND  
NC  
H
J
GND GND GND GND  
GND GND GND GND  
GND GND GND GND  
BIST  
STB  
RX  
DB[2]  
RX  
DB[7]  
RX  
DB[4]  
K
L
RX  
TRG  
RX  
DB[5]  
RX  
DB[6]  
RX  
DB[9]  
LFIB  
GND GND  
DC[4] CLKC–  
RX  
TRG  
LFIC  
RX  
RX  
RX  
GND  
GND  
GND  
DC[5] CLKC+  
DB[8] CLKB+ CLKB–  
M
N
RX  
RX  
RE  
PDOC  
TRG  
TRG  
RE  
V
CC  
DC[6] DC[7]  
CLKB+ CLKB– PDOB  
GND GND GND GND  
GND GND GND GND  
GND GND GND GND  
P
R
T
RX  
RX  
RX  
RX  
DC[3] DC[2] DC[1] DC[0]  
BIST  
RE  
RX  
RX  
V
V
V
V
V
V
V
V
CC  
CC  
CC  
CC  
STC CLKOC CLKC+ CLKC–  
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
U
V
RX  
RX  
ADDR  
[0]  
TRG  
CLKD–  
RX  
DA[4]  
BIST  
STA  
RX  
DA[0]  
V
V
V
V
GND GND  
GND GND GND  
V
V
V
V
V
V
V
V
V
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
DD[4] DD[3]  
RX  
DD[8]  
RX  
RX  
BIST ADDR  
STD [2]  
TRG  
CLKD+ CLKOA  
RE  
RX  
DA[9]  
RX  
DA[5]  
RX  
DA[2]  
RX  
DA[1]  
GND  
GND  
GND  
GND GND  
DD[5] DD[1]  
W
Y
LFID  
RX  
RX  
RX  
ADDR ADDR  
RX  
RE  
LFIA  
TRG  
CLKA+ DA[6]  
RX  
RX  
DA[3]  
GND GND  
GND GND  
CLKD–  
DD[6] DD[0]  
[3]  
[1]  
CLKA+ PDOA  
RX  
RX  
RX  
RX  
RE  
CLKOD  
NC  
RX  
CLKA–  
RE  
TRG  
RX  
RX  
DA[7]  
GND  
DD[9] CLKD+  
DD[7] DD[2]  
PDOD CLKA– DA[8]  
Note  
1. NC = Do not connect.  
Document #: 38-02102 Rev. *C  
Page 6 of 27  
CYV15G0404RB  
Pin Configuration (Bottom View)[1]  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
ROUT  
B2–  
IN  
B2–  
ROUT  
B1–  
IN  
B1–  
ROUT  
A2–  
IN  
A2–  
ROUT  
A1–  
IN  
A1–  
ROUT  
D2–  
IN  
D2–  
ROUT  
D1–  
IN  
D1–  
ROUT  
C2–  
IN  
C2–  
ROUT  
C1–  
IN  
C1–  
V
GND  
GND  
V
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
A
B
C
D
E
F
ROUT  
B2+  
IN  
B2+  
ROUT  
B1+  
IN  
B1+  
ROUT  
A2+  
IN  
A2+  
ROUT  
A1+  
IN  
A1+  
ROUT  
D2+  
IN  
D2+  
ROUT  
D1+  
IN  
D1+  
ROUT  
C2+  
IN  
C2+  
ROUT  
C1+  
IN  
C1+  
V
V
V
GND  
GND  
GND  
GND  
GND  
V
V
V
TDO  
TRST LDTD  
EN  
SPD  
SELD  
DATA  
[1]  
DATA  
[3]  
DATA  
[5]  
DATA  
[7]  
ULCC ULCD  
INSELB INSELC TMS  
TDI  
GND  
V
CC  
TMEN3 SCAN  
EN2  
ULCB  
DATA  
[0]  
DATA  
[2]  
DATA  
[4]  
DATA  
[6]  
SPD  
SELC  
ULCA  
INSELA INSELD RESET TCLK  
V
V
NC  
GND GND  
CC  
CC  
V
V
V
V
V
V
V
V
V
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
RX  
RE  
RX  
RX  
RX  
V
CC  
CC  
DB[1] CLKOB DB[0]  
DC[9] DC[8]  
RX  
SPD  
SPD  
SELB  
WREN  
GND  
NC  
GND GND  
G
H
J
DB[3] SELA  
GND GND GND GND  
GND GND GND GND  
GND GND GND GND  
RX  
DB[4]  
RX  
DB[7]  
RX  
DB[2]  
BIST  
STB  
LFIB  
RX  
DB[9]  
RX  
DB[6]  
RX  
DB[5]  
TRG  
CLKC– DC[4]  
RX  
GND GND  
K
L
RX  
RX  
RX  
LFIC  
TRG  
CLKC+ DC[5]  
RX  
GND  
GND  
GND  
CLKB– CLKB+ DB[8]  
RE  
TRG  
TRG  
RE  
PDOC  
RX  
RX  
V
CC  
M
N
P
R
T
PDOB CLKB– CLKB+  
DC[7] DC[6]  
GND GND GND GND  
GND GND GND GND  
GND GND GND GND  
RX  
RX  
RX  
RX  
DC[0] DC[1] DC[2] DC[3]  
RX  
RX  
RE  
BIST  
V
V
V
V
V
V
V
V
V
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CLKC– CLKC+ CLKOC STC  
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
RX  
DA[0]  
BIST  
STA  
RX  
DA[4]  
TRG  
CLKD–  
ADDR  
[0]  
RX  
RX  
V
V
V
V
V
V
V
V
GND GND GND  
GND GND  
V
V
V
V
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
U
V
W
Y
DD[3] DD[4]  
RX  
DA[1]  
RX  
DA[2]  
RX  
DA[5]  
RX  
DA[9]  
RE  
TRG  
CLKOA CLKD+  
ADDR BIST  
[2] STD  
RX  
RX  
RX  
DD[8]  
GND GND  
GND  
GND  
GND  
DD[1] DD[5]  
RX  
DA[3]  
RX  
TRG  
LFIA  
RE  
RX  
ADDR ADDR  
[1]  
RX  
RX  
RX  
LFID  
GND GND  
GND GND  
DA[6] CLKA+  
PDOA CLKA+  
[3]  
DD[0] DD[6]  
CLKD–  
RX  
DA[7]  
RX  
TRG  
RE  
RX  
CLKA–  
NC  
RE  
CLKOD  
RX  
RX  
RX  
RX  
GND  
DA[8] CLKA– PDOD  
DD[2] DD[7]  
CLKD+ DD[9]  
Document #: 38-02102 Rev. *C  
Page 7 of 27  
CYV15G0404RB  
Pin Definitions  
CYV15G0404RB Quad HOTLink II Deserializing Reclocker  
Name  
IO Characteristics  
Signal Description  
Receive Path Data and Status Signals  
RXDA[9:0]  
RXDB[9:0]  
RXDC[9:0]  
RXDD[9:0]  
LVTTL Output,  
synchronous to the  
RXCLK± output  
Parallel Data Output. RXDx[9:0] parallel data outputs change relative to the  
receive interface clock. If RXCLKx± is a full-rate clock, the RXCLKx± clock outputs  
are complementary clocks operating at the character rate. The RXDx[9:0] outputs  
for the associated receive channels follow the rising edge of RXCLKx+ or the  
falling edge of RXCLKx–. If RXCLKx± is a half-rate clock, the RXCLKx± clock  
outputs are complementary clocks operating at half the character rate. The  
RXDx[9:0] outputs for the associated receive channels follow both the falling and  
rising edges of the associated RXCLKx± clock outputs.  
When BIST is enabled on the receive channel, the RXDx[1:0] and BISTSTx  
outputs present the BIST status. See Table 5, “Receive BIST Status Bits,” on  
page 17 for each status that the BIST state machine reports. Also, while BIST is  
enabled, ignore the RXDx[9:2] outputs.  
BISTSTA  
BISTSTB  
BISTSTC  
BISTSTD  
LVTTL Output,  
synchronous to the  
RXCLKx± output  
BIST Status Output. When RXBISTx[1:0] = 10, BISTSTx (along with RXDx[1:0])  
displays the status of the BIST reception. See Table 5, “Receive BIST Status Bits,”  
on page 17 for the BIST status for each combination of BISTSTx and RXDx[1:0].  
When RXBISTx[1:0] 10, ignore BISTSTx.  
REPDOA  
REPDOB  
REPDOC  
REPDOD  
Asynchronous to  
reclocker output  
channel  
Reclocker Powered Down Status Output. REPDOx asserts HIGH when the  
associated channel’s reclocker output logic powers down. This occurs when  
disabling ROE2x and ROE1x by setting ROE2x = 0 and ROE1x = 0.  
enable / disable  
Receive Path Clock Signals  
TRGCLKA±  
TRGCLKB±  
TRGCLKC±  
TRGCLKD±  
Differential LVPECL or CDR PLL Training Clock. The frequency detector (Range Controller) of the  
single-ended  
LVTTL input clock  
associated receive PLL uses the TRGCLKx± clock inputs as the reference source  
to reduce PLL acquisition time.  
In the presence of valid serial data, the recovered clock output of the receive CDR  
PLL (RXCLKx±) has no frequency or phase relationship with TRGCLKx±.  
When a single-ended LVCMOS or LVTTL clock source drives the clock, connect  
the clock source to either the true or complement TRGCLKx input, and leave the  
alternate TRGCLKx input open (floating). When an LVPECL clock source drives  
it, the clock must be a differential clock, using both inputs.  
RXCLKA±  
RXCLKB±  
RXCLKC±  
RXCLKD±  
LVTTL Output Clock  
LVTTL Output  
Receive Clock Output. RXCLKx± is the receive interface clock that controls  
timing of the RXDx[9:0] parallel outputs. These true and complement clocks  
control timing of data output transfers. These clocks output continuously at either  
the half-character rate (1/20 the serial bit-rate) or character rate (1/10 the serial  
bit-rate) of the data being received, as selected by RXRATEx.  
RECLKOA  
RECLKOB  
RECLKOC  
RECLKOD  
Reclocker Clock Output. The associated reclocker output PLL synthesizes the  
RECLKOx output clock, which operates synchronous to the internal recovered  
character clock. RECLKOx operates at either the same frequency as RXCLKx±  
(RXRATEx = 0), or at twice the frequency of RXCLKx± (RXRATEx = 1). The  
reclocker clock outputs have no fixed phase relationship to RXCLKx±.  
Device Control Signals  
RESET LVTTL Input,  
Asynchronous Device Reset. RESET initializes all state machines, counters,  
and configuration latches in the device to a known state. RESET must assert LOW  
for a minimum pulse width. When the reset is removed, all state machines,  
counters and configuration latches are at an initial state. According to the JTAG  
specifications, the device RESET cannot reset the JTAG controller. Therefore, the  
JTAG controller has to be reset separately. Refer to “JTAG Support” on page 17  
for the methods to reset the JTAG state machine. See Table 3, “Device Configu-  
ration and Control Latch Descriptions,” on page 14 for the initialize values of the  
device configuration latches.  
asynchronous,  
internal pull up  
Document #: 38-02102 Rev. *C  
Page 8 of 27  
CYV15G0404RB  
Pin Definitions (continued)  
CYV15G0404RB Quad HOTLink II Deserializing Reclocker  
Name  
IO Characteristics  
Signal Description  
LDTDEN  
LVTTL Input,  
internal pull up  
Level Detect Transition Density Enable. When LDTDEN is HIGH, the Signal  
Level Detector, Range Controller, and Transition Density Detector are all enabled  
to determine if the RXPLL tracks TRGCLKx± or the selected input serial data  
stream. If the Signal Level Detector, Range Controller, or Transition Density  
Detector are out of their respective limits while LDTDEN is HIGH, the RXPLL locks  
to TRGCLKx± until they become valid. The SDASEL[A..D][1:0] inputs configure  
the trip level of the Signal Level Detector. The Transition Density Detector limit is  
one transition in every 60 consecutive bits. When LDTDEN is LOW, only the  
Range Controller determines if the RXPLL tracks TRGCLKx± or the selected input  
serial data stream. Set LDTDEN = HIGH.  
ULCA  
ULCB  
ULCC  
ULCD  
LVTTL Input,  
internal pull up  
Use Local Clock. When ULCx is LOW, the RXPLL locks to TRGCLKx± instead  
of the received serial data stream. While ULCx is LOW, the LFIx for the associated  
channel is LOW, indicating a link fault.  
When ULCx is HIGH, the RXPLL performs Clock and Data Recovery functions on  
the input data streams. This function is used in applications that need a stable  
RXCLKx±. When valid data transitions are absent for a long time, or the high-gain  
differential serial inputs (INx±) are left floating, the RXCLKx± outputs may briefly  
be different from TRGCLKx±.  
[2]  
SPDSELA  
SPDSELB  
SPDSELC  
SPDSELD  
3-Level Select  
Serial Rate Select. The SPDSELx inputs specify the operating signaling-rate  
range of each channel’s receive PLL.  
static control input  
LOW = 195–400 MBd  
MID = 400–800 MBd  
HIGH = 800–1500 MBd.  
INSELA  
INSELB  
INSELC  
INSELD  
LVTTL Input,  
asynchronous  
Receive Input Selector. The INSELx input determines which external serial bit  
stream passes to the receiver’s Clock and Data Recovery circuit. When INSELx  
is HIGH, the Primary Differential Serial Data Input, INx1±, is the associated receive  
channel. When INSELx is LOW, the Secondary Differential Serial Data Input,  
INx2±, is the associated receive channel.  
LFIA  
LFIB  
LFIC  
LFID  
LVTTL Output,  
asynchronous  
Link Fault Indication Output. LFIx is an output status indicator signal. LFIx is the  
logical OR of six internal conditions. LFIx asserts LOW when any of the following  
conditions is true:  
• Received serial data rate is outside expected range  
• Analog amplitude is below expected levels  
• Transition density is lower than expected  
• Receive is channel disabled  
• ULCx is LOW  
• TRGCLKx± is absent.  
Device Configuration and Control Bus Signals  
WREN  
LVTTL input,  
asynchronous,  
Control Write Enable. The WREN input writes the values of the DATA[7:0] bus  
into the latch specified by the address location on the ADDR[3:0] bus.  
[3]  
internal pull up  
ADDR[3:0]  
LVTTL input  
asynchronous,  
internal pull up  
Control Addressing Bus. The ADDR[3:0] bus is the input address bus that  
configures the device. The WREN input writes the values of the DATA[7:0] bus  
[3]  
into the latch specified by the address location on the ADDR[3:0] bus. Table 3,  
“Device Configuration and Control Latch Descriptions,” on page 14 lists the config-  
uration latches within the device, and the initialization value of the latches when  
RESET is asserted. Table 4, “Device Control Latch Configuration Table,” on  
page 16 shows how the latches are mapped in the device.  
Notes  
2. Use 3-Level Select inputs for static configuration. These are ternary inputs that use logic levels of LOW, MID, and HIGH. To implement the LOW level, connect  
directly to V (ground). To implement the HIGH level, connect directly to V (power). To implement the MID level, do not connect the input (leave floating),  
SS  
CC  
which allows it to self bias to the proper level.  
3. See “Device Configuration and Control Interface” on page 13 for detailed information about the operation of the Configuration Interface.  
Document #: 38-02102 Rev. *C  
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CYV15G0404RB  
Pin Definitions (continued)  
CYV15G0404RB Quad HOTLink II Deserializing Reclocker  
Name  
IO Characteristics  
Signal Description  
DATA[7:0]  
LVTTL input  
asynchronous,  
internal pull-up  
Control Data Bus. The DATA[7:0] bus is the input data bus that configures the  
device. The WREN input writes the values of the DATA[7:0] bus into the latch  
[3]  
specified by address location on the ADDR[3:0] bus. Table 3, “Device Configu-  
ration and Control Latch Descriptions,” on page 14 lists the configuration latches  
within the device, and the initialization value of the latches when RESET is  
asserted. Table 4, “Device Control Latch Configuration Table,” on page 16 shows  
the way the latches are mapped in the device.  
Internal Device Configuration Latches  
[4]  
RXRATE[A..D]  
Internal Latch  
Receive Clock Rate Select.  
[4]  
SDASEL[2..1][A..D] Internal Latch  
[1:0]  
Signal Detect Amplitude Select.  
[4]  
[4]  
[4]  
[4]  
[4]  
[4]  
RXPLLPD[A..D]  
Internal Latch  
Receive Channel Power Control.  
Receive BIST Disabled.  
RXBIST[A..D][1:0] Internal Latch  
ROE2[A..D]  
ROE1[A..D]  
GLEN[11..0]  
FGLEN[2..0]  
Internal Latch  
Internal Latch  
Internal Latch  
Internal Latch  
Reclocker Differential Serial Output Driver 2 Enable.  
Reclocker Differential Serial Output Driver 1 Enable.  
Global Latch Enable.  
Force Global Latch Enable.  
Factory Test Modes  
SCANEN2  
LVTTL input,  
internal pull down  
Factory Test 2. The SCANEN2 input is for factory testing only. Leave this input  
as a NO CONNECT, or GND only.  
TMEN3  
LVTTL input,  
internal pull down  
Factory Test 3. The TMEN3 input is for factory testing only. Leave this input as a  
NO CONNECT, or GND only.  
Analog I/O  
ROUTA1±  
ROUTB1±  
ROUTC1±  
ROUTD1±  
CML Differential  
Output  
Primary Differential Serial Data Output. The ROUTx1± PECL-compatible CML  
outputs (+3.3V referenced) can drive terminated transmission lines or standard  
fiber-optic transmitter modules, and must be AC-coupled for PECL-compatible  
connections.  
ROUTA2±  
ROUTB2±  
ROUTC2±  
ROUTD2±  
CML Differential  
Output  
Secondary Differential Serial Data Output. The ROUTx2± PECL-compatible  
CML outputs (+3.3V referenced) are capable of driving terminated transmission  
lines or standard fiber-optic transmitter modules, and must be AC coupled for  
PECL-compatible connections.  
INA1±  
INB1±  
INC1±  
IND1±  
Differential Input  
Differential Input  
Primary Differential Serial Data Input. The INx1± input accepts the serial data  
stream for deserialization. The INx1± serial stream passes to the receive CDR  
circuit to extract the data content when INSELx = HIGH.  
INA2±  
INB2±  
INC2±  
IND2±  
Secondary Differential Serial Data Input. The INx2± input accepts the serial  
data stream for deserialization. The INx2± serial stream passes to the receiver  
CDR circuit to extract the data content when INSELx = LOW.  
JTAG Interface  
TMS  
LVTTL Input,  
internal pull up  
Test Mode Select. Controls access to the JTAG Test Modes. If TMS is HIGH for  
>5 TCLK cycles, the JTAG test controller resets.  
TCLK  
LVTTL Input,  
internal pull down  
JTAG Test Clock.  
Note  
4. See Device Configuration and Control Interface for detailed information on the internal latches.  
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CYV15G0404RB  
Pin Definitions (continued)  
CYV15G0404RB Quad HOTLink II Deserializing Reclocker  
Name  
IO Characteristics  
Signal Description  
TDO  
3-State LVTTL Output Test Data Out. JTAG data output buffer. High-Z while JTAG test mode is not  
selected.  
TDI  
LVTTL Input,  
internal pull up  
Test Data In. JTAG data input port.  
TRST  
LVTTL Input,  
internal pull up  
JTAG reset signal. When asserted (LOW), this input asynchronously resets the  
JTAG test access port controller.  
Power  
V
+3.3V Power.  
CC  
GND  
Signal and Power Ground for all internal circuits.  
All of these conditions must be valid for the Signal Detect block  
CYV15G0404RB HOTLink II Operation  
to indicate a valid signal is present. This status is presented on  
the LFIx (Link Fault Indicator) output associated with each  
receive channel, which changes synchronous to the receive  
interface clock.  
The CYV15G0404RB is a highly configurable, independent  
clocking, quad-channel reclocking deserializer that supports  
reliable transfer of large quantities of digital video data, using  
high-speed serial links from multiple sources to multiple desti-  
nations. This device supports four 10-bit channels.  
Analog Amplitude  
While most signal monitors are based on fixed constants, the  
analog amplitude level detection is adjustable to allow  
operation with highly attenuated signals, or in high noise  
environments. The SDASELx latch sets the analog amplitude  
level detection via the device configuration interface. The  
SDASELx latch sets the trip point for the detection of a valid  
signal at one of three levels, as listed in Table 1. This control  
input affects the analog monitors for all receive channels. The  
Analog Signal Detect monitors are active for the Line Receiver,  
as selected by the associated INSELx input.  
CYV15G0404RB Receive Data Path  
Serial Line Receivers  
Two differential Line Receivers, INx1± and INx2±, are  
available on each channel to accept serial data streams. The  
associated INSELx input selects the active Serial Line  
Receiver on a channel. The Serial Line Receiver inputs are  
differential, and can accommodate wire interconnect and  
filtering losses or transmission line attenuation greater than  
16 dB. For normal operation, these inputs must receive a  
[5]  
Table 1. Analog Amplitude Detect Valid Signal Levels  
signal of at least VI  
> 100 mV, or 200 mV peak-to-peak  
DIFF  
differential. Each Line Receiver can be DC or AC coupled to  
+3.3V powered fiber-optic interface modules (any ECL/PECL  
family, not limited to 100K PECL) or AC coupled to +5V  
powered optical modules. The common mode tolerance of  
these line receivers accommodates a wide range of signal  
termination voltages. Each receiver provides internal DC  
restoration, to the center of the receiver’s common mode  
range, for AC coupled signals.  
SDASEL Typical Signal with Peak Amplitudes Above  
00  
01  
10  
11  
Analog Signal Detector is disabled  
140 mV p-p differential  
280 mV p-p differential  
420 mV p-p differential  
Transition Density  
Signal Detect/Link Fault  
The Transition Detection logic checks for the absence of  
transitions spanning greater than six transmission characters  
(60 bits). If there are no transitions in the data received, the  
Detection logic for that channel asserts LFIx.  
Each selected Line Receiver (that is, that routed to the clock  
and data recovery PLL) is simultaneously monitored for  
• Analog amplitude above amplitude level selected by  
SDASELx  
Range Controls  
• Transition density above the specified limit  
The CDR circuit includes logic to monitor the frequency of the  
PLL Voltage Controlled Oscillator (VCO) samples the  
incoming data stream. This logic ensures that the VCO  
• Range controls reporting the received data stream inside  
[21]  
normal frequency range (±1500 ppm  
• Receive channel enabled  
• Reference clock present  
• ULCx not asserted.  
)
Note  
5. The peak amplitudes listed in this table are for typical waveforms that generally have 3–4 transitions for every ten bits. In a worst case environment the signals  
may have a sine-wave appearance (highest transition density with repeating 0101...). Signal peak amplitudes levels within this environment type could increase  
the values in the table above by approximately 100 mV.  
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CYV15G0404RB  
operates at, or near the rate of the incoming data stream for  
two primary cases:  
in the selected serial data stream performs the clock extraction  
function.  
• When the incoming data stream resumes after a time in  
which it was “missing.”  
Each CDR accepts  
half-character-rate (bit-rate ÷ 20) training clock from the  
associated TRGCLKx± input. This TRGCLKx± input is used to  
a
character-rate (bit-rate ÷ 10) or  
• When the incoming data stream is outside the acceptable  
signaling rate range.  
• Ensure that the VCO (within the CDR) is operating at the  
correct frequency (rather than a harmonic of the bit rate)  
To perform this function, periodically compare the frequency of  
the RXPLL VCO to the frequency of the TRGCLKx± input. If  
• Reduce PLL acquisition time  
[21]  
the VCO is running at a frequency beyond ±1500 ppm  
as  
• LimitunlockedfrequencyexcursionsoftheCDRVCOwhen  
there is no input data present at the selected Serial Line  
Receiver.  
defined by the TRGCLKx± frequency, it is periodically forced  
to the correct frequency (as defined by TRGCLKx±, SPDSELx,  
and TRGRATEx) and then released in an attempt to lock to the  
input data stream.  
Regardless of the type of signal present, the CDR attempts to  
recover a data stream from it. If the signaling rate of the  
recovered data stream is outside the limits set by the range  
control monitors, the CDR tracks TRGCLKx± instead of the  
data stream. Once the CDR output (RXCLK±) frequency  
returns close to TRGCLKx± frequency, the CDR input  
switches back to the input data stream. If no data is present at  
the selected line receiver, this switching behavior may cause  
brief RXCLK± frequency excursions from TRGCLKx±.  
However, the LFIx output indicates the validity of the input data  
stream. The frequency of TRGCLKx± must be within ±1500  
Calculate the sampling and relock period of the Range Control  
as follows: RANGE_CONTROL_SAMPLING_PERIOD  
=
(RECOVERED BYTE CLOCK PERIOD) * (4096).  
During the time that the Range Control forces the RXPLL VCO  
to track TRGCLKx±, the LFIx output is asserted LOW. After a  
valid serial data stream is applied, it may take up to one  
RANGE CONTROL SAMPLING PERIOD before the PLL  
locks to the input data stream, after which LFIx is HIGH.  
Table 2 lists the operating serial signaling rate and allowable  
range of TRGCLK± frequencies.  
[21]  
ppm of the frequency of the clock that drives the reference  
clock input of the remote transmitter, to ensure a lock to the  
incoming data stream. This large ppm tolerance allows the  
CDR PLL to reliably receive a 1.485 or 1.485/1.001 Gbps  
SMPTE HD-SDI data stream with a constant TRGCLK  
frequency.  
Table 2. Operating Speed Settings  
TRGCLKx±  
Signaling  
SPDSELx TRGRATEx  
Frequency  
(MHz)  
Rate (Mbps)  
For systems using multiple or redundant connections, use the  
LFIx output to select an alternate data stream. When the  
device detects an LFIx indication, external logic toggles  
selection of the associated INx1± and INx2± input through the  
associated INSELx input. When a port switch takes place, the  
receive PLL for that channel reacquires the new serial stream.  
LOW  
MID (Open)  
HIGH  
1
0
1
0
1
0
Reserved  
19.5–40  
20–40  
195–400  
400–800  
40–80  
40–75  
800–1500  
Reclocker  
80–150  
Each receive channel performs a reclocker function on the  
incoming serial data. To do this, the Clock and Data Recovery  
PLL first recovers the clock from the data. The recovered clock  
retimes the data and then passes it to an output register. It also  
passes the recovered character clock from the receive PLL to  
the reclocker output PLL, which generates the bit clock that  
clocks the retimed data into the output register. This data  
stream is then transmitted through the differential serial  
outputs.  
Receive Channel Enabled  
The CYV15G0404RB contains four receive channels that it  
can independently enable and disable. Each channel are  
enabled or disabled separately through the RXPLLPDx input  
latch as controlled by the device configuration interface.  
RXPLLPDx latch = 0 disables the associated PLL and analog  
circuitry of the channel. Any disabled channel indicates a  
constant link fault condition on the LFIx output. RXPLLPDx =  
1 enables the associated PLL and receive channel to receive  
a serial stream.  
Reclocker Serial Output Drivers  
The serial output interface drivers use differential Current  
Mode Logic (CML) drivers to provide source-matched drivers  
for 50transmission lines. These drivers accept data from the  
reclocker output register in the reclocker channel. These  
drivers have signal swings equivalent to that of standard PECL  
drivers, and can drive AC coupled optical modules or trans-  
mission lines.  
Note When a disabled receive channel is reenabled, the  
status of the associated LFIx output and data on the parallel  
outputs for the associated channel may be indeterminate for  
up to 2 ms.  
Clock/Data Recovery  
A separate CDR block within each receive channel performs  
the extraction of a bit rate clock and recovery of bits from each  
received serial stream. An integrated PLL that tracks the  
frequency of the transitions in the incoming bit stream and  
aligns the phase of the internal bit rate clock to the transitions  
Reclocker Output Channels Enabled  
Each driver can be enabled or disabled separately via the  
device configuration interface.  
When a driver is disabled using the configuration interface, it  
internally powers down to reduce device power. If both  
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Page 12 of 27  
CYV15G0404RB  
reclocker serial drivers for a channel are in this disabled state,  
the associated internal reclocker logic also powers down. The  
deserialization logic and parallel outputs remain enabled. A  
device reset (RESET sampled LOW) disables all output  
drivers.  
Power Control  
The CYV15G0404RB supports user control of the powered up  
or down state of each transmit and receive channel. The  
RXPLLPDx latch controls the receive channels through the  
device configuration interface. RXPLLPDx = 0 disables the  
associated PLL and analog circuitry of the channel. The OE1x  
and the OE2x latches control the transmit channels via the  
device configuration interface. The ROE1x and the ROE2x  
latches control the reclocker function through the device  
configuration interface. When the configuration interface  
disables a driver, the driver internally powers down to reduce  
device power. If both serial drivers for a channel are in this  
disabled state, the associated internal logic for that channel  
also powers down. The reclocker serial drivers being disabled  
in turn disables the reclocker function, but the deserialization  
logic and parallel outputs remain enabled.  
Note When the disabled reclocker function (that is, both  
outputs disabled) is reenabled, the data on the reclocker serial  
outputs may not meet all timing specifications for up to 250 µs.  
Output Bus  
Each receive channel presents a 10-bit data signal (and a  
BIST status signal when RXBISTx[1:0] = 10).  
Receive BIST Operation  
Each receiver channel contains an internal pattern checker  
that is used to validate both device and link operation. These  
pattern checkers are enabled by the associated RXBISTx[1:0]  
latch through the device configuration interface. When  
enabled, a register in the associated receive channel becomes  
a signature pattern generator and checker by logically  
converting to a Linear Feedback Shift Register (LFSR). This  
LFSR generates a 511-character sequence. This provides a  
predictable, yet pseudorandom, sequence that can be  
matched to an identical LFSR in the attached Transmitter(s).  
When synchronized with the received data stream, the  
associated Receiver checks each character from the deseri-  
alizer with each character generated by the LFSR and  
indicates compare errors and BIST status at the RXDx[1:0]  
and BISTSTx bits of the Output Register.  
Device Reset State  
Assertion of RESET resets all state machines, counters, and  
configuration latches in the device to  
a
reset state.  
Additionally, the JTAG controller must be reset for valid  
operation (even if not performing JTAG testing). See “JTAG  
Support” on page 17 for JTAG state machine initialization. See  
Table 3, “Device Configuration and Control Latch Descrip-  
tions,” on page 14 for the initialize values of the configuration  
latches.  
Following a device reset, enable the receive channels used for  
normal operation. Do this by sequencing the appropriate  
values on the device configuration interface.  
[3]  
The BIST status bus {BISTSTx, RXDx[0], RXDx[1]} indicates  
010b or 100b for one character period per BIST loop to  
indicate loop completion. Use this status to check test pattern  
progress.  
Device Configuration and Control Interface  
Configure the CYV15G0404RB through the configuration  
interface. The configuration interface enables the device to be  
configured globally or enables each channel to be configured  
independently. Table 3, “Device Configuration and Control  
Latch Descriptions,” on page 14 lists the configuration latches  
within the device, including the initialization value of the  
latches on the assertion of RESET. Table 4, “Device Control  
Latch Configuration Table,” on page 16 shows how the latches  
are mapped in the device. Each row in Table 4 maps to an 8-bit  
latch bank. There are 16 such write only latch banks. When  
WREN = 0, the logic value in the DATA[7:0] latches to the latch  
bank specified by the values in ADDR[3:0]. The second  
column of Table 4 specifies the channels associated with the  
corresponding latch bank. For example, the first three latch  
banks (0, 1, and 2) consist of configuration bits for channel A.  
Latch banks 12, 13, and 14 consist of Global configuration bits,  
and the last latch bank (15) is the Mask latch bank, which can  
be configured to perform bit-by-bit configuration.  
Table 5, “Receive BIST Status Bits,” on page 17 lists the  
specific status reported by the BIST state machine. The  
receive status outputs report these same codes.  
If the number of invalid characters received exceeds the  
number of valid characters by 16, the receive BIST state  
machine aborts the compare operations and resets the LFSR  
to look for the start of the BIST sequence again.  
A device reset (RESET sampled LOW) presets the BIST  
Enable Latches to disable BIST on all channels.  
BIST Status State Machine  
When a receive path is enabled to look for and compare the  
received data stream with the BIST pattern, the {BISTSTx,  
RXDx[0], RXDx[1]} bits identify the present state of the BIST  
compare operation.  
The BIST state machine has multiple states, as shown in  
Figure 2, "Receive BIST State Machine," on page 18 and  
Table 5, “Receive BIST Status Bits,” on page 17. When the  
receive PLL detects an out-of-lock condition, it forces the BIST  
state to the Start-of-BIST state, regardless of the present state  
of the BIST state machine. If the number of detected errors  
ever exceeds the number of valid matches by greater than 16,  
the state machine is forced to the WAIT_FOR_BIST state,  
where it monitors the receive path for the first character of the  
next BIST sequence.  
Global Enable Function  
The global enable function, controlled by the GLENx bits, is a  
feature that can reduce the number of write operations needed  
to set up the latch banks. This function is beneficial in systems  
that use a common configuration in multiple channels. The  
GLENx bit is present in bit 0 of latch banks 0 through 11 only.  
Its default value (1) enables the global update of the latch  
bank's contents. Setting the GLENx bit to 0 disables this  
functionality.  
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Page 13 of 27  
CYV15G0404RB  
Latch Banks 12, 13, and 14 load values in the related latch  
banks in globally. A write operation to latch bank 12 performs  
a global write to latch banks 0, 3, 6, and 9, depending on the  
value of GLENx in these latch banks; latch bank 13 performs  
a global write to latch banks 1, 4, 7, and 10; and latch bank 14  
performs a global write to latch banks 2, 5, 8, and 11. The  
GLENx bit cannot be modified by a global write operation.  
latch banks. The S type contains those settings that normally  
do not change for a given application, whereas the D type  
controls the settings that might change during the application's  
lifetime. The first and second rows of each channel (address  
numbers 0, 1, 3, 4, 6, 7, 9, and 10) are the static control  
latches. The third row of latches for each channel (address  
numbers 2, 5, 8, and 11) are the dynamic control latches that  
are associated with enabling dynamic functions within the  
device.  
Force Global Enable Function  
FGLENx forces the global update of the target latch banks, but  
does not change the contents of the GLENx bits. If FGLENx =  
1 for the associated global channel, FGLENx forces the global  
update of the target latch banks.  
Latch Bank 14 is also useful for those users that do not need  
the latch based programmable feature of the device. This latch  
bank is used in those applications that do not need to modify  
the default value of the static latch banks, and that can afford  
global (that is, not independent) control of the dynamic signals.  
In this case, this feature becomes available when ADDR[3:0]  
is unchanged with a value of “1110” and WREN is asserted.  
The signals present in DATA[7:0] effectively become global  
control pins, and for the latch banks 2, 5, 8, and 11.  
Mask Function  
An additional latch bank (15) is a global mask vector that  
controls the update of the configuration latch banks on a  
bit-by-bit basis. A logic 1 in a bit location enables the update  
of that same location of the target latch bank(s), whereas a  
logic 0 disables it. The reset value of this latch bank is FFh,  
thereby making its use optional by default. The mask latch  
bank is not maskable. The bit 0 value of the mask latch bank  
does not affect the FGLEN functionality.  
Static Latch Values  
There are some latches in the table that have a static value  
(that is, 1, 0, or X). The latches that have a ‘1’ or ‘0’ must be  
configured with their corresponding value each time that their  
associated latch bank is configured. The latches that have an  
‘X’ are don’t cares and can be configured with any value  
Latch Types  
There are two types of latch banks: static (S) and dynamic (D).  
Each channel is configured by two static and one dynamic  
Table 3. Device Configuration and Control Latch Descriptions  
Name  
Signal Description  
RXRATEA  
RXRATEB  
RXRATEC  
RXRATED  
Receive Clock Rate Select. The initialization value of the RXRATEx latch = 1. RXRATEx selects the rate  
of the RXCLKx± clock output.  
When RXRATEx = 1, the RXCLKx± clock outputs are complementary clocks that follow the recovered  
clock operating at half the character rate. Data for the associated receive channels must latch alternately  
on the rising edge of RXCLKx+ and RXCLKx–.  
When RXRATEx = 0, the RXCLKx± clock outputs are complementary clocks that follow the recovered  
clock operating at the character rate. Data for the associated receive channels must latch on the rising  
edge of RXCLKx+ or falling edge of RXCLKx–.  
SDASEL1A[1:0]  
SDASEL1B[1:0]  
SDASEL1C[1:0]  
SDASEL1D[1:0]  
Primary Serial Data Input Signal Detector Amplitude Select. The initialization value of the  
SDASEL1x[1:0] latch = 10. SDASEL1x[1:0] selects the trip point for the detection of a valid signal for the  
INx1± Primary Differential Serial Data Inputs.  
When SDASEL1x[1:0] = 00, the Analog Signal Detector is disabled.  
When SDASEL1x[1:0] = 01, the typical p-p differential voltage threshold level is 140 mV.  
When SDASEL1x[1:0] = 10, the typical p-p differential voltage threshold level is 280 mV.  
When SDASEL1x[1:0] = 11, the typical p-p differential voltage threshold level is 420 mV.  
SDASEL2A[1:0]  
SDASEL2B[1:0]  
SDASEL2C[1:0]  
SDASEL2D[1:0]  
Secondary Serial Data Input Signal Detector Amplitude Select. The initialization value of the  
SDASEL2x[1:0] latch = 10. SDASEL2x[1:0] selects the trip point for the detection of a valid signal for the  
INx2± Secondary Differential Serial Data Inputs.  
When SDASEL2x[1:0] = 00, the Analog Signal Detector is disabled  
When SDASEL2x[1:0] = 01, the typical p-p differential voltage threshold level is 140 mV.  
When SDASEL2x[1:0] = 10, the typical p-p differential voltage threshold level is 280 mV.  
When SDASEL2x[1:0] = 11, the typical p-p differential voltage threshold level is 420 mV.  
TRGRATEA  
TRGRATEB  
TRGRATEC  
TRGRATED  
Training Clock Rate Select. The initialization value of the TRGRATEx latch = 0. TRGRATEx selects the  
clock multiplier for the training clock input to the associated CDR PLL. When TRGRATEx = 0, the  
associated TRGCLKx± input is not multiplied before it is passed to the CDR PLL. When TRGRATEx = 1,  
the TRGCLKx± input is multiplied by 2 before it is passed to the CDR PLL. TRGRATEx = 1 and SPDSELx  
= LOW is an invalid state and this combination is reserved.  
Document #: 38-02102 Rev. *C  
Page 14 of 27  
CYV15G0404RB  
Table 3. Device Configuration and Control Latch Descriptions (continued)  
Name  
Signal Description  
RXPLLPDA  
RXPLLPDB  
RXPLLPDC  
RXPLLPDD  
Receive Channel Enable. The initialization value of the RXPLLPDx latch = 0. RXPLLPDx selects whether  
the associated receive channel is enabled or powered down. RXPLLPDx = 0 powers down the associated  
receive PLL and analog circuitry. RXPLLPDx = 1 enables the associated receive PLL and analog circuitry.  
RXBISTA[1:0]  
RXBISTB[1:0]  
RXBISTC[1:0]  
RXBISTD[1:0]  
Receive Bist Disable / SMPTE Receive Enable. The initialization value of the RXBISTx[1:0] latch = 11.  
For SMPTE data reception, RXBISTx[1:0] should not remain in this initialization state (11). RXBISTx[1:0]  
selects whether receive BIST is disabled or enabled and sets the associated channel for SMPTE data  
reception. RXBISTx[1:0] = 01 disables the receiver BIST function and sets the associated channel to  
receive SMPTE data. RXBISTx[1:0] = 10 enables the receive BIST function and sets the associated  
channel to receive BIST data. RXBISTx[1:0] = 00 and RXBISTx[1:0] = 11 are invalid states.  
ROE2A  
ROE2B  
ROE2C  
ROE2D  
Reclocker Secondary Differential Serial Data Output Driver Enable. The initialization value of the  
ROE2x latch = 0. ROE2x selects whether the ROUT2± secondary differential output drivers are enabled  
or disabled. ROE2x = 1 enables the associated serial data output driver, allowing data to be transmitted  
from the transmit shifter. ROE2x = 0 disables the associated serial data output driver. When the config-  
uration interface disables a driver, the driver internally powers down to reduce device power. If both serial  
drivers for a channel are in this disabled state, the associated internal logic for that channel also powers  
down. A device reset (RESET sampled LOW) disables all output drivers.  
ROE1A  
ROE1B  
ROE1C  
ROE1D  
Reclocker Primary Differential Serial Data Output Driver Enable. The initialization value of the ROE1x  
latch = 0. ROE1x selects whether the ROUT1± primary differential output drivers are enabled or disabled.  
ROE1x = 1 enables the associated serial data output driver, allowing data to be transmitted from the  
transmit shifter. ROE1x = 0 disables the associated serial data output driver. When the configuration  
interface disables a driver, the driver internally powers down to reduce device power. If both serial drivers  
for a channel are in this disabled state, the associated internal logic for that channel also powers down.  
A device reset (RESET sampled LOW) disables all output drivers.  
GLEN[11..0]  
FGLEN[2..0]  
Global Enable. The initialization value of the GLENx latch = 1. The GLENx reconfigures several channels  
simultaneously in applications where several channels may have the same configuration. When GLENx  
= 1 for a given address, that address can participate in a global configuration. When GLENx = 0 for a  
given address, that address cannot participate in a global configuration.  
Force Global Enable. The initialization value of the FGLENx latch is NA. The FGLENx latch forces a  
GLobal ENable no matter what the setting is on the GLENx latch. If FGLENx = 1 for the associated Global  
channel, FGLEN forces the global update of the target latch banks.  
Device Configuration Strategy  
permits it. [This is an optional step if the default settings  
match the desired configuration.]  
Follow these steps to load the configuration latches on each  
channel:  
3. Set the dynamic bank of latches for the target channel.  
Enable the Receive PLLs and set each channel for SMPTE  
data reception (RXBISTx[1:0] = 01) or BIST data reception  
(RXBISTx[1:0] = 10). You can perform this step using a  
global operation, if the application permits it. [Required  
step.]  
1. Pulse RESET Low after device power up. This operation  
resets all four channels. Initialize the JTAG state machine  
to its reset state, as detailed in “JTAG Support” on page 17.  
2. Set the static latch banks for the target channel. You can  
perform this step using a global operation, if the application  
Document #: 38-02102 Rev. *C  
Page 15 of 27  
CYV15G0404RB  
Table 4. Device Control Latch Configuration Table  
Reset  
Value  
ADDR Channel Type  
DATA7  
DATA6  
DATA5  
DATA4  
DATA3  
DATA2  
DATA1  
DATA0  
0
A
S
S
D
S
S
D
S
S
D
S
S
D
S
S
D
D
1
0
X
X
0
0
RXRATEA  
GLEN0  
10111111  
(0000b)  
1
A
SDASEL2A[1] SDASEL2A[0] SDASEL1A[1] SDASEL1A[0]  
X
X
TRGRATEA  
X
GLEN1  
GLEN2  
GLEN3  
GLEN4  
GLEN5  
GLEN6  
GLEN7  
GLEN8  
GLEN9  
10101101  
10110011  
10111111  
10101101  
10110011  
10111111  
10101101  
10110011  
10111111  
10101101  
10110011  
N/A  
(0001b)  
2
A
RXBISTA[1]  
1
RXPLLPDA  
0
RXBISTA[0]  
X
X
X
ROE2A  
ROE1A  
(0010b)  
3
B
0
0
RXRATEB  
TRGRATEB  
X
(0011b)  
4
B
SDASEL2B[1] SDASEL2B[0] SDASEL1B[1] SDASEL1B[0]  
X
X
(0100b)  
5
B
RXBISTB[1]  
1
RXPLLPDB  
0
RXBISTB[0]  
X
X
X
ROE2B  
ROE1B  
(0101b)  
6
C
0
0
RXRATEC  
TRGRATEC  
X
(0110b)  
7
C
SDASEL2C[1] SDASEL2C[0] SDASEL1C[1] SDASEL1C[0]  
X
X
(0111b)  
8
C
D
RXBISTC[1]  
1
RXPLLPDC  
0
RXBISTC[0]  
X
X
X
ROE2C  
ROE1C  
(1000b)  
9
0
0
RXRATED  
(1001b)  
10  
(1010b)  
D
SDASEL2D[1] SDASEL2D[0] SDASEL1D[1] SDASEL1D[0]  
X
X
TRGRATED GLEN10  
GLEN11  
11  
(1011b)  
D
RXBISTD[1]  
1
RXPLLPDD  
0
RXBISTD[0]  
X
X
X
ROE2D  
ROE1D  
X
12  
(1100b)  
GLOBAL  
GLOBAL  
GLOBAL  
MASK  
0
X
0
X
RXRATEGL FGLEN0  
TRGRATEGL FGLEN1  
13  
(1101b)  
SDASEL2GL[1] SDASEL2GL[0] SDASEL1GL[1] SDASEL1GL[0]  
N/A  
14  
(1110b)  
RXBISTGL[1]  
D7  
RXPLLPDGL  
D6  
RXBISTGL[0]  
D5  
X
ROE2GL  
D3  
ROE1GL  
D2  
X
FGLEN2  
D0  
N/A  
15  
(1111b)  
D4  
D1  
11111111  
Document #: 38-02102 Rev. *C  
Page 16 of 27  
CYV15G0404RB  
JTAG controller does not enter any of the test modes after  
device power-up. In this JTAG reset state, the rest of the  
device will operate normally.  
JTAG Support  
The CYV15G0404RB contains a JTAG port to allow system  
level diagnosis of device interconnect. Of the available JTAG  
modes, boundary scan and bypass are supported. This  
capability is present only on the LVTTL inputs and outputs and  
the TRGCLKx± clock input. The high-speed serial inputs and  
outputs are not part of the JTAG test chain.  
Note The order of device reset (using RESET) and JTAG  
initialization does not matter.  
3-Level Select Inputs  
Each 3-Level select input reports as two bits in the scan  
register. These bits report the LOW, MID, and HIGH state of  
the associated input as 00, 10, and 11 respectively  
To ensure valid device operation after power-up (including  
non-JTAG operation), the JTAG state machine must also be  
initialized to a reset state. This must be done in addition to the  
device reset (using RESET). Initialize the JTAG state machine  
using TRST (assert it LOW and deassert it or leave it  
asserted), or by asserting TMS HIGH for at least 5 consecutive  
TCLK cycles. This is necessary in order to ensure that the  
JTAG ID  
The JTAG device ID for the CYV15G0404RB is ‘0C811069’x.  
Table 5. Receive BIST Status Bits  
Description  
{BISTSTx, RXDx[0],  
RXDx[1]}  
Receive BIST Status  
(Receive BIST = Enabled)  
000, 001  
010  
BIST Data Compare. Character compared correctly.  
BIST Last Good. Last Character of BIST sequence detected and valid.  
011  
Reserved.  
100  
BIST Last Bad. Last Character of BIST sequence detected invalid.  
101  
BIST Start. Receive BIST is enabled on this channel, but character compares have not yet  
commenced. This also indicates a PLL Out of Lock condition.  
110  
111  
BIST Error. While comparing characters, a mismatch was found in one or more of the character bits.  
BIST Wait. The receiver is comparing characters, but has not yet found the start of BIST character to  
enable the LFSR.  
Document #: 38-02102 Rev. *C  
Page 17 of 27  
CYV15G0404RB  
Figure 2. Receive BIST State Machine  
Monitor Data  
Receive BIST  
Received  
Detected LOW  
{BISTSTx, RXDx[0],  
RXDx[1]} =  
BIST_START (101)  
RX PLL  
Out of Lock  
{BISTSTx, RXDx[0], RXDx[1]} =  
BIST_WAIT (111)  
Start of  
BIST Detected  
No  
Yes, {BISTSTx, RXDx[0], RXDx[1]} =  
BIST_DATA_COMPARE (000, 001)  
Compare  
Next Character  
Mismatch  
{BISTSTx, RXDx[0], RXDx[1]} =  
BIST_DATA_COMPARE (000, 001)  
Match  
Auto-Abort  
Condition  
Yes  
No  
End-of-BIST  
State  
End-of-BIST  
State  
No  
Yes, {BISTSTx, RXDx[0], RXDx[1]} =  
BIST_LAST_BAD (100)  
Yes, {BISTSTx, RXDx[0], RXDx[1]} =  
BIST_LAST_GOOD (010)  
No, {BISTSTx, RXDx[0], RXDx[1]} =  
BIST_ERROR (110)  
Document #: 38-02102 Rev. *C  
Page 18 of 27  
CYV15G0404RB  
Static Discharge Voltage..........................................> 2000 V  
(MIL-STD-883, Method 3015)  
Maximum Ratings  
Excedding maximum ratings may shorten the device life. User  
guidelines are not tested  
Latch Up Current ....................................................> 200 mA  
Power Up Requirements  
Storage Temperature ..................................65°C to +150°C  
The CYV15G0404RB requires one power supply. The voltage  
on any input or I/O pin cannot exceed the power pin during  
power up.  
Ambient Temperature with  
Power Applied.............................................55°C to +125°C  
Supply Voltage to Ground Potential............... –0.5V to +3.8V  
DC Voltage Applied to LVTTL Outputs  
in High-Z State .......................................–0.5V to V + 0.5V  
Operating Range  
CC  
Range  
Ambient Temperature  
V
CC  
Output Current into LVTTL Outputs (LOW)..................60 mA  
Commercial  
0°C to +70°C  
+3.3V ±5%  
DC Input Voltage....................................–0.5V to V + 0.5V  
CC  
CYV15G0404RB DC Electrical Characteristics  
Parameter  
Description  
Test Conditions  
Min  
Max  
Unit  
LVTTL-compatible Outputs  
V
Output HIGH Voltage  
Output LOW Voltage  
I
I
= 4 mA, V = Min.  
2.4  
V
V
OHT  
OLT  
OH  
CC  
V
= 4 mA, V = Min.  
0.4  
–100  
20  
OL  
CC  
[6]  
I
Output Short Circuit Current  
V
= 0V , V = 3.3V  
–20  
–20  
mA  
µA  
OST  
OZL  
OUT  
OUT  
CC  
CC  
I
High-Z Output Leakage Current  
V
= 0V, V  
LVTTL-compatible Inputs  
V
V
Input HIGH Voltage  
Input LOW Voltage  
Input HIGH Current  
2.0  
V
+ 0.3  
V
IHT  
ILT  
CC  
–0.5  
0.8  
1.5  
V
I
TRGCLKx Input, V = V  
CC  
mA  
µA  
mA  
µA  
µA  
µA  
IHT  
IN  
Other Inputs, V = V  
+40  
–1.5  
–40  
IN  
CC  
I
Input LOW Current  
TRGCLKx Input, V = 0.0V  
IN  
ILT  
Other Inputs, V = 0.0V  
IN  
I
I
Input HIGH Current with Internal Pull Down  
Input LOW Current with Internal Pull Up  
V
V
= V  
CC  
+200  
–200  
IHPDT  
IN  
IN  
= 0.0V  
ILPUT  
LVDIFF Inputs: TRGCLKx±  
[7]  
V
V
V
V
Input Differential Voltage  
Highest Input HIGH Voltage  
Lowest Input LOW voltage  
Common Mode Range  
400  
1.2  
0.0  
1.0  
V
V
mV  
V
DIFF  
CC  
CC  
IHHP  
V
/2  
V
ILLP  
CC  
[8]  
V
– 1.2V  
V
COMREF  
CC  
3-Level Inputs  
V
Three-Level Input HIGH Voltage  
Min. V Max.  
0.87 * V  
0.47 * V  
0.0  
V
CC  
V
V
IHH  
IMM  
ILL  
CC  
CC  
V
V
Three-Level Input MID Voltage  
Three-Level Input LOW Voltage  
Input HIGH Current  
Min. V Max.  
0.53 * V  
0.13 * V  
200  
CC  
CC  
CC  
Min. V Max.  
V
CC  
CC  
I
I
I
V
V
V
= V  
CC  
µA  
µA  
µA  
IHH  
IN  
IN  
IN  
Input MID current  
= V /2  
–50  
50  
IMM  
ILL  
CC  
Input LOW current  
= GND  
–200  
Notes  
6. Tested one output at a time, output shorted for less than one second, less than 10% duty cycle.  
7. This is the minimum difference in voltage between the true and complement inputs required to ensure detection of a logic-1 or logic-0. A logic-1 exists when the  
true (+) input is more positive than the complement () input. A logic-0 exists when the complement () input is more positive than true (+) input.  
8. The common mode range defines the allowable range of TRGCLKx+ and TRGCLKxwhen TRGCLKx+ = TRGCLKx. This marks the zero-crossing between  
the true and complement inputs as the signal switches between a logic-1 and a logic-0.  
Document #: 38-02102 Rev. *C  
Page 19 of 27  
CYV15G0404RB  
CYV15G0404RB DC Electrical Characteristics (continued)  
Parameter  
Description  
Test Conditions  
Min  
Max  
Unit  
Differential CML Serial Outputs: ROUTA1±, ROUTA2±, ROUTB1±, ROUTB2±, ROUTC1±, ROUTC2±, ROUTD1±, ROUTD2±  
V
V
V
Output HIGH Voltage  
100differential load  
150differential load  
100differential load  
150differential load  
100differential load  
150differential load  
V
V
V
V
– 0.5  
– 0.5  
– 1.4  
– 1.4  
V
V
V
V
– 0.2  
– 0.2  
– 0.7  
– 0.7  
V
V
OHC  
OLC  
ODIF  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
(V Referenced)  
CC  
Output LOW Voltage  
V
(V Referenced)  
CC  
V
Output Differential Voltage  
|(OUT+) (OUT)|  
450  
560  
900  
mV  
mV  
1000  
Differential Serial Line Receiver Inputs: INA1±, INA2±, INB1±, INB2±, INC1±, INC2±, IND1±, IND2±  
[7]  
V
V
V
Input Differential Voltage |(IN+) (IN)|  
Highest Input HIGH Voltage  
Lowest Input LOW Voltage  
Input HIGH Current  
100  
1200  
mV  
V
DIFFs  
IHE  
V
CC  
V
– 2.0  
V
ILE  
CC  
I
I
V
V
= V Max.  
IHE  
1350  
+3.1  
µA  
µA  
V
IHE  
IN  
IN  
Input LOW Current  
= V Min.  
–700  
ILE  
ILE  
[9]  
COM  
VI  
Common Mode input range  
((V – 2.0V)+0.5)min,  
+1.25  
CC  
(V – 0.5V) max.  
CC  
Power Supply  
Typ  
Max  
1270  
1320  
1270  
1320  
[10,11]  
I
I
Max Power Supply Current  
TRGCLKx= Commercial  
910  
mA  
mA  
mA  
mA  
CC  
MAX  
Industrial  
[10,11]  
Typical Power Supply Current  
TRGCLKx= Commercial  
900  
CC  
125 MHz  
Industrial  
AC Test Loads and Waveforms  
3.3V  
RL = 100Ω  
R
L
R1  
R1 = 590Ω  
R2 = 435Ω  
CL 7 pF  
(Includes fixture and  
probe capacitance)  
(Includes fixture and  
probe capacitance)  
CL  
R2  
[12]  
(b) CML Output Test Load  
[12]  
(a) LVTTL Output Test Load  
VIHE  
3.0V  
VIHE  
2.0V  
0.8V  
2.0V  
0.8V  
80%  
80%  
Vth = 1.4V  
Vth = 1.4V  
20%  
20%  
VILE  
270 ps  
GND  
VILE  
270 ps  
1 ns  
1 ns  
[13]  
(d) CML/LVPECL Input Test Waveform  
(c) LVTTL Input Test Waveform  
Notes  
9. The common mode range defines the allowable range of INPUT+ and INPUTwhen INPUT+ = INPUT. This marks the zero crossing between the true and  
complement inputs as the signal switches between a logic-1 and a logic-0.  
10. Maximum I is measured with V = MAX, T = 25°C, with all channels and Serial Line Drivers enabled, sending a continuous alternating 01 pattern, and  
CC  
CC  
A
outputs unloaded.  
11. Typical I is measured under similar conditions except with V = 3.3V, T = 25°C, with all channels enabled and one Serial Line Driver for each transmit  
CC  
CC  
A
channel sending a continuous alternating 01 pattern. The redundant outputs on each channel are powered down and the parallel outputs are unloaded.  
12. Cypress uses constant current (ATE) load configurations and forcing functions. This figure is for reference only.  
13. The LVTTL switching threshold is 1.4V. All timing references are made relative to where the signal edges cross the threshold voltage.  
Document #: 38-02102 Rev. *C  
Page 20 of 27  
CYV15G0404RB  
CYV15G0404RB AC Electrical Characteristics  
Parameter  
Description  
Min  
Max  
Unit  
CYV15G0404RB Receiver LVTTL Switching Characteristics Over the Operating Range  
f
t
t
t
t
t
RXCLKx± Clock Output Frequency  
RXCLKx± Period = 1/f  
9.75  
6.66  
150  
102.56  
+1.0  
1.2  
MHz  
ns  
RS  
RXCLKP  
RXCLKD  
RXCLKR  
RS  
RXCLKx± Duty Cycle Centered at 50% (Full Rate and Half Rate)  
RXCLKx± Rise Time  
–1.0  
ns  
[14]  
[14]  
0.3  
ns  
RXCLKx± Fall Time  
0.3  
1.2  
ns  
RXCLKF  
[18]  
[19]  
[19]  
[19]  
[19]  
Status and Data Valid Time to RXCLKx± (RXRATEx = 0) (Full Rate)  
Status and Data Valid Time to RXCLKx± (RXRATEx = 1) (Half Rate)  
Status and Data Valid Time to RXCLKx± (RXRATEx = 0)  
Status and Data Valid Time to RXCLKx± (RXRATEx = 1)  
RECLKOx Clock Frequency  
5UI–2.0  
5UI–1.3  
5UI–1.8  
5UI–2.6  
19.5  
ns  
RXDv–  
RXDv+  
ROS  
ns  
[18]  
t
ns  
ns  
f
t
t
150  
51.28  
0
MHz  
ns  
RECLKOx Period = 1/f  
6.66  
RECLKO  
ROS  
RECLKOx Duty Cycle centered at 60% HIGH time  
–1.9  
ns  
RECLKOD  
CYV15G0404RB TRGCLKx Switching Characteristics Over the Operating Range  
TRGCLKx Clock Frequency  
TRGCLKx Period = 1/f  
f
19.5  
6.6  
150  
MHz  
ns  
ns  
ns  
ns  
ns  
%
TRG  
51.28  
TRGCLK  
REF  
t
TRGCLKx HIGH Time (TRGRATEx = 1)(Half Rate)  
TRGCLKx HIGH Time (TRGRATEx = 0)(Full Rate)  
TRGCLKx LOW Time (TRGRATEx = 1)(Half Rate)  
TRGCLKx LOW Time (TRGRATEx = 0)(Full Rate)  
TRGCLKx Duty Cycle  
5.9  
TRGH  
TRGL  
[14]  
2.9  
t
5.9  
[14]  
2.9  
[20]  
t
t
t
t
30  
70  
2
TRGD  
TRGR  
TRGF  
[14, 15, 16, 17]  
[14, 15, 16, 17]  
[21]  
TRGCLKx Rise Time (20%–80%)  
ns  
ns  
%
TRGCLKx Fall Time (20%–80%)  
2
TRGCLKx Frequency Referenced to Received Clock Frequency  
–0.15  
+0.15  
TRGRX  
CYV15G0404RB Bus Configuration Write Timing Characteristics Over the Operating Range  
t
t
t
Bus Configuration Data Hold  
0
ns  
ns  
ns  
DATAH  
DATAS  
WRENP  
Bus Configuration Data Setup  
Bus Configuration WREN Pulse Width  
10  
10  
CYV15G0404RB JTAG Test Clock Characteristics Over the Operating Range  
f
t
JTAG Test Clock Frequency  
JTAG Test Clock Period  
20  
MHz  
ns  
TCLK  
TCLK  
50  
Notes  
14. Tested initially and after any design or process changes that may affect these parameters, but not 100% tested.  
15. The ratio of rise time to falling time must not vary by greater than 2:1.  
16. For a given operating frequency, neither rise nor fall specification can be greater than 20% of the clock cycle period or the data sheet maximum time.  
17. All transmit AC timing parameters measured with 1ns typical rise time and fall time.  
18. Parallel data output specifications are only valid if all outputs are loaded with similar DC and AC loads.  
19. Receiver UI (Unit Interval) is calculated as 1/(f  
* 20) (when TRGRATEx = 1) or 1/(f  
* 10) (when TRGRATEx = 0). In an operating link this is equivalent to t .  
TRG  
TRG  
B
20. The duty cycle specification is a simultaneous condition with the t  
and t  
parameters. This means that at faster character rates the TRGCLKx± duty  
REFH  
REFL  
cycle cannot be as large as 30%–70%.  
21. TRGCLKx± has no phase or frequency relationship with the recovered clock(s) and only acts as a centering reference to reduce clock synchronization time.  
TRGCLKx± must be within ±1500 PPM (±0.15%) of the transmitter PLL reference (REFCLKx±) frequency. Although transmitting to a HOTLink II receiver channel  
necessitates the frequency difference between the transmitter and receiver reference clocks to be within ±1500-PPM, the stability of the crystal needs to be  
within the limits specified by the appropriate standard when transmitting to a remote receiver that is compliant to that standard.  
Document #: 38-02102 Rev. *C  
Page 21 of 27  
CYV15G0404RB  
CYV15G0404RB AC Electrical Characteristics (continued)  
Parameter  
CYV15G0404RB Device RESET Characteristics Over the Operating Range  
Device RESET Pulse Width  
CYV15G0404RB Reclocker Serial Output Characteristics Over the Operating Range  
Description  
Min  
Max  
Unit  
t
30  
ns  
RST  
Parameter  
Description  
Condition  
Min.  
5128  
50  
Max.  
660  
Unit  
ps  
t
t
Bit Time  
B
[14]  
CML Output Rise Time 2080% (CML Test Load)  
SPDSELx = HIGH  
SPDSELx = MID  
SPDSELx =LOW  
SPDSELx = HIGH  
SPDSELx = MID  
SPDSELx =LOW  
270  
ps  
RISE  
100  
180  
50  
500  
ps  
1000  
270  
ps  
[14]  
t
CML Output Fall Time 8020% (CML Test Load)  
ps  
FALL  
100  
180  
500  
ps  
1000  
ps  
PLL Characteristics  
Parameter  
Description  
Condition  
Min Typ  
Max Unit  
CYV15G0404RB Reclocker Output PLL Characteristics  
[14, 22]  
t
t
Reclocker Jitter Generation - SD Data Rate  
Reclocker Jitter Generation - HD Data Rate  
TRGCLKx = 27 MHz  
133  
107  
ps  
ps  
JRGENSD  
JRGENHD  
[14, 22]  
TRGCLKx = 148.5 MHz  
CYV15G0404RB Receive PLL Characteristics Over the Operating Range  
t
Receive PLL Lock to Input Data Stream (cold start)  
Receive PLL Lock to Input Data Stream  
Receive PLL Unlock Rate  
376k  
376k  
46  
UI  
UI  
UI  
RXLOCK  
t
RXUNLOCK  
Capacitance[14]  
Parameter  
Description  
Test Conditions  
T = 25°C, f = 1 MHz, V = 3.3V  
Max Unit  
C
C
TTL Input Capacitance  
PECL input Capacitance  
7
4
pF  
pF  
INTTL  
A
0
CC  
T = 25°C, f = 1 MHz, V = 3.3V  
INPECL  
A
0
CC  
Note  
22. Receiver input stream is BIST data from the transmit channel. This data is reclocked and output to a wide bandwidth digital sampling oscilloscope. The  
measurement was recorded after 10,000 histogram hits, time referenced to REFCLKx± of the transmit channel.  
Document #: 38-02102 Rev. *C  
Page 22 of 27  
CYV15G0404RB  
Switching Waveforms for the CYV15G0404RB HOTLink II Receiver  
Receive Interface  
Read Timing  
t
RXCLKP  
RXRATEx = 0  
RXCLKx+  
RXCLKx–  
RXDx[9:0]  
t
RXDV  
t
RXDV+  
Receive Interface  
Read Timing  
t
RXCLKP  
RXRATEx = 1  
RXCLKx+  
RXCLKx–  
RXDx[9:0]  
t
RXDV  
t
RXDV+  
CYV15G0404RB HOTLink II Bus Configuration Switching Waveforms  
Bus Configuration  
Write Timing  
ADDR[3:0]  
DATA[7:0]  
t
WRENP  
t
DATAS  
WREN  
t
DATAH  
Document #: 38-02102 Rev. *C  
Page 23 of 27  
CYV15G0404RB  
Table 6. Package Coordinate Signal Allocation  
Ball  
ID  
Ball  
ID  
Ball  
ID  
Signal Name  
Signal Type  
Signal Name  
Signal Type  
Signal Name  
Signal Type  
A01  
A02  
A03  
A04  
A05  
A06  
A07  
A08  
A09  
A10  
A11  
A12  
A13  
A14  
A15  
A16  
A17  
A18  
A19  
A20  
B01  
B02  
B03  
B04  
B05  
B06  
B07  
B08  
B09  
B10  
B11  
B12  
B13  
B14  
B15  
B16  
B17  
B18  
B19  
INC1–  
ROUTC1–  
INC2–  
CML IN  
CML OUT  
CML IN  
C07  
C08  
C09  
C10  
C11  
C12  
C13  
C14  
C15  
C16  
C17  
C18  
C19  
C20  
D01  
D02  
D03  
D04  
D05  
D06  
D07  
D08  
D09  
D10  
D11  
D12  
D13  
D14  
D15  
D16  
D17  
D18  
D19  
D20  
E01  
E02  
E03  
E04  
E17  
ULCC  
GND  
LVTTL IN PU  
GROUND  
F17  
F18  
F19  
F20  
G01  
G02  
G03  
G04  
G17  
G18  
G19  
G20  
H01  
H02  
H03  
H04  
H17  
H18  
H19  
H20  
J01  
VCC  
RXDB[0]  
RECLKOB  
RXDB[1]  
GND  
POWER  
LVTTL OUT  
LVTTL OUT  
LVTTL OUT  
GROUND  
DATA[7]  
DATA[5]  
DATA[3]  
DATA[1]  
GND  
LVTTL IN PU  
LVTTL IN PU  
LVTTL IN PU  
LVTTL IN PU  
GROUND  
ROUTC2–  
VCC  
CML OUT  
POWER  
CML IN  
IND1–  
WREN  
GND  
LVTTL IN PU  
GROUND  
ROUTD1–  
GND  
CML OUT  
GROUND  
CML IN  
VCC  
POWER  
GND  
GROUND  
IND2–  
SPDSELD  
VCC  
3-LEVEL SEL  
POWER  
SPDSELB  
NC  
3-LEVEL SEL  
NO CONNECT  
3-LEVEL SEL  
LVTTL OUT  
GROUND  
ROUTD2–  
INA1–  
CML OUT  
CML IN  
LDTDEN  
TRST  
LVTTL IN PU  
LVTTL IN PU  
GROUND  
SPDSELA  
RXDB[3]  
GND  
ROUTA1–  
GND  
CML OUT  
GROUND  
CML IN  
GND  
INA2–  
TDO  
LVTTL 3-S OUT  
LVTTL IN PD  
LVTTL IN PU  
LVTTL IN  
GND  
GROUND  
ROUTA2–  
VCC  
CML OUT  
POWER  
CML IN  
TCLK  
GND  
GROUND  
RESET  
INSELD  
INSELA  
VCC  
GND  
GROUND  
INB1–  
GND  
GROUND  
ROUTB1–  
INB2–  
CML OUT  
CML IN  
LVTTL IN  
GND  
GROUND  
POWER  
GND  
GROUND  
ROUTB2–  
INC1+  
CML OUT  
CML IN  
ULCA  
SPDSELC  
GND  
LVTTL IN PU  
3-LEVEL SEL  
GROUND  
GND  
GROUND  
GND  
GROUND  
ROUTC1+  
INC2+  
CML OUT  
CML IN  
J02  
GND  
GROUND  
DATA[6]  
DATA[4]  
DATA[2]  
DATA[0]  
GND  
LVTTL IN PU  
LVTTL IN PU  
LVTTL IN PU  
LVTTL IN PU  
GROUND  
J03  
GND  
GROUND  
ROUTC2+  
VCC  
CML OUT  
POWER  
CML IN  
J04  
GND  
GROUND  
J17  
BISTSTB  
RXDB[2]  
RXDB[7]  
RXDB[4]  
RXDC[4]  
LVTTL OUT  
LVTTL OUT  
LVTTL OUT  
LVTTL OUT  
LVTTL OUT  
PECL IN  
IND1+  
J18  
ROUTD1+  
GND  
CML OUT  
GROUND  
CML IN  
J19  
GND  
GROUND  
J20  
IND2+  
ULCB  
VCC  
LVTTL IN PU  
POWER  
K01  
ROUTD2+  
INA1+  
CML OUT  
CML IN  
K02 TRGCLKC–  
NC  
NO CONNECT  
POWER  
K03  
K04  
K17  
K18  
K19  
K20  
L01  
GND  
GND  
GROUND  
ROUTA1+  
GND  
CML OUT  
GROUND  
CML IN  
VCC  
GROUND  
SCANEN2  
TMEN3  
VCC  
LVTTL IN PD  
LVTTL IN PD  
POWER  
RXDB[5]  
RXDB[6]  
RXDB[9]  
LFIB  
LVTTL OUT  
LVTTL OUT  
LVTTL OUT  
LVTTL OUT  
LVTTL OUT  
PECL IN  
INA2+  
ROUTA2+  
VCC  
CML OUT  
POWER  
CML IN  
VCC  
POWER  
INB1+  
VCC  
POWER  
RXDC[5]  
ROUTB1+  
INB2+  
CML OUT  
CML IN  
VCC  
POWER  
L02 TRGCLKC+  
L03 LFIC  
VCC  
POWER  
LVTTL OUT  
Document #: 38-02102 Rev. *C  
Page 24 of 27  
CYV15G0404RB  
Table 6. Package Coordinate Signal Allocation (continued)  
Ball  
ID  
Ball  
ID  
Ball  
ID  
Signal Name  
Signal Type  
Signal Name  
Signal Type  
Signal Name  
Signal Type  
B20  
C01  
C02  
C03  
C04  
C05  
C06  
M03  
M04  
ROUTB2+  
TDI  
CML OUT  
LVTTL IN PU  
LVTTL IN PU  
LVTTL IN  
LVTTL IN  
POWER  
E18  
E19  
E20  
F01  
F02  
F03  
F04  
U03  
U04  
U05  
U06  
U07  
U08  
U09  
U10  
VCC  
VCC  
POWER  
POWER  
L04  
L17  
GND  
RXDB[8]  
RXCLKB+  
RXCLKB–  
GND  
GROUND  
LVTTL OUT  
LVTTL OUT  
LVTTL OUT  
GROUND  
TMS  
VCC  
POWER  
L18  
INSELC  
INSELB  
VCC  
RXDC[8]  
RXDC[9]  
VCC  
LVTTL OUT  
LVTTL OUT  
POWER  
L19  
L20  
M01  
M02  
W03  
W04  
W05  
W06  
W07  
W08  
W09  
W10  
W11  
W12  
W13  
W14  
W15  
W16  
W17  
RXDC[6]  
RXDC[7]  
LFID  
LVTTL OUT  
LVTTL OUT  
LVTTL OUT  
LVTTL OUT  
POWER  
ULCD  
VCC  
LVTTL IN PU  
POWER  
VCC  
POWER  
VCC  
POWER  
REPDOC  
LVTTL OUT  
PECL IN  
VCC  
POWER  
RXCLKD–  
VCC  
M17 TRGCLKB+  
M18 TRGCLKB–  
VCC  
POWER  
PECL IN  
RXDD[4]  
RXDD[3]  
GND  
LVTTL OUT  
LVTTL OUT  
GROUND  
GROUND  
LVTTL IN PU  
PECL IN  
RXDD[6]  
RXDD[0]  
GND  
LVTTL OUT  
LVTTL OUT  
GROUND  
M19  
M20  
N01  
N02  
N03  
N04  
N17  
N18  
N19  
N20  
P01  
P02  
P03  
P04  
P17  
P18  
P19  
P20  
R01  
R02  
R03  
R04  
R17  
R18  
R19  
R20  
T01  
T02  
REPDOB  
GND  
LVTTL OUT  
GROUND  
GROUND  
GROUND  
GROUND  
GROUND  
GROUND  
GROUND  
GROUND  
GROUND  
LVTTL OUT  
LVTTL OUT  
LVTTL OUT  
LVTTL OUT  
GROUND  
GROUND  
GROUND  
GROUND  
LVTTL OUT  
LVTTL OUT  
LVTTL OUT  
LVTTL OUT  
POWER  
GND  
GND  
ADDR [3]  
ADDR [1]  
RXCLKA+  
REPDOA  
GND  
LVTTL IN PU  
LVTTL IN PU  
LVTTL OUT  
LVTTL OUT  
GROUND  
GND  
ADDR [0]  
GND  
U11 TRGCLKD–  
GND  
U12  
U13  
U14  
U15  
U16  
U17  
U18  
U19  
U20  
V01  
V02  
V03  
V04  
V05  
V06  
V07  
V08  
V09  
V10  
GND  
GND  
GROUND  
GROUND  
GROUND  
POWER  
GND  
GND  
GND  
GND  
GROUND  
GND  
VCC  
VCC  
POWER  
GND  
VCC  
POWER  
VCC  
POWER  
RXDC[3]  
RXDC[2]  
RXDC[1]  
RXDC[0]  
GND  
RXDA[4]  
VCC  
LVTTL OUT  
POWER  
LFIA  
LVTTL OUT  
PECL IN  
W18 TRGCLKA+  
BISTSTA  
RXDA[0]  
VCC  
LVTTL OUT  
LVTTL OUT  
POWER  
W19  
W20  
Y01  
Y02  
Y03  
Y04  
Y05  
Y06  
Y07  
Y08  
Y09  
Y10  
Y11  
Y12  
Y13  
Y14  
RXDA[6]  
RXDA[3]  
VCC  
LVTTL OUT  
LVTTL OUT  
POWER  
GND  
VCC  
POWER  
VCC  
POWER  
GND  
VCC  
POWER  
RXDD[9]  
RXCLKD+  
VCC  
LVTTL OUT  
LVTTL OUT  
POWER  
GND  
RXDD[8]  
VCC  
LVTTL OUT  
POWER  
BISTSTC  
RECLKOC  
RXCLKC+  
RXCLKC–  
VCC  
RXDD[5]  
RXDD[1]  
GND  
LVTTL OUT  
LVTTL OUT  
GROUND  
LVTTL OUT  
LVTTL IN PU  
PECL IN  
RXDD[7]  
RXDD[2]  
GND  
LVTTL OUT  
LVTTL OUT  
GROUND  
BISTSTD  
ADDR [2]  
RECLKOD  
NC  
LVTTL OUT  
NO CONNECT  
GROUND  
VCC  
POWER  
VCC  
POWER  
V11 TRGCLKD+  
GND  
VCC  
POWER  
V12  
V13  
V14  
RECLKOA  
GND  
LVTTL OUT  
GROUND  
GROUND  
RXCLKA–  
GND  
LVTTL OUT  
GROUND  
VCC  
POWER  
VCC  
POWER  
GND  
GND  
GROUND  
Document #: 38-02102 Rev. *C  
Page 25 of 27  
CYV15G0404RB  
Table 6. Package Coordinate Signal Allocation (continued)  
Ball  
ID  
Ball  
ID  
Ball  
ID  
Signal Name  
Signal Type  
Signal Name  
Signal Type  
Signal Name  
Signal Type  
T03  
T04  
T17  
T18  
T19  
T20  
U01  
U02  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
POWER  
POWER  
POWER  
POWER  
POWER  
POWER  
POWER  
POWER  
V15  
V16  
V17  
V18  
V19  
V20  
W01  
W02  
VCC  
VCC  
POWER  
POWER  
Y15  
Y16  
Y17  
VCC  
VCC  
POWER  
POWER  
RXDA[9]  
RXDA[5]  
RXDA[2]  
RXDA[1]  
VCC  
LVTTL OUT  
LVTTL OUT  
LVTTL OUT  
LVTTL OUT  
POWER  
REPDOD  
LVTTL OUT  
PECL IN  
Y18 TRGCLKA–  
Y19  
Y20  
RXDA[8]  
RXDA[7]  
LVTTL OUT  
LVTTL OUT  
VCC  
POWER  
Ordering Information  
Package  
Name  
Operating  
Range  
Speed  
Ordering Code  
Package Type  
Standard CYV15G0404RB-BGC  
Standard CYV15G0404RB-BGXC  
BL256  
BL256  
256-Ball Thermally Enhanced Ball Grid Array  
Commercial  
Commercial  
Pb-Free 256-Ball Thermally Enhanced Ball Grid Array  
Package Diagram  
Figure 3. 256-Lead L2 Ball Grid Array (27 x 27 x 1.57 mm) BL256  
TOP VIEW  
0.20(4X)  
BOTTOM VIEW (BALL SIDE)  
A
27.00 0.13  
Ø0.15 M C  
Ø0.30 M C  
A
B
A1 CORNER I.D.  
A1 CORNER I.D.  
24.13  
Ø0.75 0.15(256X)  
20 18  
19  
16  
14  
12  
10  
8
6
4
2
17  
15  
13  
11  
9
7
5
3
1
A
B
C
D
E
F
G
H
J
R 2.5 Max (4X)  
K
L
M
N
P
R
T
A
U
V
W
Y
A
0.50 MIN.  
B
1.57 0.175  
0.97 REF.  
0.15  
C
26°  
0.15  
C
0.60 0.10  
0.20 MIN  
TOP OF MOLD COMPOUND  
TO TOP OF BALLS  
TYP.  
C
SEATING PLANE  
51-85123-*E  
SIDE VIEW  
SECTION A-A  
HOTLink is a registered trademark and HOTLink II is a trademark of Cypress Semiconductor. All product and company names  
mentioned in this document may be the trademarks of their respective holders.  
Document #: 38-02102 Rev. *C  
Page 26 of 27  
© Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be  
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its  
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
CYV15G0404RB  
Document History Page  
Document Title: CYV15G0404RB Independent Clock Quad HOTLink II™ Deserializing Reclocker  
Document Number: 38-02102  
ISSUE  
DATE  
ORIG. OF  
CHANGE  
REV.  
ECN NO.  
DESCRIPTION OF CHANGE  
**  
246850  
338721  
384307  
789283  
See ECN  
See ECN  
See ECN  
See ECN  
FRE  
SUA  
New Data Sheet  
Added Pb-Free package option availability  
Revised setup and hold times (t , t  
*A  
*B  
*C  
AGT  
)
RXDv– RXDv+  
KKVTMP  
Clarification to the need and procedure to initialize the JTAG controller  
(during test and non-test mode) to ensure valid device power-up. No  
changes have been made to the device specifications or character-  
estics.  
Document #: 38-02102 Rev. *C  
Page 27 of 27  

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