SP601 Hardware
User Guide
UG518 (v1.1) August 19, 2009
Download from Www.Somanuals.com. All Manuals Search And Download.
Revision History
The following table shows the revision history for this document.
Date
Version
1.0
Revision
07/15/2009
08/19/2009
Initial Xilinx release.
1.1
• Miscellaneous typographical edits and new user guide template.
UG518 (v1.1) August 19, 2009
SP601 Hardware User Guide
Download from Www.Somanuals.com. All Manuals Search And Download.
SP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
Download from Www.Somanuals.com. All Manuals Search And Download.
Table of Contents
Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Typographical. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Related Xilinx Documents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1. Spartan-6 XC6SLX16-2CSG324 FPGA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
I/O Voltage Rails . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2. 128 MB DDR2 Component Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3. SPI x4 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4. Linear Flash BPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5. 10/100/1000 Tri-Speed Ethernet PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6. USB-to-UART Bridge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7. IIC Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8-Kb NV Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8. Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Oscillator (Differential) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Oscillator Socket (Single-Ended, 2.5V or 3.3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
SMA Connectors (Differential) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9. VITA 57.1 FMC-LPC Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
10. Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
11. FPGA Awake LED and Suspend Jumper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
12. FPGA INIT and DONE LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
13. User I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
14. FPGA_PROG_B Pushbutton Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
AC Adapter and 5V Input Power Jack/Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Onboard Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
JTAG Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
SP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
5
Download from Www.Somanuals.com. All Manuals Search And Download.
6
SP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
Download from Www.Somanuals.com. All Manuals Search And Download.
Preface
About This Guide
This manual accompanies the Spartan®-6 FPGA SP601 Evaluation Board and contains
information about the SP601 hardware and software tools.
Guide Contents
This manual contains the following chapters:
•
Chapter 1, “SP601 Evaluation Board,” provides an overview of the embedded
development board and details the components and features of the SP601 board.
•
•
•
Additional Resources
To search the database of silicon and software questions and answers, or to create a
technical support case in WebCase, see the Xilinx website at:
Conventions
This document uses the following conventions. An example illustrates each convention.
Typographical
The following typographical conventions are used in this document:
Convention
Meaning or Use
Example
Messages, prompts, and
program files that the system
displays
Courier font
speed grade: - 100
Literal commands that you enter
in a syntactical statement
Courier bold
ngdbuild design_name
Commands that you select from
a menu
File → Open
Helvetica bold
Keyboard shortcuts
Ctrl+C
SP601 Hardware User Guide
7
UG518 (v1.1) August 19, 2009
Download from Www.Somanuals.com. All Manuals Search And Download.
Preface: About This Guide
Convention
Meaning or Use
Example
Variables in a syntax statement
for which you must supply
values
ngdbuild design_name
Italic font
See the User Guide for more
information.
References to other manuals
Emphasis in text
If a wire is drawn so that it
overlaps the pin of a symbol, the
two nets are not connected.
Items that are not supported or
reserved
Dark Shading
This feature is not supported
An optional entry or parameter.
However, in bus specifications, ngdbuild [option_name]
Square brackets [ ]
Braces { }
such as bus[7:0], they are
design_name
required.
A list of items from which you
must choose one or more
lowpwr ={on|off}
lowpwr ={on|off}
<directory name>
Separates items in a list of
choices
Vertical bar
|
User-defined variable or in code
samples
Angle brackets < >
IOB #1: Name = QOUT’
IOB #2: Name = CLKIN’
.
.
.
Vertical ellipsis
.
.
.
Repetitive material that has
been omitted
Repetitive material that has
been omitted
allow block block_name loc1
loc2 ... locn;
Horizontal ellipsis . . .
The prefix ‘0x’ or the suffix ‘h’
indicate hexadecimal notation
A read of address 0x00112975
returned 45524943h.
Notations
An ‘_n’ means the signal is
active low
usr_teof_nis active low.
Online Document
The following conventions are used in this document:
Convention
Meaning or Use
Example
See the section “Additional
Resources” for details.
Cross-reference link to a location
in the current document
Blue text
Refer to “Title Formats” in
Chapter 1 for details.
for the latest speed files.
Blue, underlined text
Hyperlink to a website (URL)
8
SP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
Download from Www.Somanuals.com. All Manuals Search And Download.
Chapter 1
SP601 Evaluation Board
Overview
The SP601 board enables hardware and software developers to create or evaluate designs
targeting the Spartan®-6 XC6SLX16-2CSG324 FPGA.
The SP601 provides board features for evaluating the Spartan-6 family that are common to
most entry-level development environments. Some commonly used features include a
DDR2 memory controller, a parallel linear flash, a tri-mode Ethernet PHY, general-
purpose I/O (GPIO), and a UART. Additional functionality can be added through the
Additional Information
Additional information and support material is located at:
This information includes:
•
•
•
Current version of this user guide in PDF format
Example design files for demonstration of Spartan-6 FPGA features and technology
Demonstration hardware and software configuration files for the SP601 linear and SPI
memory devices
•
•
•
•
•
Reference Design Files
Schematics in PDF format and DxDesigner schematic format
Bill of materials (BOM)
Printed-circuit board (PCB) layout in Allegro PCB format
Gerber files for the PCB (Many free or shareware Gerber file viewers are available on
the internet for viewing and printing these files.)
•
Additional documentation, errata, frequently asked questions, and the latest news
For information about the Spartan-6 family of FPGA devices, including product
highlights, data sheets, user guides, and application notes, see the Spartan-6 FPGA website
SP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
9
Download from Www.Somanuals.com. All Manuals Search And Download.
Chapter 1: SP601 Evaluation Board
Features
The SP601 board provides the following features:
•
•
•
•
•
•
♦
♦
♦
8Kb NV memory
External access 2-pin header
VITA 57.1 FMC-LPC connector
•
♦
♦
•
•
•
♦
♦
♦
FPGA_AWAKE
INIT
DONE
•
♦
♦
♦
♦
User LEDs
User DIP switch
User pushbuttons
GPIO male pin header
•
•
♦
♦
♦
3. SPI x4 Flash (both onboard and off-board)
•
10
SP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
Download from Www.Somanuals.com. All Manuals Search And Download.
Related Xilinx Documents
Block Diagram
Figure 1-1 shows a high-level block diagram of the SP601 and its peripherals.
X-Ref Target Figure 1-1
-
LEDs
DIP Switch
GPIO Header
FMC LPC
Expansion Connector
10/100/1000
Ethernet GMII
USB
JTAG Connector
DED
Bank 0
2.5 V
Parallel Flash
Spartan-6
DDR2
Bank 1
2.5V
Bank 3
1.8V
XC6SLX16
Differential Clock
Clock Socket
SMA Clock
U1
Pushbuttons
Bank 2
2.5V
IIC EEPROM
and Header
MODE
DIP Switch
SPI x4 or
External Config
USB UART
UG518_01_070809
Figure 1-1: SP601 Features and Banking
Related Xilinx Documents
Prior to using the SP601 Evaluation Board, users should be familiar with Xilinx resources.
See the following locations for additional documentation on Xilinx tools and solutions:
•
•
•
ISE: www.xilinx.com/ise
Answer Browser: www.xilinx.com/support
Intellectual Property: www.xilinx.com/ipcenter
SP601 Hardware User Guide
11
UG518 (v1.1) August 19, 2009
Download from Www.Somanuals.com. All Manuals Search And Download.
Chapter 1: SP601 Evaluation Board
Detailed Description
Figure 1-2 shows a board photo with numbered features corresponding to Table 1-1 and
the section headings in this document.
X-Ref Target Figure 1-2
-
14
13
15
9
8
2
1
16
7
11
4
8
3
5
12
10
6
13
Figure 1-2: SP601 Board Photo
The numbered features in Figure 1-2 correlate to the features and notes listed in Table 1-1.
Table 1-1: SP601 Features
Schematic
Number
Feature
Notes
XC6SLX16-2CSG324
Page
1
2
3
4
Spartan-6 FPGA
DDR2 Component
SPI x4 Flash and Headers
Linear Flash BPI
Hard memory controller w/ OCT
SPI select and External Headers
5
8
8
StrataFlash 8-bit (J3 device), 3 pins
shared w/ SPI x4
5
6
7
8
10/100/1000 Ethernet PHY GMII Marvell Alaska PHY
7
10
10
9
RS232 UART (USB Bridge)
IIC
Uses CP2103 Serial-to-USB connection
Goes to Header and VITA 57.1 FMC
Differential, Single-Ended, Differential
Clock, socket, SMA
12
SP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
Download from Www.Somanuals.com. All Manuals Search And Download.
Detailed Description
Table 1-1: SP601 Features (Cont’d)
Schematic
Page
Number
Feature
Notes
9
VITA 57.1 FMC-LPC
connector
LVDS signals, clocks, PRSNT
6
10
11
12
LEDs
Ethernet PHY Status
7
LED, Header
LEDs
FPGA Awake LED, Suspend Header
FPGA INIT, DONE
8
9
LED
User I/O (active-High)
9
DIP Switch
Pushbutton
12-pin (8 I/O) Header
User I/O (active-High)
9
13
User I/O, CPU_RESET (active-High)
9
6 pins x 2 male header with 8 I/Os
(active-High)
10
14
15
Pushbutton
USB JTAG
FPGA_PROG_B
9
Cypress USB to JTAG download cable
logic
14, 15
16
Onboard Power
Power Management
11,12,13
1. Spartan-6 XC6SLX16-2CSG324 FPGA
A Xilinx Spartan-6 XC6SLX16-2CSG324 FPGA is installed on the Embedded Development
Board.
Configuration
The SP601 supports configuration in the following modes:
•
•
•
•
Master SPI x4
Master SPI x4 with off-board device
BPI
JTAG (using the included USB-A to Mini-B cable)
For details on configuring the FPGA, see “Configuration Options.”
I/O Voltage Rails
There are four available banks on the LX16-CS324 device. Banks 0, 1, and 2 are connected
for 2.5V I/O. Bank 3 is used for the 1.8V DDR2 component memory interface of Spartan-6
FPGA’s hard memory controller. The voltage applied to the FPGA I/O banks used by the
SP601 board is summarized in Table 1-2.
Table 1-2: I/O Voltage Rail of FPGA Banks
FPGA Bank
I/O Voltage Rail
0
1
2.5V
2.5V
SP601 Hardware User Guide
13
UG518 (v1.1) August 19, 2009
Download from Www.Somanuals.com. All Manuals Search And Download.
Chapter 1: SP601 Evaluation Board
Table 1-2: I/O Voltage Rail of FPGA Banks (Cont’d)
FPGA Bank
I/O Voltage Rail
2
3
2.5V
1.8V
References
See the Xilinx Spartan-6 FPGA documentation for more information at
2. 128 MB DDR2 Component Memory
There are 128 MB of DDR2 memory available on the SP601 board. A 1-Gb Elpida
EDE1116ACBG (84-ball) DDR2 memory component is accessible through Bank 3 of the
LX16 device. The Spartan-6 FPGA hard memory controller is used for data transfer across
the DDR2 memory interface's 16-bit data path using SSTL18 signaling. The maximum data
rate supported is 800 Mb/s with a memory clock running at 400 MHz. Signal integrity is
maintained through DDR2 resistor terminations and memory on-die terminations (ODT),
as shown in Table 1-3 and Table 1-4.
Table 1-3: Termination Resistor Requirements
Signal Name
DDR2_A[14:0]
Board Termination
49.9 ohms to VTT
49.9 ohms to VTT
49.9 ohms to VTT
49.9 ohms to VTT
49.9 ohms to VTT
100 ohms to GND
4.7K ohms to GND
4.7K ohms to GND
On-Die Termination
DDR2_BA[2:0]
DDR2_RAS_N
DDR2_CAS_N
DDR2_WE_N
DDR2_CS_N
DDR2_CKE
DDR2_ODT
DDR2_DQ[15:0]
ODT
ODT
ODT
DDR2_UDQS[P,N],
DDR2_LDQS[P,N]
DDR2_UDM, DDR2_LDM
DDR2_CK[P,N]
100 ohm differential at
memory component
Notes:
1. Nominal value of V for DDR2 interface is 0.9V.
TT
Table 1-4: FPGA On-Chip (OCT) Termination External Resistor Requirements
FPGA U1 Pin
ZIO
FPGA Pin Number
Board Connection for OCT
No Connect
L6
C2
RZQ
100 ohms to GROUND
14
SP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
Download from Www.Somanuals.com. All Manuals Search And Download.
Detailed Description
Table 1-5 shows the connections and pin numbers for the DDR2 Component Memory.
Table 1-5: DDR2 Component Memory Connections
Memory U2
FPGA U1
Schematic Netname
Pin Number
Name
A0
J7
DDR2_A0
M8
M3
M7
N2
N8
N3
N7
P2
J6
DDR2_A1
DDR2_A2
DDR2_A3
DDR2_A4
DDR2_A5
DDR2_A6
DDR2_A7
DDR2_A8
DDR2_A9
DDR2_A10
DDR2_A11
DDR2_A12
A1
H5
L7
F3
A2
A3
A4
H4
H3
H6
D2
D1
F4
A5
A6
A7
P8
A8
P3
A9
M2
P7
A10
A11
A12
D3
G6
R2
L2
L1
K2
K1
H2
H1
J3
DDR2_DQ0
DDR2_DQ1
DDR2_DQ2
DDR2_DQ3
DDR2_DQ4
DDR2_DQ5
DDR2_DQ6
DDR2_DQ7
DDR2_DQ8
DDR2_DQ9
DDR2_DQ10
DDR2_DQ11
DDR2_DQ12
DDR2_DQ13
DDR2_DQ14
DDR2_DQ15
G8
G2
H7
H3
H1
H9
F1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
J1
F9
M3
M1
N2
N1
T2
T1
U2
U1
C8
C2
D7
D3
D1
D9
B1
B9
SP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
15
Download from Www.Somanuals.com. All Manuals Search And Download.
Chapter 1: SP601 Evaluation Board
Table 1-5: DDR2 Component Memory Connections (Cont’d)
Memory U2
FPGA U1
Schematic Netname
Pin Number
Name
BA0
F2
F1
E1
DDR2_BA0
L2
L3
L1
DDR2_BA1
DDR2_BA2
BA1
BA2
E3
L5
K5
K6
G3
G1
H7
L4
L3
P2
P1
K3
K4
DDR2_WE_B
DDR2_RAS_B
DDR2_CAS_B
DDR2_ODT
K3
K7
L7
K9
J8
WE
RAS
CAS
ODT
CK
DDR2_CLK_P
DDR2_CLK_N
DDR2_CKE
K8
K2
F7
E8
B7
A8
F3
B3
CK
CKE
DDR2_LDQS_P
DDR2_LDQS_N
DDR2_UDQS_P
DDR2_UDQS_N
DDR2_LDM
LDQS
LDQS
UDQS
UDQS
LDM
UDM
DDR2_UDM
Figure 1-3 provides the user constraints file (UCF) for the DDR2 SDRAM address pins,
including the I/O pin assignment and the I/O standard used.
X-Ref Target Figure 1-3
-
NET "DDR2_A12" LOC ="G6";| IOSTANDARD = SSTL18_II ;
NET "DDR2_A11" LOC ="D3";| IOSTANDARD = SSTL18_II ;
NET "DDR2_A10" LOC ="F4";| IOSTANDARD = SSTL18_II ;
NET "DDR2_A9" LOC ="D1"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_A8" LOC ="D2"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_A7" LOC ="H6"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_A6" LOC ="H3"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_A5" LOC ="H4"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_A4" LOC ="F3"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_A3" LOC ="L7"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_A2" LOC ="H5"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_A1" LOC ="J6"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_A0" LOC ="J7"; | IOSTANDARD = SSTL18_II ;
Figure 1-3: UCF Location Constraints for DDR2 SDRAM Address Inputs
16
SP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
Download from Www.Somanuals.com. All Manuals Search And Download.
Detailed Description
Figure 1-4 provides the UCF constraints for the DDR2 SDRAM data pins, including the
I/O pin assignment and I/O standard used.
X-Ref Target Figure 1-4
-
NET "DDR2_DQ15" LOC ="U1";| IOSTANDARD = SSTL18_II ;
NET "DDR2_DQ14" LOC ="U2";| IOSTANDARD = SSTL18_II ;
NET "DDR2_DQ13" LOC ="T1";| IOSTANDARD = SSTL18_II ;
NET "DDR2_DQ12" LOC ="T2";| IOSTANDARD = SSTL18_II ;
NET "DDR2_DQ11" LOC ="N1";| IOSTANDARD = SSTL18_II ;
NET "DDR2_DQ10" LOC ="N2";| IOSTANDARD = SSTL18_II ;
NET "DDR2_DQ9" LOC ="M1"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_DQ8" LOC ="M3"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_DQ7" LOC ="J1"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_DQ6" LOC ="J3"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_DQ5" LOC ="H1"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_DQ4" LOC ="H2"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_DQ3" LOC ="K1"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_DQ2" LOC ="K2"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_DQ1" LOC ="L1"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_DQ0" LOC ="L2"; | IOSTANDARD = SSTL18_II ;
Figure 1-4: UCF Location Constraints for DDR2 SDRAM Data I/O Pins
Figure 1-5 provides the UCF constraints for the DDR2 SDRAM control pins, including the
I/O pin assignment and the I/O standard used.
X-Ref Target Figure 1-5
-
NET "DDR2_WE_B" LOC ="E3"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_UDQS_P" LOC ="P2";| IOSTANDARD = SSTL18_II ;
NET "DDR2_UDQS_N" LOC ="P1";| IOSTANDARD = SSTL18_II ;
NET "DDR2_UDM" LOC ="K4"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_RAS_B" LOC ="L5"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_ODT" LOC ="K6"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_LDQS_P" LOC ="L4";| IOSTANDARD = SSTL18_II ;
NET "DDR2_LDQS_N" LOC ="L3";| IOSTANDARD = SSTL18_II ;
NET "DDR2_LDM" LOC ="K3"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_CLK_P" LOC ="G3"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_CLK_N" LOC ="G1"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_CKE" LOC ="H7"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_CAS_B" LOC ="K5"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_BA2" LOC ="E1"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_BA1" LOC ="F1"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_BA0" LOC ="F2"; | IOSTANDARD = SSTL18_II ;
Figure 1-5: UCF Location Constraints for DDR2 SDRAM Control Pins
References
See the Elpida DDR2 specifications for more information at
Also, see the Spartan-6 FPGA embedded hard memory controller block user guide at
SP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
17
Download from Www.Somanuals.com. All Manuals Search And Download.
Chapter 1: SP601 Evaluation Board
3. SPI x4 Flash
The Xilinx Spartan-6 FPGA hosts a SPI interface which is visible to the Xilinx iMPACT
configuration tool. The SPI memory device operates at 3.0V; the Spartan-6 FPGA I/Os are
3.3V tolerant and provide electrically compatible logic levels to directly access the SPI flash
through a 2.5V bank. The XC6SLX16-2CSG324 is a master device when accessing an
external SPI flash memory device.
The SP601 SPI interface has two parallel connected configuration options (see Figure 1-7):
an SPI X4 (Winbond W25Q64VSFIG) 64-Mb flash memory device and a flash
programming header (J12). J12 supports a user-defined SPI mezzanine board. The SPI
configuration source is selected via SPI select jumper J15. For details on configuring the
FPGA, see “Configuration Options.”
X-Ref Target Figure 1-6
-
J12
FPGA_PROG_B
1
2
3
FPGA_D2_MISO3
FPGA_D1_MISO2
SPI_CS_B
4
TMS
FPGA_MOSI_CSI_B_MISO0
FPGA_D0_DIN_MISO_MISO1
5
6
7
8
TDI
TDO
TCK
GND
Silkscreen
FPGA_CCLK
GND
9
VCC3V3
3V3
HDR_1X9
UG518_06_070809
Figure 1-6: J12 SPI Flash Programming Header
18
SP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
Download from Www.Somanuals.com. All Manuals Search And Download.
Detailed Description
X-Ref Target Figure 1-7
-
U1
FPGA SPI INTERFACE
J12
U17
DIN,DOUT,CCLK
SPI X4
FLASH
MEMORY
SPIX4_CS_B
SPI_CS_B
WINBOND
W25Q64VSFIG
2
1
ON = SPI X4 U17
OFF = SPI EXT. J12
SPI PROGRAM
J15
HEADER
SPI SELECT
JUMPER
UG518_07_070809
Figure 1-7: SPI Flash Interface Topology
Table 1-6: SPI x4 Memory Connections
SPI MEM U17
SPI HDR J12
FPGA U1
Schematic Netname
Pin
Pin #
Pin Name
Pin #
Pin Name
V2
V14
T14
V3
FPGA_PROG_B
1
2
3
4
5
6
7
8
9
FPGA_D2_MISO3
FPGA_D1_MISO2_R
SPI_CS_B
1
9
IO3_HOLD_B
IO2_WP_B
TMS
TDI
T13
R13
R15
FPGA_MOSI_CSI_B_MISO0
FPGA_D0_DIN_MISO_MISO1
FPGA_CCLK
15
8
DIN
IO1_DOUT
CLK
TDO
16
TCK
GND
VCC3V3
J15.2
SPIX4_CS_B
7
CS_B
SP601 Hardware User Guide
19
UG518 (v1.1) August 19, 2009
Download from Www.Somanuals.com. All Manuals Search And Download.
Chapter 1: SP601 Evaluation Board
Figure 1-8 provides the UCF constraints for the SPI serial flash PROM.
X-Ref Target Figure 1-8
-
NET "FPGA_D2_MISO3"
NET "SPI_CS_B"
NET "FPGA_D0_DIN_MISO_MISO1"
NET "FPGA_D1_MISO2"
NET "FPGA_MOSI_CSI_B_MISO0"
NET "FPGA_CCLK"
LOC = "V14";
LOC = "V3";
LOC = "R13";
LOC = "T14";
LOC = "T13";
LOC = "R15";
Figure 1-8: UCF Location Constraints for BPI Flash Connections
References
See the XPS Serial Peripheral Interface specification for more information at
4. Linear Flash BPI
An 8-bit (16 MB) Numonyx linear flash memory (TE 28F128J3D-75) (J3D type) is used to
provide non-volatile bitstream, code, and data storage. The J3D devices operate at 3.0V; the
Spartan-6 FPGA I/Os are 3.3V tolerant and provide electrically compatible logic levels to
directly access the linear flash BPI through a 2.5V bank. For details on configuring the
FPGA, see “Configuration Options.”
X-Ref Target Figure 1-9
-
U1
U10
ADDR, DATA, CTRL
FPGA
BPI FLASH
INTERFACE
NUMONYX TYPE J3vD
T28F128J3D-75
UG518_09_070809
Figure 1-9: Linear Flash BPI Interface
Table 1-7: BPI Memory Connections
BPI Memory U10
FPGA U1 Pin
Schematic Netname
Pin Number
Pin
A0
A1
A2
A3
A4
A5
K18
K17
J18
FLASH_A0
FLASH_A1
FLASH_A2
FLASH_A3
FLASH_A4
FLASH_A5
32
28
27
26
25
24
J16
G18
G16
20
SP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
Download from Www.Somanuals.com. All Manuals Search And Download.
Detailed Description
BPI Memory U10
Table 1-7: BPI Memory Connections (Cont’d)
FPGA U1 Pin
Schematic Netname
Pin Number
Pin
A6
H16
H15
H14
H13
F18
FLASH_A6
23
22
20
19
18
17
13
12
11
10
8
FLASH_A7
FLASH_A8
FLASH_A9
FLASH_A10
FLASH_A11
FLASH_A12
FLASH_A13
FLASH_A14
FLASH_A15
FLASH_A16
FLASH_A17
FLASH_A18
FLASH_A19
FLASH_A20
FLASH_A21
FLASH_A22
FLASH_A23
FLASH_A24
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
F17
K13
K12
E18
E16
G13
H12
D18
D17
G14
F14
7
6
5
4
3
C18
C17
F16
1
30
56
R13
T14
V14
U5
V5
FPGA_D0_DIN_MISO_MISO1
FPGA_D1_MISO2
FPGA_D2_MISO3
FLASH_D3
33
35
38
40
44
46
49
51
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
FLASH_D4
R3
FLASH_D5
T3
FLASH_D6
R5
FLASH_D7
M16
L18
FLASH_WE_B
FLASH_OE_B
55
54
WE_B
OE_B
SP601 Hardware User Guide
21
UG518 (v1.1) August 19, 2009
Download from Www.Somanuals.com. All Manuals Search And Download.
Chapter 1: SP601 Evaluation Board
Table 1-7: BPI Memory Connections (Cont’d)
FPGA U1 Pin Schematic Netname
BPI Memory U10
Pin Number
Pin
CE0
L17
B3
FLASH_CE_B
FMC_PWR_GOOD_FLASH_RST_B
14
16
RP_B
Note: Memory U10 pin 56 address A24 is not connected on the 16 MB device. It is made available
for larger density devices.
X-Ref Target Figure 1-10
-
NET "FLASH_A0"
LOC = "K18";
LOC = "K17";
LOC = "J18";
LOC = "J16";
LOC = "G18";
LOC = "G16";
LOC = "H16";
LOC = "H15";
LOC = "H14";
LOC = "H13";
LOC = "F18";
LOC = "F17";
LOC = "K13";
LOC = "K12";
LOC = "E18";
LOC = "E16";
LOC = "G13";
LOC = "H12";
LOC = "D18";
LOC = "D17";
LOC = "G14";
LOC = "F14";
LOC = "C18";
LOC = "C17";
LOC = "F16";
NET "FLASH_A1"
NET "FLASH_A2"
NET "FLASH_A3"
NET "FLASH_A4"
NET "FLASH_A5"
NET "FLASH_A6"
NET "FLASH_A7"
NET "FLASH_A8"
NET "FLASH_A9"
NET "FLASH_A10"
NET "FLASH_A11"
NET "FLASH_A12"
NET "FLASH_A13"
NET "FLASH_A14"
NET "FLASH_A15"
NET "FLASH_A16"
NET "FLASH_A17"
NET "FLASH_A18"
NET "FLASH_A19"
NET "FLASH_A20"
NET "FLASH_A21"
NET "FLASH_A22"
NET "FLASH_A23"
NET "FLASH_A24"
NET "FPGA_D0_DIN_MISO_MISO1"
NET "FPGA_D1_MISO2"
NET "FPGA_D2_MISO3"
NET "FLASH_D3"
NET "FLASH_D4"
NET "FLASH_D5"
LOC = "R13";
LOC = "T14";
LOC = "V14";
LOC = "U5";
LOC = "V5";
LOC = "R3";
LOC = "T3";
LOC = "R5";
NET "FLASH_D6"
NET "FLASH_D7"
NET "FLASH_WE_B"
NET "FLASH_OE_B"
NET "FLASH_CE_B"
NET "FMC_PWR_GOOD_FLASH_RST_B"
LOC = "M16";
LOC = "L18";
LOC = "L17";
LOC = "B3";
Figure 1-10: UCF Location Constraints for BPI Flash Connections
References
See the Numonyx Flash Memory specifications for more information at
In addition, see the Xilinx Spartan-6 Configuration User Guide for more information at
22
SP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
Download from Www.Somanuals.com. All Manuals Search And Download.
Detailed Description
5. 10/100/1000 Tri-Speed Ethernet PHY
The SP601 uses the onboard Marvell Alaska PHY device (88E1111) for Ethernet
communications at 10, 100, or 1000 Mb/s. The board supports a GMII/MII interface from
the FPGA to the PHY. The PHY connection to a user-provided Ethernet cable is through a
Halo HFJ11-1G01E RJ-45 connector with built-in magnetics.
On power-up, or on reset, the PHY is configured to operate in GMII mode with PHY
address 0b00111 using the settings shown in Table 1-8. These settings can be overwritten
via software commands passed over the MDIO interface.
Table 1-8: PHY Configuration Pins
Connection on
Board
Bit[2]
Bit[1]
Bit[0]
Pin
Definition and Value Definition and Value Definition and Value
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
VCC 2.5V
Ground
PHYADR[2] = 1
ENA_PAUSE = 0
ANEG[3] = 1
PHYADR[1] = 1
PHYADR[4] = 0
ANEG[2] = 1
PHYADR[0] = 1
PHYADR[3] = 0
ANEG[1] = 1
DIS_125 = 1
VCC 2.5V
VCC 2.5V
ANEG[0] = 1
ENA_XC = 1
VCC 2.5V
HWCFG_MD[2] = 1 HWCFG_MD[1] = 1 HWCFG_MD[0] = 1
VCC 2.5V
DIS_FC = 1
DIS_SLEEP = 1
INT_POL = 1
HWCFG_MD[3] = 1
75/50 OHM = 0
PHY_LED_RX
SEL_BDT = 0
Table 1-9: PHY Connections
FPGA U1
Schematic Netname
Pin
U3 M88E111
P16
N14
J13
PHY_MDIO
PHY_MDC
PHY_INT
33
35
32
L13
M13
L14
L16
P17
N18
M14
U18
U17
T18
T17
N16
N15
PHY_RESET
PHY_CRS
36
115
114
7
PHY_COL
PHY_RXCLK
PHY_RXER
PHY_RXCTL_RXDV
PHY_RXD0
PHY_RXD1
PHY_RXD2
PHY_RXD3
PHY_RXD4
PHY_RXD5
PHY_RXD6
8
4
3
128
126
125
124
123
121
SP601 Hardware User Guide
23
UG518 (v1.1) August 19, 2009
Download from Www.Somanuals.com. All Manuals Search And Download.
Chapter 1: SP601 Evaluation Board
Table 1-9: PHY Connections (Cont’d)
FPGA U1
Pin
Schematic Netname
U3 M88E111
P18
A9
B9
A8
B8
F8
PHY_RXD7
120
14
10
13
16
18
19
20
24
25
26
28
29
PHY_TXC_GTXCLK
PHY_TXCLK
PHY_TXER
PHY_TXCTL_TXEN
PHY_TXD0
G8
A6
B6
E6
F7
PHY_TXD1
PHY_TXD2
PHY_TXD3
PHY_TXD4
PHY_TXD5
A5
C5
PHY_TXD6
PHY_TXD7
X-Ref Target Figure 1-11
-
NET "PHY_COL"
LOC = "L14";
NET "PHY_CRS"
NET "PHY_INT"
NET "PHY_MDC"
LOC = "M13";
LOC = "J13";
LOC = "N14";
LOC = "P16";
LOC = "L13";
LOC = "L16";
LOC = "N18";
LOC = "M14";
LOC = "U18";
LOC = "U17";
LOC = "T18";
LOC = "T17";
LOC = "N16";
LOC = "N15";
LOC = "P18";
LOC = "P17";
LOC = "B9";
LOC = "B8";
LOC = "A9";
LOC = "F8";
LOC = "G8";
LOC = "A6";
LOC = "B6";
LOC = "E6";
LOC = "F7";
LOC = "A5";
LOC = "C5";
LOC = "A8";
NET "PHY_MDIO"
NET "PHY_RESET"
NET "PHY_RXCLK"
NET "PHY_RXCTL_RXDV"
NET "PHY_RXD0"
NET "PHY_RXD1"
NET "PHY_RXD2"
NET "PHY_RXD3"
NET "PHY_RXD4"
NET "PHY_RXD5"
NET "PHY_RXD6"
NET "PHY_RXD7"
NET "PHY_RXER"
NET "PHY_TXCLK"
NET "PHY_TXCTL_TXEN"
NET "PHY_TXC_GTXCLK"
NET "PHY_TXD0"
NET "PHY_TXD1"
NET "PHY_TXD2"
NET "PHY_TXD3"
NET "PHY_TXD4"
NET "PHY_TXD5"
NET "PHY_TXD6"
NET "PHY_TXD7"
NET "PHY_TXER"
Figure 1-11: UCF Location Constraints for PHY Connections
24
SP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
Download from Www.Somanuals.com. All Manuals Search And Download.
Detailed Description
References
See the Marvell Alaska Gigabit Ethernet Transceiver product page for more information at
Also, see the Xilinx Tri-Mode Ethernet MAC User Guide at
6. USB-to-UART Bridge
The SP601 contains a Silicon Labs CP2103GM USB-to-UART bridge device (U4) which
allows connection to a host computer with a USB cable. The USB cable is supplied in this
evaluation kit (Type A end to host computer, Type Mini-B end to SP601 connector J9).
Table 1-10 details the SP601 J9 pinout.
Xilinx UART IP is expected to be implemented in the FPGA fabric. The FPGA supports the
USB-to-UART bridge using four signal pins, transmit (TX), receive (RX), Request to Send
(RTS), and Clear to Send (CTS).
Silicon Labs provides royalty-free Virtual COM Port (VCP) drivers which permit the
CP2103GM USB-to-UART bridge to appear as a COM port to host computer
communications application software (for example, HyperTerm or TeraTerm). The VCP
device driver must be installed on the host PC prior to establishing communications with
the SP601. Refer to the SP601 Getting Started Guide for driver installation instructions.
Table 1-10: USB Type B Pin Assignments and Signal Definitions
USB Connector
Signal Name
Description
Pin
1
VBUS
+5V from host system (not used)
Bidirectional differential serial data (N-side)
Bidirectional differential serial data (P-side)
Signal ground
2
USB_DATA_N
USB_DATA_P
GROUND
3
4
Table 1-11: CP2103GM Connections
FPGA U1
Schematic Netname
Pin
U4 CP2103GM
U10
T5
USB_1_CTS
USB_1_RTS
USB_1_RX
USB_1_TX
22
23
24
25
L12
K14
X-Ref Target Figure 1-12
-
NET "USB_1_CTS"
NET "USB_1_RTS"
NET "USB_1_RX"
NET "USB_1_TX"
LOC = "U10";
LOC = "T5";
LOC = "L12";
LOC = "K14";
Figure 1-12: UCF Location Constraints for CP2103GM Connections
SP601 Hardware User Guide
25
UG518 (v1.1) August 19, 2009
Download from Www.Somanuals.com. All Manuals Search And Download.
Chapter 1: SP601 Evaluation Board
References
Technical information on the Silicon Labs CP2103GM and the VCP drivers can be found on
In addition, see some of the Xilinx UART IP specifications at:
•
•
•
7. IIC Bus
The SP601 IIC bus hosts four items:
•
FPGA U1 IIC interface
•
•
•
2-pin IIC external access header
8-Kb NV Memory
VITA 57.1 FMC Connector J1
The SP601 IIC bus topology is shown in Figure 1-13.
X-Ref Target Figure 1-13
-
FMC-LPC
GA0=1
GA1=0
VITA 57.1
FMC-LPC
J1
C31
C30
U1
U7
ST MICRO
M24 C08-WDW6TP
IIC_SDA_MAIN
IIC_SCL_MAIN
FPGA IIC
INTERFACE
Address range
54-56
0b1010100-
0b1010110
2
1
J16
IIC EXTERNAL
ACCESS
UG518_13_070809
CONNECTOR
Figure 1-13: IIC Bus Topology
The IIC Bus on the SP601 provides access to a 2-pin header, the onboard 8-Kb EEPROM,
and the VITA 57.1 FMC interface. The user must ensure there are no IIC address conflicts
with the onboard EEPROM address when attaching additional IIC devices via FMC or the
IIC 2-pin header. Note that FMC Mezzanine cards are designed with 2-Kb IIC EEPROMs
and will not conflict with the Carrier Card (SP601) 8-Kb EEPROM address range. This is
because 2-Kb EEPROMs reside below the 8-Kb EEPROM space. See the VITA 57.1
specification along with any IIC 2-Kbit EEPROM data sheet for more details.
26
SP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
Download from Www.Somanuals.com. All Manuals Search And Download.
Detailed Description
8-Kb NV Memory
The SP601 hosts a 8-Kb ST Microelectronics M24C08-WDW6TP IIC parameter storage
memory device (U7). The IIC address of U7 is 0b1010100, and U7 is not write protected
(WP pin 7 is tied to GND).
Table 1-12: IIC Memory Connections
SPI Memory U7
FPGA U1 Pin
Schematic Netname
Number
Pin Number
Pin
A0
Not Applicable Tied to GND
1
2
3
5
6
7
Not Applicable Tied to GND
A1
Not Applicable Pulled up (0 ohm) to VCC3V3
A2
N10
P11
IIC_SDA_MAIN
IIC_SCL_MAIN
SDA
SCL
WP
Not Applicable Tied to GND
X-Ref Target Figure 1-14
-
NET "IIC_SCL_MAIN"
NET "IIC_SDA_MAIN"
LOC = "P11";
LOC = "N10";
Figure 1-14: UCF Location Constraints for IIC Connections
References
See the ST Micro M24C08-WDW6TP data sheet for more information at
In addition, see the Xilinx XPS IIC Bus Interface specification at
8. Clock Generation
There are three clock sources available on the SP601.
Oscillator (Differential)
The SP601 has one 2.5V LVDS differential 200 MHz oscillator (U5) soldered onto the board
and wired to an FPGA global clock input.
•
•
Crystal oscillator: Epson EG2121CA
PPM frequency jitter: 50 ppm
X-Ref Target Figure 1-15
-
NET "SYSCLK_N"
NET "SYSCLK_P"
LOC = "K16";
LOC = "K15";
Figure 1-15: UCF Location Constraints for Oscillator Connections
References
For more details, see the Epson data sheet at
SP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
27
Download from Www.Somanuals.com. All Manuals Search And Download.
Chapter 1: SP601 Evaluation Board
Oscillator Socket (Single-Ended, 2.5V or 3.3V)
One populated single-ended clock socket (X2) is provided for user applications. The option
of 3.3V or 2.5V power may be selected via a 0 ohm resistor selection. The SP601 board is
shipped with a 27MHz 2.5V oscillator installed.
X-Ref Target Figure 1-16
-
NET "USER_CLOCK"
LOC = "V10";
Figure 1-16: UCF Location Constraints for Oscillator Socket Connections
SMA Connectors (Differential)
A high-precision clock signal can be provided to the FPGA using differential clock signals
through the onboard 50-ohm SMA connectors J7(P)/J8(N).
X-Ref Target Figure 1-17
-
NET "SMACLK_N"
NET "SMACLK_P"
LOC = "H18";
LOC = "H17";
Figure 1-17: UCF Location Constraints for SMA Connectors Connections
9. VITA 57.1 FMC-LPC Connector
The VITA 57.1 FMC expansion connector (J1) on the SP601 implements the VITA 57.1.1 LPC
format of the VITA 57.1 FMC standard specification. The VITA 57.1 FMC-LPC connector
provides 68 single-ended (34 differential) user-defined signals (Table 1-13). The VITA 57.1
FMC standard calls for two connector densities: a High Pin Count (HPC) and a Low Pin
Count (LPC) implementation. A common 10 x 40 position (400 pin locations) connector
form factor is used for both versions. The HPC version has 400 pins present, the LPC
version, 160 pins. The Samtec connector system is rated for signaling speeds up to 9 GHz
(18 Gb/s) based on a -3dB insertion loss point within a two-level signaling environment.
compliant VITA 57.1 FMC-LPC connector (ASP-134603-01) and its mate.
Note that the SP601 board FMC-LPC connector J1 VADJ voltage is FIXED at 2.5V (non-
adjustable). This rail cannot be turned off. The SP601 VITA 57.1 FMC interface is
compatible with 2.5V Mezzanine Cards capable of supporting 2.5V VADJ.
The SP601 supports all FMC LA Bus connections available on the FMC LPC connector,
(LA[00:33]) along with all available FMC M2C clock pairs (CLK0_M2C_P/N and
CLK1_M2C_P/N). The SP601 does not support the FMC DP Bus connections since the
SP601 does not support any Gigabit Transceivers on the FMC DP Bus. Therefore,
DP0_C2M_P/N, DP0_M2C_P/N and GBTCLK0_M2C_P/N are not supported by the
SP601 FMC interface.
For more details about FMC, see the VITA57.1 specification available at
28
SP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
Download from Www.Somanuals.com. All Manuals Search And Download.
Detailed Description
Table 1-13: LPC Pinout
K
J
H
G
F
E
D
PG_C2M
GND
C
B
A
1
2
3
4
5
6
7
8
9
NC NC
VREF_A_M2C
GND
NC NC
GND
NC NC
NC NC PRSNT_M2C_L
CLK1_M2C_P NC NC
CLK1_M2C_N NC NC
DP0_C2M_P NC NC
DP0_C2M_N NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
GND
CLK0_M2C_P
CLK0_M2C_N
GND
GND
GND
GND
NC NC
GBTCLK0_M2C_P
GND
GND
NC NC
NC NC
NC NC GBTCLK0_M2C_N
LA00_P_CC
LA00_N_CC
GND
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
GND
GND
DP0_M2C_P NC NC
DP0_M2C_N NC NC
LA02_P
LA02_N
GND
LA01_P_CC
LA01_N_CC
GND
GND
GND
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
LA03_P
LA03_N
GND
10 NC NC
11 NC NC
12 NC NC
13 NC NC
14 NC NC
15 NC NC
16 NC NC
17 NC NC
18 NC NC
19 NC NC
20 NC NC
21 NC NC
22 NC NC
23 NC NC
24 NC NC
25 NC NC
26 NC NC
27 NC NC
28 NC NC
29 NC NC
30 NC NC
31 NC NC
32 NC NC
33 NC NC
LA04_P
LA04_N
GND
LA06_P
LA06_N
GND
LA05_P
LA05_N
GND
LA08_P
LA08_N
GND
LA07_P
LA07_N
GND
GND
LA09_P
LA09_N
GND
LA10_P
LA10_N
GND
LA12_P
LA12_N
GND
LA11_P
LA11_N
GND
LA13_P
LA13_N
GND
GND
LA16_P
LA16_N
GND
LA14_P
LA14_N
GND
LA15_P
LA15_N
GND
LA17_P_CC
LA17_N_CC
GND
LA20_P
LA20_N
GND
GND
LA19_P
LA19_N
GND
LA18_P_CC
LA23_P
LA23_N
GND
LA18_N_CC NC NC
LA22_P
LA22_N
GND
GND
GND
LA27_P
LA27_N
GND
GND
SCL
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
LA21_P
LA21_N
GND
LA26_P
LA26_N
GND
LA25_P
LA25_N
GND
LA24_P
LA24_N
GND
TCK
LA29_P
LA29_N
GND
TDI
LA28_P
LA28_N
GND
TDO
SDA
3P3VAUX
TMS
GND
GND
LA31_P
SP601 Hardware User Guide
29
UG518 (v1.1) August 19, 2009
Download from Www.Somanuals.com. All Manuals Search And Download.
Chapter 1: SP601 Evaluation Board
Table 1-13: LPC Pinout (Cont’d)
K
J
H
G
F
E
D
C
B
A
34 NC NC
35 NC NC
36 NC NC
37 NC NC
38 NC NC
39 NC NC
40 NC NC
LA30_P
LA30_N
GND
LA31_N
GND
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
TRST_L
GA1
GA0
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
12P0V
GND
12P0V
GND
3P3V
GND
LA33_P
LA33_N
GND
3P3V
GND
3P3V
GND
3P3V
LA32_P
LA32_N
GND
VADJ
VADJ
GND
30
SP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
Download from Www.Somanuals.com. All Manuals Search And Download.
Detailed Description
X-Ref Target - Figure 1-18
NET "FMC_CLK0_M2C_N"
LOC = "A10";
LOC = "C10";
LOC = "V9";
LOC = "T9";
LOC = "C9";
LOC = "D9";
LOC = "C11";
LOC = "D11";
LOC = "A15";
LOC = "C15";
LOC = "A13";
LOC = "C13";
LOC = "A16";
LOC = "B16";
LOC = "A14";
LOC = "B14";
LOC = "C12";
LOC = "D12";
LOC = "E8";
LOC = "E7";
LOC = "E11";
LOC = "F11";
LOC = "F10";
LOC = "G11";
LOC = "C8";
LOC = "D8";
LOC = "A12";
LOC = "B12";
LOC = "C6";
LOC = "D6";
LOC = "A11";
LOC = "B11";
LOC = "A2";
LOC = "B2";
LOC = "F9";
LOC = "G9";
LOC = "A7";
LOC = "C7";
LOC = "T8";
LOC = "R8";
LOC = "T10";
LOC = "R10";
LOC = "P7";
LOC = "N6";
LOC = "P8";
LOC = "N7";
LOC = "V4";
LOC = "T4";
LOC = "T7";
LOC = "R7";
LOC = "P6";
LOC = "N5";
LOC = "V8";
LOC = "U8";
LOC = "N11";
LOC = "M11";
LOC = "V7";
LOC = "U7";
LOC = "T11";
LOC = "R11";
LOC = "V11";
LOC = "U11";
LOC = "N8";
LOC = "M8";
LOC = "V12";
LOC = "T12";
LOC = "V6";
LOC = "T6";
LOC = "V15";
LOC = "U15";
LOC = "N9";
LOC = "M10";
LOC = "U13";
LOC = "B3";
NET "FMC_CLK0_M2C_P"
NET "FMC_CLK1_M2C_N"
NET "FMC_CLK1_M2C_P"
NET "FMC_LA00_CC_N"
NET "FMC_LA00_CC_P"
NET "FMC_LA01_CC_N"
NET "FMC_LA01_CC_P"
NET "FMC_LA02_N"
NET "FMC_LA02_P"
NET "FMC_LA03_N"
NET "FMC_LA03_P"
NET "FMC_LA04_N"
NET "FMC_LA04_P"
NET "FMC_LA05_N"
NET "FMC_LA05_P"
NET "FMC_LA06_N"
NET "FMC_LA06_P"
NET "FMC_LA07_N"
NET "FMC_LA07_P"
NET "FMC_LA08_N"
NET "FMC_LA08_P"
NET "FMC_LA09_N"
NET "FMC_LA09_P"
NET "FMC_LA10_N"
NET "FMC_LA10_P"
NET "FMC_LA11_N"
NET "FMC_LA11_P"
NET "FMC_LA12_N"
NET "FMC_LA12_P"
NET "FMC_LA13_N"
NET "FMC_LA13_P"
NET "FMC_LA14_N"
NET "FMC_LA14_P"
NET "FMC_LA15_N"
NET "FMC_LA15_P"
NET "FMC_LA16_N"
NET "FMC_LA16_P"
NET "FMC_LA17_CC_N"
NET "FMC_LA17_CC_P"
NET "FMC_LA18_CC_N"
NET "FMC_LA18_CC_P"
NET "FMC_LA19_N"
NET "FMC_LA19_P"
NET "FMC_LA20_N"
NET "FMC_LA20_P"
NET "FMC_LA21_N"
NET "FMC_LA21_P"
NET "FMC_LA22_N"
NET "FMC_LA22_P"
NET "FMC_LA23_N"
NET "FMC_LA23_P"
NET "FMC_LA24_N"
NET "FMC_LA24_P"
NET "FMC_LA25_N"
NET "FMC_LA25_P"
NET "FMC_LA26_N"
NET "FMC_LA26_P"
NET "FMC_LA27_N"
NET "FMC_LA27_P"
NET "FMC_LA28_N"
NET "FMC_LA28_P"
NET "FMC_LA29_N"
NET "FMC_LA29_P"
NET "FMC_LA30_N"
NET "FMC_LA30_P"
NET "FMC_LA31_N"
NET "FMC_LA31_P"
NET "FMC_LA32_N"
NET "FMC_LA32_P"
NET "FMC_LA33_N"
NET "FMC_LA33_P"
NET "FMC_PRSNT_M2C_L"
NET "FMC_PWR_GOOD_FLASH_RST_B"
Figure 1-18: UCF Location Constraints for VITA 57.1 FMC-LPC Connections
SP601 Hardware User Guide
31
UG518 (v1.1) August 19, 2009
Download from Www.Somanuals.com. All Manuals Search And Download.
Chapter 1: SP601 Evaluation Board
10. Status LEDs
Table 1-14 defines the status LEDs.
Table 1-14: Status LEDs
Reference
Signal Name
Designator
Color
Label
Description
DS1
Indicates power available for
VITA 57.1 FMC expansion
connector.
FMC_PWR_GOOD_
PWR
GOOD
Green
Green
FLASH_RST_B
DS2
DS3
DS4
PHY_LED_LINK10
10
PHY_LED_LINK100 Green
100
PHY_LED_LINK100
Green
0
1000
DS5
DS6
DS7
DS8
DS9
PHY_LED_DUPLEX Green
DUP
RX
PHY_LED_RX
PHY_LED_TX
FPGA_AWAKE
Green
Green
Green
TX
AWAKE
Illuminates to indicate the
status of the DONE pin when
the FPGA is successfully
configured.
FPGA_DONE
Green
DONE
INIT
DS10
Illuminates after power-up to
indicate that the FPGA has
successfully powered up and
completed its internal power-
on process.
FPGA_INIT
VCC5
Red
DS15
DS16
DS17
Illuminates when 5V supply is
applied.
Green
LED_GRN,
LED_RED
Green/
Red
STATUS
USB to JTAG logic.
Illuminates to indicate that the
board power is good.
LTC_PWR_GOOD
Green
32
SP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
Download from Www.Somanuals.com. All Manuals Search And Download.
Detailed Description
11. FPGA Awake LED and Suspend Jumper
The suspend mode jumper permits the FPGA to enter an inactive, "suspend" mode. The
FPGA Awake LED DS8 will go out when the FPGA enters this mode.
X-Ref Target Figure 1-19
-
FPGA AWAKE
VCC2V5
FPGA SUSPEND
1
2
R18
4.7K
5%
J14 Suspend Jumper
1
2
R88
27.4
1%
OFF = AWAKE (default)
ON = SUSPEND
1/16W
1/16W
UG518_19_070809
Figure 1-19: FPGA Awake LED and Suspend Jumper
Table 1-15: FPGA Awake/Suspend Mode Jumper Connections
FPGA U1 Pin
Schematic Netname
FPGA_AWAKE
Suspend Mode I/O
Awake LED DS8.2
Suspend J14.2
P15
R16
FPGA_SUSPEND
X-Ref Target Figure 1-20
-
NET "FPGA_AWAKE"
NET "FPGA_SUSPEND"
LOC = "P15";
LOC = "R16";
Figure 1-20: UCF Location Constraints for FPGA Awake/Suspend Mode Jumper
See the Spartan-6 FPGA Configuration Guide for more information at
SP601 Hardware User Guide
33
UG518 (v1.1) August 19, 2009
Download from Www.Somanuals.com. All Manuals Search And Download.
Chapter 1: SP601 Evaluation Board
12. FPGA INIT and DONE LEDs
The typical Xilinx FPGA power up and configuration status LEDs are present on the
SP601. The INIT LED DS10 comes on after the FPGA powers up and completes its internal
power-on process. The DONE LED DS9 comes on after the FPGA programming bitstream
has been downloaded and the FPGA successfully configured.
X-Ref Target Figure 1-21
-
VCC2V5
1
R113
332
VCC2V5
1%
1/16W
2
FPGA DONE
VCC2V5
INIT_B = 0, LED: ON
INIT_B = 1, LED: OFF
1
2
R23
4.7K
5%
1
2
R90
27.4
1%
1
2
R89
27.4
1%
1/16W
1/16W
FPGA INIT B
1/16W
UG518_21_070809
Figure 1-21: FPGA INIT and DONE LEDs
Table 1-16: FPGA INIT and DONE LED Connections
FPGA U1 Pin
Schematic Netname Controlled LED
U3
FPGA_INIT_B
FPGA_DONE
DS10 INIT
DS9 DONE
V17
X-Ref Target Figure 1-22
-
NET "FPGA_INIT_B"
NET "FPGA_DONE"
LOC = "U3";
LOC = "V17";
Figure 1-22: UCF Location Constraints for FPGA INIT and DONE
34
SP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
Download from Www.Somanuals.com. All Manuals Search And Download.
Detailed Description
13. User I/O
The SP601 provides the following user and general purpose I/O capabilities:
•
•
•
•
•
User LEDs
User DIP switch
Pushbutton switches
CPU Reset pushbutton switch
GPIO male pin header
Note: All GPIO location constraints are collected in one partial UCF in Figure 1-27.
User LEDs
The SP601 provides four active high, green LEDs, as described in Figure 1-23 and
Table 1-17.
X-Ref Target Figure 1-23
-
GPIO LED 3
GPIO LED 2
GPIO LED 1
GPIO LED 0
1
1
2
1
2
1
2
R91
27.4
1%
R92
27.4
1%
R93
27.4
1%
R94
27.4
1%
2
1/16W
1/16W
1/16W
1/16W
UG518_23_070809
Figure 1-23: User LEDs
Table 1-17: User LEDs
Reference
Designator
Signal Name
Color
Label
FPGA Pin
DS11
GPIO_LED_0
GPIO_LED_1
Green
Green
E13
C14
DS12
SP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
35
Download from Www.Somanuals.com. All Manuals Search And Download.
Chapter 1: SP601 Evaluation Board
Table 1-17: User LEDs (Cont’d)
Reference
Designator
Signal Name
Color
Label
FPGA Pin
DS13
DS14
GPIO_LED_2
GPIO_LED_3
Green
Green
C4
A4
User DIP switch
The SP601 includes an active high four pole DIP switch, as described in Figure 1-24 and
Table 1-18.
X-Ref Target Figure 1-24
-
VCC2V5
GPIO_SWITCH_0
GPIO_SWITCH_1
GPIO_SWITCH_2
GPIO_SWITCH_3
1
2
3
4
8
7
6
5
SW8
SDMX-4-X
1
2
1
2
1
2
R22
4.7K
5%
R21
4.7K
5%
R20
4.7K
5%
R19
4.7K
5%
1
2
1/16W
1/16W
1/16W
1/16W
UG518_24_070809
Figure 1-24: User DIP Switch
Table 1-18: User DIP Switch Connections
FPGA U1 Pin
Schematic Netname
GPIO_SWITCH_0
SW8 Pin Number
D14
E12
F12
V13
1
2
3
4
GPIO_SWITCH_1
GPIO_SWITCH_2
GPIO_SWITCH_3
36
SP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
Download from Www.Somanuals.com. All Manuals Search And Download.
Detailed Description
User Pushbutton Switches
The SP601 provides five active high pushbutton switches: SW6, SW4, SW5, SW7 and SW9.
The five pushbuttons all have the same topology as the sample shown in Figure 1-25. Four
pushbuttons are assigned as GPIO, and the fifth is assigned as a CPU_RESET. Figure 1-25
and Table 1-19 describe the pushbutton switches.
X-Ref Target Figure 1-25
-
VCC1V8
Pushbutton
1
4
3
P1
P4
P3
2
CPU_RESET
P2
SW9
1
2
R188
4.7K
5%
1/16W
UG518_25_070809
Figure 1-25: User Pushbutton Switch (Typical)
Table 1-19: Pushbutton Switch Connections
FPGA U1 Pin
Schematic Netname
GPIO_BUTTON_0
Switch Pin
SW6.2
P4
F6
E4
F5
N4
GPIO_BUTTON_1
GPIO_BUTTON_2
GPIO_BUTTON_3
CPU_RESET
SW4.2
SW5.2
SW7.2
SW9.2
SP601 Hardware User Guide
37
UG518 (v1.1) August 19, 2009
Download from Www.Somanuals.com. All Manuals Search And Download.
Chapter 1: SP601 Evaluation Board
GPIO Male Pin Header
The SP601 provides a 2X6 GPIO male pin header supporting 3.3V power, GND and eight
I/Os. Figure 1-26 and Table 1-20 describe the J13 GPIO Male Pin Header.
X-Ref Target Figure 1-26
-
GPIO HDR4
GPIO HDR5
GPIO HDR0
GPIO HDR1
1
3
5
2
4
6
8
GPIO HDR2
GPIO HDR3
GPIO HDR6
GPIO HDR7
7
9
11
10
12
J13
VCC3V3
UG518_24_070809
Figure 1-26: GPIO Male Pin Header Topology
Table 1-20: GPIO Header Pins
FPGA U1 Pin
Signal Name
GPIO_HDR0
GPIO_HDR1
GPIO_HDR2
GPIO_HDR3
GPIO_HDR4
GPIO_HDR5
GPIO_HDR6
GPIO_HDR7
J13 Pin
N17
M18
A3
1
3
5
7
2
4
6
8
L15
F15
B4
F13
P12
38
SP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
Download from Www.Somanuals.com. All Manuals Search And Download.
Detailed Description
X-Ref Target Figure 1-27
-
NET "GPIO_LED_0"
LOC = "E13";
LOC = "C14";
LOC = "C4";
LOC = "A4";
NET "GPIO_LED_1"
NET "GPIO_LED_2"
NET "GPIO_LED_3"
NET "GPIO_SWITCH_0"
NET "GPIO_SWITCH_1"
NET "GPIO_SWITCH_2"
NET "GPIO_SWITCH_3"
LOC = "D14";
LOC = "E12";
LOC = "F12";
LOC = "V13";
NET "GPIO_BUTTON0"
NET "GPIO_BUTTON1"
NET "GPIO_BUTTON2"
NET "GPIO_BUTTON3"
NET "CPU_RESET"
LOC = "P4";
LOC = "F6";
LOC = "E4";
LOC = "F5";
LOC = "N4";
NET "GPIO_HDR0"
NET "GPIO_HDR1"
NET "GPIO_HDR2"
NET "GPIO_HDR3"
NET "GPIO_HDR4"
NET "GPIO_HDR5"
NET "GPIO_HDR6"
NET "GPIO_HDR7"
LOC = "N17";
LOC = "M18";
LOC = "A3";
LOC = "L15";
LOC = "F15";
LOC = "B4";
LOC = "F13";
LOC = "P12";
Figure 1-27: UCF Location Constraints for User and General-Purpose I/O
SP601 Hardware User Guide
39
UG518 (v1.1) August 19, 2009
Download from Www.Somanuals.com. All Manuals Search And Download.
Chapter 1: SP601 Evaluation Board
14. FPGA_PROG_B Pushbutton Switch
The SP601 provides one dedicated, active low FPGA_PROG_B pushbutton switch, as
shown in Figure 1-28.
X-Ref Target Figure 1-28
-
VCC2V5
1
R24
4.7K
5%
2
1/16W
Pushbutton
FPGA PROG B
1
4
3
P1
P4
2
P2
SW3
UG518_28_070809
Figure 1-28: FPGA_PROG_B Pushbutton Switch Topology
Table 1-21: FPGA_PROG_B Pushbutton Switch Connections
FPGA U1 Pin
Schematic Netname
FPGA_PROG_B
SW3 Pin
V2
1
X-Ref Target Figure 1-29
-
NET "FPGA_PROG_B" LOC = "V2";
Figure 1-29: UCF Location Constraints for BPI Flash Connections
Power Management
AC Adapter and 5V Input Power Jack/Switch
The SP601 is powered from a 5V source that is connected through a 2.1mm x 5.5mm type
plug (center positive). SP601 power can be turned on or off through a board mounted slide
switch. When the switch is in the on position, a green LED (DS15) is illuminated.
Onboard Power Supplies
The diagram in Figure 1-30 shows the power supply architecture and maximum current
handling on each supply. The typical operating currents are significantly below the
maximum capable. The board is normally shipped with a 15W power supply, which
should be sufficient for most applications.
40
SP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
Download from Www.Somanuals.com. All Manuals Search And Download.
Power Management
The SP601 uses power solutions from LTC. An estimate of the current draw on the various
power supply rails is shown in Table 1-22.
X-Ref Target Figure 1-30
-
5V
PWR
Jack
Monolithic Regulator
0.9V@3A max
Dual Switcher LTM4616
3. 3V@8A max
2. 5V@8A max
Dual Switcher LTM4616
1. 2V@8A max
1. 8V@8A max
Linear Regulator LT1763
3. 0V@500mA max
Buck-Boost Regulator LT1731
12V@1A max
UG518_30 _070809
Figure 1-30: Power Supply
Table 1-22: Estimated Current Draw
Rail (V)
Estimated Current (A)
LX16
Int/Aux
LX16
BPI/SPI
Flash
USB
Clock Marvell Estimated
LTC
µModule
FMC
1.0
DDR2
Comments
V
CP2103 Socket EPHY
Totals
CCO
12
1.0
LT1731
12V, 3A
3.3V, 8A
(1/2)
LTM4616
3.3
3.0
2.0
2.0
0.3
0.1
0.1
0.1
5.5
1.1
1.3
(1/2)
LTM4616
2.5
1.8
1.0
2.5V, 8A
1.8V, 8A
1.2V, 8A
(1/2)
LTM4616
1.0
1.0
(1/2)
LTM4616
1.2
3.0
5.0
1.0
VTT 0.9
LTC3413 0.9V, 1.0A
SP601 Hardware User Guide
41
UG518 (v1.1) August 19, 2009
Download from Www.Somanuals.com. All Manuals Search And Download.
Chapter 1: SP601 Evaluation Board
Configuration Options
The FPGA on the SP601 Evaluation Board can be configured by the following methods:
•
•
•
Table 1-23: Mode Pin Settings (M2 = 0)
Mode Pins (M1, M0)
Configuration Mode
Master Byte Peripheral Interface (BPI)
Master SPI x1, x2, or x4
00
01
10
11
Not implemented on SP601
Not implemented on SP601
JTAG Configuration
JTAG configuration is provided through onboard USB-to-JTAG configuration logic where
a computer host accesses the SP601 JTAG chain through a Type-A (computer host side) to
Type-Mini-B (SP601 side) USB cable.
The JTAG chain of the board is illustrated in Figure 1-31. JTAG configuration is allowable
at any time under any mode pin setting. JTAG initiated configuration takes priority over
the mode pin settings.
FMC bypass jumper J4 must be connected between pins 1-2 for JTAG access to the FPGA
on the basic SP601 board, as shown in Figure 1-31. When the VITA 57.1 FMC expansion
connector is populated with an expansion module that has a JTAG chain, then jumper J4
must be set to connect pins 2-3 in order to include the FMC expansion module's JTAG
chain in the main SP601 JTAG chain.
X-Ref Target Figure 1-31
-
FPGA
J10
FMC LPC Expansion
TDI
TDO
TDI
U1
J1
J4
1
TDO
*Default jumper setting excludes FMC.
To include FMC, jumper pins 2-3.
UG518_31_070809
Figure 1-31: JTAG Chain
42
SP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
Download from Www.Somanuals.com. All Manuals Search And Download.
Configuration Options
X-Ref Target Figure 1-32
-
J4
1
2
3
FPGA_TD0
JTAG_TD0
FMC_TD0
Bypass FMC LPC J1 = Jumper 1-2
Include FMC LPC J1 = Jumper 2-3
H - 1x3
UG518_32_081909
Figure 1-32: VITA 57.1 FMC JTAG Bypass Jumper
The JTAG chain can be used to program the FPGA and access the FPGA for hardware and
software debug.
The JTAG connector (USB Mini-B J10) allows a host computer to download bitstreams to
the FPGA using the iMPACT software tool, and also allows debug tools such as the
ChipScope™ Pro Analyzer tool or a software debugger to access the FPGA.
The iMPACT software tool can also program the SPI x4 flash or the BPI flash via the USB
J10 connection. iMPACT can download a temporary design to the FPGA through the
JTAG. This provides a connection within the FPGA from the FPGA's JTAG port to the
FPGA's SPI or BPI interface. Through the connection made by the temporary design in the
FPGA, iMPACT can indirectly program the SPI flash or BPI flash from the JTAG USB J10
connector.
SP601 Hardware User Guide
43
UG518 (v1.1) August 19, 2009
Download from Www.Somanuals.com. All Manuals Search And Download.
Chapter 1: SP601 Evaluation Board
44
SP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
Download from Www.Somanuals.com. All Manuals Search And Download.
Appendix A
References
This section provides references to documentation supporting Spartan-6 FPGAs, tools,
and IP. For additional information, see
Documents supporting the SP601 Evaluation Board:
SP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
45
Download from Www.Somanuals.com. All Manuals Search And Download.
Appendix A: References
46
SP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
Download from Www.Somanuals.com. All Manuals Search And Download.
Appendix B
Default Jumper and Switch Settings
Table B-1 shows the default jumper and switch settings for the SP601.
Table B-1: Default Jumper and Switch Settings
REFDES
Type/Function
SLIDE, POWER ON-OFF
DIP, 2-POLE, MODE
M0
Default
SW1
SW2
1
OFF
ON (1)
OFF (0)
2
M1
SW8
1
DIP, 4-POLE, GPIO
OFF
2
OFF
OFF
3
4
OFF
J4
HDR_1X3, JTAG BYPASS
HDR_1X2, SUSPEND
HDR_1X2, SPI SELECT
JUMP 1-2 (EXCLUDE FMC)
OPEN (0 = AWAKE)
ON (U17 SPI MEM SELECTED)
J14
J15
SP601 Hardware User Guide
47
UG518 (v1.1) August 19, 2009
Download from Www.Somanuals.com. All Manuals Search And Download.
Appendix B: Default Jumper and Switch Settings
48
SP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
Download from Www.Somanuals.com. All Manuals Search And Download.
Appendix C
VITA 57.1 FMC Connections
Table C-1 shows the VITA 57.1 FMC LPC connections.
Table C-1: VITA 57.1 FMC LPC Connections
J1 FMC
LPC Pin
U1 FPGA
Pin
J1 FMC
LPC Pin
U1 FPGA
Schematic Netname
Schematic Netname
Pin
C10
C11
C14
C15
C18
C19
C22
C23
C26
C27
C30
C31
FMC_LA06_P
FMC_LA06_N
FMC_LA10_P
D12
C12
D8
D1
FMC_PWR_GOOD_FLASH_RST_B
FMC_LA01_CC_P
FMC_LA01_CC_N
FMC_LA05_P
B3
D8
D11
C11
B14
A14
G11
F10
B11
A11
R8
D9
FMC_LA10_N
FMC_LA14_P
C8
D11
D12
D14
D15
D17
D18
D20
D21
D23
D24
D26
D27
B2
FMC_LA05_N
FMC_LA14_N
FMC_LA18_CC_P
FMC_LA18_CC_N
FMC_LA27_P
A2
FMC_LA09_P
R10
T10
R11
T11
P11
N10
FMC_LA09_N
FMC_LA13_P
FMC_LA13_N
FMC_LA27_N
IIC_SCL_MAIN
IIC_SDA_MAIN
FMC_LA17_CC_P
FMC_LA17_CC_N
FMC_LA23_P
T8
N5
P6
FMC_LA23_N
FMC_LA26_P
U7
FMC_LA26_N
V7
G2
G3
FMC_CLK1_M2C_P
FMC_CLK1_M2C_N
FMC_LA00_CC_P
FMC_LA00_CC_N
FMC_LA03_P
T9
V9
H2
H4
FMC_PRSNT_M2C_L
FMC_CLK0_M2C_P
FMC_CLK0_M2C_N
FMC_LA02_P
U13
C10
A10
C15
A15
B16
A16
G6
D9
H5
G7
C9
H7
G9
C13
A13
F11
H8
FMC_LA02_N
G10
G12
FMC_LA03_N
H10
H11
FMC_LA04_P
FMC_LA08_P
FMC_LA04_N
SP601 Hardware User Guide
49
UG518 (v1.1) August 19, 2009
Download from Www.Somanuals.com. All Manuals Search And Download.
Appendix C: VITA 57.1 FMC Connections
Table C-1: VITA 57.1 FMC LPC Connections (Cont’d)
J1 FMC
LPC Pin
U1 FPGA
Pin
J1 FMC
LPC Pin
U1 FPGA
Pin
Schematic Netname
Schematic Netname
G13
G15
G16
G18
G19
G21
G22
G24
G25
G27
G28
G30
G31
G33
G34
G36
G37
FMC_LA08_N
FMC_LA12_P
FMC_LA12_N
FMC_LA16_P
FMC_LA16_N
FMC_LA20_P
FMC_LA20_N
FMC_LA22_P
FMC_LA22_N
FMC_LA25_P
FMC_LA25_N
FMC_LA29_P
FMC_LA29_N
FMC_LA31_P
FMC_LA31_N
FMC_LA33_P
FMC_LA33_N
E11
D6
C6
H13
H14
H16
H17
H19
H20
H22
H23
H25
H26
H28
H29
H31
H32
H34
H35
H37
H38
FMC_LA07_P
FMC_LA07_N
FMC_LA11_P
FMC_LA11_N
FMC_LA15_P
FMC_LA15_N
FMC_LA19_P
FMC_LA19_N
FMC_LA21_P
FMC_LA21_N
FMC_LA24_P
FMC_LA24_N
FMC_LA28_P
FMC_LA28_N
FMC_LA30_P
FMC_LA30_N
FMC_LA32_P
FMC_LA32_N
E7
E8
B12
A12
G9
C7
A7
N7
P8
F9
N6
P7
R7
T7
T4
M11
N11
M8
N8
T6
V4
U8
V8
U11
V11
T12
V12
U15
V15
V6
M10
N9
50
SP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
Download from Www.Somanuals.com. All Manuals Search And Download.
Appendix D
SP601 Master UCF
The UCF template is provided for designs that target the SP601. Net names provided in the
constraints below correlate with net names on the SP601 rev. C schematic. On identifying
the appropriate pins, the net names below should be replaced with net names in the user
NET "CPU_RESET"
NET "DDR2_A0"
NET "DDR2_A1"
NET "DDR2_A2"
NET "DDR2_A3"
NET "DDR2_A4"
NET "DDR2_A5"
NET "DDR2_A6"
NET "DDR2_A7"
NET "DDR2_A8"
NET "DDR2_A9"
NET "DDR2_A10"
NET "DDR2_A11"
NET "DDR2_A12"
NET "DDR2_BA0"
NET "DDR2_BA1"
NET "DDR2_BA2"
NET "DDR2_CAS_B"
NET "DDR2_CKE"
NET "DDR2_CLK_N"
NET "DDR2_CLK_P"
NET "DDR2_DQ0"
NET "DDR2_DQ1"
NET "DDR2_DQ2"
NET "DDR2_DQ3"
NET "DDR2_DQ4"
NET "DDR2_DQ5"
NET "DDR2_DQ6"
NET "DDR2_DQ7"
NET "DDR2_DQ8"
NET "DDR2_DQ9"
NET "DDR2_DQ10"
NET "DDR2_DQ11"
NET "DDR2_DQ12"
NET "DDR2_DQ13"
NET "DDR2_DQ14"
NET "DDR2_DQ15"
NET "DDR2_LDM"
NET "DDR2_LDQS_N"
LOC = "N4";
LOC = "J7";
LOC = "J6";
LOC = "H5";
LOC = "L7";
LOC = "F3";
LOC = "H4";
LOC = "H3";
LOC = "H6";
LOC = "D2";
LOC = "D1";
LOC = "F4";
LOC = "D3";
LOC = "G6";
LOC = "F2";
LOC = "F1";
LOC = "E1";
LOC = "K5";
LOC = "H7";
LOC = "G1";
LOC = "G3";
LOC = "L2";
LOC = "L1";
LOC = "K2";
LOC = "K1";
LOC = "H2";
LOC = "H1";
LOC = "J3";
LOC = "J1";
LOC = "M3";
LOC = "M1";
LOC = "N2";
LOC = "N1";
LOC = "T2";
LOC = "T1";
LOC = "U2";
LOC = "U1";
LOC = "K3";
LOC = "L3";
SP601 Hardware User Guide
51
UG518 (v1.1) August 19, 2009
Download from Www.Somanuals.com. All Manuals Search And Download.
Appendix D: SP601 Master UCF
NET "DDR2_LDQS_P"
NET "DDR2_ODT"
LOC = "L4";
LOC = "K6";
LOC = "L5";
LOC = "K4";
LOC = "P1";
LOC = "P2";
LOC = "E3";
LOC = "K18";
LOC = "K17";
LOC = "J18";
LOC = "J16";
LOC = "G18";
LOC = "G16";
LOC = "H16";
LOC = "H15";
LOC = "H14";
LOC = "H13";
LOC = "F18";
LOC = "F17";
LOC = "K13";
LOC = "K12";
LOC = "E18";
LOC = "E16";
LOC = "G13";
LOC = "H12";
LOC = "D18";
LOC = "D17";
LOC = "G14";
LOC = "F14";
LOC = "C18";
LOC = "C17";
LOC = "F16";
LOC = "L17";
LOC = "U5";
LOC = "V5";
LOC = "R3";
LOC = "T3";
LOC = "R5";
LOC = "L18";
LOC = "M16";
LOC = "A10";
LOC = "C10";
LOC = "V9";
LOC = "T9";
LOC = "C9";
LOC = "D9";
LOC = "C11";
LOC = "D11";
LOC = "A15";
LOC = "C15";
LOC = "A13";
LOC = "C13";
LOC = "A16";
LOC = "B16";
LOC = "A14";
LOC = "B14";
LOC = "C12";
LOC = "D12";
LOC = "E8";
NET "DDR2_RAS_B"
NET "DDR2_UDM"
NET "DDR2_UDQS_N"
NET "DDR2_UDQS_P"
NET "DDR2_WE_B"
NET "FLASH_A0"
NET "FLASH_A1"
NET "FLASH_A2"
NET "FLASH_A3"
NET "FLASH_A4"
NET "FLASH_A5"
NET "FLASH_A6"
NET "FLASH_A7"
NET "FLASH_A8"
NET "FLASH_A9"
NET "FLASH_A10"
NET "FLASH_A11"
NET "FLASH_A12"
NET "FLASH_A13"
NET "FLASH_A14"
NET "FLASH_A15"
NET "FLASH_A16"
NET "FLASH_A17"
NET "FLASH_A18"
NET "FLASH_A19"
NET "FLASH_A20"
NET "FLASH_A21"
NET "FLASH_A22"
NET "FLASH_A23"
NET "FLASH_A24"
NET "FLASH_CE_B"
NET "FLASH_D3"
NET "FLASH_D4"
NET "FLASH_D5"
NET "FLASH_D6"
NET "FLASH_D7"
NET "FLASH_OE_B"
NET "FLASH_WE_B"
NET "FMC_CLK0_M2C_N"
NET "FMC_CLK0_M2C_P"
NET "FMC_CLK1_M2C_N"
NET "FMC_CLK1_M2C_P"
NET "FMC_LA00_CC_N"
NET "FMC_LA00_CC_P"
NET "FMC_LA01_CC_N"
NET "FMC_LA01_CC_P"
NET "FMC_LA02_N"
NET "FMC_LA02_P"
NET "FMC_LA03_N"
NET "FMC_LA03_P"
NET "FMC_LA04_N"
NET "FMC_LA04_P"
NET "FMC_LA05_N"
NET "FMC_LA05_P"
NET "FMC_LA06_N"
NET "FMC_LA06_P"
NET "FMC_LA07_N"
52
SP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
Download from Www.Somanuals.com. All Manuals Search And Download.
NET "FMC_LA07_P"
NET "FMC_LA08_N"
NET "FMC_LA08_P"
NET "FMC_LA09_N"
NET "FMC_LA09_P"
NET "FMC_LA10_N"
NET "FMC_LA10_P"
NET "FMC_LA11_N"
NET "FMC_LA11_P"
NET "FMC_LA12_N"
NET "FMC_LA12_P"
NET "FMC_LA13_N"
NET "FMC_LA13_P"
NET "FMC_LA14_N"
NET "FMC_LA14_P"
NET "FMC_LA15_N"
NET "FMC_LA15_P"
NET "FMC_LA16_N"
NET "FMC_LA16_P"
NET "FMC_LA17_CC_N"
NET "FMC_LA17_CC_P"
NET "FMC_LA18_CC_N"
NET "FMC_LA18_CC_P"
NET "FMC_LA19_N"
NET "FMC_LA19_P"
NET "FMC_LA20_N"
NET "FMC_LA20_P"
NET "FMC_LA21_N"
NET "FMC_LA21_P"
NET "FMC_LA22_N"
NET "FMC_LA22_P"
NET "FMC_LA23_N"
NET "FMC_LA23_P"
NET "FMC_LA24_N"
NET "FMC_LA24_P"
NET "FMC_LA25_N"
NET "FMC_LA25_P"
NET "FMC_LA26_N"
NET "FMC_LA26_P"
NET "FMC_LA27_N"
NET "FMC_LA27_P"
NET "FMC_LA28_N"
NET "FMC_LA28_P"
NET "FMC_LA29_N"
NET "FMC_LA29_P"
NET "FMC_LA30_N"
NET "FMC_LA30_P"
NET "FMC_LA31_N"
NET "FMC_LA31_P"
NET "FMC_LA32_N"
NET "FMC_LA32_P"
NET "FMC_LA33_N"
NET "FMC_LA33_P"
NET "FMC_PRSNT_M2C_L"
NET "FMC_PWR_GOOD_FLASH_RST_B"
NET "FPGA_AWAKE"
NET "FPGA_CCLK"
LOC = "E7";
LOC = "E11";
LOC = "F11";
LOC = "F10";
LOC = "G11";
LOC = "C8";
LOC = "D8";
LOC = "A12";
LOC = "B12";
LOC = "C6";
LOC = "D6";
LOC = "A11";
LOC = "B11";
LOC = "A2";
LOC = "B2";
LOC = "F9";
LOC = "G9";
LOC = "A7";
LOC = "C7";
LOC = "T8";
LOC = "R8";
LOC = "T10";
LOC = "R10";
LOC = "P7";
LOC = "N6";
LOC = "P8";
LOC = "N7";
LOC = "V4";
LOC = "T4";
LOC = "T7";
LOC = "R7";
LOC = "P6";
LOC = "N5";
LOC = "V8";
LOC = "U8";
LOC = "N11";
LOC = "M11";
LOC = "V7";
LOC = "U7";
LOC = "T11";
LOC = "R11";
LOC = "V11";
LOC = "U11";
LOC = "N8";
LOC = "M8";
LOC = "V12";
LOC = "T12";
LOC = "V6";
LOC = "T6";
LOC = "V15";
LOC = "U15";
LOC = "N9";
LOC = "M10";
LOC = "U13";
LOC = "B3";
LOC = "P15";
LOC = "R15";
LOC = "U16";
LOC = "P13";
NET "FPGA_CMP_CLK"
NET "FPGA_CMP_CS_B"
SP601 Hardware User Guide
53
UG518 (v1.1) August 19, 2009
Download from Www.Somanuals.com. All Manuals Search And Download.
Appendix D: SP601 Master UCF
NET "FPGA_CMP_MOSI"
LOC = "V16";
LOC = "R13";
LOC = "T14";
LOC = "V14";
LOC = "V17";
LOC = "D4";
LOC = "U3";
LOC = "T15";
LOC = "N12";
LOC = "T13";
LOC = "L6";
LOC = "C2";
LOC = "V2";
LOC = "R16";
LOC = "A17";
LOC = "D15";
LOC = "D16";
LOC = "B18";
LOC = "P3";
LOC = "P4";
LOC = "F6";
LOC = "E4";
LOC = "F5";
LOC = "N17";
LOC = "M18";
LOC = "A3";
LOC = "L15";
LOC = "F15";
LOC = "B4";
LOC = "F13";
LOC = "P12";
LOC = "E13";
LOC = "C14";
LOC = "C4";
LOC = "A4";
LOC = "D14";
LOC = "E12";
LOC = "F12";
LOC = "V13";
LOC = "P11";
LOC = "N10";
LOC = "L14";
LOC = "M13";
LOC = "J13";
LOC = "N14";
LOC = "P16";
LOC = "L13";
LOC = "L16";
LOC = "N18";
LOC = "M14";
LOC = "U18";
LOC = "U17";
LOC = "T18";
LOC = "T17";
LOC = "N16";
LOC = "N15";
LOC = "P18";
LOC = "P17";
LOC = "B9";
NET "FPGA_D0_DIN_MISO_MISO1"
NET "FPGA_D1_MISO2"
NET "FPGA_D2_MISO3"
NET "FPGA_DONE"
NET "FPGA_HSWAPEN"
NET "FPGA_INIT_B"
NET "FPGA_M0_CMP_MISO"
NET "FPGA_M1"
NET "FPGA_MOSI_CSI_B_MISO0"
NET "FPGA_ONCHIP_TERM1"
NET "FPGA_ONCHIP_TERM2"
NET "FPGA_PROG_B"
NET "FPGA_SUSPEND"
NET "FPGA_TCK_BUF"
NET "FPGA_TDI_BUF"
NET "FPGA_TDO"
NET "FPGA_TMS_BUF"
NET "FPGA_VTEMP"
NET "GPIO_BUTTON0"
NET "GPIO_BUTTON1"
NET "GPIO_BUTTON2"
NET "GPIO_BUTTON3"
NET "GPIO_HDR0"
NET "GPIO_HDR1"
NET "GPIO_HDR2"
NET "GPIO_HDR3"
NET "GPIO_HDR4"
NET "GPIO_HDR5"
NET "GPIO_HDR6"
NET "GPIO_HDR7"
NET "GPIO_LED_0"
NET "GPIO_LED_1"
NET "GPIO_LED_2"
NET "GPIO_LED_3"
NET "GPIO_SWITCH_0"
NET "GPIO_SWITCH_1"
NET "GPIO_SWITCH_2"
NET "GPIO_SWITCH_3"
NET "IIC_SCL_MAIN"
NET "IIC_SDA_MAIN"
NET "PHY_COL"
NET "PHY_CRS"
NET "PHY_INT"
NET "PHY_MDC"
NET "PHY_MDIO"
NET "PHY_RESET"
NET "PHY_RXCLK"
NET "PHY_RXCTL_RXDV"
NET "PHY_RXD0"
NET "PHY_RXD1"
NET "PHY_RXD2"
NET "PHY_RXD3"
NET "PHY_RXD4"
NET "PHY_RXD5"
NET "PHY_RXD6"
NET "PHY_RXD7"
NET "PHY_RXER"
NET "PHY_TXCLK"
54
SP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
Download from Www.Somanuals.com. All Manuals Search And Download.
NET "PHY_TXCTL_TXEN"
NET "PHY_TXC_GTXCLK"
NET "PHY_TXD0"
NET "PHY_TXD1"
NET "PHY_TXD2"
NET "PHY_TXD3"
NET "PHY_TXD4"
NET "PHY_TXD5"
NET "PHY_TXD6"
NET "PHY_TXD7"
NET "PHY_TXER"
NET "SMACLK_N"
NET "SMACLK_P"
NET "SPI_CS_B"
NET "SYSCLK_N"
NET "SYSCLK_P"
NET "USB_1_CTS"
NET "USB_1_RTS"
NET "USB_1_RX"
NET "USB_1_TX"
NET "USER_CLOCK"
LOC = "B8";
LOC = "A9";
LOC = "F8";
LOC = "G8";
LOC = "A6";
LOC = "B6";
LOC = "E6";
LOC = "F7";
LOC = "A5";
LOC = "C5";
LOC = "A8";
LOC = "H18";
LOC = "H17";
LOC = "V3";
LOC = "K16";
LOC = "K15";
LOC = "U10";
LOC = "T5";
LOC = "L12";
LOC = "K14";
LOC = "V10";
SP601 Hardware User Guide
55
UG518 (v1.1) August 19, 2009
Download from Www.Somanuals.com. All Manuals Search And Download.
|