Xilinx Computer Hardware SP605 User Manual
SP605 Hardware  
User Guide  
UG526 (v1.1.1) February 1, 2010
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Table of Contents  
Preface: About This Guide  
Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
Additional Support Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
Chapter 1: SP605 Evaluation Board  
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
Related Xilinx Documents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
1. Spartan-6 XC6SLX45T-3FGG484 FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
I/O Voltage Rails . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
2. 128 MB DDR3 Component Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
3. SPI x4 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
4. Linear BPI Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
FPGA Design Considerations for the Configuration Flash . . . . . . . . . . . . . . . . . . . . . . . 20  
5. System ACE CF and CompactFlash Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
6. USB JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
7. Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
Oscillator (Differential) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
Oscillator Socket (Single-Ended, 2.5V or 3.3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24  
SMA Connectors (Differential) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25  
8. Multi-Gigabit Transceivers (GTP MGTs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25  
9. PCI Express Endpoint Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28  
10. SFP Module Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30  
11. 10/100/1000 Tri-Speed Ethernet PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31  
12. USB-to-UART Bridge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33  
13. DVI CODEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34  
14. IIC Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35  
8-Kb NV Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36  
15. Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38  
Ethernet PHY Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39  
FPGA INIT and DONE LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40  
16. User I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41  
User LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41  
User Pushbutton Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42  
User DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43  
User SIP Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44  
User SMA GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45  
17. Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46  
Power On/Off Slide Switch SW2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46  
FPGA_PROG_B Pushbutton SW3 (Active-Low). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47  
SYSACE_RESET_B Pushbutton SW9 (Active-Low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47  
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System ACE CF CompactFlash Image Select DIP Switch S1 (Active-High) . . . . . . . . . . 48  
Mode DIP Switch SW1 (Active-High). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49  
18. VITA 57.1 FMC LPC Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50  
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52  
AC Adapter and 12V Input Power Jack/Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52  
Onboard Power Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53  
Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55  
Appendix A: Default Jumper and Switch Settings  
Appendix B: VITA 57.1 FMC LPC Connector Pinout  
Appendix C: SP605 Master UCF  
Appendix D: References  
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Preface  
About This Guide  
This manual accompanies the Spartan®-6 FPGA SP605 Evaluation Board and contains  
information about the SP605 hardware and software tools.  
Guide Contents  
This manual contains the following chapters:  
•
Chapter 1, “SP605 Evaluation Board,” provides an overview of the embedded  
development board and details the components and features of the SP605 board.  
•
•
•
•
Appendix A, “Default Jumper and Switch Settings.”  
Appendix B, “VITA 57.1 FMC LPC Connector Pinout.”  
Appendix C, “SP605 Master UCF.”  
Appendix D, “References.”  
Additional Documentation  
The following documents are available for download at  
http://www.xilinx.com/products/spartan6/.  
•
Spartan-6 Family Overview  
This overview outlines the features and product selection of the Spartan-6 family.  
•
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics  
This data sheet contains the DC and switching characteristic specifications for the  
Spartan-6 family.  
•
•
Spartan-6 FPGA Packaging and Pinout Specifications  
This specification includes the tables for device/package combinations and maximum  
I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and  
thermal specifications.  
Spartan-6 FPGA Configuration User Guide  
This all-encompassing configuration guide includes chapters on configuration  
interfaces (serial and parallel), multi-bitstream management, bitstream encryption,  
boundary-scan and JTAG configuration, and reconfiguration techniques.  
•
•
Spartan-6 FPGA SelectIO Resources User Guide  
This guide describes the SelectIO™ resources available in all Spartan-6 devices.  
Spartan-6 FPGA Clocking Resources User Guide  
SP605 Hardware User Guide  
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Preface: About This Guide  
This guide describes the clocking resources available in all Spartan-6 devices,  
including the DCMs and PLLs.  
•
•
•
Spartan-6 FPGA Block RAM Resources User Guide  
This guide describes the Spartan-6 device block RAM capabilities.  
Spartan-6 FPGA GTP Transceivers User Guide  
This guide describes the GTP transceivers available in the Spartan-6 LXT FPGAs.  
Spartan-6 FPGA DSP48A1 Slice User Guide  
This guide describes the architecture of the DSP48A1 slice in Spartan-6 FPGAs and  
provides configuration examples.  
•
•
Spartan-6 FPGA Memory Controller User Guide  
This guide describes the Spartan-6 FPGA memory controller block, a dedicated  
embedded multi-port memory controller that greatly simplifies interfacing  
Spartan-6 FPGAs to the most popular memory standards.  
Spartan-6 FPGA PCB Designer’s Guide  
This guide provides information on PCB design for Spartan-6 devices, with a focus on  
strategies for making design decisions at the PCB and interface level.  
Additional Support Resources  
To search the database of silicon and software questions and answers or to create a  
technical support case in WebCase, see the Xilinx website at:  
http://www.xilinx.com/support.  
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Chapter 1  
SP605 Evaluation Board  
Overview  
The SP605 board enables hardware and software developers to create or evaluate designs  
targeting the Spartan®-6 XC6SLX45T-3FGG484 FPGA.  
The SP605 provides board features common to many embedded processing systems. Some  
commonly used features include: a DDR3 component memory, a 1-lane PCI Express®  
interface, a tri-mode Ethernet PHY, general purpose I/O and a UART. Additional user  
desired features can be added through mezzanine cards attached to the onboard high  
speed VITA-57 FPGA Mezzanine Connector (FMC) low pin count (LPC) connector.  
“Features,” page 8 provides a general listing of the board features with details provided in  
“Detailed Description,” page 10.  
Additional Information  
Additional information and support material is located at:  
http://www.xilinx.com/sp605  
This information includes:  
•
•
•
•
Current version of this user guide in PDF format  
Example design files for demonstration of Spartan-6 FPGA features and technology  
Demonstration hardware and software configuration files for the System ACE CF  
controller, Platform Flash configuration storage device, and linear flash chip  
•
•
•
•
•
Reference Design Files  
Schematics in PDF format and DxDesigner schematic format  
Bill of materials (BOM)  
Printed-circuit board (PCB) layout in Allegro PCB format  
Gerber files for the PCB (Many free or shareware Gerber file viewers are available on  
the Internet for viewing and printing these files.)  
•
Additional documentation, errata, frequently asked questions, and the latest news  
For information about the Spartan-6 family of FPGA devices, including product  
highlights, data sheets, user guides, and application notes, see the Spartan-6 FPGA website  
at http://www.xilinx.com/support/documentation/spartan-6.htm.  
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Chapter 1: SP605 Evaluation Board  
Features  
The SP605 board provides the following features:  
•
•
•
•
•
•
•
1. Spartan-6 XC6SLX45T-3FGG484 FPGA  
2. 128 MB DDR3 Component Memory  
3. SPI x4 Flash  
4. Linear BPI Flash  
5. System ACE CF and CompactFlash Connector  
6. USB JTAG  
7. Clock Generation  
♦
♦
♦
♦
Fixed 200 MHz oscillator (differential)  
Socket with a 2.5V 27MHz oscillator (single-ended)  
SMA connectors (differential)  
SMA connectors for MGT clocking (differential)  
•
•
8. Multi-Gigabit Transceivers (GTP MGTs)  
♦
♦
♦
♦
FMC LPC connector  
SMA  
PCIe  
SFP module connector  
9. PCI Express Endpoint Connectivity  
Gen1 x1  
♦
•
•
•
•
•
10. SFP Module Connector  
11. 10/100/1000 Tri-Speed Ethernet PHY  
12. USB-to-UART Bridge  
13. DVI CODEC  
14. IIC Bus  
♦
♦
♦
♦
♦
IIC EEPROM - 1KB  
DVI CODEC  
DVI connector  
FMC LPC connector  
SFP Module connector  
•
•
15. Status LEDs  
♦
♦
♦
Ethernet Status  
FPGA INIT  
FPGA DONE  
16. User I/O  
♦
♦
♦
♦
♦
USER LED GPIO  
User pushbuttons  
CPU Reset pushbutton  
User DIP switch - GPIO  
User SMA GPIO connectors  
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Overview  
•
17. Switches  
♦
♦
♦
♦
Power On/Off slide switch  
System ACE CF Reset pushbutton  
System ACE CF bitstream image select DIP switch  
Mode DIP switch  
•
•
18. VITA 57.1 FMC LPC Connector  
Configuration Options  
♦
♦
♦
♦
3. SPI x4 Flash (both onboard and off-board)  
4. Linear BPI Flash  
5. System ACE CF and CompactFlash Connector  
6. USB JTAG  
•
Power Management  
♦
♦
AC Adapter and 12V Input Power Jack/Switch  
Onboard Power Regulation  
Block Diagram  
Figure 1-1 shows a high-level block diagram of the SP605 and its peripherals.  
X-Ref Target Figure 1-1  
-
1-Lane I/Fs:  
PCIe Edge Conn.  
SMA x4 SFP  
FMC-LPC  
PCIe 125 MHz Clk  
SMA REFCLK  
SFPCLK  
Part of  
LED  
DIP Switch  
User SMA x2  
FMC-LPC  
Expansion  
Connector  
SFP IIC Bus  
FMC GBTCLK  
JTAG  
JTAG  
Main IIC Bus  
System ACE  
MPU I/F  
DED  
MGTs  
Bank 0  
2.5V  
USB UART and  
USB Mini-B  
Connector  
L/S  
JTAG  
USB JTAG Logic  
and USB Mini-B  
Connector  
Spartan-6  
Bank 3  
1.5V  
Bank 1  
2.5V  
DVI Codec and  
DVI Connector  
XC6SLX45T-3FGG484  
U1  
DDR3  
Component  
Memory  
10/100/1000  
Ethernet PHY,  
Status LEDs,  
and Connector  
Bank 2  
2.5V  
L/S  
Pushbuttons  
DIP Switch  
GPIO Header  
Parallel Flash  
DVI IIC Bus  
LED,  
DIP Switch  
SPI x4,  
SPI Header  
Part of FMC-LPC  
Expansion Conn.  
L/S  
UG526_01_110409  
= Level Shifter  
Figure 1-1: SP605 Features and Banking  
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Chapter 1: SP605 Evaluation Board  
Related Xilinx Documents  
Prior to using the SP605 Evaluation Board, users should be familiar with Xilinx resources.  
See the following locations for additional documentation on Xilinx tools and solutions:  
•
•
•
ISE: www.xilinx.com/ise  
Answer Browser: www.xilinx.com/support  
Intellectual Property: www.xilinx.com/ipcenter  
Detailed Description  
Figure 1-2 shows a board photo with numbered features corresponding to Table 1-1 and  
the section headings in this document.  
X-Ref Target Figure 1-2  
-
15b 15a  
15e  
15h  
18  
16d  
5
10  
17a  
17b  
6
7a  
2
15c  
17d  
12  
16c  
11  
8
7c  
15d  
19b  
1
17c  
15g  
3
8
19  
13  
4
16b  
7b  
16a  
15f  
9
UG526_02 _110409  
3, 14 (on backside)  
Figure 1-2: SP605 Board Photo  
The numbered features in Figure 1-2 correlate to the features and notes listed in Table 1-1.  
Table 1-1: SP605 Features  
Schematic  
Number  
Feature  
Spartan-6 FPGA  
Notes  
Page  
2–7  
9
1
2
XC6SLX45T-3FGG484 FPGA  
Micron MT41J64M16LA-187E  
DDR3 Component Memory  
SPI Header Ext. x4  
SPI Flash x4 (on backside)  
3
Winbond W25Q64VSFIG  
18  
10  
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Detailed Description  
Table 1-1: SP605 Features (Cont’d)  
Schematic  
Page  
Number  
Feature  
Notes  
4
5
6
Linear BPI Flash x16  
Numonyx JS28F256P30T95  
XCCACE-TQ144I Controller  
USB JTAG Download Circuit  
19  
20  
SystemACE CompactFlash  
Socket  
USB JTAG Conn. (USB Mini-B)  
Clock Generation  
32  
200 MHz OSC, oscillator socket,  
SMA connectors  
13, 14  
14  
a. 200 MHz oscillator  
Epson 200 MHz 2.5V LVDS  
MMD Components 2.5V 27 MHz  
SMA pair P(J41) / N(J38)  
7
b. Oscillator socket, single-  
ended, LVCMOS  
14  
c. SMA connectors  
13  
GTP port SMA x4 and  
MGT Clocking SMA (REFCLK)  
MGT RX,TX Pairs x4 SMA MGT  
REFCLK x2 SMA  
8
13  
9
PCIe 1-lane edge conn.(Gen 1)  
SFP Module Cage/Connector  
Ethernet 10/100/1000  
Card Edge Connector, 1-lane  
AMP 136073-1  
12  
12  
11  
10  
11  
Marvell M88E1111 EPHY  
USB UART (USB-to-UART  
Bridge)  
12  
Silicon Labs CP2103GM  
15  
13  
14  
DVI Codec and Video Connector Chrontel CH7301C-TF  
16,17  
15  
IIC EEPROM (on backside)  
ST Micro M24C08-WDW6TP  
10, 11, 14,  
18, 20, 25,  
27, 31, 33  
Status LEDs  
a. FMC Power Good  
b. System ACE CF Status  
c. FPGA INIT and DONE  
d. Ethernet PHY Status  
e. JTAG USB Status  
f. FPGA Awake  
10  
11  
14  
18  
20  
27  
31  
15  
g. TI Power Good  
h. MGT AVCC, DDR3 Term  
Pwr Good  
33  
a. User LEDs (4)  
Red LEDs (active-High)  
Active-High  
14  
14  
14  
13  
b. User Pushbuttons (4)  
c. User DIP Switch (4-pole)  
d. User SMA (2)  
16  
4-pole (active-High)  
GPIO x2 SMA  
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Chapter 1: SP605 Evaluation Board  
Table 1-1: SP605 Features (Cont’d)  
Schematic  
Page  
Number  
Feature  
Notes  
Power, Configuration,  
Pushbutton Switches  
14, 18, 20,  
25  
Switches  
a. SP605 Power On-Off Slide  
Switch  
25  
18  
20  
b. FPGA Mode DIP Switch  
17  
c. System ACE CF  
Configuration DIP Switch  
d. FPGA PROG, CPU Reset,  
and System ACE CF Reset  
Pushbutton Switches  
14, 20  
18  
19  
FMC LPC Connector  
Samtec ASP-134603-01  
2x TI UCD9240PFC  
10  
a. Power Management  
Controller  
21, 26  
b. Mini-Fit Type 6-Pin, ATX  
Type 4-pin  
12V input power connectors  
25  
1. Spartan-6 XC6SLX45T-3FGG484 FPGA  
A Xilinx Spartan-6 XC6SLX45T-3FGG484 FPGA is installed on the Embedded  
Development Board.  
References  
See the Spartan-6 FPGA Data Sheet. [Ref 1]  
Configuration  
The SP605 supports configuration in the following modes:  
•
•
•
•
•
JTAG (using the included USB-A to Mini-B cable)  
JTAG (using System ACE CF and CompactFlash card)  
Master SPI x4  
Master SPI x4 with off-board device  
Linear BPI Flash  
For details on configuring the FPGA, see “Configuration Options.”  
Mode switch SW1 (see Table 1-30, page 55) is set to 10 = Slave SelectMAP to choose the  
System ACE CF default configuration.  
References  
See the Spartan-6 FPGA Configuration User Guide for more information. [Ref 2]  
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Detailed Description  
I/O Voltage Rails  
There are four available banks on the XC6SLX45T-3FGG484 device. Banks 0, 1, and 2 are  
connected for 2.5V I/O. Bank 3 is used for the 1.5V DDR3 component memory interface of  
Spartan-6 FPGA’s hard memory controller. The voltage applied to the FPGA I/O banks  
used by the SP605 board is summarized in Table 1-2.  
Table 1-2: I/O Voltage Rail of FPGA Banks  
FPGA Bank  
I/O Voltage Rail  
0
1
2
3
2.5V  
2.5V  
2.5V  
1.5V  
References  
See the Xilinx Spartan-6 FPGA documentation for more information at  
http://www.xilinx.com/support/documentation/spartan-6.htm.  
2. 128 MB DDR3 Component Memory  
There are 128 MB of DDR3 memory available on the SP605 board. A 1-Gb Micron  
MT41J64M16LA-187E (96-ball) DDR3 memory component is accessible through Bank 3 of  
the LX45T device. The Spartan-6 FPGA hard memory controller is used for data transfer  
across the DDR3 memory interface's 16-bit data path using SSTL15 signaling. The  
maximum data rate supported is 800 Mb/s with a memory clock running at 400 MHz.  
Signal integrity is maintained through DDR3 resistor terminations and memory on-die  
terminations (ODT), as shown in Table 1-3 and Table 1-4.  
Table 1-3: Termination Resistor Requirements  
Signal Name  
Board Termination  
On-Die Termination  
MEM1_A[14:0]  
MEM1_BA[2:0]  
MEM1_RAS_N  
MEM1_CAS_N  
MEM1_WE_N  
MEM1_CS_N  
MEM1_CKE  
49.9 ohms to V  
49.9 ohms to V  
49.9 ohms to V  
49.9 ohms to V  
49.9 ohms to V  
–
TT  
TT  
TT  
TT  
TT  
–
–
–
–
100 ohms to GND  
–
4.7K ohms to GND  
–
MEM1_ODT  
4.7K ohms to GND  
–
MEM1_DQ[15:0]  
–
–
–
ODT  
ODT  
ODT  
MEM1_UDQS[P,N], MEM1_LDQS[P,N]  
MEM1_UDM, MEM1_LDM  
100 ohm differential at  
memory component  
MEM1_CK[P,N]  
–
Notes:  
1. Nominal value of V for DDR3 interface is 0.75V.  
TT  
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Table 1-4: FPGA On-Chip (OCT) Termination External Resistor Requirements  
U1 FPGA Pin  
FPGA Pin Number  
Board Connection for OCT  
No Connect  
ZIO  
P3  
L6  
RZQ  
100 ohms to GROUND  
Table 1-5 shows the connections and pin numbers for the DDR3 Component Memory.  
Table 1-5: DDR3 Component Memory Connections  
Memory U42  
U1 FPGA  
Schematic Net Name  
Pin  
Pin Number  
Pin Name  
A0  
K2  
K1  
K5  
M6  
H3  
M3  
L4  
K6  
G3  
G1  
J4  
MEM1_A0  
MEM1_A1  
MEM1_A2  
MEM1_A3  
MEM1_A4  
MEM1_A5  
MEM1_A6  
MEM1_A7  
MEM1_A8  
MEM1_A9  
MEM1_A10  
MEM1_A11  
MEM1_A12  
MEM1_A13  
MEM1_A14  
MEM1_BA0  
MEM1_BA1  
MEM1_BA2  
N3  
P7  
A1  
P3  
A2  
N2  
P8  
A3  
A4  
P2  
A5  
R8  
R2  
T8  
R3  
L7  
R7  
N7  
T3  
T7  
M2  
N8  
M3  
A6  
A7  
A8  
A9  
A10/AP  
A11  
E1  
F1  
A12/BCN  
NC/A13  
NC/A14  
BA0  
J6  
H5  
J3  
J1  
BA1  
H1  
BA2  
R3  
R1  
P2  
MEM1_DQ0  
MEM1_DQ1  
MEM1_DQ2  
MEM1_DQ3  
MEM1_DQ4  
MEM1_DQ5  
MEM1_DQ6  
MEM1_DQ7  
MEM1_DQ8  
G2  
H3  
E3  
F2  
DQ6  
DQ4  
DQ0  
DQ2  
DQ7  
DQ5  
DQ1  
DQ3  
DQ11  
P1  
L3  
L1  
M2  
M1  
T2  
H7  
H8  
F7  
F8  
C2  
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Detailed Description  
Table 1-5: DDR3 Component Memory Connections (Cont’d)  
Memory U42  
U1 FPGA  
Pin  
Schematic Net Name  
Pin Number  
Pin Name  
DQ9  
T1  
U3  
U1  
W3  
W1  
Y2  
MEM1_DQ9  
MEM1_DQ10  
MEM1_DQ11  
MEM1_DQ12  
MEM1_DQ13  
MEM1_DQ14  
MEM1_DQ15  
C3  
A2  
D7  
A3  
C8  
B8  
DQ13  
DQ8  
DQ15  
DQ10  
DQ14  
DQ12  
Y1  
A7  
H2  
M5  
M4  
L6  
MEM1_WE_B  
MEM1_RAS_B  
MEM1_CAS_B  
MEM1_ODT  
L3  
J3  
WE_B  
RAS_B  
CAS_B  
ODT  
K3  
K1  
J7  
K4  
K3  
F2  
MEM1_CLK_P  
MEM1_CLK_N  
MEM1_CKE  
CLK_P  
CLK_N  
CKE  
K7  
K9  
F3  
G3  
C7  
B7  
E7  
D3  
T2  
N3  
N1  
V2  
V1  
N4  
P3  
MEM1_LDQS_P  
MEM1_LDQS_N  
MEM1_UDQS_P  
MEM1_UDQS_N  
MEM1_LDM  
LDQS_P  
LDQS_N  
UDQS_P  
UDQS_N  
LDM  
MEM1_UDM  
UDM  
E3  
MEM1_RESET_B  
RESET_B  
References  
See the Micron Technology, Inc. DDR3 SDRAM Specification for more information. [Ref 12]  
Also, see the Spartan-6 FPGA Memory Controller User Guide. [Ref 3]  
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3. SPI x4 Flash  
The Xilinx Spartan-6 FPGA hosts a SPI interface which is visible to the Xilinx iMPACT  
configuration tool. The SPI memory device operates at 3.0V; the Spartan-6 FPGA I/Os are  
3.3V tolerant and provide electrically compatible logic levels to directly access the SPI flash  
through a 2.5V bank. The XC6SLX45T-3FGG484 is a master device when accessing an  
external SPI flash memory device.  
The SP605 SPI interface has two parallel connected configuration options (Figure 1-3): an  
SPI X4 (Winbond W25Q64VSFIG) 64-Mb flash memory device (U32) and a flash  
programming header (J17). J17 supports a user-defined SPI mezzanine board. The SPI  
configuration source is selected via SPI select jumper J46. For details on configuring the  
FPGA, see “Configuration Options.”  
X-Ref Target  
-
Figure 1-3  
SPI Prog  
J17  
FPGA_PROG_B  
1
2
3
FPGA_D2_MISO3  
FPGA_D1_MISO2  
SPI_CS_B  
4
TMS  
FPGA_MOSI_CSI_B_MISO0  
FPGA_D0_DIN_MISO_MISO1  
5
6
7
8
TDI  
TDO  
TCK  
GND  
Silkscreen  
FPGA_CCLK  
GND  
9
VCC3V3  
3V3  
HDR_1X9  
UG526_03_092409  
Figure 1-3: J17 SPI Flash Programming Header  
X-Ref Target  
-
Figure 1-4  
U1  
FPGA SPI Interface  
J17  
U32  
DIN, DOUT, CCLK  
SPI x4  
Flash  
Memory  
SPIX4_CS_B  
SPI_CS_B  
2
1
Winbond  
W25Q64VSFIG  
ON = SPI X4 U32  
OFF = SPI EXT. J17  
J46  
SPI Select  
Jumper  
SPI Program  
Header  
UG526_04_092409  
Figure 1-4: SPI Flash Interface Topology  
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Detailed Description  
SPI HDR J17  
Table 1-6: SPI x4 Memory Connections  
SPI MEM U32  
U1 FPGA  
Schematic Net Name  
Pin  
Pin #  
Pin Name  
Pin #  
Pin Name  
AB2  
T14  
FPGA_PROG_B  
FPGA_D2_MISO3  
FPGA_D1_MISO2_R  
SPI_CS_B  
–
1
9
–
1
2
3
4
5
6
7
8
9
–
–
–
IO3_HOLD_B  
R13  
IO2_WP_B  
–
AA3  
AB20  
AA20  
Y20  
–
–
TMS  
TDI  
TDO  
TCK  
GND  
VCC3V3  
–
FPGA_MOSI_CSI_B_MISO0  
FPGA_D0_DIN_MISO_MISO1  
FPGA_CCLK  
15  
8
DIN  
IO1_DOUT  
16  
–
CLK  
–
–
–
–
–
–
–
J46.2(1)  
SPIX4_CS_B  
7
CS_B  
Notes:  
1. Not a U1 FPGA pin  
References  
See the Winbond Serial Flash Memory Data Sheet for more information. [Ref 13]  
See the XPS Serial Peripheral Interface Data Sheet for more information. [Ref 4]  
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4. Linear BPI Flash  
A Numonyx JS28F256P30 Linear Flash memory (U25) on the SP605 (Figure 1-5) provides  
32 MB of non-volatile storage that can be used for configuration as well as software  
storage. The Linear Flash is operated in asynchronous mode.  
For details on configuring the FPGA, see “Configuration Options.”  
X-Ref Target Figure 1-5  
-
U1  
U25  
ADDR, DATA, CTRL  
Numonyx Type P30  
JS28F256P30  
FPGA  
BPI Flash  
Interface  
UG526_05_092409  
Figure 1-5: Linear BPI Flash Interface  
Table 1-7: Linear Flash Connections  
U25 BPI FLASH  
U1 FPGA Pin  
Schematic Net Name  
Pin Number  
Pin Name  
A1  
N22  
N20  
M22  
M21  
L19  
K20  
H22  
H21  
L17  
K17  
G22  
G20  
K18  
K19  
H20  
J19  
FLASH_A0  
FLASH_A1  
FLASH_A2  
FLASH_A3  
FLASH_A4  
FLASH_A5  
FLASH_A6  
FLASH_A7  
FLASH_A8  
FLASH_A9  
FLASH_A10  
FLASH_A11  
FLASH_A12  
FLASH_A13  
FLASH_A14  
FLASH_A15  
29  
25  
24  
23  
22  
21  
20  
19  
8
A2  
A3  
A4  
A5  
A6  
A7  
A8  
A9  
7
A10  
A11  
A12  
A13  
A14  
A15  
A16  
6
5
4
3
2
1
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Detailed Description  
U25 BPI FLASH  
Table 1-7: Linear Flash Connections (Cont’d)  
U1 FPGA Pin  
Schematic Net Name  
Pin Number  
Pin Name  
A17  
E22  
E20  
F22  
F21  
H19  
H18  
F20  
G19  
FLASH_A16  
FLASH_A17  
FLASH_A18  
FLASH_A19  
FLASH_A20  
FLASH_A21  
FLASH_A22  
FLASH_A23  
55  
18  
17  
16  
11  
10  
9
A18  
A19  
A20  
A21  
A22  
A23  
26  
A24  
AA20  
R13  
FPGA_D0_DIN_MISO_MISO1  
FPGA_D1_MISO2  
FPGA_D2_MISO3  
FLASH_D3  
34  
36  
39  
41  
47  
49  
51  
53  
35  
37  
40  
42  
48  
50  
52  
54  
DQ0  
DQ1  
DQ2  
DQ3  
DQ4  
DQ5  
DQ6  
DQ7  
DQ8  
DQ9  
DQ10  
DQ11  
DQ12  
DQ13  
DQ14  
DQ15  
T14  
AA6  
AB6  
Y5  
FLASH_D4  
FLASH_D5  
AB5  
W9  
FLASH_D6  
FLASH_D7  
T7  
FLASH_D8  
U6  
FLASH_D9  
AB19  
AA18  
AB18  
Y13  
FLASH_D10  
FLASH_D11  
FLASH_D12  
FLASH_D13  
AA12  
AB12  
FLASH_D14  
FLASH_D15  
V13  
R20  
P22  
P21  
T19  
T18  
FMC_PWR_GOOD_FLASH_RST_B  
FLASH_WE_B  
44  
14  
32  
30  
46  
56  
RST_B  
WE_B  
OE_B  
FLASH_OE_B  
FLASH_CE_B  
CE_B  
FLASH_ADV_B  
ADV_B  
WAIT  
FLASH_WAIT  
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FPGA Design Considerations for the Configuration Flash  
The SP605 has the P30 BPI flash connected to the FPGA dual use configuration pins and is  
not shared. It can be used to configure the FPGA, and then controlled post-configuration  
via the FPGA fabric. After FPGA configuration, the FPGA design can disable the  
configuration flash or access the configuration flash to read/write code or data.  
When the FPGA design does not use the configuration flash, the FPGA design must drive  
the FLASH_OE_B pin High in order to disable the configuration flash and put the flash  
into a quiescent, low-power state. Otherwise, the flash memory can continue to drive its  
array data onto the data bus causing unnecessary switching noise and power  
consumption.  
For FPGA designs that access the flash for reading/writing stored code or data, connect  
the FPGA design or EDK embedded memory controller (EMC) peripheral to the flash  
through the pins defined in Figure 1-7, page 18.  
References  
See the Numonyx StrataFlash Embedded Memory Data Sheet for more information. [Ref 14]  
In addition, see the Spartan-6 FPGA Configuration User Guide for more information. [Ref 2]  
5. System ACE CF and CompactFlash Connector  
The Xilinx System ACE CompactFlash (CF) configuration controller allows a Type I or  
Type II CompactFlash card to program the FPGA through the JTAG port. Both hardware  
and software data can be downloaded through the JTAG port. The System ACE CF  
controller supports up to eight configuration images on a single CompactFlash card. The  
configuration address switches allow the user to choose which of the eight configuration  
images to use.  
The CompactFlash (CF) card shipped with the board is correctly formatted to enable the  
System ACE CF controller to access the data stored in the card. The System ACE CF  
controller requires a FAT16 file system, with only one reserved sector permitted, and a  
sector-per-cluster size of more than one (UnitSize greater than 512). The FAT16 file system  
supports partitions of up to 2 GB. If multiple partitions are used, the System ACE CF  
directory structure must reside in the first partition on the CompactFlash, with the  
xilinx.sysfile located in the root directory. The xilinx.sysfile is used by the System  
ACE CF controller to define the project directory structure, which consists of one main  
folder containing eight sub-folders used to store the eight ACE files containing the  
configuration images. Only one ACE file should exist within each sub-folder. All folder  
names must be compliant to the DOS 8.3 short file name format. This means that the folder  
names can be up to eight characters long, and cannot contain the following reserved  
characters: < > " / \ |. This DOS 8.3 file name restriction does not apply to the actual ACE  
file names.  
Other folders and files may also coexist with the System ACE CF project within the FAT16  
partition. However, the root directory must not contain more than a total of 16 folder  
and/or file entries, including deleted entries. When ejecting or unplugging the  
CompactFlash device, it is important to safely stop any read or write access to the  
CompactFlash device to avoid data corruption.  
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System ACE CF error and status LEDs indicate the operational state of the System ACE CF  
controller:  
•
•
•
•
A blinking red error LED indicates that no CompactFlash card is present  
A solid red error LED indicates an error condition during configuration  
A blinking green status LED indicates a configuration operation is ongoing  
A solid green status LED indicates a successful download  
The mode SW1 setting is important because the System ACE CF can fail to configure the  
FPGA when the mode pins are set to the master modes (Table 1-30, page 55). A  
configuration failure from the master mode can drive INIT_B low, which blocks the  
System ACE CF from downloading a configuration ACE file. The FPGA mode pins must  
be set as specified in Table 1-30 for the System ACE CF configuration solution.  
With the mode switch SW1 set to 10 (Slave SelectMAP, Table 1-30), if a Compact Flash (CF)  
card is installed in the CF socket U37, the System ACE CF will attempt to load a bitstream  
from the CF card image address pointed to by the image select switch S1.  
Every time a CompactFlash card is inserted into the System ACE CF socket, a  
configuration operation is initiated. Pressing the System ACE CF reset button reprograms  
the FPGA.  
Note: System ACE CF configuration is enabled by way of DIP switch S1. See “17. Switches,”  
page 46 for more details.  
The System ACE CF MPU port (Table 1-8) is connected to the FPGA. This connection  
allows the FPGA to use the System ACE CF controller to reconfigure the system or access  
the CompactFlash card as a generic FAT file system.  
Table 1-8: System ACE CF Connections  
U17 XCCACETQ144I  
U1 FPGA Pin  
Schematic Net Name(1)  
Pin Number  
Pin Name  
MPD00  
MPD01  
MPD02  
MPD03  
MPD04  
MPD05  
MPD06  
MPD07  
MPA00  
MPA01  
MPA02  
MPA03  
MPA04  
MPA05  
MPA06  
N6  
N7  
U4  
T4  
P6  
P7  
T3  
R4  
V5  
V3  
P5  
P4  
H4  
G4  
D2  
SYSACE_D0  
SYSACE_D1  
66  
65  
63  
62  
61  
60  
59  
58  
70  
69  
68  
67  
45  
44  
43  
SYSACE_D2  
SYSACE_D3  
SYSACE_D4  
SYSACE_D5  
SYSACE_D6  
SYSACE_D7  
SYSACE_MPA00  
SYSACE_MPA01  
SYSACE_MPA02  
SYSACE_MPA03  
SYSACE_MPA04  
SYSACE_MPA05  
SYSACE_MPA06  
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Table 1-8: System ACE CF Connections (Cont’d)  
U17 XCCACETQ144I  
Pin Number Pin Name  
U1 FPGA Pin  
Schematic Net Name(1)  
AA1  
W4  
SYSACE_MPBRDY  
SYSACE_MPCE  
SYSACE_MPIRQ  
SYSACE_MPOE  
SYSACE_MPWE  
SYSACE_CFGTDI  
FPGA_TCK  
39  
42  
41  
77  
76  
81  
80  
82  
85  
93  
MPBRDY  
MPCE  
AA2  
T6  
MPIRQ  
MPOE  
T5  
MPWE  
CFGTDI  
CFGTCK  
CFGTDO  
CFGTMS  
CLK  
G17  
A21  
E18  
D20  
N19  
FPGA_TDI  
FPGA_TMS  
CLK_33MHZ_SYSACE(2)  
Notes:  
1. U17 System ACE CF controller 3.3V signals as named are wired to a set of TXB0108 3.3V-to-1.5V level  
shifters. The nets between the 1.5V side of the level shifters and the U1 FPGA have the same names  
with _LS appended.  
2. The System ACE CF clock is sourced from U29 32.000MHz oscillator.  
References  
See the System ACE CF product page for more information at  
http://www.xilinx.com/support/documentation/system_ace_solutions.htm.  
In addition, see the System ACE CompactFlash Solution Data Sheet. [Ref 5]  
6. USB JTAG  
JTAG configuration is provided through onboard USB-to-JTAG configuration logic where  
a computer host accesses the SP605 JTAG chain through a Type-A (computer host side) to  
Type-Mini-B (SP605 side) USB cable. The JTAG chain of the board is illustrated in  
Figure 1-6. JTAG configuration is allowable at any time under any mode pin setting. JTAG  
initiated configuration takes priority over the mode pin settings.  
X-Ref Target Figure 1-6  
-
J19  
3.3V 2.5V  
J4  
FMC LPC  
System ACE CF  
FPGA  
TDI  
TDO  
TSTTDI CFGTDO  
TDI  
Buffer  
TSTTDO CFGTDI  
TDO  
U1  
J2  
U17  
UG526_06_092409  
Figure 1-6: JTAG Chain Diagram  
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FMC bypass jumper J19 must be connected between pins 1-2 (bypass) to enable JTAG  
access to the FPGA on the basic SP605 board (without FMC expansion modules installed),  
as shown in Figure 1-7. When the VITA 57.1 FMC LPC expansion connector is populated  
with an expansion module that has a JTAG chain, jumper J19 must be set to connect pins  
2-3 in order to include the FMC expansion module's JTAG chain in the main SP605 JTAG  
chain.  
X-Ref Target Figure 1-7  
-
J19  
1
2
3
FMC_TDI_BUF  
SYSACE_TDI  
FMC_TD0  
Bypass FMC LPC J2 = Jumper 1-2  
Include FMC LPC J2 = Jumper 2-3  
H - 1x3  
UG526_07_092409  
Figure 1-7: VITA 57.1 FMC LPC (J2) JTAG Bypass Jumper J19  
The JTAG chain can be used to program the FPGA and access the FPGA for hardware and  
software debug.  
The JTAG connector (USB Mini-B J4) allows a host computer to download bitstreams to the  
FPGA using the Xilinx iMPACT software tool. In addition, the JTAG connector allows  
debug tools such as the ChipScope® Pro Analyzer tool or a software debugger to access  
the FPGA. The iMPACT software tool can also program the BPI flash via the USB J4  
connection. iMPACT can download a temporary design to the FPGA through the JTAG.  
This provides a connection within the FPGA from the FPGAs JTAG port to the FPGAs BPI  
interface. Through the connection made by the temporary design in the FPGA, iMPACT  
can indirectly program the BPI flash from the JTAG USB J4 connector. For an overview on  
configuring the FPGA, see “Configuration Options,” page 55.  
7. Clock Generation  
There are three clock sources available on the SP605.  
Oscillator (Differential)  
The SP605 has one 2.5V LVDS differential 200 MHz oscillator (U6) soldered onto the board  
and wired to an FPGA global clock input.  
•
•
Crystal oscillator: Epson EG-2121CA-200.0000M-LHPA  
PPM frequency jitter: 50 ppm  
References  
See the Epson EG-2121CA Data Sheet for more information. Search EG-2121CA at Epson  
Toyocom. [Ref 15]  
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Oscillator Socket (Single-Ended, 2.5V or 3.3V)  
One populated single-ended clock socket (X2) is provided for user applications. The option  
of 2.5V or 3.3V power may be selected via a 0 ohm resistor selection. The SP605 board is  
shipped with a 27 MHz 2.5V oscillator installed.  
Figure 1-8 shows the unpopulated user oscillator socket. This figure indicates the socket  
pin 1 location. Figure 1-9 shows the oscillator installed, with its pin 1 location identifiers.  
X-Ref Target  
-
Figure 1-8  
Silkscreened outline  
has beveled corner  
Socket has notch  
in crossbar  
UG526_08_100509  
Figure 1-8: SP605 X2 Oscillator Socket Pin 1 Location Identifiers  
X-Ref Target  
-
Figure 1-9  
Oscillator top has  
corner dot marking  
Oscillator body has  
one square corner  
UG526_09_100509  
Figure 1-9: SP605 X2 Oscillator Pin 1 Location Identifiers  
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Detailed Description  
SMA Connectors (Differential)  
A high-precision clock signal can be provided to the FPGA using differential clock signals  
through the onboard 50-ohm SMA connectors J38 (N) and J41 (P).  
Table 1-9: SP605 Clock Source Connections  
Pin  
Number  
Source  
U1 FPGA Pin  
Schematic Net Name  
Pin Name  
K22  
K21  
SYSCLK_N  
SYSCLK_P  
5
4
OUT_B  
OUT  
OUT  
–
U6 200MHZ OSC  
X2 27MHZ OSC  
USER_SMA_CLOCK  
SMA Connectors  
AB13  
M19  
M20  
USER_CLOCK  
5
USER_SMA_CLOCK_N  
USER_SMA_CLOCK_P  
J38.1  
J41.1  
–
8. Multi-Gigabit Transceivers (GTP MGTs)  
The SP605 provides access to 4 MGTs.  
•
•
•
•
One (1) MGT is wired to the PCIe x1 Endpoint (P4) edge connector fingers  
One (1) MGT is wired to the FMC LPC connector (J2)  
One (1) MGT is wired to MGT SMA connectors (J36, J37)  
One (1) MGT is wired to the SFP Module connector (P4)  
The SP605 includes a set of six SMA connectors for the GTP (MGT) RX/TX Port and GTP  
(MGT) Clock as described in Figure 1-10 and Table 1-10.  
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X-Ref Target Figure 1-10  
-
J35 32K10K-400E3  
2
3
4
5
6
7
8
GND1  
GND2  
GND3  
SMA_RX_C_N  
1
SIG GND4  
GND5  
GND6  
GND7  
SMA_RX_N  
SMA_RX_P  
J34 32K10K-400E3  
2
GND1  
GND2  
GND3  
3
4
5
6
7
8
SMA_RX_C_P  
1
SIG GND4  
GND5  
GND6  
GND7  
SMA MGT Connectors  
J33 32K10K-400E3  
2
GND1  
GND2  
GND3  
3
4
5
6
7
8
1
SIG GND4  
GND5  
GND6  
GND7  
SMA_TX_N  
SMA_TX_P  
J32 32K10K-400E3  
2
3
4
5
6
7
8
GND1  
GND2  
GND3  
1
SIG GND4  
GND5  
GND6  
GND7  
J36 32K10K-400E3  
2
3
4
5
6
7
8
GND1  
GND2  
GND3  
MGT REFCLK  
SMA_REFCLK_C_N  
1
SIG GND4  
GND5  
GND6  
GND7  
SMA_REFCLK_N  
SMA_REFCLK_P  
J37 32K10K-400E3  
2
3
4
5
6
7
8
GND1  
GND2  
GND3  
SMA_REFCLK_C_P  
1
SIG GND4  
GND5  
GND6  
GND7  
UG526_10 _092409  
Figure 1-10: GTP SMA Clock  
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Table 1-10: GTP SMA Clock Connections  
U1 FPGA Pin  
Schematic Net Name  
SMA_RX_N  
SMA Pin  
J35.1  
C9  
D9  
SMA_RX_P  
J34.1  
A8  
SMA_TX_N  
J33.1  
B8  
SMA_TX_P  
J32.1  
D11  
C11  
SMA_REFCLK_N  
SMA_REFCLK_P  
J36.1  
J37.1  
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9. PCI Express Endpoint Connectivity  
The 1-lane PCIe edge connector performs data transfers at the rate of 2.5 GT/s for a Gen1  
application. The Spartan-6 FPGA GTP MGT is used for the multi-gigabit per second serial  
interface.  
The SP605 board trace impedance on the PCIe lane supports Gen1 applications. The SP605  
supports Gen1 x1.  
Table 1-11: PCIe Edge Connector Connections  
P4 PCIe Edge Connector  
U1 FPGA Pin  
Schematic Net Name  
Pin Number  
B15  
Pin Name  
PETn0  
C7  
D7  
A6  
B6  
–
PCIE_RX0_N  
PCIE_RX0_P  
B14  
PETp0  
PCIE_TX0_N(1)  
A17  
PERn0  
PERp0  
REFCLK-  
REFCLK+  
NQ  
PCIE_TX0_P(1)  
A16  
PCIE_CLK_QO_N(2)  
PCIE_CLK_QO_P(2)  
PCIE_250M_N(3)  
PCIE_250M_P(3)  
PCIE_PERST_B_LS  
A14  
–
A13  
B10  
A10  
J7  
U48.17(4)  
U48.18(4)  
A11  
Q
PERST(5)  
Notes:  
1. Each of the TX0_N/P signals has a 0.1uF series capacitor.  
2. PCIE_CLK_QO_N/P is the PC motherboard 100MHZ REFCLK.  
3. Each of the PCIE_250M_N/P signals has a 0.1uF series capacitor.  
4. U48 is an ICS874001 clock multiplier device (U48.17/18 are not P4 pins).  
5. The PERST signal from pin P4.A11 is isolated by a series resistor and then level-shifted by U52 before  
making the FPGA pin U1.J7 connection.  
The PCIe interface obtains its power from the DC power supply provided with the SP605  
or through the 12V ATX power supply connector. The PCIe edge connector is not used for  
any power connections.  
The board can be powered by one of two 12V sources; J18, a 6-pin (2x3) Mini-Fit-type  
connector and J27, a 4-pin (inline) ATX disk drive type connector.  
The 6-pin Mini-Fit-type connector provides 60W (12V @ 5A) from the AC power adapter  
provided with the board while the 4-pin ATX disk drive type connector is provided for  
users who want to power their board while it is installed inside a PC chassis.  
For applications requiring additional power, such as the use of expansion cards drawing  
significant power, a larger AC adapter might be required. If a different AC adapter is used,  
its load regulation should be better than 10%.  
SP605 power slide switch SW2 turns the board on and off by controlling the 12V supply to  
the board.  
Caution! Caution! Never apply power to the power brick 6-pin Mini-Fit type connector (J18)  
and the 4-pin ATX disk drive type connector (J27) at the same time as this will result in damage  
to the board. Never connect an auxiliary PCIe 6-pin power connector to J18 6-pin Mini-Fit type  
connector on the SP605 board as this could result in damage to the PCIe motherboard and/or  
SP605 board. The 6-pin Mini-Fit type connector is marked with a no PCIe power label to warn  
users of the potential hazard.  
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Detailed Description  
References  
See the Spartan-6 FPGA GTP Transceivers User Guide for more information. [Ref 6]  
Also, see the following websites for more information about the Spartan-6 FPGA Integrated  
Endpoint Block for PCI Express:  
•
Product information,  
http://www.xilinx.com/products/ipcenter/S6_PCI_Express_Block.htm  
•
IP data sheets, http://www.xilinx.com/support/documentation/ipbusinterfacei-  
o_pci-express.htm#131486  
In addition, see the PCI Express specifications for more information. [Ref 16]  
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10. SFP Module Connector  
The board contains a small form-factor pluggable (SFP) connector and cage assembly that  
accepts SFP modules. The SFP interface is connected to MGT Bank 123 on the FPGA. The  
SFP module serial ID interface is connected to the "SFP" IIC bus (see “14. IIC Bus,” page 35  
for more information). The control and status signals for the SFP module are connected to  
jumpers and test points as described in Table 1-12. The SFP module connections are shown  
in Table 1-13.  
Table 1-12: SFP Module Control and Status  
SFP Control/Status Signal  
Board Connection  
Test Point J15  
SFP_TX_FAULT  
High = Fault  
Low = Normal Operation  
Jumper J44  
SFP_TX_DISABLE  
SFP_MOD_DETECT  
SFP_RT_SEL  
Off = SFP Enabled  
On = SFP Disabled  
Test Point J16  
High = Module Not Present  
Low = Module Present  
Jumper J22  
Jumper Pins 1-2 = Full Bandwidth  
Jumper Pins 2-3 = Reduced Bandwidth  
Test Point J14  
SFP_LOS  
High = Loss of Receiver Signal  
Low = Normal Operation  
Table 1-13: SFP Module Connections  
P2 SFP Module Connector  
U1 FPGA Pin  
Schematic Net Name  
Pin Number  
Pin Name  
D13  
C13  
B14  
A14  
T17  
Y8  
SFP_RX_P  
SFP_RX_N  
13  
RDP  
12  
RDN  
SFP_TX_P  
18  
TDP  
SFP_TX_N  
19  
TDN  
SFP_LOS  
8
LOS  
SFP_TX_DISABLE_FPGA  
SFPCLK_QO_N(1)  
SFPCLK_QO_P(1)  
3
TX_DISABLE  
A12  
B12  
U47.6(2)  
U47.7(2)  
-
-
Notes:  
1. The 125MHz SFP clock is sourced by clock driver U47.  
2. Not P2 SFP module pins.  
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Detailed Description  
11. 10/100/1000 Tri-Speed Ethernet PHY  
The SP605 uses the onboard Marvell Alaska PHY device (88E1111) for Ethernet  
communications at 10, 100, or 1000 Mb/s. The board supports a GMII interface from the  
FPGA to the PHY. The PHY connection to a user-provided Ethernet cable is through a  
Halo HFJ11-1G01E RJ-45 connector with built-in magnetics.  
On power-up, or on reset, the PHY is configured to operate in GMII mode with PHY  
address 0b00111using the settings shown in Table 1-14. These settings can be  
overwritten via software commands passed over the MDIO interface.  
Table 1-14: PHY Configuration Pins  
Connection on  
Board  
Bit[2]  
Bit[1]  
Bit[0]  
Pin  
Definition and Value Definition and Value Definition and Value  
CFG2  
CFG3  
CFG4  
CFG5  
CFG6  
VCC 2.5V  
VCC 2.5V  
ANEG[3] = 1  
ANEG[0] = 1  
ANEG[2] = 1  
ENA_XC = 1  
ANEG[1] = 1  
DIS_125 = 1  
VCC 2.5V  
HWCFG_MD[2] = 1 HWCFG_MD[1] = 1 HWCFG_MD[0] = 1  
VCC 2.5V  
DIS_FC = 1  
DIS_SLEEP = 1  
INT_POL = 1  
HWCFG_MD[3] = 1  
75/50 OHM = 0  
PHY_LED_RX  
SEL_BDT = 0  
Table 1-15 shows the connections and pin numbers for the PHY.  
Table 1-15: Ethernet PHY Connections  
U46 M88E111  
U1 FPGA Pin  
Schematic Net Name  
Pin Number  
Pin Name  
V20  
R19  
J20  
PHY_MDIO  
PHY_MDC  
PHY_INT  
33  
35  
MDIO  
MDC  
32  
INT_B  
RESET_B  
CRS  
J22  
PHY_RESET  
PHY_CRS  
36  
N15  
M16  
P20  
U20  
T22  
P19  
Y22  
Y21  
W22  
W20  
V22  
V21  
115  
114  
7
PHY_COL  
COL  
PHY_RXCLK  
PHY_RXER  
PHY_RXCTL_RXDV  
PHY_RXD0  
PHY_RXD1  
PHY_RXD2  
PHY_RXD3  
PHY_RXD4  
PHY_RXD5  
PHY_RXD6  
RXCLK  
RXER  
RXDV  
RXD0  
RXD1  
RXD2  
RXD3  
RXD4  
RXD5  
RXD6  
8
4
3
128  
126  
125  
124  
123  
121  
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Table 1-15: Ethernet PHY Connections (Cont’d)  
U46 M88E111  
U1 FPGA Pin  
Schematic Net Name  
Pin Number  
Pin Name  
RXD7  
U22  
AB7  
L20  
U8  
PHY_RXD7  
PHY_TXC_GTPCLK  
PHY_TXCLK  
PHY_TXER  
120  
14  
10  
13  
16  
18  
19  
20  
24  
25  
26  
28  
29  
GTXCLK  
TXCLK  
TXER  
T8  
PHY_TXCTL_TXEN  
PHY_TXD0  
TXEN  
TXD0  
U10  
T10  
AB8  
AA8  
AB9  
Y9  
PHY_TXD1  
TXD1  
PHY_TXD2  
TXD2  
PHY_TXD3  
TXD3  
PHY_TXD4  
TXD4  
PHY_TXD5  
TXD5  
Y12  
W12  
PHY_TXD6  
TXD6  
PHY_TXD7  
TXD7  
References  
See the Marvell Alaska Gigabit Ethernet Transceivers product page for more information.  
[Ref 17]  
Also, see the LogiCORE™ IP Tri-Mode Ethernet MAC User Guide. [Ref 7]  
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12. USB-to-UART Bridge  
The SP605 contains a Silicon Labs CP2103GM USB-to-UART bridge device (U4) which  
allows connection to a host computer with a USB cable. The USB cable is supplied in this  
evaluation kit (Type A end to host computer, Type Mini-B end to SP605 connector J23).  
Table 1-16 details the SP605 J23 pinout.  
Xilinx UART IP is expected to be implemented in the FPGA fabric (for instance, Xilinx XPS  
UART Lite). The FPGA supports the USB-to-UART bridge using four signal pins: Transmit  
(TX), Receive (RX), Request to Send (RTS), and Clear to Send (CTS).  
Silicon Labs provides royalty-free Virtual COM Port (VCP) drivers which permit the  
CP2103GM USB-to-UART bridge to appear as a COM port to host computer  
communications application software (for example, HyperTerm or TeraTerm). The VCP  
device driver must be installed on the host PC prior to establishing communications with  
the SP605. Refer to the evaluation kit Getting Started Guide for driver installation  
instructions.  
Table 1-16: USB Type B Pin Assignments and Signal Definitions  
USB Connector  
Signal Name  
Description  
Pin  
1
VBUS  
+5V from host system (not used)  
2
USB_DATA_N Bidirectional differential serial data (N-side)  
USB_DATA_P Bidirectional differential serial data (P-side)  
3
4
GROUND  
Signal ground  
Table 1-17: USB-to-UART Connections  
UART Function Schematic Net U30 CP2103GM UART Function  
U1 FPGA Pin  
in FPGA  
RTS, output  
CTS, input  
TX, data out  
RX, data in  
Name  
Pin  
in CP2103GM  
F18  
F19  
B21  
H17  
USB_1_CTS  
USB_1_RTS  
USB_1_RX  
USB_1_TX  
22  
CTS, input  
23  
RTS, output  
RXD, data in  
TXD, data out  
24  
25  
Notes:  
1. The schematic net names correspond with the CP2103GM pin names and functions, and the UART IP  
in the FPGA must be connected accordingly.  
References  
Refer to the Silicon Labs website for technical information on the CP2103GM and the VCP  
drivers.  
In addition, see some of the Xilinx UART IP specifications at:  
•
•
http://www.xilinx.com/support/documentation/ip_documentation/xps_uartlite.pdf  
http://www.xilinx.com/support/documentation/ip_documentation/xps_uart16550.pdf  
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13. DVI CODEC  
A DVI connector (P3) is present on the board to support an external video monitor. The  
DVI circuitry utilizes a Chrontel CH7301C (U31) capable of 1600 X 1200 resolution with 24-  
bit color. The video interface chip drives both the digital and analog signals to the DVI  
connector. A DVI monitor can be connected to the board directly. A VGA monitor can also  
be connected to the board using the supplied DVI-to-VGA adaptor. The Chrontel  
CH7301C is controlled by way of the video IIC bus.  
The DVI connector (Table 1-18) supports the IIC protocol to allow the board to read the  
monitor's configuration parameters. These parameters can be read by the FPGA using the  
DVI IIC bus (see “14. IIC Bus,” page 35).  
Table 1-18: DVI Controller Connections  
U31 Chrontel CH7301C  
Schematic Net  
U1 FPGA Pin  
Name  
Pin Number  
Pin Name  
D0  
K16  
U19  
T20  
DVI_D0  
DVI_D1  
63  
62  
61  
60  
59  
58  
55  
54  
53  
52  
51  
50  
2
D1  
DVI_D2  
D2  
N16  
P16  
DVI_D3  
D3  
DVI_D4  
D4  
M17  
M18  
R15  
DVI_D5  
D5  
DVI_D6  
D6  
DVI_D7  
D7  
R16  
DVI_D8  
D8  
P17  
DVI_D9  
D9  
P18  
DVI_D10  
DVI_D11  
DVI_DE  
D10  
R17  
D11  
J17  
DE  
J16  
DVI_H  
4
H
L15  
DVI_RESET_B  
DVI_V  
13  
5
RESET_B  
V
B22  
C22  
DVI_XCLK_N  
DVI_XCLK_P  
DVI_GPIO0  
DVI_GPIO1  
56  
57  
8
XCLK_N  
XCLK_P  
GPIO0  
GPIO1  
C20  
No Connect  
D22  
7
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Detailed Description  
14. IIC Bus  
The SP605 implements three IIC bus interfaces at the FPGA.  
The MAIN IIC bus hosts four items:  
•
•
•
•
FPGA U1 Bank 1 "MAIN" IIC interface  
8-Kb NV Memory U4  
FMC LPC connector J2  
2-Pin External Access Header J45  
The DVI IIC bus hosts two items:  
•
•
FPGA U1 Bank 2 DVI IIC interface  
DVI Codec U31 and DVI connector P3  
The SFP IIC bus hosts two items:  
•
•
FPGA U1 Bank 0 SFP IIC interface  
SFP module connector P2  
The SP605 IIC bus topology is shown in Figure 1-11.  
X-Ref Target Figure 1-11  
-
U1  
U4  
ST MICRO  
M24C08-WDW6TP  
IIC_SDA_MAIN  
IIC_SCL_MAIN  
BANK 1  
BANK 0  
BANK 2  
Addr: 0b1010100  
through  
0b1010111  
IIC_SDA_SFP  
IIC_SCL_SFP  
IIC_SDA_DVI  
IIC_SCL_DVI  
J2  
FMC LPC  
Column C  
2 Kb EEPROM on  
any FMC LPC  
Mezzanine Card  
Addr: 0b1010010  
LEVEL  
SHIFTER  
P3  
IIC_CLK_DVI_F  
J45  
DVI Connector  
IIC_SDA_DVI_F  
2-Pin External  
Access Header  
Addr: 0b1010000  
U31  
P2  
SFP Module  
Connector  
DVI CODEC  
CHRONTEL  
CH730C-TF  
Addr: 0b1110110  
Addr: 0b1010000  
UG526_11_092609  
Figure 1-11: IIC Bus Topology  
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Table 1-19: IIC Bus Connections  
Schematic  
Netname  
Level-Shifted  
Connection  
Level-Shifted  
Net Name  
U1 FPGA Pin  
Connected To  
R22  
T21  
AA4  
W13  
E6  
IIC_SDA_MAIN  
IIC_SCL_MAIN  
IIC_SDA_DVI  
IIC_SCL_DVI  
IIC_SDA_SFP  
IIC_SCL_SFP  
J2.C31, U4.5(1)  
J2.C30, U4.6(1)  
Q8.2, U31.14  
Q7.2, U31.15  
P2.4  
–
–
–
–
Q8.3, P3.7  
IIC_SDA_DVI_F  
Q7.3, P3.6  
IIC_CLK_DVI_F  
–
–
–
–
E5  
P2.5  
Notes:  
1. U4 IIC bus signals are resistively coupled with 0 ohm resistors  
2. Legend  
J2, FMC LPC Connector  
P2, SFP Module Connector  
P3, DVI Connector  
Qn.n, Level-Shifting Transistor  
U31, Chrontel CH7301C  
8-Kb NV Memory  
The SP605 hosts a 8-Kb ST Microelectronics M24C08-WDW6TP IIC parameter storage  
memory device (U4). The IIC address of U4 is 0b1010100, and U4 is not write protected  
(WP pin 7 is tied to GND).  
The IIC memory is shown in Figure 1-12.  
X-Ref Target Figure 1-12  
-
VCC3V3  
1
2
1
2
1
2
R6  
R5  
R50  
IIC Address 0b1010100  
1.0K  
1.0K  
DNP  
5%  
5%  
1%  
1/10W  
1/10W  
1/16W  
VCC3V3  
U4  
6
5
IIC_SCL_MAIN  
IIC_SDA_MAIN  
SCL  
SDA  
7
WP  
1
C40  
1
2
3
0.1UF  
2
A0  
A1  
A2  
8
4
X5R  
10V  
VCC  
GND  
J45  
2
1
M24C08-WDW6TP  
1
2
H-1X2  
R216  
0
5%  
External Access  
Header  
UG526_12 _100509  
Figure 1-12: IIC Memory U4  
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Detailed Description  
IIC Memory U4  
Table 1-20: IIC Memory Connections  
U1 FPGA Pin  
Schematic Netname  
Pin Number  
Pin Name  
A0  
Not Applicable  
Not Applicable  
Not Applicable  
R22  
Tied to GND  
1
2
3
5
6
7
Tied to GND  
A1  
Pulled up (0 ohm) to VCC3V3  
IIC_SDA_MAIN  
IIC_SCL_MAIN  
Tied to GND  
A2  
SDA  
SCL  
WP  
T21  
Not Applicable  
References  
See the ST Micro M24C08 Data Sheet for more information. [Ref 18]  
In addition, see the Xilinx XPS IIC Bus Interface Data Sheet. [Ref 8]  
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15. Status LEDs  
Table 1-21 defines the status LEDs.  
Table 1-21: Status LEDs  
Reference  
Designator  
Signal Name  
Color  
Label  
Description  
DS1  
FMC_PWR_GOOD_FLASH_RST_B  
FPGA_DONE  
Green  
Green  
Green  
Green  
Green  
Green  
Green  
FMC PWR GD  
DONE  
FMC Power Good  
FPGA DONE  
GPIO_LED_0  
GPIO_LED_1  
GPIO_LED_2  
GPIO_LED_3  
FPGA AWAKE  
DS2  
DS3  
GPIO_LED_0  
DS4  
GPIO_LED_1  
DS5  
GPIO_LED_2  
DS6  
GPIO_LED_3  
DS7  
FPGA_AWAKE  
System ACE CF  
Status LED  
DS8  
DS9  
SYSACE_STAT_LED  
Green  
Green  
System ACE CF Status  
TI_PWRGOOD (AND)  
MGT_TI_PWRGOOD  
TI_CORE_PWR+TI_MGT_PWR  
GOOD  
POWER GOOD  
DS10  
DS14  
DS15  
DS17  
LED_RED / LED_GRN  
VCC12_P  
Red/Green  
Green  
STATUS  
12V  
USB JTAG Controller Status  
12V Power On  
(U11.9 PGOOD PIN)  
FPGA_INIT_B  
Green  
DDR3 PWR GD  
INIT  
DDR3 1.5V Power On  
FPGA INIT  
Red  
System ACE CF  
Error LED  
DS18  
DS19  
SYSACE_ERR_LED  
MGT_POWERGOOD  
Red  
System ACE CF Error  
MGT_AVCC Power On  
Green  
MGT_AVCC GD  
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Ethernet PHY Status LEDs  
The Ethernet PHY status LEDs (DS11-DS13) are mounted in right-angle plastic housings to  
make them visible on the connector end of the board when the SP605 board is installed into  
a PC motherboard. This cluster of six LEDs is installed adjacent to the RJ45 Ethernet jack  
P1.  
X-Ref Target Figure 1-13  
-
Direction  
Indicator  
Link Rate  
(Mbps)  
DUP  
TX  
RX  
10  
100  
1000  
P1  
End view of SP605 Ethernet jack and  
status LEDs when installed vertically  
in a PC chassis  
UG526_13 _092409  
Figure 1-13: Ethernet PHY Status LEDs  
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FPGA INIT and DONE LEDs  
The typical Xilinx FPGA power up and configuration status LEDs are present on the  
SP605.  
The red INIT LED DS17 comes on momentarily after the FPGA powers up and during its  
internal power-on process. The DONE LED DS2 comes on after the FPGA programming  
bitstream has been downloaded and the FPGA successfully configured.  
X-Ref Target Figure 1-14  
-
VCC2V5  
1
R169  
VCC2V5  
332  
1%  
1/16W  
2
FPGA_DONE  
VCC2V5  
1
R19  
2
1
4.7K  
5%  
1/16W  
1
2
R70  
2
27.4  
1%  
1/16W  
FPGA_INIT_B  
INIT_B = 0, LED: ON  
INIT_B = 1, LED: OFF  
UG526_14 _092409  
Figure 1-14: FPGA INIT and DONE LEDs  
Table 1-22: FPGA INIT and DONE LED Connections  
Schematic Net  
U1 FPGA Pin  
Controlled LED  
Name  
Y4  
FPGA_INIT_B  
FPGA_DONE  
DS17 INIT, Red  
AB21  
DS2 DONE, Green  
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16. User I/O  
The SP605 provides the following user and general purpose I/O capabilities:  
•
•
•
•
•
User LEDs  
User Pushbutton Switches  
User DIP Switch  
User SIP Header  
User SMA GPIO  
User LEDs  
The SP605 provides four active-High green LEDs as described in Figure 1-15 and  
Table 1-23.  
X-Ref Target Figure 1-15  
-
GPIO LED 3  
GPIO LED 2  
GPIO LED 1  
GPIO LED 0  
1
1
2
1
2
1
2
R74  
27.4  
1%  
R73  
27.4  
1%  
R72  
27.4  
1%  
R71  
27.4  
1%  
2
1/16W  
1/16W  
1/16W  
1/16W  
UG526_15_092409  
Figure 1-15: User LEDs  
Table 1-23: User LED Connections  
U1 FPGA Pin  
D17  
Schematic Net Name  
Controlled LED  
GPIO_LED_0  
GPIO_LED_1  
GPIO_LED_2  
GPIO_LED_3  
DS3  
DS4  
DS5  
DS6  
AB4  
D21  
W15  
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User Pushbutton Switches  
The SP605 provides five active-High pushbutton switches: SW4, SW5, SW6, SW7 and SW8.  
The five pushbuttons all have the same topology as the sample shown in Figure 1-16. Four  
pushbuttons are assigned as GPIO, and the fifth is assigned as a CPU_RESET. Figure 1-16  
and Table 1-24 describe the pushbutton switches.  
X-Ref Target Figure 1-16  
-
VCC1V5  
Pushbutton  
1
2
4
3
P1  
P4  
CPU_RESET  
P2  
P3  
SW6  
1
2
R230  
1.00K  
1%  
1/16W  
UG526_16_092409  
Figure 1-16: User Pushbutton Switch (Typical)  
Table 1-24: Pushbutton Switch Connections  
U1 FPGA Pin  
Schematic Netname  
GPIO_BUTTON_0  
Switch Pin  
SW4.2  
F3  
G6  
F5  
GPIO_BUTTON_1  
GPIO_BUTTON_2  
GPIO_BUTTON_3  
CPU_RESET  
SW7.2  
SW5.2  
C1  
H8  
SW8.2  
SW6.2  
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Detailed Description  
User DIP Switch  
The SP605 includes an active-High four-pole DIP switch, as described in Figure 1-17 and  
Table 1-25. Three poles (switches 1-3) are pulled up to 2.5V, and one pole (switch 4) is  
pulled up to 1.5V, when closed.  
X-Ref Target  
-
Figure 1-17  
VCC1V5_FPGA  
VCC2V5  
S2  
5
6
7
8
4
3
2
1
GPIO_SWITCH_3  
GPIO_SWITCH_2  
GPIO_SWITCH_1  
GPIO_SWITCH_0  
SDMX-4-X  
2
1
2
1
2
1
2
1
UG526_17 _102609  
Figure 1-17: User DIP Switch S2  
Table 1-25: User DIP Switch Connections  
U1 FPGA Pin  
Schematic Net Name  
GPIO_SWITCH_0  
GPIO_SWITCH_1  
GPIO_SWITCH_2  
GPIO_SWITCH_3  
DIP Switch Pin  
C18  
Y6  
S2.1  
S2.2  
S2.3  
S2.4  
W6  
E4  
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User SIP Header  
The SP605 includes a 6-pin single-inline (SIP) male pin header (J55) for FPGA GPIO access.  
Four pins of J55 are wired to the FPGA through 200 ohm series resistors and a level shifter,  
and the remaining two J55 pins are wired to 3.3V and GND. The J55 header is described in  
Figure 1-18 and Table 1-26.  
Note: This header is not installed on the SP605 as built.  
X-Ref Target Figure 1-18  
-
VCC1V5_FPGA  
VCC3V3  
U52  
HDR_1x6  
J55  
U1 FPGA Pin  
2
1
3
4
5
6
7
8
9
19  
20  
18  
17  
16  
15  
14  
13  
12  
11  
VCCA  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
VCCB  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
GPIO_HEADER_0  
GPIO_HEADER_1  
GPIO_HEADER_2  
GPIO_HEADER_3  
1
2
3
4
5
6
GPIO_HEADER_0_LS  
GPIO_HEADER_1_LS  
GPIO_HEADER_2_LS  
GPIO_HEADER_3_LS  
GPIO_HEADER_0  
GPIO_HEADER_1  
GPIO_HEADER_2  
GPIO_HEADER_3  
NC  
NC  
NC  
NC  
G7  
H6  
D1  
R7  
NC  
NC  
NC  
NC  
10  
OE  
GND  
TXB0108  
1
2
C384  
X5R  
10V  
0.1UF  
DNP  
VCC3V3  
UG526_18 _092409  
Figure 1-18: User SIP Header J55  
Table 1-26: User SIP Header Connections  
U1 FPGA Pin  
Schematic Net Name GPIO Header Pin  
G7  
H6  
D1  
R7  
–
GPIO_HEADER_0  
GPIO_HEADER_1  
GPIO_HEADER_2  
GPIO_HEADER_3  
GND  
J55.1  
J55.2  
J55.3  
J55.4  
J55.5  
J55.6  
–
VCC3V3  
Notes:  
1. Each GPIO_HEADER_n signal is sourced from the FPGA as  
<netname>_LS to a level shifter, then to the J55 header.  
2. Each GPIO_HEADER_n net has a 200 ohm series resistor between  
the level shifter and its respective header pin.  
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Detailed Description  
User SMA GPIO  
The SP605 includes an pair of SMA connectors for GPIO as described in Figure 1-19 and  
Table 1-27.  
X-Ref Target Figure 1-19  
-
32K10K-400E3  
GND1  
GND2  
GND3  
SIG GND4  
GND5  
2
3
4
5
6
7
8
1
GND6  
GND7  
J39  
USER_SMA_GPIO_N  
USER_SMA_GPIO_P  
32K10K-400E3  
2
3
4
5
6
7
8
GND1  
GND2  
GND3  
1
SIG GND4  
GND5  
GND6  
GND7  
J40  
UG526_19 _092409  
Figure 1-19: User SMA GPIO  
Table 1-27: User SMA Connections  
U1 FPGA Pin  
Schematic Net Name  
USER_SMA_GPIO_N  
USER_SMA_GPIO_P  
GPIO SMA Pin  
J39.1  
A3  
B3  
J40.1  
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Chapter 1: SP605 Evaluation Board  
17. Switches  
The SP605 Evaluation board includes the following switches:  
•
•
•
•
•
Power On/Off Slide Switch SW2  
FPGA_PROG_B Pushbutton SW3 (Active-Low)  
SYSACE_RESET_B Pushbutton SW9 (Active-Low)  
System ACE CF CompactFlash Image Select DIP Switch S1 (Active-High)  
Mode DIP Switch SW1 (Active-High)  
Power On/Off Slide Switch SW2  
SW2 is the SP605 board main power on/off switch. Sliding the switch actuator from the off  
to on position applies 12V power from either J18 (6-pin Mini-Fit) or J27 (4-pin ATX) power  
connector to the VCC12_P power plane. Green LED DS14 will illuminate when the SPL605  
board power is on. See “Power Management,” page 52 for details on the on-board power  
system.  
X-Ref Target Figure 1-20  
-
VCC12_P  
J18  
12v  
DPDT  
1
NC  
NC  
VCC12_P_IN  
1
2
5
3
4
2
5
3
12v  
1
2
4
R322  
1.00K  
1%  
NC  
NC  
+
C280  
330UF  
1
2
N/C  
N/C  
6
1/16W  
16V  
ELEC  
COM  
COM  
SW2  
1201M2S3ABE2  
6
39-30-1060  
CAUTION!  
PCIe  
DO NOT plug a PC ATX power supply 6-pin connector into  
the J18 connector on the SP605 board. The ATX 6-pin  
connector has a different pinout than J18 and will damage  
the SP605 board and void the board warranty.  
Power  
ATX Peripheral Cable Connector  
can plug into J27 when SP605 is  
in PC and the desk top AC adapter  
(brick) is not used.  
DO NOT plug an auxilliary PCIe 6-pin molex power  
connector into the J18 connector as this could damage the  
PCIe motherboard and/or the SP605 board. J18 is marked  
with a NO PCIE POWER label to warn users of the poten-  
tial hazard.  
J27  
1
12V  
2
COM  
3
DO NOT apply power to J18 and the 4-pin ATX disk drive  
connector J27 at the same time as this will damage the  
SP605 board.  
COM  
NC  
4
5V  
350211-1  
UG526_20 _100609  
Figure 1-20: Power On/Off Slide Switch SW2  
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Detailed Description  
FPGA_PROG_B Pushbutton SW3 (Active-Low)  
The SW3 switch (Figure 1-21) grounds the FPGA PROG_B pin when pressed. This action  
clears the FPGA. See the Spartan-6 FPGA data sheet for more information on clearing the  
contents of the FPGA.  
X-Ref Target Figure 1-21  
-
VCC2V5  
1
R17  
4.7K  
5%  
1/16W  
2
Pushbutton  
FPGA_PROG_B  
1
4
3
P1  
P4  
P3  
2
P2  
SW3  
UG526_21 _092409  
Figure 1-21: FPGA PROG_B Pushbutton SW3  
SYSACE_RESET_B Pushbutton SW9 (Active-Low)  
When the System ACE CF configuration mode pin is high (enabled by closing DIP switch  
S1 switch 4), the System ACE CF controller configures the FPGA from the CompactFlash  
card when a card is inserted or the SYSACE RESET button is pressed. See “5. System ACE  
CF and CompactFlash Connector,” page 20 for more details.  
X-Ref Target Figure 1-22  
-
Silkscreen:  
"SYSACE RESET"  
SYSACE_RESET_B  
20  
Pushbutton  
1
4
3
P1  
P4  
P3  
2
P2  
SW9  
UG526_22 _092409  
Figure 1-22: System ACE CF RESET_B Pushbutton SW9  
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System ACE CF CompactFlash Image Select DIP Switch S1 (Active-High)  
System ACE CF CompactFlash (CF) image select DIP switch S1, switches 1–3 (Figure 1-23)  
select which CF resident bitstream image is downloaded to the FPGA. S1 switches 1–3  
offer eight binary addresses. When ON (high), the S1 switch 4 enables the System ACE CF  
controller to configure the FPGA from the CompactFlash card when a card is inserted or  
the SYSACE RESET button is pressed. See “5. System ACE CF and CompactFlash  
Connector,” page 20 for more details.  
X-Ref Target Figure 1-23  
-
VCC2V5  
1
2
1
2
1
2
1
2
S1  
5
6
7
8
4
3
2
1
SYSACE_CFGMODEPIN  
SYSACE_CFGADDR2  
SYSACE_CFGADDR1  
SYSACE_CFGADDR0  
2
2
2
2
SDMX-4-X  
1
1
1
1
UG526_23 _102709  
Figure 1-23: System ACE CF CompactFlash Image Select DIP Switch S1  
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Detailed Description  
Mode DIP Switch SW1 (Active-High)  
DIP switch SW1 sets the FPGA mode as shown in Figure 1-24 and Table 1-30, page 55.  
X-Ref Target Figure 1-24  
-
VCC2V5  
2
1
2
1
1/16W  
5%  
1/16W  
5%  
200  
200  
R139  
R138  
FPGA_M0_CMP_MISO  
FPGA_M1  
1
2
4
3
SW1  
SDMX-2-X  
1
2
1
2
R8  
R9  
1.0K  
5%  
1.0K  
5%  
1/10W  
1/10W  
UG526_24 _092409  
Figure 1-24: FPGA Mode DIP Switch SW1  
References  
For more information, refer to the Spartan-6 FPGA Configuration User Guide [Ref 2]. See  
Table 1-30, page 55 for the configuration modes.  
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18. VITA 57.1 FMC LPC Connector  
The SP605 implements the Low Pin Count (LPC, J2) connector option of the VITA 57.1.1  
FMC specification.  
The FMC standard calls for two connector densities: a High Pin Count (HPC) and a Low  
Pin Count (LPC) implementation. A common 10 x 40 position (400 pin locations) connector  
form factor is used for both versions. The HPC version is fully populated with 400 pins  
present, and the LPC version is partially populated with 160 pins.  
The 10 x 40 rows of a FMC LPC connector provides connectivity for:  
•
•
•
•
•
68 single-ended or 34 differential user defined signals  
1 MGT  
1 MGT clock  
2 differential clocks  
61 ground, 10 power connections  
Of the above signal and clock connectivity capability, the SP605 implements the full set:  
•
34 differential user-defined pairs  
34 LA pairs  
♦
•
•
•
1 MGT  
1 MGT clock  
2 differential clocks  
Note: The SP605 board VADJ voltage for the FMC LPC connector J2 is fixed at 2.5V (non-  
adjustable). The 2.5V rail cannot be turned off. The SP605 VITA 57.1 FMC interfaces are compatible  
with 2.5V mezzanine cards capable of supporting 2.5V VADJ.  
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Detailed Description  
Table 1-28 shows the VITA 57.1 FMC LPC connections. The connector pinout is in  
Appendix B, “VITA 57.1 FMC LPC Connector Pinout.”  
Table 1-28: VITA 57.1 FMC LPC Connections  
J63 FMC  
LPC Pin  
U1 FPGA  
Pin  
J63 FMC  
LPC Pin  
U1 FPGA  
Pin  
Schematic Net Name  
Schematic Net Name  
D1  
D4  
FMC_PWR_GOOD_FLASH_RST_B  
FMC_GBTCLK0_M2C_P  
FMC_GBTCLK0_M2C_N  
FMC_LA01_CC_P  
FMC_LA01_CC_N  
FMC_LA05_P  
V13  
E12  
F12  
F14  
F15  
C4  
C2  
C3  
FMC_DP0_C2M_P  
FMC_DP0_C2M_N  
FMC_DP0_M2C_P  
FMC_DP0_M2C_N  
FMC_LA06_P  
B16  
A16  
D15  
C15  
D4  
D5  
C6  
D8  
C7  
D9  
C10  
C11  
C14  
C15  
C18  
C19  
C22  
C23  
C26  
C27  
C30  
C31  
D11  
D12  
D14  
D15  
D17  
D18  
D20  
D21  
D23  
D24  
D26  
D27  
FMC_LA06_N  
D5  
FMC_LA05_N  
A4  
FMC_LA10_P  
H10  
H11  
C17  
A17  
T12  
FMC_LA09_P  
F7  
FMC_LA10_N  
FMC_LA09_N  
F8  
FMC_LA14_P  
FMC_LA13_P  
G16  
F17  
Y11  
AB11  
U9  
FMC_LA14_N  
FMC_LA13_N  
FMC_LA18_CC_P  
FMC_LA18_CC_N  
FMC_LA27_P  
FMC_LA17_CC_P  
FMC_LA17_CC_N  
FMC_LA23_P  
U12  
AA10  
AB10  
T21  
FMC_LA27_N  
FMC_LA23_N  
V9  
IIC_SCL_MAIN  
IIC_SDA_MAIN  
FMC_LA26_P  
U14  
U13  
R22  
FMC_LA26_N  
G2  
G3  
FMC_CLK1_M2C_P  
FMC_CLK1_M2C_N  
FMC_LA00_CC_P  
FMC_LA00_CC_N  
FMC_LA03_P  
E16  
F16  
H10  
H11  
B18  
A18  
B20  
A20  
H13  
G13  
C5  
H2  
H4  
FMC_PRSNT_M2C_L  
FMC_CLK0_M2C_P  
FMC_CLK0_M2C_N  
FMC_LA02_P  
Y16  
H12  
G11  
G8  
G6  
H5  
G7  
H7  
G9  
H8  
FMC_LA02_N  
FMC_LA04_P  
F9  
G10  
G12  
G13  
G15  
G16  
G18  
G19  
FMC_LA03_N  
H10  
H11  
H13  
H14  
H16  
H17  
H19  
C19  
A19  
B2  
FMC_LA08_P  
FMC_LA04_N  
FMC_LA07_P  
FMC_LA08_N  
FMC_LA12_P  
FMC_LA07_N  
FMC_LA11_P  
A2  
FMC_LA12_N  
H14  
G15  
D18  
FMC_LA16_P  
FMC_LA11_N  
FMC_LA16_N  
A5  
FMC_LA15_P  
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Table 1-28: VITA 57.1 FMC LPC Connections (Cont’d)  
J63 FMC  
LPC Pin  
U1 FPGA  
Pin  
J63 FMC  
LPC Pin  
U1 FPGA  
Pin  
Schematic Net Name  
Schematic Net Name  
G21  
G22  
G24  
G25  
G27  
G28  
G30  
G31  
G33  
G34  
G36  
G37  
FMC_LA20_P  
FMC_LA20_N  
FMC_LA22_P  
FMC_LA22_N  
FMC_LA25_P  
FMC_LA25_N  
FMC_LA29_P  
FMC_LA29_N  
FMC_LA31_P  
FMC_LA31_N  
FMC_LA33_P  
FMC_LA33_N  
R9  
R8  
H20  
H22  
H23  
H25  
H26  
H28  
H29  
H31  
H32  
H34  
H35  
H37  
H38  
FMC_LA15_N  
FMC_LA19_P  
FMC_LA19_N  
FMC_LA21_P  
FMC_LA21_N  
FMC_LA24_P  
FMC_LA24_N  
FMC_LA28_P  
FMC_LA28_N  
FMC_LA30_P  
FMC_LA30_N  
FMC_LA32_P  
FMC_LA32_N  
D19  
R11  
V7  
T11  
W8  
V11  
W14  
Y14  
T15  
U15  
U16  
V15  
Y17  
AB17  
W11  
AA14  
AB14  
AA16  
AB16  
Y15  
AB15  
W17  
Y18  
Power Management  
AC Adapter and 12V Input Power Jack/Switch  
The SP605 is powered from a 12V source that is connected through a 6-pin (2X3) right  
angle Mini-Fit type connector J18. The AC-to-DC power supply included in the kit has a  
mating 6-pin plug.  
When the SP605 is installed into a table top or tower PC's PCIe slot, the SP605 is typically  
powered from the PC ATX power supply. One of the PCs ATX hard disk type 4-pin power  
connectors is plugged into SP605 connector J27. The SP605 can be powered with the AC  
power adapter (plugged into J18) even when plugged into a PC PCIe motherboard slot;  
however, users are cautioned not to also connect a PC ATX type 4-pin power connector to  
J27. See the caution notes below and in Figure 1-20, page 46.  
Caution! Caution! DO NOT plug a PC ATX power supply 6-pin connector into SP605  
connector J18.The ATX 6-pin connector has a different pinout than SP605 J18, and connecting  
the ATX 6-pin connector will damage the SP605 and void the board warranty.  
Caution! DO NOT apply power to 6-pin Mini-Fit type connector J18 and 4-pin ATX disk drive  
type connector J27 at the same time as this will damage the SP605 board. Refer to Figure 1-20,  
page 46 for details. The SP605 Power can be turned on or off through the board mounted slide  
switch SW2. When the switch is in the on position, a green LED (DS14) is illuminated.  
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Power Management  
Onboard Power Regulation  
Figure 1-25 shows the SP605 onboard power supply architecture. The SP605 uses Texas  
Instruments power controllers for primary core power control and monitoring.  
X-Ref Target Figure 1-25  
-
Power Supply  
12V  
PWR  
Jack  
J18 or J27  
Linear Regulator  
[email protected] max  
U5  
Op Amps  
TL1963AKTTR  
Linear Regulator  
3.0V@500mA max  
U49  
SPI x4 Memory  
LT1763CS8  
Power Controller 1  
U26  
UCD9240PFC  
Switching Module  
VCCINT 1.2V@10A max  
U18  
FPGA  
PTD08A010W  
Switching Module  
VCCAUX 2.5V@10A max  
PTD08A010W  
U20  
FPGA  
FPGA  
Switching Module  
U19  
VCC 2.5V@10A max  
PTD08A010W  
Linear Regulator  
1.8V@500mA max  
U44  
Linear FLash Memory  
TL1963A-18DCQR  
Power Controller 2  
UCD9240PFC  
Switching Module  
3.3V@10A max  
PTD08A010W  
U27  
U22  
System Power  
Switching Module  
1.5V@10A max  
PTD08A010W  
U21  
DDR3 Memory  
Linear Regulator  
MGT AVCC 1.2V@3A max  
TPS74401  
U51  
MGTs  
1.5V  
10K  
10K  
0.75Vref  
3.3V  
Sink/Source Regulator U11  
0.75 VTT/VREF@3A max  
TPS51200DRCT  
DDR3 Memory Terminations  
UG526_25_100509  
Figure 1-25: Onboard Power Regulators  
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Chapter 1: SP605 Evaluation Board  
Table 1-29: Onboard Power System Devices  
Reference  
Designator  
Power Rail Net Power Rail Schematic  
Device Type  
Description  
PMBus Controller - Core (Addr = 52)  
Name  
Voltage  
Page  
UCD9240PFC  
PTD08A010W  
PTD08A010W  
PTD08A010W  
U26  
21  
U18  
10A 0.6V - 3.6V Adj. Switching Regulator VCCINT_FPGA  
10A 0.6V - 3.6V Adj. Switching Regulator VCC2V5_FPGA  
1.20V  
2.50V  
2.50V  
22  
U19  
23  
U20  
10A 0.6V - 3.6V Adj. Switching Regulator  
VCCAUX  
24  
UCD9240PFC  
PTD08A010W  
PTD08A010W  
U27  
U21  
PMBus Controller - Core (Addr = 53)  
26  
29  
30  
10A 0.6V - 3.6V Adj. Switching Regulator VCC1V5_FPGA  
1.50V  
3.30V  
10A 0.6V - 3.6V Adj. Switching Regulator  
VCC3V3  
TL1963AKTTR  
TPS74401  
U5  
1.5A 12V IN, 5.0V OUT Linear Regulator  
3A 1.5V IN, 1.2V OUT Linear Regulator  
VCC5  
5.00V  
1.20V  
21  
27  
U51  
MGT_AVCC  
3A DDR3 VTERM Tracking Linear  
Regulator  
TPS512300DRCT  
U11  
VTTDDR  
0.75V  
31  
TPS512300DRCT  
TL1963-18DCQR  
U11  
U44  
10mA Tracking Reference output  
VTTVREF  
VCC1V8  
0.75V  
1.80V  
31  
31  
1.5A 2.5V IN, 1.8V OUT Linear Regulator  
500mA 5V IN, 3.0V OUT Linear  
Regulator  
LT1763CS8  
U49  
U10  
VCC3V0  
3.00V  
3.30V  
31  
17  
400mA 5V IN, 3.30V OUT Linear  
Regulator  
TPS73633DBVT  
DVI_VCCA  
Voltage and current monitoring and control are available for selected power rails through  
Texas Instruments' Fusion Digital Power™ graphical user interface (GUI). Both onboard TI  
power controllers are wired to the same PMBus. The PMBus connector, J1, is provided for  
use with the TI USB Interface Adapter PMBus pod and associated TI GUI.  
References  
Refer to the Texas Instruments website for more detailed information about power  
management controllers and regulator modules.  
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Configuration Options  
Configuration Options  
The FPGA on the SP605 Evaluation Board can be configured by the following methods:  
•
•
•
•
“3. SPI x4 Flash,” page 16  
“4. Linear BPI Flash,” page 18  
“5. System ACE CF and CompactFlash Connector,” page 20  
“6. USB JTAG,” page 22  
For more information, refer to the Spartan-6 FPGA Configuration User Guide. [Ref 2]  
Table 1-30: SP605 FPGA Configuration Modes  
Configuration  
Mode  
CCLK  
Direction  
M[1:0] Bus Width  
Configuration Solution  
User Guide Section  
3. SPI x4 Flash  
SPI X4 Memory U32 (J46 on), or  
External SPI Header J17 (J46 off)  
Master Serial/SPI  
01  
00  
xx  
1, 2, 4(1)  
8, 16  
1
Output  
Output  
Master  
Linear Flash Memory U25 (BPI)  
4. Linear BPI Flash  
6. USB JTAG  
SelectMAP/BPI(2)  
Input  
(TCK)  
Xilinx Platform Cable USB  
plugged into J4  
JTAG(3)  
System ACE CF Controller and  
CompactFlash Card  
5. System ACE CF and  
CompactFlash Connector  
Slave SelectMAP(2)  
10  
11  
8, 16  
1
Input  
Input  
Slave Serial(4)  
Not Supported  
–
Notes:  
1. Utilizing dual and quad SPI modes.  
2. Parallel configuration mode bus is auto-detected by the configuration logic.  
3. Spartan-6 devices also have a dedicated four-wire JTAG (IEEE Std 1149.1) port that is always available to the FPGA regardless of the  
mode pin settings.  
4. Default setting due to internal pull-up termination on Mode pins.  
With the mode switch SW1 set to 01, the SP605 will attempt to boot or load a bitstream  
from either the SPI X4 Flash device U32 or a user supplied SPI Flash memory mezzanine  
card installed on the SPI programming header J17, depending on the SPI select jumper J46  
configuration, as shown in Table 1-30. With the mode set to 00, the SP605 will attempt to  
boot or load a bitstream from Linear Flash device U25 (BPI).  
With the mode switch SW1 set to 10, if a CompactFlash (CF) card is installed in the CF  
socket U37, System ACE CF will attempt to load a bitstream from the CF card image  
address pointed to by the image select switch S1. With no CF card present, the SP605 can be  
configured via the onboard JTAG controller and USB download cable as described in “6.  
USB JTAG,” page 22.  
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Appendix A  
Default Jumper and Switch Settings  
Table A-1 shows the default switch settings and Table A-2, page 58 shows the default  
jumper settings for the SP605.  
Table A-1: Default Switch Settings  
REFDES  
Function/Type  
Default  
SW2  
Board power slide-switch  
off  
FPGA mode 2-pole DIP switch, Slave SelectMAP  
default selects System ACE CF configuration  
SW1  
2
1
M1 = 1  
M0 = 0  
on  
off  
System ACE CF configuration and image select  
4-pole DIP switch  
4
3
2
1
SysAce Mode = 1  
SysAce CFGAddr2 = 0  
SysAce CFGAddr1 = 0  
SysAce CFGAddr0 = 0  
on  
off  
off  
off  
S1  
User GPIO 4-pole DIP switch  
4
3
2
1
off  
off  
off  
off  
S2  
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Appendix A: Default Jumper and Switch Settings  
Table A-2: Default Jumper Settings  
Jumper  
REFDES  
Function  
Default  
FMC JTAG  
Bypass  
J19  
SFP Module  
J22  
exclude FMC LPC connector J2  
Jump 1-2  
SFP Full BW  
SFP Enabled  
Jump 1-2  
Jump 1-2  
J44  
SPI Memory  
Select  
J46  
SPI Select SPI X4 Memory U32  
Jump 1-2  
Jump 1-2  
System ACE  
CF Error LED  
J60  
System ACE CF Error LED DS18 Enabled  
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Appendix B  
VITA 57.1 FMC LPC Connector Pinout  
Figure B-1 shows the pinout of the FMC LPC connector. Pins marked NC are not  
connected.  
X-Ref Target Figure B-1  
-
K
J
H
G
F
E
D
C
B
A
1
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
VR EF_A_M2C  
PR SNT_M2C_L  
GND  
CLK0_M2C_P  
CLK0_M2C_N  
GND  
GND  
CLK1_M2C_P  
CLK1_M2C_N  
GND  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
PG_C2M  
GND  
GND  
DP0_C2M_P  
DP0_C2M_N  
GND  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
2
3
NC  
GND  
4
NC  
NC GBTCLK0_M2C_P  
NC GBTCLK0_M2C_N  
5
NC  
GND  
GND  
6
NC  
LA00_P_CC  
LA00_N_CC  
GND  
LA03_P  
LA03_N  
GND  
LA08_P  
LA08_N  
GND  
LA12_P  
LA12_N  
GND  
LA16_P  
LA16_N  
GND  
LA20_P  
LA20_N  
GND  
LA22_P  
LA22_N  
GND  
LA25_P  
LA25_N  
GND  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
GND  
GND  
LA01_P_CC  
LA01_N_CC  
GND  
LA05_P  
LA05_N  
GND  
LA09_P  
LA09_N  
GND  
LA13_P  
LA13_N  
GND  
LA17_P_CC  
LA17_N_CC  
GND  
LA23_P  
LA23_N  
GND  
DP0_M2C_P  
DP0_M2C_N  
GND  
7
NC  
LA02_P  
LA02_N  
GND  
LA04_P  
LA04_N  
GND  
LA07_P  
LA07_N  
GND  
LA11_P  
LA11_N  
GND  
LA15_P  
LA15_N  
GND  
LA19_P  
LA19_N  
GND  
LA21_P  
LA21_N  
GND  
LA24_P  
LA24_N  
GND  
8
NC  
9
NC  
GND  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
LA06_P  
LA06_N  
GND  
GND  
LA10_P  
LA10_N  
GND  
GND  
LA14_P  
LA14_N  
GND  
GND  
LA18_P_CC  
LA18_N_CC  
GND  
GND  
LA26_P  
LA26_N  
GND  
LA27_P  
LA27_N  
GND  
TCK  
GND  
LA29_P  
LA29_N  
GND  
LA31_P  
LA31_N  
GND  
LA33_P  
LA33_N  
GND  
TDI  
S CL  
LA28_P  
LA28_N  
GND  
LA30_P  
LA30_N  
GND  
TDO  
S DA  
3P3VAUX  
TMS  
GND  
GND  
TR ST_L  
GA1  
GA0  
12P0V  
GND  
3P3V  
LA32_P  
LA32_N  
GND  
GND  
12P0V  
GND  
3P3V  
GND  
3P3V  
VADJ  
GND  
GND  
VADJ  
3P3V  
UG526_26_092709  
Figure B-1: FMC LPC Connector Pinout  
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Appendix B: VITA 57.1 FMC LPC Connector Pinout  
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Appendix C  
SP605 Master UCF  
The UCF template is provided for designs that target the SP605. Net names provided in the  
constraints below correlate with net names on the SP605 rev. C schematic. On identifying  
the appropriate pins, the net names below should be replaced with net names in the user  
RTL. See the Constraints Guide for more information.  
NET "CLK_33MHZ_SYSACE"  
NET "CPU_RESET"  
##  
LOC = "N19";  
LOC = "H8";  
## 93 on U17  
## 2 on SW6 pushbutton (active-high)  
NET "DVI_D0"  
NET "DVI_D1"  
NET "DVI_D2"  
NET "DVI_D3"  
NET "DVI_D4"  
NET "DVI_D5"  
NET "DVI_D6"  
NET "DVI_D7"  
LOC = "K16";  
LOC = "U19";  
LOC = "T20";  
LOC = "N16";  
LOC = "P16";  
LOC = "M17";  
LOC = "M18";  
LOC = "R15";  
LOC = "R16";  
LOC = "P17";  
LOC = "P18";  
LOC = "R17";  
LOC = "J17";  
LOC = "D22";  
LOC = "J16";  
LOC = "L15";  
LOC = "B22";  
LOC = "C22";  
LOC = "C20";  
## 63 on U31 (thru series R39 47.5 ohm)  
## 62 on U31 (thru series R38 47.5 ohm)  
## 61 on U31 (thru series R37 47.5 ohm)  
## 60 on U31 (thru series R36 47.5 ohm)  
## 59 on U31 (thru series R35 47.5 ohm)  
## 58 on U31 (thru series R34 47.5 ohm)  
## 55 on U31 (thru series R33 47.5 ohm)  
## 54 on U31 (thru series R32 47.5 ohm)  
## 53 on U31 (thru series R31 47.5 ohm)  
## 52 on U31 (thru series R30 47.5 ohm)  
## 51 on U31 (thru series R29 47.5 ohm)  
## 50 on U31 (thru series R28 47.5 ohm)  
## 2 on U31 (thru series R40 47.5 ohm)  
## 18 on U31  
NET "DVI_D8"  
NET "DVI_D9"  
NET "DVI_D10"  
NET "DVI_D11"  
NET "DVI_DE"  
NET "DVI_GPIO1"  
NET "DVI_H"  
NET "DVI_RESET_B"  
NET "DVI_V"  
NET "DVI_XCLK_N"  
NET "DVI_XCLK_P"  
##  
## 4 on U31 (thru series R41 47.5 ohm)  
## 13 on U31  
## 5 on U31 (thru series R42 47.5 ohm)  
## 56 on U31  
## 57 on U31  
NET "FLASH_A0"  
NET "FLASH_A1"  
NET "FLASH_A2"  
NET "FLASH_A3"  
NET "FLASH_A4"  
NET "FLASH_A5"  
NET "FLASH_A6"  
NET "FLASH_A7"  
NET "FLASH_A8"  
NET "FLASH_A9"  
NET "FLASH_A10"  
NET "FLASH_A11"  
NET "FLASH_A12"  
NET "FLASH_A13"  
NET "FLASH_A14"  
NET "FLASH_A15"  
NET "FLASH_A16"  
NET "FLASH_A17"  
NET "FLASH_A18"  
NET "FLASH_A19"  
NET "FLASH_A20"  
NET "FLASH_A21"  
NET "FLASH_A22"  
NET "FLASH_A23"  
NET "FPGA_D0_DIN_MISO_MISO1"  
NET "FPGA_D1_MISO2"  
NET "FPGA_D2_MISO3"  
NET "FLASH_D3"  
NET "FLASH_D4"  
NET "FLASH_D5"  
NET "FLASH_D6"  
NET "FLASH_D7"  
NET "FLASH_D8"  
NET "FLASH_D9"  
NET "FLASH_D10"  
NET "FLASH_D11"  
NET "FLASH_D12"  
NET "FLASH_D13"  
NET "FLASH_D14"  
NET "FLASH_D15"  
NET "FLASH_WAIT"  
LOC = "N22";  
LOC = "N20";  
LOC = "M22";  
LOC = "M21";  
LOC = "L19";  
LOC = "K20";  
LOC = "H22";  
LOC = "H21";  
LOC = "L17";  
LOC = "K17";  
LOC = "G22";  
LOC = "G20";  
LOC = "K18";  
LOC = "K19";  
LOC = "H20";  
LOC = "J19";  
LOC = "E22";  
LOC = "E20";  
LOC = "F22";  
LOC = "F21";  
LOC = "H19";  
LOC = "H18";  
LOC = "F20";  
LOC = "G19";  
## 29 on U25  
## 25 on U25  
## 24 on U25  
## 23 on U25  
## 22 on U25  
## 21 on U25  
## 20 on U25  
## 19 on U25  
## 8 on U25  
## 7 on U25  
## 6 on U25  
## 5 on U25  
## 4 on U25  
## 3 on U25  
## 2 on U25  
## 1 on U25  
## 55 on U25  
## 18 on U25  
## 17 on U25  
## 16 on U25  
## 11 on U25  
## 10 on U25  
## 9 on U25  
## 26 on U25  
LOC = "AA20"; ## 34 on U25, 8 on U32 (thru series R132 100 ohm), 6 on J17  
LOC = "R13";  
LOC = "T14";  
LOC = "AA6";  
LOC = "AB6";  
LOC = "Y5";  
LOC = "AB5";  
LOC = "W9";  
LOC = "T7";  
LOC = "U6";  
LOC = "AB19"; ## 40 on U25  
LOC = "AA18"; ## 42 on U25  
LOC = "AB18"; ## 48 on U25  
LOC = "Y13";  
LOC = "AA12"; ## 52 on U25  
LOC = "AB12"; ## 54 on U25  
## 36 on U25, 3 on J17  
## 39 on U25, 2 on J17  
## 41 on U25  
## 47 on U25  
## 49 on U25  
## 51 on U25  
## 53 on U25  
## 35 on U25  
## 37 on U25  
## 50 on U25  
LOC = "T18";  
## 56 on U25  
SP605 Hardware User Guide  
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Appendix C: SP605 Master UCF  
NET "FLASH_WE_B"  
NET "FLASH_OE_B"  
NET "FLASH_CE_B"  
NET "FLASH_ADV_B"  
## NET "FMC_PWR_GOOD_FLASH_RST_B"  
##  
LOC = "R20";  
LOC = "P22";  
LOC = "P21";  
LOC = "T19";  
LOC = "V13";  
## 14 on U25  
## 32 on U25  
## 30 on U25  
## 46 on U25  
## 44 on U25 (this signal goes to multiple destinations, see below)  
NET "FMC_CLK0_M2C_N"  
NET "FMC_CLK0_M2C_P"  
NET "FMC_CLK1_M2C_N"  
NET "FMC_CLK1_M2C_P"  
NET "FMC_DP0_C2M_N"  
NET "FMC_DP0_C2M_P"  
NET "FMC_DP0_M2C_N"  
NET "FMC_DP0_M2C_P"  
NET "FMC_GBTCLK0_M2C_N"  
NET "FMC_GBTCLK0_M2C_P"  
## NET "IIC_SCL_MAIN"  
## NET "IIC_SDA_MAIN"  
NET "FMC_LA00_CC_N"  
NET "FMC_LA00_CC_P"  
NET "FMC_LA01_CC_N"  
NET "FMC_LA01_CC_P"  
NET "FMC_LA02_N"  
NET "FMC_LA02_P"  
NET "FMC_LA03_N"  
NET "FMC_LA03_P"  
NET "FMC_LA04_N"  
NET "FMC_LA04_P"  
NET "FMC_LA05_N"  
NET "FMC_LA05_P"  
NET "FMC_LA06_N"  
NET "FMC_LA06_P"  
NET "FMC_LA07_N"  
NET "FMC_LA07_P"  
NET "FMC_LA08_N"  
NET "FMC_LA08_P"  
NET "FMC_LA09_N"  
NET "FMC_LA09_P"  
NET "FMC_LA10_N"  
NET "FMC_LA10_P"  
NET "FMC_LA11_N"  
NET "FMC_LA11_P"  
NET "FMC_LA12_N"  
NET "FMC_LA12_P"  
NET "FMC_LA13_N"  
NET "FMC_LA13_P"  
NET "FMC_LA14_N"  
NET "FMC_LA14_P"  
NET "FMC_LA15_N"  
NET "FMC_LA15_P"  
NET "FMC_LA16_N"  
NET "FMC_LA16_P"  
NET "FMC_LA17_CC_N"  
NET "FMC_LA17_CC_P"  
NET "FMC_LA18_CC_N"  
NET "FMC_LA18_CC_P"  
NET "FMC_LA19_N"  
NET "FMC_LA19_P"  
NET "FMC_LA20_N"  
NET "FMC_LA20_P"  
NET "FMC_LA21_N"  
NET "FMC_LA21_P"  
NET "FMC_LA22_N"  
NET "FMC_LA22_P"  
NET "FMC_LA23_N"  
NET "FMC_LA23_P"  
NET "FMC_LA24_N"  
NET "FMC_LA24_P"  
NET "FMC_LA25_N"  
NET "FMC_LA25_P"  
NET "FMC_LA26_N"  
NET "FMC_LA26_P"  
NET "FMC_LA27_N"  
NET "FMC_LA27_P"  
NET "FMC_LA28_N"  
NET "FMC_LA28_P"  
NET "FMC_LA29_N"  
NET "FMC_LA29_P"  
NET "FMC_LA30_N"  
NET "FMC_LA30_P"  
NET "FMC_LA31_N"  
NET "FMC_LA31_P"  
NET "FMC_LA32_N"  
NET "FMC_LA32_P"  
NET "FMC_LA33_N"  
NET "FMC_LA33_P"  
NET "FMC_PRSNT_M2C_L"  
NET "FMC_PWR_GOOD_FLASH_RST_B"  
##  
LOC = "G11";  
LOC = "H12";  
LOC = "F16";  
LOC = "E16";  
LOC = "A16";  
LOC = "B16";  
LOC = "C15";  
LOC = "D15";  
LOC = "F12";  
LOC = "E12";  
LOC = "T21";  
LOC = "R22";  
LOC = "F10";  
LOC = "G9";  
LOC = "F15";  
LOC = "F14";  
LOC = "F9";  
LOC = "G8";  
LOC = "A18";  
LOC = "B18";  
LOC = "A19";  
LOC = "C19";  
LOC = "A4";  
LOC = "C4";  
LOC = "D5";  
LOC = "D4";  
LOC = "A2";  
LOC = "B2";  
LOC = "A20";  
LOC = "B20";  
LOC = "F8";  
LOC = "F7";  
LOC = "H11";  
LOC = "H10";  
LOC = "G15";  
LOC = "H14";  
LOC = "G13";  
LOC = "H13";  
LOC = "F17";  
LOC = "G16";  
LOC = "A17";  
LOC = "C17";  
LOC = "D19";  
LOC = "D18";  
LOC = "A5";  
LOC = "C5";  
## H5 on J2  
## H4 on J2  
## G3 on J2  
## G2 on J2  
## C3 on J2  
## C2 on J2  
## C7 on J2  
## C6 on J2  
## D5 on J2  
## D4 on J2  
## C30 on J2 (this signal goes to multiple destinations, see below)  
## C31 on J2 (this signal goes to multiple destinations, see below)  
## G7 on J2  
## G6 on J2  
## D9 on J2  
## D8 on J2  
## H8 on J2  
## H7 on J2  
## G10 on J2  
## G9 on J2  
## H11 on J2  
## H10 on J2  
## D12 on J2  
## D11 on J2  
## C11 on J2  
## C10 on J2  
## H14 on J2  
## H13 on J2  
## G13 on J2  
## G12 on J2  
## D15 on J2  
## D14 on J2  
## C15 on J2  
## C14 on J2  
## H17 on J2  
## H16 on J2  
## G16 on J2  
## G15 on J2  
## D18 on J2  
## D17 on J2  
## C19 on J2  
## C18 on J2  
## H20 on J2  
## H19 on J2  
## G19 on J2  
## G18 on J2  
LOC = "AB11"; ## D21 on J2  
LOC = "Y11";  
LOC = "U12";  
LOC = "T12";  
LOC = "T11";  
LOC = "R11";  
LOC = "R8";  
LOC = "R9";  
LOC = "W11";  
LOC = "V11";  
LOC = "W8";  
LOC = "V7";  
LOC = "V9";  
LOC = "U9";  
LOC = "AB14"; ## H29 on J2  
LOC = "AA14"; ## H28 on J2  
LOC = "Y14";  
LOC = "W14";  
LOC = "U13";  
LOC = "U14";  
## D20 on J2  
## C23 on J2  
## C22 on J2  
## H23 on J2  
## H22 on J2  
## G22 on J2  
## G21 on J2  
## H26 on J2  
## H25 on J2  
## G25 on J2  
## G24 on J2  
## D24 on J2  
## D23 on J2  
## G28 on J2  
## G27 on J2  
## D27 on J2  
## D26 on J2  
LOC = "AB10"; ## C27 on J2  
LOC = "AA10"; ## C26 on J2  
LOC = "AB16"; ## H32 on J2  
LOC = "AA16"; ## H31 on J2  
LOC = "U15";  
LOC = "T15";  
## G31 on J2  
## G30 on J2  
LOC = "AB15"; ## H35 on J2  
LOC = "Y15";  
LOC = "V15";  
LOC = "U16";  
LOC = "Y18";  
LOC = "W17";  
LOC = "AB17"; ## G37 on J2  
LOC = "Y17";  
LOC = "Y16";  
## H34 on J2  
## G34 on J2  
## G33 on J2  
## H38 on J2  
## H37 on J2  
## G36 on J2  
## H2 on J2  
LOC = "V13"; ## D1 on J2, 1 of Q2 (LED DS1 driver), U1 AB2 FPGA_PROG (thru series R260 DNP), 44 of U25  
NET "FPGA_AWAKE"  
NET "FPGA_CCLK"  
NET "FPGA_CMP_CLK"  
LOC = "V19";  
LOC = "Y20";  
LOC = "V17";  
## 2  
## 7  
## 3  
on DS7 LED  
on J17  
on J3  
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NET "FPGA_CMP_CS_B"  
NET "FPGA_CMP_MOSI"  
LOC = "V18";  
LOC = "W18";  
## 4  
## 2  
on J3  
on J3  
## NET "FPGA_D0_DIN_MISO_MISO1"  
## NET "FPGA_D1_MISO2"  
## NET "FPGA_D2_MISO3"  
LOC = "AA20"; ## this pin is part of the FLASH_nn group  
LOC = "R13";  
LOC = "T14";  
## this pin is part of the FLASH_nn group  
## this pin is part of the FLASH_nn group  
NET "FPGA_DONE"  
NET "FPGA_HSWAPEN"  
NET "FPGA_INIT_B"  
NET "FPGA_M0_CMP_MISO"  
NET "FPGA_M1"  
LOC = "AB21"; ## 2  
on DS2 LED  
on R125 100 ohm to GND  
on DS17 (thru sereis R69 75 ohm), 78 on U17  
on SW1 DIP switch (active-high), 1 on J3  
on SW1 DIP switch (active-high)  
LOC = "C3";  
LOC = "Y4";  
## 1  
## 1  
LOC = "AA21"; ## 1  
LOC = "Y19"; ## 2  
NET "FPGA_MOSI_CSI_B_MISO0"  
NET "FPGA_ONCHIP_TERM1"  
NET "FPGA_ONCHIP_TERM2"  
NET "FPGA_PROG_B"  
NET "FMC_PWR_GOOD_FLASH_RST_B"  
NET "FPGA_SUSPEND"  
NET "FPGA_TCK"  
NET "FPGA_TDI"  
NET "FPGA_TMS"  
NET "FPGA_VBATT"  
NET "FPGA_VTEMP"  
##  
LOC = "AB20"; ## 15 on U32, 5 on J17  
LOC = "M7";  
LOC = "K7";  
LOC = "AB2";  
## 1  
## 1  
## 1  
on R124 DNP to GND  
on R126 100 ohm to GND  
on SW3 pushbutton (active-high) 1 on J17, 2 on J48, 2 on R260 DNP connected to  
LOC = "AA22"; ## 2  
on J47  
LOC = "A21";  
LOC = "E18";  
LOC = "D20";  
LOC = "T16";  
LOC = "Y3";  
## 80 on U17  
## 82 on U17  
## 85 on U17  
## 1  
## 2  
on B2 (battery), 2 on D11 (charging circuit)  
on R207 150 ohm to VCC1V5  
NET "GPIO_BUTTON0"  
NET "GPIO_BUTTON1"  
NET "GPIO_BUTTON2"  
NET "GPIO_BUTTON3"  
##  
LOC = "F3";  
LOC = "G6";  
LOC = "F5";  
LOC = "C1";  
## 2  
## 2  
## 2  
## 2  
on SW4 pushbutton (active-high)  
on SW7 pushbutton (active-high)  
on SW5 pushbutton (active-high)  
on SW8 pushbutton (active-high)  
NET "GPIO_HEADER_0_LS"  
NET "GPIO_HEADER_1_LS"  
NET "GPIO_HEADER_2_LS"  
NET "GPIO_HEADER_3_LS"  
##  
LOC = "G7";  
LOC = "H6";  
LOC = "D1";  
LOC = "R7";  
## 1 on U52 (level shifter, U52.20 <-> GPIO_HEADER_0 <-> series R280 200 ohm <-> 1 on J55  
## 3 on U52 (level shifter, U52.18 <-> GPIO_HEADER_0 <-> series R281 200 ohm <-> 2 on J55  
## 4 on U52 (level shifter, U52.17 <-> GPIO_HEADER_0 <-> series R282 200 ohm <-> 3 on J55  
## 5 on U52 (level shifter, U52.16 <-> GPIO_HEADER_0 <-> series R283 200 ohm <-> 4 on J55  
NET "GPIO_LED_0"  
NET "GPIO_LED_1"  
NET "GPIO_LED_2"  
NET "GPIO_LED_3"  
##  
LOC = "D17";  
LOC = "AB4";  
LOC = "D21";  
LOC = "W15";  
## 2  
## 2  
## 2  
## 2  
on DS3 LED  
on DS4 LED  
on DS5 LED  
on DS6 LED  
NET "GPIO_SWITCH_0"  
NET "GPIO_SWITCH_1"  
NET "GPIO_SWITCH_2"  
NET "GPIO_SWITCH_3"  
##  
LOC = "C18";  
LOC = "Y6";  
LOC = "W6";  
LOC = "E4";  
## 1  
## 2  
## 3  
## 4  
on S2 DIP switch (active-high)  
on S2 DIP switch (active-high)  
on S2 DIP switch (active-high)  
on S2 DIP switch (active-high)  
NET "IIC_SCL_DVI"  
220 ohm <-> 6 on P3  
NET "IIC_SDA_DVI"  
220 ohm <-> 7 on P3  
NET "IIC_SCL_MAIN"  
NET "IIC_SDA_MAIN"  
NET "IIC_SCL_SFP"  
NET "IIC_SDA_SFP"  
##  
LOC = "W13";  
LOC = "AA4";  
## 15 on U31, 2 on Q7 (level shifter, Q7.3 <-> IIC_CLK_DVI_F <-> series ferrite F9  
## 14 on U31, 2 on Q8 (level shifter, Q7.3 <-> IIC_SDA_DVI_F <-> series ferrite F8  
LOC = "T21";  
LOC = "R22";  
LOC = "E5";  
LOC = "E6";  
## C30 on J2  
## C31 on J2  
## 5  
## 4  
on P2  
on P2  
NET "MEM1_A0"  
NET "MEM1_A1"  
NET "MEM1_A2"  
NET "MEM1_A3"  
NET "MEM1_A4"  
NET "MEM1_A5"  
NET "MEM1_A6"  
NET "MEM1_A7"  
LOC = "K2";  
LOC = "K1";  
LOC = "K5";  
LOC = "M6";  
LOC = "H3";  
LOC = "M3";  
LOC = "L4";  
LOC = "K6";  
LOC = "G3";  
LOC = "G1";  
LOC = "J4";  
LOC = "E1";  
LOC = "F1";  
LOC = "J6";  
LOC = "H5";  
LOC = "J3";  
LOC = "J1";  
LOC = "H1";  
LOC = "M4";  
LOC = "F2";  
LOC = "K3";  
LOC = "K4";  
LOC = "R3";  
LOC = "R1";  
LOC = "P2";  
LOC = "P1";  
LOC = "L3";  
LOC = "L1";  
LOC = "M2";  
LOC = "M1";  
LOC = "T2";  
LOC = "T1";  
LOC = "U3";  
LOC = "U1";  
LOC = "W3";  
LOC = "W1";  
LOC = "Y2";  
LOC = "Y1";  
LOC = "N4";  
## N3 on U42  
## P7 on U42  
## P3 on U42  
## N2 on U42  
## P8 on U42  
## P2 on U42  
## R8 on U42  
## R2 on U42  
## T8 on U42  
## R3 on U42  
## L7 on U42  
## R7 on U42  
## N7 on U42  
## T3 on U42  
## T7 on U42  
## M2 on U42  
## N8 on U42  
## M3 on U42  
## K3 on U42  
## K9 on U42  
## K7 on U42  
## J7 on U42  
## G2 on U42  
## H3 on U42  
## E3 on U42  
## F2 on U42  
## H7 on U42  
## H8 on U42  
## F7 on U42  
## F8 on U42  
## C2 on U42  
## C3 on U42  
## A2 on U42  
## D7 on U42  
## A3 on U42  
## C8 on U42  
## B8 on U42  
## A7 on U42  
## E7 on U42  
NET "MEM1_A8"  
NET "MEM1_A9"  
NET "MEM1_A10"  
NET "MEM1_A11"  
NET "MEM1_A12"  
NET "MEM1_A13"  
NET "MEM1_A14"  
NET "MEM1_BA0"  
NET "MEM1_BA1"  
NET "MEM1_BA2"  
NET "MEM1_CAS_B"  
NET "MEM1_CKE"  
NET "MEM1_CLK_N"  
NET "MEM1_CLK_P"  
NET "MEM1_DQ0"  
NET "MEM1_DQ1"  
NET "MEM1_DQ2"  
NET "MEM1_DQ3"  
NET "MEM1_DQ4"  
NET "MEM1_DQ5"  
NET "MEM1_DQ6"  
NET "MEM1_DQ7"  
NET "MEM1_DQ8"  
NET "MEM1_DQ9"  
NET "MEM1_DQ10"  
NET "MEM1_DQ11"  
NET "MEM1_DQ12"  
NET "MEM1_DQ13"  
NET "MEM1_DQ14"  
NET "MEM1_DQ15"  
NET "MEM1_LDM"  
SP605 Hardware User Guide  
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Appendix C: SP605 Master UCF  
NET "MEM1_LDQS_N"  
NET "MEM1_LDQS_P"  
NET "MEM1_ODT"  
NET "MEM1_RAS_B"  
NET "MEM1_RESET_B"  
NET "MEM1_UDM"  
NET "MEM1_UDQS_N"  
NET "MEM1_UDQS_P"  
NET "MEM1_WE_B"  
##  
LOC = "N1";  
LOC = "N3";  
LOC = "L6";  
LOC = "M5";  
LOC = "E3";  
LOC = "P3";  
LOC = "V1";  
LOC = "V2";  
LOC = "H2";  
## G3 on U42  
## F3 on U42  
## K1 on U42  
## J3 on U42  
## T2 on U42  
## D3 on U42  
## B7 on U42  
## C7 on U42  
## L3 on U42  
NET "PCIE_250M_N"  
NET "PCIE_250M_P"  
LOC = "B10";  
LOC = "A10";  
## 1  
## 1  
on series C301 0.1uF, C300 pin 2 -> PCIE_250M_MGT1_C_N -> 17 on U48  
on series C300 0.1uF, C300 pin 2 -> PCIE_250M_MGT1_C_P -> 18 on U48  
NET "PCIE_PERST_B_LS"  
NET "PCIE_RX0_N"  
NET "PCIE_RX0_P"  
NET "PCIE_TX0_N"  
NET "PCIE_TX0_P"  
##  
LOC = "J7";  
LOC = "C7";  
LOC = "D7";  
LOC = "A6";  
LOC = "B6";  
## 6  
## B15 on P4  
## B14 on P4  
## 2  
## 2  
on U52 (level shifter, U52.20 <-> PCIE_PERST_B <-> series R55 15 ohm <-> A11 on P4  
on series C26 0.1uF, C26 pin 1 -> PCIE_TX0_C_N -> A17 of P4  
on series C27 0.1uF, C26 pin 1 -> PCIE_TX0_C_P -> A16 of P4  
NET "PHY_COL"  
NET "PHY_CRS"  
NET "PHY_INT"  
NET "PHY_MDC"  
LOC = "M16";  
LOC = "N15";  
LOC = "J20";  
LOC = "R19";  
LOC = "V20";  
LOC = "J22";  
LOC = "P20";  
LOC = "T22";  
LOC = "P19";  
LOC = "Y22";  
LOC = "Y21";  
LOC = "W22";  
LOC = "W20";  
LOC = "V22";  
LOC = "V21";  
LOC = "U22";  
LOC = "U20";  
LOC = "L20";  
LOC = "T8";  
LOC = "AB7";  
LOC = "U10";  
LOC = "T10";  
LOC = "AB8";  
LOC = "AA8";  
LOC = "AB9";  
LOC = "Y9";  
LOC = "Y12";  
LOC = "W12";  
LOC = "U8";  
## 114 on U46  
## 115 on U46  
## 32 on U46  
## 35 on U46  
## 33 on U46  
## 36 on U46  
NET "PHY_MDIO"  
NET "PHY_RESET"  
NET "PHY_RXCLK"  
NET "PHY_RXCTL_RXDV"  
NET "PHY_RXD0"  
NET "PHY_RXD1"  
NET "PHY_RXD2"  
NET "PHY_RXD3"  
NET "PHY_RXD4"  
NET "PHY_RXD5"  
NET "PHY_RXD6"  
NET "PHY_RXD7"  
NET "PHY_RXER"  
NET "PHY_TXCLK"  
NET "PHY_TXCTL_TXEN"  
NET "PHY_TXC_GTXCLK"  
NET "PHY_TXD0"  
NET "PHY_TXD1"  
NET "PHY_TXD2"  
NET "PHY_TXD3"  
NET "PHY_TXD4"  
NET "PHY_TXD5"  
NET "PHY_TXD6"  
NET "PHY_TXD7"  
NET "PHY_TXER"  
##  
## 7  
## 4  
## 3  
on U46  
on U46  
on U46  
## 128 on U46  
## 126 on U46  
## 125 on U46  
## 124 on U46  
## 123 on U46  
## 121 on U46  
## 120 on U46  
## 8  
on U46  
## 10 on U46  
## 16 on U46  
## 14 on U46  
## 18 on U46  
## 19 on U46  
## 20 on U46  
## 24 on U46  
## 25 on U46  
## 26 on U46  
## 28 on U46  
## 29 on U46  
## 13 on U46  
NET "PMBUS_ALERT"  
NET "PMBUS_CLK"  
NET "PMBUS_CTRL"  
NET "PMBUS_DATA"  
##  
LOC = "D3";  
LOC = "W10";  
LOC = "H16";  
LOC = "Y10";  
## 35 on U26, 35 on U27  
## 19 on U26, 19 on U27  
## 36 on U26, 36 on U27  
## 20 on U26, 20 on U27  
NET "SFPCLK_QO_N"  
NET "SFPCLK_QO_P"  
NET "SFP_LOS"  
NET "SFP_RX_N"  
NET "SFP_RX_P"  
NET "SFP_TX_DISABLE_FPGA"  
NET "SFP_TX_N"  
NET "SFP_TX_P"  
##  
LOC = "B12";  
LOC = "A12";  
LOC = "T17";  
LOC = "C13";  
LOC = "D13";  
LOC = "Y8";  
LOC = "A14";  
LOC = "B14";  
## 2  
## 2  
## 8  
## 12 on P2  
## 13 on P2  
## 3  
## 19 on P2  
## 18 on P2  
on series C298 0.1uF, C298 pin 1 <- SFPCLK_QO_C_N <- 6 of U47  
on series C299 0.1uF, C299 pin 1 <- SFPCLK_QO_C_P <- 7 of U47  
on P2, 1 on J14  
on P2, 1 on J44  
NET "SMA_REFCLK_N"  
NET "SMA_REFCLK_P"  
NET "SMA_RX_N"  
NET "SMA_RX_P"  
NET "SMA_TX_N"  
NET "SMA_TX_P"  
##  
LOC = "D11";  
LOC = "C11";  
LOC = "C9";  
LOC = "D9";  
LOC = "A8";  
LOC = "B8";  
##  
##  
##  
##  
##  
##  
NET "SPI_CS_B"  
##  
LOC = "AA3";  
##  
NET "SYSACE_CFGTDI"  
NET "SYSACE_D0_LS"  
NET "SYSACE_D1_LS"  
NET "SYSACE_D2_LS"  
NET "SYSACE_D3_LS"  
NET "SYSACE_D4_LS"  
NET "SYSACE_D5_LS"  
NET "SYSACE_D6_LS"  
NET "SYSACE_D7_LS"  
NET "SYSACE_MPA00_LS"  
NET "SYSACE_MPA01_LS"  
NET "SYSACE_MPA02_LS"  
NET "SYSACE_MPA03_LS"  
NET "SYSACE_MPA04_LS"  
NET "SYSACE_MPA05_LS"  
NET "SYSACE_MPA06_LS"  
NET "SYSACE_MPBRDY_LS"  
NET "SYSACE_MPCE_LS"  
NET "SYSACE_MPIRQ_LS"  
NET "SYSACE_MPOE_LS"  
NET "SYSACE_MPWE_LS"  
LOC = "G17";  
LOC = "N6";  
LOC = "N7";  
LOC = "U4";  
LOC = "T4";  
LOC = "P6";  
LOC = "P7";  
LOC = "T3";  
LOC = "R4";  
LOC = "V5";  
LOC = "V3";  
LOC = "P5";  
LOC = "P4";  
LOC = "H4";  
LOC = "G4";  
LOC = "D2";  
LOC = "AA1";  
LOC = "W4";  
LOC = "AA2";  
LOC = "T6";  
LOC = "T5";  
##  
##  
##  
##  
##  
##  
##  
##  
##  
##  
##  
##  
##  
##  
##  
##  
##  
##  
##  
##  
##  
64  
www.xilinx.com  
SP605 Hardware User Guide  
UG526 (v1.1.1) February 1, 2010  
Download from Www.Somanuals.com. All Manuals Search And Download.  
##  
NET "SYSCLK_N"  
NET "SYSCLK_P"  
##  
LOC = "K22";  
LOC = "K21";  
##  
##  
NET "USB_1_CTS"  
NET "USB_1_RTS"  
NET "USB_1_RX"  
NET "USB_1_TX"  
##  
LOC = "F18";  
LOC = "F19";  
LOC = "B21";  
LOC = "H17";  
##  
##  
##  
##  
NET "USER_CLOCK"  
NET "USER_SMA_CLOCK_N"  
NET "USER_SMA_CLOCK_P"  
NET "USER_SMA_GPIO_N"  
NET "USER_SMA_GPIO_P"  
LOC = "AB13"; ##  
LOC = "M19";  
LOC = "M20";  
LOC = "A3";  
LOC = "B3";  
##  
##  
##  
##  
Note:  
1. Pullup and pulldown resistors which branch from nets are not included  
2. Pullup and pulldown resistors to a single point power or GND are included  
3. Series resistors are included  
4. DNP = do not populate, no component will be installed on the PCB at this location  
SP605 Hardware User Guide  
www.xilinx.com  
65  
UG526 (v1.1.1) February 1, 2010  
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Appendix C: SP605 Master UCF  
66  
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Appendix D  
References  
This appendix provides references to documentation supporting Spartan-6 FPGAs, tools,  
and IP.  
For additional information, see www.xilinx.com/support/documentation/index.htm.  
Xilinx documents supporting the SP605 Evaluation Board:  
1. DS162, Spartan-6 FPGA Data Sheet: DC and Switching Characteristics  
2. UG380, Spartan-6 FPGA Configuration User Guide  
3. UG388, Spartan-6 FPGA Memory Controller User Guide  
4. DS570, XPS Serial Peripheral Interface (SPI) Data Sheet  
5. DS080, System ACE CompactFlash Solution Data Sheet  
6. UG386, Spartan-6 FPGA GTP Transceivers User Guide  
7. UG138, LogiCORE™ IP Tri-Mode Ethernet MAC v4.2 User Guide  
8. DS606, XPS IIC Bus Interface Data Sheet  
9. UG381, Spartan-6 FPGA SelectIO Resources User Guide  
10. DS614, Clock Generator (v3.01a) Data Sheet  
11. DS643, Multi-Port Memory Controller (MPMC) (v5.02a) Data Sheet  
Additional documentation:  
12. Micron Technology, Inc., DDR3 SDRAM Specification (MT41J64M16LA-187E)  
13. Winbond, Serial Flash Memory Data Sheet (W25Q64VSFIG)  
14. Numonyx, StrataFlash Embedded Memory Data Sheet (JS28F256P30)  
15. Epson Toyocom, Oscillator Data Sheet (EG-2121CA-200.0000M-LHPA)  
16. PCI SIG, PCI Express Specifications  
17. Marvell, Alaska Gigabit Ethernet Transceivers Product Page  
18. ST Micro, M24C08 Data Sheet  
SP605 Hardware User Guide  
UG526 (v1.1.1) February 1, 2010  
www.xilinx.com  
67  
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