Toshiba Projection Television TLP510E User Manual

FILE NO. 336-9707

TECHNICAL TRAINING MANUAL

3 LCD DATA PROJECTOR

TLP511U

TLP510U

TLP511E

TLP510E

PRINTED IN JAPAN, Nov., 1997

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1-3. Voltage Switching

1. MAIN POWER SUPPLY CIRCUIT

When the voltage switching terminal of connector C

opens, pin 1 develops low, since the pin 2 of IC401 is 6V,

higher than pin 2 (3V), the voltage adjusted to 16.3V is

directly developed from IC201, since the status of Q205

turns off. When the voltage switching terminal develops

ground potential, since pin 2 of IC401 develops 0V and

the voltage of pin 2 develops low, pin 1 develops high,

Q205 turns on, voltage-set-up resistor of R201 is short-

circuited and the voltage of IC201 rises from 16.3V to

18.0V.

1-1. Description

This power supply boosts up at boost-up-converter just

after bridge-rectifying AC input voltage, supplies the

voltage smoothed to DC 350V to the lamp output. Then

current resonance DC-DC converter which uses the DC

350V as an input converts the voltage and supplies S6V,

+6V, +10V, +13V, +15.5V and –12V.

The boost-up-converter control IC, IC301, stabilizes AC

rectified voltage to DC 350V. The current resonance DC-

DC converter, IC303, turns FET Q102 and Q103 “ON/

OFF” alternately using the drive transformer T103 and

converts the voltage to secondary side through the

converter transformer T101. At this time, the voltage of

S6V at the secondary side is detected by IC402, the

negative feedback to IC303 is carried out at photo

coupler PH301 and then the voltage is stabilized. Other

outputs are determined by the turn ratio of secondary

side of T101, and the voltage rectified, smoothed, but not

stabilized are stabilized through the series regulator.

(+10V is stabilized at IC203, +13V at IC202, +15.5V at

IC201.)

1-4. Over-voltage Protection

When the negative feedback circuit of current resonance

DC-DC converter is shut down, the secondary side

voltage control is unable to operate, the voltage begins to

develop high without any restriction. At this time, when

the voltage of S6V and +6V exceeds 8.5V, the base of

transistor Q401 is biased through the zener diode D201,

and turns on, and then the voltage higher than 7V is

added to pin 6 (OVP) of IC303 through the photo coupler

PH302. When the voltage higher than 7V is added to pin

6, IC303 is latched, all outputs are shut down. ( Boost-

up-converter stops simultaneously, too.)

The voltage rectified and smoothed by D105 and C113 at

primary winding of T101 is supplied as a V voltage of

When the voltage is added to +10V, +13V, +15.5V lines

from external side, (exceeding +15V for +10V line, 13V

for +13 line and 20V for +15.5V line), on each line

respectively through the zener diodes D202, D203 and

D204, the base voltage of Q401 is biased passing, IC303

is latched in the same way as the above-mentioned, all

outputs are shut down. When releasing the latch opera-

tion, stop to supply the commercial power supply and

then re-supply the commercial power after more than

approx. 120 seconds.

IC301, IC302 and IC303 on primary side ICs, and also

the voltage rectified and smoothed by D106 and C114 is

supplied as a gate bias voltage of D306 TRIAC (triode

AC switch) which short-circuits the inrush current

limiting resistor R305. Therefore, when the electric

current resonance DC-DC converter stops to oscillate, the

voltage is not supplied so that the boost-up-

converter stops to operate.

1-2. Output Control

When the output control 1 and 2 of connector A develops

low, the voltage of approx. 14V is added to Q203 gate

and pins 4 of IC203, IC201, and IC202 through R205

and R206 respectively, since the transistors Q201 and

Q202 turn off. In this case, Q204, IC201, IC202 and

IC203 turn off, the voltages of +6V, +10V, +15.5V and

+13V are not developed.

When the output control 1 and 2 develop high, the

transistors Q201 and Q202 turn on, so no voltage is

added to the gate Q203, IC201, IC202 and IC203,

described above, and the voltage of +6V, +10V, –15.5V

and +13V are developed.

1-1

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1-5. Over-current Protection

The over-current protection for lamp output detects the

voltage drop of the current detection resistor R113 at

between pins 9 and 10 of IC302. When voltage switching

terminal of connector C opens (at 16.3V), the photo

coupler PH303 turns off since pin 1 of IC401 develops

low and the voltage of drop voltage at R113 is directly

compared at pin 10 of IC302. When the lamp output

current is from 0.7 to 0.9A, pin 8 develops high and the

voltage higher than 7V is added to pin 6 of IC303. Then

IC303 is latched and all outputs are shut down.

In S6V and +6V lines, the voltage drop owing to the

current flowing in L203 is detected by pins 5 and 6 of

IC401, when the total current amount exceeds 8A, pin 7

develops high and the voltage biasses the base voltage of

transistor Q401 passing through the zener diode D402

and diode D401. In the same way as described in the

item of the over-voltage protection, IC303 is latched and

all outputs are shutdown. The method to release the latch

operation is the same as the item of the over-voltage

protection.

When the voltage switching terminal of connector C

develops the ground potential (at 18.0V), pin 1 of IC401

develops high, PH303 turns on and the voltage of drop

voltage at R113 and the voltage divided by R317 and

R327 are compared at pin 10 of IC302. When the lamp

output is from 1.05 to 1.35A, pin 8 of IC302 develops

high, IC303 is latched and all outputs are shut down. The

method to release the latch operation is the same as the

over-voltage protection description.

Over-current protection at +10V, +13V, +15.5V lines are

carried out by the over-current protection characteristic

provided with the series regulator ICs (IC203, IC202 and

IC201). Refer to Fig. 1-5-1.

In this case, as only the line short-circuiting or overload-

ing is protected, no effect appears on other outputs. The

protection is released by removing the over current

flowing condition.

When short-circuiting or overloading continues, the IC

overheats and the overheat protection circuit inside the

IC works to shut down the output voltage. In this case,

the overheat protection is released by unloading the

current and removing the overheat of IC.

1-6. Overheat Protection

As an overheat protection of the power supply, the

temperature of switching FET Q301 of the boost-up-

converter is detected. Positive characteristic thermistor

TH301 for temperature detection is attached on the heat

sink of Q301. When Q301 is overheated owing to the

overload and/or defect of cooling fan, etc., the resistor

value of TH301 increases abruptly, while the surface

temperature exceeds approx. 120°C. Then the transistor

Q302 turns on, the voltage higher than 7V is added to the

pin 6 (OVP) of IC303, IC303 is latched and all outputs

are shut down.

100

When releasing the latch operation, stop to supply the

commercial power by canceling, cool enough after more

than approx. 120 seconds, and then re-supply the

commercial power.

1.0

2.0

3.0

4.0

Output current Io (A)

Fig. 1-5-1

1-2

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2. LAMP POWER SUPPLY CIRCUIT

(LAMP DRIVER)

2-1. Configuration

The lamp power supply cicrcuit receives a DC220 to

390V (primary side) from the system power supply and

provides a AC voltage (70 to 100V at ever turning on

the lamp) to turn on the lamp. Fig. 2-1-1 shows the block

diagram.

Lamp Driver

Commu-

tator

Stabilizer

Igniter

Lamp

Control

Mains

isolated

I122

I121

100nF

CB3

EMC GND

(optional)

CB2-1

SCI

CB2-2

Common

Flag

Fig. 2-1-1

The DC voltage is supplied to CB1 from the main power

supply unit through an interlock switch. This voltage

becomes AC input x 2Ö2 (= 340V for AC120V input)

when the lamp is off. CB2 is a connector for the lamp on

control signal input (SCI) and lamp off control signal

output (FLAG). When +5V is applied to SCI (CB2-1) in

the standby on, I122 FET transistor turns on, the igniter

develops a high voltage pulse (5 to 25 kV), and the lamp

starts to light up.

The pulse normally continues to be developed until the

lamp turns on (for max. 3s.). But if the lamp does not

turn on, I121 does not turn on, the voltage of CB2-3

develops high. I121 turns on and develops low after the

lamp turned on, the igniter circuit stops the operation.

Then the AC70 to 100V is applied to the lamp.

2-1

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3. OPTICAL SYSTEM

3-1. Configuration

No.

Name

Description

Light source of the optical system. AC lighting system 120W, arc length 1.3 mm.

As the arc length is shorter than the conventional metal halide lamp, the light source

operates as an ideal light point source and this improves the light convergence factor.

Also, the color temperature gets higher and this allows to reproduce more natural

white color.

UHP lamp

Lamp

unit

Parabolic

reflector

Parabolic reflector converges light emitted from the UHP lamp forward in approximate

parallel light beams and illuminates the liquid crystal panel.

UV IR filter

Optical filter to pass necessary visible rays and cut unnecessary ultraviolet rays and

infrared rays among light emitted from the UHP lamp.

Two multi-lenses A and B allow a circular beam light emitted from the light source to

illuminate the square liquid crystal panel evenly, thus providing projected pictures

with less brightness variation.

Multi-lenses

A, B

Polarization

light beam

splitter (PBS)

Separates the illuminating light from the light source into P polarization light and S

polarization light and leads both light to the multi-lens B with a little angle.

Phase

Converts the polarization direction of incident light via the multi-lens B into another

direction. Here, P polarization light waveform separated by PBS is converted into

another S polarization light waveform.

difference

plate

Condenser

lens

Converges the illuminating light emitted from the light source into the liquid crystal

panel.

Separates the white light emitted from the light source into RGB three primary colors.

The white light emitted from the light source reflects B light using a dichroic mirror 1

and the RG lights pass through the dichroic mirror 1. Of the RG lights passed, G light

is reflected by the dichroic mirror 2 and R light passes.

Dichroic

mirror

Mirror

box

unit

Full reflection Reflection mirror to lead the R and B lights separated by the dichroic mirrors 1 and 2

mirror

to the liquid crystal panel.

Light transmitted through liquid crystal panel is converged in direction of focal point

and effectively entered entrance pupil of the projection lens.

Field lens

In the R axis optical path which is longer than those of G, B, the relay lens works as

a correction lens to arrange the illumination distribution of the liquid crystal panel

surface with that of other liquid crystal panel.

Relay lens

The illumination lights separated into RGB have the S polarizing waveform compo-

nent in processing the PBS and phase difference plate operation previously de-

scribed.

The incident side polarized plate arranges the illumination light more effective direct

polarizing waveform. The phase difference plate used works to converge the S

polarizing waveform into the P polarizing waveform which fits to the transparent axis

of the liquid crystal panel.

Since the phase difference plate possesses the wavelength characteristics for light,

each RGB axis employs exclusive phase difference plate. These polarizing plates

and difference plates are constructed in one plate by attaching each other, and put

on a glass plate.

To increase the color purity ratio of three primary colors, the glass plate possess the

dichroic filter characteristics for RG axis.

Incident side

polarized

plate/Phase

difference

plate

Light exit side polarized plate is put on the light exit plane. When no signal voltage is

applied, the polarization direction of transmission light rotates by 90 degrees. When a

voltage is applied, the polarization direction is controlled owing to the voltage

applied. That is, the liquid crystal panel employs such general TN type liquid crystal.

Liquid crystal In this model, the incidence/exit polarization plate is placed (in normally white mode)

Prism

unit

panel

so that the light transmission amount becomes maximum (white) when no voltage is

added and the light transmission amount becomes minimum (black) when maximum

voltage is added.

According to the liquid crystal panel specification, exclusive panel for each RGB axis

is employed and shown by identification seals.

Cross prism

Works to mix RGB lights passed through the liquid crystal panel.

Demodulated by the video signal on the liquid crystal panel and projects pictures

displayed on the liquid crystal at a screen. Light axis of the projection lens is set at

upper side of center of the liquid crystal panel and this realizes easy viewing of the

panel because the projected screen position is upper than the unit position. The

projected light shows S polarizing waveform and is compatible with the polarizing

screen.

Projec-

tion

lens

Projection

lens

The projection lens employs the zoom & focus system and allows to project enlarging

a picture upto maximum approx. 300 inch.

3-1

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XGA 1.3 inch 3 plates system

-3

UHP

(120W)

-1

-2

-1

Fig. 3-1-1 Optical configuration diagram

3-2

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4. R.G.B. DRIVE CIRCUIT

4-1. Outline

The outline of RGB drive circuit is described below

using the G process of the RGB drive circuit as an

example.

Exclusive for odd number pixel

Q516

Panel

Q505,Q506,Q507

VIDEO

input

Normal

amp.1

Q502

Amp.

SW1

Q514

SW3

Q515

SW5

Odd number

pixel memory

DAC1

Q508,Q509,Q510

Inverted

amp.1

Q511,Q512,Q513

Normal

amp.2

Q504

Amp.

Even number

pixel memory

Q514

SW4

DAC2

Q515

SW6

Q523,Q524,Q510

SW2

Inverted

amp.2

Line inverted

Q517

Exclusive for

even number pixel

Frame inverted

12-phase composite

(12-phase collectively input)

12-phase decomposite

Digital PC board

Drive PC board

Fig. 4-1-1

In the panel, 1024 pixels are arranged in a horizontal

direction and 768 lines of the pixels are in a vertical as

shown in Fig. 4-1-2.

1024 pixels

1022 1023 1024

1st line

As an H inverted drive system is employed, the panel

input signal waveform is as shown in Fig. 4-1-3.

768 lines

Black level

White level

768th line

2nd line

1st line

Center voltage

1st line

2nd line

White level

Fig. 4-1-2

Black level

1st frame

2nd frame

Fig. 4-1-3

4-1

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The signal as shown in Fig. 4-1-1 is separated into the

odd and even pixels at the digital PC board. After the

signal process is carried out in the drive PC board, the

odd and even pixel signals are synthesized to

decomposite the signal on the panel.

3) the signal passing through DAC2 ® Q504 ® Normal

amp. 1 ® SW41 ® SW6 ® Q517 to the positive

phase 2 and

4) the signal passing through DAC2 ® Q504 ® inverted

amp. 2 ® SW42 ® SW6 ® Q517 to inverted phase

Referring to Fig. 4-1-1, the operation principle is

described.

the AC and DC levels of the positive phases 1, 2 and the

inverted phases 1, 2 are expected to be the same.

When assuming;

1) the signal passing through DAC1 ® Q502 ® Normal

amp. 1 ® SW31 ® SW5 ® Q516 to the positive

phase 1,

However, each voltage will vary slightly owing to the

adjustment variation. In this case, each frame signal is

assumed as follows.

2) the signal passing through DAC1 ® Q502 ® inverted

amp. 1 ® SW32 ® SW5 ® Q516 to the inverted

phase 1,

<1st frame>

10 11 12

Pixel

Inverted phase

2 voltage

Inverted phase

1 voltage

2nd line

Center voltage

1 2

10 11 12 Pixel

Normal phase 1

voltage

Normal phase 2

voltage

1st line

<2nd line>

10 11 12 Pixel

Inverted phase 2

voltage

Inverted phase 1

voltage

2nd line

Center voltage

1st line

10 11 12 Pixel

Normal phase 1

voltage

Normal phase 2

voltage

Fig. 4-1-4

As shown in Fig. 4-1-4, even if a slight level difference

occurs among the positive phases 1, 2 and inverted

phases 1, 2 signals (approx. 100 mV), the level differ-

ence will be decreased visually by reducing the level

variation of the same line between each frame and

inverting the pixel voltage of the adjacent lines (1st line

and 2nd line) between each frame.

4-2

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4-2. Operation Description

4-2-1. Outline of Liquid Crystal Panel

The liquid crystal panel module is an active matrix panel

with a built-in driver of multi-crystal silicon. The liquid

crystal panel module is designed for use of color projec-

tors in combination with an enlargement projection

system and dichroic mirror.

The video signal of the odd number pixel (even number

pixel) is sent to Q501 (Q503) base and supplied to pin 16

of Q502 (Q504), LM1201M. The signal is clamped at

pin 16 and the pedestal voltage is adjusted at pin 6 after

the DC level is stabilized and then AC level is adjusted at

pin 3.

The signal is developed from pin 8, supplied to the buffer

circuits of Q505 – Q507 and Q511 – Q513, and supplied

to the inverted circuits of Q508, Q509, Q510, Q523,

Q525 and Q510. These signals are supplied to pins 5, 6,

8, 13, 15 and 16 of 12 phases development IC.

CXA2504N, Q516 and Q517 of sample-and-hold passing

through the SW circuit composed of Q514 and Q515.

The signals are developed from pins 37, 35, 33, 25 and

23 for each input.

(1) Screen size

26.624 (W) x 19.968 (H)

(2) Pixel number

(3) Applicable to XGA

(4) Monochrome panel

(5) Drive system

(6) Dot clock

1024 (W) x 768 (H)

H inverted drive

65 MHz

(7) Inverted function for UP/DOWN/LEFT/RIGHT di-

rections

The signals at pins 4, 7, 14 are used as bias input and the

bias inputs set the center DC voltage of output equal to

the bias voltage.

Q519 works to suppress the noise occurred at 12 phases

collective input process of the panel.

4-2-2. Basic Component

Table 4-2-1 Terminal description

Pin No.

Name

Pin No.

Name

VID7

Pin No.

Name

DIRX

ENB2

ENB1

VSSX

VID2

VID4

VID6

VID8

Pin No.

Name

VID10

VID12

LCCOM

N.C.

CLY

VID5

VID3

VID1

VSSX

CLX

CLY

VDDY

NRS2

NRS1

LCCOM

VID11

VID9

NRG

CLX

DIRY

VSSY

VDDX

4-3

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Table 4-2-2 Input terminal function description

Name

Function

Start pulse input terminal of X shift register composing X driver.

Transfer clock input terminal X shift register composing X driver

X driver driving direction switch input terminal (DIRX = H R shift, DIRX = L L shift)

X driver enable pulse input terminal

CLX, CLX

DIRX, DIRX

ENB1 – ENB2

VID1 – VID12

X driver video signal input terminal

Start pulse input terminal of Y shift register composing Y driver.

Transfer clock input terminal of Y shift register composing Y driver.

CLY, CLY

Transfer clock input terminal of Y shift register composing Y driver. (DIRX = H Down shift,

DIRX = L Up shift)

DIRY, DIRY

LCCOM

VDDX

Diagonal electrode potential input terminal of liquid crystal panel

X driver positive power supply input terminal

Y driver positive power supply input terminal

X driver negative power supply input terminal

Y driver negative power supply input terminal

Drive signal input terminal for auxiliary signal circuit

Auxiliary signal input terminal

VDDY

VSSX

VSSY

NRG

NRS1 – NRS2

4-4

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5-1-3. Adjustment Control

5. MICROPROCESSOR

•

Video controls (high & low brightness ratio,

5-1. System Outline

brightness, color density, tint, sharpness)

The system microprocessor has features as shown below.

Panel adjustments (V position, H position,

phase, clock, user registration, user read-out)

In considering easy maintenance for specification

modification, etc., the program content is written in the

built-in non-volatile memory.

Mode adjustments (Wide, MIC, OSD mute,

projection)

The program is also developed in considering use of

structured notation, parts modularity, and multi filling

system.

Language adjustments (English, Japanese,

French, German, Spanish, Italian)

5-1-4. Adjustment Control at Factory Delivery

Major functions of the system microprocessor are as

follows.

•

Video sub adjustments (RGB gain, sub-bright)

Drive adjustments (each item for panel controls,

RGB trimming)

5-1-1. System Control

•

Microprocessor program write process

Non-volatile memory control process

Remote control reception process

RS-232C transmission/reception process

Status read process

Fig. 5-1-1 shows the system block diagram.

On-screen display process

5-1-2. Normal Control

•

Power

ON/OFF

(Main/Fan/Lamp)

•

Input switch

(RGB/Video/Camera)

Sound volume control UP/DOWN

Adjust

(Up/Down/Left/Right)

All mute

Audio mute

Display

Freeze

ON/OFF

Resize

Focus

UP/DOWN

(at camera use)

•

Zoom

UP/DOWN

(at camera use)

5-1

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PL010

PL004

PL001

HPCL010215

QL012

HC125

DRIVE

4 78 79 11 10

77 76 75 74 72 71 70 69 68 67 66 65 64 63 62 61 60 59 49 55 54

QL010

HC165

PL003

QL005

HC14

SENSOR

PL009

QL002

HD64F3337YF16

16 17

21 22 23 24 25 26 27 28

39 40 41 42 43 44

PL006

PL002

QL003

QL004

PQ20VZ1U

RN5VD27A

HC541

QL007

CAT24C16J

QL006

LED

Fig. 5-1-1 System block diagram

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5-2. System Microprocessor

Using an exclusive data-writer allows easy maintenance

of the system microprocessor when specification modifi-

cation, bug correction, etc. will occur.

The system microprocessor QL002 employs an 8 bit

micro-controller (HD64F3337YF16).

Table 5-2-1 shows the terminal functions of the system

microprocessor.

In this system microprocessor, a program area is pro-

vided inside the non-volatile memory.

Table 5-2-1 Terminal functions of the system microprocessor

Pin No.

Name

RES

Function

Reset input

I/O

Pin No.

Name

LED2

LED3

LED4

LED5

Function

I/O

LED data 2

LED data 3

LED data 4

LED data 5

XTAL

EXTAL

MD1

Clock input for oscillation

Clock output for oscillation

Mode 1

MD0

Mode 2

MAIN. PW Main power supply swtich

NMI

Priority interruption

Memory write voltage

Digital power supply

Not used

FAN. PW

Fan power supply switch

Digital power supply

FVPF

VCC1

WDT

RXD0

TXD0

GND1

SDA

CC2

LAMP. PW Lamp power supply switch

OSDL

DDCV

SENL

SENC

SEND

VD0C

VD0D

GND2

DRVC

DRVD

OSDC

OSDD

PLLU

SYGL

SYGC

SYGD

OSD load

RS-232C reception for camera

RS-232C transfer for camera

Digital ground

Not used

Sensor load

Used for sensor

Not used

I/O

Oscillation clock

Video I C clock

I/O

SEL

Remote controller selection

Non-volatile memory clock

Non-volatile memory data

Not used

Video I C data

EEPCK

EEPDT

Digital ground

I/O

Drive I C clock

I/O

Drive I C data

REMOCON Remote controller reception

OSD clock

AUX

KEY0

KEY1

KEY2

KEY3

KEY4

KEY5

KEY6

KEY7

AVCC

AD0

Not used

OSD data

Key input 0

Key input 1

Key input 2

Key input 3

Key input 4

Key input 5

Key input 6

Key input 7

Analog power supply

Not used

PLL enable

SYG load

SYG clock

SYG data

T-FORC data 0

T-FORC data 1

T-FORC data 2

T-FORC data 3

T-FORC data 4

T-FORC data 5

T-FORC data 6

T-FORC data 7

Digital ground

T-FORC clock

T-FORC read/write

T-FORC enable

T-FORC reset

RS-232C transfer for control

RS-232C reception for control

Not used

AD1

Not used

AD2

Not used

AD3

Not used

GND3

CLK

AD4

Not used

AD5

Not used

R/W

AD6

Not used

ENB

RST

AD7

Not used

AGND

LED0

LED1

Analog ground

LED data 0

LED data 1

TXD1

RXD1

SCL

5-3

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5-3. Power Supply Reset Process

5-5. Remote Control Reception Process

In the power supply reset process, power supply reset IC

(RN5VD27A), QL004 is employed.

In the remote control reception process, a remote control

unit (CT-9925) connected to the remote control terminal

emits a remote control signal and a remote control signal

receive section on the front panel, the rear panel or the

camera arm (for TLP511) decodes the signal.

The reset IC,QL004, develops the reset signal when the

power supply voltage for the microprocessor varies and

becomes lower than the specified voltage, and sends the

signal to the reset terminal of the system microprocessor

(QL002).

The remote control signals for rear panel and camera

section (for TLP511) are selected by QL012 buffer

(TC74HC125AF). Then both signals are mixed with the

remote control signal for front panel through QL005

buffer (74HC14AF).

5-4. Non-volatile Memory Control Process

In the non-volatile memory process, data reading and

saving for various adjustments are carried out on the

non-volatile memory, QL006 (CAT24C16J).

Finally, the signal mixed is supplied to the remote control

terminal of the system microprocessor (QL002).

When the power (AC) is on, all the adjustment data are

read out by the system microprocessor (QL002), then the

previous status is realized.

5-6. RS-232C Transmission/Reception

Process

In the RS-232C transmission/reception process, an RS-

232C signal entered through the RS-232C connector (D-

SUB 9P) is decoded in the RS-232C interface

(mPD4721), and fed to RXD1 terminal of the system

microprocessor (QL002).

When saving the data, all the adjustment data are written

by the system microprocessor (QL002), then the current

status is preserved.

However, if a failure (such as power interruption due to

lightning, etc.) occurs during the adjustment data writing,

a data error may occur. If the data is determined as

incorrect, the initial data memorized on the system

microprocessor (QL002) is read out and stored on the

non-volatile memory.

In the RS-232C transmission process, RS-232C signal

developed from TXD0 terminal of the system micropro-

cessor (QL002) is decoded in the RS-232C interface

(mPD4721) and fed to the camera microprocessor

section.

5-7. Status Read Process

In the status read process, the following status shown in

the table below are read by QL010 (74HC165AF) and

the error process corresponding to each status is carried

out.

Table 5-7-1 shows the contents of the status read signals

and the logic.

Table 5-7-1 The contents of the status read signals and the logic

Signal name

Pin No.

QL010

(L)

FAN1. ER FAN1. SW FAN2. ER

TEMP1. ER

Normal

Abnormal

LAMP. ER

Abnormal

Normal

MAIN. ER

Abnormal

Normal

Abnormal

Normal

Abnormal

Normal

(H)

Abnormal

5-4

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5-8. Status Display Process

5-9. On-screen Display Process

In the status display process, two-color lighting LEDs of

DL037, DL038 and DL039 turn ON for each kind of

status shown in the table below by using LED0 to LED5

terminal output of the microprocessor.

In the on-screen display process, control signals are

supplied to the OSD display IC QX003 (CD0016AM),

and the OSD display IC generates character display

signals at the timing determined by VD, HD and clock

supplied to the IC separately.

Table 5-8-1 Contents of the status display signals and the logic

LAMP

TEMP

Function

Status

Countermeasure

Stand-by power supply

abnormality

At AC cord plugged Repair

Green

Red

Green

Red

Green

Non-volatile memory OK

Non-volatile memory NG

Stand-by

At AC cord plugged Normal

Red

At AC cord plugged At initial time

Orange

Green

Orange

At power off

At power on

During power on

At power off

Normal

Lamp ON

(Green)

Green

Lamp Heat-up

Lamp Lighting

Lamp OFF

(Green)

Lamp cool-down

Main power supply

abnormality

Red

At power On/During Repair

Red

Lamp no-lighting

Lamp lighting-lifetime

Suction fan stop

At power On/During Repair or preparation failure

Operates after approx. 2500 H

Orange

At power on

operation

Red

(Red)

At power on

Ever

Repair

(Orange) Exhaust fan stop

(Green)

Red

Fan filter open

Temperature sensor

abnormality

Lower internal temperature of

the unit.

Red

Ever

X: Lighting OFF

( ): Blinking

5-5

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5-10. Video System Control Process

5-11. Panel System Control Process

In the video system control process, control signals are

supplied to various video system process ICs shown in

The panel system control process supplies various

control signals to the panel system control ICs shown in

the table below.

the table below. Table 5-10-1 shows the I C control for

each kind of video system.

Table 5-11-1 shows the IC control for each kind of panel

system.

Table 5-10-1 I C control for each kind of video system

Part No.

Type name

Process

CXA1855Q

(Custom: $90)

QV001

I/O SW process

TC9090N

QV002

QV005

QV008

QV007

QV045

QB025

QV057

Color signal process (3D Y/C separation)

(Custom: $B2)

TDA9141

(Custom: $8A)

Sync detection process (Custom: $8B)

Signal kinds identification (NTSC/PAL/SECAM, etc.)

TDA4780

(Custom: $88)

Video control (Density, hue)

TDA4672

(Custom: $88)

Video control (Sharpness control)

CXA1315M

(Custom: $40)

Input SW, MIC SW

Volume, mute, MIC gain

CXA1315M

(Custom: $44)

Brightness, contrast, RGB gain

Sync information

M62320FP

(Custom: $71)

Camera ON/OFF (for TLP511), focus, zoom reading

Fan switch open

Table 5-11-1 IC control for each kind of panel system

Part No.

Type name

Process

Various kinds of screen display process (position, picture frame,

property)

Screen position control (Vertical position, horizontal position)

SYG

QX004

(TC160G54AF1137)

QX007

CXA3106

Screen position control (sampling phase, sampling frequency)

QX204

QX404

QX604

TFORC

(TC203E2651AF-01)

Picture frame control (R)

Picture frame control (G)

Picture frame control (B)

M62320FP

Panel mode control

QX001

QX002

(Custom: $78)

A/D sample phase (R)

M62320FP

(Custom: $7A)

A/D sample phase (G)

A/D sample phase (B)

5-6

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5-12. Drive System Control Process

Table 5-12-1 shows each kind of the drive system IC

control.

In the drive system control process, the control signal is

supplied to each kind of drive system process ICs shown

in the the table below.

Table 5-12-1 Each kind of the drive system IC control

Part No.

Type name

Process

M62399FP

Q701

Process relative to R drive

Process relative to G drive

Process relative to B drive

Process relative to VCOM, NR

Process relative to NR, Bias

(Custom: $90)

M62399FP

(Custom: $92)

Q702

Q703

Q704

Q705

M62399FP

(Custom: $94)

M62399FP

(Custom: $96)

M62399FP

(Custom: $98)

5-13. Various Display Modes

(5) In the normal status, ON/STANDBY LED and the

LAMP LED are turned on in green, and the main

power and the lamp power are turned on.

In this system, various LED display patterns are provided

in relation to the display modes shown in Table 5-8-1.

Operation processes from the status of AC cord plugged

to that of power on and power off will be given below.

(6) When the power is turned off by pressing the ON/

STANDBY key, the unit enters the standby status in

passing through following processes.

(1) Data of the non-volatile memory are checked when

the AC cord is plugged, and all the LED are turned

on in red in the initial use. In second or later use, all

the LEDs are turned on in green and the unit enters

the standby status.

1) When the lamp power is turned off, ON/

STANDBY LED turns on in orange.

2) The LAMP LED blinks in green for about 1

min. For this period the lamp can not be turned

on again by the ON/STANDBY key.

(2) In the standby status, only the ON/STANDBY LED

is turned on in orange, and the main power is off

and the lamp power is also off.

3) When blinking of the LAMP LED stops, only

the ON/STANDBY LED turns on in orange.

After this, the lamp can be turned on again by

the ON/STANDBY key.

(3) When the power is on by pressing the ON/

STANDBY key, the unit enters a normal status in

passing through following processes.

(7) Moreover, the fan works for about 2 min. to lower

temperature of the unit. When the main power turns

off, the fan also stops and returns to the standby

status.

1) The main power is on, and ON/STANDBY LED

turns on in green.

2) The fan power is on, and the fan starts to rotate.

(8) If an error occurs due to some causes, the ON/

STANDBY LED turns on in red, and the error

information is kept in the display status of the

LAMP and TEMP LEDs. When the error is

detected, the unit enters the standby status after

cooling down process for about 2 min. In this case,

if the error status continues, the error display is also

kept and any key entry is not accepted.

3) The lamp power is on, and LAMP LED blinks

in green for about 3s.

4) With the lamp turned on, LAMP LED turns on

in green and the unit enters the normal status.

(4) If the lamp does not turn on, ON/STANDBY LED

turns on in orange, and the LAMP LED blinks in

green for about 1 min. and then the unit returns to

the standby status.

5-7

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5-14. Applicable Signal

In other mode, the signal line number is detected to allow

the separate adjustment in the VGA system (basically

effective for line number of 480 lines), SVGA system

(basically effective for line number of 600 lines) and

XGA system (basically effective for line number of 768

lines).

Various kinds of signals are used as the applicable

signals in the preset mode (standard value) as shown in

Table 5-14-1. For the signals not fit to the preset modes,

a user mode is provided.

In the preset modes, the applicable signals are based on

the VESA standard, so the sample frequency (CLOCK

adjustment in the panel menu) is not used, but the

adjustment is allowed only in the user mode.

In the user mode of SGA system (900 line system and

1024 line system), the input signal is applicable to the

plain display mode. That is, the signal is displayed in

different two ways owing to the line number in vertical

direction.

Table 5-14-1 Applicable signal

Signal

Content

Resolution

Frequency

V (Hz)

All

Sync

H/V

Operation

Clock

(MHz)

Corre-

Mode

H (kHz)

Remarks

spondence

NTSC

PAL

V60

V72

V75

V85

M13

24K

T70

T85

NTSC

664

756

640

720

640

720

800

832

1024

1152

484

574

480

400

350

400

350

400

350

400

600

624

768

870

864

15.734

15.625

31.470

37.861

37.500

43.269

35.000

24.830

31.470

37.861

37.927

35.156

37.879

48.077

46.875

53.674

49.724

48.363

56.476

60.023

68.677

59.940

50.000

59.940

72.809

75.000

85.008

66.667

56.420

70.020

85.080

85.039

56.250

60.317

72.188

75.000

85.061

74.550

60.004

70.069

75.029

84.997

12.590

12.500

25.175

31,500

31.500

36.000

30.240

21.053

28.322

31.500

35.500

36.000

40.000

50.000

49.500

56.250

57.283

65.000

75.000

78.750

94.500

75.030

75.000

75.025

800

525

625

525

520

500

509

525

444

450

445

446

625

628

666

625

631

667

806

800

808

915

900

1066

N/N

P/N

N/P

P/N

N/P

P/N

N/P

N/N

Video input

PAL

VGA 60 Hz

VGA 72 Hz

VGA 75 Hz

VGA 85 Hz

MAC-13”

800

832

840

832

864

PC98-STD

VGA 70 Hz

VGA 85 Hz

848

900

800

832

936

S56 SVGA 56 Hz

S60 SVGA 60 Hz

S72 SVGA 72 Hz

S75 SVGA 75 Hz

S85 SVGA 85 Hz

1024

1056

1040

1056

1048

1152

1344

1328

1312

1376

1456

1600

1688

M16

X60

X70

X75

X85

M21

MAC-16”

XGA 60 Hz

XGA 70 Hz

XGA 75 Hz

XGA 85 Hz

MAC-21”

100.000 68.653

108.000 67.500

Plain display

SXGA1 1152 system 1152

SXGA2 1280 system 1280

1024 135.000 79.976

• In the sync column of Table 3-14-1, P shows the posi-

tive polarity and N shows the negative polarity.

• In the operation column, O shows a standard mode, D

shows pull-in mode, X shows plain display mode.

5-8

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5-15. RS-232C Control Method

Table 5-15-1 RS-232C connection signals

Pin No. Signal name

Signal content

Receive data

I/O

Signals are connected to the RS-232C connector in a

straight format as shown in Table 5-15-1 RS-232C

connection signals. This is because a crossing connec-

tion is provided inside the unit. Communication condi-

tions are set to meet the conditions given in Table 5-15-2.

RXD

TXD

DTR

S. G

DSR

RTS

CTS

Transmit data

Data terminal ready

Signal ground

Data set ready

Table 5-15-3 shows the command list of RS-232C.

Transmission request

Transmission enable

When transmitting the command, be always sure to keep

100 ms interval between each command. Moreover, the

process time is required for a while when turning the

power ON/OFF and/or selecting the input mode. So in

such cases, also be always sure to keep enough intervals

between the commands.

Table 5-15-2 RS-232C communication conditions

Item

Conditions

Communication system

Transmission speed 9600 baud, No parity, Data length 8 bit, Stop bit: 1 bit

STX (1 byte) + CMD (3 byte) + ETX (1 byte) = 1 block

STX is 02h, ETX is 03h, CMD is command string (Uppercase character)

Communication type

5-9

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Table 5-15-3 RS-232C command list

Item

Command

PON

POF

IN1

Content

Power supply ON

Power supply OFF

Video input

Item

Command

PVP

PHP

PPH

PCK

PL0

Content

Vertical position

Horizontal position

Sampling phase

Sampling frequency

Normal status

Panel

IN2

RGB input

IN3

Camera input

Volume UP

VUP

VDW

DON

DOF

MON

MOF

AON

AOF

FON

FOF

RON

ROF

CFU

CFD

CZU

CZD

PL1

Volume DOWN

Display ON

PL2

PL3

Display OFF

All Mute ON

All Mute OFF

Audio Mute ON

Audio Mute OFF

Freeze ON

PL4

PL5

PS0

PS1

PS2

PS3

Freeze OFF

Resize ON

PS4

RGB

PS5

Resize OFF

Focus UP

Mode

MW1

MW0

MM1

MM0

MO1

Wide ON

Camera (for TLP511)

Wide OFF

MIC ON

Focus DOWN

Zoom UP

MIC OFF

Zoom DOWN

OSD mute ON

Menu left shift/

adjustment value

DOWN

Common adjustment

ALF

MO0

OSD mute OFF

Menu right shift/

Floor mounted front

projection

ARG

AUP

ADW

RST

SAV

PJ0

PJ1

PJ2

PJ3

LEN

adjustment value UP

Menu up shift

Ceiling mounted front

projection

Menu down shift

Floor mounted rear

projection

Standard setting for

each item

Ceiling munted rear

projection

Adjustment value

storing

Language

English display

Video

VCN

VBR

VCL

VTN

VSH

Contrast

Bright

Color

Tint

LJP

LFR

LGR

LSP

LIT

Japanese display

French display

German display

Spanish display

Italian display

Sharp

Camera

CSH

CSL

SIR

High sensitivity ON

High sensitivity OFF

Iris adjustment

5-10

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6. DIGITAL CIRCUIT

6-1. Outline

A Configuration of digital circuit is shown in Fig. 6-1-1.

The functions of digital circuit are described on the

following pages.

QX202, 203, 205, 206

MB814265/HM514265

(MEMORY)

QX201

CXA3026Q

(A/D CONV.)

QX204

TC203E2651AF-01

(T-FORC)

QX207

EPM7064LC68

(EXCHANGE)

QX208

MB40950

(D/A CONV.)

R signal

(2.0V - 4.0V)

R signal

(3.0V - 5.0V)

1/2 CLK

R CHANNEL

G signal

(2.0V - 4.0V)

G signal

(3.0V - 5.0V)

G CHANNEL (RX4**, CX4**, QX4**)

B signal

(2.0V - 4.0V)

B CHANNEL (RX6**, CX6**, QX6**)

B signal

(3.0V - 5.0V)

42 MHz

System clock

for T-FORC

CLK (PECL)

ZX003

42 MHz

X'tal OSC

QX003

ON SCREEN

DISPLAY

FREEZE

(MPU or camera)

VD (PANEL)

VD (INPUT)

HD (INPUT)

HD (PANEL)

QX004

TC160G54AF1137

(SYG)

QX009

EMP7160ELC84

(TIMING)

LCD panel

clock

Timing signals

for LCD drive

QX028

CXA3106Q

1/2 CLK

(PLL IC)

Reference

clock for

LCD drive

Reference clock

for signal format

measurement

For RGB signal

ZX003

32.5 MHz

X'tal OSC

QX008

TLC2932

(PLL IC)

QX029

TLC2932

(PLL IC)

For VIDEO signal

Fig. 6-1-1

6-1

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6-1-1. PLL Circuit

6-1-4. Gamma Correction Circuit

The PLL circuit develops the clock signal synchronized

with the horizontal sync signal, using the horizontal sync

signal entered.

The gamma correction is carried out in the digital circuit.

So the digital circuit develops the signal corrected in

gamma.

For RGB signals, a highly stable CXA3106 (QX028) is

used. For video signal, a highly traceable TLC2932

(QX029) is used.

The gamma correction circuit is built in the T-FORC

(QX207, QX407 and QX607) and the gamma correction

characteristics are set by the microprocessor using a bus.

6-1-2. Video Signal Format Conversion

6-1-5. Panel Driving Timing Signal Generation

The LCD panel used for the unit requires a non-interlace

signal of 65 Hz dot clock entered. Accordingly, all the

RGB signals are converted into XGA 60 Hz format (Dot

clock = 65 MHz). In the same way, the video signal

(interlace signal) is converted into a non-interlace signal

with 64 MHz dot clock in keeping the vertical sync

signal frequency. These processes are carried out by the

newly developed ICs T-FORC (QX207, QX407 and

QX607) and memories (QX202, QX203, QX205,

QX206, QX402, QX403, QX405, QX406, QX602,

QX603, QX605 and QX606).

The driving for LCD panel requires various kinds of

timing signals. These timing signals are generated in the

digital circuit and especially generated by the timing

generation PLD (QX009).

6-1-6. ON-SCREEN Character Generation

The ON-SCREEN character timing signal is generated

and superimposed inside the digital circuit. So the signal

composed of the ON-SCREEN character is developed

from the digital circuit.

6-1-7. Signal Format Measurement

Furthermore, as the clock of XGA signal reaches approx.

80 MHz (max.), all signal processes are carried out in

parallel for even and odd pixels grouped. The video

signal entered is converted into the digital video signals

for two systems by the A/D converters (QX204, QX401

and QX601).

The RGB signals consist of various kinds of signal

formats, and the timing signal, enlargement ratio and etc.

must be switched corresponding to each signal format.

For this purpose, the signal format identification is

carried out by measuring the HD signal frequency

entered and the line number per 1 frame. This circuit is

built in the SYG (QX004) and the processed result is

read by the microprocessor through the bus line.

The signals divided into two systems are processed in

parallel in stages after the digital circuit. In case of the

process carried out in parallel as described above, if the

characteristics between two systems differ, the vertical

stripes will appear on the screen. In order to reduce this

vertical stripes, the signal system used is exchanged for

every one line and one field by the EXCHANGE PLD

(QX207, QX407 and QX607). The signals exchanged are

returned to the original order just before reaching the

LCD panel.

6-1-3. Screen Size Enlargement and Reduction

The pixel number of the LCD panel used for the unit is

1024 x 768 pixels. As for a signal entered, various kinds

of signals are used ranging from 640 x 480 pixels of

VGA signal to 1280 x 1024 pixels of SXGA signal. In

this unit, these signals are displayed on the whole screen

by enlarging/reducing the signals. The enlargement/

reduction process are also carried out by the ICs T-FORC

(QX207, QX407 and QX607) and memories (QX202,

QX203, QX205, QX206, QX402, QX403, QX405,

QX406, QX602, QX603, QX605 and QX606).

6-2

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6-2. Each IC Description

The VCO, phase comparator, loop filter and frequency

dividing circuit are built in the IC, so the IC can generate

the clock signal by itself.

6-2-1. PLL IC CXA3106Q (QX028) for RGB Signals

A configuration of CXA3106Q is shown in Fig. 6-2-1.

The PLL IC of CXA3106Q is an IC with high perfor-

mance and low jitter, and can generate the clock signal

synchronized with the horizontal sync signal of max. 120

MHz.

RC 1

RC 2

1 bit

ON/OFF

DSYNC

(TTL)

VCO

(TTL)

1 - 4 CLK

TTLOUT

TTLIN

COARSE

DELAY

LATCH

LOGIC

POLARITY

1 bit

DSYNC

(PECL)

VCO

(PECL)

PECLOUT

1 bit

PECLIN

2 bits

ON/OFF

CLK

(TTL)

SYNC

(TTL)

TTLOUT

1 bit

TTLIN

POLARITY

1 bit

ON/OFF

SYNC

(PECL)

1/16 20/16 CLK

PECLIN

NCLK

(TTL)

TTLOUT

PHASE

DETECTOR

CHARGE

PUMP

FINE

DELAY

VCO

MUX

1 bit

DIV

CLK

(PECL)

PECLOUT

1 bit

2 bits

1 bit

5 bits

1/256 1/4096

ON/OFF

PROGRAMMABLE

COUNTER

CLK/2

(TTL)

TTLOUT

HOLD

(TTL)

TTLIN

1 bit

12 bits

ON/OFF

REST

NCLK/2

(TTL)

TTLOUT

1/2

CLK/2

(PECL)

PECLOUT

1 bit

ON/OFF

UNLOCK

DETECT

UNLOCK

VBB

1 bit

SYNTHESIZER

POWER SAVE

WHOLE CHIP

POWER WAVE

ON/OFF

PECL

READ OUT

TTLOUT

TTLIN

DAC

CONTROL REGISTER

1 bit

1 REF

SENABLE

SCLK

SDATA

SEROUT

DIVOUT TLOAD

Fig. 6-2-1

6-3

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6-2-2. PLL IC TLC2932 (QX029) for Video Signal

6-2-4. Timing Signal Generation PLD (QX009)

The PLL IC of TLC2932 is composed of a phase

comparator and a VCO. As a frequency dividing circuit is

not built in, so the IC works as a PLL circuit by connect-

ing to the external VCO terminal of QX028 and using the

frequency dividing circuit of QX028.

A configuration of timing signal generation PLD is

shown in Fig. 6-2-3. The timing generation PLD gener-

ates the clock pulse and the timing signal to drive the

panel. As the signal timing and clock differ owing to the

inverted driving for top/bottom/left/right of panel and

kinds of input signals, the mode signal controls the

timing signal generation PLD.

6-2-3. Sync Process IC SYG (QX004)

A configuration of the SYG component is shown in Fig.

6-2-2. The SYG IC is used as a sync process IC and

composed of the timing generation circuit for 2 systems,

one for the input signal and the other is for the panel

display, and the input signal measurement circuit. The IC

supplies the HD/VD signal to each IC and the IC works

on the timing signal basis. Also, the field identification at

video signal is carried out by the IC. In the unit, as the

PLL circuit is independent from the SYG, the sync signal

(DSYNC) enters from the PLL circuit to pin 139. The pin

is connected to the reset terminal of the horizontal

counter (for input signal).

PLL IC

QX008

PLL

CIRCUIT

PCLK

AD CLK/2

32.5 MHz

MODE

DECODER

Timing signals

for

LCD panel

Mode

PANEL TIMING

GENERATOR

CLK, HD, VD

Fig. 6-2-3

32.5 MHz

SIGNAL FORMAT

6-2-5. A/D Converter CXA3026Q

(QX201, QX401 and QX601)

MEASUREMENT

HD, VD

TIMING SIGNAL

GENERATOR 1

A configuration of CXA3026Q is shown in Fig. 6-2-4.

The max. conversion speed of 120 MHz is supported by

CXA3026Q, A/D converter.

TIMING SIGNAL

GENERATOR 2

A frequency dividing circuit is built in the A/D converter

and the converter develops the data for two systems. The

clock speed is fast, so that the clock signal to be entered

is a differential input of PECL level. The input level of

analog signal ranges from 2.0 to 4.0V.

BUS

INTERFACE

MPU

Fig. 6-2-2

6-4

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INV

VRT

R/2

(LSB)

P1D0

P1D1

6 bits

P1D2

P1D3

P1D4

8 bits

RM3

P1D5

P1D6

6 bits

126

127

128

P1D7

(MSB)

RM2

(LSB)

P2D0

129

6 bits

P2D1

P2D2

P2D3

191

192

193

RM1

8 bits

6 bits

P2D4

P2D5

254

255

P2D6

R/2

P2D7

(MSB)

(ECL)

CLK

DELAY

(TTL)

1/2

TTL

OUT

(ECL)

NRSET

(TTL)

CLK OUT

SELECTOR

SELECT

Fig. 6-2-4

6-5

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OSD, OSDI, PBLK

6-2-6. Picture Size of View Conversion IC T-FORC

(QX204, QX404, QX604)

Video

signal

A configuration of T-FORC is shown in Fig. 6-2-5. The

T-FORC is a newly developed picture size conversion IC.

Video

signal

OSD SW

BLANKING SW

By using the IC, smooth picture enlargement and

reduction, and format conversion will be made. Also, a

gamma correction circuit is built in the IC.

Video

signal

Video

signal

SEL

PANEL TIMING

TRIM

To LCD panel

(ENB, DX)

From

timing PLD

Memory Freeze

MPU

MEMORY

INTERFACE

Fig. 6-2-6

6-2-9. D/A Converter

GAMMA

(LOOK UP

TABLE)

OSD SW

BLK SW

(NOT USED)

FORMAT

CONVERTER

MB40950 is a 10 bits 3 channels D/A converter of which

max. conversion speed is 60 MHz. In order to reduce the

difference of two systems of each RGB channel, each

RGB channel possesses one IC respectively. So one

channel of 3 channels D/A converter built in the IC is not

used. The output signal level ranges from 3.0 to 5.0V.

Input CLK

System CLK

(42 MHz)

MEMORY

INTERFACE

BUS

INTERFACE

Panel CLK

(32.5 MHz)

Memory

MPU

Fig. 6-2-5

6-2-7. Memory

The memory uses four general 4 M bits EDO-DRAMs

(256k x 16 bits) per 1 channel.

6-2-8. Exchange PLD

A configuration of timing signal generation PLD is

shown in Fig. 6-2-6. In the unit, the signal process is

carried out in parallel by dividing the process into two

systems. In order to reduce the characteristic difference

between these two systems, the signals of both systems

are switched for every 1 line and 1 frame. The PLD

carries out the process. Also, the ON-SCREEN display

signal superimposing, addition of non-display section for

top and bottom and left and right, etc. are carried out by

the PLD.

6-6

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7-1-2. Video Demodulation Section

7. VIDEO CIRCUIT

In the video demodulation section, the composite video

signal and Y/C signals are demodulated into the RGB

signals.

7-1. Circuit Component

The video circuit performs selection of input signals,

video signal (NTSC, PAL, SECAM) demodulation to

RGB signals, RGB input signal amplification and audio

signal amplification.

In the video/color process IC, the color demodulation is

carried out corresponding to the color mode of the video

signal entered. The applicable color modes are NTSC,

4.43 NTSC, PAL and SECAM.

Fig. 7-1-1 shows the block diagram.

The mode identification is automatically carried out by

the video/color process IC.

7-1-1. Input Signal SW Section

When the power turns on and the input is switched, the

composite video signal passing through the input SW IC

enters and the color mode is determined. The micropro-

cessor detects the result of color mode determination and

sets a corresponding color mode. The color difference

signal demodulated by the video/color process IC is

developed after processed its phase and signal level via

1H delay IC.

All the video and audio signals entered are sent to the

input SW IC (except for RGB signals). In the input SW

IC, the signals are switched corresponding to the

composite,Y/C and color modes (NTSC, PAL SECAM

and BLACK & WHITE) respectively. Processing routes

for the composite video signals are changed depending

on the color modes (NTSC, PAL, SECAM and BLACK &

WHITE).Y/C signals, SECAM and Black & White

signals are supplied to the video color process IC in the

next stage passing through the input SW IC. NTSC, PAL

and 4.43 NTSC color signals only are separated into the

luminance Y signal and color C signal by the digital

comb filter and then enter the input SW IC again as the

Y/C signals.

The luminance signal enters the picture quality correc-

tion IC and the color difference signal enters the RGB

demodulation IC via the delay line for matching with

the luminance signal.

In the RGB demodulation IC, the gamma correction,

color adjustment, etc. are carried out as well as the

luminance color difference signal is demodulated to the

RGB signals.

In the cases other than described above, when the power

is on or the input switching occurs, the signals are

supplied to the video/color process IC as a composite

video signal passing through the input SW IC.

7-1-3. RGB SignalAmplification Section

In the RGB signal amplification section, the RGB input

signals and the video signal demodulated to the RGB

signals are switched and the contrast and brightness

adjustments are carried out. Further, the gain adjustment

for each RGB signal is also carried out.

The RGB signals entered are divided in two systems; the

internal signal process and external output systems.

The signals for the external output system enter 75 ohm

driver IC and then enter D-sub 15 pin for output. The

RGB signals for internal signal process system enter the

mute IC. When the video signal is selected, the RGB

signals are muted by the mute IC output.

The sync signals of the RGB signals correspond to

HD,VD, composite sync (CS) and SYNC ON G signals.

7-1-4. Audio SignalAmplification Section

The audio signal inputs of the video and RGB inputs

correspond to L and R stereo input. After switching the

input, the signal develops at the audio terminal through

the output buffer circuit. After L and R signals are mixed,

the sound volume control IC controls its level, thus

controlled signal is amplified to the sufficient level to

drive the speaker by the audio output IC, and then sent

to the speaker.

7-1

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Fig. 7-1-1 Block diagram

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7-2. Input Signal Switch Section

In case of TLP511, the video signal from the camera

section is supplied as Y/C signals and enters pins 9 and

11 respectively.

The signal SW section works as a circuit to supply the

signal to the signal process section in the next stage and

each output terminal by switching the signal entered

(video, audio).

The video signal selected finally develops from pins 37

(Y) and 29 (C) respectively.

Each input signal is sent to QV001 (CXA1855Q) as

7-2-2. Audio Signal

shown in Fig. 7-2-1. The IC control is carried out by I C

The audio signal employs two input systems; one is for

video signal and the other is for RGB signals. Each

system is applicable to L and R stereo inputs respec-

tively.

bus.

7-2-1. Video Signal

The composite video signal enters pins 43 (V1) and 45

(Y1) at the same time. When the composite signal

entered is a NTSC/PAL color signal, pin 43 (V1) is

selected. When it is either a SECAM or Black & White

signal and when the input switching is carried out, pin

45 (Y1) is selected.

The audio signal for the video signal is selected when

the video signal is selected and the audio signal for RGB

signals is selected when the RGB signals are selected.

The audio signal selected develops from pins 33 (L) and

32 (R).

This is because the composite signal is supplied to the

video/color process IC in the next stage passing through

the Y/C separation IC QV002 (TC9090AN) when the

composite signal is either SECAM or black & white

signal and when the input switching is carried out.

7-2-3. RGB Signal

The RGB signals are entered using a high density D-SUB

15 and separated in two systems for the internal signal

process and the external output signal. The external

output signal develops at PV002 (RGB output connec-

tor) via QB007 (6 dB amp.). When the power turns on,

the RGB output signals always develop if any signal

enters at the RGB input terminal.

This is also because in the Y/C separation IC QV002

(TC9090AN), the SECAM signal cannot be separated

into Y and C signals, and it is not necessary for the Black

& White signal to be separated in Y and C signals.

On the other hand, the internal process signals for the

RGB signals enter QB004, QB005 and QB006, respec-

tively. The input signal switch IC controls to mute the

RGB input signals when selecting the video input.

The signal developed from pin 34 is Y/C-separated by Y/

C separation IC QV002 (TC9090AN) and then enters the

signal SW IC QV001 (CXA1855Q) again. (Pin 31 (Y),

pin 29 (C))

The Y/C signals entered from S terminal enter pins 3 and

5 respectively.

QV001

CXA1855Q

QV002

TC9090AN

VIDEO

V OUT 1

COMB

FILTER

Y IN 1

C IN 1

LV1

RV1

VIDEO

AUDIO

Y OUT 1

C OUT 1

QV005

TDA9141

S1/S2

L OUT 1

AUDIO

CAMERA

R OUT 1 32

SCL

SDA

LEV

REV

RGB

AUDIO

Microprocessor

Fig. 7-2-1

7-3

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6 dB

VOUT1

YIN1

6 dB

0 dB

37 YOUT1

35 TRAP1

0 dB

6 dB

39 COUT1

29 CIN1

6 dB

23 VOUT2

21 YOUT2

24 TRAP2

6 dB

0 dB

6 dB

19 COUT2

17 VOUT3

6 dB

38 Vcc

6 dB

30 GND

BIAS

36 BIAS

LTV

LEV

LV1

LV2

LV3

33 LOUT1

32 ROUT1

22 LOUT2

20 ROUT2

18 LOUT3

6 dB

16 ROUT3

6 dB

RTV

REV

RV1

RV2

RV3

13 SCL

14 SDA

15 ADR

48 S1

Logic

6 S2

12 S3

28 MUTE

Fig. 7-2-2 Internal block diagram of CXA1855Q

7-4

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7-3. Video Demodulation Block

Table 7-3-1 Terminal function of TC9090AN

No.

7-3-1. Y/C Separation Circuit

Name

Function

This circuit separates Y and C signals from a composite

video signal. Fig. 7-3-1 shows the pin configuration of

TC9090AN and Fig. 7-3-2 shows the block diagram.

ADC bias

ADC GND

Video input

ADC VDD

ADC bias

REFH

SS1

ADIN

The composite video signal enters pin 3. A fsc (3.58/

4.43 MHz) developed from the video/color IC enters pin

19 and is converted into a 4fsc of the drive clock

frequency inside the IC. The composite video signal

entered is processed at a rate of the clock frequency of

the IC and output as Y and C signal.

DD1

REFL

BIAS1

P/S

Selection function control

SDA

I C bus clock input

SCL

I C bus data input, check output

RESET

TEST1

TEST2

KILLER

PLLSEL

I C bus reset

est terminal

VREFH

VSS1

ADIN

V^DD1

VREFL

BIAS1

P/S

28 V^SS4

27 VDD4

26 VREF1

25 YOUT

24 BIAS2

23 C^OUT

22 BIAS3

21 2/1V^DD

20 VFIL

19 CKIN

18 V^DD2

17 VSS2

16 VSS3

15 VDD3

Test terminal

Clock killer switch

Selection input clock

Digital VDD

Analog GND

PLL GND

DD3

SS3

SS2

DD2

SDA

PLL VDD

SCL

CKIN

VFIL

Clock input

VCO filter

RESET 10

TEST1 11

TEST2 12

KILLER 13

PLLSEL 14

2/1 V

Line memory bias

DAC bias

BIAS3

C output

OUT

BIAS2

DAC bias

OUT

REF1

DD4

SS4

Y output

DAC bias

Fig. 7-3-1 Pin configuration of TC9090AN

DAC VDD

DAC GND

LINE

MEMORY

VERTICAL EDGE

ENHANCE CIRCUIT

Composite

video signal

CORING

CIRCUIT

ADC

8 bits

PEDESTAL

CLIP

YDAC

8 bits

output

CLAMP

COLOR KILLER CIRCUIT

BPF

4.43 MHz NTSC

BPF

DYNAMIC

COMB

FILTER

1 LINE DOT

IMPROVE

CIRCUIT

output

CDAC

8 bits

BPF

I²C BUS

Clock 19

4 FSC

PLL

Bus

Fig. 7-3-2 Block diagram of TC9090AN

7-5

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7-3-2. Video/Color Circuit

Fig. 7-3-4 shows the pin configuration of TDA9141 and

Fig. 7-3-5 shows the block diagram of TDA9141. Fig. 7-

3-6 shows the pin configuration of TDA4665T and Fig.

7-3-7 shows the block diagram of TDA4665T.

The video/color circuit consists of two ICs, QV005

(TDA9141: NTSC/PAL/SECAM DECODER), QV006

(TDA4665T: BASE BAND DELAY LINE), and supports

each system of NTSC, PAL and SECAM.

Color difference signal

-(R-Y)

32 SECAM reference

31 Second crystal

30 Reference crystal

29 CPLL

Color difference signal

-(B-Y)

Uin

12 11

16 14

Vin

SCL

SDA

28 Filter reference

27 Analog ground

26 Y/CVBS in

25 Cin

TDA4665T

(1H DL IC)

Supply

Digital supply decoupling

Digital ground

24 HPLL

Sand castle 10

VA 11

23 Fscomb

22 Address in / CVBS out

21 R

Sand castle pulse

Yout 12

Vout 13

20 G

Uout 14

19 B

I / O port 15

O port / LLC 16

18 F

17 CLP / HA

TDA9141

(NTSC/PAL/SECAM)

Fig. 7-3-4 Pin configuration of TDA9141

Fig. 7-3-3

Vertical acquisition

synchronization pulse

GREEN

input

Chrominance

U input

Clamping pulse/

Serial data

input/output

Serial clock

input

Horizontal

PLL filter

Sand castle

output

HA synchronization

pulse input/output

Fast switch

select input

Chrominance

voltage input

RED

input

BLUE

input

21 20 19

Chrominance

output

Chrominance

output

Address

input

(CVBS output)

CBUS

TIMING

GENERATOR

VERTICAL

SYNC

MATRIX

SWITCH

INTERFACE

CLP

Luminance output

Input/output

port

STM

LCA

Output port/

line-locked

clock output

SYNC

SEPARATOR

IDENTIFI-

CATION

HORIZONTAL

PLL

TDA9141

SECAM reference

decoupling

Chrominance

input

SECAM

DEMODU-

LATOR

Chrominance

outputs

CHROMINANCE

SWITCH

CLOCHE

FILTER

TUNING

ACC

SWITCH

Filter reference

decoupling

CHROMI-

NANCE

BANDPASS

PAL/NTSC

DEMODU-

LATOR

Luminance/

CVBS input

DELAY

PLL

TRAP

HUE

Digital

supply

decoupling

FSC

BUFFER

BIAS

Analog Digital

ground ground

Positive supply

PLL

loop filter

Reference

crystal input crystal

input

Second

Comb filter

status input/output

Fig. 7-3-5 Block diagram of TDA9141

7-6

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TDA9141 has two input terminals for the composite

video/Y signal (pin 25) and C signal (pin 26), and each

Table 7-3-2 Terminal function of TDA4665T

Pin No.

Name

Function

of the signals is automatically identified through I C-

+5V power supply for

digital block

BUS control.

MED849

N.C.

GND2

I.C.

Not used

i(R-Y)

GND (0V) for digital block

Internal connection

Sandcastle pulse input

Not used

N.C.

GND2

I.C.

SAND

N.C.

I.C.

i(B-Y)

Internal connection

N.C.

I.C.

TDA4665

+5V power supply for

analog block

VP1

SAND

N.C.

I.C.

o(B-Y)

GND (0V) for analog

block

GND1

o(R-Y)

± (R–Y) output signal

± (B–Y) output signal

Not used

o(R-Y)

GND1

o(B-Y)

N.C.

I.C.

i(B-Y)

± (B–Y) input signal

Not used

N.C.

Fig. 7-3-6 Pin configuration of TDA4665T

± (R–Y) input signal

i(R-Y)

SIGNAL

CLAMPING

(R-Y)

SAMPLE

AND

HOLD

LINE

MEMORY

Color difference

input signals

Pre-amplifiers

Addition

stages

Output

buffers

Color difference

Output signals

SIGNAL

CLAMPING

(B-Y)

SAMPLE

AND

HOLD

LINE

MEMORY

analog supply

N.C.

3 MHz shifting clock

TDA4665

FREQUENCY

PHASE

DETECTOR

13 N.C.

15 N.C.

DIVIDER

BY 192

SANDCASTLE

DETECTOR

Sand castle

pulse input

DIVIDER

6 MHz

CCO

I.C.

Digital supply

GND 1

GND

MED848

Fig. 7-3-7 Block diagram of TDA4665T

7-3-3. Luminance (Y) Signal Process Circuit

(b) For a NTSC/PAL (with burst signal) input (Y/C-sepa-

rated signals), the burst signal trap circuit is bypassed.

It passes through a delay circuit for a phase match-

ing to the color signal.

The processing method differs as follows depending on

type of the signal entered.

(a) For a SECAM input, it passes through a burst signal

trap circuit.

trap circuit and the delay circuit are bypassed to per-

form a stable color killer operation.

7-7

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MED757

18 GND1

7-3-4. Color Signal Process Circuit

The color signal is level adjusted in the ACC (automatic

color control) circuit, corrected in passing through a

band pass circuit in the NTSC/PAL system, or a bell filter

correction is carried out in the SECAM system, and then

enters the color demodulation circuit.

SAND

i(R-Y)

i(Y)

The input burst signal is locked with a crystal oscillator

frequency (3.58 MHz/4.43 MHz) in the PLL circuit and

then demodulated into color difference signals after a

tint adjustment (in the NTSC system). The demodulation

for the SECAM signal is carried out using a PLL circuit.

o(R-Y)

N.C.

REF

CLP2

TDA4672

o(R-Y)

CLP1

The demodulated color difference signals are output

through low pass filters, delayed by 1H in passing

through TDA4665T, fed to TDA9141 again and directly

output.

o(Y)

i(B-Y)

GND2

SDA

COR

SCL

7-3-5. Picture Sharpness Correction Circuit

The picture sharpness is carried out by QV007,

TDA4672. Fig. 7-3-8 shows the pin configuration of

TDA4672 and Fig. 7-3-9 shows the block diagram.

Fig. 7-3-8 Pin configuration of TDA4672

Table 7-3-3 Terminal function of TDA4672

Picture sharpness correction frequency is set to 2.6 MHz.

No.

Name

Function

Positive power supply

Capacitor for delay time control

± (R–Y) color difference input signal

± (R–Y) color difference output signal

Not used

i(R–Y)

o(R–Y)

N.C.

± (B–Y) color difference output signal

± (B–Y) color difference input signal

GND 2 (0V)

o(B–Y)

i(B–Y)

GND2

SDA

I C bus data line

10 SCL

I C bus clock line

Magnetic core capacitor

Delay luminance output signal

Black level clamp capacitor 1

Black level clamp capacitor 2

Reference voltage capacitor

Luminance input signal

Sandcastle pulse input

GND 1 (0V)

COR

o(Y)

CLP1

CLP2

REF

i(Y)

17 SAND

18 GND1

7-8

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Sand castle

pulse

SDA

SCL

= 5V to 8V

100 nF

SAND CASTLE PULSE

DETECTOR

C • BUS

C • BUS RECEIVERS

delay

REF

Sand castle

5V / 12V

Coring

on / off frequency

Peaking

GENERATION

BK.H+V

DELAY TIME

CONTROL

REF

CORING

5 MHz

BLACK LEVEL

CLAMP

100

-0.5

100 nF

2.6 MHz

CORING

REF

100 nF

Control signal

5 MHz

C • BUS

2.6 MHz

PEAKING

C • BUS

BLACK

LEVEL

CLAMP

BLACK

LEVEL

CLAMP

450

180

100

100 nF

REF

TDA4672

-(R-Y)

-(B-Y)

-(R-Y)

-(B-Y)

MED758

Fig. 7-3-9 Block diagram of TDA4672

7-3-6. RGB Demodulation

FSW

SCL

SDA

The demodulation from Y and color difference signals to

RGB signals is carried out by QV008, TDA4780. Fig. 7-

3-10 shows the pin configuration of TDA4780 and Fig.

7-3-11 shows the block diagram. The TDA4780 performs

the RGB demodulation and adjusts color, contrast, and

brightness.

YHUE

-(B-Y)

-(R-Y)

TDA4780

GND

POST

FSW

PDL

15 BCL

Fig. 7-3-10 Pin configuration of TDA4780

7-9

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Table 7-3-4 Terminal function of TDA4780

No.

Name

FSW

Function

No.

Name

Function

High speed switch 2 input

Red input 2

15 BCL

17 CL

Equal beam current limit input

Memory capacitor for peak limit

PDL

Green input 2

Memory capacitor for leakage current

compensation

Blue input 2

Memory capacitor for peak dark

Cut-off measurement input

Blue output

POST

Power supply voltage

Color difference input – (B–Y)

Color difference input – (R–Y)

Luminance input

GND

19 CI

–(B–Y)

–(R–Y)

Blue cut-off memory capacitor

Green output

GND

Green cut-off memory capacitor

Red output

Red input 1

Green input 1

Red cut-off memory capacitor

Y output/hue adjustment output

Blue input 1

26 YHUE

27 SDA

28 SCL

13 FSW

14 SC

High speed switch 1 input

Sandcastle pulse input

I C bus serial data input/check output

I C bus serial clock input

FSW1 FSW2

Peak drive

limiting strage

P-BV

Average

beam

current

limiting

Peak dark

storage

YHUE

Y-output

200

hue adjust

output

1 µF

input

PEAK DRIVE

LIMITER

ABSOLUTE LEVEL

AVERAGE

BEAM

CURRENT

LIMITING

10 nF

YEXH

10 nF

RELC

SUPPLY

TDA4780

INPUT

PEAK DRIVE

LIMITER

CUT-OFF RELATED

MINIMUM

DETECTOR

HUE

ADJUST

BAND GAP

REFERENCE

10 nF

TCPL RELC

UGAP

10 nF

VOLTAGE

COMPARATOR

VOLTAGE

COMPARATOR

WHITE

POINT

ADJUST

OUTPUT

BUFFER

SELECTOR

gamma

Y-MATRIX

ADAPTIVE

BLACK

GAMMA

BLANK MP

WHITE

POINT

ADJUST

-(B-Y)

10 nF

47 nF

PAL/SECAM

COLOR

DIFFERENCE

MATRIX

SATURATION

ADJUST

CONTRAST

ADJUST

BRIGHTNESS

ADJUST

-(B-Y)

ADBL

OUTPUT

BUFFER

NTSC

R-Y

G-Y

B-Y

0.45V

1.43V

MATRIX

BLANK MP

MOD2

NMEN

WHITE

POINT

ADJUST

BLUE

OUTPUT

BUFFER

STRETCH

BLST

BLANK

DATA

REGISTERS

CONTROL REGISTERS

DIGITAL ANALOG CONVERTERS

CUT-OFF

CONTROL

OUTPUT

CLAMP

Leakage and

cut-off

UGAP

BREN

C-BUS

current input

RECEIVER

TDA4780

SC5

1ST AND 2ND

SWITCH-ON

DELAY

TIMING

GENERATOR

(H)

SAND CASTLE

DETECTOR

LEAKAGE

CURRENT

a2 ki

DELOF

COMPARATOR

UGAP

220 nF 220 nF 220 nF

330 nF

Sand castle input

SCL

SDA

Leakage storagee

Cut-off storage

C-bus

Fig. 7-3-11 Block diagram of TDA4780

7-10

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7-3-7. Audio Circuit

Fig. 7-3-12 shows the audio circuit block diagram.

Signal path from the QV001 to the LINE OUT terminal

is: QV001 ® transistor buffer ® LINE OUT terminal.

Signal path from the QV001 to the speaker is as follows.

The audio signal developed from the QV001 becomes

one signal with its L and R signal components mixed.

The mixed audio signal enters the electrical volume IC

QA01 (M5222FP) and the output level is controlled

within a range of about 0 dB to –80 dB by an external

DC voltage (DAC). The audio signal thus controlled by

the IC QA01 is fed to the speaker amplifier IC QA02

(TDA7056A) and amplified by about 36 dB to drive the

speaker.

VIDEO

QV001

INPUT SELECTOR

CXA1855Q

RGB

LINEOUT

BUFFER

QA01

M5222FP

VOLUME

MUTE

DAC

VOL / MUTE

CXA1315M

QA02

TDA7056A

SPEAKER

1.5W

SOUND OUT

Fig. 7-3-12 Audio circuit block diagram

7-11

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7H-D4.(CSR)GanBd VSDigsniganlaAlsmarpe lailfsiocsawtiiotcnheSdeicnttihoensame

Fig. 7-4-1 Block diagram of M52348FP

way as described above. This IC provides the exclusive

7-4-1. RGB Signal Switch Circuit

output terminal for SYNC/G.

The RGB input signals and the video signal demodu-

The RGB signals developed enter the RGB amplification

lated into RGB signals are switched by QB011 (Analog

circuit via buffers, and the HD (CS), VD, SYNC/G signals

SW: M52348FP). The block diagram of QB011 is shown

enter the sync signal process circuit.

in Fig. 7-4-1.

Vcc

OUTPUT

R OUT

G OUT

B OUT

0.01µ

G OUT (for Sync on G)

H OUT

V OUT

47µ

0.01µ

25 24

0.01µ

RIN1

GIN1

BIN1

HIN1

VIN1

RGB

input

RIN2

GIN2

BIN2

HIN2

VIN2

Demodulation

VIDEO

RGB

High : Demodulation

VIDEO

Low : RGB input

7-4-2. Sync Signal Process Circuit

7-12

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The sync signal process circuit is applicable to the HD,

VD, CS (composite sync), SYNC/G signals. HD (CS),VD

and G signals developed from QB011 enter the sync

separation IC (QB012: M52347FP). The sync separation

priority of the sync separation IC is; HD, VD, CS and

SYNC ON G in this order.

7-4-3. RGB SignalAmplifier Section

The RGB signal processing section employs a wide band

RGB signal IC applicable to the XGA signal. Fig. 7-4-3

shows a block diagram of QB024 (M52320SP). The

control items of the IC are five items; main contrast,

brightness and sub contrast for each RGB.

The HD and VD signals sync-separated enter the buffers

QB019 and QB020 (TC7S08F) and the outputs are sent

to the digital PC board.

The brightness and main contrast controls are provided

for the user adjustment, and the sub contrast are provided

to equal the R, G, B levels when entering A/D converter

of the digital PC board.

RGB IN

QB019

TC7S08F

QB011

M52348FP

VDD

+5V

Q512

TC74HCT240AF

HD/CS

RGB/HD

RGB/VD

QB012

M52347FP

QB020

TC7S08F

11 VIDEO/R

13 VIDEO/G

G IN

H/CS

G OUT 25

H OUT

V^DD

17 VIDEO/HD V OUT 21

VIDEO/B

+5V

QV005

TDA9141

V IN

VIDEO/VD

Fig 7-4-2

SUB OSD

(G)

OUTPUT (R)

HOLD (R)

GND2 (R)

OUTPUT (R)

HOLD (B)

GND2 (B)

ADJUST (G)

CC2

MAIN

OSD ADJUST

SUB OSD

ADJUST (B)

MAIN

BRIGHTNESS

ADJUST (R)

(R)

(B)

OUTPUT (G)

HOLD (G)

GND2 (G)

CC2

BRIGHTNESS

AMP

HOLD

AMP

HOLD

AMP

HOLD

OSD MIX

BLANKING

OSD MIX

BLANKING

OSD MIX

BLANKING

CLAMP

CONTRAST

CLAMP

CONTRAST

CLAMP

CONTRAST

INPUT (B)

BLK IN

INPUT (R)

OSD IN (R)

(G)

SUB CONTRAST

(G)

GND2 (G)

OSD IN (B)

MAIN

CONTRAST

CC1

(R) SUB CONTRAST GND2 (R)

(R)

INPUT (G)

GND IN (G)

(B) SUB CONTRAST GND2 (B)

(B)

CP IN

CC1

Fig. 7-4-3

7-13

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7-5. Microprocessor Interface

RGB/VIDEO SW, Audio mute/volume adjustment, etc.

are controlled in QV045 (CXA1315M). Further, using

camera or not, camera zoom and focus adjustment

controls are carried out in QV057.

The peripheral block diagram of the microprocessor

shows in Fig. 7-5-1. All kinds of control such as signal

SW, etc. are carried out by the I C of microprocessor. The

level control of RGB signal process IC (QB024:

M52320SP) and the sync polarity information of the

sync process IC (QB012: M52347FP) are carried out in

QB025 (CXA1315M). Refer to table 7-5-1 for the logic

about the polarity information of sync signal.

H. STATE

V. STATE

QB025

CXA1315M

M52347FP

From

Vcc

SW1

SW0

Microprocessor

H. POL

V. POL

SCL

SDA

R SUB CONTRAST

G SUB CONTRAST

B SUB CONTRAST

MAIN CONTRAST ADJUST

BRIGHT ADJUST

SDA

DAC4

DAC3

DAC2

DAC1

DAC0

GND

SAD2

SAD1

SAD0

SW3

SW2

M52320SP

QV045

CXA1315M

QV057

M62320FP

Vcc

SW1

SW0

RGB/VIDEO

CS0

SCL

CS1

SCL

SDA

DAC4

DAC3

DAC2

DAC1

DAC0

GND

CS2

Vcc

SDA

FOCUS +

FOCUS -

ZOOM +

ZOOM -

SAD2

SAD1

SAD0

SW3

SW2

FIL/SW

VDET

SYUSEN

CAMON1

PV013

MUTE

VOL

GND

ENABLE

SELECT

Fig. 7-5-1

7-14

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Table 7-5-1

QB012 (M52347FP) Input status

QB025 (CXA1315M)

SW1 (Pin 1) SW2 (Pin 9)

Pin 6: HD. COMP

Pin 8: VD

NON

SW0 (Pin 2)

SW3 (Pin 10)

HD. COMP. (POS.)

HD. COMP. (NEG.)

VD (POS.)

VD (NEG.)

NON

VD (POS.)

HD.HD. COMP.

(NEG.)

VD (NEG.)

NON

VD (POS.)

VD (NEG.)

QB012 (M52347FP) output terminal

V. POL (Pin 19) V. POL (Pin 18) H. STATE (Pin 1) V. STATE (Pin 2)

7-15

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8-1-4. Power Supply Circuit

8. CCD CAMERA CIRCUIT

(For TLP511)

The power supply circuit generates DC voltages (+15V,

+5V, +3.3V, –8.2V) necessary to the camera signal

process and power supply voltage (+9V, +5V) for lens.

Lens +9V, develops the power supply voltage (+9V)

entered from outside directly and for lens +5V, input +9V

is developed through the regulator IC (Q801).

8-1. Outline

The camera section of the unit employs the color board

camera with 3 times zoom lens. The camera video circuit

is assembled in one PC board and composed of the CCD

and drive circuit, pre-amp and AD converting circuit

(CDS, AGC and AD), video signal process circuit (DSP,

MICON) and power supply circuit.

The signal process +5V develops the power supply

voltage (+5V) entered from outside directly and the

signal process +3.3V, the input +5V is developed through

the regulator IC (Q802). The DC voltage of +15V, –8.2V

are developed from the constant voltage circuit through

the change pump circuits of Q804 – Q806.

Fig. 8-1-1 shows a block diagram of CCD camera circuit.

8-1-1. CCD and Drive Circuit

The CCD (Q101) circuit employs 1/3 inch 480,000 pixels

IT-CCD. The horizontal transmission pulse (H1, H2 and

RG) and vertical transmission pulse (øV1 – øV4 and

SUB) are supplied through the drive signal generation

circuit and vertical drive IC (Q103 and Q202) inside DSP

(Q203) by 28.5 MHz clock signal output from the

oscillator (Z201).

8-1-2. Pre-amp and AD Coversion Circuit

(CDS, AGC, AD)

The video signal developed from CCD (Q101) enters the

pre-amp IC (Q201) through the buffer (Q102).

After the signal is processed the noise reduction process

(CDS) inside the IC and amplified (AGC), the signal is

converted to AD, and then output as 10 bits digital data.

8-1-3. Video Signal Process Circuit

(DSP, MICON)

The video signal, which became 10 bits digital data,

enters the DSP (Q203) for video signal process. After the

signal is separated into the luminance and color signals,

the signal process is carried out on the luminance and

color signals respectively and DA-converted.

The luminance signal adds the sync signal and passes

through 7 MHz low pass filter. The color signal is

developed through the video driver IC (Q206) after

passing 4.43 MHz band pass filter.

All kinds of parameters on DSP (Q203) are set up by the

microprocessor (Q303) and picture quality adjustment,

etc. are carried out.

These parameters are memorized in the E PROM

(Q306). Also, the zoom, focus, etc. controls of lens are

carried out by communicating with the external device

through RS-232C driver IC (Q304).

8-1

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Fig. 8-1-1 CCD camera circuit block diagram

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CI004 prevents a rapid increase of the collector current

of QI003 before the fluorescent lamp turns on.

9. FLUORESCENT LAMP

INVERTER CIRCUIT

(For TLP511)

Also, RI009 is a protective posistor to prevent QI003

from generating temperature more than 100°C.

9-1. Operating Description

The specification of LI002 is shown in Figs. 9-1-1, 9-1-2

and Table 9-1-1.

The base current at start-up passes through QI002,

RI003, RI004, RI009 and then flows into the base of

QI003. QI002 works as a ON/OFF switch for start-up

operation and turns ON when the base voltage develops

“L”. When the base voltage develops “H” (12V), QI002

turns off. A current flows into QI001 and RI002 only

when the start-up operation is carried out, thus improves

the start-up characteristics by increasing the base current

of QI003. Especially, this circuit takes effective under

the low temperature status where the start-up operation

is likely to difficult.

Dot Mark : Polarity

NS1

NP1

NP2

NS2

NS3

(Primary side)

(Secondary side)

DI003, DI004 and DI005 connected to QI003 base

prevents an inverse break down overvoltage at QI003

Fig. 9-1-1 Winding specification

Table 9-1-1

. DI003 and DI004 are connected in series to prevent

the overheat at short-circuiting.

When the resistor value of RI006 is small, heat genera-

tion of QI003 lowers. However, if the value is too small,

the current of DI003, DI004 and DI005 in continuity

becomes large.

Winding

method

No. Coil

Terminal Turns

Wire

NP1

NP2

NP3

NP1

5 – 4

3 – 2

9 – 8

10 – 9

7 – 6

UEW 0.3

UEW 0.2

FIT

SPACE

FIT

144

DI002 increases only the base current of QI003 when it

FIT

turns on and reduces the V (sat) of QI003 to lower the

FIT

heat generation. RI005 works as a current limitation

resistor of DI002.

Weight : (9)g

UNIT : mm

17.0 max.

Lot No. 2 Month

Year

3.0 min.

(5.0 mm typ.)

9-φ0.7

20.0 max.

All products must be impregnated by varnish.

3.81 0.1

12.7 0.3

TOP VIEW

9-φ1.2

Fig. 9-1-2 Appearance and dimensions

9-1

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70 kHz

CI005 and CI006 are capacitors to stabilize the fluores-

cent lamp discharging current. After the discharging

starts, CI005 and CI006 limit the flow of the current

31V

QI003

Collector

voltage

with the reactance (X = 1/wc) of CI005 and CI006.

Before the fluorescent lamp turns on, the collector

pulse of QI007 is 70 – 80 V(p-p). The voltage is

stepped up to 420 – 480 V(p-p) by LI002 and applied to

the fluorescent lamp. When a filament is warmed, the

discharging starts and the collector voltage of QI003

becomes approx. 30 V(p-p). The fluorescent tube

voltage at turning on is approx. 120 V(p-p).

1.5A

Collector

current

Fig. 9-1-3

ARM SW works as a ON/OFF switch for the camera

power supply. When ARM SW turns on, the power is

supplied to the camera.

70 kHz

+30V

The waveforms of each section at operation is shown in

Figs. 9-1-3 and 9-1-4.

Fluorescent

lamp

voltage

– 80V

+0.16A

Fluorescent

lamp

current

– 0.22A

9-2. Troubleshooting

9-2-1. Fluorescent does not turn on

Fig. 9-1-4

Fluorescent lamp

does not turn on.

Replace

fluorescent lamp.

12V : between pins

5 and 7 of PM01.

YES

Higher than 10V.

Check power

supply unit.

QI002 base.

Lower than 3V.

Pulse higher than

25 V(p-p) is developed at

QI003 collector.

Check fluorescent

lamp ON/OFF SW

(SM005)

and ARM SW.

YES

Check secondary

side of LI002.

Check primary

side of LI002.

Fig. 9-2-1

9-2

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TOS

IBA AMERICA CONSUMER PRODUCTS, INC.

NATIONAL SERVICE DIVISION

1420-B TOSHIBA DRIVE

LEBANON, TN 37087

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