Texas Instruments Stereo System TMS320C6202 User Manual
TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
Highest Performance Fixed-Point Digital  
Signal Processor (DSP) TMS320C6202  
– 4-ns Instruction Cycle Time  
– 250-MHz Clock Rate  
– Eight 32-Bit Instructions/Cycle  
– 2000 MIPS  
32-Bit External Memory Interface (EMIF)  
– Glueless Interface to Synchronous  
Memories: SDRAM or SBSRAM  
– Glueless Interface to Asynchronous  
Memories: SRAM and EPROM  
Four-Channel Bootloading  
VelociTI Advanced Very Long Instruction  
Word (VLIW) ’C6200 CPU Core  
– Eight Highly Independent Functional  
Units:  
Direct-Memory-Access (DMA) Controller  
With an Auxiliary Channel  
Flexible Phase-Locked-Loop (PLL) Clock  
Generator  
– Six ALUs (32-/40-Bit)  
32-Bit Expansion Bus  
– Glueless/Low-Glue Interface to Popular  
PCI Bridge Chips  
– Glueless/Low-Glue Interface to Popular  
Synchronous or Asynchronous  
Microprocessor Buses  
– Two 16-Bit Multipliers (32-Bit Result)  
– Load-Store Architecture With 32 32-Bit  
General-Purpose Registers  
– Instruction Packing Reduces Code Size  
– All Instructions Conditional  
Instruction Set Features  
– Byte-Addressable (8-, 16-, 32-Bit Data)  
– 32-Bit Address Range  
– 8-Bit Overflow Protection  
– Saturation  
– Bit-Field Extract, Set, Clear  
– Bit-Counting  
– Normalization  
– Master/Slave Functionality  
– Glueless Interface to Synchronous FIFOs  
and Asynchronous Peripherals  
Three Multichannel Buffered Serial Ports  
(McBSPs)  
– Direct Interface to T1/E1, MVIP, SCSA  
Framers  
– ST-Bus-Switching Compatible  
– Up to 256 Channels Each  
– AC97-Compatible  
– Serial-Peripheral-Interface (SPI)  
Compatible (Motorola )  
3M-Bit On-Chip SRAM  
– 2M-Bit Internal Program/Cache  
– Two 128K-Byte Blocks Offer Improved  
Concurrency  
Block 0: 128K Bytes Memory-Mapped  
Block 1: 128K Bytes Direct-Mapped  
Cache/Memory-Mapped  
Two 32-Bit General-Purpose Timers  
†
IEEE-1149.1 (JTAG )  
Boundary-Scan-Compatible  
– 1M-Bit Dual-Access Internal Data  
(128K Bytes)  
352-Pin BGA Package (GJL Suffix)  
384-Pin BGA Package (GLS Suffix)  
– Two 64K-Byte Blocks Offer Improved  
Concurrency  
0.18-µm/5-Level Metal Process  
– CMOS Technology  
3.3-V I/Os, 1.8-V Internal  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
VelociTI is a trademark of Texas Instruments Incorporated.  
Motorola is a trademark of Motorola, Inc.  
†
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.  
Copyright 1999, Texas Instruments Incorporated  
ADVANCE INFORMATION concerns new products in the sampling or  
preproduction phase of development. Characteristic data and other  
specifications are subject to change without notice.  
1
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
description  
The TMS320C62x DSPs (including the TMS320C6202 device) are the fixed-point DSP family in the  
TMS320C6000 platform. The TMS320C6202 (’C6202) device is based on the high-performance, advanced  
VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI ), making this  
DSP an excellent choice for multichannel and multifunction applications.  
With performance of up to 2000 million instructions per second (MIPS) at a clock rate of 250 MHz, the ’C6202  
offers cost-effective solutions to high-performance DSP programming challenges. The ’C6202 DSP possesses  
the operational flexibility of high-speed controllers and the numerical capability of array processors. This  
processor has 32 general-purpose registers of 32–bit word length and eight highly independent functional units.  
The eight functional units provide six arithmetic logic units (ALUs) for a high degree of parallelism and two 16-bit  
multipliers for a 32-bit result. The ’C6202 can produce two multiply-accumulates (MACs) per cycle for a total  
of 500 million MACs per second (MMACS). The ’C6202 DSP also has application-specific hardware logic,  
on-chip memory, and additional on-chip peripherals.  
The ’C6202 includes a large bank of on-chip memory and has a powerful and diverse set of peripherals.  
Program memory consists of two 128K-byte blocks, with one block configured as memory-mapped program  
space, and the other block user-configured as cache or memory-mapped program space. Data memory  
consists of two 64K-byte blocks of RAM. The peripheral set includes three multichannel buffered serial ports  
(McBSPs), two general-purpose timers, an expansion bus (XB) that offers ease of interface to synchronous or  
asynchronous industry-standard host bus protocols, and a glueless external memory interface (EMIF) capable  
of interfacing to SDRAM or SBSRAM and asynchronous peripherals.  
The ’C6202 has a complete set of development tools which includes: a new C compiler, an assembly optimizer  
to simplify programming and scheduling, and a Windows debugger interface for visibility into source code  
execution.  
device characteristics  
Table 1 provides an overview of the ’C6202 DSP. The table shows significant features of each device, including  
the capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count.  
Table 1. Characteristics of the ’C6202 Processors  
CHARACTERISTICS  
DESCRIPTION  
Device Number  
TMS320C6202  
2 Mbit Program Memory  
(organized as 2 blocks)  
1 Mbit Data Memory  
On-Chip Memory  
Peripherals  
(organized as 2 blocks)  
3 Multichannel Buffered Serial Ports (McBSP)  
2 General-Purpose Timers  
External Memory Interface (EMIF)  
Expansion Bus (XB)  
Cycle Time  
4 ns  
27 mm × 27 mm, 352-Pin BGA (GJL)  
18 mm × 18 mm, 384-Pin BGA (GLS)  
Package Type  
1.8 V Core  
3.3 V I/O  
Nominal Voltage  
TI is a trademark of Texas Instruments Incorporated.  
Windows is a registered trademark of the Microsoft Corporation.  
3
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
functional block diagram  
Timers  
Interrupt Selector  
Data Memory  
Peripheral  
McBSPs  
Bus  
Controller  
XB Control  
DMA Control  
EMIF Control  
Data Memory  
Controller  
DMA  
Controller  
Expansion Bus (XB)  
Interface  
PLL  
CPU  
EMIF  
Power  
Down  
Program Memory Controller  
Program Memory/Cache  
Boot-  
Config.  
4
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
CPU description  
The CPU fetches VelociTI advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight  
32-bit instructions to the eight functional units during every clock cycle. The VelociTI VLIW architecture features  
controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The  
first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the  
previous instruction, or whether it should be executed in the following clock as a part of the next execute packet.  
Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length  
execute packets are a key memory-saving feature, distinguishing the ’C6200 CPU from other VLIW  
architectures.  
The CPU features two sets of functional units. Each set contains four units and a register file. One set contains  
functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files  
eachcontain1632-bitregistersforatotalof32general-purposeregisters. Thetwosetsoffunctionalunits, along  
with two register files, compose sides A and B of the CPU (see Figure 1 and Figure 2). The four functional units  
on each side of the CPU can freely share the 16 registers belonging to that side. Additionally, each side features  
a single data bus connected to all the registers on the other side, by which the two sets of functional units can  
access data from the register files on the opposite side. While register access by functional units on the same  
side of the CPU as the register file can service all the units in a single clock cycle, register access using the  
register file across the CPU supports one read and one write per cycle.  
Another key feature of the ’C6200 CPU is the load/store architecture, where all instructions operate on registers  
(as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data  
transfers between the register files and the memory. The data address driven by the .D units allows data  
addresses generated from one register file to be used to load or store data to or from the other register file. The  
’C6200 CPU supports a variety of indirect addressing modes using either linear- or circular-addressing modes  
with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 32 registers. Some  
registers, however, are singled out to support specific addressing or to hold the condition for conditional  
instructions (if the condition is not automatically “true”). The two .M functional units are dedicated for multiplies.  
The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results  
available every clock cycle.  
The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory.  
The 32-bit instructions destined for the individual functional units are “linked” together by “1” bits in the least  
significant bit (LSB) position of the instructions. The instructions that are “chained” together for simultaneous  
execution (up to eight in total) compose an execute packet. A “0” in the LSB of an instruction breaks the chain,  
effectively placing the instructions that follow it in the next execute packet. If an execute packet crosses the  
fetch-packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of  
the current fetch packet is padded with NOP instructions. The number of execute packets within a fetch packet  
can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one  
per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch  
packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units  
for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit  
registers, they can be subsequently moved to memory as bytes or half-words as well. All load and store  
instructions are byte-, half-word, or word-addressable.  
5
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
CPU description (continued)  
Program Memory  
32-Bit Address  
256-Bit Data  
’C62x CPU  
Program Fetch  
Control  
Registers  
Instruction Dispatch  
Instruction Decode  
Data Path A  
Register File A  
Data Path B  
Control  
Logic  
External Memory  
Interface  
Register File B  
Test  
.S1  
.M2  
.M1 .D1  
.D2  
.S2 .L2  
.L1  
Emulation  
Interrupts  
Additional  
Peripherals:  
Timers,  
Serial Ports,  
etc.  
Data Memory  
32-Bit Address  
8-, 16-, 32-Bit Data  
Figure 1. TMS320C62x CPU Block Diagram  
6
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
CPU description (continued)  
src1  
src2  
dst  
long dst  
long src  
.L1  
8
8
32  
ST1  
8
long src  
long dst  
dst  
Register  
File A  
Data Path A  
.S1  
src1  
(A0–A15)  
src2  
dst  
src1  
.M1  
.D1  
src2  
LD1  
dst  
src1  
src2  
DA1  
2X  
1X  
src2  
src1  
dst  
DA2  
.D2  
LD2  
src2  
.M2  
.S2  
src1  
dst  
src2  
Register  
File B  
(B0–B15)  
Data Path B  
src1  
dst  
long dst  
long src  
8
32  
8
ST2  
8
long src  
long dst  
dst  
.L2  
src2  
src1  
Control  
Register  
File  
Figure 2. TMS320C62x CPU Data Paths  
7
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
signal groups description  
CLKIN  
CLKOUT2  
RESET  
NMI  
CLKOUT1  
CLKMODE0  
EXT_INT7  
†
CLKMODE1  
CLKMODE2  
Clock/PLL  
EXT_INT6  
EXT_INT5  
EXT_INT4  
IACK  
†
Reset and  
Interrupts  
PLLV  
PLLG  
PLLF  
INUM3  
INUM2  
INUM1  
INUM0  
TMS  
TDO  
TDI  
IEEE Standard  
1149.1  
(JTAG)  
Emulation  
DMAC3  
DMAC2  
DMAC1  
DMAC0  
TCK  
DMA Status  
TRST  
EMU1  
EMU0  
Power-Down  
Status  
PD  
RSV4  
RSV3  
RSV2  
RSV1  
RSV0  
Reserved  
Control/Status  
†
For GLS devices only  
Figure 3. CPU Signals  
8
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
signal groups description (continued)  
ARE  
AOE  
AWE  
ARDY  
Asynchronous  
32  
ED[31:0]  
Data  
Memory  
Control  
CE3  
CE2  
CE1  
CE0  
Memory Map  
Space Select  
SDA10  
Synchronous  
SDRAS/SSOE  
Memory  
SDCAS/SSADS  
Control  
20  
SDWE/SSWE  
EA[21:2]  
Word Address  
Byte Enables  
BE3  
BE2  
BE1  
BE0  
HOLD  
HOLD/  
HOLDA  
HOLDA  
EMIF  
(External Memory Interface)  
TOUT1  
TINP1  
TOUT0  
TINP0  
Timer 1  
Timer 0  
Timers  
McBSP0  
Transmit  
CLKX0  
FSX0  
DX0  
CLKR0  
FSR0  
DR0  
Receive  
Clock  
McBSP1  
Transmit  
CLKX1  
FSX1  
DX1  
CLKS0  
CLKR1  
FSR1  
DR1  
Receive  
Clock  
McBSP2  
Transmit  
CLKX2  
FSX2  
DX2  
CLKS1  
CLKR2  
FSR2  
DR2  
Receive  
Clock  
CLKS2  
McBSPs  
(Multichannel Buffered Serial Ports)  
Figure 4. Peripheral Signals  
9
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
signal groups description (continued)  
32  
XCLKIN  
XFCLK  
XD[31:0]  
Data  
Clocks  
XBE3/XA5  
XBE2/XA4  
XBE1/XA3  
XBE0/XA2  
Byte-Enable  
Control/  
Address  
XOE  
XRE  
XWE/XWAIT  
XCE3  
XCE2  
I/O Port  
Control  
XRDY  
Control  
XCE1  
XCE0  
XHOLD  
Arbitration  
XHOLDA  
XCS  
XAS  
XCNTL  
XW/R  
XBLAST  
XBOFF  
Host  
Interface  
Control  
Expansion Bus  
Figure 4. Peripheral Signals (Continued)  
10  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
Signal Descriptions  
PIN NO.  
SIGNAL  
NAME  
†
DESCRIPTION  
TYPE  
GJL  
GLS  
CLOCK/PLL  
CLKIN  
C12  
B10  
Y18  
I
Clock Input  
CLKOUT1  
AD20  
O
Clock output at full device speed  
Clock output at half of device speed  
CLKOUT2  
AC19  
AB19  
O
•
Used for synchronous memory interface  
CLKMODE0  
CLKMODE1  
CLKMODE2  
B15  
–
B12  
A9  
I
I
I
Clock mode selects (Note: CLKMODE1 and CLKMODE2 selects are for GLS devices only)  
Selects whether the CPU clock frequency = input clock frequency x4 or x1  
•
–
A14  
C11  
C12  
A11  
‡
§
A
§
A
§
A
PLLV  
D13  
D14  
C13  
PLL analog V connection for the low-pass filter  
CC  
‡
PLLG  
PLL analog GND connection for the low-pass filter  
PLL low-pass filter connection to external components and a bypass capacitor  
JTAG EMULATION  
PLLF  
TMS  
TDO  
TDI  
AD7  
AE6  
AF5  
AE5  
AC7  
AF6  
AC8  
Y5  
I
JTAG test-port mode select (features an internal pullup)  
JTAG test-port data out  
AA4  
Y4  
O/Z  
I
I
I
JTAG test-port data in (features an internal pullup)  
JTAG test-port clock  
TCK  
AB2  
AA3  
AA5  
AB4  
TRST  
EMU1  
EMU0  
JTAG test-port reset (features an internal pulldown)  
I/O/Z  
I/O/Z  
Emulation pin 1, pullup with a dedicated 20-kΩ resistor  
Emulation pin 0, pullup with a dedicated 20-kΩ resistor  
RESET AND INTERRUPTS  
Device reset  
RESET  
NMI  
K2  
L2  
J3  
I
I
Nonmaskable interrupt  
K2  
•
Edge-driven (rising edge)  
EXT_INT7  
EXT_INT6  
EXT_INT5  
EXT_INT4  
IACK  
V4  
Y2  
U2  
U3  
W1  
V2  
V1  
R3  
T1  
T2  
T3  
External interrupts  
Edge-driven (rising edge)  
I
•
AA1  
W4  
Y1  
O
O
Interrupt acknowledge for all active interrupts serviced by the CPU  
Active interrupt identification number  
INUM3  
V2  
INUM2  
U4  
V3  
•
•
Valid during IACK for all active interrupts (not just external)  
Encoding order follows the interrupt-service fetch-packet ordering  
INUM1  
INUM0  
W2  
POWER-DOWN STATUS  
PD  
AB2  
Y2  
O
Power-down modes 2 or 3 (active if high)  
†
‡
§
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground  
PLLV and PLLG are not part of external voltage supply or ground. See the clock PLL section for information on how to connect these pins.  
A = Analog Signal (PLL Filter)  
For emulation and normal operation, pull up EMU1 and EMU0 with a dedicated 20-kΩ resistor. For boundary scan, pull down EMU1 and EMU0  
with a dedicated 20-kΩ resistor.  
11  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
Signal Descriptions (Continued)  
PIN NO.  
SIGNAL  
NAME  
†
DESCRIPTION  
TYPE  
GJL  
GLS  
EXPANSION BUS  
XCLKIN  
A9  
B9  
C8  
A8  
I
Expansion bus synchronous host interface clock input  
Expansion bus FIFO interface clock output  
XFCLK  
XD31  
XD30  
XD29  
XD28  
XD27  
XD26  
XD25  
XD24  
XD23  
XD22  
XD21  
XD20  
XD19  
XD18  
XD17  
XD16  
XD15  
XD14  
XD13  
XD12  
XD11  
XD10  
XD9  
O
D15  
B16  
A17  
B17  
D16  
A18  
B18  
D17  
C18  
A20  
D18  
C19  
A21  
D19  
C20  
B21  
A22  
D20  
B22  
E25  
F24  
E26  
F25  
G24  
H23  
F26  
G25  
J23  
G26  
H25  
J24  
K23  
F2  
C13  
A13  
C14  
B14  
B15  
C15  
A15  
B16  
C16  
A17  
B17  
C17  
B18  
A19  
C18  
B19  
C19  
B20  
A21  
C21  
D20  
B22  
D21  
E20  
E21  
D22  
F20  
F21  
E22  
G20  
G21  
G22  
D2  
Expansion bus data  
•
•
Used for transfer of data, address, and control  
Also controls initialization of DSP modes and expansion bus at reset via pullup/pulldown  
resistors  
– XCE[3:0] memory type  
– XBLAST polarity  
– XW/R polarity  
– Asynchronous or synchronous host operation  
– Arbitration mode (internal or external)  
– FIFO mode  
– Little endian/big endian  
– Boot mode  
I/O/Z  
XD8  
XD7  
XD6  
XD5  
XD4  
XD3  
XD2  
XD1  
XD0  
XCE3  
XCE2  
XCE1  
XCE0  
Expansion bus I/O port memory space enables  
E1  
B1  
O/Z  
•
•
Enabled by bits 28, 29, and 30 of the word address  
Only one asserted during any I/O port data access  
F3  
D3  
E2  
C2  
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground  
12  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
Signal Descriptions (Continued)  
PIN NO.  
SIGNAL  
NAME  
†
DESCRIPTION  
EXPANSION BUS (CONTINUED)  
Expansion bus multiplexed byte-enable control/address signals  
TYPE  
GJL  
GLS  
XBE3/XA5  
XBE2/XA4  
XBE1/XA3  
XBE0/XA2  
XOE  
C7  
D8  
C5  
A4  
B5  
C6  
A6  
C7  
B7  
C9  
B6  
B9  
B8  
C4  
B4  
A10  
A2  
B3  
I/O/Z  
•
•
Act as byte enable for host port operation  
Act as address for I/O port operation  
A6  
C8  
A7  
O/Z  
O/Z  
O/Z  
I
Expansion bus I/O port output enable  
XRE  
C9  
Expansion bus I/O port read enable  
XWE/XWAIT  
XCS  
D10  
A10  
D9  
Expansion bus I/O port write enable and host port wait signals  
Expansion bus host port chip-select input  
XAS  
I/O/Z  
I
Expansion bus host port address strobe  
XCNTL  
XW/R  
B10  
D11  
A5  
Expansion bus host control. XCNTL selects between expansion bus address or data register  
Expansion bus host port write/read enable. XW/R polarity selected at reset  
Expansion bus host port ready (active low) and I/O port ready (active high)  
Expansion bus host port burst last–polarity selected at reset  
Expansion bus back off  
I/O/Z  
I/O/Z  
I/O/Z  
I
XRDY  
XBLAST  
XBOFF  
XHOLD  
XHOLDA  
B6  
B11  
B5  
I/O/Z  
I/O/Z  
Expansion bus hold request  
D7  
Expansion bus hold acknowledge  
EMIF – CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY  
CE3  
CE2  
CE1  
CE0  
BE3  
BE2  
BE1  
BE0  
AB25  
AA24  
AB26  
AA25  
Y24  
Y21  
W20  
AA22  
W21  
V20  
Memory space enables  
O/Z  
O/Z  
•
•
Enabled by bits 24 and 25 of the word address  
Only one asserted during any external data access  
Byte-enable control  
W23  
AA26  
Y25  
V21  
•
•
•
Decoded from the two lowest bits of the internal address  
Byte-write enables for most types of memory  
Can be directly connected to SDRAM read and write mask signal (SDQM)  
W22  
U20  
EMIF – ADDRESS  
EA21  
EA20  
EA19  
EA18  
EA17  
EA16  
EA15  
EA14  
EA13  
EA12  
EA11  
J25  
J26  
H20  
H21  
H22  
J20  
J21  
K21  
K20  
K22  
L21  
L20  
L22  
L23  
K25  
L24  
L25  
M23  
M24  
M25  
N23  
P24  
O/Z  
External address (word address)  
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
Signal Descriptions (Continued)  
PIN NO.  
SIGNAL  
NAME  
†
DESCRIPTION  
EMIF – ADDRESS (CONTINUED)  
TYPE  
GJL  
GLS  
EA10  
P23  
R25  
R24  
R23  
T25  
T24  
U25  
T23  
V26  
M20  
M21  
N22  
N20  
N21  
P21  
P20  
R22  
R21  
EA9  
EA8  
EA7  
EA6  
EA5  
EA4  
EA3  
EA2  
O/Z  
External address (word address)  
EMIF – DATA  
ED31  
ED30  
ED29  
ED28  
ED27  
ED26  
ED25  
ED24  
ED23  
ED22  
ED21  
ED20  
ED19  
ED18  
ED17  
ED16  
ED15  
ED14  
ED13  
ED12  
ED11  
ED10  
ED9  
AD8  
AC9  
Y6  
AA6  
AB6  
Y7  
AF7  
AD9  
AC10  
AE9  
AA7  
AB8  
Y8  
AF9  
AC11  
AE10  
AD11  
AE11  
AC12  
AD12  
AE12  
AC13  
AD14  
AC14  
AE15  
AD15  
AC15  
AE16  
AD16  
AE17  
AC16  
AF18  
AE18  
AC17  
AD18  
AF20  
AC18  
AD19  
AF21  
AA8  
AA9  
Y9  
AB10  
Y10  
AA10  
AA11  
Y11  
AB12  
Y12  
I/O/Z  
External data  
AA12  
AA13  
Y13  
AB13  
Y14  
AA14  
AA15  
Y15  
ED8  
ED7  
ED6  
AB15  
AA16  
Y16  
ED5  
ED4  
ED3  
AB17  
AA17  
Y17  
ED2  
ED1  
ED0  
AA18  
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
Signal Descriptions (Continued)  
PIN NO.  
SIGNAL  
NAME  
†
DESCRIPTION  
TYPE  
GJL  
GLS  
EMIF – ASYNCHRONOUS MEMORY CONTROL  
ARE  
AOE  
V24  
V25  
U23  
W25  
T21  
R20  
T22  
T20  
O/Z  
Asynchronous memory read enable  
Asynchronous memory output enable  
Asynchronous memory write enable  
Asynchronous memory ready input  
O/Z  
O/Z  
I
AWE  
ARDY  
EMIF – SYNCHRONOUS DRAM (SDRAM)/SYNCHRONOUS BURST SRAM (SBSRAM) CONTROL  
SDA10  
AE21  
AE22  
AF22  
AC20  
AA19  
AB21  
Y19  
O/Z  
O/Z  
O/Z  
O/Z  
SDRAM address 10 (separate for deactivate command)  
SDRAM column-address strobe/SBSRAM address strobe  
SDRAM row-address strobe/SBSRAM output enable  
SDRAM write enable/SBSRAM write enable  
EMIF – BUS ARBITRATION  
SDCAS/SSADS  
SDRAS/SSOE  
SDWE/SSWE  
AA20  
HOLD  
Y26  
V23  
V22  
U21  
I
Hold request from the host  
HOLDA  
O
Hold-request-acknowledge to the host  
TIMERS  
TOUT1  
TINP1  
TOUT0  
TINP0  
J4  
G2  
F1  
H4  
F2  
F3  
D1  
E2  
O
I
Timer 1 or general-purpose output  
Timer 1 or general-purpose input  
O
I
Timer 0 or general-purpose output  
Timer 0 or general-purpose input  
DMA ACTION COMPLETE STATUS  
DMAC3  
DMAC2  
DMAC1  
DMAC0  
Y3  
V3  
W2  
AA1  
W3  
AA2  
AB1  
AA3  
O
DMA action complete  
MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0)  
CLKS0  
CLKR0  
CLKX0  
DR0  
M4  
M2  
M3  
R2  
P4  
N3  
N4  
K3  
L2  
I
External clock source (as opposed to internal)  
Receive clock  
I/O/Z  
I/O/Z  
I
K1  
M2  
M3  
M1  
L3  
Transmit clock  
Receive data  
DX0  
O/Z  
I/O/Z  
I/O/Z  
Transmit data  
FSR0  
FSX0  
Receive frame sync  
Transmit frame sync  
MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1)  
CLKS1  
CLKR1  
CLKX1  
DR1  
G1  
J3  
H2  
L4  
J1  
J2  
K4  
E1  
G2  
G3  
H1  
H2  
H3  
G1  
I
External clock source (as opposed to internal)  
Receive clock  
I/O/Z  
I/O/Z  
I
Transmit clock  
Receive data  
DX1  
O/Z  
I/O/Z  
I/O/Z  
Transmit data  
FSR1  
FSX1  
Receive frame sync  
Transmit frame sync  
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
Signal Descriptions (Continued)  
PIN NO.  
SIGNAL  
NAME  
†
DESCRIPTION  
TYPE  
GJL  
GLS  
MULTICHANNEL BUFFERED SERIAL PORT 2 (McBSP2)  
CLKS2  
R3  
T2  
R4  
V1  
T4  
U2  
T3  
N1  
N2  
N3  
R2  
R1  
P3  
P2  
I
External clock source (as opposed to internal)  
Receive clock  
CLKR2  
CLKX2  
DR2  
I/O/Z  
I/O/Z  
I
Transmit clock  
Receive data  
DX2  
O/Z  
I/O/Z  
I/O/Z  
Transmit data  
FSR2  
FSX2  
Receive frame sync  
Transmit frame sync  
RESERVED FOR TEST  
RSV0  
RSV1  
RSV2  
RSV3  
RSV4  
L3  
J2  
I
I
Reserved for testing, pullup with a dedicated 20-kΩ resistor  
Reserved for testing, pullup with a dedicated 20-kΩ resistor  
Reserved for testing, pullup with a dedicated 20-kΩ resistor  
Reserved (leave unconnected, do not connect to power or ground)  
Reserved (leave unconnected, do not connect to power or ground)  
SUPPLY VOLTAGE PINS  
G3  
E3  
A12  
C15  
D12  
B11  
B13  
C10  
I
O
O
A11  
A16  
B7  
A3  
A7  
A16  
A20  
D4  
B8  
B19  
B20  
C6  
D6  
D7  
C10  
C14  
C17  
C21  
G4  
D9  
D10  
D13  
D14  
D16  
D17  
D19  
F1  
DV  
S
3.3-V supply voltage  
DD  
G23  
H3  
H24  
K3  
F4  
K24  
L1  
F19  
F22  
G4  
L26  
N24  
P3  
G19  
J4  
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
Signal Descriptions (Continued)  
PIN NO.  
SIGNAL  
NAME  
†
DESCRIPTION  
SUPPLY VOLTAGE PINS (CONTINUED)  
TYPE  
GJL  
GLS  
T1  
T26  
U3  
J19  
K4  
K19  
L1  
U24  
W3  
W24  
Y4  
M22  
N4  
N19  
P4  
Y23  
AD6  
AD10  
AD13  
AD17  
AD21  
AE7  
AE8  
AE19  
AE20  
AF11  
AF16  
–
P19  
T4  
T19  
U1  
U4  
U19  
U22  
W4  
DV  
S
3.3-V supply voltage  
DD  
W6  
W7  
W9  
W10  
W13  
W14  
W16  
W17  
W19  
AB5  
AB9  
AB14  
AB18  
E7  
–
–
–
–
–
–
–
–
–
A1  
A2  
E8  
A3  
E10  
E11  
E12  
E13  
E15  
E16  
F7  
A24  
A25  
A26  
B1  
CV  
S
1.8-V supply voltage  
DD  
B2  
B3  
B24  
B25  
B26  
C1  
F8  
F9  
F11  
F12  
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
Signal Descriptions (Continued)  
PIN NO.  
SIGNAL  
NAME  
†
DESCRIPTION  
SUPPLY VOLTAGE PINS (CONTINUED)  
TYPE  
GJL  
GLS  
C2  
C3  
F14  
F15  
F16  
G5  
C4  
C23  
C24  
C25  
C26  
D3  
G6  
G17  
G18  
H5  
D4  
H6  
D5  
H17  
H18  
J6  
D22  
D23  
D24  
E4  
J17  
K5  
E23  
K18  
L5  
AB4  
AB23  
AC3  
AC4  
AC5  
AC22  
AC23  
AC24  
AD1  
AD2  
AD3  
AD4  
AD23  
AD24  
AD25  
AD26  
AE1  
AE2  
AE3  
AE24  
AE25  
AE26  
AF1  
AF2  
AF3  
AF24  
AF25  
L6  
L17  
L18  
M5  
M6  
CV  
S
1.8-V supply voltage  
DD  
M17  
M18  
N5  
N18  
P6  
P17  
R5  
R6  
R17  
R18  
T5  
T6  
T17  
T18  
U7  
U8  
U9  
U11  
U12  
U14  
U15  
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
Signal Descriptions (Continued)  
PIN NO.  
SIGNAL  
NAME  
†
DESCRIPTION  
SUPPLY VOLTAGE PINS (CONTINUED)  
TYPE  
GJL  
GLS  
AF26  
U16  
V7  
–
–
–
–
–
–
–
–
V8  
V10  
V11  
V12  
V13  
V15  
V16  
CV  
S
1.8-V supply voltage  
DD  
GROUND PINS  
A4  
A8  
A1  
A5  
A13  
A14  
A15  
A19  
A23  
B4  
A12  
A18  
A22  
B2  
B21  
C1  
B12  
B13  
B14  
B23  
C5  
C3  
C20  
C22  
D5  
D8  
C11  
C16  
C22  
D1  
D11  
D12  
D15  
D18  
E4  
V
SS  
GND  
Ground pins  
D2  
D6  
E5  
D21  
D25  
D26  
E3  
E6  
E9  
E14  
E17  
E18  
E19  
F5  
E24  
F4  
F23  
H1  
F6  
H26  
F10  
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
Signal Descriptions (Continued)  
PIN NO.  
SIGNAL  
NAME  
†
DESCRIPTION  
TYPE  
GJL  
GLS  
GROUND PINS (CONTINUED)  
K1  
K26  
M1  
F13  
F17  
F18  
H4  
M26  
N1  
H19  
J1  
N2  
N25  
N26  
P1  
J5  
J18  
J22  
K6  
P2  
P25  
P26  
R1  
K17  
L4  
L19  
M4  
R26  
U1  
M19  
N6  
U26  
W1  
N17  
P1  
W26  
AA4  
AA23  
AB3  
AB24  
AC1  
AC2  
AC6  
AC21  
AC25  
AC26  
AD5  
AD22  
AE4  
AE13  
AE14  
AE23  
AF4  
AF8  
V
SS  
GND  
Ground pins  
P5  
P18  
P22  
R4  
R19  
U5  
U6  
U10  
U13  
U17  
U18  
V4  
V5  
V6  
V9  
V14  
V17  
V18  
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
Signal Descriptions (Continued)  
PIN NO.  
SIGNAL  
NAME  
†
DESCRIPTION  
TYPE  
GJL  
GLS  
GROUND PINS (CONTINUED)  
AF10  
V19  
W5  
AF12  
AF13  
W8  
AF14  
W11  
W12  
W15  
W18  
Y1  
AF15  
AF17  
AF19  
AF23  
–
–
–
–
–
–
–
–
–
–
–
–
Y3  
Y20  
Y22  
AA2  
AA21  
AB1  
AB3  
AB7  
AB11  
AB16  
AB20  
AB22  
V
SS  
GND  
Ground pins  
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
development support  
Texas Instruments offers an extensive line of development tools for the ’C6200 generation of DSPs, including  
tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and  
fully integrate and debug software and hardware modules.  
The following products support development of ’C6200-based applications:  
Software Development Tools:  
Assembly optimizer  
Assembler/Linker  
Simulator  
Optimizing ANSI C compiler  
Application algorithms  
C/Assembly debugger and code profiler  
Hardware Development Tools:  
Extended development system (XDS ) emulator (supports ’C6200 multiprocessor system debug)  
EVM (Evaluation Module)  
The TMS320 DSP Development Support Reference Guide (SPRU011) contains information about  
development-support products for all TMS320 family member devices, including documentation. See this  
document for further information on TMS320 documentation or any TMS320 support products from Texas  
Instruments. An additional document, the TMS320 Third-Party Support Reference Guide (SPRU052), contains  
informationaboutTMS320-relatedproductsfromothercompaniesintheindustry. ToreceiveTMS320literature,  
contact the Literature Response Center at 800/477-8924.  
See Table 2 for a complete listing of development-support tools for the ’C6200. For information on pricing and  
availability, contact the nearest TI field sales office or authorized distributor.  
Table 2. TMS320C6xx Development-Support Tools  
DEVELOPMENT TOOL  
PLATFORM  
Software  
PART NUMBER  
C Compiler/Assembler/Linker/Assembly Optimizer  
C Compiler/Assembler/Linker/Assembly Optimizer  
Simulator  
Win32  
TMDX3246855-07  
SPARC Solaris  
Win32  
TMDX3246555-07  
TMDS3246851-07  
TMDS3246551-07  
TMDX324016X-07  
Simulator  
SPARC Solaris  
Win32, Windows NT  
Hardware  
XDS510 Debugger/Emulation Software  
†
XDS510 Emulator  
PC  
TMDS00510  
‡
XDS510WS Emulator  
SCSI  
TMDS00510WS  
Software/Hardware  
PC/Win95/Windows NT  
PC/Win95/Windows NT  
EVM Evaluation Kit  
TMDX3260A6201  
TMDX326006201  
EVM Evaluation Kit (including TMDX3246855–07)  
†
‡
Includes XDS510 board and JTAG emulation cable. TMDX324016X-07 C-source Debugger/Emulation software is not included.  
Includes XDS510WS box, SCSI cable, power supply, and JTAG emulation cable.  
XDS, XDS510, and XDS510WS are trademarks of Texas Instruments Incorporated.  
Win32 and Windows NT are trademarks of Microsoft Corporation.  
SPARC is a trademark of SPARC International, Inc.  
Solaris is a trademark of Sun Microsystems, Inc.  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
device and development-support tool nomenclature  
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all TMS320  
devices and support tools. Each TMS320 member has one of three prefixes: TMX, TMP, or TMS. Texas  
Instruments recommends two of three possible prefix designators for support tools: TMDX and TMDS. These  
prefixes represent evolutionary stages of product development from engineering prototypes (TMX/TMDX)  
through fully qualified production devices/tools (TMS/TMDS).  
Device development evolutionary flow:  
TMX  
TMP  
TMS  
Experimental device that is not necessarily representative of the final device’s electrical  
specifications  
Final silicon die that conforms to the device’s electrical specifications but has not completed  
quality and reliability verification  
Fully qualified production device  
Support tool development evolutionary flow:  
TMDX  
Development-support product that has not yet completed Texas Instruments internal qualification  
testing.  
TMDS  
Fully qualified development-support product  
TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:  
“Developmental product is intended for internal evaluation purposes.”  
TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability  
of the device have been demonstrated fully. TI’s standard warranty applies.  
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production  
devices. TexasInstrumentsrecommendsthatthesedevicesnotbeusedinanyproductionsystembecausetheir  
expected end-use failure rate still is undefined. Only qualified production devices are to be used.  
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type  
(for example, GJL), the temperature range (for example, blank is the default commercial temperature range),  
and the device speed range in megahertz (for example, -250 is 250 MHz). Figure 5 provides a legend for  
reading the complete device name for any TMS320 family member.  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
device and development-support tool nomenclature (continued)  
(A)  
TMS 320  
C
6202 GJL  
–250  
PREFIX  
DEVICE SPEED RANGE  
–100 MHz  
TMX= Experimental device  
TMP= Prototype device  
TMS= Qualified device  
SMJ = MIL-STD-883C  
–150 MHz  
–167 MHz  
–200 MHz  
–233 MHz  
SM = High Rel (non-883C)  
–250 MHz  
–300 MHz  
DEVICE FAMILY  
320 = TMS320 family  
TEMPERATURE RANGE (DEFAULT: 0°C TO 90°C)  
Blank = 0°C to 90°C, commercial temperature  
A
=
–40°C to 105°C, extended temperature  
†
PACKAGE TYPE  
N
=
=
=
=
=
=
=
=
=
=
Plastic DIP  
J
Ceramic DIP  
TECHNOLOGY  
JD  
GB  
FZ  
FN  
FD  
PJ  
PQ  
PZ  
Ceramic DIP side-brazed  
Ceramic PGA  
Ceramic CC  
Plastic leaded CC  
Ceramic leadless CC  
100-pin plastic EIAJ QFP  
132-pin plastic bumpered QFP  
100-pin plastic TQFP  
C = CMOS  
E
F
=
=
CMOS EPROM  
CMOS Flash EEPROM  
PBK = 128-pin plastic TQFP  
PGE = 144-pin plastic TQFP  
GFN = 256-pin plastic BGA  
GGU = 144-pin plastic BGA  
GGP = 352-pin plastic BGA  
GJC = 352-pin plastic BGA  
GJL = 352-pin plastic BGA  
GLS = 384-pin plastic BGA  
DEVICE  
’1x DSP:  
10  
14  
15  
16  
17  
’2x DSP:  
’2xx DSP:  
’3x DSP:  
25  
26  
203 206 240  
204 209  
30  
31  
32  
’4x DSP:  
’5x DSP:  
40  
44  
50  
51  
52  
53  
56  
57  
’54x DSP:  
’6x DSP:  
541 545  
542 546  
543 548  
†
DIP  
PGA  
CC  
=
=
=
=
Dual-In-Line Package  
Pin Grid Array  
Chip Carrier  
6201  
6201B  
6202  
6203  
6211  
6701  
6711  
QFP  
Quad Flat Package  
TQFP = Thin Quad Flat Package  
BGA Ball Grid Array  
=
Figure 5. TMS320 Device Nomenclature (Including TMS320C6202)  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
documentation support  
Extensive documentation supports all TMS320 family generations of devices from product announcement  
through applications development. The types of documentation available include: data sheets, such as this  
document, with design specifications; complete user’s reference guides for all devices; technical briefs;  
development-support tools; and hardware and software applications. The following is a brief, descriptive list of  
support documentation specific to the ’C6x devices:  
The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) describes the  
’C6000 CPU architecture, instruction set, pipeline, and associated interrupts.  
The TMS320C6000 Peripherals Reference Guide (literature number SPRU190) describes the functionality of  
the peripherals available on ’C6x devices, such as the external memory interface (EMIF), host-port interface  
(HPI), multichannel buffered serial ports (McBSPs), direct-memory-access (DMA), enhanced  
direct-memory-access (EDMA) controller, expansion bus (XB), clocking and phase-locked loop (PLL); and  
power-down modes. This guide also includes information on internal data and program memories.  
The TMS320C6000 Programmer’s Guide (literature number SPRU198) describes ways to optimize C and  
assembly code for ’C6x devices and includes application program examples.  
The TMS320C6x C Source Debugger User’s Guide (literature number SPRU188) describes how to invoke the  
’C6x simulator and emulator versions of the C source debugger interface and discusses various aspects of the  
debugger, including: command entry, code execution, data management, breakpoints, profiling, and analysis.  
The TMS320C6x Peripheral Support Library Programmer’s Reference (literature number SPRU273) describes  
the contents of the ’C6x peripheral support library of functions and macros. It lists functions and macros both  
by header file and alphabetically, provides a complete description of each, and gives code examples to show  
how they are used.  
TMS320C6000 Assembly Language Tools User’s Guide (literature number SPRU186) describes the assembly  
language tools (assembler, linker, and other tools used to develop assembly language code), assembler  
directives, macros, common object file format, and symbolic debugging directives for the ’C6000 generation of  
devices.  
The TMS320C6x Evaluation Module Reference Guide (literature number SPRU269) provides instructions for  
installing and operating the ’C6x evaluation module. It also includes support software documentation,  
application programming interfaces, and technical reference material.  
TMS320C62x Multichannel Evaluation Module User’s Guide (literature number SPRU285) provides  
instructions for installing and operating the ’C62x multichannel evaluation module. It also includes support  
software documentation, application programming interfaces, and technical reference material.  
TMS320C62x Multichannel Evaluation Module Technical Reference (SPRU308) provides provides technical  
reference information for the ’C62x multichannel evaluation module (McEVM). It includes support software  
documentation, application programming interface references, and hardware descriptions for the ’C62x  
McEVM.  
TMS320C6000 DSP/BIOS User’s Guide (literature number SPRU303) describes how to use DSP/BIOS tools  
and APIs to analyze embedded real-time DSP applications.  
Code Composer User’s Guide (literature number SPRU296) explains how to use the Code Composer  
development environment to build and debug embedded real-time DSP applications.  
Code Composer Studio Tutorial(literaturenumberSPRU301)introducestheCodeComposerStudiointegrated  
development environment and software tools.  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
documentation support (continued)  
The TMS320C6000 Technical Brief (literature number SPRU197) gives an introduction to the ’C62x/C67x  
devices, associated development tools, and third-party support.  
A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support DSP research and  
education. The TMS320 newsletter, Details on Signal Processing, is published quarterly and distributed to  
update TMS320 customers on product information. The TMS320 DSP bulletin board service (BBS) provides  
access to information pertaining to the TMS320 family, including documentation, source code, and object code  
for many DSP algorithms and utilities. The BBS can be reached at 281/274-2323.  
Information regarding TI DSP products is also available on the Worldwide Web at http://www.ti.com uniform  
resource locator (URL).  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
clock PLL  
All of the internal ’C6202 clocks are generated from a single source through the CLKIN pin. This source clock  
either drives the PLL, which generates the internal CPU clock, or bypasses the PLL to become the CPU clock.  
To use the PLL to generate the CPU clock, the filter circuit shown in Figure 6 must be properly designed.  
To configure the ’C6202 PLL clock for proper operation, see Figure 6 and Table 3. To minimize the clock jitter,  
a single clean power supply should power both the ’C6202 device and the external clock oscillator circuit. The  
minimum CLKIN rise and fall times should also be observed. See the input and output clocks section for input  
clock timing requirements.  
3.3 V  
3 OUT  
’320C6202  
PLLV  
PLLF  
R1  
÷ 1  
CLKOUT1  
CLKOUT2  
CPU Clock  
1 IN  
÷ 2  
2
PLLG  
10 µF  
0.1 µF C1 C2  
GND  
(Bypass)  
CLKIN  
0
0
0
0
0
1
– MULT×1  
– MULT×4  
f(CPU Clock)=f(CLKIN)  
f(CPU Clock)=f(CLKIN)×4  
All Other Modes – Reserved  
NOTES: A. The ’C6202 PLL can generate CPU clock frequencies in the range of 130 MHz to 250 MHz. For frequencies below 130 MHz, the  
PLL should be configured to operate in bypass mode.  
B. For the ’C6202, values for C1, C2, and R1 are fixed and apply to all valid frequency ranges of CLKIN and CPU clock frequency.  
C. For CLKMODE x1, the PLL is bypassed and all six external PLL components can be removed. For this case, the PLLV terminal  
has to be connected to a clean 3.3-V supply and the PLLG and PLLF terminals should be tied together.  
D. The 3.3-V supply for the EMI filter (and PLLV) must be from the same 3.3-V power plane supplying the I/O voltage, DV  
E. EMI filter manufacturer TDK part number ACF451832-153-T  
.
DD  
F. CLKMODE2 and CLKMODE1 exist only on the GLS device. There are no equivalent connections on the GJL device.  
G. ThereservedPLLclockmodes(GLSdevicesonly)mayormaynotbesupportedonfuturedevicesasadditionalPLLmultiplyfactors.  
For future flexibility, a board can be designed so that these inputs are configurable (either through jumpers, switches, or 0-Ω  
resistors).  
Figure 6. PLL Block Diagram  
†
Table 3. TMS320C6202 PLL Component Selection Table  
CPU CLOCK  
FREQUENCY  
(CLKOUT1)  
CLKIN  
RANGE  
(MHz)  
CLKOUT2  
RANGE  
(MHz)  
TYPICAL  
LOCK TIME  
(µs)  
R1  
(Ω)  
C1  
(nF)  
C2  
(pF)  
CLKMODE  
RANGE (MHz)  
x4  
32.5–62.5  
130–250  
65–125  
60.4  
27  
560  
75  
†
Under some operating conditions, the maximum PLL lock time may vary as much as 150% from the specified typical value. For example, if the  
typical lock time is specified as 100 µs, the maximum value may be as long as 250 µs.  
power-supply sequencing  
The 1.8-V supply powers the core and the 3.3-V supply powers the I/O buffers. The core supply should be  
powered up first, or at the same time as the I/O buffers supply. This is to ensure that the I/O buffers have valid  
inputs from the core before the output buffers are powered up, thus preventing bus contention with other chips  
on the board.  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
†
absolute maximum ratings over operating case temperature range (unless otherwise noted)  
Supply voltage range, CV  
Supply voltage range, DV  
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 2.3 V  
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V  
DD  
DD  
Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V  
Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V  
Operating case temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 90 C  
C
Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55 C to 150 C  
stg  
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
NOTE 1: All voltage values are with respect to V  
SS  
.
recommended operating conditions  
MIN NOM  
MAX UNIT  
CV  
DV  
Supply voltage  
1.71  
3.14  
0
1.8  
3.30  
0
1.89  
3.46  
0
V
V
DD  
DD  
Supply voltage  
V
V
V
Supply ground  
V
SS  
High-level input voltage  
Low-level input voltage  
High-level output current  
Low-level output current  
Operating case temperature  
2.0  
V
IH  
IL  
0.8  
–8  
8
V
I
I
mA  
mA  
C
OH  
OL  
T
C
0
90  
electrical characteristics over recommended ranges of supply voltage and operating case  
temperature (unless otherwise noted)  
PARAMETER  
High-level output voltage  
Low-level output voltage  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
V
V
V
DV  
DV  
= MIN,  
= MIN,  
I
I
= MAX  
= MAX  
2.4  
OH  
DD  
DD  
OH  
OL  
0.6  
±10  
±10  
V
OL  
‡
I
I
I
I
I
Input current  
V = V  
I
to DV  
uA  
uA  
mA  
mA  
mA  
pF  
I
SS  
DD  
or 0 V  
DD  
Off-state output current  
V
O
= DV  
OZ  
§
Supply current, CPU + CPU memory access  
CV  
CV  
DV  
= NOM,  
= NOM,  
= NOM,  
CPU clock = 200 MHz  
CPU clock = 200 MHz  
CPU clock = 200 MHz  
TBD  
TBD  
TBD  
DD2V  
DD2V  
DD3V  
DD  
DD  
DD  
Supply current, peripherals  
#
Supply current, I/O pins  
Input capacitance  
C
C
10  
10  
i
Output capacitance  
pF  
o
‡
§
TMS and TDI are not included due to internal pullups. TRST is not included due to internal pulldown.  
Measured with average CPU activity:  
50% of time:  
50% of time:  
Measured with average peripheral activity:  
8 instructions per cycle, 32-bit DMEM access per cycle  
2 instructions per cycle, 16-bit DMEM access per cycle  
#
50% of time:  
Timers at max rate  
McBSPs at E1 rate  
DMA burst transfer between DMEM and SDRAM  
Timers at max rate  
McBSPs at E1 rate  
50% of time:  
DMA servicing McBSPs  
Measured with average I/O activity (30-pF load, SDCLK on):  
25% of time:  
25% of time:  
50% of time:  
Reads from external SDRAM  
Writes to external SDRAM  
No activity  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
PARAMETER MEASUREMENT INFORMATION  
I
OL  
Tester Pin  
Electronics  
Output  
Under  
Test  
50 Ω  
V
ref  
†
= 30 pF  
C
T
I
OH  
†
Typical distributed load circuit capacitance  
signal transition levels  
All input and output timing parameters are referenced to 1.5 V for both “0” and “1” logic levels.  
V
ref  
= 1.5 V  
Figure 7. Input and Output Voltage Reference Levels for ac Timing Measurements  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
INPUT AND OUTPUT CLOCKS  
†
timing requirements for CLKIN (see Figure 8)  
’C6202-200  
’C6202-233  
’C6202-250  
CLKMODE  
= x4  
CLKMODE  
= x1  
CLKMODE  
CLKMODE  
= x1  
CLKMODE  
CLKMODE  
= x1  
NO.  
UNIT  
= x4  
= x4  
MIN MAX  
MIN MAX  
MIN MAX  
MIN MAX  
MIN MAX  
MIN MAX  
Cycle time,  
CLKIN  
1
2
3
4
t
t
t
t
20  
5
17.2  
6.9  
6.9  
5
4.3  
16  
6.4  
6.4  
5
4
ns  
ns  
ns  
ns  
c(CLKIN)  
w(CLKINH)  
w(CLKINL)  
t(CLKIN)  
Pulse duration,  
CLKIN high  
8
8
5
2.25  
2.25  
0.6  
1.9  
1.9  
0.6  
1.8  
1.8  
0.6  
Pulse duration,  
CLKIN low  
Transition time,  
CLKIN  
†
The reference points for the rise and fall transitions are measured at 20% and 80%, respectively, of V  
.
IH  
1
4
2
CLKIN  
3
4
Figure 8. CLKIN Timings  
†‡  
timing requirements for XCLKIN (see Figure 9)  
’C6202-200  
’C6202-233  
’C6202-250  
NO.  
UNIT  
MIN MAX  
4P  
1
2
3
4
t
t
t
t
Cycle time, XCLKIN  
ns  
ns  
ns  
ns  
c(XCLKIN)  
w(XCLKINH)  
w(XCLKINL)  
t(XCLKIN)  
Pulse duration, XCLKIN high  
Pulse duration, XCLKIN low  
Transition time, XCLKIN  
1.8P  
1.8P  
0.6  
†
‡
The reference points for the rise and fall transitions are measured at 20% and 80%, respectively, of V  
P = 1/CPU clock frequency in nanoseconds (ns).  
.
IH  
1
4
2
XCLKIN  
3
4
Figure 9. XCLKIN Timings  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
INPUT AND OUTPUT CLOCKS (CONTINUED)  
†‡  
switching characteristics for CLKOUT1 (see Figure 10)  
’C6202-200  
’C6202-233  
’C6202-250  
NO.  
PARAMETER  
UNIT  
CLKMODE = x4  
MIN MAX  
P + 0.7  
CLKMODE = x1  
MIN MAX  
1
2
3
4
t
t
t
t
Cycle time, CLKOUT1  
P – 0.7  
(P/2) – 0.5  
(P/2) – 0.5  
P – 0.7  
PH – 0.5  
PL – 0.5  
P + 0.7  
PH + 0.5  
PL + 0.5  
0.6  
ns  
ns  
ns  
ns  
c(CKO1)  
w(CKO1H)  
w(CKO1L)  
t(CKO1)  
Pulse duration, CLKOUT1 high  
Pulse duration, CLKOUT1 low  
Transition time, CLKOUT1  
(P/2 ) + 0.5  
(P/2 ) + 0.5  
0.6  
†
‡
PH is the high period of CLKIN in ns and PL is the low period of CLKIN in ns.  
P = 1/CPU clock frequency in nanoseconds (ns).  
1
4
2
CLKOUT1  
3
4
Figure 10. CLKOUT1 Timings  
‡
switching characteristics for CLKOUT2 (see Figure 11)  
’C6202-200  
’C6202-233  
’C6202-250  
NO.  
PARAMETER  
UNIT  
MIN  
MAX  
1
2
3
4
t
t
t
t
Cycle time, CLKOUT2  
2P – 0.7  
P – 0.7  
P – 0.7  
2P + 0.7  
P + 0.7  
P + 0.7  
0.6  
ns  
ns  
ns  
ns  
c(CKO2)  
w(CKO2H)  
w(CKO2L)  
t(CKO2)  
Pulse duration, CLKOUT2 high  
Pulse duration, CLKOUT2 low  
Transition time, CLKOUT2  
‡
P = 1/CPU clock frequency in nanoseconds (ns).  
1
4
2
CLKOUT2  
3
4
Figure 11. CLKOUT2 Timings  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
INPUT AND OUTPUT CLOCKS (CONTINUED)  
†‡  
switching characteristics for XFCLK (see Figure 12)  
’C6202-200  
’C6202-233  
’C6202-250  
NO.  
PARAMETER  
UNIT  
MIN  
D * P – 0.7  
MAX  
1
2
3
4
t
t
t
t
Cycle time, XFCLK  
D * P + 0.7  
ns  
ns  
ns  
ns  
c(XFCK)  
w(XFCKH)  
w(XFCKL)  
t(XFCK)  
Pulse duration, XFCLK high  
Pulse duration, XFCLK low  
Transition time, XFCLK  
(D/2) * P – 0.7 (D/2) * P + 0.7  
(D/2) * P – 0.7 (D/2) * P + 0.7  
0.6  
†
‡
P = 1/CPU clock frequency in ns.  
D = 8, 6, 4, or 2; FIFO clock divide ratio, user-programmable  
1
4
2
XFCLK  
3
4
Figure 12. XFCLK Timings  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
ASYNCHRONOUS MEMORY TIMING  
†
timing requirements for asynchronous memory cycles (see Figure 13 – Figure 14)  
’C6202-200  
’C6202-233  
’C6202-250  
NO.  
UNIT  
MIN MAX  
6
7
t
t
t
t
Setup time, read EDx valid before CLKOUT1 high  
Hold time, read EDx valid after CLKOUT1 high  
Setup time, ARDY valid before CLKOUT1 high  
Hold time, ARDY valid after CLKOUT1 high  
4.0  
0
ns  
ns  
ns  
ns  
su(EDV-CKO1H)  
h(CKO1H-EDV)  
su(ARDY-CKO1H)  
h(CKO1H-ARDY)  
10  
11  
4.0  
0
†
To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. If ARDY does meet setup or hold  
time, it may be recognized in the current cycle or the next cycle. Thus, ARDY can be an asynchronous input.  
‡
switching characteristics for asynchronous memory cycles (see Figure 13 – Figure 14)  
’C6202-200  
’C6202-233  
’C6202-250  
NO.  
PARAMETER  
UNIT  
MIN  
0
MAX  
1
2
t
t
t
t
t
t
t
t
t
t
Delay time, CLKOUT1 high to CEx valid  
Delay time, CLKOUT1 high to BEx valid  
Delay time, CLKOUT1 high to BEx invalid  
Delay time, CLKOUT1 high to EAx valid  
Delay time, CLKOUT1 high to EAx invalid  
Delay time, CLKOUT1 high to AOE valid  
Delay time, CLKOUT1 high to ARE valid  
Delay time, CLKOUT1 high to EDx valid  
Delay time, CLKOUT1 high to EDx invalid  
Delay time, CLKOUT1 high to AWE valid  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
d(CKO1H-CEV)  
d(CKO1H-BEV)  
d(CKO1H-BEIV)  
d(CKO1H-EAV)  
d(CKO1H-EAIV)  
d(CKO1H-AOEV)  
d(CKO1H-AREV)  
d(CKO1H-EDV)  
d(CKO1H-EDIV)  
d(CKO1H-AWEV)  
0
3
0
4
0
5
0
8
0
9
0
12  
13  
14  
0
0
4.0  
‡
The minimum delay is also the minimum output hold after CLKOUT1 high.  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
ASYNCHRONOUS MEMORY TIMING (CONTINUED)  
Not ready = 2  
Setup = 2  
Strobe = 5  
HOLD = 1  
CLKOUT1  
CEx  
1
2
4
1
3
BE[3:0]  
EA[21:2]  
ED[31:0]  
AOE  
5
7
6
8
8
9
9
ARE  
AWE  
11  
11  
10  
10  
ARDY  
Figure 13. Asynchronous Memory Read Timing  
Not ready = 2  
Setup = 2  
Strobe = 5  
HOLD = 1  
CLKOUT1  
1
2
4
1
3
5
CEx  
BE[3:0]  
EA[21:2]  
12  
13  
14  
ED[31:0]  
AOE  
ARE  
14  
AWE  
11  
11  
10  
10  
ARDY  
Figure 14. Asynchronous Memory Write Timing  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
SYNCHRONOUS-BURST MEMORY TIMING  
timing requirements for synchronous-burst SRAM cycles (see Figure 15)  
’C6202-200  
’C6202-233  
’C6202-250  
NO.  
UNIT  
MIN  
MAX  
MIN  
MAX  
MIN  
MAX  
Setup time, read EDx valid before CLKOUT2  
high  
7
8
t
t
2.5  
2.1  
2
ns  
ns  
su(EDV-CKO2H)  
Hold time, read EDx valid after CLKOUT2 high  
1.5  
1.5  
1.5  
h(CKO2H-EDV)  
†‡  
switching characteristics for synchronous-burst SRAM cycles (see Figure 15 and Figure 16)  
’C6202-200  
’C6202-233  
’C6202-250  
NO.  
PARAMETER  
UNIT  
MIN  
MAX  
MIN  
MAX  
MIN  
MAX  
Output setup time, CEx valid  
before CLKOUT2 high  
1
2
3
4
5
6
t
t
t
t
t
t
2P – 5.5  
2P – 4.4  
2P – 3.8  
ns  
ns  
ns  
ns  
ns  
ns  
osu(CEV-CKO2H)  
oh(CKO2H-CEV)  
osu(BEV-CKO2H)  
oh(CKO2H-BEIV)  
osu(EAV-CKO2H)  
oh(CKO2H-EAIV)  
Output hold time, CEx valid after  
CLKOUT2 high  
1
2P – 5.5  
1
1
2P – 4.4  
1
1
2P – 3.8  
1
Output setup time, BEx valid  
before CLKOUT2 high  
Output hold time, BEx invalid  
after CLKOUT2 high  
Output setup time, EAx valid  
before CLKOUT2 high  
2P – 5.5  
1
2P – 4.4  
1
2P – 3.8  
1
Output hold time, EAx invalid  
after CLKOUT2 high  
Output setup time,  
9
t
t
t
SDCAS/SSADS valid before  
CLKOUT2 high  
2P – 5.5  
1
2P – 4.4  
1
2P – 3.8  
1
ns  
ns  
ns  
osu(ADSV-CKO2H)  
oh(CKO2H-ADSV)  
osu(OEV-CKO2H)  
Output hold time,  
SDCAS/SSADS valid after  
CLKOUT2 high  
10  
11  
Output setup time,  
SDRAS/SSOE valid before  
CLKOUT2 high  
2P – 5.5  
2P – 4.4  
2P – 3.8  
Output hold time, SDRAS/SSOE  
valid after CLKOUT2 high  
12  
13  
14  
15  
16  
t
t
t
t
t
1
2P – 5.5  
1
1
2P – 4.4  
1
1
2P – 3.8  
1
ns  
ns  
ns  
ns  
ns  
oh(CKO2H-OEV)  
osu(EDV-CKO2H)  
oh(CKO2H-EDIV)  
osu(WEV-CKO2H)  
oh(CKO2H-WEV)  
Output setup time, EDx valid  
§
before CLKOUT2 high  
Output hold time, EDx invalid  
after CLKOUT2 high  
Output setup time, SDWE/SSWE  
valid before CLKOUT2 high  
2P – 5.5  
1
2P – 4.4  
1
2P – 3.8  
1
Output hold time, SDWE/SSWE  
valid after CLKOUT2 high  
†
‡
§
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.  
SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses.  
For the first write in a series of one or more consecutive adjacent writes, the write data is generated one CLKOUT2 cycle early to accommodate  
the ED enable time.  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)  
CLKOUT2  
1
2
CEx  
3
4
6
BE[3:0]  
BE1  
BE2  
A2  
BE3  
A3  
BE4  
5
A1  
A4  
8
EA[21:2]  
ED[31:0]  
7
Q1  
Q2  
Q3  
10  
Q4  
9
†
SDCAS/SSADS  
11  
12  
†
†
SDRAS/SSOE  
SDWE/SSWE  
†
SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses.  
Figure 15. SBSRAM Read Timing  
CLKOUT2  
1
2
CEx  
BE[3:0]  
3
4
6
BE1  
BE2  
A2  
BE3  
A3  
BE4  
A4  
5
EA[21:2]  
A1  
13  
14  
10  
Q1  
Q2  
Q3  
Q4  
ED[31:0]  
9
†
SDCAS/SSADS  
†
SDRAS/SSOE  
SDWE/SSWE  
15  
16  
†
†
SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses.  
Figure 16. SBSRAM Write Timing  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
SYNCHRONOUS DRAM TIMING  
timing requirements for synchronous DRAM cycles (see Figure 17)  
’C6202-200  
’C6202-233  
’C6202-250  
NO.  
UNIT  
MIN MAX  
MIN MAX  
MIN MAX  
7
8
t
t
Setup time, read EDx valid before CLKOUT2 high  
Hold time, read EDx valid after CLKOUT2 high  
1
3
1
3
0.5  
3
ns  
ns  
su(EDV-CKO2H)  
h(CKO2H-EDV)  
†‡  
switching characteristics for synchronous DRAM cycles (see Figure 17–Figure 22)  
’C6202-200  
’C6202-233  
’C6202-250  
NO.  
PARAMETER  
UNIT  
MIN  
MAX  
MIN  
MAX  
MIN  
MAX  
Output setup time, CEx valid  
before CLKOUT2 high  
1
2
3
4
5
6
t
t
t
t
t
t
2P – 6  
2P – 4.6  
2P – 4  
ns  
ns  
ns  
ns  
ns  
ns  
osu(CEV-CKO2H)  
oh(CKO2H-CEV)  
osu(BEV-CKO2H)  
oh(CKO2H-BEIV)  
osu(EAV-CKO2H)  
oh(CKO2H-EAIV)  
Output hold time, CEx valid after  
CLKOUT2 high  
1.5  
2P – 6  
1.5  
1.5  
2P – 4.6  
1.5  
1.5  
2P – 4  
1.5  
Output setup time, BEx valid  
before CLKOUT2 high  
Output hold time, BEx invalid after  
CLKOUT2 high  
Output setup time, EAx valid  
before CLKOUT2 high  
2P – 6  
1.5  
2P – 4.6  
1.5  
2P – 4  
1.5  
Output hold time, EAx invalid after  
CLKOUT2 high  
Output setup time,  
9
t
SDCAS/SSADS valid before  
CLKOUT2 high  
2P – 6  
2P – 4.6  
2P – 4  
ns  
osu(CASV-CKO2H)  
Output hold time, SDCAS/SSADS  
valid after CLKOUT2 high  
10  
11  
12  
13  
14  
15  
16  
17  
18  
t
t
t
t
t
t
t
t
t
1.5  
2P – 6  
1.5  
1.5  
2P – 4.6  
1.5  
1.5  
2P – 4  
1.5  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
oh(CKO2H-CASV)  
osu(EDV-CKO2H)  
oh(CKO2H-EDIV)  
osu(WEV-CKO2H)  
oh(CKO2H-WEV)  
osu(SDA10V-CKO2H)  
oh(CKO2H-SDA10IV)  
osu(RASV-CKO2H)  
oh(CKO2H-RASV)  
Output setup time, EDx valid  
§
before CLKOUT2 high  
Output hold time, EDx invalid after  
CLKOUT2 high  
Output setup time, SDWE/SSWE  
valid before CLKOUT2 high  
2P – 6  
1.5  
2P – 4.6  
1.5  
2P – 4  
1.5  
Output hold time, SDWE/SSWE  
valid after CLKOUT2 high  
Output setup time, SDA10 valid  
before CLKOUT2 high  
2P – 6  
1.5  
2P – 4.6  
1.5  
2P – 4  
1.5  
Output hold time, SDA10 invalid  
after CLKOUT2 high  
Output setup time, SDRAS/SSOE  
valid before CLKOUT2 high  
2P – 6  
1.5  
2P – 4.6  
1.5  
2P – 4  
1.5  
Output hold time, SDRAS/SSOE  
valid after CLKOUT2 high  
†
‡
§
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.  
SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.  
For the first write in a series of one or more consecutive adjacent writes, the write data is generated one CLKOUT2 cycle early to accommodate  
the ED enable time.  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
SYNCHRONOUS DRAM TIMING (CONTINUED)  
READ  
READ  
READ  
CLKOUT2  
CEx  
1
5
2
3
4
BE[3:0]  
EA[15:2]  
BE1  
BE2  
CA3  
BE3  
7
6
CA1  
CA2  
8
D1  
D2  
D3  
ED[31:0]  
SDA10  
15  
9
16  
10  
†
SDRAS/SSOE  
†
†
SDCAS/SSADS  
SDWE/SSWE  
†
SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.  
Figure 17. Three SDRAM READ Commands  
WRITE  
WRITE  
WRITE  
CLKOUT2  
CEx  
1
3
5
2
4
6
BE[3:0]  
BE1  
CA1  
BE2  
CA2  
D2  
BE3  
CA3  
D3  
EA[15:2]  
11  
12  
D1  
ED[31:0]  
SDA10  
15  
16  
†
SDRAS/SSOE  
9
10  
14  
†
SDCAS/SSADS  
13  
†
SDWE/SSWE  
†
SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.  
Figure 18. Three SDRAM WRT Commands  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
SYNCHRONOUS DRAM TIMING (CONTINUED)  
ACTV  
CLKOUT2  
1
5
2
CEx  
BE[3:0]  
Bank Activate/Row Address  
EA[15:2]  
ED[31:0]  
15  
Row Address  
SDA10  
17  
18  
†
†
†
SDRAS/SSOE  
SDCAS/SSADS  
SDWE/SSWE  
†
SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.  
Figure 19. SDRAM ACTV Command  
DCAB  
CLKOUT2  
1
2
CEx  
BE[3:0]  
EA[15:2]  
ED[31:0]  
15  
16  
SDA10  
17  
18  
†
†
SDRAS/SSOE  
SDCAS/SSADS  
13  
14  
†
SDWE/SSWE  
†
SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.  
Figure 20. SDRAM DCAB Command  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
SYNCHRONOUS DRAM TIMING (CONTINUED)  
REFR  
CLKOUT2  
CEx  
1
2
BE[3:0]  
EA[15:2]  
ED[31:0]  
SDA10  
17  
9
18  
10  
†
SDRAS/SSOE  
†
SDCAS/SSADS  
†
SDWE/SSWE  
†
SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.  
Figure 21. SDRAM REFR Command  
MRS  
CLKOUT2  
1
2
6
CEx  
BE[3:0]  
5
EA[15:2]  
ED[31:0]  
SDA10  
MRS Value  
17  
18  
10  
14  
†
SDRAS/SSOE  
9
†
†
SDCAS/SSADS  
13  
SDWE/SSWE  
†
SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.  
Figure 22. SDRAM MRS Command  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
HOLD/HOLDA TIMING  
†
timing requirements for the HOLD/HOLDA cycles (see Figure 23)  
’C6202-200  
’C6202-233  
’C6202-250  
NO.  
UNIT  
MIN MAX  
3
t Hold time, HOLD low after HOLDA low  
oh(HOLDAL-HOLD
P
ns  
†
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.  
†‡  
switching characteristics for the HOLD/HOLDA cycles (see Figure 23)  
’C6202-200  
’C6202-233  
’C6202-250  
NO.  
PARAMETER  
UNIT  
MIN  
4P  
0
MAX  
§
1
2
4
5
t
t
t
t
Response time, HOLD low to EMIF Bus high impedance  
Delay time, EMIF Bus high impedance to HOLDA low  
Response time, HOLD high to EMIF Bus low impedance  
Delay time, EMIF Bus low impedance to HOLDA high  
ns  
ns  
ns  
ns  
R(HOLDL-EMHZ)  
d(EMHZ-HOLDAL)  
R(HOLDH-EMLZ)  
d(EMLZ-HOLDAH)  
2P  
7P  
2P  
3P  
0
†
‡
§
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.  
EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE, and SDA10.  
All pending EMIF transactions are allowed to complete before HOLDA is asserted. The worst case for this is an asynchronous read or write with  
external ARDY used or a minimum of eight consecutive SDRAM reads or writes when RBTR8 = 1. If no bus transactions are occurring, then the  
minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.  
External Requestor  
DSP Owns Bus  
DSP Owns Bus  
Owns Bus  
3
HOLD  
2
5
HOLDA  
1
4
†
EMIF Bus  
C6202  
C6202  
†
EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE, and SDA10.  
Figure 23. HOLD/HOLDA Timing  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
RESET TIMING  
timing requirements for reset (see Figure 24)  
’C6202-200  
’C6202-233  
’C6202-250  
NO.  
UNIT  
MIN  
MAX  
CLKOUT1  
cycles  
†
Width of the RESET pulse (PLL stable)  
10  
1
t
w(RST)  
‡
Width of the RESET pulse (PLL needs to sync up)  
250  
5
µs  
CLKOUT1  
cycles  
§
Setup time, XD configuration bits valid before RESET high  
11  
12  
t
t
su(XD)  
CLKOUT1  
cycles  
§
Hold time, XD configuration bits valid after RESET high  
5
h(XD)  
†
‡
This parameter applies to CLKMODE x1 when CLKIN is stable and applies to CLKMODE x4 when CLKIN and PLL are stable.  
This parameter only applies to CLKMODE x4. The RESET signal is not connected internally to the clock PLL circuit. The PLL, however, may  
need up to 250 µs to stabilize following device power up or after PLL configuration has been changed. During that time, RESET must be asserted  
to ensure proper device operation. See the clock PLL section for PLL lock times.  
§
XD[31:0] are the boot configuration pins during device reset.  
switching characteristics during reset (see Figure 24)  
’C6202-200  
’C6202-233  
’C6202-250  
NO.  
PARAMETER  
UNIT  
MIN  
MAX  
CLKOUT1  
cycles  
2
t
Response time to change of value in RESET signal  
2
R(RST)  
3
4
t
t
t
t
t
t
t
t
Delay time, CLKOUT1 high to CLKOUT2 invalid  
Delay time, CLKOUT1 high to CLKOUT2 valid  
Delay time, CLKOUT1 high to high group invalid  
Delay time, CLKOUT1 high to high group valid  
Delay time, CLKOUT1 high to low group invalid  
Delay time, CLKOUT1 high to low group valid  
Delay time, CLKOUT1 high to Z group high impedance  
Delay time, CLKOUT1 high to Z group valid  
–1  
–1  
–1  
–1  
–1  
–1  
–1  
–1  
10  
10  
10  
10  
10  
10  
10  
10  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
d(CKO1H-CKO2IV)  
d(CKO1H-CKO2V)  
d(CKO1H-XFCKIV)  
d(CKO1H-XFCKV)  
d(CKO1H-LOWIV)  
d(CKO1H-LOWV)  
d(CKO1H-ZHZ)  
5
6
7
8
9
10  
d(CKO1H-ZV)  
High group consists of:  
Low group consists of:  
Z group consists of:  
XFCLK  
IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1  
EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE,  
SDA10, CLKX0, CLKX1, CLKX2, FSX0, FSX1, FSX2, DX0, DX1, DX2, CLKR0, CLKR1, CLKR2, FSR0, FSR1,  
FSR2, XCE[3:0], XBE[3:0]/XA[5:2], XOE, XRE, XWE/XWAIT, XAS, XW/R, XRDY, XBLAST, XHOLD,  
and XHOLDA  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
RESET TIMING (CONTINUED)  
CLKOUT1  
1
2
2
RESET  
3
5
7
4
6
8
CLKOUT2  
†
HIGH GROUP  
LOW GROUP  
†
9
10  
†
Z GROUP  
12  
11  
‡
XD[31:0]  
†
‡
High group consists of:  
Low group consists of:  
Z group consists of:  
XFCLK  
IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1.  
EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE,  
SDA10, CLKX0, CLKX1, CLKX2, FSX0, FSX1, FSX2, DX0, DX1, DX2, CLKR0, CLKR1, CLKR2, FSR0, FSR1,  
FSR2, XCE[3:0], XBE[3:0]/XA[5:2], XOE, XRE, XWE/XWAIT, XAS, XW/R, XRDY, XBLAST, XHOLD,  
and XHOLDA.  
XD[31:0] are the boot configuration pins during device reset.  
Figure 24. Reset Timing  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
EXTERNAL INTERRUPT TIMING  
†
timing requirements for interrupt response cycles (see Figure 25)  
’C6202-200  
’C6202-233  
’C6202-250  
NO.  
UNIT  
MIN  
2P  
MAX  
2
3
t
t
Width of the interrupt pulse low  
Width of the interrupt pulse high  
ns  
ns  
w(ILOW)  
2P  
w(IHIGH)  
†
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.  
†
switching characteristics during interrupt response cycles (see Figure 25)  
’C6202-200  
’C6202-233  
’C6202-250  
NO.  
PARAMETER  
UNIT  
MIN  
9P  
0
MAX  
1
4
5
6
t
t
t
t
Response time, EXT_INTx high to IACK high  
Delay time, CLKOUT2 low to IACK valid  
Delay time, CLKOUT2 low to INUMx valid  
Delay time, CLKOUT2 low to INUMx invalid  
ns  
ns  
ns  
ns  
R(EINTH – IACKH)  
d(CKO2L-IACKV)  
d(CKO2L-INUMV)  
d(CKO2L-INUMIV)  
10  
10  
10  
0
0
†
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.  
1
CLKOUT2  
3
2
EXT_INTx, NMI  
Intr Flag  
4
4
IACK  
6
5
INUMx  
Interrupt Number  
Figure 25. Interrupt Timing  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
EXPANSION BUS SYNCHRONOUS FIFO TIMING  
timing requirements for synchronous FIFO interface (see Figure 26, Figure 27, and Figure 28)  
NO.  
5
MIN  
2.5  
MAX  
UNIT  
ns  
t
t
Setup time, read XDx valid before XFCLK high  
Hold time, read XDx valid after XFCLK high  
su(XDV-XFCKH)  
6
2
ns  
h(XFCKH-XDV)  
switching characteristics for synchronous FIFO interface (see Figure 26, Figure 27, and Figure 28)  
NO.  
1
PARAMETER  
MIN  
1.5  
MAX  
5.2  
5.2  
5.2  
5.2  
5.2  
5.2  
UNIT  
ns  
t
t
t
t
t
t
t
Delay time, XFCLK high to XCEx valid  
Delay time, XFCLK high to XBE[3:0]/XA[5:2] valid  
Delay time, XFCLK high to XOE valid  
Delay time, XFCLK high to XRE valid  
d(XFCKH-XCEV)  
d(XFCKH-XAV)  
d(XFCKH-XOEV)  
d(XFCKH-XREV)  
d(XFCKH-XWEV)  
d(XFCKH-XDV)  
d(XFCKH-XDIV)  
†
2
1.5  
1.5  
1.5  
1.5  
ns  
3
ns  
4
ns  
‡
7
Delay time, XFCLK high to XWE/XWAIT valid  
ns  
8
Delay time, XFCLK high to XDx valid  
Delay time, XFCLK high to XDx invalid  
ns  
9
1.5  
ns  
†
‡
XBE[3:0]/XA[5:2] operates as address signals XA[5:2] during synchronous FIFO accesses.  
XWE/XWAIT operates as the write enable signal XWE during synchronous FIFO accesses.  
XFCLK  
1
1
†
XCE3  
2
3
4
2
3
‡
XA1  
XA2  
XA3  
XA4  
XBE[3:0]/XA[5:2]  
XOE  
XRE  
4
§
XWE/XWAIT  
6
5
XD[31:0]  
FIFO read (glueless) mode only available in XCE3.  
XBE[3:0]/XA[5:2] operates as address signals XA[5:2] during synchronous FIFO accesses.  
XWE/XWAIT operates as the write enable signal XWE during synchronous FIFO accesses.  
D1  
D2  
D3  
D4  
†
‡
§
Figure 26. FIFO Read Timing (Glueless Read Mode)  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
EXPANSION BUS SYNCHRONOUS FIFO TIMING (CONTINUED)  
XFCLK  
XCEx  
1
2
3
4
1
2
3
†
XBE[3:0]/XA[5:2]  
XA1  
XA2  
XA3  
XA4  
XOE  
XRE  
4
‡
XWE/XWAIT  
6
5
XD[31:0]  
D1  
D2  
D3  
D4  
†
‡
XBE[3:0]/XA[5:2] operates as address signals XA[5:2] during synchronous FIFO accesses.  
XWE/XWAIT operates as the write enable signal XWE during synchronous FIFO accesses.  
Figure 27. FIFO Read Timing  
XFCLK  
1
1
XCEx  
2
2
†
XBE[3:0]/XA[5:2]  
XA1  
XA2  
XA3  
XA4  
XOE  
XRE  
7
8
7
‡
XWE/XWAIT  
9
XD[31:0]  
D1  
D2  
D3  
D4  
†
‡
XBE[3:0]/XA[5:2] operates as address signals XA[5:2] during synchronous FIFO accesses.  
XWE/XWAIT operates as the write enable signal XWE during synchronous FIFO accesses.  
Figure 28. FIFO Write Timing  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
EXPANSION BUS ASYNCHRONOUS PERIPHERAL TIMING  
†
timing requirements for asynchronous peripheral cycles (see Figure 29–Figure 30)  
’C6202-200  
’C6202-233  
’C6202-250  
NO.  
UNIT  
MIN MAX  
4
5
8
9
t
t
t
t
Setup time, read XDx valid before CLKOUT1 high  
Hold time, read XDx valid after CLKOUT1 high  
Setup time, XRDY valid before CLKOUT1 high  
Hold time, XRDY valid after CLKOUT1 high  
4.0  
0
ns  
ns  
ns  
ns  
su(XDV-CKO1H)  
h(CKO1H-XDV)  
su(XRY-CKO1H)  
h(CKO1H-XRY)  
4.0  
0
†
To ensure data setup time, simply program the strobe width wide enough. XRDY is internally synchronized. If XRDY does meet setup or hold  
time, it may be recognized in the current cycle or the next cycle. Thus, XRDY can be an asynchronous input.  
‡§¶  
switching characteristics for asynchronous peripheral cycles  
(see Figure 29–Figure 30)  
’C6202-200  
’C6202-233  
’C6202-250  
NO.  
PARAMETER  
UNIT  
MIN  
0
MAX  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
1
2
t
t
t
t
t
t
t
t
Delay time, CLKOUT1 high to XCEx valid  
Delay time, CLKOUT1 high to XBE[3:0]/XA[5:2] valid  
Delay time, CLKOUT1 high to XBE[3:0]/XA[5:2] invalid  
Delay time, CLKOUT1 high to XOE valid  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
d(CKO1H-XCEV)  
d(CKO1H-XAV)  
d(CKO1H-XAIV)  
d(CKO1H-XOEV)  
d(CKO1H-XREV)  
d(CKO1H-XDV)  
d(CKO1H-XDIV)  
d(CKO1H-XWEV)  
0
3
0
6
0
7
Delay time, CLKOUT1 high to XRE valid  
0
10  
11  
12  
Delay time, CLKOUT1 high to XDx valid  
Delay time, CLKOUT1 high to XDx invalid  
Delay time, CLKOUT1 high to XWE/XWAIT valid  
0
0
4.0  
‡
§
The minimum delay is also the minimum output hold after CLKOUT1 high.  
XBE[3:0]/XA[5:2] operates as address signals XA[5:2] during asynchronous peripheral accesses.  
XWE/XWAIT operates as the write enable signal XWE during asynchronous peripheral accesses.  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
EXPANSION BUS ASYNCHRONOUS PERIPHERAL TIMING (CONTINUED)  
Not ready = 2  
Setup = 2  
Strobe = 5  
HOLD = 2  
CLKOUT1  
XCEx  
1
2
1
3
†
XBE[3:0]/XA[5:2]  
5
4
XD[31:0]  
XOE  
6
6
7
7
XRE  
‡
XWE/XWAIT  
9
9
8
8
§
XRDY  
†
‡
§
XBE[3:0]/XA[5:2] operates as address signals XA[5:2] during asynchronous peripheral accesses.  
XWE/XWAIT operates as the write enable signal XWE during asynchronous peripheral accesses.  
XRDY operates as active-high ready input during asynchronous peripheral accesses.  
Figure 29. Expansion Bus Asynchronous Peripheral Read Timing  
Not ready = 2  
Setup = 2  
Strobe = 5  
HOLD = 2  
CLKOUT1  
XCEx  
1
2
1
3
†
XBE[3:0]/XA[5:2]  
10  
11  
XD[31:0]  
XOE  
XRE  
12  
12  
‡
XWE/XWAIT  
9
9
8
8
§
XRDY  
†
‡
§
XBE[3:0]/XA[5:2] operates as address signals XA[5:2] during asynchronous peripheral accesses.  
XWE/XWAIT operates as the write enable signal XWE during asynchronous peripheral accesses.  
XRDY operates as active-high ready input during asynchronous peripheral accesses.  
Figure 30. Expansion Bus Asynchronous Peripheral Write Timing  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
EXPANSION BUS SYNCHRONOUS HOST PORT TIMING  
timing requirements with external device as bus master (see Figure 31 and Figure 32)  
NO.  
1
MIN  
MAX  
UNIT  
ns  
t
t
t
t
t
t
t
t
t
t
Setup time, XCS valid before XCLKIN high  
Hold time, XCS valid after XCLKIN high  
Setup time, XAS valid before XCLKIN high  
Hold time, XAS valid after XCLKIN high  
Setup time, XCNTL valid before XCLKIN high  
Hold time, XCNTL valid after XCLKIN high  
4
su(XCSV-XCKIH)  
h(XCKIH-XCS)  
su(XAS-XCKIH)  
h(XCKIH-XAS)  
2
2.3  
4
ns  
3
ns  
4
2.3  
4
ns  
5
ns  
su(XCTL-XCKIH)  
h(XCKIH-XCTL)  
su(XWR-XCKIH)  
h(XCKIH-XWR)  
su(XBLTV-XCKIH)  
h(XCKIH-XBLTV)  
6
2.3  
4
ns  
†
7
Setup time, XW/R valid before XCLKIN high  
ns  
†
8
Hold time, XW/R valid after XCLKIN high  
Setup time, XBLAST valid before XCLKIN high  
2.3  
4
ns  
‡
9
ns  
‡
10  
Hold time, XBLAST valid after XCLKIN high  
Setup time, XBE[3:0]/XA[5:2] valid before XCLKIN high  
2.3  
ns  
§
16  
17  
18  
19  
t
t
t
t
4
2.3  
4
ns  
ns  
ns  
ns  
su(XBEV-XCKIH)  
h(XCKIH-XBEV)  
su(XD-XCKIH)  
h(XCKIH-XD)  
§
Hold time, XBE[3:0]/XA[5:2] valid after XCLKIN high  
Setup time, XDx valid before XCLKIN high  
Hold time, XDx valid after XCLKIN high  
2.3  
†
‡
§
XW/R input/output polarity selected at boot.  
XBLAST input polarity selected at boot.  
XBE[3:0]/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses.  
switching characteristics with external device as bus master (see Figure 31 and Figure 32)  
NO.  
11  
PARAMETER  
MIN  
MAX  
UNIT  
ns  
t
t
t
t
t
t
t
Delay time, XCLKIN high to XDx low impedance  
Delay time, XCLKIN high to XDx valid  
5
5
d(XCKIH-XDLZ)  
d(XCKIH-XDV)  
d(XCKIH-XDIV)  
d(XCKIH-XDHZ)  
d(XCKIH-XRY)  
d(XCKIH-XRYLZ)  
d(XCKIH-XRYHZ)  
12  
13  
14  
15  
20  
21  
15.5  
ns  
Delay time, XCLKIN high to XDx invalid  
Delay time, XCLKIN high to XDx high impedance  
ns  
18  
15.5  
15.5  
ns  
#
Delay time, XCLKIN high to XRDY valid  
5
5
ns  
Delay time, XCLKIN high to XRDY low impedance  
Delay time, XCLKIN high to XRDY high impedance  
ns  
#
2P + 5 3P + 15.5  
ns  
#
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.  
XRDY operates as active-low ready input/output during host-port accesses.  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
EXPANSION BUS SYNCHRONOUS HOST PORT TIMING (CONTINUED)  
XCLKIN  
2
4
6
8
8
1
3
5
XCS  
XAS  
XCNTL  
7
†
XW/R  
7
†
‡
XW/R  
XBE[3:0]/XA[5:2]  
10  
10  
9
9
§
XBLAST  
XBLAST  
§
13  
14  
12  
11  
D1  
15  
D2  
D3  
D4  
XD[31:0]  
21  
20  
15  
XRDY  
†
‡
§
XW/R input/output polarity selected at boot  
XBE[3:0]/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses.  
XBLAST input polarity selected at boot  
XRDY operates as active-low ready input/output during host-port accesses.  
Figure 31. External Host as Bus Master—Read  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
EXPANSION BUS SYNCHRONOUS HOST PORT TIMING (CONTINUED)  
XCLKIN  
2
4
6
8
8
1
3
5
7
7
XCS  
XAS  
XCNTL  
†
†
XW/R  
XW/R  
17  
16  
‡
XBE[3:0]/XA[5:2]  
XBLAST  
XBE1  
XBE2  
XBE3  
9
XBE4  
10  
10  
§
9
§
XBLAST  
19  
18  
D1  
15  
D2  
D3  
D4  
XD[31:0]  
21  
20  
15  
XRDY  
†
‡
§
XW/R input/output polarity selected at boot  
XBE[3:0]/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses.  
XBLAST input polarity selected at boot  
XRDY operates as active-low ready input/output during host-port accesses.  
Figure 32. External Host as Bus Master—Write  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
EXPANSION BUS SYNCHRONOUS HOST PORT TIMING (CONTINUED)  
timing requirements with ’C6202 as bus master (see Figure 33, Figure 34, and Figure 35)  
NO.  
9
MIN  
MAX  
UNIT  
ns  
t
t
t
t
t
t
Setup time, XDx valid before XCLKIN high  
Hold time, XDx valid after XCLKIN high  
Setup time, XRDY valid before XCLKIN high  
4
su(XDV-XCKIH)  
h(XCKIH-XDV)  
su(XRY-XCKIH)  
h(XCKIH-XRY)  
su(XBFF-XCKIH)  
h(XCKIH-XBFF)  
10  
11  
12  
14  
15  
2.3  
4
ns  
†
ns  
†
Hold time, XRDY valid after XCLKIN high  
2.3  
4
ns  
Setup time, XBOFF valid before XCLKIN high  
Hold time, XBOFF valid after XCLKIN high  
ns  
2.3  
ns  
†
XRDY operates as active-low ready input/output during host-port accesses.  
switching characteristics with ’C6202 as bus master (see Figure 33, Figure 34, and Figure 35)  
NO.  
1
PARAMETER  
Delay time, XCLKIN high to XAS valid  
Delay time, XCLKIN high to XW/R valid  
MIN  
MAX  
15.5  
15.5  
15.5  
15.5  
UNIT  
ns  
t
t
t
t
t
t
t
t
t
5
d(XCKIH-XASV)  
d(XCKIH-XWRV)  
d(XCKIH-XBLTV)  
d(XCKIH-XBEV)  
d(XCKIH-XDLZ)  
d(XCKIH-XDV)  
d(XCKIH-XDIV)  
d(XCKIH-XDHZ)  
d(XCKIH-XWTV)  
‡
2
5
5
5
5
ns  
§
3
Delay time, XCLKIN high to XBLAST valid  
ns  
4
Delay time, XCLKIN high to XBE[3:0]/XA[5:2] valid  
Delay time, XCLKIN high to XDx low impedance  
Delay time, XCLKIN high to XDx valid  
ns  
5
ns  
6
15.5  
ns  
7
Delay time, XCLKIN high to XDx invalid  
5
5
ns  
8
Delay time, XCLKIN high to XDx high impedance  
18  
ns  
#
13  
Delay time, XCLKIN high to XWE/XWAIT valid  
15.5  
ns  
‡
§
#
XW/R input/output polarity selected at boot.  
XBLAST output polarity is always active low.  
XBE[3:0]/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses.  
XWE/XWAIT operates as XWAIT output signal during host-port accesses.  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
EXPANSION BUS SYNCHRONOUS HOST PORT TIMING (CONTINUED)  
XCLKIN  
1
1
2
XAS  
2
3
†
†
XW/R  
XW/R  
3
‡
§
XBLAST  
4
4
XBE[3:0]/XA[5:2]  
BE  
5
9
7
6
8
10  
D2  
AD  
D1  
D3  
D4  
XD[31:0]  
XRDY  
11  
12  
13  
13  
XWE/XWAIT  
†
‡
§
XW/R input/output polarity selected at boot  
XBLAST output polarity is always active low.  
XBE[3:0]/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses.  
XWE/XWAIT operates as XWAIT output signal during host-port accesses.  
Figure 33. ’C6202 as Bus Master—Read  
XCLKIN  
XAS  
1
1
†
XW/R  
XW/R  
2
2
3
4
7
†
3
‡
XBLAST  
4
§
XBE[3:0]/XA[5:2]  
6
Addr  
5
8
D1  
D2  
11  
D3  
D4  
XD[31:0]  
XRDY  
12  
13  
13  
XWE/XWAIT  
†
‡
§
XW/R input/output polarity selected at boot  
XBLAST output polarity is always active low.  
XBE[3:0]/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses.  
XWE/XWAIT operates as XWAIT output signal during host-port accesses.  
Figure 34. ’C6202 as Bus Master—Write  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
EXPANSION BUS SYNCHRONOUS HOST PORT TIMING (CONTINUED)  
XCLKIN  
1
1
XAS  
†
XW/R  
2
2
†
‡
XW/R  
XBLAST  
4
4
7
§
XBE[3:0]/XA[5:2]  
6
5
8
Addr  
D1  
11  
D2  
XD[31:0]  
XRDY  
12  
15  
14  
XBOFF  
#
XHOLD  
XHOLDA  
XHOLD  
#
XHOLDA  
†
‡
§
#
||  
XW/R input/output polarity selected at boot  
XBLAST output polarity is always active low.  
XBE[3:0]/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses.  
Internal arbiter enabled  
External arbiter enabled  
This diagram illustrates XBOFF timing. Bus arbitration timing is shown in Figure 38 and Figure 39.  
||  
Figure 35. ’C6202 as Bus Master—BOFF Operation  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
EXPANSION BUS ASYNCHRONOUS HOST PORT TIMING  
†
timing requirements with external device as asynchronous bus master (see Figure 36 and  
Figure 37)  
NO.  
1
MIN  
4P  
MAX  
UNIT  
ns  
t
t
t
t
t
t
t
t
t
Pulse duration, XCS low  
Pulse duration, XCS high  
w(XCSL)  
2
4P  
2
ns  
w(XCSH)  
‡
3
Setup time, expansion bus select signals valid before XCS low  
ns  
su(XSEL-XCSL)  
h(XCSL-XSEL)  
h(XRYL-XCSL)  
su(XBEV-XCSH)  
h(XCSH-XBEV)  
su(XDV-XCSH)  
h(XCSH-XDV)  
‡
4
Hold time, expansion bus select signals valid after XCS low  
2
ns  
10  
11  
12  
13  
14  
Hold time, XCS low after XRDY low  
P
2
ns  
§
Setup time, XBE[3:0]/XA[5:2] valid before XCS high  
ns  
§
Hold time, XBE[3:0]/XA[5:2] valid after XCS high  
Setup time, XDx valid before XCS high  
Hold time, XDx valid after XCS high  
2
ns  
2
ns  
2
ns  
†
‡
§
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.  
Expansion bus select signals include XCNTL and XR/W.  
XBE[3:0]/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses.  
switching characteristics with external device as asynchronous bus master (see Figure 36 and  
Figure 37)  
NO.  
5
PARAMETER  
Delay time, XCS low to XDx low impedance  
Delay time, XCS high to XDx invalid  
Delay time, XCS high to XDx high impedance  
Delay time, XRDY low to XDx valid  
MIN  
MAX  
UNIT  
ns  
t
t
t
t
t
0
d(XCSL-XDLZ)  
d(XCSH-XDIV)  
d(XCSH-XDHZ)  
d(XRYL-XDV)  
d(XCSH-XRYH)  
6
0
12  
ns  
7
12  
4
ns  
8
0
0
ns  
9
Delay time, XCS high to XRDY high  
12  
ns  
1
1
2
10  
10  
XCS  
3
4
3
4
XCNTL  
†
XBE[3:0]/XA[5:2]  
3
4
3
3
4
4
‡
XR/W  
XR/W  
3
4
‡
7
6
7
6
5
8
5
8
Word  
XD[31:0]  
XRDY  
9
9
†
‡
XBE[3:0]/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses.  
XW/R input/output polarity selected at boot  
Figure 36. External Device as Asynchronous Master—Read  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
EXPANSION BUS ASYNCHRONOUS HOST PORT TIMING (CONTINUED)  
1
10  
2
10  
1
XCS  
3
3
4
4
XCNTL  
11  
11  
12  
12  
†
‡
‡
XBE[3:0]/XA[5:2]  
XR/W  
3
3
3
3
4
4
4
4
XR/W  
13  
13  
14  
9
14  
9
Word  
XD[31:0]  
XRDY  
†
‡
XBE[3:0]/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses.  
XW/R input/output polarity selected at boot  
Figure 37. External Device as Asynchronous Master—Write  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
XHOLD/XHOLDA TIMING  
†
timing requirements for expansion bus arbitration (internal arbiter enabled) (see Figure 38)  
NO.  
MIN  
MAX  
UNIT  
3
t
Output hold time, XHOLD high after XHOLDA high  
P
ns  
oh(XHDAH-XHDH)  
†
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.  
†‡  
switching characteristics for expansion bus arbitration (internal arbiter enabled) (see Figure 38)  
NO.  
1
PARAMETER  
MIN  
4P  
MAX  
UNIT  
ns  
§
t
t
t
t
Response time, XHOLD high to XBus high impedance  
Delay time, XBus high impedance to XHOLDA high  
Response time, XHOLD low to XHOLDA low  
Delay time, XHOLDA low to XBus low impedance  
R(XHDH-XBHZ)  
d(XBHZ-XHDAH)  
R(XHDL-XHDAL)  
d(XHDAL-XBLZ)  
2
0
4P  
0
2P  
ns  
4
ns  
5
2P  
ns  
†
‡
§
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.  
XBus consists of XBE[3:0]/XA[5:2], XAS, XW/R, and XBLAST.  
All pending XBus transactions are allowed to complete before XHOLDA is asserted.  
External Requestor  
DSP Owns Bus  
Owns Bus  
DSP Owns Bus  
3
XHOLD (input)  
2
4
XHOLDA (output)  
1
5
†
C6202  
C6202  
XBus  
†
XBus consists of XBE[3:0]/XA[5:2], XAS, XW/R, and XBLAST.  
Figure 38. Expansion Bus Arbitration—Internal Arbiter Enabled  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
XHOLD/XHOLDA TIMING (CONTINUED)  
switching characteristics for expansion bus arbitration (internal arbiter disabled) (see Figure 39)  
†
NO.  
1
PARAMETER  
MIN  
2P 2P + 10  
2P  
MAX  
UNIT  
ns  
‡
t
t
Delay time, XHOLDA high to XBus low impedance  
d(XHDAH-XBLZ)  
‡
2
Delay time, XBus high impedance to XHOLD low  
0
ns  
d(XBHZ-XHDL)  
†
‡
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.  
XBus consists of XBE[3:0]/XA[5:2], XAS, XW/R, and XBLAST.  
2
XHOLD (output)  
XHOLDA (input)  
1
†
XBus  
C6202  
†
XBus consists of XBE[3:0]/XA[5:2], XAS, XW/R, and XBLAST.  
Figure 39. Expansion Bus Arbitration—Internal Arbiter Disabled  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
MULTICHANNEL BUFFERED SERIAL PORT TIMING  
†‡  
timing requirements for McBSP (see Figure 40)  
’C6202-200  
’C6202-233  
’C6202-250  
NO.  
UNIT  
MIN  
2P  
P–1  
9
MAX  
2
3
t
t
Cycle time, CLKR/X  
CLKR/X ext  
CLKR/X ext  
CLKR int  
CLKR ext  
CLKR int  
CLKR ext  
CLKR int  
CLKR ext  
CLKR int  
CLKR ext  
CLKX int  
CLKX ext  
CLKX int  
CLKX ext  
ns  
ns  
c(CKRX)  
Pulse duration, CLKR/X high or CLKR/X low  
w(CKRX)  
5
6
t
t
t
t
t
t
Setup time, external FSR high before CLKR low  
Hold time, external FSR high after CLKR low  
Setup time, DR valid before CLKR low  
ns  
ns  
ns  
ns  
ns  
ns  
su(FRH-CKRL)  
h(CKRL-FRH)  
su(DRV-CKRL)  
h(CKRL-DRV)  
su(FXH-CKXL)  
h(CKXL-FXH)  
1
6
3
8
7
0
3
8
Hold time, DR valid after CLKR low  
3
9
10  
11  
Setup time, external FSX high before CLKX low  
Hold time, external FSX high after CLKX low  
1
6
3
†
‡
CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.  
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)  
†‡  
switching characteristics for McBSP (see Figure 40)  
’C6202-200  
’C6202-233  
’C6202-250  
NO.  
PARAMETER  
UNIT  
MIN  
MAX  
Delay time, CLKS high to CLKR/X high for internal  
CLKR/X generated from CLKS input  
1
t
4
10  
ns  
d(CKSH-CKRXH)  
§
2
3
4
t
t
t
Cycle time, CLKR/X  
CLKR/X int  
CLKR/X int  
CLKR int  
CLKX int  
CLKX ext  
CLKX int  
CLKX ext  
CLKX int  
CLKX ext  
2P  
ns  
ns  
ns  
c(CKRX)  
Pulse duration, CLKR/X high or CLKR/X low  
Delay time, CLKR high to internal FSR valid  
C – 1  
C + 1  
w(CKRX)  
–2  
–2  
3
3
3
9
4
9
4
9
d(CKRH-FRV)  
9
t
t
t
Delay time, CLKX high to internal FSX valid  
ns  
ns  
ns  
d(CKXH-FXV)  
dis(CKXH-DXHZ)  
d(CKXH-DXV)  
–1  
3
Disable time, DX high impedance following last data bit  
from CLKX high  
12  
13  
–1  
3
Delay time, CLKX high to DX valid  
Delay time, FSX high to DX valid  
FSX int  
FSX ext  
–1  
3
3
9
14  
t
ns  
d(FXH-DXV)  
ONLY applies when in data delay 0 (XDATDLY = 00b)  
mode.  
†
‡
§
CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.  
Minimum delay times also represent minimum output hold times.  
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.  
C = H or L  
S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)  
=
sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)  
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even  
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero  
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even  
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)  
CLKS  
1
2
3
3
CLKR  
FSR (int)  
FSR (ext)  
DR  
4
4
5
6
7
8
Bit(n-1)  
(n-2)  
(n-3)  
2
3
3
CLKX  
9
FSX (int)  
11  
10  
FSX (ext)  
FSX (XDATDLY=00b)  
13  
(n-2)  
14  
13  
12  
DX  
Bit 0  
Bit(n-1)  
(n-3)  
Figure 40. McBSP Timings  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)  
timing requirements for FSR when GSYNC = 1 (see Figure 41)  
’C6202-200  
’C6202-233  
’C6202-250  
NO.  
UNIT  
MIN  
4
MAX  
1
2
t
t
Setup time, FSR high before CLKS high  
Hold time, FSR high after CLKS high  
ns  
ns  
su(FRH-CKSH)  
4
h(CKSH-FRH)  
CLKS  
1
2
FSR external  
CLKR/X (no need to resync)  
CLKR/X(needs resync)  
Figure 41. FSR Timing When GSYNC = 1  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)  
†‡  
timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0 (see Figure 42)  
’C6202-200  
’C6202-233  
’C6202-250  
NO.  
UNIT  
MASTER  
SLAVE  
MIN MAX  
MIN  
12  
4
MAX  
4
5
t
t
Setup time, DR valid before CLKX low  
Hold time, DR valid after CLKX low  
2 – 3P  
5 + 6P  
ns  
ns  
su(DRV-CKXL)  
h(CKXL-DRV)  
†
‡
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.  
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.  
†‡  
switching characteristics for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0  
(see Figure 42)  
’C6202-200  
’C6202-233  
’C6202-250  
NO.  
PARAMETER  
UNIT  
§
MASTER  
SLAVE  
MIN  
MIN MAX  
MAX  
1
2
3
t
t
t
Hold time, FSX low after CLKX low  
T – 2 T + 3  
L – 2 L + 3  
ns  
ns  
ns  
h(CKXL-FXL)  
d(FXL-CKXH)  
d(CKXH-DXV)  
#
Delay time, FSX low to CLKX high  
Delay time, CLKX high to DX valid  
–2  
4
3P + 4 5P + 17  
Disable time, DX high impedance following last data bit from  
CLKX low  
6
t
L – 2 L + 3  
ns  
dis(CKXL-DXHZ)  
Disable time, DX high impedance following last data bit from  
FSX high  
7
8
t
t
P + 3 3P + 17  
2P + 2 4P + 17  
ns  
ns  
dis(FXH-DXHZ)  
Delay time, FSX low to DX valid  
d(FXL-DXV)  
†
‡
§
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.  
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.  
S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)  
=
sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)  
T = CLKX period = (1 + CLKGDV) * S  
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even  
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero  
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even  
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero  
FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX  
and FSR is inverted before being used internally.  
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP  
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP  
#
FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock  
(CLKX).  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)  
CLKX  
FSX  
1
2
8
7
6
3
DX  
DR  
Bit 0  
Bit(n-1)  
Bit(n-1)  
(n-2)  
(n-3)  
(n-4)  
4
5
Bit 0  
(n-2)  
(n-3)  
(n-4)  
Figure 42. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)  
†‡  
timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0 (see Figure 43)  
’C6202-200  
’C6202-233  
’C6202-250  
NO.  
UNIT  
MASTER  
SLAVE  
MIN MAX  
MIN  
12  
4
MAX  
4
5
t
t
Setup time, DR valid before CLKX high  
Hold time, DR valid after CLKX high  
2 – 3P  
5 + 6P  
ns  
ns  
su(DRV-CKXH)  
h(CKXH-DRV)  
†
‡
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.  
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.  
†‡  
switching characteristics for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0  
(see Figure 43)  
’C6202-200  
’C6202-233  
’C6202-250  
NO.  
PARAMETER  
UNIT  
§
MASTER  
SLAVE  
MIN  
MIN MAX  
MAX  
1
2
3
t
t
t
Hold time, FSX low after CLKX low  
L – 2 L + 3  
T – 2 T + 3  
ns  
ns  
ns  
h(CKXL-FXL)  
d(FXL-CKXH)  
d(CKXL-DXV)  
#
Delay time, FSX low to CLKX high  
Delay time, CLKX low to DX valid  
–2  
4
3P + 4 5P + 17  
3P + 3 5P + 17  
Disable time, DX high impedance following last data bit from  
CLKX low  
6
t
–2  
4
ns  
ns  
dis(CKXL-DXHZ)  
7
t
Delay time, FSX low to DX valid  
H – 2 H + 4  
2P + 2 4P + 17  
d(FXL-DXV)  
†
‡
§
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.  
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.  
S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)  
=
sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)  
T = CLKX period = (1 + CLKGDV) * S  
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even  
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero  
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even  
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero  
FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX  
and FSR is inverted before being used internally.  
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP  
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP  
#
FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock  
(CLKX).  
CLKX  
1
2
7
FSX  
DX  
6
3
Bit 0  
Bit(n-1)  
Bit(n-1)  
(n-2)  
(n-3)  
(n-3)  
(n-4)  
4
5
DR  
Bit 0  
(n-2)  
(n-4)  
Figure 43. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)  
†‡  
timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1 (see Figure 44)  
’C6202-200  
’C6202-233  
’C6202-250  
NO.  
UNIT  
MASTER  
SLAVE  
MIN MAX  
MIN  
12  
4
MAX  
4
5
t
t
Setup time, DR valid before CLKX high  
Hold time, DR valid after CLKX high  
2 – 3P  
5 + 6P  
ns  
ns  
su(DRV-CKXH)  
h(CKXH-DRV)  
†
‡
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.  
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.  
†‡  
switching characteristics for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1  
(see Figure 44)  
’C6202-200  
’C6202-233  
’C6202-250  
NO.  
PARAMETER  
UNIT  
§
MASTER  
SLAVE  
MIN  
MIN MAX  
MAX  
1
2
3
t
t
t
Hold time, FSX low after CLKX high  
T – 2 T + 3  
H – 2 H + 3  
ns  
ns  
ns  
h(CKXH-FXL)  
d(FXL-CKXL)  
d(CKXL-DXV)  
#
Delay time, FSX low to CLKX low  
Delay time, CLKX low to DX valid  
–2  
4
3P + 4 5P + 17  
Disable time, DX high impedance following last data bit from  
CLKX high  
6
t
H – 2 H + 3  
ns  
dis(CKXH-DXHZ)  
Disable time, DX high impedance following last data bit from  
FSX high  
7
8
t
t
P + 3 3P + 17  
2P + 2 4P + 17  
ns  
ns  
dis(FXH-DXHZ)  
Delay time, FSX low to DX valid  
d(FXL-DXV)  
†
‡
§
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.  
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.  
S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)  
=
sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)  
T = CLKX period = (1 + CLKGDV) * S  
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even  
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero  
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even  
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero  
FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX  
and FSR is inverted before being used internally.  
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP  
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP  
#
FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock  
(CLKX).  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)  
CLKX  
FSX  
1
2
8
7
6
3
DX  
DR  
Bit 0  
Bit(n-1)  
Bit(n-1)  
(n-2)  
(n-3)  
(n-4)  
4
5
Bit 0  
(n-2)  
(n-3)  
(n-4)  
Figure 44. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)  
†‡  
timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1 (see Figure 45)  
’C6202-200  
’C6202-233  
’C6202-250  
NO.  
UNIT  
MASTER  
SLAVE  
MIN MAX  
MIN  
12  
4
MAX  
4
5
t
t
Setup time, DR valid before CLKX low  
Hold time, DR valid after CLKX low  
2 – 3P  
5 + 6P  
ns  
ns  
su(DRV-CKXL)  
h(CKXL-DRV)  
†
‡
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.  
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.  
†‡  
switching characteristics for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1  
(see Figure 45)  
’C6202-200  
’C6202-233  
’C6202-250  
NO.  
PARAMETER  
UNIT  
§
MASTER  
SLAVE  
MIN  
MIN MAX  
MAX  
1
2
3
t
t
t
Hold time, FSX low after CLKX high  
H – 2 H + 3  
T – 2 T + 1  
ns  
ns  
ns  
h(CKXH-FXL)  
d(FXL-CKXL)  
d(CKXH-DXV)  
#
Delay time, FSX low to CLKX low  
Delay time, CLKX high to DX valid  
–2  
4
3P + 4 5P + 17  
3P + 3 5P + 17  
Disable time, DX high impedance following last data bit from  
CLKX high  
6
t
–2  
4
ns  
ns  
dis(CKXH-DXHZ)  
7
t
Delay time, FSX low to DX valid  
L – 2 L + 4  
2P + 2 4P + 17  
d(FXL-DXV)  
†
‡
§
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.  
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.  
S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)  
=
sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)  
T = CLKX period = (1 + CLKGDV) * S  
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even  
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero  
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even  
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero  
FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX  
and FSR is inverted before being used internally.  
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP  
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP  
#
FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock  
(CLKX).  
CLKX  
1
2
FSX  
DX  
7
6
3
Bit 0  
Bit 0  
Bit(n-1)  
Bit(n-1)  
(n-2)  
(n-3)  
(n-4)  
4
5
DR  
(n-2)  
(n-3)  
(n-4)  
Figure 45. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
DMAC, TIMER, POWER-DOWN TIMING  
†
switching characteristics for DMAC outputs (see Figure 46)  
’C6202-200  
’C6202-233  
’C6202-250  
NO.  
PARAMETER  
UNIT  
MIN  
MAX  
1
t
Pulse duration, DMAC high  
2P–3  
ns  
w(DMACH)  
†
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.  
1
DMAC[3:0]  
Figure 46. DMAC Timing  
†
timing requirements for timer inputs (see Figure 47)  
’C6202-200  
’C6202-233  
’C6202-250  
NO.  
UNIT  
MIN  
2P  
MAX  
1
2
t
t
Pulse duration, TINP high  
Pulse duration, TINP low  
ns  
ns  
w(TINPH)  
2P  
w(TINPL)  
†
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.  
†
switching characteristics for timer outputs (see Figure 47)  
’C6202-200  
’C6202-233  
’C6202-250  
NO.  
PARAMETER  
UNIT  
MIN  
2P–3  
2P–3  
MAX  
3
4
t
t
Pulse duration, TOUT high  
Pulse duration, TOUT low  
ns  
ns  
w(TOUTH)  
w(TOUTL)  
†
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.  
2
1
TINPx  
4
3
TOUTx  
Figure 47. Timer Timing  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
DMAC, TIMER, POWER-DOWN TIMING (CONTINUED)  
†
switching characteristics for power-down outputs (see Figure 48)  
’C6202-200  
’C6202-233  
’C6202-250  
NO.  
PARAMETER  
UNIT  
MIN  
MAX  
1
t
Pulse duration, PD high  
10P  
ns  
w(PDH)  
†
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.  
1
PD  
Figure 48. Power-Down Timing  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
JTAG TEST-PORT TIMING  
timing requirements for JTAG test port (see Figure 49)  
’C6202-200  
’C6202-233  
’C6202-250  
NO.  
UNIT  
MIN  
MAX  
50  
1
3
4
t
t
t
Cycle time, TCK  
ns  
ns  
ns  
c(TCK)  
Setup time, TDI/TMS/TRST valid before TCK high  
Hold time, TDI/TMS/TRST valid after TCK high  
10  
5
su(TDIV-TCKH)  
h(TCKH-TDIV)  
switching characteristics for JTAG test port (see Figure 49)  
’C6202-200  
’C6202-233  
’C6202-250  
NO.  
PARAMETER  
UNIT  
MIN  
MAX  
15  
2
t
Delay time, TCK low to TDO valid  
0
ns  
d(TCKL-TDOV)  
1
TCK  
TDO  
2
2
4
3
TDI/TMS/TRST  
Figure 49. JTAG Test-Port Timing  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
MECHANICAL DATA  
GJL (S-PBGA-N352)  
PLASTIC BALL GRID ARRAY  
27,20  
26,80  
SQ  
SQ  
25,20  
24,80  
25,00 TYP  
1,00  
16,30 NOM  
0,50  
AF  
AD  
AB  
Y
AE  
AC  
AA  
W
U
V
T
R
P
N
M
K
L
J
H
G
F
E
D
C
B
A
1
3
5
7
9
11 13 15 17 19 21 23 25  
2
4
6
8
10 12 14 16 18 20 22 24 26  
Heat Slug  
See Note E  
3,50 MAX  
1,00 NOM  
Seating Plane  
0,15  
0,70  
0,50  
M
∅ 0,10  
0,60  
0,40  
4173516-2/C 07/99  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Thermally enhanced plastic package with heat slug (HSL).  
D. Flip chip application only  
E. Possible protrusion in this area, but within 3,50 max package height specification  
F. Falls within JEDEC MO-151/AAL-1  
thermal resistance characteristics (S-PBGA package)  
†
NO  
°C/W  
0.47  
14.2  
12.3  
10.2  
8.6  
Air Flow LFPM  
1
2
3
4
5
RΘ  
RΘ  
RΘ  
RΘ  
RΘ  
Junction-to-case  
N/A  
0
JC  
JA  
JA  
JA  
JA  
Junction-to-free air  
Junction-to-free air  
Junction-to-free air  
Junction-to-free air  
100  
250  
500  
†
LFPM = Linear Feet Per Minute  
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TMS320C6202  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999  
MECHANICAL DATA  
GLS (S-PBGA-N384)  
PLASTIC BALL GRID ARRAY  
18,10  
17,90  
SQ  
16,80 TYP  
0,80  
0,40  
AB  
Y
AA  
W
U
R
N
L
V
T
P
M
K
H
F
J
G
E
D
B
C
A
1
3
5
7
9
11 13 15 17 19 21  
2
4
6
8
10 12 14 16 18 20 22  
Heat Slug  
2,80 MAX  
1,00 NOM  
Seating Plane  
0,15  
0,55  
0,45  
M
0,10  
0,45  
0,35  
4188959/B 12/98  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Thermally enhanced plastic package with heat slug (HSL)  
D. Flip chip application only  
thermal resistance characteristics (S-PBGA package)  
†
NO  
°C/W  
0.85  
21.6  
17.9  
14.2  
11.8  
Air Flow LFPM  
1
2
3
4
5
RΘ  
RΘ  
RΘ  
RΘ  
RΘ  
Junction-to-case  
N/A  
0
JC  
JA  
JA  
JA  
JA  
Junction-to-free air  
Junction-to-free air  
Junction-to-free air  
Junction-to-free air  
100  
250  
500  
†
LFPM = Linear Feet Per Minute  
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