User’s Guide
April 2001
Mixed-Signal Products
SLOU061A
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Preface
Related Documentation From Texas Instruments
Amplifiers and Comparators Data Book (literature number
SLOD002). This data book contains data sheets and other
information on the TI operational amplifiers that can be used with this
evaluation module.
Power Supply Circuits Data Book (literature number SLVD002).
This data book contains data sheets and other information on the TI
shunt regulators that can be used with this evaluation module.
FCC Warning
This equipment is intended for use in a laboratory test environment only. It
generates, uses, and can radiate radio frequency energy and has not been
tested for compliance with the limits of computing devices pursuant to subpart
J of part 15 of FCC rules, which are designed to provide reasonable protection
against radio frequency interference. Operation of this equipment in other
environments may cause interference with radio communications, in which
case the user at his own expense will be required to take whatever measures
may be required to correct this interference.
Trademarks
PowerPAD is a trademark of Texas Instruments.
iii
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Contents
1
2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.1
1.2
Design Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Evaluation Module Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1
2.2
2.3
2.4
2.5
2.6
2.7
Physical Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Area 100—Single Device SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Area 200—Dual Device SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Area 300—Quad Device SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
General Power Dissipation Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
EVM Component Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
EVM Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
3
Example Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
Schematic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Inverting Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Noninverting Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Differential Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Sallen-Key Low-Pass Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
Sallen-Key High-Pass Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
Two Operational Amplifier Instrumentation Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
Quad Operational Amplifier Instrumentation Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
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Figures
2–1
2–2
2–3
2–4
2–5
2–6
2–7
Area 100 Schematic—Single Device, SOIC (8-pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Area 200 Schematic—Dual Device, SOIC (14-pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Area 300 Schematic—Quad Device, SOIC (16-pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Maximum Power Dissipation vs Free-Air Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
EVM Component Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
EVM Board Layout—Top . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
EVM Board Layout—Bottom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
3–1
3–2
3–3
3–4
3–5
3–6
3–7
Inverting Amplifier with Dual Supply Using Area 100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Noninverting Amplifier with Single Supply Using Area 100 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Single Operational Amplifier Differential Amplifier With Single Supply Using Area 100 . . 3-4
Sallen-Key Low-Pass Filter With Dual Supply Using Area 200 . . . . . . . . . . . . . . . . . . . . . . . 3-5
Sallen-Key High-Pass Filter With Single Supply Using Area 200 . . . . . . . . . . . . . . . . . . . . . 3-7
Two Operational Amplifier Instrumentation Amplifier With Single Supply Using Area 200 3-9
Quad Operational Amplifier Instrumentation Amplifier With Dual Supply Using Area 300 3-11
Table
2–1
Dissipation Rating Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
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Chapter 1
Introduction
This user’s guide describes the universal operational amplifier single, dual,
quad (SOIC) evaluation module (EVM) with shutdown (SLOP248). The EVM
simplifies evaluation of Texas Instruments surface-mount op amps with or
without shutdown feature.
Topic
Page
1.1 Design Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
1.2 Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
1-1
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Design Features
1.1 Design Features
The EVM board design allows many circuits to be constructed easily and
quickly. There are three circuit development areas on the board, and each
uses IC amplifiers in the SOIC package. Area 100 is for a single operational
amplifier (op amp), with or without shutdown. It also features offset nulling pin
pads. Area 200 is for a dual op amp, with or without shutdown. Area 300 is for
a quad op amp, with or without shutdown. A few possible circuits include:
Voltage follower
Noninverting amplifier
Inverting amplifier
Simple or algebraic summing amplifier
Difference amplifier
Current to voltage converter
Voltage to current converter
Integrator/low-pass filter
Differentiator/high-pass filter
Instrumentation amplifier
Sallen-Key filter
The EVM PCB is of two-layer construction, with a ground plane on the solder
side. Circuit performance should be comparable to final production designs.
1.2 Power Requirements
The devices and designs that are used dictate the input power requirements.
Three input terminals are provided for each area of the board:
Vx+
GNDx
Vx–
Positive input power for area x00 i.e., V1+ ⇒ area 100
Ground reference for area x00 i.e., GND2 ⇒ area 200
Negative input power for area x00 i.e., V3– ⇒ area 300
Each area has four bypass capacitors – two for the positive supply, and two
for the negative supply. Each supply should have a 1-µF to 10-µF capacitor for
low-frequency bypassing and a 0.01-µF to 0.1-µFcapacitorforhigh-frequency
bypassing.
When using single-supply circuits, the negative supply is shorted to ground by
bridgingC104orC105inarea100, C209orC210inarea200, orC311orC312
in area 300. Power input is between Vx+ and GNDx. The voltage reference
circuitry is provided for single-supply applications that require a reference
voltage to be generated.
1-2
Introduction
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Chapter 2
Evaluation Module Layout
This chapter shows the universal operational amplifier single, dual, quad
(SOIC) evaluation module (EVM) with shutdown board layout, schematics of
each area, and describes the relationships between the three areas.
Topic
Page
2.1 Physical Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
2.2 Area 100—Single Device SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3
2.3 Area 200—Dual Device SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
2.4 Area 300—Quad Device SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
2.5 General Power Dissipation Considerations . . . . . . . . . . . . . . . . . . . . . . 2–7
2.6 Component Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8
2.7 Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9
2-1
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Physical Considerations
2.1 Physical Considerations
The EVM board has three circuit development areas. Each area can be
separated from the others by breaking along the score lines. The circuit layout
in each area supports an op amp package, voltage reference, and ancillary
devices. The op amp package is unique to each area as described in the
following paragraphs. The voltage reference and supporting devices are the
same for all areas. Surface-mount or through-hole components can be used
for all capacitors and resistors on the board.
The voltage reference can be either surface-mount or through-hole. If
surface-mount is desired, the TLV431ACDBV5 or TLV431AIDBV5 adjustable
shunt regulators can be used. If through hole is desired, the TLV431ACLP,
TLV431AILP, TL431CLP, TL431ACLP, TL431ILP, or TL431AILP adjustable
shunt regulators can be used. Refer to Texas Instruments’ Power Supply
Circuits Data Book (literature number SLVD002) for details on usage of these
shunt regulators.
Each passive component (resistor or capacitor) has a surface mount 1206
footprint with through holes at 0.2″ spacing on the outside of the 1206 pads.
C105, C106, C107, C207, C208, C209, C312, C314, and C315 have a surface
mount 1210 footprint with through holes at 0.2″ spacing on the outside of the
1210 pads. Therefore, either surface-mount or through-hole parts can be
used. The potentiometer for the offset nulling feature in area 100 can also be
either a surface-mount or a through-hole unit.
Figures 2–1 through 2–3 show schematics for each of the board areas. The
schematics show all components that the board layout can accommodate.
These should only be used as reference, since not all components will be used
at any one time.
2-2
Evaluation Module Layout
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Physical Considerations
2.2 Area 100—Single Device SOIC
Area 100 uses 1xx reference designators, and is compatible with a single op
amp, with or without shutdown, packaged as an 8-pin SOIC. This
surface-mount package is designated by a D suffix in TI part numbers, as in
TxxxxCD, TxxxxID, etc.
Offset nulling can be extremely important in some applications. The EVM
accommodates TI IC op amps that provide this feature. The input offset can
be adjusted by connecting a 100-kΩ potentiometer between terminals 1 and
5 of the device and connecting the wiper to VCC– via a resistor (R101) as
shown below. This resistor is used to fine tune the offset adjustment. For
example, when using the TLC070 or TLC071 device and a 100-kΩ nulling
potentiometer, the offset voltage adjustment is ±10 mV when R101 is 5.6 kΩ
and ±3 mV when R101 is 20 kΩ.
When using the nonshutdown version of the device, pin 8 of the IC is a no
connect.
Figure 2–1 shows the area 100 schematic.
Figure 2–1. Area 100 Schematic—Single Device, SOIC (8 pin)
C110
V1+
R114
V1+
R112
V1+
C109
R110
C107
C108
A101–
GND1
U101
R109
R103
7
–
SD
OUT
2
8
C105
C104
A102–
6
R104
3
+
V1–
5
A103+
4
1
Power Supply Bypass
R108
A104+
V1–
V1–
R107
R102
R105
R106
A1 FLT
C103
V1+
VREF1
C101
R111
U102
R101
C102
V1–
C106
R113
Voltage Reference
2-3
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Physical Considerations
2.3 Area 200—Dual Device SOIC
Area 200 uses 2xx reference designators, and is compatible with dual op
amps, with or without shutdown, packaged as an 8-pin (without shutdown) or
14-pin (with shutdown) SOIC. This package is designated by a D suffix in TI
part numbers, as in TxxxxCD.
When using the nonshutdown version of the device, ensure that the IC is
aligned at the top of the IC pad array—the last six PCB pads (three on each
side—pins 5, 6, 7, 8, 9, and 10) will not be used.
Figure 2–2 shows the area 200 schematic.
Figure 2–2. Area 200 Schematic—Dual Device, SOIC (14 pin)
C211
R216
V2+
R212
V2+
C215
R221
A201–
V2+
6
14
–
R220
R219
C206
C207
A2/SD
2
A202–
1
GND2
R218
A2OUT
3
+
4
A203+
U201a
1/2 Dual Op Amp
C209
C210
A204+
V2–
V2–
R217
R214
A2 FLT
C214
V2–
Power Supply Bypass
C212
R215
C213
R210
C203
R207
C202
V2+
VREF2
R211
U202
R206
R204
B201–
9
C208
B2/SD
R203
R201
12
11
R213
–
B202–
13
U201b
R205
B2OUT
+
B203+
1/2 Dual Op Amp
Voltage Reference
B204+
R202
R208
B2 FLT
C205
R209
C204
C201
2-4
Evaluation Module Layout
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Physical Considerations
2.4 Area 300—Quad Device SOIC
Area 300 uses 3xx reference designators, and is compatible with quad op
amps, with or without shutdown, packaged in a 14-pin (without shutdown) or
16-pin (with shutdown) SOIC. This surface-mount package is designated by
a D suffix in TI part numbers, as in TxxxxID.
When using the nonshutdown version of the device, ensure that the IC is
aligned at the top of the IC pad array—the last two PCB pads (one on each
side—pins 8 and 9) will not be used.
Figure 2–3 shows the area 300 schematic.
2-5
Evaluation Module Layout
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Physical Considerations
Figure 2–3. Area 300 Schematic—Quad Device SOIC (16 pin)
C302
R302
V3+
R304
V3+
C313
C314
C301
R301
A301–
GND3
V3+
4
R303
R306
C311
C312
AB3/SD
A3 OUT
2
3
8
–
A302–
1
V3–
R305
+
A303+
U301A
V3–
Power Supply Bypass
13
A304+
V3–
R308
R309
C310
R318
R314
C308
A3 FLT
C305
R307
C304
R310
B301–
C303
R312
R313
6
5
–
B302–
7
B3 OUT
R317
+
B303+
U301B
B304+
R315
R316
B3 FLT
C306
R311
C307
C317
R323
C316
R325
C309
R322
C301–
R324
R327
CD3/SD
C3 OUT
11
12
9
–
C302–
10
R326
+
C303+
C324
U301C
R331
C321
C304+
R329
R339
R330
R332
C3 FLT
C320
D301–
R328
C318
R333
R335
15
14
–
D302–
16
U301D
D3 OUT
R334
C319
+
D303+
D304+
R336
R338
R321
D3 FLT
C323
V1+
VREF3
R337
C322
R320
R319
U302
C325
C315
Voltage Reference
2-6
Evaluation Module Layout
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General Power Dissipation Considerations
2.5 General Power Dissipation Considerations
For a given θ , the maximum power dissipation is shown in Figure 2–4 and is calculated by the
JA
following formula:
T
–T
MAX
A
P
D
JA
Where:
P
= Maximum power dissipation of Txxxx IC (watts)
= Absolute maximum junction temperature (150°C)
= Free-air temperature (°C)
D
T
MAX
T
A
θ
= θ + θ
JC CA
JA
θ
= Thermal coefficient from junction to case
= Thermal coefficient from case to ambient air (°C/W)
JC
θ
CA
Figure 2–4. Maximum Power Dissipation vs Free-Air Temperature
MAXIMUM POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
2
SOIC (16-pin)
Package
T
= 150°C
J
Low-K Test PCB
θ
= 114.7°C/W
JA
1.5
SOIC (8-pin)
Package
Low-K Test PCB
1
0.5
0
SOIC (14-pin)
Package
Low-K Test PCB
–55
–25
5
35
65
95
125
T
A
– Free-Air Temperature – °C
NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB.
Table 2–1.Dissipation Rating Table
θ
θ
T
A
≤ 25°C
JC
JA
PACKAGE
(°C/W)
(°C/W)
POWER RATING
D (8)
D (14)
D (16)
38.3
176
710 mW
26.9
122.3
114.7
1022 mW
25.7
1090 mW
2-7
Evaluation Module Layout
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EVM Component Placement
2.6 EVM Component Placement
Figure 2–5 shows component placement for the EVM board.
Figure 2–5. EVM Component Placement
2-8
Evaluation Module Layout
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EVM Board Layout
2.7 EVM Board Layout
Figures 2–6 and 2–7 show the EVM top and bottom board layouts,
respectively.
Figure 2–6. EVM Board Layout—Top
2-9
Evaluation Module Layout
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EVM Board Layout
Figure 2–7. EVM Board Layout—Bottom
2-10
Evaluation Module Layout
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Chapter 3
Example Circuits
This chapter shows and discusses several example circuits that can be
constructed using the universal operational amplifier EVM. The circuits are all
classic designs that can be found in most operational amplifier design books.
Topic
Page
3.1 Schematic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2
3.2 Inverting Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2
3.3 Noninverting Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3
3.4 Differential Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4
3.5 Sallen-Key Low-Pass Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5
3.6 Sallen-Key High-Pass Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6
3.7 Two Operational Amplifier Instrumentation Amplifier . . . . . . . . . . . . 3–8
3.8 Quad Operational Amplifier Instrumentation Amplifier . . . . . . . . . 3–10
3-1
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Schematic Conventions
3.1 Schematic Conventions
Figures 3–1 through 3–6 show schematic examples of circuits that can be
constructed using the universal operational amplifier EVM with shutdown. The
components that are placed on the board are shown in bold. Unused
components are blanked out. Jumpers and other changes are noted. These
examples are only a few of the many circuits that can be built.
3.2 Inverting Amplifier
Figure 3–1 shows area 100 equipped with a single operational amplifier
configured as an inverting amplifier using dual power supplies.
Basic setup is done by choice of input and feedback resistors. The transfer
function for the circuit as shown is:
R112
R109
V
V
OUT
IN
To cancel the effects of input bias current, set R105 = R112 || R109, or use a
0-Ω jumper for R105 if the operational amplifier is a low input bias operational
amplifier.
Figure 3–1. Inverting Amplifier With Dual Supply Using Area 100
C110
R114
V1+
R112
V1+
C109
R110
R112
R109
A101–
V1+
V
= –V
OUT
IN
SD
A OUT
C107
0.1 µF
C108
10 µF
8
R109
R103
7
2
–
A102–
6
R104
GND1
3
+
4
A103+
U101
C105
0.1 µF
C104
10 µF
R102
R105 = R112 II R109,
or Short if Using Low
Input Bias Op Amp
A104–
+
V1–
V1–
V
in
V1–
–
Power Supply Bypass
R105
C101
R106
A1 FLT
C103
V1+
C102
R108
VREF1
2
–
6
3
+
1
5
R111
C
R107
C106
Optional
U102
R
100 k
5.6 k
A
R113
R101
V1–
Voltage Reference
Not Used
3-2
Example Circuits
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Noninverting Amplifier
3.3 Noninverting Amplifier
Figure 3–2 shows area 100 equipped with a single operational amplifier
configured as a noninverting amplifier with single-supply power input.
Basic setup is done by choice of input and feedback resistors. The transfer
function for the circuit as shown is:
R112
R109
V
V
1
VREF1
OUT
IN
The input signal must be referenced to VREF1.
To cancel the effects of input bias current, set R102 = R112 || R109, or use a
0-Ω jumper for R102 if the operational amplifier is a low input bias operational
amplifier.
The TL431 adjustable precision shunt regulator, configured as shown,
provides a low impedance reference for the circuit at about 1/2 V1+ in a 3 V
system. Another option is to adjust resistors R113 and R111 for the desired
VREF1 voltage. The formula for calculating VREF1 is:
R111 R113
VREF1
1.24 V
R113
Figure 3–2. Noninverting Amplifier With Single Supply Using Area 100
V1+
R114
C109
C110
V1+
R112
V1+
C107
C108
R110
R109
0.1 µF
10 µF
R112
R109
A101+
V
= V
1 +
+ VREF4
OUT IN(
)
GND1
Jumper 102 – to VREF1
7
8
C104
2
3
C105
SD
1 OUT
–
A102–
6
R104
V1–
R103
R102
+
4
A103+
U101
Power Supply Bypass
V1+
V1–
A104–
V1–
+
C101
R105
V
in
R108
2.2 kΩ
R106
–
1 FLT
C103
VREF1 = 1.24 V
C102
C106
10 µF
R111
C
R102 = R112 II R109,
or Short if Using Low Input
Bias Op Amp
Input Signal With
Reference to VREF1
U102 = TLV431ACDBV5
R
A
2
–
6
5
R113
3
+
1
Voltage Reference
R107
100 k
Optional
R101
V1–
5.6 k
3-3
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Differential Amplifier
3.4 Differential Amplifier
Figure 3–3 shows area 100 equipped with a single operational amplifier
configured as a differential amplifier using a voltage reference and single
power supply.
Basic setup is done by choice of input and feedback resistors. The transfer
function for the circuit as shown is:
R112
IN
R109
V
V
VREF1
OUT
Where:
R102
R103
R112
R109
The TLV431 adjustable precision shunt regulator, configured as shown,
provides a low impedance reference for the circuit at about 1/2 V1+ in a 3-V
system. Another option is to adjust resistors R111 and R113 for the desired
VREF1 voltage. The formula for calculating VREF1 is:
R111 R113
VREF1
1.24 V
R113
Figure 3–3. Single Operational Amplifier Differential Amplifier With Single Supply Using
Area 100
R114
C109
C110
R112
V1+
R110
101–
V1+
R112
V
= V
in
+ V
REF1
V1+
7
–
out
(R109 )
C107
0.1 µF
C108
10 µF
R109
R103
8
+
2
1/SD
1OUT
102–
6
R104
GND1
V
in
3
+
4
103+
U101
–
C105
Jumper
C104
R102
104+
V1–
V1–
R112
R109
R102
R103
=
Power Supply Bypass
V1+
V1–
C101
R105
R106
A1 FLT
C103
R108
2.2 kΩ
C102
VREF1 = 1.24 V
Jumper 104+ to VREF1
R111
C106
10 µF
C
A
U102
TLV431ACDBV5
R
R113
Voltage Reference
3-4
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Sallen-Key Low-Pass Filter
3.5 Sallen-Key Low-Pass Filter
Figure 3–4 shows area 200 equipped with a dual operational amplifier
configured as a second-order Sallen-Key low-pass filter using dual-power
supplies.
Basic setup is done by proper choice of resistors R and mR, and capacitors
C and nC. The transfer function is:
V
OUT
1
2
V
IN
j
Q
f
o
f
o
1
f
f
Where:
And
1
f
o
2
m nRC
m n
Q
m
1
Figure 3–4. Sallen-Key Low-Pass Filter Wwith Dual Supply Using Area 200
R216
C211
R212
Jumper
V2+
C215
V2+
R221
A201–
V
V
1
out
in
=
2
1– (f/fo) + (j/Q)(f/fo)
V2+
6
C206
0.1 µ F
C207
10 µ F
14
–
R220
A2/SD
2
A202–
1
R218
R
GND2
R219
mR
A2OUT
1/2 Dual Op Amp
3
+
U201A
A203+
4
C209
0.1 µ F
C210
10 µ F
A204+
V2–
1
V2–
R217
fo =
Q =
2π √mn RC
+
V2–
√mn
m+1
Power Supply Bypass
C212
V
R215
in
–
R214
A2 FLT
C214
C213
nC
V2+
R207
C202
C203
R210
R206
VREF2
R204
R203
Jumper
B201–
R211
C
9
B2/SD
12
11
C208
–
B202–
U202
13
R205
B2OUT
R
A
R201
R202
+
U201B
B203+
1/2 Dual Op Amp
R213
B204+
Not Used
R209
Voltage Reference
Not Used
R208
C204
B2 FLT
C205
C201
3-5
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Sallen-Key High-Pass Filter
3.6 Sallen-Key High-Pass Filter
Figure 3–5 shows area 200 equipped with a dual operational amplifier
configured as a second-order Sallen-Key high-pass filter using single-supply
power input.
Basic setup is done by proper choice of resistors R and mR, and capacitors
C and nC. Note that capacitors should be used for components R201 and
R205, and a resistor for C201. The transfer function for the circuit as shown
is:
2
f
f
o
VOUT
VIN
VREF2
2
j
Q
f
f
o
1
f
f
o
Where:
And
1
f
o
2
n
m n RC
m n
Q
1
The TL431 adjustable precision shunt regulator, configured as shown,
provides a low impedance reference for the circuit at about 1/2 V2+ in a 5 V
system. Another option is to adjust resistors R211 and R213 for the desired
VREF2 voltage. The formula for calculating VREF2 is:
R211 R213
VREF2
2.50 V
R213
3-6
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Sallen-Key High-Pass Filter
Figure 3–5. Sallen-Key High-Pass Filter With Single Supply Using Area 200
R216
C211
V2+
R212
R221
C215
Jumper
A201–
V2+
V2+
14
–
6
C206
0.1 µF
C207
10 µF
R220
R219
A2/SD
2
A202–
1
GND2
A2OUT
R218
3
+
A203+
U201A
4
1/2 Dual Op Amp
Not Used
C210
C209
R217
A204+
V2–
V2–
V2–
Power Supply Bypass
R215
C212
R214
A2 FLT
C213
C214
R207
C202
C203
R206
Jumper
9
VREF2 = 2.5 V
V2+
R204
2
–(f/fo)
B201–
V
= V
+ VREF2
OUT
IN
2
1+(j/Q)(f/fo) – (f/fo)
R203
R202
12
B2/SD
B2OUT
R210
2.2 kΩ
–
B202–
13
U201B
11
+
B204+
1/2 Dual Op Amp
fo =
mR
R201
R205
nC
R211
C208
10 µF
1
C
A
B203+
2π √mn RC
U202
C
R
√mn
m+1
TL431ACLP
+
Q =
C204
R209
R213
V
in
R208
–
B2 FLT
C205
C201
R
Jumper B204 + to VREF2
Voltage Reference
3-7
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Two Operational Amplifier Instrumentation Amplifier
3.7 Two Operational Amplifier Instrumentation Amplifier
Figure 3–6 shows area 200 equipped with a dual operational amplifier
configured as a two-operational-amplifier instrumentation amplifier using a
voltage reference and single power supply.
Basic setup is done by choice of input and feedback resistors. The transfer
function for the circuit as shown is:
2R212 R212
V
V
1
VREF2
OUT
IN
R220
R221
Where:
R212 = R206 and R221 = R203
To cancel the effects of input bias current, set R217 = R212 || R220 and set
R202 = R206 ||R203, or use a 0-Ω jumper for R217 and R202 if the operational
amplifier is a low input bias operational amplifier.
The TLV431 adjustable precision shunt regulator, configured as shown,
provides a low impedance reference for the circuit at about 1/2 V2+ in a 3 V
system. Another option is to adjust resistors R211 and R213 for the desired
VREF2 voltage. The formula for calculating VREF2 is:
R211 R213
VREF2
1.24 V
R213
3-8
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Two Operational Amplifier Instrumentation Amplifier
Figure 3–6. Two Operational Amplifier Instrumentation Amplifier Wwith Single Supply
Using
Area 200
C211
R216
Jumper A201 – to B2OUT
R212
C215
R221
R217 = R212 II R220
or Short if Using Low Input
Bias Op Amp
2R212
R220
R212
R221
A201–
V
= Vin(1+
+
)+ V
OUT
REF2
Jumper
R218
V2+
14
–
R220
R219
6
1
2
A2/SD
A2OUT
A202–
V2+
3
+
A203+
U201A
4
1/2 Dual Op Amp
R217
V2+
A204+
V2–
R212 = R206
R221 = R203
C206
C207
0.1 µF
10 µF
GND2
C212
R215
C213
R214
Jumper
A202– to B201–
C209
C210
A2 FLT
C214
V2–
+
V2–
Power Supply Bypass
V2+
V
in
–
C203
R206
R207
C202
Jumper VREF2 to B202–
R204
R210
2.2 kΩ
B201–
VREF2 = 1.24 V
Jumper
R203
Jumper
R205
9
12
11
B2/SD
B2OUT
–
B202–
R211
13
R201
C208
10 µF
C
A
B203+
+
U201B
1/2 Dual Op Amp
U202
R
TLV431ACDBV5
R202
B204+
R213
R202 = R206 II R203
or Short if Using Low Input
Bias Op Amp
R209
Voltage Reference
R208
C204
B2 FLT
C205
C201
3-9
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Quad Operational Amplifier Instrumentation Amplifier
3.8 Quad Operational Amplifier Instrumentation Amplifier
Figure 3–7 shows area 300 equipped with a quad operational amplifier
configured as a quad-operational-amplifier instrumentation amplifier using a
dual power supply.
Basic setup is done by choice of input and feedback resistors. The transfer
function for the circuit as shown is:
(
)
R303 2 R302
R325
R309
V
V
V
INA
OUT
INB
R303
Where:
R302 = R318, R309 = R316, and R325 = R329
(
)
R303 2 R302
R325
R309
A
101 as shown
V
R303
To cancel the effects of offset errors, adjust V (D304+) by applying an extra
adj
signal.
3-10
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Quad Operational Amplifier Instrumentation Amplifier
Figure 3–7. Quad Operational Amplifier Instrumentation Amplifier With Dual Supply Using
Area 300
R304
C302
V3+
2.5 = V3+
R302
0.1 µF
C314
10 µF
GND3
10 µF
2.5 = V3–
R301
C301
C313
5 kΩ
A301–
V3+
4
R303
100 Ω
0.1 µF
C312
AB3/SD
A3 OUT
2
3
C311
8
–
A302–
1
Jumpers
+
A303+
U301A
13
R306
R308
R305
V3–
Power Supply Bypass
A304+
V3–
R309 A3 FLT
+
R307
C304
10 kΩ
V
INA
C305
–
R323
C317
C303
R325
R322
C316
C301–
10 kΩ
R324
R327
Jumpers
R326
CD3/SD
C3 OUT
11
12
9
–
C302–
10
+
C303+
C310
R314
C308
U301C
10 kΩ
C304+
R318
R329
C3 FLT
R330
R310
B301–
5 kΩ
R328
C318
R312
C320
6
–
B302–
7
Jumpers
B3 OUT
5
+
B303+
C319
U301B
R313
R315
R317
B304+
B3 FLT
R316
+
R311
C307
10 kΩ
V
INB
C306
–
C309
R321
V3+
VREF3
C324
R331
C321
R320
U302
R339
R332
C315
Jumper
D301–
R319
R333
R335
15
14
–
D3 OUT
D302–
16
U301D
Voltage Reference
R334
+
D303+
D304+
R336
Jumper
R338
D3 FLT
C323
+
R337
C322
V
adj
–
C325
3-11
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3-12
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