Sony Stud Sensor E01X23A41 User Manual

ICX423AL  
Diagonal 11mm (Type 2/3) CCD Image Sensor for CCIR B/W Video Cameras  
Description  
20 pin DIP (Ceramic)  
The ICX423AL is an interline CCD solid-state image  
sensor suitable for CCIR B/W video cameras with a  
diagonal 11mm (Type 2/3) system. Compared with the  
current product ICX083AL, basic characteristics such  
as sensitivity and smear are improved drastically and  
high saturation characteristics are realized.  
This chip features a field period readout system and  
an electronic shutter with variable charge-storage  
time. This chip is compatible with the pins of the  
ICX083AL and has the same drive conditions.  
Pin 1  
2
Features  
High sensitivity (+3.0dB compared with the ICX083AL)  
Low smear (–10.0dB compared with the ICX083AL)  
High saturation signal (+2.0dB compared with the ICX083AL)  
High resolution and Low dark current  
Excellent antiblooming characteristics  
Continuous variable-speed shutter  
V
3
12  
H
40  
Pin 11  
Optical black position  
(Top View)  
Device Structure  
Interline CCD image sensor  
Optical size:  
Diagonal 11mm (Type 2/3)  
Number of effective pixels: 752 (H) × 582 (V) approx. 440K pixels  
Total number of pixels:  
Chip size:  
795 (H) × 596 (V) approx. 470K pixels  
10.25mm (H) × 8.5mm (V)  
Unit cell size:  
Optical black:  
11.6µm (H) × 11.2µm (V)  
Horizontal (H) direction: Front 3 pixels, rear 40 pixels  
Vertical (V) direction:  
Horizontal 22  
Front 12 pixels, rear 2 pixels  
Number of dummy bits:  
Vertical 1 (even fields only)  
Silicon  
Substrate material:  
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by  
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the  
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.  
– 1 –  
E01X23A41  
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ICX423AL  
Block Diagram and Pin Configuration  
(Top view)  
Vφ4  
Vφ3  
Vφ2  
1
2
3
4
5
6
V
L
7
GND  
VDD  
9
10  
11  
12  
SUB  
GND  
VOUT  
VGG  
Note)  
VSS 13  
14  
Vφ1  
Horizontal Register  
GND  
15  
16  
17  
18  
19  
20  
HIS  
RD  
RG  
VL  
Hφ1  
Hφ2  
Note)  
: Photo sensor  
Pin Description  
Pin No. Symbol  
Pin No. Symbol  
Description  
Signal output  
Description  
1
2
Vφ4  
Vφ3  
Vφ2  
SUB  
GND  
Vφ1  
VL  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
VOUT  
VGG  
VSS  
GND  
RD  
Vertical register transfer clock  
Vertical register transfer clock  
Vertical register transfer clock  
Substrate (overflow drain)  
GND  
Output amplifier gate bias  
Output amplifier source  
GND  
3
4
5
Reset drain  
6
RG  
Reset gate clock  
Protective transistor bias  
Vertical register transfer clock  
Protective transistor bias  
7
VL  
8
NC  
Hφ1  
Hφ2  
HIS  
Horizontal register transfer clock  
Horizontal register transfer clock  
Horizontal register input source bias  
9
GND  
VDD  
GND  
10  
Output amplifier drain power  
– 3 –  
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ICX423AL  
Absolute Maximum Ratings  
Item  
Substrate voltage SUB – GND  
Ratings  
–0.3 to +55  
–0.3 to +20  
–55 to +10  
–15 to +20  
to +10  
Unit  
V
Remarks  
V
HIS, VDD, RD, VOUT, VSS – GND  
Supply voltage  
V
HIS, VDD, RD, VOUT, VSS – SUB  
Vertical clock input pins – GND  
Vertical clock input pins – SUB  
V
Vertical clock input  
voltage  
V
1  
Voltage difference between vertical clock input pins  
Voltage difference between horizontal clock input pins  
Hφ1, Hφ2 – Vφ4  
to +15  
V
to +17  
V
–17 to +17  
–10 to +15  
–55 to +10  
–65 to +0.3  
–0.3 to +30  
–0.3 to +24  
–0.3 to +20  
–30 to +80  
–10 to +60  
V
Hφ1, Hφ2, RG, VGG – GND  
Hφ1, Hφ2, RG, VGG – SUB  
VL – SUB  
V
V
V
Vφ1, Vφ3, HIS, VDD, RD, VOUT – VL  
RG – VL  
V
V
Vφ2, Vφ4, VGG, VSS, Hφ1, Hφ2 – VL  
Storage temperature  
V
°C  
°C  
Operating temperature  
1
27V (Max.) when clock width < 10µs, clock duty factor < 0.1%.  
Bias Conditions  
Item  
Symbol Min.  
Typ.  
15.0  
15.0  
4.2  
Max. Unit  
Remarks  
Output amplifier drain voltage  
VDD  
14.7  
14.7  
3.8  
15.3  
15.3  
4.6  
V
V
V
Reset drain voltage  
VRD  
VRD = VDD  
Output amplifier gate voltage  
VGG  
Ground with 750resistor  
Output amplifier source  
VSS  
±5%  
2  
Substrate voltage adjustment range  
Substrate voltage adjustment precision  
Reset gate clock voltage adjustment range  
Reset gate clock voltage adjustment precision  
Protective transistor bias  
VSUB  
VSUB  
VRGL  
VRGL  
VL  
9
–3  
19  
+3  
V
%
V
2  
0
3.0  
+3  
–3  
%
V
3  
–11  
14.7  
–10.5  
15.0  
–10  
15.3  
Horizontal register input source bias  
VHIS  
V
VHIS = VDD  
– 4 –  
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ICX423AL  
DC Characteristics  
Item  
Output amplifier drain current  
Input current  
Symbol Min.  
Typ.  
6
Max.  
Unit  
mA  
µA  
Remarks  
IDD  
IIN1  
IIN2  
4
1
5
Input current  
10  
µA  
2  
Indications of substrate voltage (VSUB) and reset gate clock voltage (VRGL) setting value  
The setting value of the substrate voltage and reset gate clock voltage are indicated on the back of the  
image sensor by a special code. Adjust the substrate voltage (VSUB) and reset gate clock voltage (VRGL) to  
the indicated voltage. The adjustment precision is ±3%.  
VSUB code — one character indication  
VRGL code — one character indication  
VRGL code VSUB code  
"Code" and optimal setting correspond to each other as follows.  
VRGL code  
1
0
2
3
4
5
6
7
Optimal setting  
0.5 1.0 1.5 2.0 2.5 3.0  
VSUB code  
D
E
f
G
h
J
K
L
m
N
P
Q
R
S
T
U
V
W
X
Y
Z
Optimal setting 9.0 9.5 10.0 10.5 11.0 11.5 12.0 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 17.0 17.5 18.0 18.5 19.0  
<Example> "5K" VRGL = 2.0V  
VSUB = 12.0V  
3
This must no exceed the VVL voltage of the vertical clock waveform.  
4
1) Current to each pin when 20V is applied to VDD, RD, VOUT, VSS, HIS and SUB pins, while pins that are  
not tested are grounded.  
2) Current to each pin when 20V is applied sequentially to Vφ1, Vφ2, Vφ3 and Vφ4 pins, while pins that are  
not tested are grounded. However, 20V is applied to SUB pin.  
3) Current to each pin when 15V is applied sequentially to Hφ1, Hφ2, RG and VGG pins, while pins that are  
not tested are grounded. However, 15V is applied to SUB pin.  
4) Current to VL pin when 30V is applied to Vφ1, Vφ3, HIS, VDD, RD and VOUT pins or when, 24V is applied  
to RG pin or when, 20V is applied to Vφ2, Vφ4, VGG, VSS, Hφ1 and Hφ2 pins, while VL pin is grounded.  
However, GND and SUB pins are left open.  
5
Current to SUB pin when 55V is applied to SUB pin, while pins that are not tested are grounded.  
– 5 –  
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ICX423AL  
Clock Voltage Conditions  
Waveform  
diagram  
Item  
Symbol  
Min.  
14.5  
–0.6  
Typ.  
15.0  
Max. Unit  
Remarks  
Readout clock voltage VVT  
15.5  
0
V
V
1
2
VVH1, VVH2,  
VVH3, VVH4  
VVH = (VVH1 + VVH2)/2  
VVL1, VVL2,  
VVL3, VVL4  
–9.6  
V
2
VVL = (VVL3 + VVL4)/2  
VφV  
8.9  
V
V
V
V
V
V
V
V
V
V
V
V
V
2
2
2
2
2
2
2
2
3
3
3
3
4
VφV = VVHn – VVLn (n = 1 to 4)  
| VVH1 – VVH2 |  
VVH3 – VVH  
VVH4 – VVH  
VVHH  
0.2  
0
Vertical transfer clock  
voltage  
–0.5  
–0.5  
0
0.8  
1.0  
0.8  
0.8  
8.0  
–3.0  
13.0  
3.0  
32.0  
High-level coupling  
High-level coupling  
Low-level coupling  
Low-level coupling  
VVHL  
VVLH  
VVLL  
VφH  
6.0  
–3.5  
6.0  
0
Horizontal transfer  
clock voltage  
VHL  
1  
VφRG  
Reset gata clock  
voltage  
VRGL  
Substrate clock voltage VφSUB  
27.0  
1  
The reset gate clock voltage need not be adjusted when the reset gate clock is driven when the  
specifications are as given below. In this case, the reset gate clock voltage setting indicated on the back of  
the image sensor has not significance.  
Waveform  
diagram  
Item  
Symbol  
Min.  
Typ.  
Max. Unit  
Remarks  
VRGL  
VφRG  
–0.2  
8.5  
0
0.2  
9.5  
V
V
3
3
Reset gate clock  
voltage  
9.0  
– 6 –  
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ICX423AL  
Clock Equivalent Circuit Constant  
Symbol  
Typ.  
2700  
2700  
2600  
950  
Item  
Min.  
Max. Unit  
Remarks  
CφV1, CφV3  
pF  
pF  
pF  
pF  
pF  
pF  
Capacitance between vertical transfer  
clock and GND  
CφV2, CφV4  
CφV12, CφV34  
CφV23, CφV41  
CφV13  
Capacitance between vertical transfer  
clocks  
1000  
500  
CφV24  
Capacitance between horizontal  
transfer clock and GND  
CφH1, CφH2  
CφHH  
47  
58  
7
pF  
pF  
pF  
pF  
Capacitance between horizontal  
transfer clocks  
Capacitance between reset gate clock  
and GND  
CφRG  
Capacitance between substrate clock  
and GND  
CφSUB  
800  
R1, R2, R3, R4  
RGND  
22  
3
Vertical transfer clock series resistor  
Vertical transfer clock ground resistor  
Horizontal transfer clock series resistor  
RφH  
10  
Vφ2  
Vφ1  
CφV12  
R1  
R2  
RφH  
RφH  
Hφ1  
Hφ2  
CφV1  
CφV2  
CφHH  
CφV41  
CφV23  
CφH2  
CφH1  
CφV13  
CφV24  
RGND  
CφV3  
CφV4  
R4  
R3  
CφV34  
Vφ4  
Vφ3  
Vertical transfer clock equivalent circuit  
Horizontal transfer clock equivalent circuit  
– 7 –  
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ICX423AL  
Drive Clock Waveform Conditions  
(1) Readout clock waveform  
100%  
90%  
φM  
VVT  
φM  
2
10%  
0%  
0V  
tr  
twh  
tf  
(2) Vertical transfer clock waveform  
Vφ1  
Vφ3  
VVH1  
VVHH  
VVHH  
VVH  
VVH  
VVHH  
VVHH  
VVHL  
VVHL  
VVHL  
VVHL  
VVH3  
VVL1  
VVL3  
VVLH  
VVLH  
VVLL  
VVLL  
VVL  
VVL  
Vφ2  
Vφ4  
VVHH  
VVHH  
VVH4  
VVHH  
VVHH  
VVH  
VVH  
VVHL  
VVHL  
VVHL  
VVHL  
VVH2  
VVLH  
VVL2VVLH  
VVLL  
VVLL  
VVL4  
VVL  
VVL  
VVH = (VVH1 + VVH2)/2  
VVL = (VVL3 + VVL4)/2  
VφV = VVHn – VVLn (n = 1 to 4)  
– 8 –  
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ICX423AL  
(3) Horizontal transfer clock waveform · Reset gate clock waveform  
tr  
twh  
tf  
90%  
10%  
VφH, VφRG  
twl  
VHL, VRGL  
(4) Substrate clock waveform  
100%  
90%  
φM  
VφSUB  
φM  
2
10%  
0%  
VSUB  
tr  
twh  
tf  
Clock Switching Characteristics  
twh  
twl  
tr  
tf  
Symbol  
Item  
Unit  
Remarks  
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.  
Readout clock  
VT  
2.3 2.5  
62.6  
1.3  
0.5  
0.5  
0.1  
0.1  
µs During readout  
Vφ1, Vφ2  
Vφ3, Vφ4  
Hφ  
0.74  
62.1  
20  
0.1  
µs  
Vertical transfer  
clock  
During imaging  
µs  
0.1  
20  
15 19  
0.01  
0.01  
15 19 ns During imaging  
During  
Horizontal  
transfer clock  
Hφ1  
5.38  
0.01  
0.01  
µs  
µs  
parallel-serial  
conversion  
Hφ2  
5.38  
51  
Reset gate  
clock  
φRG  
11 13  
1.5 1.8  
2.0  
0.5  
2.0  
ns  
When draining  
charge  
Substrate clock φSUB  
0.5 µs  
– 9 –  
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ICX423AL  
Image Sensor Characteristics  
Item Symbol Min.  
Sensitivity  
(Ta = 25°C)  
Remarks  
Typ.  
Max. Unit Measurement method  
S
700  
1000  
mV  
mV  
dB  
%
1
2
3
4
5
6
7
8
Saturation signal  
Smear  
Vsat  
Sm  
SH  
Vdt  
Vdt  
F
1000  
Ta = 60°C  
–130  
–120  
25  
2
Video signal shading  
Dark signal  
Dark signal shading  
Flicker  
mV  
mV  
%
Ta = 60°C  
Ta = 60°C  
1
5
Lag  
Lag  
0.5  
%
Image Sensor Characteristics Measurement Method  
Measurement conditions  
1) In the following measurements, the substrate voltage and the reset gate clock voltage are set to the values  
indicated on the device, and the device drive conditions are at the typical values of the bias and clock  
voltage conditions.  
2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical  
black (OB) level is used as the reference for the signal output, and the value measured at point [ A] in the  
drive circuit example is used.  
Definition of standard imaging conditions  
1) Standard imaging condition I:  
Use a pattern box (luminance 706cd/m2, color temperature of 3200K halogen source) as a subject. (Pattern  
for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.00mm) as an IR cut filter  
and image at F8. The luminous intensity to the sensor receiving surface at this point is defined as the  
standard sensitivity luminous intensity.  
2) Standard imaging condition II :  
Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles.  
Use a testing standard lens with CM500S (t = 1.00mm) as an IR cut filter. The luminous intensity is adjusted  
to the value indicated in each testing item by the lens diaphragm.  
1. Sensitivity  
Set to standard imaging condition I. After selecting the electronic shutter mode with a shutter speed of 1/250s,  
measure the signal output (Vs) at the center of the screen and substitute the value into the following formula.  
250  
50  
S = Vs ×  
[mV]  
2. Saturation signal  
Set to standard imaging condition II. After adjusting the luminous intensity to 10 times the intensity with  
average value of signal output, 350mV, measure the minimum value of the signal output.  
– 10 –  
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ICX423AL  
3. Smear  
Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity to  
500 times the intensity with average value of the signal output, 350mV. When the readout clock is stopped  
and the charge drain is executed by the electronic shutter at the respective H blankings, measure the  
maximum value (VSm [mV]) of the signal output and substitute the value into the following formula.  
1
500  
1
10  
VSm  
350  
Sm = 20 × log  
×
×
× 100 [dB] (1/10V method conversion value)  
4. Video signal shading  
Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity so  
that the average value of the signal output is 350mV. Then measure the maximum (Vmax [mV]) and  
minimum (Vmin [mV]) values of the signal output and substitute the values into the following formula.  
SH = (Vmax – Vmin)/350 × 100 [%]  
5. Dark signal  
Measure the average value of the signal output (Vdt [mV]) with the device ambient temperature 60°C and  
the device in the light-obstructed state, using the horizontal idle transfer level as a reference.  
6. Dark signal shading  
After measuring 5, measure the maximum (Vdmax [mV]) and minimum (Vdmin [mV]) values of the dark  
signal output and substitute the values into the following formula.  
Vdt = Vdmax – Vdmin [mV]  
7. Flicker  
Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the signal  
output is 350mV, and then measure the difference in the signal level between fields (Vf [mV]). Then  
substitute the value into the following formula.  
F = (Vf/350) × 100 [%]  
8. Lag  
Adjust the signal output value generated by strobe light to 350mV. After setting the strobe light so that it  
strobes with the following timing, measure the residual signal (Vlag). Substitute the value into the following  
formula.  
Lag = (Vlag/350) × 100 [%]  
FLD  
V1  
Light  
Strobe light  
timing  
Signal output 350mV  
Vlag (lag)  
Output  
– 11 –  
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ICX423AL  
D D V  
G N D  
N C  
L V  
1 φ V  
G N D  
S U B  
2 φ V  
O U V T  
G G V  
S S V  
G N D  
R D  
R G  
L V  
1 φ H  
3 φ V  
2 φ H  
4 φ V  
H I S  
– 12 –  
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ICX423AL  
Spectral Sensitivity Characteristics (includes lens characteristics, excludes light source characteristics)  
1.0  
0.9  
0.8  
0.7  
0.6  
0.5  
0.4  
0.3  
0.2  
0.1  
0
400  
500  
600  
700  
800  
900  
1000  
Wave Length [nm]  
Sensor Readout Clock Timing Chart  
V1  
V2  
2.5  
Odd Field  
V3  
V4  
1.5  
2.6 2.5 2.5  
33.6  
0.2  
V1  
V2  
Even Field  
V3  
V4  
Unit: µs  
– 13 –  
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ICX423AL  
3 4 0  
3 3 5  
3 3 0  
3 2 5  
3 2 0  
3 1 5  
3 1 0  
2 5  
2 0  
1 5  
1 0  
5
4
3
2
1
6 2 5  
6 2 0  
– 14 –  
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ICX423AL  
2 0  
1 0  
3
2
1
3
2
1
2 2  
2 0  
1 0  
5
3
2
1
4 0  
3 0  
2 0  
1 0  
5
3
1
7 5 2  
7 5 0  
7 4 5  
– 15 –  
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ICX423AL  
Notes on Handling  
1) Static charge prevention  
CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following  
protective measures.  
a) Either handle bare handed or use non-chargeable gloves, clothes or material.  
Also use conductive shoes.  
b) When handling directly use an earth band.  
c) Install a conductive mat on the floor or working table to prevent the generation of static electricity.  
d) Ionized air is recommended for discharge when handling CCD image sensor.  
e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges.  
2) Soldering  
a) Make sure the package temperature does not exceed 80°C.  
b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a 30W soldering iron  
with a ground wire and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently.  
c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering  
tool, use a thermal controller of the zero cross On/Off type and connect it to ground.  
3) Dust and dirt protection  
Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and  
dirt. Clean glass plates with the following operation as required, and use them.  
a) Operate in clean environments (around class 1000 is appropriate).  
b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces.  
Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity  
ionized air is recommended.)  
c) Clean with a cotton bud and ethyl alcohol if the grease stained. Be careful not to scratch the glass.  
d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when  
moving to a room with great temperature differences.  
e) When a protective tape is applied before shipping, just before use remove the tape applied for  
electrostatic protection. Do not reuse the tape.  
4) Do not expose to strong light (sun rays) for long periods. For continuous using under cruel condition  
exceeding the normal using condition, consult our company.  
5) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or usage  
in such conditions.  
6) CCD image sensors are precise optical equipment that should not be subject to too much mechanical  
shocks.  
– 16 –  
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ICX423AL  
6 . 0  
2 -  
~
~
( A T S T A N D O F F )  
2 0 . 3 2  
0 ˚ t o 9 ˚  
5 . 5 ± 0 . 2  
3 . 2 ± 0 . 3  
2 0 . 2 ± 0 . 3  
1 . 0  
5 . 0  
Sony Corporation  
– 17 –  
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