National Instruments Network Card NI 6013 User Manual

DAQ  
NI 6013/6014 User Manual  
Multifunction I/O Devices for PCI Bus Computers  
NI 6013/6014 User Manual  
October 2002 Edition  
Part Number 370636A-01  
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Important Information  
Warranty  
The NI 6013 and NI 6014 devices are warranted against defects in materials and workmanship for a period of one year from the date of  
shipment, as evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace equipment that proves to  
be defective during the warranty period. This warranty includes parts and labor.  
The media on which you receive National Instruments software are warranted not to fail to execute programming instructions, due to defects  
in materials and workmanship, for a period of 90 days from date of shipment, as evidenced by receipts or other documentation. National  
Instruments will, at its option, repair or replace software media that do not execute programming instructions if National Instruments receives  
notice of such defects during the warranty period. National Instruments does not warrant that the operation of the software shall be  
uninterrupted or error free.  
A Return Material Authorization (RMA) number must be obtained from the factory and clearly marked on the outside of the package before  
any equipment will be accepted for warranty work. National Instruments will pay the shipping costs of returning to the owner parts which are  
covered by warranty.  
National Instruments believes that the information in this document is accurate. The document has been carefully reviewed for technical  
accuracy. In the event that technical or typographical errors exist, National Instruments reserves the right to make changes to subsequent  
editions of this document without prior notice to holders of this edition. The reader should consult National Instruments if errors are suspected.  
In no event shall National Instruments be liable for any damages arising out of or related to this document or the information contained in it.  
EXCEPT AS SPECIFIED HEREIN, NATIONAL INSTRUMENTS MAKES NO WARRANTIES, EXPRESS OR IMPLIED, AND SPECIFICALLY DISCLAIMS ANY WARRANTY OF  
MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. CUSTOMERS RIGHT TO RECOVER DAMAGES CAUSED BY FAULT OR NEGLIGENCE ON THE PART OF  
NATIONAL INSTRUMENTS SHALL BE LIMITED TO THE AMOUNT THERETOFORE PAID BY THE CUSTOMER. NATIONAL INSTRUMENTS WILL NOT BE LIABLE FOR  
DAMAGES RESULTING FROM LOSS OF DATA, PROFITS, USE OF PRODUCTS, OR INCIDENTAL OR CONSEQUENTIAL DAMAGES, EVEN IF ADVISED OF THE POSSIBILITY  
THEREOF. This limitation of the liability of National Instruments will apply regardless of the form of action, whether in contract or tort, including  
negligence. Any action against National Instruments must be brought within one year after the cause of action accrues. National Instruments  
shall not be liable for any delay in performance due to causes beyond its reasonable control. The warranty provided herein does not cover  
damages, defects, malfunctions, or service failures caused by owners failure to follow the National Instruments installation, operation, or  
maintenance instructions; owners modification of the product; owners abuse, misuse, or negligent acts; and power failure or surges, fire,  
flood, accident, actions of third parties, or other events outside reasonable control.  
Copyright  
Under the copyright laws, this publication may not be reproduced or transmitted in any form, electronic or mechanical, including photocopying,  
recording, storing in an information retrieval system, or translating, in whole or in part, without the prior written consent of National  
Instruments Corporation.  
Trademarks  
CVI, DAQ-STC, LabVIEW, Measurement Studio, MITE, MXI, National Instruments, NI, NI Developer Zone, ni.com, and  
NI-DAQare trademarks of National Instruments Corporation.  
Product and company names mentioned herein are trademarks or trade names of their respective companies.  
Patents  
For patents covering National Instruments products, refer to the appropriate location: Help»Patents in software, the patents.txt file on the  
CD, or ni.com/patents.  
WARNING REGARDING USE OF NATIONAL INSTRUMENTS PRODUCTS  
(1) NATIONAL INSTRUMENTS PRODUCTS ARE NOT DESIGNED WITH COMPONENTS AND TESTING FOR A LEVEL OF  
RELIABILITY SUITABLE FOR USE IN OR IN CONNECTION WITH SURGICAL IMPLANTS OR AS CRITICAL COMPONENTS IN  
ANY LIFE SUPPORT SYSTEMS WHOSE FAILURE TO PERFORM CAN REASONABLY BE EXPECTED TO CAUSE SIGNIFICANT  
INJURY TO A HUMAN.  
(2) IN ANY APPLICATION, INCLUDING THE ABOVE, RELIABILITY OF OPERATION OF THE SOFTWARE PRODUCTS CAN BE  
IMPAIRED BY ADVERSE FACTORS, INCLUDING BUT NOT LIMITED TO FLUCTUATIONS IN ELECTRICAL POWER SUPPLY,  
COMPUTER HARDWARE MALFUNCTIONS, COMPUTER OPERATING SYSTEM SOFTWARE FITNESS, FITNESS OF COMPILERS  
AND DEVELOPMENT SOFTWARE USED TO DEVELOP AN APPLICATION, INSTALLATION ERRORS, SOFTWARE AND  
HARDWARE COMPATIBILITY PROBLEMS, MALFUNCTIONS OR FAILURES OF ELECTRONIC MONITORING OR CONTROL  
DEVICES, TRANSIENT FAILURES OF ELECTRONIC SYSTEMS (HARDWARE AND/OR SOFTWARE), UNANTICIPATED USES OR  
MISUSES, OR ERRORS ON THE PART OF THE USER OR APPLICATIONS DESIGNER (ADVERSE FACTORS SUCH AS THESE ARE  
HEREAFTER COLLECTIVELY TERMED SYSTEM FAILURES). ANY APPLICATION WHERE A SYSTEM FAILURE WOULD  
CREATE A RISK OF HARM TO PROPERTY OR PERSONS (INCLUDING THE RISK OF BODILY INJURY AND DEATH) SHOULD  
NOT BE RELIANT SOLELY UPON ONE FORM OF ELECTRONIC SYSTEM DUE TO THE RISK OF SYSTEM FAILURE. TO AVOID  
DAMAGE, INJURY, OR DEATH, THE USER OR APPLICATION DESIGNER MUST TAKE REASONABLY PRUDENT STEPS TO  
PROTECT AGAINST SYSTEM FAILURES, INCLUDING BUT NOT LIMITED TO BACK-UP OR SHUT DOWN MECHANISMS.  
BECAUSE EACH END-USER SYSTEM IS CUSTOMIZED AND DIFFERS FROM NATIONAL INSTRUMENTS' TESTING  
PLATFORMS AND BECAUSE A USER OR APPLICATION DESIGNER MAY USE NATIONAL INSTRUMENTS PRODUCTS IN  
COMBINATION WITH OTHER PRODUCTS IN A MANNER NOT EVALUATED OR CONTEMPLATED BY NATIONAL  
INSTRUMENTS, THE USER OR APPLICATION DESIGNER IS ULTIMATELY RESPONSIBLE FOR VERIFYING AND VALIDATING  
THE SUITABILITY OF NATIONAL INSTRUMENTS PRODUCTS WHENEVER NATIONAL INSTRUMENTS PRODUCTS ARE  
INCORPORATED IN A SYSTEM OR APPLICATION, INCLUDING, WITHOUT LIMITATION, THE APPROPRIATE DESIGN,  
PROCESS AND SAFETY LEVEL OF SUCH SYSTEM OR APPLICATION.  
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Compliance  
FCC/Canada Radio Frequency Interference Compliance  
Determining FCC Class  
The Federal Communications Commission (FCC) has rules to protect wireless communications from interference. The FCC  
places digital electronics into two classes. These classes are known as Class A (for use in industrial-commercial locations only)  
or Class B (for use in residential or commercial locations). Depending on where it is operated, this product could be subject to  
restrictions in the FCC rules. (In Canada, the Department of Communications (DOC), of Industry Canada, regulates wireless  
interference in much the same way.)  
Digital electronics emit weak signals during normal operation that can affect radio, television, or other wireless products. By  
examining the product you purchased, you can determine the FCC Class and therefore which of the two FCC/DOC Warnings  
apply in the following sections. (Some products may not be labeled at all for FCC; if so, the reader should then assume these are  
Class A devices.)  
FCC Class A products only display a simple warning statement of one paragraph in length regarding interference and undesired  
operation. Most of our products are FCC Class A. The FCC rules have restrictions regarding the locations where FCC Class A  
products can be operated.  
FCC Class B products display either a FCC ID code, starting with the letters EXN,  
or the FCC Class B compliance mark that appears as shown here on the right.  
Consult the FCC Web site at http://www.fcc.gov for more information.  
FCC/DOC Warnings  
This equipment generates and uses radio frequency energy and, if not installed and used in strict accordance with the instructions  
in this manual and the CE Marking Declaration of Conformity*, may cause interference to radio and television reception.  
Classification requirements are the same for the Federal Communications Commission (FCC) and the Canadian Department  
of Communications (DOC).  
Changes or modifications not expressly approved by National Instruments could void the users authority to operate the  
equipment under the FCC Rules.  
Class A  
Federal Communications Commission  
This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of the FCC  
Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is operated  
in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and  
used in accordance with the instruction manual, may cause harmful interference to radio communications. Operation of this  
equipment in a residential area is likely to cause harmful interference in which case the user will be required to correct  
the interference at his own expense.  
Canadian Department of Communications  
This Class A digital apparatus meets all requirements of the Canadian Interference-Causing Equipment Regulations.  
Cet appareil numérique de la classe A respecte toutes les exigences du Règlement sur le matériel brouilleur du Canada.  
Class B  
Federal Communications Commission  
This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the  
FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation.  
This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the  
instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not  
occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can  
be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of  
the following measures:  
Reorient or relocate the receiving antenna.  
Increase the separation between the equipment and receiver.  
Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.  
Consult the dealer or an experienced radio/TV technician for help.  
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Canadian Department of Communications  
This Class B digital apparatus meets all requirements of the Canadian Interference-Causing Equipment Regulations.  
Cet appareil numérique de la classe B respecte toutes les exigences du Règlement sur le matériel brouilleur du Canada.  
Compliance to EU Directives  
Readers in the European Union (EU) must refer to the Manufacturers Declaration of Conformity (DoC) for information*  
pertaining to the CE Marking compliance scheme. The Manufacturer includes a DoC for most every hardware product except  
for those bought for OEMs, if also available from an original manufacturer that also markets in the EU, or where compliance is  
not required as for electrically benign apparatus or cables.  
To obtain the DoC for this product, click Declaration of Conformity at ni.com/hardref.nsf/. This Web site lists the DoCs  
by product family. Select the appropriate product family, followed by your product, and a link to the DoC appears in Adobe  
Acrobat format. Click the Acrobat icon to download or read the DoC.  
*
The CE Marking Declaration of Conformity will contain important supplementary information and instructions for the user  
or installer.  
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About This Manual  
Chapter 1  
Software Programming Choices ....................................................................................1-2  
NI-DAQ...........................................................................................................1-2  
Optional Equipment.......................................................................................................1-4  
Chapter 2  
Installing the Software...................................................................................................2-1  
Chapter 3  
Scanning Multiple Channels............................................................................3-3  
Analog Output................................................................................................................3-4  
Analog Output Glitch ......................................................................................3-4  
Digital I/O......................................................................................................................3-4  
Timing Signal Routing...................................................................................................3-5  
Programmable Function Inputs .......................................................................3-6  
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Contents  
Chapter 4  
Types of Signal Sources.................................................................................. 4-7  
Floating Signal Sources.................................................................... 4-7  
Ground-Referenced Signal Sources.................................................. 4-7  
GPCTR0_SOURCE Signal .............................................................. 4-34  
GPCTR0_GATE Signal ................................................................... 4-35  
GPCTR0_OUT Signal...................................................................... 4-35  
GPCTR0_UP_DOWN Signal........................................................... 4-36  
GPCTR1_SOURCE Signal .............................................................. 4-36  
GPCTR1_GATE Signal ................................................................... 4-37  
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GPCTR1_UP_DOWN Signal...........................................................4-38  
Chapter 5  
Loading Calibration Constants ......................................................................................5-1  
Self-Calibration..............................................................................................................5-2  
External Calibration.......................................................................................................5-2  
Appendix A  
Specifications  
Appendix B  
Custom Cabling and Optional Connectors  
Appendix C  
Appendix D  
Technical Support and Professional Services  
Glossary  
Index  
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About This Manual  
The National Instruments 6013/6014 devices are high-performance  
multifunction analog, digital, and timing I/O devices for PCI. The NI 6014  
features 16 channels (eight differential) of 16-bit analog input (AI),  
two channels of 16-bit analog output (AO), a 68-pin connector, and  
eight lines of digital I/O (DIO). The NI 6013 is identical to the NI 6014,  
except that it does not have AO channels.  
This manual describes the electrical and mechanical aspects of the  
NI 6013/6014 and contains information concerning their operation and  
programming.  
Conventions Used in This Manual  
The following conventions are used in this manual:  
<>  
Angle brackets containing numbers separated by an ellipsis represent  
a range of values associated with a bit or signal namefor example,  
DIO<3..0>. Angle brackets can also denote a variable in a channel  
namefor example, ACH<i> and ACH<i+8>.  
The symbol indicates that the text following it applies only to a specific  
product, a specific operating system, or a specific software version.  
»
The » symbol leads you through nested menu items and dialog box options  
to a final action. The sequence File»Page Setup»Options directs you to  
pull down the File menu, select the Page Setup item, and select Options  
from the last dialog box.  
This icon denotes a note, which alerts you to important information.  
This icon denotes a caution, which advises you of precautions to take to  
avoid injury, data loss, or a system crash. When this symbol is marked on  
the device, refer to Appendix A, Specifications, for precautions to take.  
6013/6014  
This phrase denotes the NI PCI-6013 and NI PCI-6014 devices.  
bold  
Bold text denotes items that you must select or click in the software, such  
as menu items and dialog box options. Bold text also denotes parameter  
names and hardware labels.  
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About This Manual  
italic  
Italic text denotes variables, emphasis, a cross reference, or an introduction  
to a key concept. This font also denotes text that is a placeholder for a word  
or value that you must supply.  
monospace  
Text in this font denotes text or characters that you should enter from the  
keyboard, sections of code, programming examples, and syntax examples.  
This font is also used for the proper names of disk drives, paths, directories,  
programs, subprograms, subroutines, device names, functions, operations,  
variables, filenames and extensions, and code excerpts.  
NI-DAQ  
PC  
NI-DAQ refers to the NI-DAQ driver software for PC compatible  
computers unless otherwise noted.  
PC refers to all PC AT series computers with PCI bus unless otherwise  
noted.  
Related Documentation  
The following documents contain information you may find helpful:  
DAQ Quick Start Guide, at ni.com/manuals  
DAQ-STC Technical Reference Manual, at ni.com/manuals  
NI Developer Zone tutorial, Field Wiring and Noise Considerations  
for Analog Signals, at ni.com/zone  
NI-DAQ User Manual for PC Compatibles, at ni.com/manuals  
PCI Local Bus Specification Revision 2.3, at pcisig.com  
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1
Introduction  
This chapter describes the NI 6013/6014, lists what you need to get started,  
describes the optional software and equipment, and explains how to unpack  
the NI 6013/6014.  
About the NI 6013/6014 Device  
Thank you for buying an NI 6013/6014. The NI 6014 features 16 channels  
(eight differential) of 16-bit analog input, two channels of 16-bit analog  
output, a 68-pin connector, and eight lines of digital I/O. The NI 6013 is  
identical to the NI 6014, except that it does not have AO channels.  
The NI 6013/6014 uses the NI data acquisition system timing controller  
(DAQ-STC) for time-related functions. The DAQ-STC consists of three  
timing groups that control AI, AO, and general-purpose counter/timer  
functions. These groups include a total of seven 24-bit and three 16-bit  
counters and a maximum timing resolution of 50 ns. The DAQ-STC makes  
possible such applications as buffered pulse generation, equivalent time  
sampling, and seamless changing of the sampling rate.  
What You Need to Get Started  
To set up and use the device, you need the following items:  
At least one of the following devices:  
NI 6013 for PCI  
NI 6014 for PCI  
NI 6013/6014 User Manual  
NI-DAQ (for PC Compatibles)  
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Chapter 1  
Introduction  
One of the following software packages and documentation:  
LabVIEW (for Windows)  
Measurement Studio (for Windows)  
VI Logger  
A PCI-bus computer  
Software Programming Choices  
When programming National Instruments DAQ hardware, you can use an  
NI application development environment (ADE) or other ADEs. In either  
case, you use NI-DAQ.  
NI-DAQ  
NI-DAQ, which ships with the NI 6013/6014, has an extensive library of  
functions that you can call from the ADE. These functions allow you to use  
all the features of the NI 6013/6014.  
NI-DAQ carries out many of the complex interactions, such as  
programming interrupts, between the computer and the DAQ hardware.  
NI-DAQ maintains a consistent software interface among its different  
versions so that you can change platforms with minimal modifications  
to the code. Whether you are using LabVIEW, Measurement Studio,  
VI Logger, or other ADEs, your application uses NI-DAQ, as illustrated  
in Figure 1-1.  
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Chapter 1  
Introduction  
Conventional  
Programming  
Environment  
LabVIEW,  
Measurement Studio,  
or VI Logger  
NI-DAQ  
Personal  
Computer or  
Workstation  
DAQ Hardware  
Figure 1-1. The Relationship Among the Programming Environment,  
NI-DAQ, and the Hardware  
To download a free copy of the most recent version of NI-DAQ, click  
Download Software at ni.com.  
National Instruments ADE Software  
LabVIEW features interactive graphics, a state-of-the-art interface,  
and a powerful graphical programming language. The LabVIEW Data  
Acquisition VI Library, a series of virtual instruments for using LabVIEW  
with National Instruments DAQ hardware, is included with LabVIEW.  
Measurement Studio, which includes LabWindows/CVI, tools for  
Visual C++, and tools for Visual Basic, is a development suite that allows  
you to use ANSI C, Visual C++, and Visual Basic to design the test and  
measurement software. For C developers, Measurement Studio includes  
LabWindows/CVI, a fully integrated ANSI C application development  
environment that features interactive graphics and the LabWindows/CVI  
Data Acquisition and Easy I/O libraries. For Visual Basic developers,  
Measurement Studio features a set of ActiveX controls for using National  
Instruments DAQ hardware. These ActiveX controls provide a high-level  
programming interface for building virtual instruments. For Visual C++  
developers, Measurement Studio offers a set of Visual C++ classes and  
tools to integrate those classes into Visual C++ applications. The libraries,  
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Chapter 1  
Introduction  
ActiveX controls, and classes are available with Measurement Studio and  
NI-DAQ.  
Using LabVIEW, Measurement Studio, or VI Logger greatly reduces  
the development time for your data acquisition and control application.  
Optional Equipment  
NI offers a variety of products to use with the device, including cables,  
connector blocks, and other accessories, as follows:  
Cables and cable assemblies, shielded and ribbon  
Connector blocks, shielded and unshielded screw terminals  
Low channel-count signal conditioning modules, devices, and  
accessories, including conditioning for strain gauges and resistance  
temperature detectors (RTDs), simultaneous sample and hold, and  
relays  
For more information about these products, refer to the NI catalog at  
ni.com/catalog.  
Unpacking  
The NI 6013/6014 is shipped in an antistatic package to prevent  
electrostatic damage to the device. Electrostatic discharge (ESD)  
can damage several components on the device.  
Caution Never touch the exposed pins of connectors.  
To avoid such damage in handling the device, take the following  
precautions:  
Ground yourself using a grounding strap or by holding a grounded  
object.  
Touch the antistatic package to a metal part of the computer chassis  
before removing the device from the package.  
Remove the device from the package and inspect the device for loose  
components or any sign of damage. Notify NI if the device appears  
damaged in any way. Do not install a damaged device into the computer.  
Store the NI 6013/6014 in the antistatic envelope when not in use.  
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Chapter 1  
Introduction  
Safety Information  
The following section contains important safety information that you must  
follow during installation and use of the product.  
Do not operate the product in a manner not specified in this document.  
Misuse of the product can result in a hazard. You can compromise the  
safety protection built into the product if the product is damaged in any  
way. If the product is damaged, return it to NI for repair.  
If the product is rated for use with hazardous voltages (>30 Vrms, 42.4 Vpk,  
or 60 VDC), you may need to connect a safety earth-ground wire according  
to the installation instructions. Refer to Appendix A, Specifications, for  
maximum voltage ratings.  
Do not substitute parts or modify the product. Use the product only with the  
chassis, modules, accessories, and cables specified in the installation  
instructions. You must have all covers and filler panels installed during  
operation of the product.  
Do not operate the product in an explosive atmosphere or where there may  
be flammable gases or fumes. Operate the product only at or below the  
pollution degree stated in Appendix A, Specifications. Pollution is foreign  
matter in a solid, liquid, or gaseous state that can produce a reduction of  
dielectric strength or surface resistivity. The following is a description of  
pollution degrees:  
Pollution Degree 1 means no pollution or only dry, nonconductive  
pollution occurs. The pollution has no influence.  
Pollution Degree 2 means that only nonconductive pollution occurs in  
most cases. Occasionally, however, a temporary conductivity caused  
by condensation must be expected.  
Pollution Degree 3 means that conductive pollution occurs, or dry,  
nonconductive pollution occurs, which becomes conductive due to  
condensation.  
Clean the product with a soft nonmetallic brush. The product must be  
completely dry and free from contaminants before returning it to service.  
You must insulate signal connections for the maximum voltage for which  
the product is rated. Do not exceed the maximum ratings for the product.  
Remove power from signal lines before connection to or disconnection  
from the product.  
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Chapter 1  
Introduction  
Operate this product only at or below the installation category stated in  
Appendix A, Specifications.  
The following is a description of installation categories:  
Installation Category I is for measurements performed on circuits not  
directly connected to MAINS1. This category is a signal level such as  
voltages on a printed wire board (PWB) on the secondary of an  
isolation transformer.  
Examples of Installation Category I are measurements on circuits not  
derived from MAINS and specially protected (internal)  
MAINS-derived circuits.  
Installation Category II is for measurements performed on circuits  
directly connected to the low-voltage installation. This category refers  
to local-level distribution such as that provided by a standard wall  
outlet.  
Examples of Installation Category II are measurements on household  
appliances, portable tools, and similar equipment.  
Installation Category III is for measurements performed in the building  
installation. This category is a distribution level referring to hardwired  
equipment that does not rely on standard building insulation.  
Examples of Installation Category III include measurements on  
distribution circuits and circuit breakers. Other examples of  
Installation Category III are wiring including cables, bus-bars, junction  
boxes, switches, socket outlets in the building/fixed installation, and  
equipment for industrial use, such as stationary motors with a  
permanent connection to the building/fixed installation.  
Installation Category IV is for measurements performed at the source  
of the low-voltage (<1,000 V) installation.  
Examples of Installation Category IV are electric meters, and  
measurements on primary overcurrent protection devices and  
ripple-control units.  
1
MAINS is defined as the electricity supply system to which the equipment concerned is designed to be connected either for  
powering the equipment or for measurement purposes.  
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Chapter 1  
Introduction  
Below is a diagram of a sample installation.  
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2
Installing and Configuring  
the NI 6013/6014  
This chapter explains how to install and configure the NI 6013/6014.  
Installing the Software  
Complete the following steps to install the software before installing the  
NI 6013/6014.  
1. Install the ADE, such as LabVIEW, Measurement Studio, or  
VI Logger, according to the instructions on the CD and the release  
notes.  
2. Install NI-DAQ according to the instructions on the CD and the  
DAQ Quick Start Guide included with the NI 6013/6014.  
Note It is important to install NI-DAQ before installing the NI 6013/6014 to ensure that  
the NI 6013/6014 is properly detected.  
Installing the Hardware  
The NI 6013/6014 fits in any PCI system slot in the computer. However, to  
achieve best noise performance, leave as much room as possible between  
the NI 6013/6014 and other devices.  
The following are general installation instructions, but consult the  
computer user manual or technical reference manual for specific  
instructions and warnings.  
Note Follow the guidelines in the computer documentation for installing plug-in  
hardware.  
1. Power off and unplug the computer.  
2. Remove the cover.  
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Chapter 2  
Installing and Configuring the NI 6013/6014  
wait until they go out before continuing the installation.  
4. Remove the expansion slot cover on the back panel of the computer.  
5. Ground yourself using a grounding strap or by holding a grounded  
object. Follow the ESD protection precautions described in the  
Unpacking section of Chapter 1, Introduction.  
6. Insert the NI 6013/6014 into a PCI system slot. Gently rock the device  
to ease it into place. It may be a tight fit, but do not force the device  
into place.  
7. If required, screw the mounting bracket of the device to the back panel  
rail of the computer.  
8. Visually verify the installation. Make sure the device is not touching  
other devices or components and is fully inserted into the slot.  
9. Replace the cover.  
10. Plug in and power on the computer.  
Note For proper cooling, all covers and filler panels must be installed when operating the  
device.  
The NI 6013/6014 is now installed. You are now ready to configure the  
device.  
Configuring the Hardware  
Because of the NI standard architecture for data acquisition and standard  
bus specifications, the NI 6013/6014 is completely software configurable.  
Two types of configuration are performed on the NI 6013/6014:  
bus-related and data acquisition-related.  
The NI 6013/6014 device is fully compatible with the industry-standard  
PCI Local Bus Specification Revision 2.3. This specification allows the PCI  
system to automatically perform all bus-related configurations with no user  
interaction. Bus-related configuration includes setting the device base  
memory address and interrupt channel.  
Data acquisition-related configuration, which you must perform, includes  
such settings as AI coupling and range, and others. You can modify these  
settings using NI-DAQ or ADE software, such as LabVIEW and  
Measurement Studio. Refer to the software documentation for  
configuration instructions. Refer to Chapter 3, Hardware Overview,  
for more information about the various settings available for the device.  
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Chapter 2  
Installing and Configuring the NI 6013/6014  
To configure the NI 6013/6014 in Measurement & Automation Explorer  
(MAX), refer to ni.com/manuals to view either the DAQ Quick Start  
Guide or the NI-DAQ User Manual for PC Compatibles, or launch MAX  
to access the Measurement & Automation Explorer Help for DAQ  
(Help»Help Topics»NI-DAQ).  
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3
Hardware Overview  
This chapter presents an overview of the hardware functions on the  
NI 6013/6014.  
Voltage  
REF  
Calibration  
DACs  
EEPROM  
(8)  
(8)  
Control  
Analog  
Input  
Muxes  
Analog Mode  
Multiplexer  
Generic  
Bus  
Interface  
PCI/PXI  
Bus  
Interface  
MINI-  
MITE  
ADC  
FIFO  
A/D  
Converter  
PGIA  
Data  
Address/Data  
Configuration  
Memory  
AI Control  
EEPROM  
IRQ  
DMA  
DMA/  
Interrupt  
Request  
Trigger  
Interface  
Analog Input  
Timing/Control  
PFI / Trigger  
Analog  
Input  
Control  
EEPROM  
DMA  
Control Interface  
Counter/  
Timing I/O  
Bus  
Interface  
Plug  
DAQ-STC  
Bus  
Interface  
DAQ - STC  
Timing  
and  
DAQ - APE  
Play  
82C55  
Bus  
Analog Output  
Timing/Control  
Analog  
Output  
Control  
DIO  
Digital I/O  
Interface  
Control  
Digital I/O  
AO Control  
DAC0  
DAC1  
Calibration DACs  
Not On NI 6013  
Analog Output  
Figure 3-1. NI 6013/6014 Block Diagram  
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Analog Input  
The AI section of the NI 6013/6014 is software configurable.  
The following sections describe in detail each AI setting.  
Input Mode  
The NI 6013/6014 has two input modesnonreferenced single-ended  
(NRSE) mode and differential (DIFF) mode. NRSE mode provides up to  
16 channels. DIFF input mode provides up to eight channels. Input modes  
are programmed on a per channel basis for multimode scanning.  
For example, you can configure the circuitry to scan 12 channelsfour  
differentially configured channels and eight single-ended channels.  
Table 3-1 describes the two input modes.  
Table 3-1. Available Input Modes  
Mode  
DIFF  
Description  
A channel configured in DIFF mode uses two AI  
lines. One line connects to the positive input of  
the programmable gain instrumentation amplifier  
(PGIA) on the device, and the other connects to  
the negative input of the PGIA.  
NRSE  
line, which connects to the positive input of the  
PGIA. The negative input of the PGIA connects to  
AI sense (AISENSE).  
For diagrams showing the signal paths of the two configurations, refer to  
the Connecting Analog Input Signals section of Chapter 4, Connecting  
Signals.  
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Input Range  
The NI 6013/6014 has a bipolar input range that changes with the  
programmed gain. Each channel may be programmed with a unique gain  
of 0.5, 1.0, 10, or 100 to maximize the A/D converter (ADC) resolution.  
With the proper gain setting, you can use the full resolution of the ADC  
to measure the input signal. Table 3-2 shows the input range and precision  
according to the gain used.  
Table 3-2. Measurement Precision  
Gain  
0.5  
Input Range  
10 to +10 V  
5 to +5 V  
Precision1  
305.2 µV  
152.6 µV  
15.3 µV  
1.0  
10.0  
100.0  
500 to +500 mV  
50 to +50 mV  
1.53 µV  
1 The value of 1 least significant bit (LSB) of the 16-bit ADC; that is, the voltage increment  
corresponding to a change of one count in the ADC 16-bit count.  
Note: Refer to Appendix A, Specifications, for absolute maximum ratings.  
Scanning Multiple Channels  
The devices can scan multiple channels at the same maximum rate as their  
single-channel rate; however, pay careful attention to the settling times for  
each device. No extra settling time is necessary between channels as long  
as the gain is constant and source impedances are low. Refer to  
Appendix A, Specifications, for a complete listing of settling times for each  
of the devices.  
When scanning among channels at various gains, the settling times may  
increase. When the PGIA switches to a higher gain, the signal on the  
previous channel may be well outside the new, smaller range. For instance,  
suppose a 4 V signal is connected to channel 0 and a 1 mV signal is  
connected to channel 1, and suppose the PGIA is programmed to apply  
a gain of one to channel 0 and a gain of 100 to channel 1. When the  
multiplexer switches to channel 1 and the PGIA switches to a gain of 100,  
the new full-scale range is 50 mV.  
The approximately 4 V step from 4 V to 1 mV is 4,000% of the new  
full-scale range. It may take as long as 100 µs for the circuitry to settle to  
1 LSB after such a large transition. In general, this extra settling time is not  
needed when the PGIA is switching to a lower gain.  
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Settling times can also increase when scanning high-impedance signals  
because of a phenomenon called charge injection, where the AI multiplexer  
injects a small amount of charge into each signal source when that source  
is selected. If the impedance of the source is not low enough, the effect of  
the chargea voltage errordoes not decay by the time the ADC samples  
the signal. For this reason, keep source impedances under 1 kto perform  
high-speed scanning.  
Due to the previously described limitations of settling times resulting from  
these conditions, multiple-channel scanning is not recommended unless  
sampling rates are low enough or it is necessary to sample several signals  
as nearly simultaneously as possible. The data is much more accurate and  
channel-to-channel independent if you acquire data from each channel  
independently (for example, 100 points from channel 0, then 100 points  
from channel 1, then 100 points from channel 2, and so on.)  
Analog Output  
NI 6014 only  
The NI 6014 supplies two channels of 16-bit AO voltage at the I/O  
connector. Each device has a fixed bipolar output range of 10 V. Data  
written to the D/A converter (DAC) is interpreted in twos complement  
format, where for a number x expressed in base 2 with n digits to the left  
of the radix point, the (base 2) number is 2n x.  
Analog Output Glitch  
In normal operation, a DAC output glitches whenever it is updated with  
a new value. The glitch energy differs from code to code and appears as  
distortion in the frequency spectrum.  
Digital I/O  
The NI 6013/6014 contains eight lines of digital I/O (DIO<0..7>) for  
general-purpose use. You can individually software-configure each line for  
either input or output. At system startup and reset, the DIO ports are all  
high-impedance.  
The hardware up/down control for general-purpose counters 0 and 1 are  
connected onboard to DIO6 and DIO7, respectively. Thus, you can use  
DIO6 and DIO7 to control the general-purpose counters. The up/down  
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control signals, GPCTR0_UP_DOWN and GPCTR1_UP_DOWN,  
are input only and do not affect the operation of the DIO lines.  
Timing Signal Routing  
The DAQ-STC chip provides a flexible interface for connecting timing  
signals to other devices or external circuitry. The NI 6013/6014 uses the  
Programmable Function Input (PFI) pins on the I/O connector to connect  
the device to external circuitry. These connections are designed to enable  
the NI 6013/6014 to both control and be controlled by other devices and  
circuits.  
The DAQ-STC has 13 internal timing signals that can be controlled by  
an external source. These timing signals can also be controlled by signals  
generated internally to the DAQ-STC, and these selections are fully  
software configurable. Figure 3-2 shows an example of the signal routing  
multiplexer controlling the CONVERT* signal.  
CONVERT*  
PFI<0..9>  
Sample Interval Counter TC  
GPCTR0_OUT  
Figure 3-2. CONVERT* Signal Routing  
Figure 3-2 shows that CONVERT* can be generated from a number  
of sources, including the external signals PFI<0..9> and the internal signals  
Sample Interval Counter TC and GPCTR0_OUT.  
Many of these timing signals are also available on the PFI pins, as indicated  
in Chapter 4, Connecting Signals.  
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Programmable Function Inputs  
The 10 PFI pins are connected to the signal routing multiplexer for each  
timing signal, and software can select any PFI pin as the external source for  
a given timing signal. It is important to note that any of the PFI pins can be  
used as an input by any of the timing signals and that multiple timing  
signals can simultaneously use the same PFI. This flexible routing scheme  
reduces the need to change physical connections to the I/O connector for  
different applications.  
To use the PFI pins as outputs, you must use the Route Signal VI or the  
Select Signal VI to individually enable each of the PFI pins to output a  
specific internal timing signal. For example, if you need the UPDATE*  
signal as an output on the I/O connector, software must turn on the output  
driver for the PFI5/UPDATE* pin.  
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Connecting Signals  
This chapter describes how to make input and output signal connections  
to the NI 6013/6014 using the I/O connector. Table 4-1 shows the cables  
that can be used with the I/O connectors to connect to different accessories.  
Table 4-1. I/O Connector Details  
Cable for  
Connecting  
to 100-pin  
Accessories  
Cable for  
Connecting  
to 68-pin  
Cable for  
Connecting to  
50-pin Signal  
Accessories  
Device with I/O  
Connector  
Numberof  
Pins  
Accessories  
PCI-6013/6014  
68  
N/A  
SH6868Shielded SH6850Shielded  
Cable,  
Cable,  
SH68-68R1-EP  
Shielded Cable,  
R6868 Ribbon  
Cable  
R6850 Ribbon  
Cable  
Caution Connections that exceed any of the maximum ratings of input or output signals  
on the NI 6013/6014 can damage the device and the computer. NI is not liable for any  
damage resulting from such signal connections. The Protection column of Table 4-3 shows  
the maximum input ratings for each signal.  
I/O Connector  
Figure 4-1 shows the pin assignments for the 68-pin I/O connector.  
Refer to Appendix B, Custom Cabling and Optional Connectors, for pin  
assignments of the optional 50- and 68-pin connectors. A signal description  
follows the figures.  
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Chapter 4  
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34 68  
ACH1 33 67  
ACH8  
ACH0  
AIGND  
ACH9  
32 66  
31 65  
30 64  
29 63  
28 62  
AIGND  
ACH10  
ACH3  
ACH2  
AIGND  
ACH11  
AISENSE  
ACH12  
ACH5  
AIGND  
ACH4  
AIGND 27 61  
ACH13 26 60  
ACH6  
AIGND 24 58  
25 59  
AIGND  
ACH14  
ACH7  
ACH15  
23 57  
22 56  
21 55  
DAC0OUT1  
DAC1OUT1  
AIGND  
AOGND  
AOGND  
DGND  
DIO0  
RESERVED 20 54  
19 53  
18 52  
17 51  
16 50  
15 49  
DIO4  
DGND  
DIO1  
DIO5  
DIO6  
DGND  
DIO2  
DGND  
+5V 14 48  
DGND 13 47  
DGND 12 46  
DIO7  
DIO3  
SCANCLK  
PFI0/TRIG1  
11 45  
10 44  
EXTSTROBE*  
DGND  
PFI1/TRIG2  
DGND  
9
8
7
6
5
4
3
2
1
43  
42  
41  
40  
39  
38  
37  
36  
35  
PFI2/CONVERT*  
PFI3/GPCTR1_SOURCE  
PFI4/GPCTR1_GATE  
GPCTR1_OUT  
DGND  
+5V  
DGND  
PFI5/UPDATE*  
PFI6/WFTRIG  
DGND  
PFI7/STARTSCAN  
PFI8/GPCTR0_SOURCE  
DGND  
PFI9/GPCTR0_GATE  
GPCTR0_OUT  
FREQ_OUT  
DGND  
1 Not available on the NI 6013  
Figure 4-1. I/O Connector Pin Assignment for the NI 6013/6014  
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Table 4-2. Signal Descriptions for I/O Connector Pins  
Signal Name  
AIGND  
Reference  
Direction  
Description  
Analog Input GroundThese pins are the bias current  
return point for AI measurements. Refer to Figure 4-3  
for recommended connections. All three ground  
referencesAIGND, AOGND, and DGNDareconnected  
on the device.  
ACH<0..15>  
AISENSE  
AIGND  
AIGND  
Input  
Input  
Analog Input Channels 0 through 15Each channel pair,  
ACH<i, i+8> (i = 0..7), can be configured as either one  
differential input or two single-ended inputs.  
Analog Input SenseThis pin serves as the reference node  
for any of channels ACH<0..15> in NRSE configuration.  
AISENSE must be connected to AIGND directly or to an  
external ground reference for single-ended measurements.  
Invalid random readings result if AISENSE is left  
unconnected when using NRSE mode. Refer to Figure 4-3  
for recommended connections.  
DAC0OUT1  
DAC1OUT1  
AOGND  
AOGND  
AOGND  
Output  
Output  
Analog Channel 0 OutputThis pin supplies the voltage  
output of AO channel 0.  
Analog Channel 1 OutputThis pin supplies the voltage  
output of AO channel 1.  
Analog Output GroundThe AO voltages are referenced to  
this node. All three ground referencesAIGND, AOGND,  
and DGNDare connected on the device.  
DGND  
Digital GroundThis pin supplies the reference for the  
digital signals at the I/O connector as well as the +5 VDC  
supply. All three ground referencesAIGND, AOGND,  
and DGNDare connected together on the device.  
DIO<0..7>  
+5V  
DGND  
DGND  
DGND  
Input  
Output  
Digital I/O SignalsDIO6 and 7 can control the up/down  
signal of general-purpose counters 0 and 1, respectively.  
Output  
Output  
+5 VDC SourceThese pins are fused for up to 1 A of  
+5 V supply. The fuse is self-resetting.  
SCANCLK  
Scan ClockThis pin pulses once for each A/D conversion  
in scanning mode when enabled. The low-to-high edge  
indicates when the input signal can be removed from the  
input or switched to another signal.  
EXTSTROBE*  
DGND  
Output  
External StrobeThis output can be toggled under software  
control to latch signals or trigger events on external devices.  
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Table 4-2. Signal Descriptions for I/O Connector Pins (Continued)  
Signal Name  
PFI0/TRIG1  
Reference  
Direction  
Description  
DGND  
Input  
Output  
PFI0/Trigger 1As an input, this signal is a Programmable  
PFI. PFI signals are explained in the Connecting Timing  
Signals section. As an output, this signal is the TRIG1  
(AI Start Trigger) signal. In posttriggered DAQ sequences,  
a low-to-high transition indicates the initiation of the  
acquisition sequence. In pretriggered applications,  
a low-to-high transition indicates the initiation of  
the pretrigger conversions.  
PFI1/TRIG2  
DGND  
Input  
Output  
PFI1/Trigger 2As an input, this signal is a PFI. As an  
output, this signal is the TRIG2 (AI Stop Trigger) signal.  
In pretrigger applications, a low-to-high transition indicates  
the initiation of the posttrigger conversions. TRIG2 is not  
used in posttrigger applications.  
PFI2/CONVERT*  
DGND  
DGND  
DGND  
Input  
Output  
PFI2/ConvertAs an input, this signal is a PFI. As an  
output, this signal is the CONVERT* (AI Convert) signal.  
A high-to-low edge on CONVERT* indicates that an A/D  
conversion is occurring.  
PFI3/GPCTR1_SOURCE  
PFI4/GPCTR1_GATE  
Input  
Output  
PFI3/Counter 1 SourceAs an input, this signal is a PFI.  
As an output, this signal is the GPCTR1_SOURCE signal.  
This signal reflects the actual source connected to the  
general-purpose counter 1.  
Input  
Output  
PFI4/Counter 1 GateAs an input, this signal is a PFI.  
As an output, this signal is the GPCTR1_GATE signal.  
This signal reflects the actual gate signal connected to the  
general-purpose counter 1.  
GPCTR1_OUT  
PFI5/UPDATE*  
DGND  
DGND  
Output  
Counter 1 OutputThis output is from the general-purpose  
counter 1 output.  
Input  
Output  
PFI5/UpdateAs an input, this signal is a PFI. As an  
output, this signal is the UPDATE* (AO Update) signal.  
A high-to-low edge on UPDATE* indicates that the AO  
primary group is being updated for the NI 6014.  
PFI6/WFTRIG  
DGND  
DGND  
Input  
Output  
PFI6/Waveform TriggerAs an input, this signal is a PFI.  
As an output, this signal is the WFTRIG (AO Start Trigger)  
signal. In timed AO sequences, a low-to-high transition  
indicates the initiation of the waveform generation.  
PFI7/STARTSCAN  
Input  
Output  
PFI7/Start of ScanAs an input, this signal is a PFI. As an  
output, this signal is the STARTSCAN (AI Scan Start)  
signal. This pin pulses once at the start of each AI scan in  
the interval scan. A low-to-high transition indicates the start  
of the scan.  
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Table 4-2. Signal Descriptions for I/O Connector Pins (Continued)  
Signal Name  
Reference  
Direction  
Description  
PFI8/GPCTR0_SOURCE  
DGND  
Input  
Output  
PFI8/Counter 0 SourceAs an input, this signal is a PFI.  
As an output, this signal is the GPCTR0_SOURCE signal.  
This signal reflects the actual source connected to the  
general-purpose counter 0.  
PFI9/GPCTR0_GATE  
DGND  
Input  
Output  
PFI9/Counter 0 GateAs an input, this signal is a PFI.  
As an output, this signal is the GPCTR0_GATE signal.  
This signal reflects the actual gate signal connected to the  
general-purpose counter 0.  
GPCTR0_OUT  
FREQ_OUT  
DGND  
DGND  
Output  
Output  
Counter 0 OutputThis output is from the general-purpose  
counter 0 output.  
Frequency OutputThis output is from the frequency  
generator output.  
* Indicates that the signal is active low.  
1 Not available on the NI 6013.  
Table 4-3. I/O Signal Summary for the NI 6013/6014  
Signal  
Type and  
Direction  
Impedance  
Input/  
Output  
Protection  
(Volts)  
On/Off  
Sink  
(mA  
at V)  
Rise  
Time  
(ns)  
Source  
(mA at V)  
Signal Name  
Bias  
ACH<0..15>  
AI  
AI  
100 GΩ  
in  
parallel  
with  
25/15  
25/15  
200 pA  
100 pF  
AISENSE  
AIGND  
100 GΩ  
in  
parallel  
with  
200 pA  
100 pF  
AO  
AO  
DAC0OUT  
(NI 6014only)  
0.1 Ω  
Short-circuit  
to ground  
5 at 10  
5 at  
10  
4
V/µs  
DAC1OUT  
(NI 6014 only)  
AO  
0.1 Ω  
Short-circuit  
to ground  
5 at 10  
5 at  
10  
4
V/µs  
AOGND  
DGND  
VCC  
AO  
DO  
DO  
0.1 Ω  
Short-circuit  
to ground  
1A fused  
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Table 4-3. I/O Signal Summary for the NI 6013/6014 (Continued)  
Signal  
Type and  
Direction  
Impedance  
Input/  
Output  
Protection  
(Volts)  
On/Off  
Sink  
(mA  
at V)  
Rise  
Time  
(ns)  
Source  
(mA at V)  
Signal Name  
Bias  
DIO<0..7>  
DIO  
VCC +0.5  
10 at (VCC 0.4)  
24 at  
0.4  
1.1  
1.5 kpd  
SCANCLK  
DO  
DO  
3.5 at (VCC 0.4)  
3.5 at (VCC 0.4)  
3.5 at (VCC 0.4)  
3.5 at (VCC 0.4)  
3.5 at (VCC 0.4)  
3.5 at (VCC 0.4)  
3.5 at (VCC 0.4)  
3.5 at (VCC 0.4)  
3.5 at (VCC 0.4)  
3.5 at (VCC 0.4)  
3.5 at (VCC 0.4)  
3.5 at (VCC 0.4)  
3.5 at (VCC 0.4)  
3.5 at (VCC 0.4)  
3.5 at (VCC 0.4)  
5 at 0.4  
5 at 0.4  
5 at 0.4  
5 at 0.4  
5 at 0.4  
5 at 0.4  
5 at 0.4  
5 at 0.4  
5 at 0.4  
5 at 0.4  
5 at 0.4  
5 at 0.4  
5 at 0.4  
5 at 0.4  
5 at 0.4  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
50 kpu  
50 kpu  
50 kpu  
50 kpu  
50 kpu  
50 kpu  
50 kpu  
50 kpu  
50 kpu  
50 kpu  
50 kpu  
50 kpu  
50 kpu  
50 kpu  
50 kpu  
EXTSTROBE*  
PFI0/TRIG1  
DIO  
DIO  
DIO  
DIO  
DIO  
DO  
VCC +0.5  
VCC +0.5  
VCC +0.5  
VCC +0.5  
VCC +0.5  
PFI1/TRIG2  
PFI2/CONVERT*  
PFI3/GPCTR1_SOURCE  
PFI4/GPCTR1_GATE  
GPCTR1_OUT  
PFI5/UPDATE*  
PFI6/WFTRIG  
DIO  
DIO  
DIO  
DIO  
DIO  
DO  
VCC +0.5  
VCC +0.5  
VCC +0.5  
VCC +0.5  
VCC +0.5  
PFI7/STARTSCAN  
PFI8/GPCTR0_SOURCE  
PFI9/GPCTR0_GATE  
GPCTR0_OUT  
FREQ_OUT  
DO  
pd = pull down  
pu = pull up  
DO = Digital Output  
The tolerance on the 50 kpull-up resistors is very large. Actual value may range between 17 and 100 k.  
Analog Input Signal Overview  
The AI signals for the NI 6013/6014 are ACH<0..15>, AISENSE, and  
AIGND. Connection of these AI signals to the device depends on the type  
of input signal source and the configuration of the AI channels you are  
using. This section provides an overview of the different types of signal  
sources and AI configuration modes. More specific signal connection  
information is provided in the Connecting Analog Input Signals section.  
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Types of Signal Sources  
When making signal connections, you must first determine whether the  
signal sources are floating or ground-referenced. The following sections  
describe these two types of signals.  
Floating Signal Sources  
A floating signal source is not connected in any way to the building ground  
system but, rather, has an isolated ground-reference point. Some examples  
of floating signal sources are outputs of transformers, thermocouples,  
battery-powered devices, optical isolator outputs, and isolation amplifiers.  
An instrument or device that has an isolated output is a floating signal  
source. You must tie the ground reference of a floating signal to the  
NI 6013/6014 AIGND to establish a local or onboard reference for the  
signal. Otherwise, the measured input signal varies as the source floats  
outside the common-mode input range.  
Ground-Referenced Signal Sources  
A ground-referenced signal source is connected in some way to the  
building system ground and is, therefore, already connected to a common  
ground point with respect to the NI 6013/6014, assuming that the computer  
is plugged into the same power system. Nonisolated outputs of instruments  
and devices that plug into the building power system fall into this category.  
The difference in ground potential between two instruments connected  
to the same building power system is typically between 1 and 100 mV,  
but it can be much higher if power distribution circuits are improperly  
connected. If a grounded signal source is improperly measured, this  
difference may appear as a measurement error. The connection instructions  
for grounded signal sources are designed to eliminate this ground potential  
difference from the measured signal.  
Analog Input Modes  
You can use the NI 6013/6014 PGIA in different ways, depending on  
whether you configure the NI 6013/6014 for NRSE or DIFF mode.  
Figure 4-2 shows a diagram of the device PGIA.  
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Instrumentation  
Amplifier  
Vin+  
+
+
PGIA  
Measured  
Voltage  
Vm  
Vin–  
Vm = [Vin+ – Vin–]* Gain  
Figure 4-2. Programmable Gain Instrumentation Amplifier (PGIA)  
In NRSE mode, signals connected to ACH<0..15> are routed to the positive  
input of the PGIA, and AISENSE is connected to the negative input of the  
PGIA. In DIFF mode, signals connected to ACH<0..7> are routed to the  
positive input of the PGIA, signals connected to ACH<8..15> are routed to  
the negative input of the PGIA, and AISENSE is not used.  
Caution Exceeding the differential and common-mode input ranges distorts the input  
signals. Exceeding the maximum input voltage rating can damage the device and the  
computer. NI is not liable for any damage resulting from such signal connections.  
The maximum input voltage ratings are listed in the Protection column of Table 4-3.  
AIGND is an AI common signal that is routed directly to the ground tie  
point on the devices. You can use this signal for a general analog ground  
tie point to the device if necessary.  
Note AIGND is not connected to the negative input of the PGIA in single-ended mode  
unless it is connected to AISENSE with an external wire.  
The PGIA applies gain and common-mode voltage rejection and presents  
high-input impedance to the AI signals connected to the device. Signals are  
routed to the positive and negative inputs of the PGIA through input  
multiplexers on the device. The PGIA converts two input signals to a signal  
that is the difference between the two input signals multiplied by the gain  
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setting of the amplifier. The amplifier output voltage is referenced to the  
device ground. The device ADC measures this output voltage when it  
performs A/D conversions.  
Connecting Analog Input Signals  
The following sections discuss the use of single-ended and differential  
measurements and make recommendations for measuring both floating  
and ground-referenced signal sources.  
Figure 4-3 summarizes the recommended input configuration for both  
types of signal sources.  
Input  
Floating Signal Source  
Grounded Signal Source  
(Not Connected to Building Ground)  
Examples  
Example  
Ungrounded Thermocouples  
Signal Conditioning with  
Isolated Outputs  
Plug-in Instruments with Nonisolated  
Outputs  
Input  
Battery Devices  
ACH(+)  
ACH(+)  
+
+
+
+
V1  
V1  
ACH()  
ACH()  
Differential  
(DIFF)  
R
AIGND  
AIGND  
See text for information on bias resistors.  
ACH  
ACH  
+
+
+
+
V1  
V1  
AISENSE  
AISENSE  
Single-Ended —  
Nonreferenced  
(NRSE)  
R
AIGND  
AIGND  
Figure 4-3. Summary of AI Connections  
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Differential Connection Considerations  
A differential connection is one in which the AI signal has its own reference  
signal or signal return path. These connections are available when the  
selected channel is configured in DIFF input mode. In DIFF mode, the AI  
channels are paired, with ACH<i> as the signal input and ACH<i+8> as the  
signal reference. For example, ACH0 is paired with ACH8, ACH1 is paired  
with ACH9, and so on. The input signal is tied to the positive input of the  
PGIA, and its reference signal, or return, is tied to the negative input of  
the PGIA.  
When you configure a channel for DIFF input mode, each signal uses  
two multiplexer inputsone for the signal and one for its reference signal.  
Therefore, with a differential configuration for every channel, up to eight  
AI channels are available.  
You should use DIFF input connections for any channel that meets any of  
the following conditions:  
The input signal is low level (less than 1 V).  
The leads connecting the signal to the device are greater than  
3 m (10 ft).  
The input signal requires a separate ground-reference point or return  
signal.  
The signal leads travel through noisy environments.  
Differential signal connections reduce noise pick up and increase  
common-mode noise rejection. Differential signal connections also allow  
input signals to float within the common-mode limits of the PGIA.  
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Differential Connections for Ground-Referenced  
Signal Sources  
Figure 4-4 shows how to connect a ground-referenced signal source to  
a channel on the device configured in DIFF input mode.  
ACH+  
Ground-  
Referenced  
Signal  
+
Instrumentation  
Vs  
Amplifier  
+
Source  
PGIA  
+
ACH–  
Measured  
Voltage  
Vm  
Common-  
Mode  
+
Noise and  
Ground  
Potential  
Vcm  
Input Multiplexers  
AISENSE  
AIGND  
I/O Connector  
Selected Channel in DIFF Configuration  
Figure 4-4. Differential Input Connections for Ground-Referenced Signals  
With this type of connection, the PGIA rejects both the common-mode  
noise in the signal and the ground potential difference between the signal  
source and the device ground, shown as Vcm in Figure 4-4.  
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Differential Connections for Nonreferenced or  
Floating Signal Sources  
Figure 4-5 shows how to connect a floating signal source to a channel  
configured in DIFF input mode on the NI 6013/6014.  
ACH+  
Bias  
Resistors  
(see text)  
+
Floating  
Instrumentation  
Amplifier  
Signal  
Source  
Vs  
+
PGIA  
+
ACH–  
Measured  
Voltage  
Vm  
Bias  
Current  
Return  
Paths  
Input Multiplexers  
AISENSE  
AIGND  
I/O Connector  
Selected Channel in DIFF Configuration  
Figure 4-5. Differential Input Connections for Nonreferenced Signals  
Figure 4-5 shows two bias resistors connected in parallel with the signal  
leads of a floating signal source. If you do not use the resistors and the  
source is truly floating, the source is unlikely to remain within the  
common-mode signal range of the PGIA. The PGIA then saturates, causing  
erroneous readings.  
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You must reference the source to AIGND. The easiest way is to connect  
the positive side of the signal to the positive input of the PGIA and connect  
the negative side of the signal to AIGND as well as to the negative input  
of the PGIA, without any resistors. This connection works well for  
DC-coupled sources with low source impedance (less than 100 ).  
However, for larger source impedances, this connection leaves the  
differential signal path significantly off balance. Noise that couples  
electrostatically onto the positive line does not couple onto the negative  
line, because it is connected to ground. Hence, this noise appears as a  
differential-mode signal instead of a common-mode signal, and the PGIA  
does not reject it. In this case, instead of directly connecting the negative  
line to AIGND, connect it to AIGND through a resistor that is about  
100 times the equivalent source impedance. The resistor puts the signal  
path nearly in balance, so that about the same amount of noise couples onto  
both connections, yielding better rejection of electrostatically-coupled  
noise. Also, this configuration does not load down the source (other than  
the very high input impedance of the PGIA).  
You can fully balance the signal path by connecting another resistor of the  
same value between the positive input and AIGND, as shown in Figure 4-5.  
This fully balanced configuration offers slightly better noise rejection  
but has the disadvantage of loading the source down with the series  
combination (sum) of the two resistors. If, for example, the source  
impedance is 2 kand each of the two resistors is 100 k, the resistors  
load down the source with 200 kand produce a 1% gain error.  
Both inputs of the PGIA require a DC path to ground in order for the PGIA  
to work. If the source is AC coupled (capacitively coupled), the PGIA needs  
a resistor between the positive input and AIGND. If the source has low  
impedance, choose a resistor that is large enough not to significantly load  
the source but small enough not to produce significant input offset voltage  
as a result of input bias current (typically 100 kto 1 M). In this case,  
you can tie the negative input directly to AIGND. If the source has high  
output impedance, you should balance the signal path as previously  
described using the same value resistor on both the positive and negative  
inputs. You should be aware that there is some gain error from loading  
down the source.  
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Single-Ended Connection Considerations  
A single-ended connection is one in which the AI signal of the  
NI 6013/6014 is referenced to a common ground that can be shared with  
other input signals. The input signal is tied to the positive input of the  
PGIA, and the common ground is tied to the negative input of the PGIA  
using AISENSE.  
When every channel is configured for single-ended input, up to  
16 AI channels are available.  
You can use single-ended input connections for any input signal that meets  
the following conditions:  
The input signal is high level (greater than 1 V).  
The leads connecting the signal to the device are less than 3 m (10 ft).  
The input signal can share a common reference point with other  
signals.  
DIFF input connections are recommended for greater signal integrity  
for any input signal that does not meet the preceding conditions.  
NRSE mode is the only single-ended configuration supported on the  
NI 6013/6014. The AISENSE connection differs for floating and grounded  
signal sources. For floating signal sources, AISENSE is connected directly  
to AIGND, and the NI 6013/6014 provides the reference ground point for  
the external signal. For grounded signal sources, AISENSE is connected  
to the external signal reference ground, preventing current loops and  
measurement errors.  
In single-ended configurations, more electrostatic and magnetic noise  
couples into the signal connections than in differential configurations.  
The coupling is the result of differences in the signal path. Magnetic  
coupling is proportional to the area between the two signal conductors.  
Electrical coupling is a function of how much the electric field differs  
between the two conductors.  
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Single-Ended Connections for Floating Signal  
Sources  
Figure 4-6 shows how to connect a floating signal source to a channel  
configured for NRSE mode on the NI 6013/6014.  
ACH  
Instrumentation  
+
Floating  
Signal  
Amplifier  
+
Vs  
Source  
PGIA  
+
Input Multiplexers  
AISENSE  
Measured  
Voltage  
Vm  
AIGND  
I/O Connector  
Selected Channel in NRSE Configuration  
Figure 4-6. Single-Ended Input Connections for Nonreferenced or Floating Signals  
Single-Ended Connections for Grounded Signal  
Sources  
To measure a grounded signal source with a single-ended configuration,  
you must configure the NI 6013/6014 in NRSE input mode. The signal  
is then connected to the positive input of the PGIA, and the signal local  
ground reference is connected to the negative input of the PGIA.  
The ground point of the signal should, therefore, be connected to the  
AISENSE pin. Any potential difference between the device ground and  
the signal ground appears as a common-mode signal at both the positive  
and negative inputs of the PGIA, and this difference is rejected by the  
amplifier. If AISENSE is connected to AIGND in this situation, the  
difference in ground potentials appears as an error in the measured voltage.  
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Figure 4-7 shows how to connect a grounded signal source to a channel  
configured for NRSE mode on the NI 6013/6014.  
ACH<0..15>  
Instrumentation  
Ground-  
Referenced  
Signal  
+
Amplifier  
+
Vs  
Source  
PGIA  
+
Input Multiplexers  
Measured  
Voltage  
Vm  
Common-  
Mode  
Noise  
+
AISENSE  
AIGND  
Vcm  
and Ground  
Potential  
Selected Channel in NRSE Configuration  
I/O Connector  
Figure 4-7. Single-Ended Input Connections for Ground-Referenced Signals  
Common-Mode Signal Rejection Considerations  
Figures 4-4 and 4-7 show connections for signal sources that are  
already referenced to some ground point with respect to the NI 6013/6014.  
In these cases, the PGIA can reject any voltage caused by ground potential  
differences between the signal source and the device. In addition, with  
differential input connections, the PGIA can reject common-mode noise  
pickup in the leads connecting the signal sources to the device. The PGIA  
can reject common-mode signals as long as Vin+ and Vin(input signals)  
are both within 11 V of AIGND.  
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Connecting Analog Output Signals  
NI 6014 only  
The AO signals are DAC0OUT, DAC1OUT, and AOGND. DAC0OUT and  
DAC1OUT are not available on the NI 6013.  
DAC0OUT is the voltage output signal for AO channel 0. DAC1OUT is the  
voltage output signal for AO channel 1.  
AOGND is the ground-referenced signal for both AO channels and the  
external reference signal.  
Figure 4-8 shows how to connect AO signals to the NI 6013/6014.  
DAC0OUT  
Channel 0  
+
VOUT 0  
Load  
Load  
AOGND  
VOUT 1  
DAC1OUT  
+
Channel 1  
Analog Output Channels  
I/O Connector  
Figure 4-8. AO Connections  
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Connecting Digital I/O Signals  
The DIO signals on the NI 6013/6014 are DIO<0..7> and DGND.  
DIO<0..7> are the signals making up the DIO port, and DGND is the  
ground-reference signal for the DIO port. You can program all lines  
individually to be inputs or outputs.  
Caution Exceeding the maximum input voltage ratings, which are listed in Table 4-3, can  
damage the NI 6013/6014 and the computer. NI is not liable for any damage resulting from  
such signal connections.  
Figure 4-9 shows signal connections for three typical DIO applications.  
+5 V  
LED  
DIO<4..7>  
TTL Signal  
DIO<0..3>  
+5 V  
Switch  
DGND  
I/O Connector  
Figure 4-9. Digital I/O Connections  
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Figure 4-9 shows DIO<0..3> configured for digital input and DIO<4..7>  
configured for digital output. Digital input applications include receiving  
TTL signals and sensing external device states, such as the switch state  
shown in the Figure 4-9. Digital output applications include sending TTL  
signals and driving external devices, such as the LED shown in Figure 4-9.  
Power Connections  
Two pins on the I/O connector supply +5 V from the computer power  
supply using a self-resetting fuse. The fuse resets automatically within  
a few seconds after the overcurrent condition is removed. These pins are  
referenced to DGND and can be used to power external digital circuitry.  
The power rating is +4.65 to +5.25 VDC at 1 A.  
Caution Do not connect these +5 V power pins directly to analog or digital ground or to  
any other voltage source on the NI 6013/6014 or any other device. Doing so can damage  
the NI 6013/6014 and the computer. NI is not liable for damage resulting from such  
a connection.  
Connecting Timing Signals  
damage the device and the computer. NI is not liable for any damage resulting from such  
signal connections.  
All external control over the timing of the device is routed through the  
10 PFIs labeled PFI<0..9>. These signals are explained in detail in the  
Programmable Function Input Connections section. These PFIs are  
bidirectional; as outputs they are not programmable and reflect the state  
of many DAQ, waveform generation, and general-purpose timing signals.  
There are five other dedicated outputs for the remainder of the timing  
signals. As inputs, the PFI signals are programmable and can control  
any DAQ, waveform generation, and general-purpose timing signals.  
The DAQ signals are explained in the DAQ Timing Connections section.  
The Waveform Generation Timing Connections section explains the  
waveform generation signals, and the General-Purpose Timing Signal  
Connections section explains the general-purpose timing signals.  
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All digital timing connections are referenced to DGND. This reference  
is demonstrated in Figure 4-10, which shows how to connect an external  
TRIG1 source and an external CONVERT* source to two PFI pins on the  
NI 6013/6014.  
PFI0/TRIG1  
PFI2/CONVERT*  
TRIG1  
Source  
CONVERT*  
Source  
DGND  
I/O Connector  
Figure 4-10. Timing I/O Connections  
Programmable Function Input Connections  
There are 13 internal timing signals that you can externally control from the  
PFI pins. The source for each of these signals is software-selectable from  
any PFI pin when you want external control. This flexible routing scheme  
reduces the need to change the physical wiring to the device I/O connector  
for different applications requiring alternative wiring.  
You can individually enable each PFI pin to output a specific internal  
timing signal. For example, if you need the CONVERT* signal as an output  
on the I/O connector, software can turn on the output driver for the  
PFI2/CONVERT* pin.  
Note Be careful not to drive a PFI signal externally when it is configured as an output.  
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As an input, each PFI pin can be individually configured for edge or level  
detection and for polarity selection. You can use the polarity selection for  
any of the timing signals, but the edge or level detection depends upon the  
particular timing signal being controlled. The detection requirements for  
each timing signal are listed within the section that discusses that individual  
signal.  
In edge-detection mode, the minimum pulse width required is 10 ns. This  
applies for both rising-edge and falling-edge polarity settings. There is no  
maximum pulse-width requirement in edge-detect mode.  
In level-detection mode, there are no minimum or maximum pulse-width  
requirements imposed by the PFIs themselves, but there may be limits  
imposed by the particular timing signal being controlled. These  
requirements are listed later in this chapter.  
DAQ Timing Connections  
The DAQ timing signals are TRIG1, TRIG2, STARTSCAN, CONVERT*,  
AIGATE, SISOURCE, SCANCLK, and EXTSTROBE*.  
Posttriggered data acquisition allows you to view only data that is acquired  
after a trigger event is received. A typical posttriggered DAQ sequence is  
shown in Figure 4-11.  
TRIG1  
STARTSCAN  
CONVERT*  
Scan Counter  
4
3
2
1
0
Figure 4-11. Typical Posttriggered Acquisition  
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Pretriggered data acquisition allows you to view data that is acquired before  
the trigger of interest in addition to data acquired after the trigger.  
Figure 4-12 shows a typical pretriggered DAQ sequence. The description  
for each signal shown in these figures is included later in this chapter.  
TRIG1  
n/a  
TRIG2  
STARTSCAN  
CONVERT*  
Scan Counter  
3
2
1
0
2
2
2
1
0
Figure 4-12. Typical Pretriggered Acquisition  
TRIG1 Signal  
Any PFI pin can externally input the TRIG1 signal, which is available as  
an output on the PFI0/TRIG1 pin.  
Refer to Figures 4-11 and 4-12 for the relationship of TRIG1 to the DAQ  
sequence.  
As an input, TRIG1 is configured in the edge-detection mode. You can  
select any PFI pin as the source for TRIG1 and configure the polarity  
selection for either rising or falling edge. The selected edge of TRIG1 starts  
the DAQ sequence for both posttriggered and pretriggered acquisitions.  
As an output, TRIG1 reflects the action that initiates a DAQ sequence, even  
if the acquisition is being externally triggered by another PFI. The output is  
an active high pulse with a pulse width of 50 to 100 ns. This output is set to  
high-impedance at startup.  
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Figures 4-13 and 4-14 show the input and output timing requirements  
for TRIG1.  
tw  
Rising-Edge  
Polarity  
Falling-Edge  
Polarity  
tw = 10 ns minimum  
Figure 4-13. TRIG1 Input Signal Timing  
tw  
tw = 50 to 100 ns  
Figure 4-14. TRIG1 Output Signal Timing  
The device also uses TRIG1 to initiate pretriggered DAQ operations.  
In most pretriggered applications, TRIG1 is generated by a software  
trigger. Refer to the TRIG2 signal description for a complete description  
of the use of TRIG1 and TRIG2 in a pretriggered DAQ operation.  
TRIG2 Signal  
Any PFI pin can externally input the TRIG2 signal, which is available as  
an output on the PFI1/TRIG2 pin. Refer to Figure 4-12 for the relationship  
of TRIG2 to the DAQ sequence.  
As an input, TRIG2 is configured in the edge-detection mode. You can  
select any PFI pin as the source for TRIG2 and configure the polarity  
selection for either rising or falling edge. The selected edge of TRIG2  
initiates the posttriggered phase of a pretriggered DAQ sequence. In  
pretriggered mode, the TRIG1 signal initiates the data acquisition. The scan  
counter (SC) indicates the minimum number of scans before TRIG2 can be  
recognized. After the SC decrements to zero, it is loaded with the number  
of posttrigger scans to acquire while the acquisition continues. The device  
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ignores TRIG2 if it is asserted prior to the SC decrementing to zero. After  
the selected edge of TRIG2 is received, the device acquires a fixed number  
of scans and the acquisition stops. This mode acquires data both before and  
after receiving TRIG2.  
As an output, TRIG2 reflects the posttrigger in a pretriggered DAQ  
sequence, even if the acquisition is being externally triggered by another  
PFI. TRIG2 is not used in posttriggered data acquisition. The output is an  
active high pulse with a pulse width of 50 to 100 ns. This output is set to  
high-impedance at startup.  
Figures 4-15 and 4-16 show the input and output timing requirements  
for TRIG2.  
tw  
Rising-Edge  
Polarity  
Falling-Edge  
Polarity  
tw = 10 ns minimum  
Figure 4-15. TRIG2 Input Signal Timing  
tw  
tw = 50 to 100 ns  
Figure 4-16. TRIG2 Output Signal Timing  
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STARTSCAN Signal  
Any PFI pin can receive as an input the STARTSCAN signal, which is  
available as an output on the PFI7/STARTSCAN pin. Refer to Figures 4-11  
and 4-12 for the relationship of STARTSCAN to the DAQ sequence.  
As an input, STARTSCAN is configured in the edge-detection mode.  
You can select any PFI pin as the source for STARTSCAN and configure  
the polarity selection for either rising or falling edge. The selected edge of  
STARTSCAN initiates a scan. The sample interval counter starts if you  
select internally triggered CONVERT*.  
As an output, STARTSCAN reflects the actual start pulse that initiates a  
scan, even if the starts are being externally triggered by another PFI. You  
have two output options. The first is an active high pulse with a pulse width  
of 50 to 100 ns, which indicates the start of the scan. The second action is  
an active high pulse that terminates at the start of the last conversion in the  
scan, which indicates a scan in progress. STARTSCAN is deasserted toff  
after the last conversion in the scan is initiated. This output is set to  
high-impedance at startup.  
Figures 4-17 and 4-18 show the input and output timing requirements for  
the STARTSCAN signal.  
tw  
Rising-Edge  
Polarity  
Falling-Edge  
Polarity  
tw = 10 ns minimum  
Figure 4-17. STARTSCAN Input Signal Timing  
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tw  
STARTSCAN  
tw = 50 to 100 ns  
a. Start of Scan  
Start Pulse  
CONVERT*  
STARTSCAN  
t
off = 10 ns minimum  
toff  
b. Scan in Progress, Two Conversions per Scan  
Figure 4-18. STARTSCAN Output Signal Timing  
The CONVERT* pulses are masked off until the device generates the  
STARTSCAN signal. If you are using internally generated conversions,  
the first CONVERT* appears when the onboard sample interval counter  
(SI2) reaches zero. If you select an external CONVERT*, the first external  
pulse after STARTSCAN generates a conversion. The STARTSCAN pulses  
should be separated by at least one scan period.  
A counter on the NI 6013/6014 internally generates STARTSCAN unless  
you select some external source. This counter is started by the TRIG1  
signal and is stopped either by software or by the sample counter.  
Scans generated by either an internal or external STARTSCAN signal are  
inhibited unless they occur within a DAQ sequence. Scans occurring within  
a DAQ sequence may be gated by either the hardware (AIGATE) signal or  
software command register gate.  
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CONVERT* Signal  
Any PFI pin can externally input the CONVERT* signal, which is  
available as an output on the PFI2/CONVERT* pin.  
Refer to Figures 4-11 and 4-12 for the relationship of CONVERT* to  
the DAQ sequence.  
As an input, CONVERT* is configured in the edge-detection mode.  
You can select any PFI pin as the source for CONVERT* and configure  
the polarity selection for either rising or falling edge. The selected edge of  
CONVERT* initiates an A/D conversion.  
The ADC switches to hold mode within 60 ns of the selected edge. This  
hold-mode delay time is a function of temperature and does not vary from  
one conversion to the next. CONVERT* pulses should be separated by at  
least 5 µs (200 kHz sample rate).  
As an output, CONVERT* reflects the actual convert pulse that is  
connected to the ADC, even if the conversions are being externally  
generated by another PFI. The output is an active low pulse with a pulse  
width of 50 to 150 ns. This output is set to high-impedance at startup.  
Figures 4-19 and 4-20 show the input and output timing requirements for  
CONVERT*.  
tw  
Rising-Edge  
Polarity  
Falling-Edge  
Polarity  
tw = 10 ns minimum  
Figure 4-19. CONVERT* Input Signal Timing  
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tw  
tw = 50 to 150 ns  
Figure 4-20. CONVERT* Output Signal Timing  
The SI2 counter on the NI 6013/6014 normally generates CONVERT*  
unless you select some external source. The counter is started by the  
STARTSCAN signal and continues to count down and reload itself until  
the scan is finished. It then reloads itself in preparation for the next  
STARTSCAN pulse.  
A/D conversions generated by either an internal or external CONVERT*  
signal are inhibited unless they occur within a DAQ sequence. Scans  
occurring within a DAQ sequence may be gated by either the hardware  
(AIGATE) signal or software command register gate.  
AIGATE Signal  
Any PFI pin can externally input the AIGATE signal, which is not  
available as an output on the I/O connector. AIGATE can mask off scans  
in a DAQ sequence. You can configure the PFI pin you select as the source  
for AIGATE in level-detection mode. You can configure the polarity  
selection for the PFI pin for either active high or active low. In  
level-detection mode if AIGATE is active, the STARTSCAN signal is  
masked off and no scans can occur.  
AIGATE can neither stop a scan in progress nor continue a previously  
gated-off scan; in other words, once a scan has started, AIGATE does not  
gate off conversions until the beginning of the next scan and, conversely,  
if conversions are being gated off, AIGATE does not gate them back on  
until the beginning of the next scan.  
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SISOURCE Signal  
Any PFI pin can externally input the SISOURCE signal, which is not  
available as an output on the I/O connector. The onboard scan interval (SI)  
counter uses SISOURCE as a clock to time the generation of  
the STARTSCAN signal. You must configure the PFI pin you select as  
the source for SISOURCE in the level-detection mode. You can configure  
the polarity selection for the PFI pin for either active high or active low.  
The maximum allowed frequency is 20 MHz, with a minimum pulse width  
of 23 ns high or low. There is no minimum frequency limitation.  
Either the 20 MHz or 100 kHz internal timebase generates SISOURCE  
unless you select some external source. Figure 4-21 shows the timing  
requirements for the SISOURCE signal.  
tp  
tw  
tw  
tp = 50 ns minimum  
tw = 23 ns minimum  
Figure 4-21. SISOURCE Signal Timing  
SCANCLK Signal  
SCANCLK is an output-only signal that generates a pulse with the leading  
edge occurring approximately 50 to 100 ns after an A/D conversion begins.  
The polarity of this output is software-selectable but is typically configured  
so that a low-to-high leading edge can clock external AI multiplexers  
indicating when the input signal has been sampled and can be removed.  
This signal has a 400 to 500 ns pulse width and is software enabled.  
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Figure 4-22 shows the timing for SCANCLK.  
CONVERT*  
td  
SCANCLK  
tw  
td = 50 to 100 ns  
tw = 400 to 500 ns  
Figure 4-22. SCANCLK Signal Timing  
Note When using NI-DAQ, SCANCLK polarity is low-to-high and cannot be changed  
programmatically.  
EXTSTROBE* Signal  
EXTSTROBE* is an output-only signal that generates either a single pulse  
or a sequence of eight pulses in the hardware-strobe mode. An external  
device can use this signal to latch signals or to trigger events. In the  
single-pulse mode, software controls the level of EXTSTROBE*. A 10 µs  
and a 1.2 µs clock are available for generating a sequence of eight pulses in  
the hardware-strobe mode.  
Figure 4-23 shows the timing for the hardware-strobe mode  
EXTSTROBE* signal.  
VOH  
VOL  
tw  
tw  
tw = 600 ns or 500  
s
Figure 4-23. EXTSTROBE* Signal Timing  
Note EXTSTROBE* cannot be enabled through NI-DAQ.  
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Waveform Generation Timing Connections  
The analog group defined for the device is controlled by WFTRIG,  
UPDATE*, and UISOURCE.  
WFTRIG Signal  
Any PFI pin can externally input the WFTRIG signal, which is available as  
an output on the PFI6/WFTRIG pin.  
As an input, WFTRIG is configured in the edge-detection mode. You can  
select any PFI pin as the source for WFTRIG and configure the polarity  
selection for either rising or falling edge. The selected edge of WFTRIG  
starts the waveform generation for the DACs. The update interval (UI)  
counter is started if you select internally generated UPDATE*.  
As an output, WFTRIG reflects the trigger that initiates waveform  
generation, even if the waveform generation is being externally triggered  
by another PFI. The output is an active high pulse with a pulse width of  
50 to 100 ns. This output is set to high-impedance at startup.  
Figures 4-24 and 4-25 show the input and output timing requirements for  
WFTRIG.  
tw  
Rising-Edge  
Polarity  
Falling-Edge  
Polarity  
tw = 10 ns minimum  
Figure 4-24. WFTRIG Input Signal Timing  
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tw  
tw = 50 to 100 ns  
Figure 4-25. WFTRIG Output Signal Timing  
UPDATE* Signal  
Any PFI pin can externally input the UPDATE* signal, which is available  
as an output on the PFI5/UPDATE* pin.  
As an input, UPDATE* is configured in the edge-detection mode. You can  
select any PFI pin as the source for UPDATE* and configure the polarity  
selection for either rising or falling edge. The selected edge of UPDATE*  
updates the outputs of the DACs. In order to use UPDATE*, you must set  
the DACs to posted-update mode.  
As an output, UPDATE* reflects the actual update pulse that is connected  
to the DACs, even if the updates are being externally generated by another  
PFI. The output is an active low pulse with a pulse width of 300 to 350 ns.  
This output is set to high-impedance at startup.  
Figures 4-26 and 4-27 show the input and output timing requirements for  
UPDATE*.  
tw  
Rising-Edge  
Polarity  
Falling-Edge  
Polarity  
tw = 10 ns minimum  
Figure 4-26. UPDATE* Input Signal Timing  
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tw  
tw = 300 to 350 ns  
Figure 4-27. UPDATE* Output Signal Timing  
The DACs are updated within 100 ns of the leading edge. Separate the  
UPDATE* pulses with enough time that new data can be written to the DAC  
latches.  
The device UI counter normally generates the UPDATE* signal unless you  
select some external source. The UI counter is started by the WFTRIG  
signal and can be stopped by software or the internal Buffer Counter (BC).  
D/A conversions generated by either an internal or external UPDATE*  
signal do not occur when gated by the software command register gate.  
UISOURCE Signal  
Any PFI pin can externally input the UISOURCE signal, which is not  
available as an output on the I/O connector. The UI counter uses  
UISOURCE as a clock to time the generation of the UPDATE* signal.  
You must configure the PFI pin you select as the source for UISOURCE  
in the level-detection mode. You can configure the polarity selection for  
the PFI pin for either active high or active low. Figure 4-28 shows the  
timing requirements for UISOURCE.  
tp  
tw  
tw  
tp = 50 ns minimum  
tw = 23 ns minimum  
Figure 4-28. UISOURCE Signal Timing  
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The maximum allowed frequency is 20 MHz, with a minimum pulse width  
of 23 ns high or low. There is no minimum frequency limitation.  
Either the 20 MHz or 100 kHz internal timebase normally generates  
UISOURCE unless you select some external source.  
General-Purpose Timing Signal Connections  
The general-purpose timing signals are GPCTR0_SOURCE,  
GPCTR0_GATE, GPCTR0_OUT, GPCTR0_UP_DOWN,  
GPCTR1_SOURCE, GPCTR1_GATE, GPCTR1_OUT,  
GPCTR1_UP_DOWN, and FREQ_OUT.  
GPCTR0_SOURCE Signal  
Any PFI pin can externally input the GPCTR0_SOURCE signal, which is  
available as an output on the PFI8/GPCTR0_SOURCE pin.  
As an input, GPCTR0_SOURCE is configured in the edge-detection mode.  
You can select any PFI pin as the source for GPCTR0_SOURCE and  
configure the polarity selection for either rising or falling edge.  
As an output, GPCTR0_SOURCE reflects the actual clock connected to  
general-purpose counter 0, even if another PFI externally inputs the source  
clock. This output is set to high-impedance at startup.  
Figure 4-29 shows the timing requirements for GPCTR0_SOURCE.  
tp  
tw  
tw  
tp = 50 ns minimum  
tw = 23 ns minimum  
Figure 4-29. GPCTR0_SOURCE Signal Timing  
The maximum allowed frequency is 20 MHz, with a minimum pulse width  
of 23 ns high or low. There is no minimum frequency limitation.  
The 20 MHz or 100 kHz timebase normally generates GPCTR0_SOURCE  
unless you select some external source.  
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GPCTR0_GATE Signal  
Any PFI pin can externally input the GPCTR0_GATE signal, which is  
available as an output on the PFI9/GPCTR0_GATE pin.  
As an input, GPCTR0_GATE is configured in the edge-detection mode.  
You can select any PFI pin as the source for GPCTR0_GATE and configure  
the polarity selection for either rising or falling edge. You can use the gate  
signal in a variety of different applications to perform actions such as  
starting and stopping the counter, generating interrupts, saving the counter  
contents, and so on.  
As an output, GPCTR0_GATE reflects the actual gate signal connected to  
general-purpose counter 0, even if the gate is being externally generated by  
another PFI. This output is set to high-impedance at startup.  
Figure 4-30 shows the timing requirements for GPCTR0_GATE.  
tw  
Rising-Edge  
Polarity  
Falling-Edge  
Polarity  
tw = 10 ns minimum  
Figure 4-30. GPCTR0_GATE Signal Timing in Edge-Detection Mode  
GPCTR0_OUT Signal  
This signal is available only as an output on the GPCTR0_OUT pin.  
GPCTR0_OUT reflects the terminal count (TC) of general-purpose  
counter 0. You have two software-selectable output optionspulse on TC  
and toggle output polarity on TC. The output polarity is software-selectable  
for both options. This output is set to high-impedance at startup.  
Figure 4-31 shows the timing of GPCTR0_OUT.  
Note When using external clocking mode with correlated DIO, this pin is used as an input  
for the external clock.  
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TC  
GPCTR0_SOURCE  
GPCTR0_OUT  
(Pulse on TC)  
GPCTR0_OUT  
(Toggle Output on TC)  
Figure 4-31. GPCTR0_OUT Signal Timing  
GPCTR0_UP_DOWN Signal  
This signal can be externally input on the DIO6 pin and is not available as  
an output on the I/O connector. The general-purpose counter 0 counts down  
when this pin is at a logic low and count up when it is at a logic high.  
You can disable this input so that software can control the up-down  
functionality and leave the DIO6 pin free for general use.  
GPCTR1_SOURCE Signal  
Any PFI pin can externally input the GPCTR1_SOURCE signal, which  
is available as an output on the PFI3/GPCTR1_SOURCE pin.  
As an input, GPCTR1_SOURCE is configured in the edge-detection mode.  
You can select any PFI pin as the source for GPCTR1_SOURCE and  
configure the polarity selection for either rising or falling edge.  
As an output, GPCTR1_SOURCE monitors the actual clock connected to  
general-purpose counter 1, even if the source clock is being externally  
generated by another PFI. This output is set to high-impedance at startup.  
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Figure 4-32 shows the timing requirements for GPCTR1_SOURCE.  
tp  
tw  
tw  
tp = 50 ns minimum  
tw = 23 ns minimum  
Figure 4-32. GPCTR1_SOURCE Signal Timing  
The maximum allowed frequency is 20 MHz, with a minimum pulse width  
of 23 ns high or low. There is no minimum frequency limitation.  
The 20 MHz or 100 kHz timebase normally generates GPCTR1_SOURCE  
unless you select some external source.  
GPCTR1_GATE Signal  
Any PFI pin can externally input the GPCTR1_GATE signal, which  
is available as an output on the PFI4/GPCTR1_GATE pin.  
As an input, GPCTR1_GATE is configured in edge-detection mode.  
You can select any PFI pin as the source for GPCTR1_GATE and configure  
the polarity selection for either rising or falling edge. You can use the gate  
signal in a variety of different applications to perform such actions as  
starting and stopping the counter, generating interrupts, saving the counter  
contents, and so on.  
As an output, GPCTR1_GATE monitors the actual gate signal connected  
to general-purpose counter 1, even if the gate is being externally generated  
by another PFI. This output is set to high-impedance at startup.  
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Figure 4-33 shows the timing requirements for GPCTR1_GATE.  
tw  
Rising-Edge  
Polarity  
Falling-Edge  
Polarity  
tw = 10 ns minimum  
Figure 4-33. GPCTR1_GATE Signal Timing in Edge-Detection Mode  
GPCTR1_OUT Signal  
This signal is available only as an output on the GPCTR1_OUT pin.  
GPCTR1_OUT monitors the TC device general-purpose counter 1.  
You have two software-selectable output optionspulse on TC and toggle  
output polarity on TC. The output polarity is software selectable for both  
options. This output is set to high-impedance at startup.  
Figure 4-34 shows the timing requirements for GPCTR1_OUT.  
tw  
Rising-Edge  
Polarity  
Falling-Edge  
Polarity  
tw = 10 ns minimum  
Figure 4-34. GPCTR1_OUT Signal Timing  
GPCTR1_UP_DOWN Signal  
This signal can be externally input on the DIO7 pin and is not available  
as an output on the I/O connector. General-purpose counter 1 counts down  
when this pin is at a logic low and counts up at a logic high. This input  
can be disabled so that software can control the up-down functionality  
and leave the DIO7 pin free for general use. Figure 4-35 shows the timing  
requirements for the GATE and SOURCE input signals and the timing  
specifications for the OUT output signals of the device.  
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tsc  
tsp  
tsp  
VIH  
VIL  
SOURCE  
GATE  
tgsu  
tgh  
VIH  
VIL  
tgw  
tout  
VOH  
VOL  
OUT  
Source Clock Period  
Source Pulse Width  
Gate Setup Time  
Gate Hold Time  
Gate Pulse Width  
Output Delay Time  
tsc  
tsp  
tgsu  
tgh  
tgw  
tout  
50 ns minimum  
23 ns minimum  
10 ns minimum  
0 ns minimum  
10 ns minimum  
80 ns maximum  
Figure 4-35. GPCTR Timing Summary  
The GATE and OUT signal transitions shown in Figure 4-35 are referenced  
to the rising edge of the SOURCE signal. The assumption for this timing  
diagram is that the counters are programmed to count rising edges. The  
same timing diagram, but with the source signal inverted and referenced  
to the falling edge of the source signal, would apply when the counter is  
programmed to count falling edges.  
The GATE input timing parameters are referenced to the signal at the  
SOURCE input or to one of the internally generated signals on the  
NI 6013/6014. Figure 4-35 shows the GATE signal referenced to the rising  
edge of a source signal. The gate must be valid (either high or low) for at  
least 10 ns before the rising or falling edge of a source signal for the gate to  
take effect at that source edge, as shown by tgsu and tgh in Figure 4-35.  
The gate signal is not required to be held after the active edge of the source  
signal.  
If you use an internal timebase clock, the gate signal cannot be  
synchronized with the clock. In this case, gates applied close to a source  
edge take effect either on that source edge or on the next one. This  
arrangement results in an uncertainty of one source clock period with  
respect to unsynchronized gating sources.  
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The OUT output timing parameters are referenced to the signal at the  
SOURCE input or to one of the internally generated clock signals on  
the NI 6013/6014. Figure 4-35 shows the OUT signal referenced to the  
rising edge of a source signal. Any OUT signal state changes occur within  
80 ns after the rising or falling edge of the source signal.  
FREQ_OUT Signal  
This signal is available only as an output on the FREQ_OUT pin. The  
device frequency generator outputs the FREQ_OUT pin. The frequency  
generator is a 4-bit counter that can divide its input clock by the numbers  
1 through 16. The input clock of the frequency generator is  
software-selectable from the internal 10 MHz and 100 kHz timebases.  
The output polarity is software-selectable. This output is set to  
high-impedance at startup.  
Field Wiring Considerations  
Environmental noise can seriously affect the accuracy of measurements  
made with the device if you do not take proper care when running signal  
wires between signal sources and the device. The following  
recommendations apply mainly to AI signal routing to the device, although  
they also apply to signal routing in general.  
Minimize noise pickup and maximize measurement accuracy by taking the  
following precautions:  
Use differential AI connections to reject common-mode noise.  
Use individually shielded, twisted-pair wires to connect AI signals to  
the device. With this type of wire, the signals attached to the CH+ and  
CHinputs are twisted together and then covered with a shield. You  
then connect this shield only at one point to the signal source ground.  
This kind of connection is required for signals traveling through areas  
with large magnetic fields or high electromagnetic interference.  
Route signals to the device carefully. Keep cabling away from noise  
sources. The most common noise source in a computer-based DAQ  
system is the video monitor. Separate the monitor from the analog  
signals as much as possible.  
Separate device signal lines from high-current or high-voltage lines.  
These lines can induce currents in or voltages on the device signal lines  
if they run in parallel paths at a close distance. To reduce the magnetic  
coupling between lines, separate them by a reasonable distance if they  
run in parallel, or run the lines at right angles to each other.  
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Do not run signal lines through conduits that also contain power lines.  
Protect signal lines from magnetic fields caused by electric motors,  
welding equipment, breakers, or transformers by running them through  
special metal conduits.  
For more information, refer to the NI Developer Zone tutorial, Field Wiring  
and Noise Consideration for Analog Signals, at ni.com/zone.  
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5
Calibration  
This chapter discusses the calibration procedures for the NI 6013/6014.  
NI-DAQ includes calibration functions for performing all of the steps in  
the calibration process.  
Calibration refers to the process of minimizing measurement and output  
voltage errors by making small circuit adjustments. On the NI 6013/6014,  
these adjustments take the form of writing values to onboard calibration  
DACs (CalDACs).  
Some form of device calibration is required for most applications. If you do  
not calibrate the NI 6013/6014, the signals and measurements could have  
very large offset, gain, and linearity errors.  
Three levels of calibration are available to you and described in this chapter.  
The first level is the fastest, easiest, and least accurate, whereas the last  
level is the slowest, most difficult, and most accurate.  
Loading Calibration Constants  
The NI 6013/6014 is factory calibrated before shipment at approximately  
25 °C to the levels indicated in Appendix A, Specifications. The associated  
calibration constantsthe values that were written to the CalDACs to  
achieve calibration in the factoryare stored in the onboard nonvolatile  
memory (EEPROM). Because the CalDACs have no memory capability,  
they do not retain calibration information when the device is unpowered.  
Loading calibration constants refers to the process of loading the CalDACs  
with the values stored in the EEPROM. NI-DAQ determines when loading  
calibration constants is necessary and does it automatically. If you are not  
using NI-DAQ, you must load these values yourself.  
In the EEPROM, there is a user-modifiable calibration area in addition  
to the permanent factory calibration area. The user-modifiable calibration  
area allows you to load the CalDACs with values either from the original  
factory calibration or from a calibration that you subsequently performed.  
This method of calibration is not very accurate because it does not take into  
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Chapter 5  
Calibration  
account the fact that the device measurement and output voltage errors can  
vary with time and temperature. It is better to self-calibrate when the device  
is installed in the environment in which it is used.  
Self-Calibration  
The NI 6013/6014 can measure and correct for almost all of its  
calibration-related errors without any external signal connections. NI-DAQ  
provides a self-calibration method. This self-calibration process, which  
generally takes less than two minutes, is the preferred method of assuring  
accuracy in your application. Initiate self-calibration to minimize the  
effects of any offset and gain drifts, particularly those due to warmup.  
Immediately after self-calibration, the only significant residual calibration  
error could be gain error due to time or temperature drift of the onboard  
voltage reference. This error is addressed by external calibration, which is  
discussed in the following section. If you are interested primarily in relative  
measurements, you can ignore a small amount of gain error, and  
self-calibration should be sufficient.  
External Calibration  
The NI 6013/6014 has an onboard calibration reference to ensure the  
accuracy of self-calibration. Its specifications are listed in Appendix A,  
Specifications. The reference voltage is measured at the factory and stored  
in the EEPROM for subsequent self-calibrations. This voltage is stable  
enough for most applications, but if you are using the device at an extreme  
temperature or if the onboard reference has not been measured for a year or  
more, you may wish to externally calibrate the device.  
An external calibration refers to calibrating the device with a known  
external reference rather than relying on the onboard reference.  
Redetermining the value of the onboard reference is part of this process and  
the results can be saved in the EEPROM, so you should not have to perform  
an external calibration very often. You can externally calibrate the device  
by calling the NI-DAQ calibration function.  
To externally calibrate the device, be sure to use a very accurate external  
reference. The reference should be several times more accurate than the  
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A
Specifications  
This appendix lists the specifications of the NI 6013/6014.  
These specifications are typical at 25 °C unless otherwise noted.  
Analog Input  
Input Characteristics  
Number of channels ............................... 16 single-ended or 8 differential  
(software-selectable per channel)  
Type of ADC.......................................... Successive approximation  
Resolution .............................................. 16 bits, 1 in 65,536  
Sampling rate ........................................ 200 kS/s guaranteed  
Input signal ranges ................................ Bipolar only  
Device Gain  
(Software-Selectable)  
Range  
10 V  
0.5  
1
5 V  
10  
100  
500 mV  
50 mV  
Input coupling ........................................ DC  
Overvoltage protection  
Powered Off  
15 V  
Signal Name  
Powered On  
25 V  
ACH<0..15>  
AISENSE  
15 V  
25 V  
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Appendix A  
Specifications  
FIFO buffer size......................................512 samples  
Data transfers..........................................DMA, interrupts,  
programmed I/O  
DMA modes ...........................................Scatter-gather  
(Single transfer, demand transfer)  
Number of DMA channels .....................11  
Configuration memory size ....................512 words  
Accuracy Information  
Absolute Accuracy  
Relative Accuracy  
Resolution (µV)  
Noise + Quantization  
(µV)  
Temp  
Drift  
Nominal  
Range at  
Full Scale  
(V)  
Absolute  
Accuracy at  
Full Scale  
(mV)  
% of Reading  
Offset  
(µV)  
24 Hours  
0.0658  
0.0158  
0.0658  
0.0658  
1 Year  
Single Pt.  
933.0  
466.5  
56.2  
Averaged  
82.40  
(%/°C)  
0.0010  
0.0005  
0.0010  
0.0010  
Single Point  
Averaged  
108.49  
54.245  
6.630  
10  
5
0.0700  
0.0200  
0.0700  
0.0700  
1897.5  
959.8  
115.8  
31.4  
8.984  
2.003  
0.471  
0.069  
1084.90  
542.45  
66.299  
40.382  
41.20  
0.5  
0.05  
5.035  
31.40  
3.067  
4.038  
Note: Accuracies are valid for measurements after calibration. Averaged numbers assume dithering and averaging of 100 single-channel  
readings. Measurement accuracies are listed for operational temperatures within 1 °C of internal calibration temperature and 10 °C of  
external or factory calibration temperature.  
Transfer Characteristics  
Relative accuracy.................................... 1.0 LSB typ, 3.0 LSB max  
DNL........................................................ 0.5 LSB typ, 1.0 LSB max  
No missing codes....................................16 bits, guaranteed  
Offset error  
Pregain error after calibration.......... 2.0 µV max  
Pregain error before calibration....... 28.8 mV max  
Postgain error after calibration........ 305 µV max  
Postgain error before calibration ..... 40.2 mV max  
1
The NI 6013/6014 has one DMA channel to be shared by all resources on the device.  
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Appendix A  
Specifications  
Gain error (relative to calibration reference)  
After calibration (gain = 1) ............. 74 ppm of reading max  
Before calibration ........................... 18,900 ppm of reading max  
Gain 1 with gain error  
adjusted to 0 at gain = 1................. 300 ppm of reading max  
Amplifier Characteristics  
Input impedance  
Normal powered on ........................ 100 Gin parallel with 100 pF  
Powered off..................................... 820 Ω  
Overload.......................................... 820 Ω  
Input bias current ................................... 200 pA  
Input offset current................................. 100 pA  
CMRR (DC to 60 Hz)  
Gain 0.5, 1.0.................................... 85 dB  
Gain 10, 100.................................... 96 dB  
Dynamic Characteristics  
Bandwidth  
Signal  
Small (3 dB)  
Bandwidth  
425 kHz  
Large (1% THD)  
450 kHz  
Settling time for full-scale step  
Gain 100.......................................... 2 LSB, 5 µs typ  
Gain 1, 10........................................ 2 LSB, 5 µs max  
Gain 0.5........................................... 4 LSB, 5 µs typ  
System noise (LSBrms, including quantization)  
Gain  
0.5, 1.0  
10  
LSBrms  
0.9  
1.1  
100  
6.7  
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Appendix A  
Specifications  
Crosstalk .................................................DC to 100 kHz  
Adjacent channels............................75 dB  
Other channels.................................≤ 90 dB  
Stability  
Recommended warm-up time.................15 min  
Offset temperature coefficient  
Pregain............................................. 20 µV/°C  
Postgain ........................................... 175 µV/°C  
Gain temperature coefficient .................. 32 ppm/°C  
Analog Output  
NI 6014 only  
Output Characteristics  
Number of channels................................2 voltage  
Resolution...............................................16 bits, 1 in 65,536  
Max update rate  
DMA................................................10 kHz, system dependent  
Interrupts..........................................1 kHz, system dependent  
Type of DAC ..........................................Double buffered, multiplying  
FIFO buffer size......................................None  
Data transfers..........................................DMA, interrupts,  
programmed I/O  
DMA modes ...........................................Scatter-gather  
(Single transfer, demand transfer)  
Number of DMA channels .....................11  
1
The NI 6013/6014 has one DMA channel to be shared by all resources on the device.  
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Appendix A  
Specifications  
Accuracy Information  
Absolute Accuracy  
Nominal Range (V)  
% of Reading  
Absolute  
Accuracy at  
Full Scale  
(µV)  
Offset  
(µV)  
Temp Drift  
Positive FS  
Negative FS  
24 Hours  
90 Days  
1 Year  
(%/°C)  
10  
10  
0.0154  
0.0174  
0.0196  
1,873  
0.0005  
3,835  
Transfer Characteristics  
Relative accuracy (INL)......................... 3 LSB, typ  
DNL ....................................................... 2 LSB, typ  
Monotonicity.......................................... 15 bits  
Offset error  
After calibration.............................. 372 µV max  
Before calibration ........................... 250 mV max  
Gain error (relative to internal reference)  
After calibration.............................. 75 ppm  
Before calibration ........................... 22,700 ppm  
Voltage Output  
Range ..................................................... 10 V  
Output coupling...................................... DC  
Output impedance .................................. 0.1 max  
Current drive .......................................... 5 mA max  
Protection ............................................... Short-circuit to ground  
Power-on state (steady state).................. 250 mV  
Initial power-up glitch  
Magnitude ....................................... 6.0 V  
Duration .......................................... 4 ms  
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Appendix A  
Specifications  
Power reset glitch  
Magnitude........................................ 3.0 V  
Duration...........................................3 ms  
Dynamic Characteristics  
Settling time for full-scale step...............8 µs to 1 LSB accuracy  
Slew rate .................................................4 V/µs  
Noise.......................................................360 µVrms, DC to 400 kHz  
Midscale transition glitch  
Magnitude........................................ 200 mV  
Duration...........................................2.0 µs  
Stability  
Offset temperature coefficient................ 128 µV/°C  
Gain temperature coefficient .................. 26.8 ppm/°C  
Digital I/O  
Number of channels................................8 input/output  
Compatibility..........................................TTL/CMOS  
DIO<0..7>  
Digital logic levels  
Level  
Min  
0 V  
2 V  
Max  
0.8 V  
5 V  
Input low voltage  
Input high voltage  
Input low current (Vin = 0 V)  
Input high current (Vin = 5 V)  
Output low voltage (IOL = 24 mA)  
Output high voltage (IOH = 10 mA)  
320 µA  
10 µA  
0.4 V  
4.35 V  
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Appendix A  
Specifications  
Power-on state........................................ Input (high-impedance),  
1.5 kpull down to DGND  
Data transfers ......................................... Programmed I/O  
Max transfer rate .................................... 50 kwords/s, system dependent  
Timing I/O  
Number of channels ............................... 2 up/down counter/timers,  
1 frequency scaler  
Resolution  
Counter/timers ................................ 24 bits  
Frequency scalers............................ 4 bits  
Compatibility ......................................... TTL/CMOS  
Base clocks available  
Counter/timers ................................ 20 MHz, 100 kHz  
Frequency scalers............................ 10 MHz, 100 kHz  
Base clock accuracy............................... 0.01%  
Max source frequency............................ 20 MHz  
Min source pulse duration...................... 10 ns in edge-detect mode  
Min gate pulse duration.......................... 10 ns in edge-detect mode  
Data transfers ......................................... DMA, interrupts,  
programmed I/O  
DMA modes........................................... Scatter-gather  
(Single transfer, demand transfer)  
Number of DMA channels..................... 11  
1
The NI 6013/6014 has one DMA channel to be shared by all resources on the device.  
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Appendix A  
Specifications  
Triggers  
Digital Trigger  
Compatibility..........................................TTL  
Response.................................................Rising or falling edge  
Pulse width .............................................10 ns min  
Calibration  
Recommended warm-up time.................15 min  
Interval....................................................1 year  
External calibration reference.................>6 and <10 V  
Onboard calibration reference  
Level................................................5.000 V ( 3.5 mV)  
(over full operating temperature,  
actual value stored in EEPROM)  
Temperature coefficient................... 5 ppm/°C max  
Long-term stability.......................... 15 ppm/ 1,000 h  
Power Requirement  
+5 VDC ( 5%) .......................................0.7 A  
Note Excludes power consumed through VCC available at the I/O connector.  
Power available at I/O connector............+4.65 to +5.25 VDC at 1 A  
Physical  
Dimensions  
(not including connectors)......................17.5 by 10.6 cm (6.9 by 4.2 in.)  
I/O connector ..........................................68-pin male SCSI-II type  
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Appendix A  
Specifications  
Maximum Working Voltage  
Maximum working voltage refers to the signal voltage plus the  
common-mode voltage.  
Channel-to-earth..................................... 11 V, Installation Category II  
Environmental  
Operating temperature............................ 0 to 50 °C  
Storage temperature ............................... 20 to 70 °C  
Humidity ................................................ 10 to 70% RH, noncondensing  
Maximum altitude.................................. 2,000 meters  
Pollution Degree (indoor use only)........ 2  
Safety  
The NI 6013/6014 meets the requirements of the following standards for  
safety and electrical equipment for measurement, control, and laboratory  
use:  
EN 61010-1:1993/A2:1995, IEC 61010-1:1990/A2:1995  
UL 3101-1:1993, UL 3111-1:1994, UL 3121:1998  
CAN/CSA c22.2 no. 1010.1:1992/A2:1997  
Electromagnetic Compatibility  
CE, C-Tick, and FCC Part 15 (Class A) Compliant  
Electrical emissions................................ EN 55011 Class A at 10 m  
FCC Part 15A above 1 GHz  
Electrical immunity................................ Evaluated to EN 61326:1998,  
Table 1  
Note For full EMC compliance, you must operate this device with shielded cabling.  
In addition, all covers and filler panels must be installed. Refer to the DoC for this product  
for any additional regulatory compliance information. To obtain the DoC for this product,  
click Declaration of Conformity at ni.com/hardref.nsf/. This Web site lists the  
DoCs by product family. Select the appropriate product family, followed by the product,  
and a link to the DoC appears in Adobe Acrobat format. Click the Acrobat icon to  
download or read the DoC.  
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B
Custom Cabling and Optional  
Connectors  
This appendix describes the various cabling and connector options for the  
NI 6013/6014.  
Custom Cabling  
NI offers cables and accessories for you to prototype your application or to  
use if you frequently change device interconnections.  
If you want to develop your own cable, however, adhere to the following  
guidelines for best results:  
For AI signals, use shielded twisted-pair wires for each AI pair for  
differential inputs. Tie the shield for each signal pair to the ground  
reference at the source.  
Route the analog lines separately from the digital lines.  
When using a cable shield, use separate shields for the analog and  
digital halves of the cable. Failure to do so results in noise coupling  
into the analog signals from transient digital signals.  
Mating connectors and a backshell kit for making custom 68-pin cables are  
available from NI.  
The parts in the following list are recommended for connectors that mate to  
the I/O connector on the NI 6013/6014:  
Honda 68-position, solder cup, female connector  
Honda backshell  
Optional Connectors  
Figure B-1 shows the pin assignments for the 68-pin connector.  
This connector is available when you use the SH6868 or R6868 cable  
assemblies.  
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Appendix B  
Custom Cabling and Optional Connectors  
34 68  
ACH1 33 67  
ACH8  
ACH0  
AIGND  
ACH9  
32 66  
31 65  
30 64  
29 63  
28 62  
AIGND  
ACH10  
ACH3  
ACH2  
AIGND  
ACH11  
AISENSE  
ACH12  
ACH5  
AIGND  
ACH4  
AIGND 27 61  
ACH13 26 60  
ACH6  
AIGND 24 58  
25 59  
AIGND  
ACH14  
ACH7  
ACH15  
23 57  
22 56  
21 55  
DAC0OUT1  
DAC1OUT1  
AIGND  
AOGND  
AOGND  
DGND  
DIO0  
RESERVED 20 54  
19 53  
18 52  
17 51  
16 50  
15 49  
DIO4  
DGND  
DIO1  
DIO5  
DIO6  
DGND  
DIO2  
DGND  
+5V 14 48  
DGND 13 47  
DGND 12 46  
DIO7  
DIO3  
SCANCLK  
PFI0/TRIG1  
11 45  
10 44  
EXTSTROBE*  
DGND  
PFI1/TRIG2  
DGND  
9
8
7
6
5
4
3
2
1
43  
42  
41  
40  
39  
38  
37  
36  
35  
PFI2/CONVERT*  
PFI3/GPCTR1_SOURCE  
PFI4/GPCTR1_GATE  
GPCTR1_OUT  
DGND  
+5V  
DGND  
PFI5/UPDATE*  
PFI6/WFTRIG  
DGND  
PFI7/STARTSCAN  
PFI8/GPCTR0_SOURCE  
DGND  
PFI9/GPCTR0_GATE  
GPCTR0_OUT  
FREQ_OUT  
DGND  
1 Not available on the NI 6013  
Figure B-1. 68-Pin Connector Pin Assignments  
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Appendix B  
Custom Cabling and Optional Connectors  
Figure B-2 shows the pin assignments for the 50-pin connector.  
This connector is available when you use the SH6850 or R6850 cable  
assemblies.  
1
3
5
7
9
2
4
AIGND  
ACH0  
ACH1  
AIGND  
ACH8  
ACH9  
ACH10  
ACH11  
ACH12  
ACH13  
ACH14  
6
8
ACH2  
ACH3  
10  
11 12  
13 14  
15 16  
17 18  
19 20  
21 22  
23 24  
25 26  
27 28  
29 30  
31 32  
33 34  
ACH4  
ACH5  
ACH6  
ACH7  
ACH15  
DAC0OUT1  
RESERVED  
AISENSE  
DAC1OUT1  
AOGND  
DIO0  
DGND  
DIO4  
DIO1  
DIO5  
DIO2  
DIO6  
DIO3  
DIO7  
DGND  
+5V  
+5V 35 36  
SCANCLK  
PFI0/TRIG1  
PFI2/CONVERT*  
PFI4/GPCTR1_GATE  
PFI5/UPDATE*  
PFI7/STARTSCAN  
PFI9/GPCTR0_GATE  
FREQ_OUT  
37 38  
39 40  
41 42  
43 44  
45 46  
47 48  
49 50  
EXTSTROBE*  
PFI1/TRIG2  
PFI3/GPCTR1_SOURCE  
GPCTR1_OUT  
PFI6/WFTRIG  
PFI8/GPCTR0_SOURCE  
GPCTR0_OUT  
1 Not available on the NI 6013  
Figure B-2. 50-Pin Connector Pin Assignments  
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C
Common Questions  
This appendix contains a list of commonly asked questions and their  
answers relating to usage and special features of the NI 6013/6014.  
General Information  
What is the DAQ-STC?  
The DAQ-STC is the system timing control application-specific  
integrated circuit (ASIC) designed by NI and is the backbone of the  
NI 6013/6014. The DAQ-STC contains seven 24-bit counters and three  
16-bit counters. The counters are divided into the following three groups:  
AItwo 24-bit, two 16-bit counters  
AOthree 24-bit, one 16-bit counters  
General-purpose counter/timer functionstwo 24-bit counters  
The groups can be configured independently with timing resolutions of  
50 ns or 10 µs. With the DAQ-STC, you can interconnect a wide variety of  
internal timing signals to other internal blocks. The interconnection scheme  
is quite flexible and completely software configurable. New capabilities  
such as buffered pulse generation, equivalent time sampling, and seamless  
changing of the sampling rate are possible.  
What does sampling rate mean to me?  
Sampling rate is the fastest you can acquire data on the NI 6013/6014 and  
still achieve accurate results. For example, these devices have a sampling  
rate of 200 kS/s. This sampling rate is aggregate: one channel at 200 kS/s  
or two channels at 100 kS/s per channel illustrates the relationship.  
What type of 5 V protection does the NI 6013/6014 have?  
The NI 6013/6014 has 5 V lines equipped with a self-resetting 1 A fuse.  
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Appendix C  
Common Questions  
How do I use the NI 6013/6014 with the C API in NI-DAQ?  
The NI-DAQ User Manual for PC Compatibles contains example code and  
describes the general programming flow when using the NI-DAQ C API.  
For a list of functions that support the NI 6013/6014, refer to the NI-DAQ  
Function Reference Help (NI-DAQ version 6.7 or later) or the NI-DAQ  
Function Reference Manual for PC Compatibles (NI-DAQ version 6.6 or  
earlier).  
Refer to ni.com/manuals for the NI-DAQ User Manual for PC  
Compatibles, and refer to ni.com/downloads to download the version of  
NI-DAQ that your application requires.  
Installing and Configuring the Device  
How do I set the base address for the NI 6013/6014?  
The base address of the NI 6013/6014 is assigned automatically through  
the PCI bus protocol. This assignment is completely transparent to you.  
What jumpers should I be aware of when configuring the  
NI 6013/6014?  
The NI 6013/6014 is jumperless and switchless.  
Which NI document should I read first to get started using DAQ  
software?  
The DAQ Quick Start Guide and the NI-DAQ or ADE release notes  
documentation are good places to start.  
What version of NI-DAQ must I have to use the NI 6013/6014?  
The NI 6013/6014 requires NI-DAQ version 6.9.3 or later.  
What is the best way to test the NI 6013/6014 without programming  
the device?  
If you are using Windows, Measurement & Automation Explorer (MAX)  
has a Test Panel option that is available by selecting Devices and  
Interfaces and then selecting the device. The Test Panels are excellent tools  
for performing simple functional tests of the device, such as AI, DIO, and  
counter/timer tests.  
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Appendix C  
Common Questions  
Analog Input and Output  
I am using the device in differential AI mode, and I have connected a  
differential input signal, but the readings are random and drift rapidly.  
What is wrong?  
Check the ground reference connections. The signal may be referenced  
to a level that is considered floating with reference to the device ground  
reference. Even if you are in differential mode, the signal must still be  
referenced to the same ground level as the device reference. You can use  
one of various methods to achieve ground reference while maintaining  
a high common-mode rejection ratio (CMRR). Refer to Chapter 4,  
Connecting Signals, for more information.  
I am using the DACs to generate a waveform, but I discovered with a  
digital oscilloscope that there are glitches on the output signal. Is this  
normal?  
When it switches from one voltage to another, any DAC produces glitches  
due to released charges. The largest glitches occur when the most  
significant bit (MSB) of the D/A code switches. You can build a lowpass  
deglitching filter to remove some of these glitches, depending on the  
frequency and nature of the output signal.  
Can I programmatically enable channels on the NI 6013/6014 to  
acquire in different modes? For example, can I configure ACH0 in  
DIFF input mode and ACH1 in NRSE input mode?  
Channels on the NI 6013/6014 can be enabled to acquire in different  
modes, but different pairs of channels are used in different modes. In the  
example configuration given above, ACH0 and ACH8 are configured in  
DIFF mode and ACH1 and AISENSE are configured in NRSE mode.  
In this configuration, ACH8 is not used in a single-ended configuration.  
To enable multimode scanning in LabVIEW, use the coupling and input  
configuration cluster input of the AI Config VI. This input has a one-to-one  
correspondence with the channel array input of the AI Config VI. You must  
list all channels either individually or in groups of channels with the same  
input configuration. For example, if you want ACH0 to be differential, and  
ACH1 and ACH2 to be NRSE, Figure C-1 demonstrates how to program  
this configuration in LabVIEW.  
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Appendix C  
Common Questions  
1:2  
Figure C-1. Configuring Channels to Acquire in Different Modes in LabVIEW  
To enable multimode scanning in using NI-DAQ functions, call the  
AI_Configure function for each channel.  
I am seeing crosstalk or ghost voltages when sampling multiple  
channels. What does this mean?  
You maybe experiencing a phenomenon called charge injection, which  
occurs when you sample a series of high-output impedance sources with  
a multiplexer. Multiplexers contain switches, usually made of switched  
capacitors. When a channel, for example ACH0, is selected in a  
multiplexer, those capacitors accumulate charge. When the next channel,  
for example ACH1, is selected, the accumulated current, or charge, leaks  
backward through that channel. If the output impedance of the source  
connected to ACH1 is high enough, the resulting reading can somewhat  
reflect the voltage trends in ACH0. To circumvent this problem, you must  
use a voltage follower that has operational amplifiers (op-amps) with unity  
gain for each high-impedance source before connecting to the DAQ device.  
Otherwise, you must decrease the rate at which each channel is sampled.  
Another common cause of channel crosstalk is due to sampling among  
multiple channels at various gains. In this situation, the settling times may  
increase. For more information on charge injection and sampling channels  
at different gains, refer to the Multichannel Scanning Considerations  
section of Chapter 3, Hardware Overview.  
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Common Questions  
How can I use the STARTSCAN and CONVERT* signals on the  
NI 6013/6014 to sample the AI channel(s)?  
The NI 6013/6014 uses the STARTSCAN and CONVERT* signals to  
perform interval sampling. As Figure C-2 shows, STARTSCAN controls  
the scan interval, which is determined by the following equality:  
1
------------------------------ = scan rate  
scan interval  
Channel 0  
Channel 1  
Interchannel Delay  
Scan Interval  
Figure C-2. Scan Interval  
CONVERT* controls the interchannel delay, which is determined by the  
following equality:  
1
-------------------------------------------- = sampling rate  
interchannel delay  
This method allows multiple channels to be sampled relatively quickly in  
relationship to the overall scan rate, providing a nearly simultaneous effect  
with a fixed delay between channels.  
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Appendix C  
Common Questions  
Timing and Digital I/O  
What types of triggering can be hardware-implemented on the  
NI 6013/6014?  
Digital triggering is hardware-supported on the NI 6013/6014.  
I am using one of the general-purpose counter/timers on the device, but  
I do not see the counter/timer output on the I/O connector. Why?  
If you are using the NI-DAQ language interface or LabWindows/CVI, you  
must configure the output line to output the signal to the I/O connector. Use  
the Select_Signal function in NI-DAQ to configure the output line.  
By default, all timing I/O lines except EXTSTROBE* are tri-stated.  
What are the PFIs and how do I configure these lines?  
PFIs are Programmable Function Inputs. These lines serve as connections  
to virtually all internal timing signals.  
If you are using NI-DAQ or Measurement Studio, use the Select_Signal  
function to route internal signals to the I/O connector, route external signals  
to internal timing sources, or tie internal timing signals together.  
If you are using NI-DAQ with LabVIEW and you want to connect external  
signal sources to the PFI lines, you can use the AI Clock Config, AI Trigger  
Config, AO Clock Config, AO Trigger and Gate Config, and Counter Set  
Attribute advanced-level VIs to indicate which function the connected  
signal serves. Use the Route Signal VI to enable the PFI lines to output  
internal signals.  
Caution If you enable a PFI line for output, do not connect any external signal sources to  
it; if you do, you can damage the device, the computer, and the connected equipment.  
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Appendix C  
Common Questions  
Table C-1 corresponds the hardware signal names to the software signal  
names in LabVIEW and NI-DAQ.  
Table C-1. Signal Name Equivalencies  
Hardware  
LabVIEW  
Signal Name  
Route Signal  
AI Start Trigger  
AI Stop Trigger  
AI Scan Start  
NI-DAQ Select_Signal  
ND_IN_START_TRIGGER  
TRIG1  
TRIG2  
ND_IN_STOP_TRIGGER  
STARTSCAN  
SISOURCE  
CONVERT*  
AIGATE  
ND_IN_SCAN_START  
ND_IN_SCAN_CLOCK_TIMEBASE  
ND_IN_CONVERT  
AI Convert  
ND_IN_EXTERNAL_GATE  
ND_OUT_START_TRIGGER  
ND_OUT_UPDATE  
WFTRIG  
AO Start Trigger  
AO Update  
UPDATE*  
UISOURCE  
AOGATE  
ND_OUT_UPDATE_CLOCK_TIMEBASE  
ND_OUT_EXTERNAL_GATE  
What are the power-on states of the PFI and DIO lines on the I/O  
connector?  
At system power-on and reset, both the PFI and DIO lines are set to  
circuitry is not actively driving the output either high or low. However,  
these lines may have pull-up or pull-down resistors connected to them as  
shown in Table 4-3, I/O Signal Summary for the NI 6013/6014. These  
resistors weakly pull the output to either a logic-high or logic-low state.  
For example, DIO<0> is in the high-impedance state after power on, and  
Table 4-3, I/O Signal Summary for the NI 6013/6014, shows the 1.5 kΩ  
pull-down resistor. This pull-down resistor sets the DIO<0> pin to a logic  
low when the output is in a high-impedance state.  
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D
Technical Support and  
Professional Services  
Visit the following sections of the NI Web site at ni.com for technical  
support and professional services:  
SupportOnline technical support resources include the following:  
Self-Help ResourcesFor immediate answers and solutions,  
visit our extensive library of technical support resources available  
in English, Japanese, and Spanish at ni.com/support. These  
resources are available for most products at no cost to registered  
users and include software drivers and updates, a KnowledgeBase,  
product manuals, step-by-step troubleshooting wizards, hardware  
schematics and conformity documentation, example code,  
tutorials and application notes, instrument drivers, discussion  
forums, a measurement glossary, and so on.  
Assisted Support OptionsContact NI engineers and other  
measurement and automation professionals by visiting  
ni.com/ask. Our online system helps you define your question  
and connects you to the experts by phone, discussion forum,  
or email.  
TrainingVisit ni.com/custed for self-paced tutorials, videos, and  
interactive CDs. You also can register for instructor-led, hands-on  
courses at locations around the world.  
System IntegrationIf you have time constraints, limited in-house  
technical resources, or other project challenges, NI Alliance Program  
members can help. To learn more, call your local NI office or visit  
ni.com/alliance.  
If you searched ni.com and could not find the answers you need, contact  
your local office or NI corporate headquarters. Phone numbers for our  
worldwide offices are listed at the front of this manual. You also can visit  
the Worldwide Offices section of ni.com/niglobal to access the branch  
office Web sites, which provide up-to-date contact information, support  
phone numbers, email addresses, and current events.  
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Glossary  
Prefix  
p-  
Meanings  
pico  
Value  
1012  
109  
106  
103  
103  
n-  
nano-  
micro-  
milli-  
kilo-  
µ-  
m-  
k-  
M-  
G-  
mega-  
giga-  
106  
109  
Symbols  
%
percent  
+
positive of, or plus  
negative of, or minus  
plus or minus  
per  
/
°
degree  
ohm  
A
A
amperes  
A/D  
ACH  
analog-to-digital  
AI channel signal  
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Glossary  
ADC  
analog-to-digital converteran electronic device, often an integrated  
circuit, that converts an analog voltage to a digital number  
AI  
analog input  
AIGATE  
AIGND  
AISENSE  
ANSI  
AI gate signal  
AI ground signal  
AI sense signal  
American National Standards Institute  
analog output  
AO  
AOGND  
AO ground signal  
B
base address  
a memory address that serves as the starting address for programmable  
registers. All other addresses are located by adding to the base address.  
bipolar  
a signal range that includes both positive and negative values (for example,  
5 to +5 V)  
BC  
bus  
buffered counter  
the group of conductors that interconnect individual circuitry in a computer.  
Typically, a bus is the expansion vehicle to which I/O or other devices are  
connected. Examples of PC buses are the ISA and PCI bus.  
C
C
Celsius  
CalDAC  
CH  
calibration DAC  
channelpin or wire lead to which you apply or from which you read the  
analog or digital signal. Analog signals can be single-ended or differential.  
For digital signals, you group channels to form ports. Ports usually consist  
of either four or eight digital channels.  
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Glossary  
CMRR  
common-mode rejection ratioa measure of an instruments ability to  
reject interference from a common-mode signal, usually expressed in  
decibels (dB)  
common-mode signal  
any voltage present at the instrumentation amplifier inputs with respect to  
amplifier ground  
CONVERT*  
counter/timer  
convert signal  
a circuit that counts external pulses or clock pulses (timing)  
D
D/A  
digital-to-analog  
DAC  
digital-to-analog converteran electronic device, often an integrated  
circuit, that converts a digital number into a corresponding analog voltage  
or current  
DAC0OUT  
DAC1OUT  
DAQ  
analog channel 0 output signal  
analog channel 1 output signal  
data acquisition(1) collecting and measuring electrical signals from  
sensors, transducers, and test probes or fixtures and inputting them to a  
computer for processing; (2) collecting and measuring the same kinds of  
electrical signals with A/D and/or DIO devices plugged into a computer,  
and possibly generating control signals with D/A and/or DIO devices in the  
same computer  
dB  
decibelthe unit for expressing a logarithmic measure of the ratio of  
two signal levels: dB = 20log10 V1/V2, for signals in volts  
DC  
direct current  
DGND  
digital ground signal  
differential mode  
DIFF  
differential input  
an analog input consisting of two terminals, both of which are isolated from  
computer ground, whose difference is measured  
DIO  
digital input/output  
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Glossary  
dithering  
DMA  
the addition of Gaussian noise to an AI signal  
direct memory accessa method by which data can be transferred to/from  
computer memory from/to a device or memory on the bus while the  
processor does something else. DMA is the fastest method of transferring  
data to/from computer memory.  
DNL  
differential nonlinearitya measure in least significant bit of the  
worst-case deviation of code widths from their ideal value of 1 LSB  
DO  
digital output  
DoC  
DOC  
driver  
Declaration of Conformity  
Department of Communications  
software that controls a specific hardware device such as a DAQ device or  
a GPIB interface board  
E
EEPROM  
electrically erasable programmable read-only memoryROM that can be  
erased with an electrical signal and reprogrammed  
EXTSTROBE  
external strobe signal  
F
FCC  
Federal Communications Commission  
FIFO  
first-in first-out memory bufferthe first data stored is the first data sent to  
the acceptor. FIFOs are often used on DAQ devices to temporarily store  
incoming or outgoing data until that data can be retrieved or output. For  
example, an AI FIFO stores the results of A/D conversions until the data  
can be retrieved into system memory, a process that requires the servicing  
of interrupts and often the programming of the DMA controller. This  
process can take several milliseconds in some cases. During this time, data  
accumulates in the FIFO for future retrieval. With a larger FIFO, longer  
latencies can be tolerated. In the case of analog output, a FIFO permits  
faster update rates, because the waveform data can be stored on the FIFO  
ahead of time. This again reduces the effect of latencies associated with  
getting the data from system memory to the DAQ device.  
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floating signal sources  
FREQ_OUT  
signal sources with voltage signals that are not connected to an absolute  
reference or system ground. Also called nonreferenced signal sources.  
Some common example of floating signal sources are batteries,  
transformers, or thermocouples.  
frequency output signal  
G
gain  
the factor by which a signal is amplified, sometimes expressed in decibels  
a measure of deviation of the gain of an amplifier from the ideal gain  
gate signal  
gain accuracy  
GATE  
glitch  
an unwanted momentary deviation from a desired signal  
general purpose counter  
GPCTR  
GPCTR0_GATE  
GPCTR0_OUT  
GPCTR0_SOURCE  
GPCTR0_UP_DOWN  
GPCTR1_GATE  
GPCTR1_OUT  
GPCTR1_SOURCE  
GPCTR1_UP_DOWN  
general purpose counter 0 gate signal  
general purpose counter 0 output signal  
general purpose counter 0 clock source signal  
general purpose counter 0 up down  
general purpose counter 1 gate signal  
general purpose counter 1 output signal  
general purpose counter 1 clock source signal  
general purpose counter 1 up down  
grounded measurement See referenced single-ended configuration.  
system  
H
h
hour  
Hz  
hertzthe number of scans read or updates written per second  
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Glossary  
I
I/O  
input/outputthe transfer of data to/from a computer system involving  
communications channels, operator interface devices, and/or data  
acquisition and control interfaces  
in.  
inches  
INL  
integral nonlinearitya measure in LSB of the worst-case deviation from  
the ideal A/D or D/A transfer characteristic of the analog I/O circuitry  
input bias current  
input impedance  
input offset current  
the current that flows into the inputs of a circuit  
the resistance and capacitance between the input terminals of a circuit  
the difference in the input bias currents of the two inputs of an  
instrumentation amplifier  
instrumentation  
amplifier  
a circuit whose output voltage with respect to ground is proportional to the  
difference between the voltages at its two high impedance inputs  
interrupt  
a computer signal indicating that the CPU should suspend its current task  
to service a designated activity  
IOH  
IOL  
current, output high  
current, output low  
K
k
kilothe standard metric prefix for 1,000, or 103, used with units of  
measure such as volts, hertz, and meters  
kS  
1,000 samples  
L
LabVIEW  
Laboratory Virtual Instrument Engineering Workbencha program  
development application based on the programming language G and used  
commonly for test and measurement purposes  
LED  
light-emitting diode  
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Glossary  
library  
a file containing compiled object modules, each comprised of one of more  
functions, that can be linked to other object modules that make use of these  
functions. NIDAQMSC.LIB is a library that contains NI-DAQ functions.  
The NI-DAQ function set is broken down into object modules so that only  
the object modules that are relevant to your application are linked in, while  
those object modules that are not relevant are not linked.  
linearity  
LSB  
the adherence of device response to the equation R = KS, where  
R = response, S = stimulus, and K = a constant  
least significant bit  
M
MITE  
MXI Interface to Everythinga custom ASIC designed by NI that  
implements the PCI bus interface. The MITE supports bus mastering  
for high-speed data transfers over the PCI bus.  
MSB  
mux  
most significant bit  
multiplexera switching device with multiple inputs that sequentially  
connects each of its inputs to its output, typically at high speeds, in order  
to measure several signals with a single AI channel  
N
NI  
National Instruments  
NI-DAQ  
noise  
National Instruments driver software for DAQ hardware  
an undesirable electrical signalnoise comes from external sources such  
as the AC power line, motors, generators, transformers, fluorescent lights,  
soldering irons, CRT displays, computers, electrical storms, welders, radio  
transmitters, and internal sources such as semiconductors, resistors, and  
capacitors. Noise corrupts signals you are trying to send or receive.  
NRSE  
nonreferenced single-ended modeall measurements are made with  
respect to a common (NRSE) measurement system reference, but the  
voltage at this reference can vary with respect to the measurement system  
ground.  
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Glossary  
O
OUT  
output pina counter output pin where the counter can generate various  
TTL pulse waveforms  
P
PCI  
Peripheral Component Interconnecta high-performance expansion bus  
architecture originally developed by Intel to replace ISA and EISA. It is  
achieving widespread acceptance as a standard for PCs and work-stations;  
it offers a theoretical maximum transfer rate of 132 Mbytes/s.  
pd  
pull down  
PFI  
programmable function input  
PFI0/trigger 1  
PFI0/TRIG1  
PFI1/TRIG2  
PFI2/CONVERT*  
PFI1/trigger 2  
PFI2/convert  
PFI3/GPCTR1_  
SOURCE  
PFI3/general purpose counter 1 source  
PFI4/GPCTR1_GATE  
PFI5/UPDATE*  
PFI4/general purpose counter 1 gate  
PFI5/update  
PFI6/WFTRIG  
PFI6/waveform trigger  
PFI7/STARTSCAN  
PFI7/start of scan  
PFI8/GPCTR0_  
SOURCE  
PFI8/general purpose counter 0 source  
PFI9/GPCTR0_GATE  
PFI9/general purpose counter 0 gate  
PGIA  
port  
programmable gain instrumentation amplifier  
(1) a communications connection on a computer or a remote controller;  
(2) a digital port, consisting of four or eight lines of digital input and/or  
output  
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Glossary  
ppm  
pu  
parts per million  
pull up  
Q
quantization error  
the inherent uncertainty in digitizing an analog value due to the finite  
resolution of the conversion process  
R
referenced single-ended RSEall measurements are made with respect to a common reference  
configuration  
measurement system or ground; also called a grounded measurement  
system  
relative accuracy  
a measure in LSB of the accuracy of an ADC. It includes all non-linearity  
and quantization errors. It does not include offset and gain errors of the  
circuitry feeding the ADC.  
resolution  
the smallest signal increment that can be detected by a measurement  
system. Resolution can be expressed in bits, in proportions, or in percent  
of full scale. For example, a system has 12-bit resolution, one part in  
4,096 resolution, and 0.0244% of full scale.  
ribbon cable  
rms  
a flat cable in which the wires are lined up, not bunched together  
root mean squarethe square root of the average value of the square of the  
instantaneous signal amplitude; a measure of signal amplitude  
RSE  
See referenced single-ended configuration.  
S
s
seconds  
samples  
S
S/s  
samples per secondused to express the rate at which a DAQ device  
samples an analog signal  
sample counter  
the clock that counts the output of the channel clock, in other words, the  
number of samples taken. On devices with simultaneous sampling, this  
counter counts the output of the scan clock and hence the number of scans.  
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Glossary  
SC  
scan counter  
scan  
one or more analog or digital input samples. Typically, the number of input  
samples in a scan is equal to the number of channels in the input group. For  
example, one pulse from the scan clock produces one scan which acquires  
one new sample from every AI channel in the group.  
scan clock  
the clock controlling the time interval between scans  
settling time  
the amount of time required for a voltage to reach its final value within  
specified limits  
SI  
scan interval  
SI2  
sample interval  
signal conditioning  
SISOURCE  
software trigger  
SOURCE  
STARTSCAN  
STC  
the manipulation of signals to prepare them for digitizing  
SI counter clock signal  
a programmed event that triggers an event such as data acquisition  
source signal  
start scan signal  
system timing controller  
T
TC  
terminal countthe highest value of a counter  
gate hold time  
tgh  
tgsu  
tgw  
THD  
gate setup time  
gate pulse width  
total harmonic distortionthe ratio of the total rms signal due to harmonic  
distortion to the overall rms signal, in decibel or a percentage  
toff  
tout  
pulse off  
output delay time  
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Glossary  
tp  
pulse period  
TRIG  
trigger  
tsc  
trigger signal  
any event that causes or starts some form of data capture  
source clock period  
tsp  
source pulse width  
TTL  
transistor-transistor logica digital circuit composed of bipolar transistors  
wired in a certain manner  
tw  
pulse width  
twos complement  
given a number x expressed in base 2 with n digits to the left of the radix  
point, the (base 2) number 2n x  
U
UI  
update interval  
UISOURCE  
update  
update interval counter clock signal  
the output equivalent of a scan. One or more analog or digital output  
samples. Typically, the number of output samples in an update is equal to  
the number of channels in the output group. For example, one pulse from  
the update clock produces one update which sends one new sample to every  
AO channel in the group.  
update rate  
the number of output updates per second  
V
V
volts  
VCC  
VDC  
VIH  
VIL  
positive supply voltage  
volts direct current  
volts, input high  
volts, input low  
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Glossary  
Vin  
volts in  
Vm  
measured voltage  
volts, output high  
volts, output low  
volts, root mean square  
VOH  
VOL  
Vrms  
W
waveform  
WFTRIG  
working voltage  
multiple voltage readings taken at a specific sampling rate  
waveform generation trigger signal  
the highest voltage that should be applied to a product in normal use,  
normally well under the breakdown voltage for safety margin.  
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Index  
specifications, A-1 to A-4  
accuracy information, A-2  
amplifier characteristics, A-3  
dynamic characteristics, A-3 to A-4  
input characteristics, A-1 to A-2  
stability, A-4  
Numbers  
+5 V signal  
description (table), 4-3  
self-resetting fuse, C-1  
transfer characteristics, A-2 to A-3  
types of signal sources, 4-7  
floating signal sources, 4-7  
ground-referenced signal sources, 4-7  
analog input modes  
A
ACH <0..15> signals  
analog input modes, 4-8  
analog input signal connections, 4-6  
description (table), 4-3  
available input configurations (table), 3-2  
common-mode signal rejection  
considerations, 4-16  
I/O signal summary (table), 4-5  
acquisition timing connections. See DAQ timing  
connections.  
differential connections, 4-10 to 4-13  
ground-referenced signal sources, 4-11  
nonreferenced or floating signal  
sources, 4-12 to 4-13  
exceeding common-mode input ranges  
(caution), 4-8  
overview, 3-2, 4-7 to 4-9  
PGIA, 4-7 to 4-8  
questions about, C-3  
ActiveX controls, 1-3  
AIGATE signal, 4-28  
AIGND signal  
analog input modes, 4-8  
analog input signal connections, 4-6  
description (table), 4-3  
differential connections, 4-13  
I/O signal summary (table), 4-5  
AISENSE signal  
recommended input configuration  
(figure), 4-9  
analog input modes, 4-8  
analog input signal connections, 4-6  
description (table), 4-3  
single-ended connection, 4-14 to 4-16  
floating signal sources, 4-15  
grounded signal sources, 4-15 to 4-16  
analog output  
I/O signal summary (table), 4-5  
analog input. See also analog input modes.  
input range  
glitch operation, 3-4  
overview, 3-4  
measurement precision (table), 3-3  
overview, 3-3  
questions about, C-3 to C-5  
scanning multiple channels, 3-3 to 3-4  
signal connections, 4-9 to 4-16  
signal overview, 4-6 to 4-9  
questions about, C-3 to C-5  
signal connections, 4-17  
specifications, A-4 to A-6  
accuracy information, A-5  
dynamic characteristics, A-6  
output characteristics, A-4  
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Index  
stability, A-6  
transfer characteristics, A-5  
voltage output, A-5 to A-6  
correlated digital I/O. See digital I/O.  
crosstalk, multiple channel scanning, C-4  
custom cabling, B-1  
AOGND signal  
analog output signal connections, 4-17  
D
description (table), 4-3  
DAC0OUT signal  
I/O signal summary (table), 4-5  
analog output signal connections, 4-17  
description (table), 4-3  
I/O signal summary (table), 4-5  
DAC1OUT signal  
B
base address configuration, C-2  
bipolar input range, 3-3  
block diagram, 3-1  
analog output signal connections, 4-17  
description (table), 4-3  
I/O signal summary (table), 4-5  
DAQ timing connections, 4-21 to 4-30  
AIGATE signal, 4-28  
C
C API, using with NI-DAQ, C-2  
cables. See also I/O connectors.  
custom cabling, B-1  
CONVERT* signal, 4-27 to 4-28  
EXTSTROBE* signal, 4-30  
SCANCLK signal, 4-29 to 4-30  
SISOURCE signal, 4-29  
STARTSCAN signal, 4-25 to 4-26  
TRIG1 signal, 4-22 to 4-23  
TRIG2 signal, 4-23 to 4-24  
typical posttriggered acquisition  
(figure), 4-21  
field wiring considerations, 4-40 to 4-41  
optional equipment, 1-4  
using with I/O connectors (table), 4-1  
calibration, 5-1 to 5-3  
external calibration, 5-2  
loading calibration constants, 5-1 to 5-2  
self-calibration, 5-2  
typical pretriggered acquisition  
(figure), 4-22  
specifications, A-8  
charge injection, 3-4, C-4  
commonly asked questions. See questions and  
answers.  
DAQ-STC system timing controller, 1-1, C-1  
DGND signal  
description (table), 4-3  
common-mode signal rejection  
considerations, 4-16  
I/O signal summary (table), 4-5  
DIFF mode  
configuration  
description (table), 3-2  
description, 2-2 to 2-3  
questions about, C-2  
recommended input configuration  
(figure), 4-9  
connectors. See I/O connectors.  
conventions used in manual, xi-xii  
CONVERT* signal  
differential connections, 4-10 to 4-13  
ground-referenced signal sources, 4-11  
nonreferenced or floating signal sources,  
4-12 to 4-13  
DAQ timing connections, 4-27 to 4-28  
questions about, C-5  
questions about, C-3  
signal routing (figure), 3-5  
when to use, 4-10  
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Index  
digital I/O  
overview, 3-4 to 3-5  
I/O signal summary (table), 4-6  
frequently asked questions. See questions and  
answers.  
questions about, C-6 to C-7  
signal connections, 4-18 to 4-19  
specifications, A-6 to A-7  
digital trigger specifications, A-8  
DIO<0..7> signal  
fuse, self-resetting, C-1  
G
gain error, adjusting, 5-3  
description (table), 4-3  
general-purpose timing signal connections,  
4-34 to 4-40  
digital I/O signal connections, 4-18  
I/O signal summary (table), 4-6  
documentation  
FREQ_OUT signal, 4-40  
GPCTR0_GATE signal, 4-35  
GPCTR0_OUT signal, 4-35 to 4-36  
GPCTR0_SOURCE signal, 4-34  
GPCTR0_UP_DOWN signal, 4-36  
GPCTR1_GATE signal, 4-37 to 4-38  
GPCTR1_OUT signal, 4-38  
GPCTR1_SOURCE signal, 4-36 to 4-37  
GPCTR1_UP_DOWN signal,  
4-38 to 4-40  
about this manual, xi  
conventions used in manual, xi-xii  
related documentation, xii  
E
EEPROM storage of calibration constants, 5-1  
electromagnetic compatibility  
specifications, A-9  
questions about, C-6  
glitches  
environment specifications, A-9  
environmental noise, 4-40 to 4-41  
equipment, optional, 1-4  
analog output, 3-4  
waveform generation glitches, C-3  
GPCTR0_GATE signal, 4-35  
GPCTR0_OUT signal  
EXTSTROBE* signal  
DAQ timing connections, 4-30  
description (table), 4-3  
description (table), 4-5  
I/O signal summary (table), 4-6  
general-purpose timing signal  
connections, 4-35 to 4-36  
F
I/O signal summary (table), 4-6  
GPCTR0_SOURCE signal, 4-34  
GPCTR0_UP_DOWN signal, 4-36  
GPCTR1_GATE signal, 4-37 to 4-38  
GPCTR1_OUT signal  
field wiring considerations, 4-40 to 4-41  
floating signal sources  
description, 4-7  
differential connections, 4-12 to 4-13  
single-ended connections, 4-15  
FREQ_OUT signal  
description (table), 4-4  
general-purpose timing signal  
connections, 4-38  
description (table), 4-5  
I/O signal summary (table), 4-6  
GPCTR1_SOURCE signal, 4-36 to 4-37  
GPCTR1_UP_DOWN signal, 4-38 to 4-40  
general-purpose timing signal  
connections, 4-40  
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Index  
ground-referenced signal sources  
description, 4-7  
exceeding maximum ratings  
(caution), 4-1  
optional connectors, B-1 to B-3  
50-pin connector pin assignments  
(figure), B-3  
differential connections, 4-11  
single-ended connections (NRSE  
configuration), 4-15 to 4-16  
68-pin connector pin assignments  
(figure), B-2  
pin assignments (figure), 4-2  
signal descriptions (table), 4-3 to 4-5  
signal summary (table), 4-5 to 4-6  
H
hardware installation  
procedure, 2-1 to 2-2  
unpacking 6013/6014 device, 1-4  
hardware overview  
L
analog input, 3-2 to 3-4  
input mode, 3-2  
scanning multiple channels,  
3-3 to 3-4  
analog output, 3-4  
LabVIEW Data Acquisition VI Library, 1-3  
LabVIEW software  
correspondence of signal names in  
LabVIEW and NI-DAQ (table), C-7  
overview, 1-3  
block diagram, 3-1  
LabWindows/CVI software, 1-3  
digital I/O, 3-4 to 3-5  
timing signal routing, 3-5 to 3-6  
programmable function inputs, 3-6  
M
manual. See documentation.  
maximum working voltage specifications, A-9  
Measurement Studio software, 1-3  
multiple channel scanning  
I
input mode. See analog input modes.  
input range  
description, 3-3 to 3-4  
questions about, C-4  
exceeding common-mode input ranges  
(caution), 4-8  
measurement precision (table), 3-3  
overview, 3-3  
installation  
N
NI 6013/6014 device. See also hardware  
overview.  
categories of installation, 1-6 to 1-7  
procedure, 2-1 to 2-2  
questions about, C-2  
block diagram, 3-1  
configuration, 2-2 to 2-3  
optional equipment, 1-4  
overview, 1-1  
questions about, C-1 to C-7  
requirements for getting started, 1-1 to 1-2  
safety information, 1-5 to 1-7  
software programming choices, 1-2 to 1-4  
software installation, 2-1  
unpacking 6013/6014 device, 1-4  
I/O connectors, 4-1 to 4-6  
(table), 4-1  
correspondence of signal names in  
LabVIEW and NI-DAQ (table), C-7  
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National Instruments ADE software,  
1-3 to 1-4  
PFI5/UPDATE signal  
description (table), 4-4  
NI-DAQ driver software, 1-2 to 1-3  
unpacking, 1-4  
I/O signal summary (table), 4-6  
PFI6/WFTRIG signal  
NI-DAQ driver software  
description (table), 4-4  
correspondence of signal names in  
LabVIEW and NI-DAQ (table), C-7  
overview, 1-2 to 1-3  
I/O signal summary (table), 4-6  
PFI7/STARTSCAN signal  
description (table), 4-4  
questions about, C-2  
I/O signal summary (table), 4-6  
PFI8/GPCTR0_SOURCE signal  
description (table), 4-5  
I/O signal summary (table), 4-6  
PFI9/GPCTR0_GATE signal  
description (table), 4-5  
I/O signal summary (table), 4-6  
PFIs (programmable function inputs)  
questions about, C-6 to C-7  
signal routing, 3-6  
noise, environmental, 4-40 to 4-41  
NRSE (nonreferenced single-ended) mode  
description (table), 3-2  
differential connections, 4-12 to 4-13  
recommended input configuration  
(figure), 4-9  
single-ended connections for  
ground-referenced signal sources,  
4-15 to 4-16  
timing connections, 4-20 to 4-21  
PGIA (programmable gain instrumentation  
amplifier)  
O
optional equipment, 1-4  
analog input modes, 4-7 to 4-8  
differential connections  
ground-referenced signal sources  
(figure), 4-11  
nonreferenced or floating signal  
sources, 4-12 to 4-13  
P
PCI Local Bus Specification Revision 2.3, 2-2  
PFI0/TRIG1 signal  
description (table), 4-4  
overview, 4-11  
I/O signal summary (table), 4-6  
PFI1/TRIG2 signal  
single-ended connections  
floating signal sources (figure), 4-15  
ground-referenced signal sources  
(figure), 4-16  
description (table), 4-4  
I/O signal summary (table), 4-6  
PFI2/CONVERT* signal  
physical specifications, A-8  
pin assignments. See I/O connectors.  
posttriggered data acquisition  
overview, 4-21  
typical acquisition (figure), 4-21  
power connections, 4-19  
description (table), 4-4  
I/O signal summary (table), 4-6  
PFI3/GPCTR1_SOURCE signal  
description (table), 4-4  
I/O signal summary (table), 4-6  
PFI4/GPCTR1_GATE signal  
description (table), 4-4  
power requirement specifications, A-8  
power-on states of PFI and DIO lines, C-7  
I/O signal summary (table), 4-6  
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Index  
pretriggered acquisition  
differential connection  
considerations, 4-10 to 4-13  
input configurations, 4-9 to 4-16  
single-ended connection  
considerations, 4-14 to 4-16  
summary of input configurations  
(figure), 4-9  
overview, 4-22  
typical acquisition (figure), 4-22  
professional services and technical  
support, D-1  
programmable function inputs (PFIs). See  
PFIs (programmable function inputs).  
programmable gain instrumentation amplifier.  
See PGIA (programmable gain  
instrumentation amplifier).  
types of signal sources, 4-7  
analog output, 4-17  
digital I/O, 4-18 to 4-19  
field wiring considerations, 4-40 to 4-41  
I/O connectors, 4-1 to 4-6  
cables for use with I/O connectors  
(table), 4-1  
Q
questions and answers, C-1 to C-7  
analog input and output, C-3 to C-5  
general information, C-1 to C-2  
installation and configuration, C-2  
timing and digital I/O, C-6 to C-7  
correspondence of signal names in  
LabVIEW and NI-DAQ  
(table), C-7  
exceeding maximum ratings  
(caution), 4-1  
I/O connector signal descriptions  
(table), 4-3 to 4-5  
I/O signal summary (table),  
4-5 to 4-6  
R
requirements for getting started, 1-1 to 1-2  
pin assignments (figure), 4-2  
I/O connectors, optional, B-1 to B-3  
50-pin connector pin assignments  
(figure), B-3  
S
safety information, 1-5 to 1-7  
safety specifications, A-9  
sampling rate, C-1  
68-pin connector pin assignments  
(figure), B-2  
SCANCLK signal  
power connections, 4-19  
timing connections, 4-19 to 4-40  
DAQ timing connections,  
4-21 to 4-30  
DAQ timing connections, 4-29 to 4-30  
description (table), 4-3  
I/O signal summary (table), 4-6  
scanning multiple channels  
description, 3-3 to 3-4  
questions about, C-4  
settling time, in multiple channel scanning,  
3-3 to 3-4  
general-purpose timing signal  
connections, 4-34 to 4-40  
programmable function input  
connections, 4-20 to 4-21  
waveform generation timing  
connections, 4-31 to 4-34  
signal connections  
common-mode signal rejection  
considerations, 4-16  
signal sources  
floating signal sources, 4-7  
ground-referenced signal sources, 4-7  
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single-ended connections, 4-14 to 4-16  
grounded signal sources (NRSE  
configuration), 4-15 to 4-16  
when to use, 4-14  
SISOURCE signal, 4-29  
software installation, 2-1  
software programming choices, 1-2 to 1-4  
National Instruments ADE software,  
1-3 to 1-4  
T
technical support and professional  
services, D-1  
timing connections, 4-19 to 4-40  
DAQ timing connections, 4-21 to 4-30  
AIGATE signal, 4-28  
CONVERT* signal, 4-27 to 4-28  
EXTSTROBE* signal, 4-30  
SCANCLK signal, 4-29 to 4-30  
SISOURCE signal, 4-29  
STARTSCAN signal, 4-25 to 4-26  
TRIG1 signal, 4-22 to 4-23  
TRIG2 signal, 4-23 to 4-24  
typical posttriggered acquisition  
(figure), 4-21  
NI-DAQ driver software, 1-2 to 1-3  
specifications  
analog input, A-1 to A-4  
accuracy information, A-2  
amplifier characteristics, A-3  
dynamic characteristics, A-3 to A-4  
input characteristics, A-1 to A-2  
stability, A-4  
typical pretriggered acquisition  
(figure), 4-22  
transfer characteristics, A-2 to A-3  
analog output, A-4 to A-6  
accuracy information, A-5  
dynamic characteristics, A-6  
output characteristics, A-4  
stability, A-6  
transfer characteristics, A-5  
voltage output, A-5 to A-6  
calibration, A-8  
digital I/O, A-6 to A-7  
electromagnetic compatibility, A-9  
environment, A-9  
maximum working voltage, A-9  
physical, A-8  
general-purpose timing signal  
connections, 4-34 to 4-40  
FREQ_OUT signal, 4-40  
GPCTR0_GATE signal, 4-35  
GPCTR0_OUT signal, 4-35 to 4-36  
GPCTR0_SOURCE signal, 4-34  
GPCTR0_UP_DOWN signal, 4-36  
GPCTR1_GATE signal, 4-37 to 4-38  
GPCTR1_OUT signal, 4-38  
GPCTR1_SOURCE signal,  
4-36 to 4-37  
GPCTR1_UP_DOWN signal,  
4-38 to 4-40  
overview, 4-19 to 4-20  
power requirement, A-8  
safety, A-9  
timing I/O, A-7  
programmable function input  
connections, 4-20 to 4-21  
timing I/O connections (figure), 4-20  
waveform generation timing connections,  
4-31 to 4-34  
triggers, A-8  
digital trigger, A-8  
UISOURCE signal, 4-33 to 4-34  
UPDATE* signal, 4-32 to 4-33  
WFTRIG signal, 4-31 to 4-32  
STARTSCAN signal  
DAQ timing connections, 4-25 to 4-26  
questions about, C-5  
© National Instruments Corporation  
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Index  
timing I/O  
V
questions about, C-6 to C-7  
VCC signal (table), 4-5  
voltage  
specifications, A-7  
timing signal routing, 3-5 to 3-6  
CONVERT* signal routing (figure), 3-5  
programmable function inputs, 3-6  
TRIG1 signal, 4-22 to 4-23  
TRIG2 signal, 4-23 to 4-24  
triggers  
maximum working voltage  
specifications, A-9  
output specifications, A-5 to A-6  
W
digital trigger specifications, A-8  
questions about, C-6  
waveform generation timing connections,  
4-31 to 4-34  
UISOURCE signal, 4-33 to 4-34  
UPDATE* signal, 4-32 to 4-33  
WFTRIG signal, 4-31 to 4-32  
WFTRIG signal, 4-31 to 4-32  
U
UISOURCE signal, 4-33 to 4-34  
unpacking 6013/6014 device, 1-4  
UPDATE* signal, 4-32 to 4-33  
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