Intel Switch D15343 003 User Manual

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Intel 82854 Graphics Memory  
Controller Hub (GMCH)  
Datasheet  
Revision 2.0  
June 2005  
Order Number: D15343-003  
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Contents  
Contents  
1.0 Introduction....................................................................................................................................11  
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2.0 Intel 82854 GMCH Overview.......................................................................................................21  
2.1.1 Intel 82854 GMCH...............................................................................................21  
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3.0 Signal Description..........................................................................................................................27  
4.0 Register Description ......................................................................................................................41  
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Intel 82854 Graphics Memory Controller Hub (GMCH)  
4.9  
Intel 854 GMCH Main Memory Control, Memory I/O Control Registers (Device #0, Function  
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4.11 Intel 82854 GMCH Integrated Graphics Device Registers (Device #2, Function #0).....100  
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5.0 Intel 82854 GMCH System Address Map..................................................................................111  
6.0 Functional Description.................................................................................................................123  
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Intel 82854 Graphics Memory Controller Hub (GMCH)  
7.0 Power and Thermal Management ...............................................................................................147  
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8.0 Intel 82854 GMCH Strap Pins...................................................................................................151  
9.0 Ballout and Package Information.................................................................................................153  
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Figures  
Intel 82854 GMCH Graphics Block Diagram (Native Graphic Mode only) .............................126  
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12 Intel 82854 GMCH Ballout Diagram (Top View).....................................................................153  
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13 Intel 82854 GMCH Micro-FCBGA Package Dimensions (Top View) .....................................164  
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14 Intel 82854 GMCH Micro-FCBGA Package Dimensions (Side View) ....................................165  
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15 Intel 82854 GMCH Micro-FCBGA Package Dimensions (Bottom View) ................................166  
Tables  
Intel 82854 GMCH Interface Clocks.........................................................................................25  
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24 Intel 82854 GMCH Configurations and Some Resolution Examples: Native Graphics Mode.99  
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Revision History  
Date  
Revision  
Description  
Initial release of this document.  
March 2005  
1.0  
2.0  
Add support for Genuine Intel® Processor at 1.2 GHz and  
Genuine Intel® Processor at 1.5 GHz technology.  
June 2005  
§ §  
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Introduction  
1.0  
Introduction  
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This document is the datasheet for the Intel 82854 Graphics Memory Controller Hub (GMCH).  
1.1  
Overview  
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The Intel 854 chipset is a combination of the Intel 82854 Graphics Memory Controller Hub  
(GMCH) (Graphics Memory Controller Hub) and ICH4-M (I/O Controller Hub). The Intel 854  
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Chipset is designed to work with the Ultra Low Voltage (ULV) Intel Celeron M processor at 600  
MHz with 512 KB of on-die L2 cache on an 0.13 micron process, Genuine Intel Processor at 1.2  
GHz, and Genuine Intel Processor at 1.5 GHz. The Intel 82854 GMCH provides high-  
performance, integrated graphics and manages the flow of information. Figure 1 depicts the Intel  
854 chipset block diagram.  
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Processor/Host Bus Support  
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The Genuine Intel Processor at 1.2 GHz and Genuine Intel Processor at 1.5 GHz have the  
following key features:  
High performance, low power core  
AGTL+ bus driver technology with integrated AGTL+ termination resistors and low voltage  
operation  
Supports Intel Architecture with Dynamic Execution  
400-MHz, Source-Synchronous processor system bus  
2x address, 4x data  
On-die, primary 32-Kbyte instruction cache and 32-Kbyte write-back data cache  
On-die, 512-Kbyte second level cache with Advanced Transfer Cache Architecture  
Advanced Branch Prediction and Data Prefetch Logic  
Streaming SIMD Extensions 2 (SSE2)  
Advanced Power Management features  
Memory System  
Directly supports one DDR SDRAM channel, 64-bits wide  
Supports 266/333-MHz DDR SDRAM devices with max of two, double-sided DIMM (four  
rows populated) with unbuffered PC2100/PC2700 DDR SDRAM.  
Supports 128-Mbit, 256-Mbit, and 512-Mbit technologies providing maximum capacity of  
2 GB with x16 devices  
All supported devices have four banks  
Supports up to 16 simultaneous open pages  
Supports page sizes of 2 kB, 4 kB, 8 kB, and 16 kB. Page size is individually selected for  
every row  
UMA support only  
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Intel 82854 Graphics Memory Controller Hub (GMCH)  
System Interrupts  
Supports Intel 8259 and front side bus interrupt delivery mechanism  
Supports interrupts signaled as upstream memory writes from PCI and Hub interface  
MSI sent to the CPU through the system bus  
IOxAPIC in ICH4-M provides redirection for upstream interrupts to the system bus  
Video Stream Decoder  
Hardware motion compensation for MPEG2  
All video format decoder (18 ATSC video formats) supported  
Dynamic Bob and Weave support for video streams  
Software DVD at 60 Fields/second and 30 frames/second full screen  
Support for standard definition DVD (i.e., NTSC pixel resolution of 720x480, and so on)  
quality encoding at low CPU utilization  
Video Overlay  
Single high quality scalable overlay and second Sprite to support second overlay  
Multiple overlay functionality provided via arithmetic stretch BLT (Block Transfer)  
5-tap horizontal, 3-tap vertical filtered scaling  
Multiple overlay formats  
Direct YUV from overlay to TV-out  
Independent gamma correction  
Independent brightness / contrast/ saturation  
Independent tint/hue support  
Destination colorkeying  
Source chromakeying  
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Introduction  
Display  
Analog display support  
— 350-MHz integrated 24-bit RAMDAC that can drive a standard progressive scan analog  
monitor with pixel resolution up to 1600x1200 at 85 Hz and up to 2048x1536 at 75 Hz  
Dual independent pipe support  
— Concurrent: different images and display timings on each display device  
— Simultaneous: same images and display timings on each display device  
DVO (DVOB and DVOC) support  
— Digital video out ports DVOB and DVOC with 165-MHz dot clock on each 12-bit  
interface; two 12-bit channels can be combined to form one dual channel 24-bit interface  
with an effective dot clock of 330 MHz  
— The combined DVO B/C ports as well as individual DVO B/C ports can drive a variety of  
DVO devices (TV-Out Encoders, TMDS and LVDS transmitters, and so on) with pixel  
resolution up to 1600x1200 at 85 Hz and up to 2048x1536 at 72 Hz.  
— Compliant with DVI Specification 1.0  
Tri-view support through DVO B, C port, and CRT  
Internal Graphics Features  
Up to 64 MB of dynamic video memory allocation  
Display image rotation  
Graphics core frequency at 200, 250 MHz  
2D graphics engine  
— Optimized 128-bit BLT engine  
— Ten programmable and predefined monochrome patterns  
— Alpha Stretch BLT (via 3D pipeline)  
— Anti-aliased lines  
— Hardware-based BLT Clipping and Scissoring  
— 32-bit Alpha Blended cursor  
— Programmable 64 x 64 3-color Transparent cursor  
— Color Space Conversion  
— Three Operand Raster BLTs  
— 8-bit, 16-bit, and 32-bit color  
— ROP support  
— DIB translation and Linear/Tile addressing  
— Multiple hardware color cursor support (32-bit with alpha and legacy 2-bpp mode)  
2
— Accompanying I C and DDC channels provided through multiplexed interface  
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Intel 82854 Graphics Memory Controller Hub (GMCH)  
3D graphics engine  
— 3D setup and render engine  
— Enhanced Hardware Binning Instruction Set supported  
— Zone rendering  
— High quality performance texture engine  
— Viewpoint transform and perspective divide  
— Triangle lists, strips and fans support  
— Indexed vertex and flexible vertex formats  
— Pixel accurate fast scissoring and clipping operation  
— Backface culling support  
— Direct 3D support  
— Anti-Aliased lines support  
— Sprite points support  
— Provides the highest sustained fill rate performance in 32-bit color and 24-bit W mode  
— High quality performance texture engine  
— 266-MegaTexel/s peak performance  
— Per pixel perspective corrected texture mapping  
— Single pass texture compositing (multi-textures)  
— Enhanced texture blending functions  
— Twelve level of detail MIP map sizes from 1x1 to 2k x 2k  
— Numerous texture formats  
— Alpha and Luminance maps  
— Texture chromakeying  
— Bilinear, trilinear, and anisotropic MIP map filtering  
— Cubic environment reflection mapping  
— Dot product bump-mapping  
— Embossed bump-mapping  
— DXTn texture decompression  
— FX1 texture compression  
— 3D graphics rasterization enhancements  
— One Pixel per clock  
— Flat and Gouraud shading  
— Color alpha blending for transparency  
Vertex and programmable pixel fog and atmospheric effects  
— Color specular lighting  
— Z Bias support  
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— Dithering  
— Line and full-scene anti-aliasing  
— 16- and 24-bit Z buffering  
— 16- and 24-bit W buffering  
— 8-bit Stencil buffering  
— Double and triple render buffer support  
— 16- and 32-bit color  
— Destination alpha  
Vertex cache  
— Optimal 3D resolution supported  
— Fast Clear support  
— ROP support  
Hub Interface to ICH4-M  
266-MB/s point-to-point Hub interface to ICH4-M  
66-MHz base clock  
Graphic Power Management  
Dynamic Frequency Switching  
Memory Self-Refresh during C3  
Intel Display Power Saving Technology  
Power Management  
SMRAM space remapping to A0000h (128-kB)  
Supports extended SMRAM space above 256-MB, additional 1-MB TSEG from top of  
memory, cacheable (cacheability controlled by CPU)  
APM Rev 1.2 compliant power management  
Supports Suspend to System Memory (S3), Suspend to Disk (S4) and Soft Off (S5)  
ACPI 1.0b, 2.0 support  
Optimized Clock Gating for 3D and Display Engines  
On-Die Thermal Sensor  
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Intel 82854 Graphics Memory Controller Hub (GMCH)  
Package  
732-pin Micro-FCBGA (37.5 x 37.5 mm)  
Figure 1.  
Intel® 854 Chipset system block diagram (Native Graphic mode)  
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Intel Celeron M  
Processor  
VGA  
400 MHz  
512 MB DDR  
Memory Down  
VGA  
DVO  
Intel® 82854  
333 MHz  
(GMCH)  
TV  
ADD Slot  
IDE  
USB 2.0/1.1  
LCI  
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Intel 82801DBM  
AC Link  
Audio  
Codec  
(ICH4-M)  
6 USB  
LAN  
PHY  
LPC  
FWH  
PS/2  
PCI Slots  
SIO  
Serial  
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Introduction  
1.2  
Terminology  
Table 1.  
Terms and Descriptions  
Term  
Description  
AGTL+  
BLI  
Advanced Gunning Transceiver Logic + (AGTL+) bus  
Backlight Inverter  
Core  
CPU  
CRT  
DBI  
The internal base logic in the Intel® 82854 GMCH  
Central Processing Unit  
Cathode Ray Tube  
Dynamic Bus inversion  
DBL  
Display Brightness Link  
DDC  
DPMS  
DVI*  
Display Data Channel (standard created by VESA)  
Display Power Management Signaling (standard created by VESA)  
Digital Visual Interface is the interface specified by the DDWG (Digital Display  
Working Group) DVI Spec. Rev. 1.0 utilizing only the Silicon Image developed  
TMDS protocol  
DVMT  
DVO  
EDID  
EIST  
FSB  
Dynamic Video Memory Technology  
Digital Video Out  
Extended Display Identification Data  
Enhanced Intel® SpeedStep® Technology  
Front side bus. Connection between Intel® 82854 GMCH and the CPU. Also  
known as the Host interface  
Full Reset  
GMCH  
HD  
A full Intel® 82854 GMCH Reset is defined in this document when RSTIN# is  
asserted  
Refers to the GMCH component. Throughout this datasheet, the Intel® 82854  
Graphics Memory Controller Hub (GMCH) will be referred to as the GMCH.  
High definition, typically MP@HL for MPEG2; Resolution supported are 720p,  
1080i and 1080p  
Host  
This term is used synonymously with processor  
Hub Interface (HI)  
The proprietary interconnect between the Intel® 82854 GMCH and the ICH4-M  
component. In this document, the Hub interface cycles originating from or  
destined for the ICH4-M are generally referred to as “Hub interface cycles.” Hub  
cycles originating from or destined for the primary PCI interface on are  
sometimes referred to as “Hub interface/PCI cycles”  
I2C  
Inter-IC (a two wire serial bus created by Philips)  
Integrated Graphics Device  
IGD  
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Intel 82854 Graphics Memory Controller Hub (GMCH)  
Intel 82801DBM ICH4-M  
The component contains the primary PCI interface, LPC interface, USB 2.0,  
ATA-100, AC’97, and other I/O functions. It communicates with the Intel® 82854  
GMCH over a proprietary interconnect called the Hub interface. Throughout this  
datasheet, the Intel 82801DBM ICH4-M component will be referred to as the  
ICH4-M  
IPI  
Inter Processor Interrupt  
Liquid Crystal Display  
LCD  
MSI  
Message Signaled Interrupts. MSI allow a device to request interrupt service via  
a standard memory write transaction instead of through a hardware signal  
Native Graphic Mode  
The Intel® 82854 GMCH can support RGB and Dual Independent Display in this  
mode  
PWM  
SD  
Pulse Width Modulation  
Standard definition, typically MP@ML for MPEG2  
Spread Spectrum Clocking  
Set Top Box  
SSC  
STB  
System Bus  
Processor-to-Intel® 82854 GMCH interface. The Enhanced mode of the  
Scalable bus is the P6 Bus plus enhancements, consisting of source  
synchronous transfers for address and data, and system bus interrupt delivery.  
The Intel Celeron M processor implements a subset of Enhanced mode.  
UMA  
VDL  
Unified Memory Architecture with graphics memory for the IGD inside system  
memory  
Video Data Link  
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Introduction  
1.3  
Reference Documents  
Table 2.  
Reference Documents  
Document  
Location  
Intel® Celeron® M Processor Datasheet  
http://www.intel.com/design/mobile/datashts/300302.htm  
Ultra Low Voltage Intel(R) Celeron(R) M  
Processor at 600 MHz Addendum to the  
Intel(R) Celeron(R) M Processor Datasheet  
http://developer.intel.com/design/intarch/datashts/  
301753.htm  
Intel® 854 Chipset Platform Design Guide  
for Use with Ultra Low Voltage Intel®  
Celeron® M Processor at 600 MHz  
Please contact your local Intel representative for this  
document.  
PCI Local Bus Specification 2.2  
Intel® 82801DBM I/O Controller Hub 4  
Mobile (ICH4-M) Datasheet  
http://developer.intel.com/design/mobile/datashts/  
Advanced Configuration and Power  
Management (ACPI) Specification 1.0b &  
2.0  
IA-32 Intel® Architecture Software  
Developer Manual Volume 3: System  
Programming Guide  
http://developer.intel.com/design/pentium4/manuals/  
INTEL® DIGITAL VIDEO OUT (DVO) PORT  
HARDWARE EXTERNAL DESIGN  
SPECIFICATION (EDS) VER – 2.X  
Please contact your local Intel representative for this  
document.  
ARIB TR-B15 Operational Guidelines for  
Digital Satellite Broadcasting (detailed  
Implementation guideline for receiver)  
http://www.atsc.org/standards.html  
ATSC Standards  
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Intel 82854 Graphics Memory Controller Hub (GMCH)  
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Intel 82854 GMCH Overview  
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2.0  
Intel 82854 GMCH Overview  
2.1  
System Architecture  
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The Intel 82854 GMCH includes a processor interface, DDR SDRAM interface, display  
interface, and Hub interface.  
Combined with the ULV Intel® Celeron® M Processor or Genuine Intel® Processor, and an ICH4-  
M, it provides many of the functions required to deliver the features below:  
Overall system software platform  
Graphic overlay function for the GUI and 3-D graphics for gaming.  
Soft CODEC function  
STB middleware execution  
New STB embedded applications requiring IA level of high performance.  
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2.1.1  
Intel 82854 GMCH  
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The Intel 82854 GMCH is in a 732-pin Micro-FCBGA package that contains the following  
functionality listed below:  
AGTL+ host bus supporting 32-bit host addressing with Enhanced Intel SpeedStep technology  
support  
Supports a single channel of DDR SDRAM memory  
System memory supports DDR 266/333 MHz (SSTL_2) DDR SDRAM  
Integrated graphics capabilities: Graphic Core frequency at 200, 250 MHz  
Supports three display ports: one progressive scan analog monitor and two DVO ports.  
Enhanced Power Management Graphics features  
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Intel 82854 Graphics Memory Controller Hub (GMCH)  
2.2  
Processor Host Interface  
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The Intel 82854 GMCH supports the Intel Celeron M Processor, and Genuine Intel Processor.  
Key features of the front side bus (FSB) are:  
Support for a 400-MHz system bus frequency.  
Source synchronous double pumped address (2X)  
Source synchronous quad pumped data (4X)  
Front side bus interrupt delivery  
Low voltage swing Vtt (1.05 ~ 1.55V)  
Dynamic Power Down (DPWR#) support  
Integrates AGTL+ termination resistors on all of the AGTL+ signals  
Supports 32-bit host bus addressing allowing the CPU to access the entire 4 GB of the GMCH  
memory address space.  
An 8-deep, In-Order queue  
Support DPWR# signal  
Supports one outstanding defer cycle at a time to any particular I/O interface  
2.3  
GMCH System Memory Interface  
The GMCH system memory controller directly supports the following:  
One channel of PC2100/2700 DIMM DDR SDRAM memory  
DDR SDRAM devices with densities of 128-Mb, 256-Mb, and 512-Mb technology  
Up to 1 GB (512-Mb technology) with two DDR DIMMs  
Up to 2 GB (512-Mb technology) using high density devices with two DDR DIMMs  
Table 3.  
DDR SDRAM Memory Capacity  
System Memory Capacity  
with Stacked Memory  
Technology  
Width  
System Memory Capacity  
128 Mb  
256 Mb  
512 Mb  
128 Mb  
256 Mb  
512 Mb  
16  
16  
16  
8
256 MB  
512 MB  
1 GB  
-
-
-
256 MB  
512 MB  
1 GB  
512 MB  
1 GB  
2 GB  
8
8
The GMCH system memory interface supports a thermal throttling scheme to selectively throttle  
reads and/or writes. Throttling can be triggered either by the on-die thermal sensor, or by preset  
write bandwidth limits. Read throttle can also be triggered by an external input pin. The memory  
controller logic supports aggressive Dynamic Row Power Down features to help reduce power and  
supports Address and Control line tri-stating when DDR SDRAM is in an active power down or in  
self refresh state.  
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Intel 82854 GMCH Overview  
The GMCH system memory architecture is optimized to maintain open pages (up to 16-KB page  
size) across multiple rows. As a result, up to 16 pages across four rows is supported. To  
complement this, the GMCH will tend to keep pages open within rows, or will only close a single  
bank on a page miss. The GMCH supports only four bank memory technologies.  
2.4  
Graphics Features  
The GMCH IGD provides a highly integrated graphics accelerator delivering high performance  
2D, 3D, and video capabilities. With its interfaces to UMA using a DVMT configuration, an analog  
display, and two digital display ports, the GMCH can provide a complete graphics solution.  
The GMCH also provides 2D hardware acceleration for block transfers of data (BLTs). The BLT  
engine provides the ability to copy a source block of data to a destination and perform raster  
operations (for example, ROP1, ROP2, and ROP3) on the data using a pattern, and/or another  
destination. Performing these common tasks in hardware reduces CPU load, and thus improves  
performance.  
High bandwidth access to data is provided through the system memory interface. The GMCH uses  
Tiling architecture to increase system memory efficiency and thus maximize effective rendering  
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bandwidth. The Intel 82854 GMCH improves 3D performance and quality with 3D Zone  
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rendering technology. The Intel 82854 GMCH also supports Video Mixer rendering, and Bi-  
Cubic filtering.  
2.5  
Display Features  
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The Intel 82854 GMCH has three display ports: one analog and two digital. With these interfaces,  
the GMCH can provide support for a progressive scan analog monitor and two DVO ports. The  
native graphic mode is able to deliver up to two streams of data via the two DVO ports.  
2.5.1  
GMCH Analog Display Port  
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The Intel 82854 GMCH has an integrated 350-MHz, 24-bit RAMDAC that can directly drive a  
progressive scan analog monitor pixel resolution up to 1600x1200 at 85-Hz refresh and up to  
2048x1536 at 75-Hz refresh. In the native graphic mode, the Analog display port can be driven by  
Pipe A or Pipe B.  
2.5.2  
GMCH Integrated DVO Ports  
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The Intel 82854 GMCH provides a digital display channel that is capable of driving a pixel clock  
up to 165 MHz.  
The GMCH supports three ARIB planes of graphics: Still Picture Plane, Text and Graphic Plane,  
and Superimpose Text Plane at a frame rate of 10 fps. A minimum of two displays are supported.  
The ARIB plane resolutions supported can be found in Figure 8.  
In native graphics mode, the GMCH supports a single display up to 60 fps real time with maximum  
resolution of 720 x 480 pixels.  
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Intel 82854 Graphics Memory Controller Hub (GMCH)  
2.6  
2.7  
Hub Interface  
A proprietary interconnect connects the GMCH to the ICH4-M. All communication between the  
GMCH and the ICH4-M occurs over the Hub interface 1.5. The Hub interface runs at 66 MHz  
(266-MB/s).  
Address Decode Policies  
Host initiated I/O cycles are positively decoded to the GMCH configuration space and  
subtractively decoded to the Hub interface. Host initiated system memory cycles are positively  
decoded to DDR SDRAM and are again subtractively decoded to the Hub interface, if less than  
4 GB. System memory accesses from the Hub interface to DDR SDRAM will be snooped on  
the FSB.  
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Intel 82854 GMCH Overview  
2.8  
GMCH Clocking  
The GMCH has the following clock input/output pins:  
400-MHz, spread spectrum, low voltage differential BCLK, BCLK# for front side bus (FSB)  
66-MHz, 3.3-V GCLKIN for Hub interface buffers  
Six pairs of differential output clocks (SCK[5:0], SCK[5:0]#), 200/266 MHz, 2.5 V for system  
memory interface  
48-MHz, non-Spread Spectrum, 3.3-V DREFCLK for the Display Frequency Synthesis  
8-MHz or 66-MHz, Spread Spectrum, 3.3-V DREFSSCLK for the Display Frequency  
Synthesis  
Up to 148.5 MHz, 1.5-V DVOBCCLKINT for TV-Out mode  
DPMS clock for S1-M  
Clock Synthesizer chips are responsible for generating the system host clocks, GMCH display  
clocks, Hub interface clocks, PCI clocks, SIO clocks, and FWH clocks. The host target speed is  
400 MHz. The GMCH does not require any relationship between the BCLK Host clock and the  
66-MHz clock generated for the Hub interface; they are asynchronous to each other. The Hub  
interface runs at a constant 66-MHz base frequency. Table 4 indicates the frequency ratios between  
the various interfaces that the GMCH supports.  
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Table 4.  
Intel 82854 GMCH Interface Clocks  
CPU System  
Bus Frequency  
Ratio  
Data Rate  
(Mega-  
samples/s)  
Data  
Width  
(Bytes)  
Peak  
Bandwidth  
(MB/s)  
Samples  
Per Clock  
Interface  
Clock Speed  
CPU Bus  
100 MHz  
133 MHz  
166 MHz  
Reference  
4
2
2
2
400  
266  
333  
330  
8
8
3200  
2128  
2664  
495  
DDR SDRAM  
1:1 Synchronous  
1:1 Synchronous  
Asynchronous  
8
DVO B or DVO C  
Up to 165  
MHz  
1.5  
(Native Graphic  
Mode)  
DVO B+DVO C  
Up to 330  
MHz  
Asynchronous  
Asynchronous  
2
1
660  
350  
3
3
1980  
1050  
(Native Graphic  
Mode)  
DAC Interface  
350 MHz  
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Intel 82854 Graphics Memory Controller Hub (GMCH)  
2.9  
System Interrupts  
The GMCH supports both the legacy Intel 8259 Programmable Interrupt delivery mechanism and  
the Intel Celeron M processor FSB interrupt delivery mechanism. The serial APIC Interrupt  
mechanism is not supported.  
The Intel 8259 Interrupt delivery mechanism support consists of flushing in bound Hub interface  
write buffers when an Interrupt Acknowledge cycle is forwarded from the system bus to the Hub  
interface.  
PCI MSI interrupts are generated as memory writes. The GMCH decodes upstream memory writes  
to the range 0FEE0_0000h - 0FEEF_FFFFh from the Hub interface as message based interrupts.  
The GMCH forwards the memory writes along with the associated write data to the system bus as  
an Interrupt Message transaction. Since this address does not decode as part of main system  
memory, the write cycle and the write data do not get forwarded to system memory via the write  
buffer. The GMCH provides the response and HTRDY# for all Interrupt Message cycles including  
the ones originating from the GMCH. The GMCH also supports interrupt redirection for upstream  
interrupt memory writes.  
For message based interrupts, system write buffer coherency is maintained by relying on strict  
ordering of memory writes. The GMCH ensures that all memory writes received from a given  
interface prior to an interrupt message memory write are delivered to the system bus for snooping  
in the same order that they occur on the given interface.  
26  
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Signal Description  
3.0  
Signal Description  
®
This section describes the Intel 82854 GMCH signals. These signals are arranged in functional  
groups according to their associated interface. The following notations are used to describe the  
signal type.  
Notation  
Description  
I
Input pin  
O
I/O  
Output pin  
Bi-directional Input/Output pin  
The signal description also includes the type of buffer used for the particular signal:  
Buffer  
Description  
AGTL+  
Open Drain AGTL+ interface signal. Refer to the AGTL+ I/O  
Specification for complete details. The GMCH integrates AGTL+  
termination resistors, and supports VTTLF of 1.05 V ± 5%. AGTL+  
signals are "inverted bus" style where a low voltage represents a  
logical 1.  
DVO  
DVO buffers (1.5-V tolerant)  
Hub  
Compatible to Hub interface 1.5  
SSTL_2  
LVTTL  
CMOS  
Analog  
Ref  
Stub Series Termination Logic compatible signals (2.5-V tolerant)  
Low Voltage TTL compatible signals (3.3-V tolerant)  
CMOS buffers (3.3-V tolerant)  
Analog signal interface  
Voltage reference signal  
Note: System Address and Data Bus signals are logically inverted signals. In other words, the actual  
values are inverted from what appears on the system bus. This must be taken into account and the  
addresses and data bus signals must be inverted inside the GMCH. All processor control signals  
follow normal convention: A 0 indicates an active level (low voltage), and a 1 indicates an active  
level (high voltage).  
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®
Intel 854 Graphics Memory Controller Hub (GMCH)  
3.1  
Host Interface Signals  
Table 5.  
Host Interface Signal Descriptions  
Signal Name  
ADS#  
Type  
I/O  
Description  
Address Strobe: The system bus owner asserts ADS# to indicate the  
first of two cycles of a request phase. The GMCH can assert this signal  
for snoop cycles and interrupt messages.  
AGTL+  
BNR#  
BPRI#  
I/O  
AGTL+  
Block Next Request: Used to block the current request bus owner from  
issuing a new request. This signal is used to dynamically control the CPU  
bus pipeline depth.  
O
Bus Priority Request: The GMCH is the only Priority Agent on the  
system bus. It asserts this signal to obtain the ownership of the address  
bus. This signal has priority over symmetric bus requests and will cause  
the current symmetric owner to stop issuing new transactions unless the  
HLOCK# signal was asserted.  
AGTL+  
BREQ0#  
I/O  
AGTL+  
Bus Request 0#: The GMCH pulls the processor bus BREQ0# signal  
low during CPURST#. The signal is sampled by the processor on the  
active-to-inactive transition of CPURST#. The minimum setup time for  
this signal is 4 BCLKs. The minimum hold time is 2 clocks and the  
maximum hold time is 20 BCLKs. BREQ0# should be tristated after the  
hold time requirement has been satisfied.  
During regular operation, the GMCH will use BREQ0# as an early  
indication for FSB Address and Ctl input buffer and sense amp activation.  
CPURST#  
O
CPU Reset: The CPURST# pin is an output from the GMCH. The  
GMCH asserts CPURST# while RESET# (PCIRST# from ICH4-M) is  
asserted and for approximately 1 ms after RESET# is deasserted. The  
CPURST# allows the processor to begin execution in a known state.  
AGTL+  
Note that the ICH4-M must provide CPU strap set-up and hold-times  
around CPURST#. This requires strict synchronization between GMCH,  
CPURST# deassertion and ICH4-M driving the straps.  
DBSY#  
I/O  
Data Bus Busy: Used by the data bus owner to hold the data bus for  
AGTL+  
transfers requiring more than one cycle.  
DEFER#  
O
Defer: GMCH will generate a deferred response as defined by the rules  
of the GMCH’s Dynamic Defer policy. The GMCH will also use the  
DEFER# signal to indicate a CPU retry response.  
AGTL+  
DINV[3:0]#  
I/O  
AGTL+  
Dynamic Bus Inversion: Driven along with the HD[63:0]# signals.  
Indicates if the associated signals are inverted or not. DINV[3:0]# are  
asserted such that the number of data bits driven electrically low (low  
voltage) within the corresponding 16-bit group never exceeds 8.  
DINV# Data Bits  
DINV[3]# HD[63:48]#  
DINV[2]# HD[47:32]#  
DINV[1]# HD[31:16]#  
DINV[0]# HD[16:0]#  
DPSLP#  
I
Deep Sleep #: This signal comes from the ICH4-M device, providing an  
indication of C3 and C4 state control to the CPU. Deassertion of this  
signal is used as an early indication for C3 and C4 wake up (to active  
HPLL). Note that this is a low-voltage CMOS buffer operating on the FSB  
VTT power plane.  
CMOS  
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Signal Description  
DRDY#  
I/O  
Data Ready: Asserted for each cycle that data is transferred.  
AGTL+  
HA[31:3]#  
I/O  
AGTL+  
Host Address Bus: HA[31:3]# connects to the CPU address bus. During  
processor cycles the HA[31:3]# are inputs. The GMCH drives HA[31:3]#  
during snoop cycles on behalf of Hub interface. HA[31:3]# are  
transferred at 2x rate. Note that the address is inverted on the CPU bus.  
HADSTB[1:0]#  
I/O  
AGTL+  
Host Address Strobe: HA[31:3]# connects to the CPU address bus.  
During CPU cycles, the source synchronous strobes are used to transfer  
HA[31:3]# and HREQ[4:0]# at the 2x transfer rate.  
Strobe  
Address Bits  
HADSTB[0]#  
HADSTB[1]#  
HA[16:3]#, HREQ[4:0]#  
HA[31:17]#  
HD[63:0]#  
I/O  
AGTL+  
Host Data: These signals are connected to the CPU data bus.  
HD[63:0]# are transferred at 4x rate. Note that the data signals are  
inverted on the CPU bus.  
HDSTBP[3:0]#  
HDSTBN[3:0]#  
I/O  
AGTL+  
Differential Host Data Strobes: The differential source synchronous  
strobes are used to transfer HD[63:0]# and DINV[3:0]# at the 4x  
transfer rate.  
Strobe  
Data Bits  
HDSTBP[3]#, HDSTBN[3]#  
HDSTBP[2]#, HDSTBN[2]#  
HDSTBP[1]#, HDSTBN[1]#  
HDSTBP[0]#, HDSTBN[0]#  
HD[63:48]#, DINV[3]#  
HD[47:32]#, DINV[2]#  
HD[31:16]#, DINV[1]#  
HD[15:0]#, DINV[0]#  
HIT#  
I/O  
AGTL+  
Hit: Indicates that a caching agent holds an unmodified version of the  
requested line. Also, driven in conjunction with HITM# by the target to  
extend the snoop window.  
HITM#  
I/O  
AGTL+  
Hit Modified: Indicates that a caching agent holds a modified version of  
the requested line and that this agent assumes responsibility for  
providing the line. Also, driven in conjunction with HIT# to extend the  
snoop window.  
HLOCK#  
I/O  
AGTL+  
Host Lock: All CPU bus cycles sampled with the assertion of HLOCK#  
and ADS#, until the negation of HLOCK# must be atomic; that is, no Hub  
interface snoopable access to system memory is allowed when HLOCK#  
is asserted by the CPU.  
HREQ[4:0]#  
I/O  
AGTL+  
Host Request Command: Defines the attributes of the request.  
HREQ[4:0]# are transferred at 2x rate. Asserted by the requesting agent  
during both halves of the Request Phase. In the first half the signals  
define the transaction type to a level of detail that is sufficient to begin a  
snoop request. In the second half the signals carry additional information  
to define the complete transaction type.  
The transactions supported by the GMCH Host Bridge are defined in the  
Host Interface section of this document.  
HTRDY#  
O
Host Target Ready: Indicates that the target of the processor  
AGTL+  
transaction is able to enter the data transfer phase.  
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Intel 854 Graphics Memory Controller Hub (GMCH)  
RS[2:0]#  
O
Response Status: Indicates the type of response according to the  
AGTL+  
following the table:  
RS[2:0]#  
000  
Response type  
Idle state  
001  
Retry response  
010  
Deferred response  
Reserved (not driven by GMCH)  
Hard Failure (not driven by GMCH)  
No data response  
011  
100  
101  
110  
Implicit Write back  
111  
Normal data response  
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Signal Description  
3.2  
DDR SDRAM Interface  
Table 6.  
DDR SDRAM Interface Descriptions  
Signal Name  
SCS[3:0]#  
Type  
Description  
O
Chip Select: These pins select the particular DDR SDRAM  
SSTL_2  
components during the active state.  
NOTE: There is one SCS# per DDR-SDRAM Physical DDR DIMM  
device row. These signals can be toggled on every rising System  
Memory Clock edge (SCMDCLK).  
SMA[12:0]  
SBA[1:0]  
O
Multiplexed Memory Address: These signals are used to provide the  
multiplexed row and column address to the DDR SDRAM.  
SSTL_2  
O
Bank Select (Memory Bank Address): These signals define which  
banks are selected within each DDR SDRAM row. The SMA and SBA  
signals combine to address every possible location within a DDR  
SDRAM device.  
SSTL_2  
SRAS#  
SCAS#  
SWE#  
O
DDR Row Address Strobe: SRAS# may be heavily loaded and  
requires tw0 DDR SDRAM clock cycles for setup time to the DDR  
SDRAMs. Used with SCAS# and SWE# (along with SCS#) to define the  
system memory commands.  
SSTL_2  
O
DDR Column Address Strobe: SCAS# may be heavily loaded and  
requires two clock cycles for setup time to the DDR SDRAMs. Used  
with SRAS# and SWE# (along with SCS#) to define the system memory  
commands.  
SSTL_2  
O
Write Enable: Used with SCAS# and SRAS# (along with SCS#) to  
define the DDR SDRAM commands. SWE# is asserted during writes to  
DDR SDRAM. SWE# may be heavily loaded and requires two clock  
cycles for setup time to the DDR SDRAMs.  
SSTL_2  
SDQ[63:0]  
SDQS[8:0]  
I/O  
SSTL_2  
Data Lines: These signals are used to interface to the DDR SDRAM  
data bus.  
I/O  
SSTL_2  
Data Strobes: Data strobes are used for capturing data. During writes,  
SDQS is centered on data. During reads, SDQS is edge aligned with  
data. The following list matches the data strobe with the data bytes.  
There is an associated data strobe (DQS) for each data signal (DQ) and  
check bit (CB) group.  
SDQS[7] -> SDQ[63:56]  
SDQS[6] -> SDQ[55:48]  
SDQS[5] -> SDQ[47:40]  
SDQS[4] -> SDQ[39:32]  
SDQS[3] -> SDQ[31:24]  
SDQS[2] -> SDQ[23:16]  
SDQS[1] -> SDQ[15:8]  
SDQS[0] -> SDQ[7:0]  
SCKE[3:0]  
O
Clock Enable: These pins are used to signal a self-refresh or power  
down command to the DDR SDRAM array when entering system  
suspend. SCKE is also used to dynamically power down inactive DDR  
SDRAM rows. There is one SCKE per DDR SDRAM row. These  
signals can be toggled on every rising SCK edge.  
SSTL_2  
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Intel 854 Graphics Memory Controller Hub (GMCH)  
SMAB[5,4,2,1]  
SDM[8:0]  
O
Memory Address Copies: These signals are identical to SMA[5,4,2,1]  
and are used to reduce loading for selective CPC(clock-per-command).  
These copies are not inverted.  
SSTL_2  
O
Data Mask: When activated during writes, the corresponding data  
groups in the DDR SDRAM are masked. There is one SDM for every  
eight data lines. SDM can be sampled on both edges of the data  
strobes.  
SSTL_2  
RCVENOUT#  
RCVENIN#  
O
Clock Output: Reserved, NC.  
SSTL_2  
O
Clock Input: Reserved, NC.  
SSTL_2  
3.3  
Hub Interface Signals  
Table 7.  
Hub Interface Signals  
Signal Name  
Type  
Description  
HL[10:0]  
HLSTB  
I/O Hub  
I/O Hub  
Packet Data: Data signals used for HI read and write operations.  
Packet Strobe: One of two differential strobe signals used to transmit or  
receive packet data over HI.  
HLSTB#  
I/O Hub  
Packet Strobe Complement: One of two differential strobe signals used  
to transmit or receive packet data over HI.  
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Signal Description  
3.4  
Clocks  
Table 8.  
Clock Signals  
Signal Name  
Type  
Description  
Host Processor Clocking  
BCLK  
I
Differential Host Clock In: These pins receive a buffered host clock  
from the external clock synthesizer. This clock is used by all of the  
GMCH logic that are in the Host clock domain (Host, Hub and system  
memory). The clock is also the reference clock for the graphics core  
PLL. This is a low voltage differential input.  
BCLK#  
CMOS  
System Memory Clocking  
SCK[5:0]  
O
Differential DDR SDRAM Clock: SCK and SCK# pairs are differential  
clock outputs. The crossing of the positive edge of SCK and the  
negative edge of SCK# is used to sample the address and control  
signals on the DDR SDRAM. There are 3 pairs to each DDR DIMM.  
SSTL_2  
SCK[5:0]#  
O
Complementary Differential DDR SDRAM Clock: These are the  
complimentary differential DDR SDRAM clock signals.  
SSTL_2  
DVO/Hub Input Clocking  
GCLKIN  
I
Input Clock: 66-MHz, 3.3-V input clock from external buffer DVO/Hub  
interface.  
CMOS  
DVO Clocking  
DVOBCLK  
O
Differential DVO Clock Output: These pins provide a differential pair  
DVOBCLK#  
reference clock that can run up to 165-MHz.  
DVO  
DVOBCLK corresponds to the primary clock out.  
DVOBCLK# corresponds to the primary complementary clock out.  
DVOBCLK and DVOBCLK# should be left as NC (“Not Connected”) if  
the DVO B port is not implemented.  
DVOCCLK  
O
Differential DVO Clock Output: These pins provide a differential pair  
DVOCCLK#  
reference clock that can run up to 165-MHz.  
DVO  
DVOCCLK corresponds to the primary clock out.  
DVOCCLK# corresponds to the primary complementary clock out.  
DVOCCLK and DVOCCLK# should be left as NC (“Not Connected”) if  
the DVO C port is not implemented.  
DVOBCCLKINT  
I
DVOBC Pixel Clock Input/Interrupt: This signal may be selected as  
the reference input to either dot clock PLL (DPLL) or may be  
configured as an interrupt input. A TV-out device can provide the clock  
reference. The maximum input frequency for this signal is 148.5 -MHz.  
DVO  
DVOBC Pixel Clock Input: When selected as the dot clock PLL (DPLL)  
reference input, this clock reference input supports SSC clocking for  
DVO LVDS devices.  
DVOBC Interrupt: When configured as an interrupt input, this interrupt  
can support either DVOB or DVOC.  
DVOBCCLKINT needs to be pulled down if the signal is NOT used.  
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Intel 854 Graphics Memory Controller Hub (GMCH)  
DPMS  
I
Display Power Management Signaling: This signal is used only in  
mobile systems to act as the DREFCLK in certain power management  
states (i.e., Display Power Down Mode); DPMS Clock is used to  
refresh video during S1-M. Clock Chip is powered down in S1-M.  
DPMS should come from a clock source that runs during S1-M and  
needs to be 1.5 V. So, an example would be to use a 1.5-V version of  
SUSCLK from ICH4-M.  
DVO  
DAC Clocking  
DREFCLK  
I
Display Clock Input: This pin is used to provide a 48-MHz input clock  
to the Display PLL that is used for 2D/Video and DAC.  
LVTTL  
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Signal Description  
3.5  
Internal Graphics Display Signals  
The IGD has support for DVOB/C interfaces, and an Analog CRT port.Digital Video Output B  
(DVOB) Port.  
3.5.1  
Digital Video Output B (DVOB) Port  
Table 9.  
Digital Video Output B (DVOB) Port Signal Descriptions  
Name  
Type  
Description  
DVOBD[11:0]  
O
DVOB Data: This data bus is used to drive 12-bit RGB data on each edge  
of the differential clock signals, DVOBCLK and DVOBCLK#. This provides  
24-bits of data per clock period. In dual channel mode, this provides the  
lower 12-bits of pixel data.  
DVO  
DVOBD[11:0] should be left as NC (“Not Connected”) if not used.  
DVOBHSYNC  
DVOBVSYNC  
O
Horizontal Sync: HSYNC signal for the DVOB interface.  
DVO  
DVOBHSYNC should be left as left as NC (“Not Connected”) if not used.  
O
Vertical Sync: VSYNC signal for the DVOB interface.  
DVO  
DVOBVSYNC should be left as left as NC (“Not Connected”) if the signal  
is NOT used when using internal graphics device.  
DVOBBLANK#  
DVOBFLDSTL  
O
Flicker Blank or Border Period Indication: DVOBBLANK# is a  
programmable output pin driven by the GMCH.  
DVO  
When programmed as a blank period indication, this pin indicates active  
pixels excluding the border. When programmed as a border period  
indication, this pin indicates active pixel including the border pixels.  
DVOBBLANK# should be left as left as NC (“Not Connected”) if not used.  
I
TV Field and Flat Panel Stall Signal. This input can be programmed to  
be either a TV Field input from the TV encoder or Stall input from the flat  
panel.  
DVO  
DVOB TV Field Signal: When used as a Field input, it synchronizes the  
overlay field with the TV encoder field when the overlay is displaying an  
interleaved source.  
DVOB Flat Panel Stall Signal: When used as the Stall input, it indicates  
that the pixel pipeline should stall one horizontal line. The signal changes  
during horizontal blanking. The panel fitting logic, when expanding the  
image vertically, uses this.  
DVOBFLDSTL needs to be pulled down if not used.  
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®
Intel 854 Graphics Memory Controller Hub (GMCH)  
3.5.2  
Digital Video Output C (DVOC) Port  
Table 10.  
Digital Video Output C (DVOC) Port Signal Descriptions  
Name  
Type  
Description  
DVOCD[11:0]  
O
[Native Graphic Mode]  
DVO  
DVOC Data: This data bus is used to drive 12-bit RGB data on each edge  
of the differential clock signals, DVOCCLK and DVOCCLK#. This  
provides 24-bits of data per clock period. In dual channel mode, this  
provides the upper 12-bits of pixel data.  
DVOCD[11:0] should be left as left as NC (“Not Connected”) if not used.  
DVOCHSYNC  
DVOCVSYNC  
O
Horizontal Sync: HSYNC signal for the DVOC interface.  
DVO  
DVOCHSYNC should be left as left as NC (“Not Connected”) if not used.  
O
Vertical Sync: VSYNC signal for the DVOC interface.  
DVO  
DVOCVSYNC should be left as left as NC (“Not Connected”) if the signal  
is NOT used when using internal graphics device.  
DVOCBLANK#  
DVOCFLDSTL  
O
Flicker Blank or Border Period Indication: DVOCBLANK# is a  
programmable output pin driven by the GMCH.  
DVO  
When programmed as a blank period indication, this pin indicates active  
pixels excluding the border. When programmed as a border period  
indication, this pin indicates active pixel including the border pixels.  
DVOCBLANK# should be left as left as NC (“Not Connected”) if not used.  
I
TV Field and Flat Panel Stall Signal. This input can be programmed to  
be either a TV Field input from the TV encoder or Stall input from the flat  
panel.  
DVO  
DVOC TV Field Signal: When used as a Field input, it synchronizes the  
overlay field with the TV encoder field when the overlay is displaying an  
interleaved source.  
DVOC Flat Panel Stall Signal: When used as the Stall input, it indicates  
that the pixel pipeline should stall one horizontal line. The signal changes  
during horizontal blanking. The panel fitting logic, when expanding the  
image vertically, uses this.  
DVOCFLDSTL needs to be pulled down if not used.  
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Signal Description  
Table 11.  
DVOB and DVOC Port Common Signal Descriptions  
Name  
Type  
Description  
DVOBCINTR#  
I
DVOBC Interrupt: This pin is used to signal an interrupt, typically used to  
indicate a hot plug or unplug of a digital display.  
DVO  
ADDID[7:0]  
I
ADDID[7:0]: These pins are used to communicate to the Video BIOS  
when an external device is interfaced to the DVO port.  
DVO  
Note: Bit[7] needs to be strapped low when an on-board DVO device is  
present. The other pins should be left as NC.  
ADDID[0] = 0, Reserve  
ADDID[0] = 1, the Intel® 82854 GMCH is strapped to operate under  
Native Graphic Mode  
For detail of strapping option, please refer to Table 33.  
DVODETECT  
I
DVODETECT: This strapping signal indicates to the GMCH whether a  
DVO device is present or not. When a DVO device is connected, then  
DVODETECT = 0.  
DVO  
3.5.3  
Analog CRT Display  
Table 12.  
Analog CRT Display Signal Descriptions  
Pin Name  
VSYNC  
Type  
Description  
O
CRT Vertical Synchronization: This signal is used as the vertical sync signal.  
CMOS  
HSYNC  
RED  
O
CRT Horizontal Synchronization: This signal is used as the horizontal sync  
signal.  
CMOS  
O
Red (Analog Video Output): This signal is a CRT Analog video output from  
the internal color palette DAC. The DAC is designed for a 37.5-equivalent  
load on each pin (that is, a 75-resistor on the board, in parallel with the 75-Ω  
CRT load).  
Analog  
RED#  
O
Red# (Analog Output): Tied to ground.  
Analog  
GREEN  
O
Green (Analog Video Output): This signal is a CRT analog video output from  
the internal color palette DAC. The DAC is designed for a 37.5-equivalent  
load on each pin (that is, a 75-resistor on the board, in parallel with the 75- Ω  
CRT load).  
Analog  
GREEN#  
O
Green# (Analog Output): Tied to ground.  
Analog  
Blue (Analog Video Output) : This signal is a CRT Analog video output from  
the internal color palette DAC. The DAC is designed for a 37.5-equivalent  
load on each pin (that is, a 75-ohm resistor on the board, in parallel with the 75-  
CRT load).  
O
BLUE  
Analog  
O
Blue# (Analog Output): Tied to ground.  
BLUE#  
Analog  
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Intel 854 Graphics Memory Controller Hub (GMCH)  
3.5.4  
General Purpose Input/Output Signals  
Table 13.  
GPIO Signal Descriptions  
GPIO I/F Total  
RSTIN#  
Type  
Comments  
I
Reset: Primary Reset, Connected to PCIRST# of ICH4-M.  
CMOS  
PWROK  
I
Power OK: Indicates that power to GMCH is stable.  
CMOS  
EXTTS_0  
I
External Thermal Sensor Input: This signal is an active low input to the  
GMCH and is used to monitor the thermal condition around the system memory  
and is used for triggering a read throttle. The GMCH can be optionally  
programmed to send a SERR, SCI, or SMI message to the ICH4-M upon the  
triggering of this signal.  
CMOS  
LCLKCTLA  
LCLKCTLB  
O
SSC Chip Clock Control: Can be used to control an external clock chip with  
SSC control.  
CMOS  
O
SSC Chip Data Control: Can be used to control an external clock chip for  
SSC control.  
CMOS  
I/O  
DDCACLK  
CRT DDC Clock: This signal is used as the DDC clock signal between the  
CRT monitor and the GMCH.  
CMOS  
I/O  
DDCADATA  
CRT DDC Data: This signal is used as the DDC data signal between the CRT  
monitor and the GMCH.  
CMOS  
MI2CCLK  
I/O  
DVO I2C Clock: This signal is used as the I2C_CLK for a digital display (i.e.  
TV-Out Encoder, TMDS transmitter). This signal is tri-stated during a hard  
reset.  
DVO  
MI2CDATA  
MDVICLK  
MDVIDATA  
MDDCDATA  
MDDCCLK  
I/O  
DVO I2C Data: This signal is used as the I2C_DATA for a digital display (i.e.  
TV-Out Encoder, TMDS transmitter). This signal is tri-stated during a hard  
reset.  
DVO  
I/O  
DVI DDC Clock: This signal is used as the DDC clock for a digital display  
connector (that is, primary digital monitor). This signal is tri-stated during a hard  
reset.  
DVO  
I/O  
DVI DDC Data: The signal is used as the DDC data for a digital display  
connector (that is, the primary digital monitor). This signal is tri-stated during a  
hard reset.  
DVO  
I/O  
DVI DDC Clock: The signal is used as the DDC data for a digital display  
connector (that is, the secondary digital monitor). This signal is tri-stated during  
a hard reset.  
DVO  
I/O  
DVI DDC Data: The signal is used as the DDC clock for a digital display  
connector (that is, the secondary digital monitor). This signal is tri-stated during  
a hard reset.  
DVO  
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Signal Description  
3.6  
Voltage References, PLL Power  
Table 14.  
Voltage References, PLL Power  
Signal Name  
Type  
Description  
Host Processor  
HXRCOMP  
HYRCOMP  
HXSWING  
Analog  
Host RCOMP: Used to calibrate the Host AGTL+ I/O buffers.  
Host RCOMP: Used to calibrate the Host AGTL+ I/O buffers.  
Analog  
Analog  
Host Voltage Swing (RCOMP reference voltage): This signal provides  
a reference voltage used by the FSB RCOMP circuit.  
HYSWING  
Analog  
Host Voltage Swing (RCOMP reference voltage): This signal provides  
a reference voltage used by the FSB RCOMP circuit.  
HDVREF[2:0]  
Ref  
Analog  
Host Data (input buffer) VREF: Reference voltage input for the data  
signals of the Host AGTL+ Interface. Input buffer differential amplifier to  
determine a high versus low input voltage.  
HAVREF  
Ref  
Analog  
Host Address (input buffer) VREF: Reference voltage input for the  
address signals of the Host AGTL+ Interface. This signal is connected to  
the input buffer differential amplifier to determine a high versus low input  
voltage.  
HCCVREF  
Ref Analog  
Host Common Clock (Command input buffer) VREF: Reference  
voltage input for the common clock signals of the Host AGTL+ Interface.  
This signal is connected to the input buffer differential amplifier to  
determine a high versus low input voltage.  
VTTLF  
VTTHF  
Power  
Power  
FSB Power Supply: VTTLF is the low frequency connection from the  
board. This signal is the primary connection of power for GMCH.  
FSB Power Supply: VTTHF is the high frequency supply. It is for direct  
connection from an internal package plane to a capacitor placed  
immediately adjacent to the GMCH.  
NOTE: Not to be connected to power rail.  
System Memory  
SMRCOMP  
Analog  
System Memory RCOMP: This signal is used to calibrate the memory I/  
O buffers.  
SMVREF_0  
Ref  
Memory Reference Voltage(Input buffer VREF):Reference voltage  
Analog  
input for Memory Interface.  
Input buffer differential amplifier to determine a high versus low input  
voltage.  
SMVSWINGH  
SMVSWINGL  
Ref  
Analog  
RCOMP reference voltage: This is connected to the RCOMP buffer  
differential amplifier and is used to calibrate the I/O buffers.  
Ref  
RCOMP reference voltage: This is connected to the RCOMP buffer  
Analog  
differential amplifier and is used to calibrate the I/O buffers.  
VCCSM  
Power  
Power  
Power  
Power supply for Memory I/O.  
VCCQSM  
VCCASM  
Power supply for system memory clock buffers.  
Power supply for system memory logic running at the core voltage  
(isolated supply, not connected to the core).  
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Intel 854 Graphics Memory Controller Hub (GMCH)  
Hub Interface  
HLRCOMP  
PSWING  
HLVREF  
Analog  
Analog  
Hub Interface RCOMP: This signal is connected to a reference resistor  
in order to calibrate the buffers.  
RCOMP reference voltage: This is connected to the RCOMP buffer  
differential amplifier and is used to calibrate the buffers.  
Ref  
Input buffer VREF: Input buffer differential amplifier to determine a high  
versus low input voltage.  
Analog  
VCCHL  
Power  
Power supply for Hub interface buffers  
DVO  
DVORCOMP  
Analog  
Analog  
Compensation for DVO: This signal is used to calibrate the DVO I/O  
buffers.  
GVREF  
Ref Analog  
Power  
Input buffer VREF: Input buffer differential amplifier to determine a high  
versus low input voltage.  
VCCDVO  
GPIO  
Power supply for DVO.  
VCCGPIO  
DAC  
Power  
Power supply for GPIO buffers  
REFSET  
Ref  
Resistor Set: Set point resistor for the internal color palette DAC.  
Analog  
VCCADAC  
VSSADAC  
IGD  
Power  
Power  
Power supply for the DAC  
Ground supply for the DAC  
VCC1_5  
VCC2_5  
VCCA  
Power  
Power  
Power  
Power  
Digital power supply.  
Digital power supply  
Analog power supply.  
Ground supply  
VSSA  
Clocks  
VCCAHPLL  
VCCAGPLL  
VCCADPLLA  
VCCADPLLB  
Core  
Power  
Power  
Power  
Power  
Power supply for the Host PLL.  
Power supply for the Hub/DVO PLL.  
Power supply for the display PLL A.  
Power supply for the display PLL B.  
VCC  
Power  
Power  
Power supply for the core.  
Ground supply for the chip.  
VSS  
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Register Description  
4.0  
Register Description  
4.1  
Conceptual Overview of the Platform Configuration  
Structure  
The GMCH and ICH4-M are physically connected by a Hub interface. From a configuration  
standpoint, the Hub interface is logically PCI bus #0. As a result, all devices internal to the GMCH  
and ICH4-M appear to be on PCI bus #0. The system's primary PCI expansion bus is physically  
attached to the ICH4-M and from a configuration perspective, appears to be a hierarchical PCI bus  
behind a PCI-to-PCI bridge and therefore has a programmable PCI Bus number. Note that the  
primary PCI bus is referred to as PCI_A in this document and is not PCI bus #0 from a  
configuration standpoint. For the GMCH, the graphics subsystem appears to system software to be  
a real PCI bus behind PCI-to-PCI bridges, resident as devices on PCI bus #0.  
The GMCH contains two PCI devices within a single physical component. The configuration  
registers for the two devices are mapped as devices residing on PCI bus #0.  
Device #0: Host-Hub Interface Bridge/DDR SDRAM Controller. Logically this appears as a PCI  
device residing on PCI bus #0. Physically, Device #0 contains the standard PCI registers, DDR  
SDRAM registers, the Graphics Aperture Controller registers, HI Control registers and other  
GMCH specific registers. Device #0 is divided into the following functions:  
Function #0: Host Bridge Legacy registers including Graphics Aperture Control registers, HI  
Configuration registers and Interrupt Control registers  
Function #1: DDR SDRAM Interface Registers  
Function #3: Intel Configuration Process Registers  
Device #2: Integrated Graphics Controller. Logically this appears as a PCI device residing on PCI  
bus #0. Physically Device #2 contains the Configuration registers for 2D, 3D, and display  
functions.  
®
Note: The legacy VGA registers are only supported when the Intel 82854 GMCH is strapped into  
Native Graphics Mode.  
Table 15 shows the Device # assignment for the various internal GMCH devices.  
Table 15.  
Device Number Assignment  
GMCH Function  
Bus #0, Device#  
Host-Hub interface, DDR SDRAM I/F, Legacy control  
Integrated Graphics Controller (IGD)  
Device #0  
Device #2  
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Intel 82854 Graphics Memory Controller Hub (GMCH)  
4.2  
Nomenclature for Access Attributes  
Table 16 provides the nomenclature for the access attributes.  
Table 16.  
Nomenclature for Access Attributes  
RO  
Read Only. If a register is Read Only, Writes to this register have no effect.  
R/W  
Read/Write. A register with this attribute can be Read and Written.  
R/W/L  
R/WC  
Read/Write/Lock. A register with this attribute can be Read, Written, and Locked.  
Read/Write Clear. A register bit with this attribute can be Read and Written.  
However, a Write of a 1 clears (sets to 0) the corresponding bit and a Write of a 0  
has no effect.  
R/WO  
Read/Write Once. A register bit with this attribute can be Written to only once  
after power up. After the first Write, this bit becomes Read Only.  
L
Lock. A register bit with this attribute becomes Read Only after a Lock bit is set.  
Reserved Bits  
Some of the GMCH registers described in this section contain Reserved bits.  
These bits are labeled "Reserved”. Software must deal correctly with fields that are  
Reserved. On Reads, software must use appropriate masks to extract the defined  
bits and not rely on Reserved bits being of any particular value. On Writes,  
software must ensure that the values of Reserved bit positions are preserved. That  
is, the values of Reserved bit positions must first be Read, Merged with the new  
values for other bit positions and then Written back. Note the software does not  
need to perform Read, Merge, and Write operations for the Configuration Address  
register.  
Reserved Registers  
In addition to Reserved bits within a register, the GMCH contains address locations  
in the configuration space of the Host-Hub Interface Bridge entity that are marked  
either "Reserved" or “Intel Reserved”. The GMCH responds to accesses to  
“Reserved” address locations by completing the Host cycle. When a “Reserved”  
register location is Read, in certain cases, a zero value can be returned  
(“Reserved” registers can be 8-bit, 16-bit, or 32-bit in size) or a non-zero value can  
be returned. In certain cases, Writes to “Reserved” registers may have no effect on  
the GMCH or may cause system failure. Registers that are marked as “Intel  
Reserved” must not be modified by system software.  
Default Value upon a  
Reset  
Upon Reset, the GMCH sets all of its internal configuration registers to  
predetermined default states. Some register values at Reset are determined by  
external strapping options. The default state represents the minimum functionality  
feature set required to successfully bring up the system. Hence, it does not  
represent the optimal system configuration. It is the responsibility of the system  
initialization software (usually BIOS) to properly determine the DDR SDRAM  
configurations, operating parameters and optional system features that are  
applicable, and to program the GMCH registers accordingly.  
S
SW Semaphore.  
A physical PCI Bus #0 does not exist. The Hub interface and the internal devices in the GMCH and  
ICH4-M logically constitute PCI Bus #0 to configuration software.  
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Register Description  
4.3  
Standard PCI Bus Configuration Mechanism  
The PCI Bus defines a slot based “configuration space” that allows each device to contain up to  
eight functions with each function containing up to 256, 8-bit configuration registers. The PCI  
Specification defines two bus cycles to access the PCI Configuration Space: Configuration Read  
and Configuration Write. Memory and I/O spaces are supported directly by the CPU.  
Configuration Space is supported by a mapping mechanism implemented within the GMCH. The  
PCI 2.2 specification defines two mechanisms to access Configuration Space: Mechanism #1 and  
Mechanism #2. The GMCH supports only Mechanism #1.  
The Configuration Access Mechanism makes use of the CONFIG_ADDRESS register (at I/O  
address 0CF8h though 0CFBh) and CONFIG_DATA register (at I/O address 0CFCh though  
0CFFh). To reference a Configuration register a Dword I/O Write cycle is used to place a value  
into CONFIG_ADDRESS that specifies the PCI Bus, the device on that bus, the function within  
the device, and a specific Configuration register of the device function being accessed.  
CONFIG_ADDRESS[31] must be a 1 to enable a Configuration cycle. CONFIG_DATA then  
becomes a window into the four Bytes of Configuration Space specified by the contents of  
CONFIG_ADDRESS. Any Read or Write to CONFIG_DATA will result in the GMCH translating  
the CONFIG_ADDRESS into the appropriate Configuration cycle.  
The GMCH is responsible for translating and routing the CPU’s I/O accesses to the  
CONFIG_ADDRESS and CONFIG_DATA registers to internal GMCH Configuration registers  
and to the Hub interface.  
4.4  
Routing Configuration Accesses  
The GMCH supports one bus interface: the Hub interface. PCI Configuration cycles are selectively  
routed to this interface. The GMCH is responsible for routing PCI Configuration cycles to the  
proper interface. PCI configuration cycles to the ICH4-M internal devices, and Primary PCI  
(including downstream devices) are routed to theICH4-M via the Hub interface.  
4.4.1  
PCI Bus #0 Configuration Mechanism  
The GMCH decodes the Bus Number (bits 23:16) and the Device Number fields of the  
CONFIG_ADDRESS register. If the Bus Number field of CONFIG_ADDRESS is 0, then the  
Configuration cycle is targeting a PCI Bus #0 device.  
The Host-Hub Interface Bridge entity within the GMCH is hardwired as Device #0 on PCI Bus #0.  
Configuration cycles to any of the GMCH’s internal devices are confined to the GMCH and not  
sent over Hub interface. Accesses to disabled GMCH internal devices will be forwarded over the  
Hub interface as Type 0 Configuration cycles.  
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Intel 82854 Graphics Memory Controller Hub (GMCH)  
4.4.2  
Primary PCI and Downstream Configuration Mechanism  
If the Bus Number in the CONFIG_ADDRESS is non-zero, the GMCH will generate a Type 1 Hub  
interface Configuration Cycle. A[1:0] of the Hub interface request packet for the Type 1  
configuration cycle will be “01”. This Hub interface configuration cycle will be sent over Hub  
interface.  
If the cycle is forwarded to the ICH4-M via Hub interface, the ICH4-M compares the non-zero Bus  
Number with the Secondary bus number and Subordinate bus number registers of its PCI-to-PCI  
bridges to determine if the configuration cycle is meant for Primary PCI, one of the ICH4-M’s Hub  
interfaces, or a downstream PCI bus.  
4.5  
Register Definitions  
The GMCH contains four sets of software accessible registers accessed via the Host CPU I/O  
Address Space, and they are as follows:  
Control registers: I/O Mapped into the CPU I/O Space, which control access to PCI  
Configuration Space via Configuration Mechanism #1 in the PCI 2.2 specification.  
Internal Configuration registers: residing within the GMCH, they are partitioned into two  
logical device register sets (“logical” since they reside within the single physical device). The  
first register set is dedicated to Host-HI Bridge functionality (that is, DDR SDRAM  
configuration, other chip-set operating parameters and optional features). The second register  
block is for the integrated graphics functions.  
Internal Memory Mapped Configuration registers: reside in the GMCH Device #0.  
Internal Memory Mapped Configuration registers, Legacy VGA registers, or blending  
function registers: reside in the GMCH Device #2 that controls the Integrated Graphics  
Controller.  
The GMCH internal registers (I/O Mapped and Configuration registers) are accessible by the Host  
CPU. The registers can be accessed as Byte, Word (16-bit), or Dword (32-bit) quantities, with the  
exception of CONFIG_ADDRESS, which can only be accessed as a Dword. All multi-byte  
numeric fields use “Little Endian Byte Ordering” (that is, lower addresses contain the least  
significant parts of the field).  
Reserved Bits  
Some of the GMCH registers described in this section contain Reserved bits. These bits are labeled  
“Reserved”. Software must deal correctly with fields that are Reserved. On Reads, software must  
use appropriate Masks to extract the defined bits and not rely on Reserved bits being any particular  
value. On Writes, software must ensure that the values of Reserved bit positions are preserved.  
That is, the values of Reserved bit positions must first be Read, Merged with the new values for  
other bit positions and then Written back.  
Note: The software does not need to perform Read, Merge, and Write operations for the Configuration  
Address register.  
Default Value upon Reset  
Upon a Full Reset, the GMCH sets all of its Internal Configuration registers to a predetermined  
default state. Some register values at Reset are determined by external strapping options. The  
default state represents the minimum functionality feature set required to successfully bring up the  
system. Hence, it does not represent the optimal system configuration. It is the responsibility of the  
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Register Description  
system initialization software (usually BIOS) to properly determine the DDR SDRAM  
configurations, operating parameters, and optional system features that are applicable and to  
program the GMCH registers accordingly.  
4.6  
I/O Mapped Registers  
The GMCH contains two registers that reside in the CPU I/O Address Space: the Configuration  
Address (CONFIG_ADDRESS) Register and the Configuration Data (CONFIG_DATA) Register.  
The Configuration Address Register enables/disables the Configuration Space and determines  
what portion of Configuration Space is visible through the Configuration Data window.  
4.6.1  
CONFIG_ADDRESS – Configuration Address Register  
I/O Address:  
Default Value:  
Access:  
0CF8h Accessed as a Dword  
00000000h  
Read/Write  
Size:  
32 bits  
CONFIG_ADDRESS is a 32-bit register that can be accessed only as a Dword. A Byte or Word  
reference will “pass through” the Configuration Address Register and the Hub interface, onto the  
PCI bus as an I/O cycle. The CONFIG_ADDRESS register contains the Bus Number, Device  
Number, Function Number, and Register Number for which a subsequent configuration access is  
intended.  
Figure 2.  
Configuration Address Register  
Bit  
Default  
31 30 24 23 16 15 11 10  
8 7  
2 1 0  
R
R
0
0
0
0
0
Reserved  
Register Number  
Function Number  
Device Number  
Bus Number  
Reserved  
Enable  
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Intel 82854 Graphics Memory Controller Hub (GMCH)  
Bit  
Descriptions  
31  
Configuration Enable (CFGE): When this bit is set to 1, accesses to PCI Configuration Space  
are enabled. If this bit is Reset to 0, accesses to PCI Configuration Space are disabled.  
30:24  
23:16  
Reserved  
Bus Number: When the Bus Number is programmed to 00h, the target of the Configuration  
Cycle is a Hub interface agent (GMCH, ICH4-M, and so on.).  
The Configuration Cycle is forwarded to Hub interface if the Bus Number is programmed to 00h  
and the GMCH is not the target (the device number is >= 2).  
15:11  
10:8  
Device Number: This field selects one agent on the PCI Bus selected by the Bus Number. When  
the Bus Number field is 00 the GMCH decodes the Device Number field. The GMCH is always  
Device Number 0 for the Host-Hub interface bridge entity. Therefore, when the Bus Number =0  
and the Device Number=0-1 the internal GMCH devices are selected.  
For Bus Numbers resulting in Hub interface Configuration cycles, the GMCH propagates the  
device number field as A[15:11].  
Function Number: This field is mapped to A[10:8] during Hub interface Configuration cycles.  
This allows the configuration registers of a particular function in a multi-function device to be  
accessed. The GMCH ignores Configuration cycles to its internal Devices if the function number is  
not equal to 0.  
7:2  
1:0  
Register Number: This field selects one register within a particular Bus, Device, and Function as  
specified by the other fields in the Configuration Address register. This field is mapped to A[7:2]  
during Hub interface Configuration cycles.  
Reserved  
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Register Description  
4.6.2  
CONFIG_DATA – Configuration Data Register  
I/O Address:  
Default Value:  
Access:  
0CFCh  
00000000h  
Read/Write  
32 bits  
Size:  
CONFIG_DATA is a 32-bit Read/Write window into Configuration Space. The portion of  
Configuration Space that is referenced by CONFIG_DATA is determined by the contents of  
CONFIG_ADDRESS.  
Figure 3.  
Configuration Data Register  
31  
0
Bit  
0
Default  
Configuration Data Window  
Bit  
31:0  
Descriptions  
Configuration Data Window (CDW). If bit 31 of CONFIG_ADDRESS is 1, then any I/O access  
to the CONFIG_DATA register will be mapped to Configuration Space using the contents of  
CONFIG_ADDRESS.  
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Intel 82854 Graphics Memory Controller Hub (GMCH)  
4.7  
VGA I/O Mapped Registers  
If Native Graphics mode is strapped, and Device #2 is enabled, and Function #0 within Device #2  
is enabled for VGA, and IO_EN is set within Function #0 then GMCH claims a set of I/O registers  
for legacy VGA function. Table 17 lists direct CPU Access registers and Table 18 lists registers  
that are Index – Data registers that are used to access Internal VGA registers.  
Table 17.  
VGA I/O Mapped Register List  
Name  
Function  
Read @  
Write @  
ST00  
ST01  
FCR  
MSR  
VGA Input Status Register 0  
3C2h  
3BAh/3Dah  
3CAh  
VGA Input Status Register 1  
VGA Feature Control Register  
VGA Miscellaneous Status/Output Register  
3BAh/3DAh  
3C2h  
3CCh  
Table 18.  
Index – Data Registers  
Name  
Function  
Index IO  
Data IO  
SRX  
GRX  
ARX  
Sequencer Registers  
3C4  
3CE  
3C0  
3C5  
3CF  
Graphics Controller Registers  
Attribute Control Registers  
3C0: Write  
3C1: Read  
DACMASK  
DACSTATE  
DACRX  
Pixel Data Mask Register  
DAC State Register  
--  
--  
3C6h  
3C7 Read Only  
--  
Palette Read Index Register  
Palette Write Index Register  
Palette Data Register  
CRT Registers  
3C7 Write Only  
3C8 Write Only  
3C9  
DACWX  
DACDATA  
CRX  
3B4/3D4  
3B5/3D5  
(MDA/CGA)  
(MDA/CGA)  
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Register Description  
4.8  
Intel 854 GMCH Host-Hub Interface Bridge Device Registers  
(Device #0, Function #0)  
Table 5 summarizes the configuration space for Device #0, Function#0.  
Table 19.  
GMCH Configuration Space - Device #0, Function#0  
Register  
Symbol  
Register  
Start  
Register  
End  
Register Name  
Default Value  
Access  
Vendor Identification  
Device Identification  
PCI Command  
VID  
DID  
00  
02  
04  
06  
08  
0A  
0B  
0E  
2C  
01  
03  
05  
07  
08  
0A  
0B  
0E  
2D  
8086h  
358Ch  
0006h  
0090h  
02h  
RO  
RO  
PCICMD  
PCISTS  
RID  
RO,R/W  
RO,R/WC  
RO  
PCI Status  
Revision Identification  
Sub-Class Code  
Base Class Code  
Header Type  
SUBC  
BCC  
00h  
RO  
06h  
RO  
HDR  
80h  
RO  
Subsystem Vendor  
Identification  
SVID  
0000h  
R/WO  
Subsystem Identification  
Capabilities Pointer  
SID  
CAPPTR  
CAPID  
GMC  
2E  
34  
40  
50  
52  
54  
58  
59  
60  
2F  
34  
44  
51  
53  
55  
58  
5F  
60  
0000h  
40h  
R/WO  
RO  
Capability Identification  
GMCH Misc. Control  
84_A105_0009h  
0000h  
RO  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W/L  
GMCH Graphics Control  
Device and Function Control  
Fixed Dram Hole Control  
Programmable Attribute Map  
GGC  
0030h  
DAFC  
0000h  
FDHC  
00h  
PAM (6:0)  
SMRAM  
00h Each  
02h  
System Management RAM  
Control  
Extended System  
ESMRAMC  
61  
61  
38h  
R/W/L  
Management RAM Control  
Error Status  
ERRSTS  
ERRCMD  
SMICMD  
SCICMD  
SHIC  
62  
64  
66  
67  
74  
63  
65  
66  
67  
77  
0000h  
0000h  
00h  
R/WC  
R/W  
Error Command  
SMI Command  
SCI Command  
R/W  
00h  
R/W  
Secondary Host Interface  
Control Register  
00006010h  
RO, R/W  
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Intel 82854 Graphics Memory Controller Hub (GMCH)  
Aperture Translation Table  
Base  
ATTBASE  
HEM  
B8  
F0  
BB  
F3  
00000000h  
00000000h  
RO, R/W  
RO, R/W  
Host Error Control/Status/  
Obs  
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Register Description  
4.8.1  
VID – Vendor Identification Register  
Address Offset:  
Default Value:  
Access:  
00-01h  
8086h  
Read only  
16 bits  
Size:  
The VID Register contains the vendor identification number. This 16-bit register, combined with  
the Device Identification Register, uniquely identifies any PCI device. Writes to this register have  
no effect.  
Bit  
Descriptions  
15:0  
Vendor Identification (VID): This register field contains the PCI standard identification for Intel.  
4.8.2  
DID – Device Identification Register  
Address Offset:  
Default Value:  
Access:  
02-03h  
358Ch  
Read only  
16 bits  
Size:  
This 16-bit register combined with the Vendor Identification register uniquely identifies any PCI  
device. Writes to this register have no effect.  
Bit  
Descriptions  
15:0  
Device Identification (DID): This is a 16-bit value assigned to the GMCH Host-Hub interface  
bridge, Device #0.  
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Intel 82854 Graphics Memory Controller Hub (GMCH)  
4.8.3  
PCICMD – PCI Command Register  
Address Offset:  
Default Value:  
Access:  
04-05h  
0006h  
Read only, Read/Write  
16 bits  
Size:  
Since GMCH Device #0 does not physically reside on PCI_A many of the bits are not  
implemented.  
Bit  
Descriptions  
Reserved  
15:10  
9
Fast Back-to-Back Enable (FB2B): This bit controls whether or not the master can do fast back-  
to-back Write. Since Device #0 is strictly a target, this bit is not implemented and is hardwired to  
0. Writes to this bit position have no affect.  
8
SERR Enable (SERRE): This bit is a global enable bit for Device #0 SERR messaging. The  
GMCH does not have an SERR# signal, but communicates the SERR# condition by sending an  
SERR message to the ICH4-M.  
1 = Enable. GMCH is enabled to generate SERR messages over Hub interface for specific  
Device #0 error conditions that are individually enabled in the ERRCMD register. The error status  
is reported in the ERRSTS and PCISTS registers.  
0 = SERR message is not generated by the GMCH for Device #0.  
NOTE: This bit only controls SERR messaging for the Device #0. Device #1 has its own SERRE  
bit to control error reporting for error conditions occurring on Device #1. The two control bits are  
used in a logical OR manner to enable the SERR Hub interface message mechanism.  
7
6
5
4
Address/Data Stepping Enable (ADSTEP): Address/data stepping is not implemented in the  
GMCH, and this bit is hardwired to 0. Writes to this bit position have no effect.  
Parity Error Enable (PERRE): PERR# is not implemented by GMCH and this bit is hardwired to  
0. Writes to this bit position have no effect.  
VGA Palette Snoop Enable (VGASNOOP): The GMCH does not implement this bit and it is  
hardwired to a 0. Writes to this bit position have no effect.  
Memory Write and Invalidate Enable (MWIE): The GMCH will never issue memory write and  
invalidate commands. This bit is therefore hardwired to 0. Writes to this bit position will have no  
effect.  
3
2
1
0
Special Cycle Enable (SCE): The GMCH does not implement this bit and it is hardwired to a 0.  
Writes to this bit position have no effect.  
Bus Master Enable (BME): The GMCH is always enabled as a master on HI. This bit is  
hardwired to a 1. Writes to this bit position have no effect.  
Memory Access Enable (MAE): The GMCH always allows access to main system memory. This  
bit is not implemented and is hardwired to 1. Writes to this bit position have no effect.  
I/O Access Enable (IOAE): This bit is not implemented in the GMCH and is hardwired to a 0.  
Writes to this bit position have no effect.  
52  
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Register Description  
4.8.4  
PCI Status Register  
Address Offset:  
Default Value:  
Access:  
06-07h  
0090h  
Read only, Read/WriteClear  
16 bits  
Size:  
PCISTS is a 16-bit status register that reports the occurrence of error events on Device #0's PCI  
Interface. Bit 14 is Read/Write Clear. All other bits are Read Only. Since GMCH Device #0 does  
not physically reside on PCI_A many of the bits are not implemented.  
Bit  
Descriptions  
15  
Detected Parity Error (DPE): The GMCH does not implement this bit and it is hardwired to a 0.  
Writes to this bit position have no effect.  
14  
Signaled System Error (SSE): R/WC. This bit is set to 1 when GMCH Device #0 generates an  
SERR message over HI for any enabled Device #0 error condition. Device #0 error conditions are  
enabled in the PCICMD and ERRCMD registers. Device #0 error flags are read/reset from the  
PCISTS or ERRSTS registers. Software sets SSE to 0 by writing a 1 to this bit.  
13  
12  
Received Master Abort Status (RMAS): R/WC. This bit is set when the GMCH generates a HI  
request that receives a Master Abort completion packet or Master Abort Special Cycle. Software  
clears this bit by writing a 1 to it.  
Received Target Abort Status (RTAS): R/WC. This bit is set when the GMCH generates a HI  
request that receives a Target Abort completion packet or Target Abort Special Cycle. Software  
clears this bit by writing a 1 to it. If bit 6 in the ERRCMD is set to a one and an Serr# special cycle  
is generated on the HI bus.  
11  
Signaled Target Abort Status (STAS): The GMCH will not generate a Target Abort HI  
completion packet or Special Cycle. This bit is not implemented in the GMCH and is hardwired to  
a 0. Writes to this bit position have no effect.  
10:9  
DEVSEL Timing (DEVT): These bits are hardwired to “00”. Writes to these bit positions have no  
affect. Device #0 does not physically connect to PCI_A. These bits are set to “00” (fast decode)  
so that the GMCH does not limit optimum DEVSEL timing for PCI_A.  
8
7
Master Data Parity Error Detected (DPD): PERR signaling and messaging are not implemented  
by the GMCH therefore this bit is hardwired to 0. Writes to this bit position have no effect.  
Fast Back-to-Back (FB2B): This bit is hardwired to 1. Writes to these bit positions have no  
effect. Device #0 does not physically connect to PCI_A. This bit is set to 1 (indicating fast back-to-  
back capability) so that the GMCH does not limit the optimum setting for PCI_A.  
6:5  
4
Reserved  
Capability List (CLIST): This bit is hardwired to 1 to indicate to the configuration software that  
this device/function implements a list of new capabilities. A list of new capabilities is accessed via  
register CAPPTR at configuration address offset 34h.  
3:0  
Reserved  
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®
Intel 82854 Graphics Memory Controller Hub (GMCH)  
4.8.5  
RID – Register Identification  
Address Offset:  
Default Value:  
Access:  
08h  
02h  
Read only  
8 bits  
Size:  
This register contains the revision number of the GMCH Device #0. These bits are read only and  
writes to this register have no effect.  
Bit  
Descriptions  
7:0  
Revision Identification Number (RID): This is an 8-bit value that indicates the revision  
identification number for the GMCH Device #0.  
4.8.6  
SUBC – Sub Class Code Register  
Address Offset:  
Default Value:  
Access:  
0Ah  
00h  
Read only  
8 bits  
Size:  
This register contains the Sub-Class Code for the GMCH Device #0. This code is 00h indicating a  
Host Bridge device.  
Bit  
Descriptions  
7:0  
Sub-Class Code (SUBC): This is an 8-bit value that indicates the category of Bridge into which  
the GMCH falls. The code is 00h indicating a Host Bridge.  
54  
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Register Description  
4.8.7  
BCC – Base Class Code Register  
Address Offset:  
Default Value:  
Access:  
0Bh  
06h  
Read only  
8 bits  
Size:  
This register contains the Base Class code of the GMCH Device #0. This code is 06h indicating a  
Bridge device.  
Bit  
Descriptions  
7:0  
Base Class Code (BASEC): This is an 8-bit value that indicates the Base Class Code for the  
GMCH. This code has the value 06h, indicating a Bridge device.  
4.8.8  
HDR – Header Type Register  
Address Offset:  
Default Value:  
Access:  
0Eh  
80h  
Read only  
8 bits  
Size:  
This register identifies the header layout of the configuration space. No physical register exists at  
this location.  
Bit  
Descriptions  
7:0  
PCI Header (HDR): This field always returns 80 to indicate that Device #0 is a multifunction  
device. If Functions other than 0 are disabled, this field returns a 00 to indicate that the GMCH is a  
single function device with standard header layout. Writes to this location have no effect.  
4.8.9  
SVID – Subsystem Vendor Identification Register  
Address Offset:  
Default Value:  
Access:  
2C-2Dh  
0000h  
Read/Write Once  
16 bits  
Size:  
This value is used to identify the vendor of the subsystem.  
Bit  
Descriptions  
15:0  
Subsystem Vendor ID (SUBVID): This field should be programmed during boot-up to indicate the  
vendor of the system board. After it has been written once, it becomes Read Only.  
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®
Intel 82854 Graphics Memory Controller Hub (GMCH)  
4.8.10  
SID – Subsystem Identification Register  
Address Offset:  
Default Value:  
Access:  
2E-2Fh  
0000h  
Read/Write Once  
16 bits  
Size:  
This value is used to identify a particular subsystem.  
Bit  
Descriptions  
15:0  
Subsystem ID (SUBID): This field should be programmed during BIOS initialization. After it has  
been written once, it becomes Read Only.  
4.8.11  
CAPPTR – Capabilities Pointer Register  
Address Offset:  
Default Value:  
Access:  
34h  
40h  
Read Only  
8 bits  
Size:  
The CAPPTR provides the offset that is the pointer to the location of the first device capability in  
the capability list.  
Bit  
Descriptions  
7:0  
Pointer to the offset of the first capability ID register block: In this case the first capability is  
the Product-Specific Capability, which is located at offset 40h.  
56  
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Register Description  
4.8.12  
CAPID – Capabilities Identification Register (Device #0)  
Address Offset:  
Default Value:  
Access:  
40-44h  
chipset independent  
Read Only  
40 bits  
Size:  
The Capability Identification Register uniquely identifies chipset capabilities as defined in the  
table below. The bits in this register are intended to define a capability ceiling for each feature, not  
a capability select. The capability selection for each feature is implemented elsewhere. The  
mechanism to select the capability for each feature must comprehend these Capability registers and  
not allow a selected setting above the ceiling specified in these registers. The BIOS must read this  
register to identify the part and comprehend the capabilities specified within when configuring the  
effected portions of the GMCH.  
The default setting, in most cases, allows the maximum capability. Exceptions are noted in the  
individual bits. This register is Read Only. Writes to this register have no effect.  
Bit  
Descriptions  
39:37  
Capability ID [2:0]:  
000: Intel® 82854 GMCH  
001-111: Reserved  
36:28  
27:24  
Reserved  
CAPREG Version: This field has the value 0001b to identify the first revision of the CAPREG  
definition.  
23:16  
15:0  
Cap_length: This field has the value 05h indicating the structure length.  
Reserved  
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®
Intel 82854 Graphics Memory Controller Hub (GMCH)  
4.8.13  
GMC – GMCH Miscellaneous Control Register (Device #0)  
Address Offset:  
Default Value:  
Access:  
50-51h  
0000h  
Read/Write  
16 bits  
Size:  
Bit  
Descriptions  
15:10  
Reserved  
Reserved  
9
8
RRBAR Access Enable—R/W:  
1: Enables the RRBAR space.  
0: Disable  
7:1  
0
Reserved  
MDA Present (MDAP)—R/W:  
This bit should not be set when the VGA Enable bit is not set. If the VGA enable bit is set, then  
accesses to IO address range x3BCh–x3BFh are forwarded to Hub interface. If the VGA enable bit  
is not set then accesses to IO address range x3BCh–x3BFh are treated just like any other IO  
accesses. MDA resources are defined as the following:  
Memory: 0B0000h – 0B7FFFh  
I/O: 3B4h, 3B5h, 3B8h, 3B9h, 3BAh, 3BFh,  
(including ISA address aliases, A[15:10] are not used in decode)  
Any I/O reference that includes the I/O locations listed above, or their aliases, will be forwarded to  
Hub interface even if the reference includes I/O locations not listed above.  
The following table shows the behavior for all combinations of MDA and VGA:  
VGA  
0 0  
MDA Behavior  
All References to MDA and VGA go to Hub interface (Default)  
Reserved  
0 1  
1 0  
All References to VGA go to PCI.  
MDA-only references (I/O address 3BF and aliases will go to Hub interface.  
1 1  
VGA References go to PCI; MDA References go to Hub interface  
58  
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Register Description  
4.8.14  
GGC – GMCH Graphics Control Register (Device #0)  
Address Offset:  
Default Value:  
Access:  
52-53h  
0030h  
Read/Write  
16 bits  
Size:  
Bit  
Descriptions  
Reserved  
15:7  
6:4  
Graphics Mode Select (GMS): This field is used to select the amount of Main system memory  
that is pre-allocated to support the Internal Graphics Device in VGA (non-linear) and Native (linear)  
modes. The BIOS ensures that system memory is pre-allocated only when Internal Graphics is  
enabled.  
000: No system memory pre-allocated. Device #2 (IGD) does not claim VGA cycles (Memory and  
I/O), and the Sub-Class Code field within Device #2 Function #0 Class Code register is 80.  
001: DVMT (UMA) mode, 1 MB of system memory pre-allocated for frame buffer.  
010: DVMT (UMA) mode, 4 MB of system memory pre-allocated for frame buffer.  
011: DVMT (UMA) mode, 8 MB of system memory pre-allocated for frame buffer.  
100: DVMT (UMA) mode, 16 MB of system memory pre-allocated for frame buffer.  
101: DVMT (UMA) mode, 32 MB of system memory pre-allocated for frame buffer.  
All other combinations reserved.  
3
2
Reserved  
Device #2 Function #1 Enable/Disable:  
1: Disable Function #1 within Device #2.  
0: Enable Function #1 within Device #2.  
1
0
IGD VGA Disable (IVD): VGA can only be enabled in Naytive Graphics Mode. If strapped in other  
mode, this bit should always set to 1.  
1: Disable. Device #2 (IGD) does not claim VGA Memory and I/O Mem cycles, and the Sub-Class  
Code field within Device #2 Function #0 Class Code register is 80.  
0: Enable. Device #2 (IGD) claims VGA Memory and I/O cycles, the Sub-Class Code within Device  
#2 Class Code register is 00.  
Reserved  
D15343-003  
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®
Intel 82854 Graphics Memory Controller Hub (GMCH)  
4.8.15  
DAFC – Device and Function Control Register (Device #0)  
Address Offset:  
Default Value:  
Access:  
54-55h  
0000h  
Read/Write  
16 bits  
Size:  
This 16-bit register controls the visibility of devices and functions within the GMCH to  
configuration software.  
Bit  
Description  
Reserved  
15:8  
7
Device #2 Disable:  
1: Disabled.  
0: Enabled.  
6:3  
2
Reserved  
Device #0 Function #3 Disable:  
1: Disable Function #3 registers within Device #0 and all associated DDR SDRAM and I/O ranges.  
0: Enable Function #3 within Device #0.  
1
0
Reserved  
Device #0 Function #1 Disable:  
1: Disable Function #1 within Device #0.  
0: Enable Function #1 within Device #0.  
4.8.16  
FDHC – Fixed DRAM Hold Control Register (Device #0)  
Address Offset:  
Default Value:  
Access:  
58h  
00h  
Read/Write  
8 bits  
Size:  
This 8-bit register controls a single fixed DDR SDRAM hole: 15-16 MB.  
Bit  
Description  
7
Hole Enable (HEN): This field enables a memory hole in DDR SDRAM space. Host cycles  
matching an enabled hole are passed onto ICH4-M through Hub interface. The GMCH will ignore  
Hub interface cycles matching an enabled hole.  
NOTE: A selected hole is not re-mapped.  
0: None  
1: 15 MB–16 MB (1MBs)  
6:0  
Reserved  
60  
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Register Description  
4.8.17  
PAM(6:0) – Programmable Attribute Map Register (Device #0)  
Address Offset:  
Default Value:  
Access:  
59-5Fh  
00h Each  
Read/Write  
Size:  
4 bits/register, 14 registers  
The GMCH allows programmable DDR SDRAM attributes on 13 Legacy system memory  
segments of various sizes in the 640 kB -1 MB address range. Seven Programmable Attribute Map  
(PAM) registers are used to support these features. Cacheability of these areas is controlled via the  
MTRR registers in the P6 processor. Two bits are used to specify system memory attributes for  
each system memory segment. These bits apply to both Host and Hub interface initiator accesses to  
the PAM areas. These attributes are:  
RE - Read Enable. When RE = 1, the CPU Read accesses to the corresponding system  
memory segment are claimed by the GMCH and directed to main system memory. Conversely,  
when RE = 0, the Host Read accesses are directed to PCI0.  
WE - Write Enable. When WE = 1, the Host Write accesses to the corresponding system  
memory segment are claimed by the GMCH and directed to main system memory. Conversely,  
when WE = 0, the Host Write accesses are directed to PCI0.  
The RE and WE attributes permit a system memory segment to be Read Only, Write Only, Read/  
Write, or Disabled. For example, if a system memory segment has RE = 1 and WE = 0, the segment  
is Read Only.  
Each PAM register controls two regions, typically 16 kB in size. Each of these regions has a 4-bit  
field. The 4 bits that control each region have the same encoding and are defined in the following  
table.  
Table 20.  
Attribute Bit Assignment  
Bits [7, 3]  
Reserved  
Bits [6, 2]  
Reserved  
Bits [5, 1]  
WE  
Bits [4, 0]  
RE  
Description  
X
X
0
0
Disabled. DDR SDRAM is disabled and all accesses  
are directed to Hub interface. The GMCH does not  
respond as a Hub interface target for any Read or  
Write access to this area.  
X
X
0
1
Read Only. Reads are forwarded to DDR SDRAM  
and Writes are forwarded to Hub interface for  
termination. This Write protects the corresponding  
DDR SDRAM segment. The GMCH will respond as a  
Hub interface target for Read accesses but not for  
any Write accesses.  
X
X
X
X
1
1
0
1
Write Only. Writes are forwarded to DDR SDRAM  
and Reads are forwarded to the Hub interface for  
termination. The GMCH will respond as a Hub  
interface target for Write accesses but not for any  
Read accesses.  
Read/Write. This is the normal operating mode of  
main system memory. Both Read and Write cycles  
from the host are claimed by the GMCH and  
forwarded to DDR SDRAM. The GMCH will respond  
as a Hub interface target for both Read and Write  
accesses.  
D15343-003  
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®
Intel 82854 Graphics Memory Controller Hub (GMCH)  
As an example, consider a BIOS that is implemented on the Expansion bus. During the  
initialization process, the BIOS can be shadowed in main system memory to increase the system  
performance. When BIOS is shadowed in main system memory, it should be copied to the same  
address location. To shadow the BIOS, the attributes for that address range should be set to Write  
Only. The BIOS is shadowed by first doing a Read of that address. This Read is forwarded to the  
Expansion bus. The Host then does a Write of the same address, which is directed to main system  
memory. After the BIOS is shadowed, the attributes for that system memory area are set to Read  
Only so that all Writes are forwarded to the Expansion bus. Figure 4 and Table 21 show the PAM  
registers and the associated attribute bits.  
Figure 4.  
PAM Registers  
Offset  
PAM6  
PAM5  
PAM4  
PAM3  
PAM2  
PAM1  
PAM0  
5Fh  
5Eh  
5Dh  
5Ch  
5Bh  
5Ah  
59h  
7
6
5
4
3
2
1
0
R
R
WE  
RE  
R
R
WE  
RE  
Reserved  
Reserved  
Read Enable (R/W)  
1=Enable  
0=Disable  
Write Enable (R/W)  
1=Enable  
0=Disable  
Write Enable (R/W)  
1=Enable  
0=Disable  
Read Enable (R/W)  
1=Enable  
0=Disable  
Reserved  
Reserved  
pam  
62  
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Register Description  
Table 21.  
PAM Registers and Associated System Memory Segments  
PAM Reg  
Attribute Bits  
System Memory Segment  
Reserved  
Comments  
Offset  
PAM0[3:0]  
59h  
PAM0[7:4]  
PAM1[3:0]  
PAM1[7:4]  
PAM2[3:0]  
PAM2[7:4]  
PAM3[3:0]  
PAM3[7:4]  
PAM4[3:0]  
PAM4[7:4]  
PAM5[3:0]  
PAM5[7:4]  
PAM6[3:0]  
PAM6[7:4]  
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
WE  
RE  
0F0000h–0FFFFFh  
0C0000h–0C3FFFh  
0C4000h–0C7FFFh  
0C8000h–0CBFFFh  
0CC000h–0CFFFFh  
0D0000h–0D3FFFh  
0D4000h–0D7FFFh  
0D8000h–0DBFFFh  
0DC000h–0DFFFFh  
0E0000h–0E3FFFh  
0E4000h–0E7FFFh  
0E8000h–0EBFFFh  
0EC000h–0EFFFFh  
BIOS Area  
59h  
5Ah  
5Ah  
5Bh  
5Bh  
5Ch  
5Ch  
5Dh  
5Dh  
5Eh  
5Eh  
5Fh  
5Fh  
WE  
WE  
WE  
WE  
WE  
WE  
WE  
WE  
WE  
WE  
WE  
WE  
RE  
RE  
RE  
RE  
RE  
RE  
RE  
RE  
RE  
RE  
RE  
RE  
ISA Add-on BIOS  
ISA Add-on BIOS  
ISA Add-on BIOS  
ISA Add-on BIOS  
ISA Add-on BIOS  
ISA Add-on BIOS  
ISA Add-on BIOS  
ISA Add-on BIOS  
BIOS Extension  
BIOS Extension  
BIOS Extension  
BIOS Extension  
For details on overall system address mapping scheme see the Address Decoding section of this  
document.  
DOS Application Area (00000h-9FFFh)  
The DOS area is 640 kB in size and it is further divided into two parts. The 512-kB area at 0 to  
7FFFFh is always mapped to the main system memory controlled by the GMCH, while the 128-kB  
address range from 080000 to 09FFFFh can be mapped to PCI0 or to main DDR SDRAM. By  
default this range is mapped to main system memory and can be declared as a main system  
memory hole (accesses forwarded to PCI0) via GMCH's FDHC Configuration register.  
Video Buffer Area (A0000h-BFFFFh)  
Attribute Bits do not control this 128-kB area. The Host-initiated cycles in this region are always  
forwarded to either PCI0 or PCI2 unless this range is accessed in SMM mode. Routing of accesses  
is controlled by the Legacy VGA Control Mechanism of the "Virtual" PCI-PCI Bridge Device  
embedded within the GMCH.  
This area can be programmed as SMM area via the SMRAM register. When the GMCH is strapped  
in other mode, or when used as an SMM space, this range can not be accessed from the Hub  
interface.  
Expansion Area (C0000h-DFFFFh)  
This 128-kB area is divided into eight 16-kB segments that can be assigned with different attributes  
via PAM Control register as defined in Figure 4 and Table 21.  
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®
Intel 82854 Graphics Memory Controller Hub (GMCH)  
Extended System BIOS Area (E0000h-EFFFFh)  
This 64-kB area is divided into four 16-kB segments that can be assigned with different attributes  
via PAM Control register as defined in Figure 4 and Table 21.  
System BIOS Area (F0000h-FFFFFh)  
This area is a single 64-kB segment that can be assigned with different attributes via PAM Control  
register as defined in Figure 4 and Table 21.  
4.8.18  
SMRAM – System Management RAM Control Register (Device #0)  
Address Offset:  
Default Value:  
Access:  
60h  
02h  
Read/Write/Lock, Read Only  
8 bits  
Size:  
The SMRAM register controls how accesses to Compatible and Extended SMRAM spaces are  
treated. The Open, Close, and Lock Bits function only when G_SMRAME Bit is set to a 1. Also,  
the Open Bit must be Reset before the LOCK Bit is set.  
Bit  
Description  
Reserved  
7
6
SMM Space Open (D_OPEN): When D_OPEN=1 and D_LCK=0, the SMM space DDR  
SDRAM is made visible even when SMM decode is not active. This is intended to help BIOS  
initialize SMM space. Software should ensure that D_OPEN=1 and D_CLS=1 are not set at the  
same time. When D_LCK is set to a 1, D_OPEN is Reset to 0 and becomes Read Only.  
5
4
SMM Space Closed (D_CLS): When D_CLS = 1 SMM Space, DDR SDRAM is not accessible  
to data references, even if SMM decode is active. Code references may still access SMM  
space DDR SDRAM. This will allow SMM software to reference “through” SMM space to  
update the display even when SMM is mapped over the VGA range. Software should ensure  
that D_OPEN=1 and D_CLS=1 are not set at the same time. D_CLS applies to all SMM spaces  
(Cseg, Hseg, and Tseg).  
SMM Space Locked (D_LCK): When D_LCK is set to 1, then D_OPEN is Reset to 0 and  
D_LCK, D_OPEN, G_SMRAME, C_BASE_SEG, GMS, DRB, DRA, H_SMRAM_EN, TSEG_SZ  
and TSEG_EN become Read Only. D_LCK can be set to 1 via a normal Configuration Space  
Write but can only be cleared by a Full Reset. The combination of D_LCK and D_OPEN  
provide convenience with security. The BIOS can use the D_OPEN function to initialize SMM  
space and then use D_LCK to “lock down” SMM space in the future so that no application  
software (or BIOS itself) can violate the integrity of SMM space, even if the program has  
knowledge of the D_OPEN function.  
3
Global SMRAM Enable (G_SMRAME): If set to a 1, then Compatible SMRAM functions is  
enabled, providing 128 kB of DDR SDRAM accessible at the A0000h address while in SMM  
(ADS# with SMM decode). To enable Extended SMRAM function this bit must be set to 1, refer  
to the section on SMM for more details. Once D_LCK is set, this bit becomes Read Only.  
2:0  
Compatible SMM Space Base Segment (C_BASE_SEG)—RO: This field indicates the  
location of SMM space. “SMM DRAM” is not remapped. It is simply “made visible” if the  
conditions are right to access SMM space, otherwise the access is forwarded to Hub interface.  
C_BASE_SEG is hardwired to 010 to indicate that the GMCH supports the SMM space at  
A0000h–BFFFFh.  
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Register Description  
4.8.19  
ESMRAMC – Extended System Management RAM Control (Device #0)  
Address Offset:  
Default Value:  
Access:  
61h  
38h  
Read/Write/Lock  
8 bits  
Size:  
The Extended SMRAM register controls the configuration of Extended SMRAM Space. The  
Extended SMRAM (E_SMRAM) Memory provides a Write-Back cacheable SMRAM Memory  
Space that is above 1 MB.  
Bit  
Description  
7
H_SMRAM_EN (H_SMRAME): Controls the SMM Memory Space location (that is, above 1 MB  
or below 1 MB). When G_SMRAME is 1 and H_SMRAME this bit is set to 1, the high SMRAM  
Memory Space is enabled. SMRAM accesses from 0FEDA0000h to 0FEDBFFFFh are  
remapped to DDR SDRAM address 000A0000h to 000BFFFFh.  
Once D_LCK is set, this bit becomes Read Only.  
6
E_SMRAM_ERR (E_SMERR): This bit is set when CPU accesses the defined DDR SDRAM  
ranges in Extended SMRAM (High system memory and T-segment) while not in SMM Space. It  
is software’s responsibility to clear this bit. The software must Write a 1 to this bit to clear it.  
5
SMRAM_Cache (SM_CACHE): GMCH forces this bit to 1.  
SMRAM_L1_EN (SM_L1): GMCH forces this bit to 1.  
SMRAM_L2_EN (SM_L2): GMCH forces this bit to 1.  
Reserved  
4
3
2:1  
0
TSEG_EN (T_EN): Enabling of SMRAM Memory (TSEG, 1 Mbytes of additional SMRAM  
Memory) for Extended SMRAM Space only. When G_SMRAME =1 and TSEG_EN = 1, the  
TSEG is enabled to appear in the appropriate physical address space.  
Once D_LCK is set, this bit becomes Read Only.  
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®
Intel 82854 Graphics Memory Controller Hub (GMCH)  
4.8.20  
ERRSTS – Error Status Register (Device #0)  
Address Offset:  
Default Value:  
Access:  
62-63h  
0000h  
Read/Write Clear  
16 bits  
Size:  
This register is used to report various error conditions via Hub Interface Special cycles. An SERR,  
SMI, or SCI Error Hub Interface Special cycle may be generated on a zero to one transition of any  
of these flags when enabled in the PCICMD/ERRCMD, SMICMD, or SCICMD registers  
respectively.  
Bit  
Description  
Reserved  
15:14  
13  
FSB Strobe Glitch Detected (FSBAGL): When this bit is set to 1 the GMCH has detected a glitch  
on one of the FSB strobes. Writing a 1 to it clears this bit.  
12  
11  
GMCH Software Generated Event for SMI:  
1: This indicates the source of the SMI was a Device #2 Software Event.  
0: Software must Write a 1 to clear this bit.  
GMCH Thermal Sensor Event for SMI/SCI/SERR:  
1: Indicates that a GMCH Thermal Sensor trip has occurred and an SMI, SCI or SERR has been  
generated. Note that the status bit is set only if a message is sent based on Thermal event  
enables in Error Command, SMI Command and SCI Command registers. Note that a Trip Point  
can generate one of SMI, SCI or SERR interrupts (two or more per event is illegal). Multiple Trip  
Points can generate the same interrupt. If software chooses this mode, then subsequent Trips  
may be lost.  
0: Software must Write a 1 to clear this status bit. If this bit is set, then an interrupt message will not  
be sent on a new Thermal Sensor event.  
10  
9
Reserved  
LOCK to non-DDR SDRAM Memory Flag (LCKF)—R/WC:  
1: Indicates that a CPU initiated LOCK cycle targeting non-DDR SDRAM Memory Space occurred.  
0: Software must Write a 1 to clear this status bit  
8
7
Received Refresh Timeout—R/WC:  
1: This bit is set when 1024 memory core refresh are Queued up.  
0: Software must Write a 1 to clear this status bit.  
DRAM Throttle Flag (DTF)—R/WC:  
1: Indicates that the DDR SDRAM Throttling condition occurred.  
0: Software must Write a 1 to clear this status bit.  
6
5
Reserved  
Received Unimplemented Special Cycle Hub Interface Completion Packet FLAG (UNSC)—  
R/WC:  
1: Indicates that the GMCH initiated a Hub interface request that was terminated with an  
Unimplemented Special Cycle completion packet.  
0: Software must Write a 1 to clear this status bit.  
4:0  
Reserved  
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Register Description  
4.8.21  
ERRCMD – Error Command Register (Device #0)  
Address Offset:  
Default Value:  
Access:  
64-65h  
0000h  
Read/Write Clear  
16 bits  
Size:  
This register enables various errors to generate a SERR Hub Interface Special cycle. Since the  
GMCH does not have a SERR# signal, SERR messages are passed from the GMCH to the ICH4-M  
over Hub interface. The actual generation of the SERR message is globally enabled for Device  
#0 via the PCI Command register.  
Note: An error can generate one and only one Hub Interface Error Special cycle. It is software's  
responsibility to make sure that when an SERR error message is enabled for an error condition,  
SMI and SCI error messages are disabled for that same error condition.  
Bit  
Description  
Reserved  
15:14  
13  
SERR on FSB Strobe Glitch: When this bit is asserted, the GMCH will generate a HI SERR  
message when a glitch is detected on one of the FSB strobes.  
12  
11  
Reserved  
SERR on GMCH Thermal Sensor Event:  
1: The GMCH generates a SERR Hub Interface Special cycle on a Thermal Sensor Trip that  
requires an SERR. The SERR must not be enabled at the same time as the SMI/SCI for a  
Thermal Sensor Trip event.  
0: Software must write a 1 to clear this status bit.  
10  
9
Reserved  
SERR on LOCK to non-DDR SDRAM Memory:  
1: The GMCH generates an SERR Hub Interface Special cycle when a CPU initiated LOCK  
transaction targeting non-DDR SDRAM Memory Space occurs.  
0: Reporting of this condition is disabled.  
8
7
6
SERR on DDR SDRAM Refresh timeout:  
1: The GMCH generates an SERR Hub Interface Special cycle when a DDR SDRAM Refresh  
timeout occurs.  
0: Reporting of this condition is disabled.  
SERR on DDR SDRAM Throttle Condition:  
1: The GMCH generates an SERR Hub Interface Special cycle when a DDR SDRAM Read or  
Write Throttle condition occurs.  
0: Reporting of this condition is disabled.  
SERR on Receiving Target Abort on Hub Interface:  
1: The GMCH generates an SERR Hub Interface Special cycle when a GMCH originated Hub  
interface cycle is terminated with a Target Abort.  
0: Reporting of this condition is disabled.  
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®
Intel 82854 Graphics Memory Controller Hub (GMCH)  
5
SERR on Receiving Unimplemented Special Cycle Hub Interface Completion Packet:  
1: The GMCH generates an SERR Hub Interface Special cycle when a GMCH initiated Hub  
interface request is terminated with a Unimplemented Special cycle completion packet.  
0: Reporting of this condition is disabled.  
4:2  
1
Reserved  
SERR on Multiple-bit ECC Error:  
0: This system does not support ECC, this field must be set to 0.  
0
SERR on Single-bit ECC Error:  
0: This system does not support ECC, this field must be set to 0.  
4.8.22  
SMICMD – SMI Error Command Register (Device #0)  
Address Offset:  
Default Value:  
Access:  
66h  
00h  
Read/Write  
8 bits  
Size:  
This register enables various errors to generate an SMI Hub Interface Special cycle. When an Error  
Flag is set in the ERRSTS register, it can generate a SERR, SMI, or SCI Hub Interface Special  
cycle when enabled in the ERRCMD, SMICMD, or SCICMD registers respectively.  
Note: An error can generate one and only one Hub Interface Error Special cycle. It is software's  
responsibility to make sure that when an SMI Error Message is enabled for an error condition,  
SERR, and SCI Error Messages are disabled for that same error condition.  
Bit  
Description  
7:4  
3
Reserved  
SMI on GMCH Thermal Sensor Trip:  
1: An SMI Hub Interface Special cycle is generated by GMCH when the Thermal Sensor Trip  
requires an SMI. A Thermal Sensor Trip Point cannot generate more than one special cycle.  
2
1
Reserved  
SMI on Multiple-bit ECC Error:  
0: This system does not support ECC, this field must be set to 0.  
0
SMI on Single-bit ECC Error:  
0: This system does not support ECC, this field must be set to 0.  
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Register Description  
4.8.23  
SCICMD – SCI Error Command Register (Device #0)  
Address Offset:  
Default Value:  
Access:  
67h  
00h  
Read/Write  
8 bits  
Size:  
This register enables various errors to generate a SCI Hub Interface Special cycle. When an Error  
Flag is set in the ERRSTS register, it can generate a SERR, SMI, or SCI Hub Interface Special  
cycle when enabled in the ERRCMD, SMICMD, or SCICMD registers respectively.  
Note: An error can generate one and only one Hub Interface Error Special cycle. It is software's  
responsibility to make sure that when an SCI error message is enabled for an error condition, SERR  
and SMI Error Messages are disabled for that same error condition.  
Bit  
Description  
7:4  
3
Reserved  
SCI on GMCH Thermal Sensor Trip:  
1: An SCI Hub Interface Special cycle is generated by GMCH when the Thermal Sensor Trip  
requires an SCI. A Thermal Sensor Trip Point cannot generate more than one special cycle.  
2
1
Reserved  
SCI on Multiple-bit ECC Error:  
0: This system does not support ECC, this field must be set to 0.  
0
SCI on Single-bit ECC Error:  
0: This system does not support ECC, this field must be set to 0.  
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®
Intel 82854 Graphics Memory Controller Hub (GMCH)  
4.8.24  
SHIC – Secondary Host Interface Control Register (Device #0)  
Address Offset:  
Default Value:  
Access:  
74-77h  
00006010h  
Read Only, Read/Write  
32 bits  
Size:  
Bit  
Descriptions  
Reserved  
31  
30  
BREQ0# Control of FSB Address and Control bus power management:  
0: Disable FSB address and control bus power management.  
1: Eisable FSB address and control bus power management.  
29:28  
27  
Reserved  
On Die Termination (ODT) Gating Disable:  
0: Enable.  
1: Disable.  
26:7  
6
Reserved  
FSB Data Bus Power Management Control:  
0: FSB Data Bus Power Management disabled (Default).  
1: FSB Data Bus Power Management enabled  
5
Reserved  
4:3  
DPWR# Control.  
00: DPWR# pin is always asserted.  
10: DPWR# pin is asserted at least 2 clocks before read data is returned to the processor on the  
FSB (2 clocks before DRDY# asserted). This is default setting.  
01: DPWR# is always de-asserted.  
11: Reserved  
2
C2 state GMCH FSB Interface Power Management Control:  
0: Power Management Disabled in C2 state  
1: Power Management Enabled in C2 state  
1
0
Reserved.  
Reserved  
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Register Description  
4.8.25  
HEM – Host Error Control, Status, and Observation (Device #0)  
Address Offset:  
Default Value:  
Access:  
F0-F3h  
00000000h  
Read Only, Read/Write  
32 bits  
Size:  
Bit  
Description  
31  
Detected HADSTB1# Glitch (ASTB1GL): This bit is set when the GMCH has detected a glitch  
on address strobe HADSTB1#. Software must write a 1 to clear this status bit.  
30  
29  
28  
27  
Detected HADSTB0# Glitch (ASTB0GL): This bit is set when the GMCH has detected a glitch  
on address strobe HADSTB0#. Software must write a 1 to clear this status bit.  
Detected HDSTB3# Glitch (DSTB3GL): This bit is set when the GMCH has detected a glitch on  
data strobe pair HDSTB3#. Software must write a 1 to clear this status bit.  
Detected HDSTB2# Glitch (DSTB2GL): This bit is set when the GMCH has detected a glitch on  
data strobe pair HDSTB2#. Software must write a 1 to clear this status bit.  
Detected HDSTB1# Glitch (DSTB1GL): This bit is set when the GMCH has detected a glitch on  
data strobe pair HDSTB1#. Software must write a 1 to clear this status bit.  
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®
Intel 82854 Graphics Memory Controller Hub (GMCH)  
4.9  
Intel 854 GMCH Main Memory Control, Memory I/O Control  
Registers (Device #0, Function #1)  
The following table shows the GMCH Configuration Space for Device #0, Function #1. See  
Table 22.  
Host-Hub I/F Bridge/System Memory Controller Configuration Space (Device #0,  
Function#1)  
Register  
Symbol  
Register  
Start  
Register  
End  
Register Name  
Default Value  
Access  
Vendor Identification  
Device Identification  
PCI Command  
VID  
DID  
00  
02  
04  
06  
08  
0A  
0B  
0E  
2C  
01  
03  
05  
07  
08  
0A  
0B  
0E  
2D  
8086h  
358Ch  
0006h  
0080h  
02h  
RO  
RO  
PCICMD  
PCISTS  
RID  
RO,R/W  
RO,R/WC  
RO  
PCI Status  
Revision Identification  
Sub-Class Code  
Base Class Code  
Header Type  
SUBC  
BCC  
80h  
RO  
08h  
RO  
HDR  
80h  
RO  
Subsystem Vendor  
Identification  
SVID  
0000h  
R/WO  
Subsystem Identification  
Capabilities Pointer  
SID  
CAPPTR  
DRB  
2E  
34  
40  
50  
60  
68  
2F  
34  
43  
51  
63  
6B  
0000h  
00h  
R/WO  
RO  
DRAM Row 0-3 Boundary  
DRAM Row 0-3 Attribute  
DRAM Timing  
00000000h  
7777h  
RW  
DRA  
RW  
DRT  
18004425h  
00000000h  
RW  
DRAM Controller Power  
Management Control  
PWRMG  
R/W  
Dram Controller Mode  
DRAM Throttle Control  
DRC  
DTC  
70  
A0  
73  
A3  
00000081h  
00000000h  
R/W  
R/W/L  
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Register Description  
4.9.1  
VID – Vendor Identification Register  
Address Offset:  
Default Value:  
Access:  
00-01h  
8086h  
Read Only  
16 bits  
Size:  
The VID Register contains the vendor identification number. This 16-bit register combined with  
the Device Identification Register uniquely identifies any PCI device. Writes to this register have  
no effect.  
Bit  
Descriptions  
15:0  
Vendor Identification (VID): This register field contains the PCI standard identification for Intel.  
4.9.2  
DID – Device Identification Register  
Address Offset:  
Default Value:  
Access:  
02-03h  
358Ch  
Read Only  
16 bits  
Size:  
This 16-bit register combined with the Vendor Identification register uniquely identifies any PCI  
device. Writes to this register have no effect.  
Bit  
Descriptions  
15:0  
Device Identification Number (DID): This is a 16-bit value assigned to the GMCH Host- HI  
Bridge Function #1 (358Ch).  
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®
Intel 82854 Graphics Memory Controller Hub (GMCH)  
4.9.3  
PCICMD – PCI Command Register  
Address Offset:  
Default Value:  
Access:  
04-05h  
0006h  
Read Only, Read/Write  
16 bits  
Size:  
Since Intel chipset Device #0 does not physically reside on PCI_A, many of the bits are not  
implemented.  
Bit  
Descriptions  
Reserved  
15:10  
9
Fast Back-to-Back Enable (FB2B): This bit controls whether or not the master can do fast back-  
to-back Write. Since Device #0 is strictly a target, this bit is not implemented and is hardwired to  
0. Writes to this bit position have no affect.  
8
7
6
5
4
SERR Enable (SERRE): SERR# is not implemented by Function #1 of Device #0 of the GMCH  
and this bit is hardwired to 0. Writes to this bit position have no effect.  
Address/Data Stepping Enable (ADSTEP): Address/data stepping is not implemented in the  
GMCH, and this bit is hardwired to 0. Writes to this bit position have no effect.  
Parity Error Enable (PERRE): PERR# is not implemented by GMCH and this bit is hardwired to  
0. Writes to this bit position have no effect.  
VGA Palette Snoop Enable (VGASNOOP): The GMCH does not implement this bit and it is  
hardwired to a 0. Writes to this bit position have no effect.  
Memory Write and Invalidate Enable (MWIE): The GMCH will never issue Memory Write and  
Invalidate commands. This bit is therefore hardwired to 0. Writes to this bit position will have no  
effect.  
3
2
1
0
Special Cycle Enable (SCE): The GMCH does not implement this bit and it is hardwired to a 0.  
Writes to this bit position have no effect.  
Bus Master Enable (BME): The GMCH is always enabled as a master on HI. This bit is  
hardwired to a 1. Writes to this bit position have no effect.  
Memory Access Enable (MAE): The GMCH always allows access to main system memory. This  
bit is not implemented and is hardwired to 1. Writes to this bit position have no effect.  
I/O Access Enable (IOAE): This bit is not implemented in the GMCH and is hardwired to a 0.  
Writes to this bit position have no effect.  
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Register Description  
4.9.4  
PCISTS – PCI Status Register  
Address Offset:  
Default Value:  
Access:  
06-07h  
0080h  
Read Only, Read/Write Clear  
16 bits  
Size:  
PCISTS is a 16-bit status register that reports the occurrence of error events on Device #0's PCI  
Interface. Bit 14 is Read/Write Clear. All other bits are Read Only. Since GMCH Device #0 does  
not physically reside on PCI_A, many of the bits are not implemented.  
Bit  
Descriptions  
15  
Detected Parity Error (DPE): The GMCH does not implement this bit and it is hardwired to a 0.  
Writes to this bit position have no effect.  
14  
Signaled System Error (SSE): The GMCH does not implement this bit and it is hardwired to a 0.  
Writes to this bit position have no effect.  
13  
Received Master Abort Status (RMAS): The GMCH does not implement this bit and it is  
hardwired to a 0. Writes to this bit position have no effect.  
12  
Received Target Abort Status (RTAS): The GMCH does not implement this bit and it is  
hardwired to a 0. Writes to this bit position have no effect.  
11  
Signaled Target Abort Status (STAS): The GMCH does not implement this bit and it is  
hardwired to a 0. Writes to this bit position have no effect.  
10:9  
DEVSEL Timing (DEVT): These bits are hardwired to “00”. Writes to these bit positions have no  
affect. Device #0 does not physically connect to PCI_A. These bits are set to “00” (fast decode)  
so that the GMCH does not limit optimum DEVSEL timing for PCI_A.  
8
7
Master Data Parity Error Detected (DPD): The GMCH does not implement this bit and it is  
hardwired to a 0. Writes to this bit position have no effect.  
Fast Back-to-Back (FB2B): This bit is hardwired to 1. Writes to these bit positions have no  
effect. Device #0 does not physically connect to PCI_A. This bit is set to 1 (indicating fast back-to-  
back capability) so that the GMCH does not limit the optimum setting for PCI_A.  
6:5  
4
Reserved  
Capability List (CLIST): This bit is hardwired to 0 to indicate to the configuration software that  
this device/function does not implement new capabilities.  
Default Value = 0  
3:0  
Reserved  
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®
Intel 82854 Graphics Memory Controller Hub (GMCH)  
4.9.5  
4.9.6  
4.9.7  
RID – Revision Identification Register  
Address Offset:  
Default Value:  
Access:  
08h  
02h  
Read Only  
8 bits  
Size:  
®
This register contains the revision number of the Intel 82854 GMCH Device #0. These bits are  
Read Only and Writes to this register have no effect.  
Bit  
Descriptions  
7:0  
Revision Identification Number (RID): This is an 8-bit value that indicates the revision  
identification number for the GMCH Device #0.  
RID – Revision Identification Register  
Address Offset:  
Default Value:  
Access:  
0Ah  
80h  
Read Only  
8 bits  
Size:  
®
This register contains the Sub-Class code for the Intel 82854 GMCH Device #0. This code is 80h  
indicating Other Peripheral device.  
Bit  
Descriptions  
7:0  
Sub-Class Code (SUBC): This is an 8-bit value that indicates the category of Peripheral device  
into which the GMCH Function #1 falls. The code is 80h indicating Other Peripheral device.  
BCC – Base Class Code Register  
Address Offset:  
Default Value:  
Access:  
0Bh  
08h  
Read Only  
8 bits  
Size:  
®
This register contains the Base Class code of the Intel 82854 GMCH Device #0 Function #1. This  
code is 08h indicating Other Peripheral device.  
Bit  
Descriptions  
7:0  
Base Class Code (BASEC): This is an 8-bit value that indicates the Base Class Code for the  
GMCH. This code has the value 08h, indicating Other Peripheral device.  
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Register Description  
4.9.8  
HDR – Header Type Register  
Address Offset:  
Default Value:  
Access:  
0Eh  
80h  
Read Only  
8 bits  
Size:  
This register identifies the header layout of the configuration space. No physical register exists at  
this location.  
Bit  
Descriptions  
7:0  
PCI Header (HDR): This field always returns 80 to indicate that Device #0 is a multifunction  
device. Reads and Writes to this location have no effect.  
4.9.9  
SVID – Subsystem Vendor Identification Register  
Address Offset:  
Default Value:  
Access:  
2C-2Dh  
0000h  
Read/Write Once  
16 bits  
Size:  
This value is used to identify the vendor of the subsystem.  
Bit  
Descriptions  
15:0  
Subsystem Vendor ID (SUBVID): This field should be programmed during boot-up to indicate  
the vendor of the system board. After it has been written once, it becomes Read Only.  
4.9.10  
SID – Subsystem Identification Register  
Address Offset:  
Default Value:  
Access:  
2E-2Fh  
0000h  
Read/Write Once  
16 bits  
Size:  
This value is used to identify a particular subsystem.  
Bit  
Descriptions  
15:0  
Subsystem ID (SUBID): This field should be programmed during BIOS initialization. After it has  
been Written once, it becomes Read Only.  
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®
Intel 82854 Graphics Memory Controller Hub (GMCH)  
4.9.11  
CAPPTR – Capabilities Pointer Register  
Address Offset:  
Default Value:  
Access:  
34h  
00h  
Read Only  
8 bits  
Size:  
The CAPPTR provides the offset that is the pointer to the location of the first device capability in  
the capability list.  
Bit  
Descriptions  
7:0  
Pointer to the offset of the first capability ID register block: In this case there are no  
capabilities, therefore these bits are hardwired to 00h to indicate the end of the capability linked  
list.  
4.9.12  
DRB – DRAM Row (0:3) Boundary Register (Device #0)  
Address Offset:  
Default Value:  
Access:  
40-43h  
00h each  
Read/Write  
8 bits each  
Size:  
The DDR SDRAM Row Boundary Register defines the upper boundary address of each DDR  
SDRAM row with a granularity of 32 MB. Each row has its own single-byte DRB register. For  
example, a value of 1 in DRB0 indicates that 32 MB of DDR SDRAM has been populated in the  
first row. Since the GMCH supports a total of four rows of system memory, DRB0-3 are used. The  
registers from 44h-4Fh are Reserved for DRBs 4-15.  
Row0: 40h  
Row1: 41h  
Row2: 42h  
Row3: 43h  
44h to 4Fh is reserved.  
DRB0 = Total system memory in Row0 (in 32-MB increments)  
DRB1 = Total system memory in Row0 + Row1 (in 32-MB increments)  
DRB2 = Total system memory in Row0 + Row1 + Row2 (in 32-MB increments)  
DRB3 = Total system memory in Row0 + Row1 + Row2 + Row3 (in 32-MB increments)  
Each Row is represented by a Byte. Each Byte has the following format.  
Bit  
Descriptions  
7:0  
DDR SDRAM Row Boundary Address: This 8-bit value defines the upper and lower addresses  
for each DDR SDRAM row. This 8-bit value is compared against a set of address lines to  
determine the upper address limit of a particular row. Also the minimum system memory  
supported is 64 MB in 64-Mb granularity; hence bit 0 of this register must be programmed to a  
zero.  
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Register Description  
4.9.13  
DRA – DRAM Row Attribute Register (Device #0)  
Address Offset:  
Default Value:  
Access:  
50-51h  
77h  
Read/Write  
8 bits  
Size:  
The DDR SDRAM Row Attribute Register defines the page sizes to be used when accessing  
different pairs of Rows. Each Nibble of information in the DRA registers describes the page size  
of a pair of Rows:  
Row 0, 1:  
Row 2, 3:  
52h-5Fh:  
50h  
51h  
Reserved.  
7
6
4
4
3
2
0
0
R
Row attribute for Row1  
R
Row Attribute for Row0  
7
6
3
2
R
Row attribute for Row3  
R
Row Attribute for Row2  
Bit  
Description  
7
Reserved  
6:4  
Row Attribute for odd-numbered Row: This field defines the page size of the corresponding row.  
000: Reserved  
001: 4 kB  
010: 8 kB  
011: 16 kB  
111: Not Populated  
Others: Reserved  
3
Reserved  
2:0  
Row Attribute for even-numbered Row: This field defines the page size of the corresponding row.  
000: Reserved  
001: 4 kB  
010: 16 kB  
111: Not Populated  
Others: Reserved  
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®
Intel 82854 Graphics Memory Controller Hub (GMCH)  
4.9.14  
DRT – DRAM Timing Register (Device #0)  
Address Offset:  
Default Value:  
Access:  
60-63h  
18004425h  
Read/Write  
32 bits  
Size:  
This register controls the timing of the DDR SDRAM controller.  
Bit  
Description  
31  
DDR Internal Write to Read Command delay (tWTR):  
The tWTR is a std. DDR SDRAM timing parameter with a value of 1 CK for CL=2 and 2.5. The  
tWTR is used to time RD command after a WR command (to same Row):  
0: tWTR is set to 1 Clock (CK), used for DDR SDRAM CL=2 or 2.5  
1: Reserved  
30  
DDR Write Recovery time (tWR):  
Write recovery time is a std. DDR timing parameter with the value of 15 ns. It should be set to 2 CK  
when DDR200 is used. The tWR is used to time PRE command launch after a WR command,  
when DDR SDRAM components are populated.  
0: tWR is set to 2 Clocks (CK)  
1: tWR is set to 3 Clocks (CK)  
29:28  
Back To Back Write-Read commands spacing (DDR different Rows/Bank):  
This field determines the WR-RD command spacing, in terms of common clocks for DDR SDRAM  
based on the following formula: DQSS + 0.5xBL + TA (WR-RD) – CL  
DQSS: is time from Write command to data and is always 1 CK  
BL: is Burst Length and can be set to 4.  
TA (WR-RD): is required DQ turn-around, can be set to 1 or 2 CK  
CL: is CAS Latency, can be set to 2 or 2.5  
Examples of usage:  
For BL=4, with single DQ turn-around and CL=2, this field must be set to 2 CK (1+2+1-2)  
Encoding  
00:  
CK between WR and RD commands  
4
01:  
3
2
10:  
11:  
Reserved  
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Register Description  
27:26  
Back To Back Read-Write commands spacing (DDR, same or different Rows/Bank): This  
field determines the RD-WR command spacing, in terms of common clocks based on the following  
formula: CL + 0.5xBL + TA (RD-WR) – DQSS  
DQSS: is time from Write command to data and is always 1 CK  
BL: is Burst Length which is set to 4  
TA (RD-WR): is required DQ turn-around, can be set to 1, 2 or 3 CK  
CL: is CAS latency, can be set to 2 or 2.5  
Examples of usage:  
For BL=4, with single DQ turn-around and CL=2, this field must be set to 4 CK (2+2+1-1)  
Encoding  
00:  
CK between RD and WR commands  
7
6
5
4
01:  
10:  
11:  
NOTE: Since reads in DDR SDRAM cannot be terminated by Writes, the Space between  
commands is not a function of Cycle Length but of Burst Length.  
25  
Back To Back Read-Read commands spacing (DDR, different Rows):  
This field determines the RD-RD Command Spacing, in terms of common clocks based on the  
following formula: 0.5xBL + TA(RD-RD)  
BL: is Burst Length and can be set to 4.  
TA (RD-RD): is required DQ turn-around, can be set to 1 or 2 CK  
Examples of usage:  
For BL=4, with single DQ turn-around, this field must be set to 3 CK (2+1)  
Encoding  
CK between RD and RD commands  
0:  
1:  
4
3
NOTE: Since a Read to a different row does not terminate a Read, the Space between commands  
is not a function of Cycle Length but of Burst Length.  
24:15  
14:12  
Reserved  
Refresh Cycle Time (tRFC):  
Refresh Cycle Time is measured for a given row from REF command (to perform a refresh) until  
following ACT to same row (to perform a Read or Write). It is tracked separately from tRC for DDR  
SDRAM.  
Current DDR SDRAM spec requires tRFC of 75 ns (DDR266) and 80 ns (DDR200). Therefore, this  
field will be set to 8 clocks for DDR200, 10 clocks for DDR266.  
Encoding  
000:  
tRFC  
14  
clocks  
clocks  
clocks  
clocks  
clocks  
clocks  
clocks  
clocks  
001:  
13  
12  
11  
10  
9
010:  
011:  
100:  
101:  
110:  
8
111:  
7
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®
Intel 82854 Graphics Memory Controller Hub (GMCH)  
11  
Activate to Precharge delay (tRAS), MAX:  
This bit controls the maximum number of clocks that a DDR SDRAM bank can remain open. After  
this time period, the system memory Controller will guarantee to pre-charge the bank. Note that  
this time period may or may not be set to overlap with time period that requires a refresh to  
happen.  
The DDR SDRAM Controller includes a separate tRAS-MAX counter for every supported bank.  
With a maximum of four rows and four banks per row, there are 16 counters.  
0: 120 micro-seconds  
1: Reserved.  
10:9  
Activate to Precharge delay (tRAS), MIN:  
This bit controls the number of DDR SDRAM clocks for tRAS MIN  
00: 8 Clocks  
01: 7 Clocks  
10: 6 Clocks  
11: 5 Clocks  
8:7  
6:5  
Reserved  
CAS# Latency (tCL):  
Encoding  
00:  
DDR SDRAM CL  
2.5  
01:  
2
10:  
Reserved  
Reserved  
11:  
4
Reserved  
3:2  
DDR SDRAM RAS# to CAS# Delay (tRCD): This bit controls the number of clocks inserted  
between a Row Activate command and a Read or Write command to that row.  
Encoding  
00:  
tRCD  
4 DDR SDRAM Clocks (DDR 333 SDRAM)  
3 DDR SDRAM Clocks  
2 DDR SDRAM Clocks  
Reserved  
01:  
10:  
11:  
1:0  
DDR SDRAM RAS# Precharge (tRP): This bit controls the number of clocks that are inserted  
between a row precharge command and an activate command to the same row.  
Encoding  
00:  
tRP  
4 DDR SDRAM Clocks (DDR 333 SDRAM)  
3 DDR SDRAM Clocks  
2 DDR SDRAM Clocks  
Reserved  
01:  
10:  
11:  
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Register Description  
4.9.15  
PWRMG – DRAM Controller Power Management Control Register  
(Device #0)  
Address Offset:  
Default Value:  
Access:  
68-6Bh  
00000000h  
Read/Write  
32 bits  
Size:  
Bit  
Description  
Reserved  
31:24  
23:20  
Row State Control: This field determines the number of clocks the System Memory Controller  
will remain in the idle state before it begins pre-charging all pages or powering down rows.  
- PDEn: Power Down Enable  
- PCEn: Page Close Enable  
- TC: Timer Control  
PDEn(23):  
PCEn(22):  
TC(21:20)  
Function  
0
0
1
1
1
1
0
1
0
1
1
1
XX  
XX  
XX  
00  
All Disabled  
Reserved  
Reserved  
Immediate Precharge and Powerdown  
Reserved  
01  
10  
Precharge and Power Down after 16 DDR  
SDRAM Clocks  
1
1
11  
Precharge and Power Down after 64 DDR  
SDRAM Clocks  
19:16  
15  
Reserved  
Self Refresh GMCH Memory Interface Data Bus Power Management Optimization Enable:  
0 = Enable  
1 = Disable  
14  
13  
12  
11  
CS# Signal Drive Control:  
0 = Enable CS# Drive Control, based on rules described in DRC bit 12.  
1 = Disable CS# Drive Control, based on rules described in DRC bit 12.  
Self Refresh GMCH Memory Interface Data Bus Power Management:  
0 = In Self Refresh Mode GMCH Power Management is Enabled.  
1 = In Self Refresh Mode the GMCH Power Management is Disabled.  
Dynamic Memory Interface Power Management:  
0 = Dynamic Memory Interface Power Management Enabled.  
1 = Dynamic Memory Interface Power Management Disabled.  
Rcven DLL shutdown disable:  
0 = Normal operation. RCVEN DLL is turned off when the corresponding SO-DIMM is  
unpopulated.  
1 = RCVEN DLL is turned on irrespective of SO-DIMM population.  
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Intel 82854 Graphics Memory Controller Hub (GMCH)  
10  
9:1  
0
Reserved.  
Reserved  
Power State S1/S3 Refresh Control:  
0 = Normal Operation, Pending refreshes are not completed before entering Self Refresh for S1/  
S3.  
1 = All Pending Refreshes plus one extra is performed before entering Self Refresh for S1/S3.  
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Register Description  
4.9.16  
DRC – DRAM Controller Mode Register (Device #0)  
Address Offset:  
Default Value:  
Access:  
70-73h  
00000081h  
RO, Read/Write  
32 bits  
Size:  
Bit  
Description  
31:30  
Revision Number (REV): Reflects the revision number of the format used for DDR SDRAM  
register definition (Read Only).  
29  
Initialization Complete (IC): This bit is used for communication of software state between the  
Memory Controller and the BIOS. BIOS sets this bit to 1 after initialization of the DDR SDRAM  
Memory Array is complete. Setting this bit to a 1 enables DDR SDRAM Refreshes. On power up  
and S3 exit, the BIOS initializes the DDR SDRAM array and sets this bit to a 1. This bit works in  
combination with the RMS bits in controlling Refresh state:  
IC Refresh State  
0
1
OFF  
ON  
28:24  
23:22  
Reserved  
Number of Channels (CHAN): Reflects that GMCH supports only one system memory channel.  
00: One channel is populated appropriately  
Others: Reserved  
21:20  
DDIM DDR SDRAM Data Integrity Mode:  
00: ECC is not supported on this system. Thus, no read-merge-write on partial writes. ECC data  
sense-amps are disabled and the data output is tristate (Default).  
XX: Reserved  
19:16  
15  
Reserved  
RAS Lock-Out Enable: Set to a 1 if all populated rows support RAS Lock-Out. Defaults to 0.  
If this bit is set to a 1 the DDR SDRAM Controller assumes that the DDR SDRAM guarantees  
tRAS min before an auto precharge (AP) completes (Note: An AP is sent with a Read or a Write  
command). Also, the DDR SDRAM Controller does not issue an activate command to the auto pre-  
charged bank for tRP.  
If this bit is set to a 0 the DDR SDRAM Controller does not schedule an AP if tRAS min is not met.  
14:13  
12  
Reserved  
Address Tri-state enable (ADRTRIEN): When set to a 1, the SDRAM Controller will tri-state the  
MA, CMD, and CS# (only when all CKEs are deasserted). Note that when CKE to a row is  
deasserted, fast chip select assertion is not permitted by the hardware. CKEs deassert based on  
Idle Timer and/or max row count control.  
0: Address Tri-state Disabled  
1: Address Tri-state Enabled  
11:10  
Reserved  
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Intel 82854 Graphics Memory Controller Hub (GMCH)  
9:7  
Refresh Mode Select (RMS): This field determines whether Refresh is enabled and, if so, at what  
rate Refreshes will be executed.  
000:  
001:  
010:  
011:  
111:  
Refresh disabled  
Refresh enabled. Refresh interval 15.6 µsec  
Refresh enabled. Refresh interval 7.8 µsec  
Reserved.  
Refresh enabled. Refresh interval 64 clocks (fast refresh mode)  
Other: Reserved  
Any change in the programming of this field Resets the Refresh counter to zero. This function is for  
testing purposes, it allows test program to align refresh events with the test and thus improve  
failure repeatability.  
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Register Description  
6:4  
Mode Select (SMS). These bits select the special operational mode of the DDR SDRAM  
Interface. The special modes are intended for initialization at power up.  
000: Post Reset State – When the GMCH exits Reset (power-up or otherwise), the mode select  
field is cleared to 000. Software is not expected to Write this value, however if this value is Written,  
there are no side effects (no Self Refresh or any other special DDR SDRAM cycle).  
During any Reset sequence, while power is applied and Reset is active, the GMCH deasserts all  
CKE signals. After internal Reset is deasserted, CKE signals remain deasserted until this field is  
written to a value different than 000. On this event, all CKE signals are asserted.  
During Suspend (S3, S4), GMCH internal signal triggers DDR SDRAM Controller to flush pending  
commands and enter all rows into Self-Refresh mode. As part of Resume sequence, GMCH will  
be Reset , which will clear this bit field to 000 and maintain CKE signals deasserted. After internal  
Reset is deasserted, CKE signals remain deasserted until this field is Written to a value different  
than 000. On this event, all CKE signals are asserted.  
During Entry to other low power states (C3, S1-M), GMCH internal signal triggers DDR SDRAM  
Controller to flush pending commands and enter all rows in S1 and relevant rows in C3 (Based on  
RPDNC3) into Self-Refresh mode. During exit to Normal mode, the GMCH signal triggers DDR  
SDRAM Controller to Exit Self-Refresh and Resume Normal operation without S/W involvement.  
001: NOP Command Enable – All CPU cycles to DDR SDRAM result in a NOP command on the  
DDR SDRAM interface.  
010: All Banks Pre-charge Enable – All CPU cycles to DDR SDRAM result in an All Banks  
Precharge command on the DDR SDRAM interface.  
011: Mode Register Set Enable – All CPU cycles to DDR SDRAM result in a Mode Register set  
command on the DDR SDRAM Interface. Host address lines are mapped to DDR SDRAM  
address lines in order to specify the command sent. Host address HA[13:3] are mapped to  
Memory address SMA[11,9:0]. SMA3 must be driven to 1 for interleave wrap type.  
For Double Data Rate  
MA[6:4] needs to be driven based on the value programmed in the CAS# Latency field.  
CAS Latency MA[6:4]  
1.5 Clocks  
2.0 Clocks  
2.5 Clocks  
001  
010  
110  
SMA[7] should always be driven to a 0.  
SMA[8] Should be driven to a 1 for DLL Reset and 1 for Normal Operation.  
SMA[12:9] must be driven to 00000.  
BIOS must calculate and drive the correct host address for each row of Memory such that the  
correct command is driven on the SMA[12:0] lines. Note that SMAB[5,4,2,1]# are inverted from  
SMA[5,4,2,1]; BIOS must account for this.  
100: Extended Mode Register Set Enable – All CPU cycles to DDR SDRAM result in an  
“Extended Mode register set” command on the DDR SDRAM Interface. Host address lines are  
mapped to DDR SDRAM address lines in order to specify the command sent. Host address lines  
are mapped to DDR SDRAM address lines in order to specify the command sent. Host address  
HA[13:3] are mapped to Memory address SMA[11,9:0]. SMA[0] = 0 for DLL enable and 1 for DLL  
disable. All the other SMA lines are driven to 0’s. Note that SMAB[5,4,2,1]# are inverted from  
SMA[5,4,2,1]; BIOS must account for this.  
101: Reserved  
110: CBR Refresh Enable – In this mode all CPU cycles to DDR SDRAM result in a CBR cycle on  
the DDR SDRAM interface  
111: Normal operation  
3:0  
Reserved  
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®
Intel 82854 Graphics Memory Controller Hub (GMCH)  
4.9.17  
DTC – DRAM Throttling Control Register (Device #0)  
Address Offset:  
Default Value:  
Access:  
A0-A3h  
00000000h  
Read/Write/Lock  
32 bits  
Size:  
Throttling is independent for system memory banks, GMCH Writes, and Thermal Sensor Trips.  
Read and Write Bandwidth is measured independently for each bank. If the number of Octal -  
Words (16 bytes) Read/Written during the window defined below (Global DDR SDRAM Sampling  
Window: GDSW) exceeds the DDR SDRAM Bandwidth Threshold, then the DDR SDRAM  
Throttling mechanism will be invoked to limit DDR SDRAM Reads/Writes to a lower bandwidth  
checked over smaller time windows. The throttling will be active for the remainder of the current  
GDSW and for the next GDSW after which it will return to Non-Throttling mode. The throttling  
mechanism accounts for the actual bandwidth consumed during the sampling window, by reducing  
the allowed bandwidth within the smaller throttling window based on the bandwidth consumed  
during the sampling period. Although bandwidth from/to independent rows and GMCH Write  
bandwidth is measured independently, once Tripped all transactions except high priority graphics  
Reads are subject to throttling.  
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Register Description  
Bit  
Description  
31:28  
DDR SDRAM Throttle Mode (TMODE):  
Four bits control which mechanisms for Throttling are enabled in an “OR” fashion. Counter-  
based Throttling is lower priority than Thermal Trips Throttling when both are enabled and  
Tripped. Counter-based trips point Throttling values and Thermal-based Trip Point Throttling  
values are specified in this register.  
If the counter and thermal mechanisms for either Rank or GMCH are both enabled, Throttle  
settings for the one that Trips first is used until the end of the second gdsw.  
[Rank Counter, GMCH Write Counter, Rank Thermal Sensor, GMCH Thermal Sensor]  
0000 = Throttling turned off. This is the default setting. All Counters are off.  
0001 = Only GMCH Thermal Sensor based Throttling is enabled. If GMCH Thermal Sensor is  
Tripped, Write Throttling begins based on the setting in WTTC.  
0010 = Only Rank Thermal Sensor based Throttling is enabled. When the external SO-DIMM  
Thermal sensor is Tripped, DDR SDRAM Throttling begins based on the setting in RTTC.  
0011 = Both Rank and GMCH Thermal Sensor based throttling is enabled. When the external  
SO-DIMM Thermal Sensor is Tripped DDR SDRAM Throttling begins based on the setting in  
RTTC. If the GMCH Thermal Sensor is Tripped, Write Throttling begins based on the setting in  
WTTC.  
0100 = Only the GMCH Write Counter mechanism is enabled. When the length of write  
transfers programmed (GDSW * WCTC) is reached, DRAM throttling begins based on the  
setting in WCTC..  
0101 = GMCH Thermal Sensor and GMCH Write DDR SDRAM Counter mechanisms are both  
enabled. If the GMCH Write DDR SDRAM Counter mechanism threshold is reached, DDR  
SDRAM Throttling begins based on the setting in WCTC. If the GMCH Thermal Sensor is  
tripped, DDR SDRAM Throttling begins based on the setting in WTTC. If both threshold  
mechanisms are tripped, the DDR SDRAM Throttling begins based on the settings in WTTC.  
0110 = Rank Thermal Sensor and GMCH Write DDR SDRAM Counter mechanisms are both  
enabled. If the GMCH Write DDR SDRAM Counter mechanism threshold is reached, DDR  
SDRAM Throttling begins based on setting in WCTC. If the external SO-DIMM Thermal Sensor  
is tripped, Rank DDR SDRAM throttling begins based on the setting in RTTC.  
0111 = Similar to 0101 for Writes and when the Rank Thermal Sensor is tripped, DDR SDRAM  
Throttling begins based on the setting in RTTC.  
1000 = Only Rank Counter mechanism is enabled. When the length of read transfers  
programmed (GDSW * RCTC) is reached, DRAM throttling begins based on the setting in  
RCTC  
1001 = Rank Counter mechanism is enabled and GMCH Thermal Sensor based throttling are  
both enabled. If GMCH thermal sensor is tripped, write throttling begins based on the setting in  
WTTC. If the rank counter mechanism is tripped, DRAM throttling begins based on the setting  
in RCTC.  
1010 = Rank Thermal Sensor and Rank DDR SDRAM Counter mechanisms are both enabled.  
If the rank DDR SDRAM Counter mechanism threshold is reached, DDR SDRAM Throttling  
begins based on the setting in RCTC. If the external SO-DIMM Thermal Sensor is tripped,  
DRAM Throttling begins based on the setting in RTTC.  
1011 = Similar to 1010 and if the GMCH Thermal Sensor is tripped, Write Throttling begins  
based on the setting in WTTC.  
1111 = Rank and GMCH Thermal Sensor based Throttling and Rank and GMCH Write Counter  
based Throttling are enabled. If both the Write Counter and GMCH Thermal Sensor based  
mechanisms are tripped, DDR SDRAM Throttling begins based on the setting allowed in WTTC.  
If both the Rank Counter and Rank Thermal Sensor based mechanisms are tripped, DDR  
SDRAM Throttling begins based on the setting allowed in RTTC.  
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®
Intel 82854 Graphics Memory Controller Hub (GMCH)  
27:24  
23:20  
19:16  
Read Counter Based Power Throttle Control (RCTC): These bits select the Counter based  
Power Throttle Bandwidth Limits for Read operations to system memory.  
R/W, RO if Throttle Lock.  
0h = 85%  
1h = 70%  
2h = 65%  
3h = 60%  
4h = 55%  
5h = 50%  
6h = 45%  
7h = 40%  
8h = 35%  
9h = 30%  
Ah = 20%  
B-Fh = Reserved  
Write Counter Based Power Throttle Control (WCTC): These bits select the counter based  
Power Throttle Bandwidth Limits for Write operations to system memory.  
R/W, RO if Throttle Lock  
0h = 85%  
1h = 70%  
2h = 65%  
3h = 60%  
4h = 55%  
5h = 50%  
6h = 45%  
7h = 40%  
8h = 35%  
9h = 30%  
Ah = 20%  
B-Fh = Reserved  
Read Thermal Based Power Throttle Control (RTTC): These bits select the Thermal Sensor  
based Power Throttle Bandwidth Limits for Read operations to system memory.  
R/W, RO if Throttle Lock.  
0h = 85%  
1h = 70%  
2h = 65%  
3h = 60%  
4h = 55%  
5h = 50%  
6h = 45%  
7h = 40%  
8h = 35%  
9h = 30%  
Ah = 20%  
B-Fh = Reserved  
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Register Description  
15:12  
Write Thermal Based Power Throttle Control (WTTC): These bits select the Thermal based  
Power Throttle Bandwidth Limits for Write operations to system memory.  
R/W, RO if Throttle Lock  
0h = 85%  
1h = 70%  
2h = 65%  
3h = 60%  
4h = 55%  
5h = 50%  
6h = 45%  
7h = 40%  
8h = 35%  
9h = 30%  
Ah = 20%  
B-Fh = Reserved  
11  
10  
Counter Based Throttle Lock (CTLOCK): This bit secures RCTC and WCTC. This bit defaults  
to 0. Once a 1 is written to this bit, RCTC and WCTC (including CTLOCK) become Read-Only.  
Thermal Throttle Lock (TTLOCK): This bit secures the DDR SDRAM Throttling Control  
register. This bit defaults to 0. Once a 1 is written to this bit, all of the configuration register bits  
in DTC (including TTLOCK) except CTLOCK, RCTC and WCTC become Read-Only.  
9
8
Thermal Power Throttle Control fields Enable:  
0 = RTTC and WTTC are not used. RCTC and WTCT are used for both Counter and Thermal  
based Throttling.  
1 = RTTC and WTTC are used for Thermal based Throttling.  
High Priority Stream Throttling Enable:  
Normally High Priority Streams are not Throttled when either the counter based mechanism or  
Thermal Sensor mechanism demands Throttling.  
0 = Normal operation.  
1 = Block High priority streams during Throttling.  
7:0  
Global DDR SDRAM Sampling Window (GDSW): This 8-bit value is multiplied by 4 to define  
the length of time in milliseconds (0–1020) over which the number of Octal Words (16 bytes)  
Read/Written is counted and Throttling is imposed. Note that programming this field to 00h  
disables system memory throttling.  
Recommended values are between 0.25 and 0.75 seconds.  
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Intel 82854 Graphics Memory Controller Hub (GMCH)  
4.10  
Intel 854 GMCH Configuration Process Registers (Device  
#0, Function #3)  
summarizes all Device#0, Function #3 registers.  
Table 23.  
Configuration Process Configuration Space (Device#0, Function #3)  
Register  
Symbol  
Register  
Start  
Register  
End  
Register Name  
Default Value  
Access  
Vendor Identification  
Device Identification  
PCI Command  
VID  
DID  
00  
02  
04  
06  
08  
0A  
0B  
0E  
2C  
2E  
34  
C0  
01  
03  
05  
07  
08  
0A  
0B  
0E  
2D  
2F  
34  
C1  
8086h  
358Ch  
0006h  
0080h  
02h  
RO  
RO  
PCICMD  
PCISTS  
RID  
RO,R/W  
RO,R/WC  
RO  
PCI Status  
Revision Identification  
Sub-Class Code  
SUBC  
BCC  
80h  
RO  
Base Class Code  
08h  
RO  
Header Type  
HDR  
80h  
RO  
Subsystem Vendor Identification  
Subsystem Identification  
Capabilities Pointer  
HPLL Clock Control  
SVID  
0000h  
0000h  
00h  
R/WO  
R/WO  
RO  
SID  
CAPPTR  
HPLLCC  
00h  
RO  
4.10.1  
VID – Vendor Identification Register  
Address Offset:  
Default Value:  
Access:  
00-01h  
8086h  
Read Only  
16 bits  
Size:  
The VID Register contains the vendor identification number. This 16-bit register combined with  
the Device Identification register uniquely identifies any PCI device. Writes to this register have no  
effect.  
Bit  
Descriptions  
15:0  
Vendor Identification (VID): This register field contains the PCI standard identification for  
8086h.  
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Register Description  
4.10.2  
DID – Device Identification Register  
Address Offset:  
Default Value:  
Access:  
02-03h  
358Ch  
Read Only  
16 bits  
Size:  
This 16-bit register combined with the Vendor Identification register uniquely identifies any PCI  
device. Writes to this register have no effect.  
Bit  
Descriptions  
15:0  
Device Identification Number (DID): This is a 16-bit value assigned to the Intel 854 GMCH  
Host-HI Bridge Function #3 (358Ch).  
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®
Intel 82854 Graphics Memory Controller Hub (GMCH)  
4.10.3  
PCICMD – PCI Command Register  
Address Offset:  
Default Value:  
Access:  
04-05h  
0006h  
Read Only, Read/Write  
16 bits  
Size:  
®
Since the Intel 82854 GMCH Device #0 does not physically reside on PCI_A many of the bits are  
not implemented.  
Bit  
Descriptions  
Reserved  
15:10  
9
Fast Back-to-Back Enable (FB2B): This bit controls whether or not the master can do fast back-  
to-back Write. Since Device #0 is strictly a target, this bit is not implemented and is hardwired to  
0. Writes to this bit position have no effect.  
8
7
6
5
4
SERR Enable (SERRE): SERR# is not implemented by Function #1 of Device #0 of the GMCH  
and this bit is hardwired to 0. Writes to this bit position have no effect.  
Address/Data Stepping Enable (ADSTEP): Address/data stepping is not implemented in the  
GMCH, and this bit is hardwired to 0. Writes to this bit position have no effect.  
Parity Error Enable (PERRE): PERR# is not implemented by GMCH and this bit is hardwired to  
0. Writes to this bit position have no effect.  
VGA Palette Snoop Enable (VGASNOOP): The GMCH does not implement this bit and it is  
hardwired to a 0. Writes to this bit position have no effect.  
Memory Write and Invalidate Enable (MWIE): The GMCH will never issue Memory Write and  
Invalidate commands. This bit is therefore hardwired to 0. Writes to this bit position will have no  
effect.  
3
2
1
0
Special Cycle Enable (SCE): The GMCH does not implement this bit and it is hardwired to a 0.  
Writes to this bit position have no effect.  
Bus Master Enable (BME): The GMCH is always enabled as a master on HI. This bit is  
hardwired to a 1. Writes to this bit position have no effect.  
Memory Access Enable (MAE): The GMCH always allows access to Main Memory. This bit is  
not implemented and is hardwired to 1. Writes to this bit position have no effect.  
I/O Access Enable (IOAE): This bit is not implemented in the GMCH and is hardwired to a 0.  
Writes to this bit position have no effect.  
94  
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Register Description  
4.10.4  
PCISTS – PCI Status Register  
Address Offset:  
Default Value:  
Access:  
06-07h  
0080h  
Read Only, Read/Write Clear  
16 bits  
Size:  
PCISTS is a 16-bit status register that reports the occurrence of error events on Device #0's PCI  
Interface. Bit 14 is Read/Write clear. All other bits are Read Only. Since GMCH Device #0 does  
not physically reside on PCI_A many of the bits are not implemented.  
Bit  
Descriptions  
15  
Detected Parity Error (DPE): The GMCH does not implement this bit and it is hardwired to a 0.  
Writes to this bit position have no effect.  
14  
Signaled System Error (SSE): The GMCH does not implement this bit and it is hardwired to a 0.  
Writes to this bit position have no effect.  
13  
Received Master Abort Status (RMAS): The GMCH does not implement this bit and it is  
hardwired to a 0. Writes to this bit position have no effect.  
12  
Received Target Abort Status (RTAS): The GMCH does not implement this bit and it is  
hardwired to a 0. Writes to this bit position have no effect.  
11  
Signaled Target Abort Status (STAS): The GMCH does not implement this bit and it is  
hardwired to a 0. Writes to this bit position have no effect.  
10:9  
DEVSEL Timing (DEVT): These bits are hardwired to "00". Writes to these bit positions have no  
affect. Device #0 does not physically connect to PCI_A. These bits are set to "00" (fast decode)  
so that the GMCH does not limit optimum DEVSEL timing for PCI_A.  
8
7
Master Data Parity Error Detected (DPD): The GMCH does not implement this bit and it is  
hardwired to a 0. Writes to this bit position have no effect.  
Fast Back-to-Back (FB2B): This bit is hardwired to 1. Writes to these bit positions have no  
effect. Device #0 does not physically connect to PCI_A. This bit is set to 1 (indicating fast back-to-  
back capability) so that the GMCH does not limit the optimum setting for PCI_A.  
6:5  
4
Reserved  
Capability List (CLIST): This bit is hardwired to 0 to indicate to the configuration software that  
this device/function does not implement new capabilities.  
3:0  
Reserved  
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Intel 82854 Graphics Memory Controller Hub (GMCH)  
4.10.5  
4.10.6  
4.10.7  
RID – Revision Identification Register  
Address Offset:  
Default Value:  
Access:  
08h  
02h  
Read Only  
8 bits  
Size:  
®
This register contains the revision number of the Intel 82854 GMCH. These bits are Read Only  
and Writes to this register have no effect.  
Bit  
Descriptions  
7:0  
Revision Identification Number (RID): This is an 8-bit value that indicates the revision  
identification number for the GMCH.  
SUBC – Sub-Class Code Register  
Address Offset:  
Default Value:  
Access:  
0Ah  
80h  
Read Only  
8 bits  
Size:  
®
This register contains the Sub-Class Code for the Intel 82854 GMCH Device #0. This code is 80h  
indicating a peripheral device.  
Bit  
Descriptions  
7:0  
Sub-Class Code (SUBC): This is an 8-bit value that indicates the category of Bridge into which  
GMCH falls. The code is 80h indicating other peripheral device.  
BCC – Base Class Code Register  
Address Offset:  
Default Value:  
Access:  
0Bh  
08h  
Read Only  
8 bits  
Size:  
®
This register contains the Base Class Code of the Intel 82854 GMCH Device #0 Function #3.  
This code is 08h indicating a peripheral device.  
Bit  
Descriptions  
7:0  
Base Class Code (BASEC): This is an 8-bit value that indicates the Base Class code for the  
GMCH. This code has the value 08h, indicating other peripheral device.  
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Register Description  
4.10.8  
HDR – Header Type Register  
Address Offset:  
Default Value:  
Access:  
0Eh  
80h  
Read Only  
8 bits  
Size:  
This register identifies the header layout of the configuration space. No physical register exists at  
this location.  
Bit  
Descriptions  
7:0  
PCI Header (HDR): This field always returns 80 to indicate that Device #0 is a multifunction  
device. If Functions other than #0 are disabled this field returns a 00 to indicate that the GMCH is  
a single function device with standard header layout. The default is 80 Reads and Writes to this  
location have no effect.  
4.10.9  
SVID – Subsystem Vendor Identification Register  
Address Offset:  
Default Value:  
Access:  
2C-2Dh  
0000h  
Read/Write Once  
16 bits  
Size:  
This value is used to identify the vendor of the subsystem.  
Bit  
Descriptions  
15:0  
Subsystem Vendor ID (SUBVID): This field should be programmed during boot-up to indicate  
the vendor of the system board. After it has been Written once, it becomes Read Only.  
4.10.10  
ID – Subsystem Identification Register  
Address Offset:  
Default Value:  
Access:  
2E-2Fh  
0000h  
Read/Write Once  
16 bits  
Size:  
This value is used to identify a particular subsystem.  
Bit  
Descriptions  
7:0  
Subsystem ID (SUBID): This field should be programmed during BIOS initialization. After it has  
been Written once, it becomes Read Only.  
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®
Intel 82854 Graphics Memory Controller Hub (GMCH)  
4.10.11  
CAPPTR – Capabilities Pointer Register  
Address Offset:  
Default Value:  
Access:  
34h  
00h  
Read Only  
8 bits  
Size:  
The CAPPTR provides the offset that is the pointer to the location of the first device capability in  
the capability list.  
Bit  
Descriptions  
7:0  
Pointer to the offset of the first capability ID register block: In this case there are no  
capabilities therefore these bits are hardwired to 00h to indicate the end of the capability-linked  
list.  
4.10.12  
HPLLCC – HPLL Clock Control Register (Device #0)  
Address Offset:  
Default Value:  
Access:  
C0-C1h  
00h  
Read Only  
16 bits  
Size:  
Bit  
Descriptions  
15:11  
10  
Reserved  
HPLL VCO Change Sequence Initiate Bit:  
Software must Write a 0 to clear this bit and then Write a 1 to initiate sequence again.  
9
Hphase Reset Bit:  
1 = Assert  
0 = Deassert (default)  
8
Reserved  
Reserved  
7:2  
1:0  
HPLL Clock Control:  
Software is allowed to update this register.  
See Table 24.  
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Register Description  
®
Table 24.  
Intel 82854 GMCH Configurations and Some Resolution Examples: Native  
Graphics Mode  
Straps Read  
Through  
HPLLCC[2:0]:  
D0:F3:Register  
Offset C0-C1h,  
bits[2:0]  
GFX Core  
Clock(Low)  
GFX Core  
System  
Memory  
Frequency  
FSB  
Rate  
DVO Port  
CRT Port  
Clock (High)  
000  
111  
400  
MHz  
266 MHz  
333 MHz  
200 MHz  
1600x1200@85 Hz  
DCLK = 229- MHz  
1600x1200@85-Hz  
DCLK = 229 -MHz  
2048x1536@72 Hz  
DCLK = 324 MHz  
2048x1536@75 Hz  
DCLK = 340 MHz  
400  
MHz  
250 MHz  
1600x1200@85 Hz  
DCLK = 229 MHz  
1600x1200@85 Hz  
DCLK = 229 MHz  
2048x1536@72 Hz  
DCLK = 324 MHz  
2048x1536@75 Hz  
DCLK = 340 MHz  
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Intel 82854 Graphics Memory Controller Hub (GMCH)  
4.11  
Intel® 82854 GMCH Integrated Graphics Device Registers  
(Device #2, Function #0)  
This section contains the PCI configuration registers listed in order of ascending offset address.  
Device #2 incorporates Function #0. See “Nomenclature for Access Attributes” on page 42 for  
access nomenclature.  
Note: C0F0 = Copy of Function #0 and U1F1 = Unique in Function #1.  
Table 25.  
Integrated Graphics Device Configuration Space (Device #2, Function#0)  
Register  
Symbol  
Address  
Offset  
Register  
End  
Default  
Value  
Regs in  
Function#1  
Register Name  
Access  
Vendor Identification  
Device Identification  
PCI Command  
VID  
DID  
00h  
02h  
04h  
06h  
08h  
09h  
0Ch  
0Dh  
0Eh  
10h  
01h  
03h  
05h  
07h  
08h  
0Bh  
0Ch  
0Dh  
0Eh  
13h  
8086h  
358Eh  
0000h  
0090h  
02h  
RO  
RO  
C0F0  
C0F0  
U1F1  
U1F1  
C0F0  
U1F1  
C0F0  
C0F0  
C0F0  
U1F1  
PCICMD  
PCISTS  
RID  
RO,R/W  
RO  
PCI Status  
Revision Identification  
Class Code  
RO  
CC  
030000h  
00h  
RO  
Cache Line Size  
Master Latency Timer  
Header Type  
CLS  
RO  
MLT  
00h  
RO  
HDR  
00h  
RO  
Graphics Memory  
Range Address  
GMADR  
00000008h  
RO,R/W  
Memory Mapped Range  
Address  
MMADR  
14h  
17h  
00000000h  
RO,R/W  
U1F1  
IO Range  
IOBAR  
SVID  
18h  
2Ch  
2Eh  
30h  
1Bh  
2Dh  
2Fh  
33h  
00000001h  
0000h  
RO,R/W  
R/WO  
R/ WO  
RO  
Subsystem Vendor ID  
Subsystem ID  
C0F0  
C0F0  
C0F0  
SID  
0000h  
Video Bios ROM Base  
Address  
ROMADR  
00000000h  
Interrupt Line  
Interrupt Pin  
INTRLINE  
INTRPIN  
3Ch  
3Dh  
3Ch  
3Dh  
00h  
01h  
RO in F#1,  
R/W  
RO, Reserved  
In F#1  
Minimum Grant  
MINGNT  
MAXLAT  
PMCAP  
3Eh  
3Fh  
D2h  
3Eh  
3Fh  
D3h  
00h  
00h  
RO  
RO  
RO  
C0F0  
C0F0  
C0F0  
Maximum Latency  
Power Management  
Capabilities  
0221h  
Power Management  
Control  
PMCS  
D4h  
D5h  
0000h  
RO,R/W  
U1F1  
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Register Description  
4.11.1  
VID – Vendor Identification Register (Device #2)  
Address Offset:  
Default Value:  
Access:  
00-01h  
8086h  
Read Only  
16 bits  
Size:  
The VID Register contains the vendor identification number. This 16-bit register combined with  
the Device Identification Register uniquely identifies any PCI device. Writes to this register have  
no effect.  
Bit  
Description  
15:0  
Vendor Identification Number: This is a 16-bit value assigned to Intel.  
4.11.2  
DID – Device Identification Register (Device #2)  
Address Offset:  
Default Value:  
Access:  
02-03h  
358Eh  
Read Only  
16 bits  
Size:  
This 16-bit register combined with the Vendor Identification register uniquely identifies any PCI  
device. Writes to this register have no effect.  
Bit  
Description  
15:0  
Device Identification Number: This is a 16-bit value assigned to the GMCH IGD (358Eh).  
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Intel 82854 Graphics Memory Controller Hub (GMCH)  
4.11.3  
PCICMD – PCI Command Register (Device #2)  
Address Offset:  
Default Value:  
Access:  
04-05h  
0000h  
Read Only, Read/Write  
16 bits  
Size:  
This 16-bit register provides basic control over the IGD's ability to respond to PCI cycles. The  
PCICMD register in the IGD disables the IGD PCI compliant master accesses to main system  
memory.  
Bit  
Description  
15:10  
Reserved  
9
8
7
6
5
4
3
2
Fast Back-to-Back (FB2B)–RO  
SERR# Enable (SERRE) –RO  
Address/Data Stepping–RO  
Parity Error Enable (PERRE) –RO  
Video Palette Snooping (VPS) –RO  
Memory Write and Invalidate Enable (MWIE) –RO  
Special Cycle Enable (SCE) –RO  
Bus Master Enable (BME) –R/W: This bit determines if the IGD is to function as a PCI compliant  
master.  
0= Disable IGD bus mastering (default).  
1 = Enable IGD bus mastering.  
1
0
Memory Access Enable (MAE) –R/W: This bit controls the IGD’s response to System Memory  
Space accesses.  
0= Disable (default).  
1 = Enable.  
I/O Access Enable (IOAE) –R/W: This bit controls the IGD’s response to I/O Space accesses.  
0 = Disable (default).  
1 = Enable.  
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Register Description  
4.11.4  
PCISTS – PCI Status Register (Device #2)  
Address Offset:  
Default Value:  
Access:  
06-07h  
0090h  
Read Only  
16 bits  
Size:  
PCISTS is a 16-bit status register that reports the occurrence of a PCI compliant master abort and  
PCI compliant target abort. PCISTS also indicates the DEVSEL# timing that has been set by the  
IGD.  
Bit  
Description  
15  
14  
13  
12  
11  
10:9  
8
Detected Parity Error (DPE): Since the IGD does not detect parity, this bit is always set to 0.  
Signaled System Error (SSE) – RO  
Received Master Abort Status (RMAS) – RO  
Received Target Abort Status (RTAS) – RO  
Signaled Target Abort Status (STAS) – RO  
DEVSEL# Timing (DEVT) – RO  
Data Parity Detected (DPD) – RO  
7
Fast Back-to-Back (FB2B) – RO  
6
User Defined Format (UDF) – RO  
5
66-MHz PCI Capable (66C) – RO  
4
CAP LIST: This bit is set to 1 to indicate that the register at 34h provides an offset into the  
Function’s PCI Configuration Space containing a pointer to the location of the first item in the list.  
3:0  
Reserved  
4.11.5  
RID – Revision Identification Register (Device #2)  
Address Offset:  
Default Value:  
Access:  
08h  
02h  
Read Only  
8 bits  
Size:  
This register contains the revision number of the IGD. These bits are Read Only and Writes to this  
register have no effect.  
Bit  
Description  
7:0  
Revision Identification Number: This is an 8-bit value that indicates the revision identification  
number for the GMCH.  
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Intel 82854 Graphics Memory Controller Hub (GMCH)  
4.11.6  
CC – Class Code Register (Device #2)  
Address Offset:  
Default Value:  
Access:  
09-0Bh  
030000h  
Read Only  
24 bits  
Size:  
This register contains the device programming interface information related to the Sub-Class code  
and Base Class code definition for the IGD. This register also contains the Base Class code and the  
function sub-class in relation to the Base Class code.  
Bit  
Description  
23:16  
15:8  
Base Class Code (BASEC): 03=Display controller  
Sub-Class Code (SCC):  
Function 0: 00h=VGA compatible or 80h=Non VGA  
Function 1: 80h=Non VGA  
7:0  
Programming Interface (PI): 00h=Hardwired as a Display controller.  
4.11.7  
CLS – Cache Line Size Register (Device #2)  
Address Offset:  
Default Value:  
Access:  
0Ch  
00h  
Read Only  
8 bits  
Size:  
The IGD does not support this register as a PCI slave.  
Bit  
Description  
7:0  
Cache Line Size (CLS) – RO  
4.11.8  
MLT – Master Latency Timer Register (Device #2)  
Address Offset:  
Default Value:  
Access:  
0Dh  
00h  
Read Only  
8 bits  
Size:  
The IGD does not support the programmability of the master latency timer because it does not  
perform bursts.  
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Register Description  
Bit  
Description  
7:0  
Master Latency Timer Count Value – RO  
4.11.9  
HDR – Header Type Register (Device #2)  
Address Offset:  
Default Value:  
Access:  
0Eh  
00h  
Read Only  
8 bits  
Size:  
This register contains the Header Type of the IGD.  
Bit  
Description  
7
Multi Function Status (MFunc): Indicates if the device is a multi-function device.  
6:0  
Header Code (H): This is a 7-bit value that indicates the Header code for the IGD. This code has  
the value 00h, indicating a type 0 configuration space format.  
4.11.10  
GMADR – Graphics Memory Range Address Register (Device #2)  
Address Offset:  
Default Value:  
Access:  
10-13h  
00000008h  
Read/Write, Read Only  
32 bits  
Size:  
IGD graphics system memory base address is specified in this register.  
Bit  
Description  
31:27  
26  
Memory Base Address–R/W: Set by the OS, these bits correspond to address signals [31:26].  
128-MB Address Mask – RO: 0 indicates 128-MB address  
Address Mask–RO: Indicates (at least) a 32-MB address range.  
Prefetchable Memory–RO: Enable prefetching.  
25:4  
3
2:1  
0
Memory Type–RO: Indicates 32-bit address.  
Memory/IO Space–RO: Indicates System Memory Space.  
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Intel 82854 Graphics Memory Controller Hub (GMCH)  
4.11.11  
MMADR – Memory Mapped Range Address Register (Device #2)  
Address Offset:  
Default Value:  
Access:  
14-17h  
00000000h  
Read/Write, Read Only  
32 bits  
Size:  
This register requests allocation for the IGD registers and instruction ports. The allocation is for  
512-kB and the base address is defined by bits [31:19].  
Bit  
Description  
31:19  
18:4  
3
Memory Base Address–R/W: Set by the OS, these bits correspond to address signals [31:19].  
Address Mask–RO: Indicate 512-kB address range.  
Prefetchable Memory–RO: Prevents prefetching.  
2:1  
0
Memory Type–RO: Indicates 32-bit address.  
Memory / IO Space–RO: Indicates System Memory space.  
4.11.12  
IOBAR – I/O Base Address Register (Device #2)  
Address Offset:  
Default Value:  
Access:  
18-1Bh  
00000001h  
Read/Write  
32 bits  
Size:  
This register provides the Base offset of the I/O registers within Device #2. Bits 15:3 are  
programmable allowing the I/O Base to be located anywhere in 16-bit I/O Address Space. Bits 2:1  
are fixed and return zero, bit 0 is hardwired to a one indicating that 8-bytes of I/O space are  
decoded.  
Access to the 8Bs of IO space is allowed in PM state D0 when IO Enable (PCICMD bit 0) set.  
Access is disallowed in PM states D1-D3 or if IO Enable is clear or if Device #2 is turned off or if  
internal graphics is disabled. Note that access to this IO BAR is independent of VGA functionality  
within Device #2. Also note that this mechanism is available only through Function #0 of  
Device#2 and is not duplicated in Function #1.  
If accesses to this I/O bar are allowed, then the GMCH claims all 8-bit, 16-bit, or 32-bit I/O cycles  
from the CPU that falls within the 8B claimed.  
Bit  
Description  
31:16  
15:3  
2:1  
Reserved  
IO Base Address–R/W: Set by the OS, these bits correspond to address signals [15:3].  
Memory Type–RO: Indicates 32-bit address.  
0
Memory / IO Space–RO  
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Register Description  
4.11.13  
4.11.14  
4.11.15  
SVID – Subsystem Vendor Identification Register (Device #2)  
Address Offset:  
Default Value:  
Access:  
2C-2Dh  
0000h  
Read/Write Once  
16 bits  
Size:  
Bit  
Description  
15:0  
Subsystem Vendor ID: This value is used to identify the vendor of the subsystem. This register  
should be programmed by BIOS during boot-up. Once written, this register becomes Read Only.  
This register can only be cleared by a reset.  
SID – Subsystem Identification Register (Device #2)  
Address Offset:  
Default Value:  
Access:  
2E-2Fh  
0000h  
Read/Write Once  
16 bits  
Size:  
Bit  
Description  
15:0  
Subsystem Identification: This value is used to identify a particular subsystem. This field should  
be programmed by BIOS during boot-up. Once written, this register becomes Read Only. This  
register can only be cleared by a reset.  
ROMADR – Video BIOS ROM Base Address Registers (Device #2)  
Address Offset:  
Default Value:  
Access:  
30-33h  
00000000h  
Read Only  
32 bits  
Size:  
The IGD does not use a separate BIOS ROM, therefore this register is hardwired to 0's.  
Bit  
Description  
31:18  
17:11  
10:1  
0
ROM Base Address–RO  
Address Mask–RO: Indicates 256-kB address range.  
Reserved  
ROM BIOS Enable–RO: Indicates ROM not accessible.  
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Intel 82854 Graphics Memory Controller Hub (GMCH)  
4.11.16  
INTRLINE – Interrupt Line Register (Device #2)  
Address Offset:  
Default Value:  
Access:  
3Ch  
00h  
Read/Write  
8 bits  
Size:  
Bit  
Description  
7:0  
Interrupt Connection: Used to communicate interrupt line routing information. POST software  
Writes the routing information into this register as it initializes and configures the system. The value  
in this register indicates which input of the System Interrupt controller that the device’s interrupt pin  
is connected to.  
4.11.17  
INTRPIN – Interrupt Pin Register (Device #2)  
Address Offset:  
Default Value:  
Access:  
3Dh  
01h  
Read Only  
8 bits  
Size:  
Bit  
Description  
7:0  
Interrupt Pin: As a single function device, the IGD specifies INTA# as its interrupt pin. 01h=INTA#.  
For Function #1, this register is set to 00h.  
4.11.18  
MINGNT – Minimum Grant Register (Device #2)  
Address Offset:  
Default Value:  
Access:  
3Eh  
00h  
Read Only  
8 bits  
Size:  
Bit  
Description  
7:0  
Minimum Grant Value: The IGD does not burst as a PCI compliant master.  
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Register Description  
4.11.19  
MAXLAT – Maximum Latency Register (Device #2)  
Address Offset:  
Default Value:  
Access:  
3Fh  
00h  
Read Only  
8 bits  
Size:  
Bit  
Description  
7:0  
Maximum Latency Value: Bits[7:0]=00h. The IGD has no specific requirements for how often it  
needs to access the PCI bus.  
4.11.20  
PMCAP – Power Management Capabilities Register (Device #2)  
Address Offset:  
Default Value:  
Access:  
D2-D3h  
0221h  
Read Only  
16 bits  
Size:  
Bit  
Description  
15:11  
PME Support: This field indicates the power states in which the IGD may assert PME#. Hardwired  
to 0 to indicate that the IGD does not assert the PME# signal.  
10:6  
5
Reserved  
Device Specific Initialization (DSI): Hardwired to 1 to indicate that special initialization of the IGD  
is required before generic class device driver is to use it.  
4
Auxiliary Power Source: Hardwired to 0.  
3
PME Clock: Hardwired to 0 to indicate IGD does not support PME# generation.  
2:0  
Version: Hardwired to 001b to indicate there are 4 bytes of power management registers  
implemented.  
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Intel 82854 Graphics Memory Controller Hub (GMCH)  
4.11.21  
PMCS – Power Management Control/Status Register (Device #2)  
Address Offset:  
Default Value:  
Access:  
D4-D5h  
0000h  
Read/Write, Read Only  
16 bits  
Size:  
Bit  
Description  
15  
PME_Status –RO: This bit is 0 to indicate that IGD does not support PME# generation from D3  
(cold).  
14:9  
8
Reserved  
PME_En–RO: This bit is 0 to indicate that PME# assertion from D3 (cold) is disabled.  
7:2  
1:0  
Reserved  
PowerState–R/W: This field indicates the current power state of the IGD and can be used to set  
the IGD into a new power state. If software attempts to Write an unsupported state to this field,  
Write operation must complete normally on the bus, but the data is discarded and no state change  
occurs.  
On a transition from D3 to D0 the graphics controller is optionally Reset to initial values.  
Bits[1:0] Power State  
00  
01  
10  
11  
D0 Default  
D1  
D2 Not Supported  
D3  
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Intel 82854 GMCH System Address Map  
®
5.0  
Intel 82854 GMCH System Address Map  
A system based on the GMCH supports 4 GB of addressable system memory space and 64 kB+3B  
of addressable I/O space. The I/O and system memory spaces are divided by system configuration  
software into regions. The system memory ranges are useful either as system memory or as  
specialized system memory, while the I/O regions are used solely to control the operation of  
devices in the system.  
When the GMCH receives a Write request whose address targets an invalid space, the data is  
ignored. For Reads, the GMCH responds by returning all zeros on the requesting interface.  
5.1  
System Memory Address Ranges  
The GMCH provides a maximum system memory of 2 GB. The GMCH does not remap APIC  
memory space and does not limit DDR SDRAM space in hardware. It is the BIOS or system  
designer's responsibility to limit system memory population so that adequate PCI High BIOS and  
APIC memory space can be allocated. Figure 5 and Figure 6 depict the system memory address  
map in a simplified form and provide details on mapping specific system memory regions as  
defined and supported by the GMCH.  
Figure 5.  
Simplified View of System Address Map  
4 GB  
Graphics  
Memory  
Graphic  
(Local)  
Memory  
Address  
Range  
Top of the  
Main Memory  
Independently  
Programmable  
Main  
Memory  
Address  
Range  
Non-Overlapping  
Memory Windows  
0
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®
Intel 82854 Graphics Memory Controller Hub (GMCH)  
Figure 6.  
Detailed View of System Address Map  
4 GB max  
TOM  
1 MB  
SBIOS  
Upper  
0FFFFFh  
BIOS Area  
(64 kB)  
Extended  
0F0000h  
0EFFFFh  
960 kB  
896 kB  
SBIOS Lower  
PCI Memory  
Range  
BIOS Area ( 64  
kB) 16 kB x 4  
0E0000h  
0DFFFFh  
1 GB  
16 MB  
15 MB  
Expansion  
Card  
BIOS and  
Buffer Area  
(128 kB)  
16 kBx8  
Optional ISA  
Hole  
0C0000h  
0BFFFFh  
Standard 768 kB  
PCI/ISA  
Video  
Memory  
(SMM  
Memory)  
128 kB  
DOS  
Compatibility  
Memory  
1 MB  
DOS  
Compatibility  
Memory  
640 kB  
0A0000h  
09FFFFh  
640 kB  
0 B  
DOS Area  
000000h  
5.2  
DOS Compatibility Area  
This compatibility region is divided into the following address regions:  
0 - 640 kB DOS Area  
640 - 768 kB Video Buffer Area  
768 - 896 kB in 16-kB sections (total of eight sections) - expansion area  
896 -960 kB in 16-kB sections (total of four sections) - extended system BIOS area  
960 kB - 1 MB system BIOS area  
There are 16 system memory segments in the compatibility area. Thirteen of the system memory  
ranges can be enabled or disabled independently for both Read and Write cycles.  
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®
Intel 82854 GMCH System Address Map  
Table 26.  
System Memory Segments and Their Attributes  
System Memory  
Segments  
Attributes  
Comments  
000000H - 09FFFFH  
0A0000H - 0BFFFFH  
0C0000H - 0C3FFFH  
Fixed - always mapped to main  
DDR SDRAM  
0 to 640 kB – DOS Region  
Mapped to Hub interface or IGD  
- configurable as SMM space  
Video Buffer (physical DDR SDRAM  
configurable as SMM space)  
WE(Write Enable) RE (Read  
Enable)  
Add-on BIOS  
0C4000H - 0C7FFFH  
0C8000H - 0CBFFFH  
0CC000H - 0CFFFFH  
0D0000H - 0D3FFFH  
0D4000H - 0D7FFFH  
0D8000H - 0DBFFFH  
0DC000H - 0DFFFFH  
0E0000H - 0E3FFFH  
0E4000H - 0E7FFFH  
0E8000H - 0EBFFFH  
0EC000H - 0EFFFFH  
0F0000H - 0FFFFFH  
WE RE  
WE RE  
WE RE  
WE RE  
WE RE  
WE RE  
WE RE  
WE RE  
WE RE  
WE RE  
WE RE  
WE RE  
Add-on BIOS  
Add-on BIOS  
Add-on BIOS  
Add-on BIOS  
Add-on BIOS  
Add-on BIOS  
Add-on BIOS  
BIOS Extension  
BIOS Extension  
BIOS Extension  
BIOS Extension  
BIOS Area  
DOS Area (000000h-09FFFFh)  
The DOS area is 640 kB in size and is always mapped to the main system memory controlled by  
the GMCH.  
Legacy VGA Ranges (0A0000h-0BFFFFh)  
®
Legacy VGA ranges is accessible when the Intel 82854 GMCH is strapped into Native Graphics  
mode. The legacy 128-kB VGA memory range A0000h-BFFFFh (VGA Frame Buffer) can be  
mapped to IGD (Device #2) and to the Hub interface depending on the programming of the VGA  
steering bits. Priority for VGA mapping is constant in that the GMCH always decodes internally  
mapped devices first. Internal to the GMCH, decode precedence is always given to IGD. The  
GMCH always positively decodes internally mapped devices, namely the IGD. Subsequent  
decoding of regions mapped to the Hub interface depends on the Legacy VGA configurations bits  
(VGA Enable and MDAP). This region is also the default for SMM space.  
Compatible SMRAM Address Range (0A0000h-0BFFFFh)  
When compatible SMM space is enabled, SMM-mode CPU accesses to this range are routed to  
physical DDR SDRAM at this address. Non-SMM-mode CPU accesses to this range are  
considered to be to the video buffer area as described above. Hub interface originated cycles to  
enabled SMM space are not allowed and are considered to be to the video buffer area.  
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Intel 82854 Graphics Memory Controller Hub (GMCH)  
Monochrome Display Adapter (MDA) Range (0B0000h - 0B7FFFh)  
Monochrome Display Adapter ranges is accessible when the Intel® 854 Chipset is strapped into  
Native Graphics mode. Legacy support requires the ability to have a second graphics controller  
(monochrome) in the system. Accesses in the standard VGA range are forwarded to IGD and the  
Hub interface (depending on configuration bits). Since the monochrome adapter may be mapped  
to anyone of these devices, the GMCH must decode cycles in the MDA range and forward them  
either to IGD or to Hub interface. This capability is controlled by a VGA steering bits and the  
legacy configuration bit (MDAP bit). In addition to the system memory range B0000h to B7FFFh,  
the GMCH decodes IO cycles at 3B4h, 3B5h, 3B8h, 3B9h, 3BAh, and 3BFh and forwards them to  
either the IGD or the Hub interface.  
Expansion Area (0C0000h-0DFFFFh)  
This 128-kByte ISA Expansion region is divided into eight, 16-kB segments. Each segment can be  
assigned one of four Read/Write states: read-only, write-only, read/write, or disabled. Typically,  
these blocks are mapped through GMCH and are subtractively decoded to ISA space. System  
memory that is disabled is not remapped.  
Extended System BIOS Area (0E0000h-0EFFFFh)  
This 64-kByte area is divided into four, 16-kB segments. Each segment can be assigned  
independent read and write attributes so it can be mapped either to main DDR SDRAM or to Hub  
interface. Typically, this area is used for RAM or ROM. System memory segments that are  
disabled are not remapped elsewhere.  
System BIOS Area (0F0000h-0FFFFFh)  
This area is a single 64-kB segment. This segment can be assigned Read and Write attributes. It is  
by default (after Reset) Read/Write disabled and cycles are forwarded to Hub interface. By  
manipulating the Read/Write attributes, the GMCH can "shadow" BIOS into the main DDR  
SDRAM. When disabled, this segment is not remapped.  
5.3  
Extended System Memory Area  
This system memory area covers 100000h (1 MB) to FFFFFFFFh (4 GB-1) address range and it is  
divided into the following regions:  
Main system memory from 1 MB to the top of system memory.  
PCI Memory space from the top of system memory to 4 GB with two specific ranges.  
APIC Configuration Space from FEC0_0000h (4 GB-20 MB) to FECF_FFFFh (4 GB-19 MB  
- 1) and FEE0_0000h (4 GB-18 MB) to FEEF_FFFFh (4 GB-17 MB-1).  
High BIOS area from 4 GB to 4 GB - 2 MB  
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Intel 82854 GMCH System Address Map  
5.4  
Main System Memory Address Range (0010_0000h to Top  
of Main Memory)  
The address range from 1 MB to the top of main system memory is mapped to main DDR SDRAM  
address range controlled by the GMCH. The GMCH will forward all accesses to addresses within  
this range to the DDR SDRAM unless a hole in this range is created using the fixed hole as  
controlled by the FDHC register. Accesses within this hole are forwarded to Hub interface.  
The GMCH provides a maximum DDR SDRAM address decode space of 4-GB. The GMCH does  
not remap APIC memory space. The GMCH does not limit DDR SDRAM address space in  
hardware.  
5.4.1  
5.4.2  
15 MB-16 MB Window  
A hole can be created at 15 MB-16 MB as controlled by the fixed hole enable (FDHC register) in  
Device 0 space. Accesses within this hole are forwarded to the Hub interface. The range of  
physical DDR SDRAM disabled by opening the hole is not remapped to the top of the memory –  
that physical DDR SDRAM space is not accessible. This 15 MB-16 MB hole is an optionally  
enabled ISA hole. Video accelerators originally used this hole. Validation and customer SV teams  
also use it for some of their test cards. That is why it is being supported. There is no inherent  
BIOS request for the 15-16 hole.  
Pre-allocated System Memory  
Voids of physical addresses that are not accessible as general system memory and reside within  
system memory address range (< TOM) are created for SMM-mode and legacy VGA graphics  
compatibility. It is the responsibility of BIOS to properly initialize these regions. The number of  
UMA options has been extended. Allocation is at a fixed address in terms of rigid positioning of  
UMA system memory 'TOM-TSEG-UMA(size), but it is mapped at any available address by a PCI  
allocation algorithm. GMADR and MMADR are requested through BARs.  
The following table details the location and attributes of the regions.  
Table 27.  
Table 33. Pre-allocated System Memory  
System Memory Segments  
Attributes  
Comments  
00000000H - 03E7FFFFH  
03E80000H - 03F7FFFFH  
R/W  
R/W  
Available system memory 62.5 -MB  
Pre-allocated Graphics VGA memory  
1-MB (or 4/8/16/32- MB) when IGD is  
enabled  
03F80000H - 03FFFFFFH  
03F80000H - 03FFFFFFH  
SMM Mode Only - CPU Reads  
TSEG Address Range  
SMM Mode Only - CPU Reads TSEG Pre-allocated system memory  
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Intel 82854 Graphics Memory Controller Hub (GMCH)  
5.4.2.1  
5.4.2.2  
Extended SMRAM Address Range (HSEG and TSEG)  
The HSEG and TSEG SMM transaction address spaces reside in this extended system memory  
area.  
HSEG  
SMM mode CPU accesses to enabled HSEG are remapped to 000A0000h-000BFFFFh. Non-SMM  
mode CPU accesses to enabled HSEG are considered invalid are terminated immediately on the  
FSB. The exceptions to this rule are Non-SMM mode Write Back cycles that are remapped to  
SMM space to maintain cache coherency. Hub interface originated cycles to enabled SMM space  
are not allowed. Physical DDR SDRAM behind the HSEG transaction address is not remapped and  
is not accessible.  
5.4.2.3  
TSEG  
TSEG is 1-MB in size and is at the top of physical system memory. SMM mode CPU accesses to  
enabled TSEG access the physical DDR SDRAM at the same address. Non-SMM mode CPU  
accesses to enabled TSEG are considered invalid and are terminated immediately on the FSB. The  
exceptions to this rule are Non-SMM-mode Write Back cycles that are directed to the physical  
SMM space to maintain cache coherency. Hub interface originated cycles that enable SMM space  
are not allowed.  
The size of the SMRAM space is determined by the USMM value in the SMRAM register. When  
the extended SMRAM space is enabled, non-SMM CPU accesses and all other accesses in this  
range are forwarded to the Hub interface. When SMM is enabled the amount of system memory  
available to the system is equal to the amount of physical DDR SDRAM minus the value in the  
TSEG register.  
5.4.2.4  
Dynamic Video Memory Technology (DVMT)  
The IGD supports DVMT in a non-graphics system memory configuration. DVMT is a mechanism  
that manages system memory and the internal graphics device for optimal graphics performance.  
DVMT-enabled software drivers, working with the memory arbiter and the operating system,  
utilize the system memory to support 2D graphics and 3D applications. DVMT dynamically  
responds to application requirements by allocating the proper amount of display and texturing  
memory.  
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Intel 82854 GMCH System Address Map  
5.4.2.5  
PCI Memory Address Range (Top of Main System Memory to 4 GB)  
The address range from the top of main DDR SDRAM to 4-GB (top of physical system memory  
space supported by the GMCH) is normally mapped via the Hub interface to PCI.  
As an internal graphics configuration, there are two exceptions to this rule.  
1. The first exception is addresses decoded to the graphics memory range. One per function in  
device #2.  
2. The second exception is addresses decoded to the system memory mapped range of the  
Internal Graphics device. One per function in device #2. Both exception cases are forwarded to  
the Internal Graphics device.  
There are two sub-ranges within the PCI Memory address range defined as APIC configuration  
space and High BIOS Address range. As an Internal Graphics device, the Graphics Memory range  
and the Memory mapped range of the Internal Graphics device MUST NOT overlap with these two  
ranges. These ranges are described in detail in the following paragraphs.  
5.4.2.6  
APIC Configuration Space (FEC0_0000h -FECF_FFFFh, FEE0_0000h- FEEF_FFFFh)  
This range is reserved for APIC configuration space that includes the default I/O APIC  
configuration space. The default Local APIC configuration space is FEE0_0000h to FEEF_0FFFh.  
CPU accesses to the Local APIC configuration space do not result in external bus activity since the  
Local APIC configuration space is internal to the CPU. However, an MTRR must be programmed  
to make the Local APIC range uncacheable (UC). The Local APIC base address in each CPU  
should be relocated to the FEC0_0000h (4 GB-20 MB) to FECF_FFFFh range so that one MTRR  
can be programmed to 64-kB for the Local and I/O APICs. The I/O APIC(s) usually resides in the  
ICH4-M portion of the chip-set or as a stand-alone component(s).  
I/O APIC units will be located beginning at the default address FEC0_0000h. The first I/O APIC  
will be located at FEC0_0000h. Each I/O APIC unit is located at FEC0_x000h where x is I/O APIC  
unit number 0 through F(hex). This address range will be normally mapped to Hub interface.  
The address range between the APIC configuration space and the High BIOS (FED0_0000h to  
FFDF_FFFFh) is always mapped to the Hub interface.  
5.4.2.7  
High BIOS Area (FFE0_0000h -FFFF_FFFFh)  
The top 2-MB of the Extended Memory region is reserved for System BIOS (High BIOS),  
extended BIOS for PCI devices, and the A20 alias of the system BIOS. CPU begins execution  
from the High BIOS after reset. This region is mapped to Hub interface so that the upper subset of  
this region aliases to 16 MB to 256-kB range. The actual address space required for the BIOS is  
less than 2-MB but the minimum CPU MTRR range for this region is 2-MB so that full 2-MB must  
be considered.  
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Intel 82854 Graphics Memory Controller Hub (GMCH)  
5.4.3  
System Management Mode (SMM) Memory Range  
The GMCH supports the use of main system memory as System Management RAM (SMM RAM)  
enabling the use of System Management mode. The GMCH supports three SMM options:  
Compatible SMRAM (C_SMRAM), High Segment (HSEG), and Top of Memory Segment  
(TSEG). System Management RAM space provides a system memory area that is available for the  
SMI handler's and code and data storage. This system memory resource is normally hidden from  
the system OS so that the processor has immediate access to this system memory space upon entry  
to SMM. The GMCH provides three SMRAM options:  
Below 1-MB option that supports compatible SMI handlers.  
Above 1-MB option that allows new SMI handlers to execute with Write-back cacheable  
SMRAM.  
Above 1-MByte solutions require changes to compatible SMRAM handlers code to properly  
execute above 1 MByte.  
Note: Hub interface is not allowed to access the SMM space.  
5.4.3.1  
SMM Space Restrictions  
If any of the following conditions are violated the results of SMM accesses are unpredictable and  
may cause the system to hang:  
The Compatible SMM space must not be set-up as cacheable.  
High or TSEG SMM transaction address space must not overlap address space assigned to  
DDR SDRAM or to any PCI devices (including Hub interface and graphics devices). This is a  
BIOS responsibility.  
Both D_OPEN and D_CLOSE must not be set to 1 at the same time.  
When TSEG SMM space is enabled, the TSEG space must not be reported to the OS as  
available. This is a BIOS responsibility.  
5.4.3.2  
SMM Space Definition  
SMM space is defined by its addressed SMM space and its DDR SDRAM SMM space. The  
addressed SMM space is defined as the range of bus addresses used by the CPU to access SMM  
space. DDR SDRAM SMM space is defined as the range of physical DDR SDRAM locations  
containing the SMM code. SMM space can be accessed at one of three transaction address ranges:  
Compatible, High, and TSEG. The Compatible and TSEG SMM space is not remapped and  
therefore the addressed and DDR SDRAM SMM space is the same address range. Since the High  
SMM space is remapped the addressed and DDR SDRAM SMM space is a different address range.  
Note that the High DDR SDRAM space is the same as the Compatible Transaction Address space.  
Table 28 describes three unique address ranges:  
Compatible Transaction Address (Adr C)  
High Transaction Address (Adr H)  
TSEG Transaction Address (Adr T)  
These abbreviations are used later in Table 28.  
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Intel 82854 GMCH System Address Map  
Table 28.  
SMM Space Transaction Handling  
SMM Space Enabled  
Transaction Address Space (Adr)  
A0000h to BFFFFh  
DRAM Space (DRAM)  
Compatible (C)  
High (H)  
A0000h to BFFFFh  
A0000h to BFFFFh  
0FEDA0000h to 0FEDBFFFFh  
(TOM-TSEG_SZ) to TOM  
TSEG (T)  
(TOM-TSEG_SZ) to TOM  
5.4.4  
5.4.5  
System Memory Shadowing  
Any block of system memory that can be designated as Read-Only or Write-Only can be  
"shadowed" into GMCH DDR SDRAM. Typically this is done to allow ROM code to execute  
more rapidly out of main DDR SDRAM. ROM is used as a Read-Only during the copy process  
while DDR SDRAM at the same time is designated Write-Only. After copying, the DDR SDRAM  
is designated Read-Only so that ROM is shadowed. CPU bus transactions are routed accordingly.  
I/O Address Space  
The GMCH does not support the existence of any other I/O devices beside itself on the CPU bus.  
The GMCH generates Hub interface or PCI bus cycles for all CPU I/O accesses that it does not  
claim. Within the Host bridge the GMCH contains two internal registers in the CPU I/O space,  
Configuration Address register (CONFIG_ADDRESS) and the Configuration Data register  
(CONFIG_DATA). These locations are used to implement Configuration Space Access  
Mechanism and as described in the Configuration register section.  
The CPU allows 64 kB +3 B to be addressed within the I/O space. The GMCH propagates the CPU  
I/O address without any translation on to the destination bus and therefore provides addressability  
for 64 k+3 B locations. Note that the upper three locations can be accessed only during I/O address  
wrap-around when CPU bus A16# address signal is asserted. A16# is asserted on the CPU bus  
whenever an I/O access is made to 4 bytes from address 0FFFDh, 0FFFEh, or 0FFFFh. A16# is  
also asserted when an I/O access is made to 2 bytes from address 0FFFFh.  
A set of I/O accesses (other than ones used for configuration space access) is consumed by the  
internal graphics device if it is enabled. The mechanisms for internal graphics IO decode and the  
associated control is explained later.  
The I/O accesses (other than ones used for configuration space access) are forwarded normally to  
the Hub interface. The GMCH will not post I/O Write cycles to IDE.  
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Intel 82854 Graphics Memory Controller Hub (GMCH)  
5.4.5.1  
PCI I/O Address Mapping  
The GMCH can be programmed to direct non-memory (I/O) accesses to the PCI bus interface  
when CPU initiated I/O cycle addresses are within the I/O address range. This range is controlled  
via the I/O Base Address (IOBASE) and I/O Limit Address (IOLIMIT) registers in GMCH  
Device #1 configuration space.  
Address decoding for this range is based on the following concept. The top 4 bits of the respective  
I/O Base and I/O Limit registers correspond to address bits A[15:12] of an I/O address. For the  
purpose of address decoding, the GMCH assumes that lower 12 address bits A[11:0] of the I/O  
base are zero and that address bits A[11:0] of the I/O limit address are FFFh. This forces the I/O  
address range alignment to 4-kB boundary and produces a size granularity of 4 kB.  
The GMCH positively decodes I/O accesses to AGP I/O address space as defined by the following  
equation:  
I/O_Base_Address CPU I/O Cycle Address I/O_Limit_Address  
The effective size of the range is programmed by the plug-and-play configuration software and it  
depends on the size of I/O space claimed by the AGP device.  
In Native Graphics mode, the GMCH also forwards accesses to the Legacy VGA I/O ranges  
according to the settings in the Device #1 configuration registers BCTRL (VGA Enable) and  
PCICMD1 (IOAE1), unless a second adapter (monochrome) is present on the Hub interface/PCI  
(or ISA). The presence of a second graphics adapter is determined by the MDAP configuration bit.  
When MDAP is set, the GMCH will decode legacy monochrome IO ranges and forward them to  
the Hub interface. The IO ranges decoded for the monochrome adapter are 3B4h, 3B5h, 3B8h,  
3B9h, 3Bah and 3BFh.  
Note: The GMCH Device #1 I/O address range registers defined above are used for all I/O space  
allocation for any devices requiring such a window on PCI. These devices would include the AGP  
device, PCI-66MHz/3.3V agents, and multifunctional AGP devices where one or more functions  
are implemented as PCI devices.  
The PCICMD1 register can disable the routing of I/O cycles to PCI.  
5.4.6  
GMCH Decode Rules and Cross-Bridge Address Mapping  
The address map described above applies globally to accesses arriving on any of the three  
interfaces (e.g., Host bus, IGD, and Hub interface).  
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Intel 82854 GMCH System Address Map  
5.4.7  
Hub Interface Decode Rules  
The GMCH accepts accesses from Hub interface to the following address ranges:  
All Memory Read and Write accesses to Main DDR SDRAM including PAM region (except  
SMM space)  
Memory writes to VGA range (Native Graphics Mode only)  
All Memory Reads from the Hub interface A that are targeted > 4-GB system memory range will  
be terminated with Master Abort completion, and all Memory Writes (>4-GB) from the Hub  
interface will be ignored.  
Hub interface system memory accesses that fall elsewhere within the system memory range are  
considered invalid and will be remapped to system memory address 0h, snooped on the Host Bus,  
and dispatched to DDR SDRAM. Reads will return all 1's with Master Abort completion. Writes  
will have BE's deasserted and will terminate with Master Abort if completion is required. I/O  
cycles will not be accepted. They are terminated with Master Abort completion packets.  
5.4.7.1  
Hub Interface Accesses to GMCH that Cross Device Boundaries  
Hub interface accesses are limited to 256 B (Bytes) but have no restrictions on crossing address  
boundaries. A single Hub interface request may therefore span device boundaries (DDR SDRAM)  
or cross from valid addresses to invalid addresses (or visa versa). The GMCH does not support  
transactions that cross device boundaries. For Reads and for Writes requiring completion, the  
GMCH will provide separate completion status for each naturally aligned 32-B or 64-B block. If  
the starting address of a transaction hits a valid address, the portion of a request that hits that target  
device (DDR SDRAM) will complete normally. The remaining portion of the access that crosses a  
device boundary (targets a different device than that of the starting address) or hits an invalid  
address will be remapped to system memory address 0h, snooped on the Host Bus, and dispatched  
to DDR SDRAM. Reads will return all 1's with Master Abort completion. Writes will have BE's  
(Byte Enable) deasserted and will terminate with Master Abort if completion is required.  
If the starting address of a transaction hits an invalid address the entire transaction will be  
remapped to system memory address 0h, snooped on the Host Bus, and dispatched to DDR  
SDRAM. Reads will return all 1's with Master Abort completion. Writes will have BE's deasserted  
and will terminate with Master Abort if completion is required.  
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Intel 82854 Graphics Memory Controller Hub (GMCH)  
5.4.7.2  
Interface Decode Rules  
Cycles Initiated Using PCI Protocol  
The GMCH does not support any PCI access targeting Hub interface. The GMCH will claim PCI  
initiated memory read and write transactions decoded to the main DDR SDRAM range. All other  
memory read and write requests will be master-aborted by the PCI initiator as a consequence of  
GMCH not responding to a transaction.  
Under certain conditions, the GMCH restricts access to the DOS Compatibility ranges governed by  
the PAM registers by distinguishing access type and destination bus. The GMCH accepts PCI  
write transactions to the compatibility ranges if the PAM designates DDR SDRAM as writeable. If  
accesses to a range are not write enabled by the PAM, the GMCH does not respond and the cycle  
will result in a master-abort. The GMCH accepts PCI read transactions to the compatibility ranges  
if the PAM designates DDR SDRAM as readable. If accesses to a range are not read enabled by  
the PAM, the GMCH does not respond and the cycle will result in a master-abort.  
If agent on PCI issues an I/O or PCI Special Cycle transaction, the GMCH will not respond and  
cycle will result in a master-abort. The GMCH will accept PCI configuration cycles to the internal  
GMCH devices as part of the PCI configuration/co-pilot mode mechanism.  
Accesses to GMCH that Cross Device Boundaries  
For FRAME# accesses, when a PCI master gets disconnected it will resume at the new address  
which allows the cycle to be routed to or claimed by the new target. Therefore accesses should be  
disconnected by the target on potential device boundaries. The GMCH will disconnect PCI  
transactions on 4-kB boundaries.  
SBA accesses are limited to 256 bytes and must hit DDR SDRAM. Accesses are dispatched to  
DDR SDRAM on naturally aligned 32 byte block boundaries. The portion of the request that hits a  
valid address will complete normally. The portion of a read access that hits an invalid address will  
be remapped to address 0h, return data from address 0h, and set the IAAF error flag. The portion of  
a write access that hits an invalid address will be remapped to memory address 0h with BE's  
deasserted (effectively dropped "on the floor") and set the IAAF error flag.  
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Functional Description  
6.0  
Functional Description  
6.1  
Host Interface Overview  
The GMCH front side bus uses source synchronous transfer for the address and data signals. The  
address signals are double pumped and two addresses can be generated every bus clock. At  
100-MHz bus frequency, the two address signals run at 200 MHz for a maximum address queue  
rate of 50-M addresses/sec. The data is quad pumped and an entire 64-B cache line can be  
transferred in two bus clocks. At 100-MHz/133MHz bus frequency, the data signals run at  
400 MHz for a maximum bandwidth of 3.2/4.3GB/s. The GMCH supports a 8-deep IOQ (In-  
Order-Queue) using the Intel Celeron M processor, or Genuine Intel® Processor.  
6.2  
Dynamic Bus Inversion  
The GMCH supports dynamic bus inversion (DBI) when driving and receiving data from the Host  
Bus. DBI limits the number of data signals that are driven to a low voltage on each quad pumped  
data phase. This decreases the power consumption of the GMCH. DINV[3:0]# indicates if the  
corresponding 16 bits of data are inverted on the bus for each quad pumped data phase:  
Table 29.  
Relation of DBI Bits to Data Bits  
DINV[3:0]  
Data Bits  
DINV[0]#  
DINV[1]#  
DINV[2]#  
DINV[3]#  
HD[15:0]#  
HD[31:16]#  
HD[47:32]#  
HD[63:48]#  
Whenever the CPU or the GMCH drives data, each 16-bit segment is analyzed. If more than eight  
of the 16 signals would normally be driven low on the bus the corresponding DINV# signal will be  
asserted and the data will be inverted prior to being driven on the bus. Whenever the CPU or the  
GMCH receives data it monitors DINV[3:0]# to determine if the corresponding data segment  
should be inverted.  
6.2.1  
System Bus Interrupt Delivery  
The Intel Celeron M processor support system bus interrupt delivery. It does not support the APIC  
serial bus interrupt delivery mechanism. Interrupt related messages are encoded on the system bus  
as Interrupt Message transactions. System bus interrupts may originate from the processor on the  
system bus, or from a downstream device on the Hub interface.  
In a GMCH platform, the ICH4-M contains IOxAPICs and its interrupts are generated as upstream  
Hub interface Memory Writes. Furthermore, PCI 2.2 defines MSI's (Message Signaled Interrupts)  
that are also in the form of Memory Writes. A PCI 2.2 device may generate an interrupt as an MSI  
cycle on its PCI bus instead of asserting a hardware signal to the IOxAPIC. The MSI may be  
directed to the IOxAPIC, which in turn generates an interrupt as an upstream Hub interface  
memory write. Alternatively the MSI may be directed directly to the system bus. The target of an  
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Intel 82854 Graphics Memory Controller Hub (GMCH)  
MSI is dependent on the address of the interrupt Memory Write. The GMCH forwards inbound  
Hub interface memory writes to address 0FEEx_xxxxh, to the system bus as Interrupt Message  
transactions.  
6.2.2  
Upstream Interrupt Messages  
The GMCH accepts message based interrupts from its Hub interface and forwards them to the  
system bus as Interrupt Message transactions. The Interrupt Messages presented to the GMCH are  
in the form of Memory Writes to address 0FEEx_xxxxh. At the Hub interface, the Memory Write  
Interrupt Message is treated like any other Memory Write; it is either posted into the inbound data  
buffer (if space is available) or retried (if data buffer space is not immediately available). Once  
posted, the Memory Write from the Hub interface, to address 0FEEx_xxxxh, is decoded as a cycle  
that needs to be propagated by the GMCH to the front side bus as an Interrupt Message transaction.  
6.3  
System Memory Interface  
6.3.1  
DDR SDRAM Interface Overview  
The GMCH supports DDR SDRAM at 200/266-MHz and includes the following support:  
Up to 1 GB of PC2100/PC2700 DDR SDRAM  
Maximum of two DDR DIMMs, single-sided and/or double-sided  
The 2-bank select lines SBA[1:0] and the 13 Address lines SMA[12:0] allow the GMCH to support  
64-bit wide DDR DIMMs using 128-Mb, 256-Mb, and 512-Mb DDR SDRAM technology. While  
address lines SMA[9:0] determine the starting address for a burst, burst length can only be 4. Four  
chip selects SCS[3:0]# lines allow a maximum of two rows of single-sided DDR SDRAM DIMMs  
and four rows of double-sided DDR SDRAM DIMMs.  
The GMCH main system memory controller targets CAS latencies of 2 and 2.5 for DDR SDRAM.  
The GMCH provides refresh functionality with a programmable rate (normal DDR SDRAM rate is  
1 refresh/15.6 µs). For write operations of less than a full cache line, GMCH will perform a cache-  
line read and into the write buffer and perform byte-wise write-merging in the write buffer.  
6.3.2  
System Memory Organization and Configuration  
6.3.2.1  
Configuration Mechanism for DDR DIMMs  
Detection of the type of DDR SDRAM installed on the DDR DIMM is supported via Serial  
Presence Detect mechanism as defined in the JEDEC 200-pin DDR DIMM specification.  
Before any cycles to the system memory interface can be supported, the GMCH DDR SDRAM  
registers must be initialized. The GMCH must be configured for operation with the installed  
system memory types. Detection of system memory type and size is done via the System  
Management Bus (SMB) interface on the ICH4-M. This two-wire bus is used to extract the DDR  
SDRAM type and size information from the Serial Presence Detect port on the DDR SDRAM  
DDR DIMMs. DDR SDRAM DIMMs contain a 5-pin Serial Presence Detect interface, including  
SCL (serial clock), SDA (serial data) and SA[2:0]. Devices on the SMBus have a 7-bit address.  
For the DDR SDRAM DIMMs, the upper four bits are fixed at 1010b. The lower three bits are  
strapped on the SA[2:0] pins. SCL and SDA are connected directly to the System Management bus  
on the ICH4-M. Thus data is read from the Serial Presence Detect port on the DDR DIMMs via a  
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Functional Description  
series of I/O cycles to the south bridge. The BIOS needs to determine the size and type of system  
memory used for each of the rows of system memory in order to properly configure the GMCH  
system memory interface.  
For SMBus Configuration and Access of the Serial Presence Detect Ports, refer to the Intel®  
82801DBM I/O Controller Hub 4 (ICH4-M) Datasheet (252337) for more detail.  
6.3.2.2  
System Memory Register Programming  
This section provides an overview of how the required information for programming the DDR  
SDRAM registers is obtained from the Serial Presence Detect ports on the DDR DIMMs. The  
Serial Presence Detect ports are used to determine Refresh Rate, MA and MD Buffer Strength, row  
Type (on a row by row basis), DDR SDRAM Timings, row sizes and row page sizes. Table 30 lists  
a subset of the data available through the on board Serial Presence Detect ROM on each DDR  
DIMM.  
Table 30.  
Data Bytes on DDR DIMM Used for Programming DRAM Registers  
Byte  
Function  
2
System Memory Type (DDR SDRAM)  
Number of row addresses, not counting Bank Addresses  
Number of Column Addresses  
Number of DIMM banks  
3
4
5
12  
17  
Refresh Rate/Type  
Number Banks on each Device  
Table 30 is only a subset of the defined SPD bytes on the DDR DIMMs. These bytes collectively  
provide enough data for programming the GMCH DDR SDRAM registers.  
6.3.3  
DDR SDRAM Performance Description  
The overall system memory performance is controlled by the DDR SDRAM timing register,  
pipelining depth used in GMCH, system memory speed grade and the type of DDR SDRAM used  
in the system. Besides this, the exact performance in a system is also dependent on the total system  
memory supported, external buffering and system memory array layout. The most important  
contribution to overall performance by the system memory controller is to minimize the latency  
required to initiate and complete requests to system memory, and to support the highest possible  
bandwidth (full streaming, quick turn-arounds). One measure of performance is the total flight  
time to complete a cache line request. A true discussion of performance really involves the entire  
chipset, not just the system memory controller.  
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Intel 82854 Graphics Memory Controller Hub (GMCH)  
6.4  
Integrated Graphics Overview  
®
The Intel 82854 GMCH provides a highly integrated graphics accelerator and PCI set while  
allowing a flexible Integrated System Graphics solution.  
®
Figure 7.  
Intel 82854 GMCH Graphics Block Diagram (Native Graphic Mode only)  
DDR/SDRAM  
Memory Control  
DAC  
Overlay  
Video Engine  
(MPEG2 Decode)  
Cntl  
Mux  
Port  
Alpha  
Blend/  
Gamma/  
CRC  
2D Engine  
DVOB  
Primary  
Display  
3D Engine  
Instr./  
Data  
Setup/Transform  
Scan Conversion  
Texture Engine  
Raster Engine  
DVOC  
Display C  
2nd Overlay  
High bandwidth access to data is provided through the system memory port. The GMCH uses a  
tiling architecture to minimize page miss latencies and thus maximize effective rendering  
bandwidth.  
6.4.1  
3D/2D Instruction Processing  
The GMCH contains an extensive set of instructions that control various functions including 3D  
rendering, BLT operations, display, MPEG decode acceleration, and overlay. The 3D instructions  
set 3D pipeline states and control the processing functions. The 2D instructions provide an efficient  
method for invoking BLT operations.  
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Functional Description  
6.4.2  
3D Engine  
The 3D engine of the GMCH has been designed with a deeply pipelined architecture, where  
performance is maximized by allowing each stage of the pipeline to simultaneously operate on  
different primitives or portions of the same primitive. The GMCH supports the following:  
Perspective-corrected Texture mapping  
Multitexturing  
Embossed and Dot-Product Bump mapping  
Cubic Environment Maps  
Bilinear, Trilinear, and Anisotropic MIP map filtering  
Gouraud shading and Flat shading  
Alpha-blending  
Per-Vertex and per- pixel fog  
Z/W buffering  
These features are independently controlled via a set of 3D instructions. The 3D pipeline  
subsystem performs the 3D rendering acceleration. The main blocks of the pipeline are the Setup  
Engine, Scan Converter, Texture Pipeline, and Raster Pipeline. A typical programming sequence  
would be to send instructions to set the state of the pipeline followed by rendering instructions  
containing 3D primitive vertex data.  
6.4.2.1  
Setup Engine  
The GMCH 3D setup engine takes the input data associated with each vertex of a 3D primitive and  
computes the various parameters required for scan conversion. In formatting this data, the GMCH  
maintains sub-pixel accuracy. The per-vertex data is converted into gradients that can be used to  
interpolate the data at any pixel within a polygon (colors, alpha, Z or W depth, fog, and texture  
coordinates). The pixels covered by a polygon are identified and per-pixel texture addresses are  
calculated.  
6.4.2.2  
6.4.2.3  
6.4.2.4  
Viewport Transform and Perspective Divide  
A 3D-geometry pipeline typically involves transformation of vertices from model space to clipping  
space followed by clip test and clipping. Lighting can be performed during the transformation or at  
any other point in the pipeline. After clipping, the next stage involves perspective divide followed  
by transformation to the viewport or screen space. The GMCH can support viewport transform and  
perspective divide portion of the 3D geometry pipeline in hardware.  
3D Primitives and Data Formats Support  
The 3D primitives rendered by the GMCH are points, lines, discrete triangles, line strips, triangle  
strips, triangle fans, and polygons. In addition to this, the GMCH supports DirectX's* Flexible  
Vertex Format* (FVF), which enables the application to specify a variable length parameter list,  
obviating the need for sending unused information to the hardware. Strips, Fans, and Indexed  
Vertices as well as FVF improves delivered vertex rate to the setup engine significantly.  
Pixel Accurate Fast Scissoring and Clipping Operation  
The GMCH supports clipping to a scissoring rectangle within the drawing window. The GMCH  
clipping and scissoring in hardware reduce the need for software to process polygons, and thus  
improves performance. During the setup stage, the GMCH clips polygons to the drawing window.  
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Intel 82854 Graphics Memory Controller Hub (GMCH)  
The scissor rectangle accelerates the clipping process by allowing the driver to clip to a bigger  
region than the hardware renders to. The scissor rectangle is pixel accurate, and independent of line  
and point width. The GMCH supports a single scissor box rectangle.  
6.4.2.5  
Backface Culling  
As part of the setup, the GMCH can discard polygons from further processing, if they are either  
facing away from or towards the user's viewpoint. This operation, referred to as Back Face Culling  
is accomplished based on the clockwise or counter-clockwise orientation of the vertices on a  
primitive. This can be enabled or disabled by the driver.  
6.4.2.6  
6.4.2.7  
Scan Converter  
The Scan Converter takes the vertex and edge information identifies all pixels that are affected by  
features being rendered. It works on a per-polygon basis, and one polygon may be entering the  
pipeline while calculations finish on another.  
Texture Engine  
The GMCH allows an image pattern or video to be placed on the surface of a 3D polygon. The  
texture engine performs texture color or chromakey matching texture filtering (anisotropic,  
trilinear, and bilinear) and YUV to RGB conversion.  
As texture sizes increase beyond the bounds of graphics memory, executing textures from graphics  
memory becomes impractical. Every rendering pass would require copying each and every texture  
in a scene from system memory to graphics memory, then using the texture, and finally overwriting  
the local memory copy of the texture by copying the next texture into graphics memory. The  
GMCH, using Intel's Direct Memory Execution model, simplifies this process by rendering each  
scene using the texture located in system memory. The GMCH includes a cache controller to avoid  
frequent memory fetches of recently used texture data.  
6.4.2.8  
6.4.2.9  
Perspective Correct Texture Support  
A textured polygon is generated by mapping a 2D texture pattern onto each pixel of the polygon. A  
texture map is like wallpaper pasted onto the polygon. Since polygons are rendered in perspective,  
it is important that texture be mapped in perspective as well. Without perspective correction,  
texture is distorted when an object recedes into the distance. Perspective correction involves a  
compute-intensive "per-pixel-divide" operation on each pixel. Perspective correction is necessary  
for realistic 3D graphics.  
Texture Decompression  
As the textures' average size gets larger with higher color depth and multiple textures become the  
norm, it becomes increasingly important to provide support for compressed textures.  
DirectX* supports Texture Compression/Decompression to reduce the bandwidth required to  
deliver textures. The GMCH supports several compressed texture formats (DirectX: DXT1, DXT2,  
DXT3, DXT4, DXT5) and OpenGL FXT1 formats.  
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6.4.2.10  
Texture Chromakey  
Chromakey is a method for removing a specific color or range of colors from a texture map before  
it is applied to an object. For nearest texture filter modes, removing a color simply makes those  
portions of the object transparent (the previous contents of the back buffer show through). For  
linear texture filtering modes, the texture filter is modified if only the non-nearest neighbor texels  
match the key (range).  
Chromakeying can be performed for both paletted and non-paletted textures, and removes texels  
that fall within a specified color range. The Chromakey mode refers to testing the ARGB or YUV  
components to see if they fall between high and low state variable values. If the color of a texel  
contribution is in this range and chromakey is enabled, then this contribution is removed from the  
resulting pixel color.  
6.4.2.11  
Anti-Aliasing  
Aliasing is one of the artifacts that degrade image quality. In its simplest manifestation, aliasing  
causes the jagged staircase effects on sloped lines and polygon edges. Another artifact is the moiré  
patterns, which occur as a result of the fact that there is very small number of pixels available on  
screen to contain the data of a high-resolution texture map.  
Full scene anti-aliasing uses super-sampling, which means that the image is rendered internally at a  
higher resolution than it is displayed on screen. The GMCH renders internally at 1600x1200, reads  
the image as a texture, and finally down-samples (via a Bilinear filter) to the screen resolution of  
640x480 and 800x600. Full scene anti-aliasing removes jaggies at the edges.  
6.4.2.12  
Texture Map Filtering  
Many texture-mapping modes are supported. Perspective correct mapping is always performed.  
As the map is fitted across the polygon, the map can be tiled, mirrored in either the U or V  
directions, or mapped up to the end of the texture and no longer placed on the object (this is known  
as clamp mode). The way a texture is combined with other object attributes is also definable.  
The GMCH supports up to 12 Levels-of-Detail (LODs) ranging in size from 2048x2048 to 1x1  
texels. (A texel is defined as a texture map element.) Included in the texture processor is a texture  
cache, which provides efficient MIP-mapping.  
The GMCH supports seven types of texture filtering:  
Nearest (also known as Point filtering): Texel with coordinates nearest to the desired pixel is  
used. (This is used if only one LOD is present.)  
Linear (also known as Bilinear filtering): A weighted average of a 2x2 area of texels  
surrounding the desired pixel is used. (This is used if only one LOD is present.)  
Nearest MIP Nearest (also known as Point filtering): This is used if many LODs are present.  
The nearest LOD is chosen and the texel with coordinates nearest to the desired pixel are used.  
Linear MIP Nearest (Bilinear MIP mapping): This is used if many LODs are present. The  
nearest LOD is chosen and a weighted average of a 2x2 area of texels surrounding the desired  
pixel is used (four texels). This is also referred to as Bilinear MIP Mapping.  
Nearest MIP Linear (Point MIP mapping): This is used if many LODs are present. Two  
appropriate LODs are selected and within each LOD the texel with coordinates nearest to the  
desired pixel are selected. The Final texture value is generated by linear interpolation between  
the two texels selected from each of the MIP Maps.  
Linear MIP Linear (Trilinear MIP mapping): This is used if many LODs are present. Two  
appropriate LODs are selected and a weighted average of a 2x2 area of texels surrounding the  
desired pixel in each MIP Map is generated (four texels per MIP Map). The Final texture  
value is generated by linear interpolation between the two texels generated for each of the MIP  
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Maps. Trilinear MIP Mapping is used minimize the visibility of LOD transitions across the  
polygon.  
Anisotropic MIP Nearest (Anisotropic filtering): This filter can be used when textured object  
pixels map back to significantly non-square regions of the texture (e.g., when the texture is  
scaled in one screen direction than the other screen direction).  
Both DirectX and OpenGL (Rev.1.1) allow support for all these filtering modes.  
6.4.2.13  
Multiple Texture Composition  
The GMCH also performs multiple texture composition. This allows the combination of two or  
greater MIP maps to produce a new one with new LODs and texture attributes in a single or  
iterated pass. The setup engine supports up to four texture map coordinates in as single pass. The  
GMCH allows up to two Bilinear MIP Maps or a single Trilinear MIP Map to be composited in a  
single pass. Greater than two Bilinear MIP Maps or more than one Trilinear MIP Map would  
require multiple passes. The actual blending or composition of the MIP Maps is done in the raster  
engine. The texture engine provides the required texels including blending information.  
Flexible vertex format support allows multi-texturing because it makes it possible to pass more  
than one texture in the vertex structure.  
6.4.2.14  
Cubic Environment Mapping  
Environment maps allow applications to render scenes with complex lighting and reflections while  
significantly decreasing CPU load. There are several methods to generate environment maps such  
as spherical, circular and cubic. The GMCH supports cubic reflection mapping over spherical and  
circular since it is the best choice to provide real-time environment mapping for complex lighting  
and reflections.  
Cubic Mapping supports a texture map for each of the 6 cube faces. These can be generated by  
pointing a camera with a 90-degree field-of-view in the appropriate direction. Per-vertex vectors  
(normal, reflection or refraction) are interpolated across the polygon and the intersection of these  
vectors with the cube texture faces are calculated. Texel values are then read from the intersection  
point on the appropriate face and filtered accordingly.  
6.4.2.15  
Bump Mapping  
The GMCH only supports embossed and dot product bump mapping, not environment bump  
mapping.  
6.4.3  
Raster Engine  
The Raster engine is where the color data such as fogging, specular RGB, texture map blending,  
etc. is processed. The final color of the pixel is calculated and the RGB value is combined with the  
corresponding components resulting from the Texture engine. These textured pixels are modified  
by the specular and fog parameters. These specular highlighted, fogged, textured pixels are color  
blended with the existing values in the frame buffer. In parallel, stencil, alpha, and depth buffer  
tests are conducted which will determine whether the Frame and Depth buffers will be updated  
with the new pixel values.  
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Functional Description  
6.4.3.1  
6.4.3.2  
Texture Map Blending  
Multiple textures can be blended together in an iterative process and applied to a primitive. The  
GMCH allows up to four distinct or shared texture coordinates and texture maps to be specified  
onto the same polygon. Also, the GMCH supports a texture coordinate set to access multiple  
texture maps. State variables in multiple textures are bound to texture coordinates, texture map or  
texture blending.  
Combining Intrinsic and Specular Color Components  
The GMCH allows an independently specified and interpolated specular RGB attribute to be added  
to the post-texture blended pixel color. This feature provides a full RGB specular highlight to be  
applied to a textured surface, permitting a high quality reflective colored lighting effect not  
available in devices which apply texture after the lighting components have been combined. If the  
specular-add state variable is disabled, only the resultant colors from the map blending are used. If  
this state variable is enabled, the specular RGB color is added to the RGB values from the output of  
the map blending.  
6.4.3.3  
Color Shading Modes  
The Raster engine supports the Flat and Gouraud shading modes. These shading modes are  
programmed by the appropriate state variables issued through the command stream.  
Flat shading is performed by smoothly interpolating the vertex intrinsic color components  
(Red, Green, Blue), Specular (R, G, B), Fog, and Alpha to the pixel, where each vertex color  
has the same value. The setup engine substitutes one of the vertex's attribute values for the  
other two vertices attribute values thereby creating the correct flat shading terms. This  
condition is set up by the appropriate state variables issued prior to rendering the primitive.  
Gouraud shading is performed by smoothly interpolating the vertex intrinsic color components  
(Red, Green, Blue). Specular (RGB), Fog, and Alpha to the pixel, where each vertex color has  
a different value.  
6.4.3.4  
6.4.3.5  
Color Dithering  
Color Dithering in the GMCH helps to hide color quantization errors for 16-bit color buffers. Color  
Dithering takes advantage of the human eye's propensity to average the colors in a small area. Input  
color, alpha, and fog components are converted from 8-bit components to 5-bit or 6-bit component  
by dithering. Dithering is performed on blended textured pixels. In 32-bit mode, dithering is not  
performed.  
Vertex and Per Pixel Fogging  
Fogging is used to create atmospheric effects such as low visibility conditions in flight simulator-  
type games. It adds another level of realism to computer-generated scenes. Fog can be used for  
depth cueing or hiding distant objects. With fog, distant objects can be rendered with fewer details  
(less polygons), thereby improving the rendering speed or frame rate. Fog is simulated by  
attenuating the color of an object with the fog color as a function of distance, and the greater the  
distance, the higher the density (lower visibility for distant objects). There are two ways to  
implement the fogging technique: per-vertex (linear) fogging and per-pixel (non-linear) fogging.  
The per-vertex method interpolates the fog value at the vertices of a polygon to determine the fog  
factor at each pixel within the polygon. This method provides realistic fogging as long as the  
polygons are small. With large polygons (such as a ground plane depicting an airport runway), the  
per-vertex technique results in unnatural fogging.  
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Intel 82854 Graphics Memory Controller Hub (GMCH)  
The GMCH supports both types of fog operations, vertex and per pixel. If fog is disabled, the  
incoming color intensities are passed unchanged to the destination blend unit. If fog is enabled, the  
incoming pixel color is blended with the fog color based on a fog coefficient on a per pixel basis.  
6.4.3.6  
Alpha Blending  
Alpha blending in the GMCH adds the material property of transparency or opacity to an object.  
Alpha blending combines a source pixel color and alpha component with a destination pixel color  
and alpha component. For example, this is so that a glass surface on top (source) of a red surface  
(destination) would allow much of the red base color to show through.  
Blending allows the source and destination color values to be multiplied by programmable factors  
and then combined via a programmable blend function. The combined and independent selection  
of factors and blend functions for color and alpha is supported.  
6.4.3.7  
Color Buffer Formats: (Destination Alpha)  
The Raster engine supports 8-bit, 16-bit, and 32-bit Color Buffer formats. The 8-bit format is used  
to support planar YUV4:2:0 format, which is used only in Motion Compensation and Arithmetic  
Stretch format. The bit format of Color and Z is allowed to mix.  
The GMCH can support an 8-bit destination alpha in 32-bit mode. Destination alpha is supported in  
16-bit mode in 1:5:5:5 or 4:4:4:4 format. The GMCH does not support general 3D rendering to 8-  
bit surfaces. 8-bit destinations are supported for operations on planar YUV surfaces (for example,  
stretch BLTs) where each 8-bit color component is written in a separate pass. The GMCH also  
supports a mode where both U and V planar surfaces can be operated on simultaneously.  
The frame buffer of the GMCH contains at least two hardware buffers - the Front Buffer (display  
buffer) and the Back Buffer (rendering buffer). While the back buffer may actually coincide with  
(or be part of) the visible display surface, a separate (screen or window-sized) back buffer is  
typically used to permit double-buffered drawing. That is, the image being drawn is not visible  
until the scene is complete and the back buffer made visible or copied to the front buffer via a 2D  
BLT operation. Rendering to one buffer and displaying from the other buffer removes image  
tearing artifacts. Additionally, more than two back buffers (for example, triple-buffering) can be  
supported.  
6.4.3.8  
Depth Buffer  
The Raster Engine is able to read and write from this buffer and use the data in per fragment  
operations that determine resultant color and depth value of the pixel for the fragment are to be  
updated or not.  
Typical applications for entertainment or visual simulations with exterior scenes require far/near  
ratios of 1000 to 10000. At 1000, 98% of the range is spent on the first 2% of the depth. This can  
cause hidden surface artifacts in distant objects, especially when using 16-bit depth buffers. A 24-  
bit Z-buffer provides 16 million Z-values as opposed to only 64 k with a 16-bit Z-buffer. With  
lower Z-resolution, two distant overlapping objects may be assigned the same Z-value. As a result,  
the rendering hardware may have a problem resolving the order of the objects, and the object in the  
back may appear through the object in the front.  
By contrast, when w (or eye-relative z) is used, the buffer bits can be more evenly allocated  
between the near and far clip planes in world space. The key benefit is that the ratio of far and near  
is no longer an issue, and allows applications to support a maximum range of miles, yet still get  
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Functional Description  
reasonably accurate depth buffering within inches of the eye point. The selection of depth buffer  
size is relatively independent of the color buffer. A 16-bit Z/W or 24-bit Z/W buffer can be selected  
with a 16-bit color buffer. Z buffer is not supported in 8-bit mode.  
6.4.3.9  
Stencil Buffer  
The Raster engine provides 8-bit stencil buffer storage in 32-bit mode and the ability to perform  
stencil testing. Stencil testing controls 3D drawing on a per pixel basis and conditionally eliminates  
a pixel on the outcome of a comparison between a stencil reference value and the value in the  
stencil buffer at the location of the source pixel being processed. They are typically used in  
multipass algorithms to achieve special effects, such as decals, outlining, shadows, and  
constructive solid geometry rendering.  
One of three possible stencil operations is performed when stencil testing is enabled. The stencil  
operation specifies how the stencil buffer is modified when a fragment passes or fails the stencil  
test. The selection of the stencil operation to be performed is based upon the result of the stencil  
test and the depth test. A stencil write mask is also included that controls the writing of particular  
bits into the stencil buffer. It selects between the destination value and the updated value on a per-  
bit basis. The mask is 8-bit wide.  
6.4.3.10  
Projective Textures  
The GMCH supports two simultaneous projective textures at full rate processing. These textures  
require three floating-point texture coordinates to be included in the FVF format. Projective  
textures enable special effects such as projecting spot light textures obliquely onto walls, and so on.  
6.4.4  
2D Engine  
The GMCH provides an extensive set of 2D instructions and 2D HW acceleration for block  
transfers of data (BLTs). The BLT engine provides the ability to copy a source block of data to a  
destination and perform operations (for example, ROP1, ROP2, and ROP3) on the data using a  
pattern, and/or another destination. The Stretch BLT engine is used to move source data to a  
destination that need not be the same size, with source transparency. Performing these common  
tasks in hardware reduces CPU load, and thus improves performance.  
6.4.4.1  
256-Bit Pattern Fill and BLT Engine  
Use of this BLT engine accelerates the Graphical User Interface (GUI) of Microsoft* Windows*.  
The GMCH BLT Engine provides hardware acceleration of block transfers of pixel data for many  
common Windows operations. The term BLT refers to a block transfer of pixel data between  
system memory locations. The BLT engine can be used for the following:  
Move rectangular blocks of data between system memory locations  
Data alignment  
Perform logical operations (raster ops)  
The rectangular block of data does not change as it is transferred between system memory  
locations. Data to be transferred can consist of regions of system memory, patterns, or solid color  
fills. A pattern will always be 8x8 pixels wide and may be 8-bits, 16-bits, or 32-bits per pixel.  
The GMCH BLT engine has the ability to expand monochrome data into a color depth of 8 bits, 16  
bits, or 32 bits. BLTs can be either opaque or transparent. Opaque transfers, move the data  
specified to the destination. Transparent transfers compare destination color to source color and  
write according to the mode of transparency selected.  
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Intel 82854 Graphics Memory Controller Hub (GMCH)  
Data is horizontally and vertically aligned at the destination. If the destination for the BLT  
overlaps with the source system memory location, the GMCH can specify which area in system  
memory to begin the BLT transfer. Hardware is included for all 256 raster operations (source,  
pattern, and destination) defined by Microsoft, including transparent BLT.  
The GMCH has instructions to invoke BLT operations, permitting software to set up instruction  
buffers and use batch processing as described in the Instruction Processing section. The GMCH  
can perform hardware clipping during BLTs.  
6.4.4.2  
Alpha Stretch BLT  
The stretch BLT function can stretch source data in the X and Y directions to a destination larger or  
smaller than the source. Stretch BLT functionality expands a region of system memory into a  
larger or smaller region using replication and interpolation. The stretch BLT function also provides  
format conversion and data alignment.  
6.4.5  
Planes and Engines  
The GMCH display can be functionally delineated into planes and engines (pipes and ports). A  
plane consists of rectangular shaped image that has characteristics such as source, size, position,  
method, and format. These planes get attached to source surfaces, which are rectangular system  
memory surfaces with a similar set of characteristics. They are also associated with a particular  
destination pipe.  
A pipe consists of a set of planes that will be combined with a timing generator. A port is the  
destination for the result of the pipe. The GMCH supports one Analog Output Port and two DVO  
ports. In conclusion, planes are associated with pipes and pipes are associated with ports.  
6.4.5.1  
Dual Pipe Independent Display Functionality (Native Graphic Mode only)  
The display consists of two display pipes, A and B. Pipes have a set of planes that are assigned to  
them as sources. The analog display port may only use Pipe A or Pipe B, the DVO B or C ports  
may use either Pipe A or Pipe B. This limits the resolutions available on a digital display when an  
analog CRT is active.  
Table 31.  
Dual Display Usage Model (Native Graphic Mode only)  
Display Pipe A  
Display Pipe B  
DVO B or C or Both  
CRT  
CRT  
DVO B or C or Both  
DVO C  
DVO B  
6.4.6  
Hardware Cursor Plane (Native Graphic Mode only)  
The GMCH supports two hardware cursors. The cursor plane is one of the simplest display planes.  
With a few exceptions, has a fixed size of 64 x 64 and a fixed Z-order (top). In legacy modes,  
cursor can cause the display data below it to be inverted. In the alpha blend mode, true color cursor  
data can be alpha blended into the display stream. It can be assigned to either display pipe A or  
display pipe B and dynamically flipped from one to the other when both are running.  
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Functional Description  
6.4.6.1  
Cursor Color Formats  
Color data can be in an indexed format or a true color format. Indexed data uses the entries in the  
four-entry cursor palette to convert the two-bit index to a true color format before being passed to  
the blenders. The index can optionally specify that a cursor pixel be transparent or cause an  
inversion of the pixel value below it or one of two colors from the cursor palette. Blending of YUV  
or RGB data is only supported with planes that have data of the same format.  
6.4.6.2  
6.4.6.3  
Popup Plane (Second Cursor)  
The popup plane is used for control functions in mobile applications. Only the hardware cursor has  
a higher Z-order precedence over the hardware icon. In standard modes (non-VGA) either cursor A  
or cursor B can be used as a Popup Icon. For VGA modes, 32-bpp data format is not supported.  
Popup Color Formats  
Source color data for the popup is in an indexed format. Indexed data uses the entries in the four-  
entry cursor palette to convert the two-bit index to a true color format before being passed to the  
blenders. Blending of color data is only supported with data of the same format.  
6.4.7  
Overlay Plane  
The overlay engine provides a method of merging either video capture data (from an external  
Video Capture device) or data delivered by the CPU, with the graphics data on the screen.  
6.4.7.1  
Multiple Overlays (Display C)  
A single overlay plane and scalar is implemented. This overlay plane can be connected to the  
primary display, secondary display or in bypass mode. In the default mode, it appears on the  
primary display. The overlay may be displayed in a multi-monitor scenario for single-pipe  
simultaneous displays only. Picture-in-Picture feature is supported via software through the  
arithmetic stretch BLT.  
6.4.7.2  
Source/Destination Color/Chromakeying  
Overlay source/destination chromakeying enables blending of the overlay with the underlying  
graphics background. Destination color-/chromakeying can be used to handle occluded portions of  
the overlay window on a pixel-by-pixel basis that is actually an underlay. Destination color keying  
supports a specific color (8-bit or 15-bit) mode as well as 32-bit alpha blending.  
Source color/chromakeying is used to handle transparency based on the overlay window on a  
pixel-by-pixel basis. This is used when "blue screening" an image to overlay the image on a new  
background later.  
6.4.7.3  
6.4.7.4  
Gamma Correction  
To compensate for overlay color intensity loss, the overlay engine supports independent gamma  
correction. This allows the overlay data to be converted to linear data or corrected for the display  
device when not blending.  
YUV to RGB Conversion  
The format conversion can be bypassed in the case of RGB source data.  
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6.4.7.5  
6.4.7.6  
Color Control  
Color control provides a method of changing the color characteristics of the pixel data. It is applied  
to the data while in YUV format and uses input parameters such as brightness, saturation, hue (tint)  
and contrast. This feature is supplied for the overlay only and works in YUV formats only.  
Dynamic Bob and Weave  
Interlaced data that originates from a video camera creates two fields that are temporally offset by  
1/60 of a second. There are several schemes to de-interlace the video stream: line replication,  
vertical filtering, field merging, and vertical temporal filtering. Field merging takes lines from the  
previous field and inserts them into the current field to construct the frame - this is known as  
weaving. This is the best solution for images with little motion; however, showing a frame that  
consists of the two fields will have serration or feathering of moving edges when there is motion in  
the scene. Vertical filtering or "Bob" interpolates adjacent lines rather replicating the nearest  
neighbor. This is the best solution for images with motion however, it will have reduced spatial  
resolution in areas that have no motion and introduce jaggies. In absence of any other de-  
interlacing, these form the baseline and are supported by the GMCH.  
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Functional Description  
6.4.8  
Video Functionality  
The GMCH supports MPEG-2 decoding hardware, sub-picture support and DTV.  
6.4.8.1  
MPEG-2 Decoding  
The GMCH MPEG2 Decoding supports Hardware Motion Compensation (HWMC). The GMCH  
can accelerate video decoding for the following video coding standards:  
MPEG-2 support  
MPEG-1: Full feature support  
H.263 support  
MPEG-4: Only supports some features in the simple profile  
The HWMC interface supports Hardware Video Acceleration Compatible API’s (HVA).  
6.4.8.2  
6.4.8.3  
Hardware Motion Compensation  
The HWMC process consists of reconstructing a new picture by predicting (either forward,  
backward, or bi-directional) the resulting pixel colors from one or more reference pictures. The  
GMCH receives the video stream and implements Motion Compensation and subsequent steps in  
hardware. Performing Motion Compensation in hardware reduces the processor demand of  
software-based MPEG-2 decoding, and thus improves system performance.  
Sub-picture Support  
Sub-picture is used for two purposes: Subtitles for movie captions, which are superimposed on a  
main picture, and for menus to provide some visual operation environments for the user.  
DVD allows movie subtitles to be recorded as sub-pictures. On a DVD disc, it is called subtitle  
because it has been prepared for storing captions. Since the disc can have a maximum of 32 tracks  
for subtitles, they can be used for various applications, for example, as Subtitles in different  
languages.  
There are two kinds of menus, the System menus and other In-Title menus. First, the System  
menus are displayed and operated at startup of or during the playback of the disc or from the stop  
state. Second, In-Title menus can be programmed as a combination of Sub-picture and Highlight  
commands to be displayed during playback of the disc.  
The GMCH supports sub-picture for DVD by mixing the two video streams via alpha blending.  
Unlike color keying, alpha blending provides a softer effect and each pixel that is displayed is a  
composite between the two video stream pixels. The GMCH can utilize four methods when dealing  
with sub-pictures. This flexibility means that the GMCH can work with all sub-picture formats.  
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Intel 82854 Graphics Memory Controller Hub (GMCH)  
6.5  
Internal Graphic Display Interface  
The GMCH has three dedicated display ports: an Analog CRT port and two Digital display ports,  
DVOB and DVOC.  
When the GMCH is strapped to operate in Native Graphic Mode, the DVOB and DVOC can  
support down stream devices such as TV-out encoders, external DACs, LVDS transmitters, and  
TMDS transmitters. Each display port has control signals that may be used to control, configure  
and/or determine the capabilities of an external device. The data that is sent out the display ports  
are selected from one of the two possible sources, display pipe A or display pipe B.  
The GMCH's digital display port is capable of driving a 165-MHz pixel clock on a single DVO  
port, or a 330-MHz pixel clock by combining DVOB and DVOC.  
6.5.1  
Pipe A Timing Generator Unit  
The Pipe A Timing generator provides the basic timing information for Display Pipe A. Timings  
are composed of blank, sync, border and active periods. The active period represents the data area;  
this is normally the size of a fixed resolution display or the selected resolution. Sync happens only  
within blank periods thereby dividing the blank into three regions consisting of a front porch, sync  
time, and back porch. Borders only happen directly before the start of blank and directly after the  
end of blank. Borders are referred to as left, right, top, or bottom. The Pipe A timing generator has  
been adapted to offer interlace support for the generation of HSYNC and VSYNC relative timing  
to support downstream field identification. It has also been adapted to provide interlace timing  
support for 480i and PAL formats. The following sections detail the features supported by the  
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Functional Description  
6.5.1.1  
ARIB Support  
Please refer to the ARIB TR-B15 Operational Guidelines for Digital Satellite Broadcasting  
(detailed Implementation guideline for receiver) for an exhaustive coverage of this topic  
®
the ARIB resolutions in Figure 8 except the Motion Picture (Movie) Plane and the Movie/Still  
picture selection plane. This device supports the remaining planes outlined in Figure 8.  
Figure 8.  
ARIB TR-B15 Plane Resolutions  
Plane name  
Requirements  
Resolution  
1920x1080x16,YCbCr(4:2:2), 16:9  
Still Picture Plane  
720x480x16,YCbCr(4:2:2), 16:9  
720x480x16,YCbCr(4:2:2), 4:3  
960x540x8, 16:9 (Display resolution is 1920x1080 – 1 pixel on the plane is transferred to 2x2 pixel on display)  
Text and Graphic  
Plane  
Resolution  
CLUT  
720x480x8, 16:9  
720x480x8, 4:3  
Number of CLUTs: 1  
Standard fixed color: 128 colors  
Receiver dependent color: 32 colors  
Vender dependent color: 96 colors  
8 bit index of CLUT input is tranfered to YCbCr (4:2:2) and 4 bit alpha value  
Translation  
Resolution  
960x540x8, 16:9 (Display resolution is 1920x1080 – 1 pixel on the plane is transferred to 2x2 pixel on display)  
Superimpose text  
plane  
720x480x8, 16:9  
720x480x8, 4:3  
Number of CLUTs: 1  
CLUT  
Standard fixed color: 128 colors  
Receiver dependent color: 32 colors  
Vender dependent color: 96 colors  
8 bit index of CLUT input is tranfered to YCbCr (4:2:2) and 4 bit alpha value  
Translation  
6.5.1.2  
H, V timing signals for active and blank timing  
®
Figure 9 depicts the major resolutions supported by the Intel 82854 GMCH, included in this table  
is support for NTSC and High Definition.  
®
The progressive timing modes are supported by the Intel 82854 GMCH in Native Graphic Mode.  
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Intel 82854 Graphics Memory Controller Hub (GMCH)  
Figure 9.  
H, V Parameters  
Parameter  
480i  
480p  
720p  
750  
1080i  
1080p  
1125  
576i  
768p  
Total  
Vert ical  
Lines  
525  
480  
525  
480  
525  
525  
1125  
1080  
625  
576  
802  
805  
Active  
Vert ical  
Lines  
480  
45  
480  
45  
720  
30  
1080  
45  
768  
34  
768  
37  
Total Blank  
Lines  
45  
45  
45  
49  
0-239  
0-239  
0-539  
0-287  
Active Line  
Number  
263-502  
263-502  
0-479  
858  
0-479  
858  
0-719  
1650  
563-1102  
0-1079  
2200  
313-600  
0-767  
1688  
0-767  
1656  
Total Pixels  
per Line  
858  
720  
858  
640  
2200  
1920  
864  
720  
Active Pixels  
per Line  
720  
640  
1280  
1920  
1280  
1366  
Blank Pixels  
per Line  
138  
218  
138  
27  
218  
27  
370  
280  
280  
144  
408  
290  
Pixel Clock  
[MHz]  
13.5  
13.5  
74.25  
74.25  
148.5  
13.5  
81.23  
79.99  
6.5.1.3  
HSYNC/VSYNC Field Timing  
The interlace timing is provided on the timing generator associated with Display Pipe A. When  
data is being driven out of the device, HSYNC and VSYNC accompanies or frames the data.  
Interlace timing requires that frame data is sent as two fields. Field1 data is scanned out first  
followed by Field2. The Pipe A timing produces a field timing signal (Field1) that is used by the  
Video Overlay and Display Plane A to produce Field1/Field2 data.  
Downstream devices use the relative placement of the VSYNC and HSYNC timing signals to  
discern field timing. For Field1 detection, the rising (asserting) edge of VSYNC is coincident with  
the rising (asserting) edge of HSYNC. For Field2 detection, VSYNC is asserted after the HSYNC  
pulse and occurs after at least 50% of the line is completed (see Figure 10).  
Figure 10.  
Interlaced Timing Using HSYNC and VSYNC for Field1/Field2 Downstream  
Detection  
VSYNC  
HSYNC  
Field2  
Field1  
D > 1/2 line  
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Functional Description  
Following conditions should be met for the sync (HSYNC, VSYNC) and blank (HBLANK,  
VBLANK) signals:  
Start of H(V)SYNC can not coincide with start of H(V)BLANK  
H(V)SYNC should always start after H(V)BLANK starts.  
In interlaced mode, the Vertical Total (VTOTAL_A register bits 27:16), Vertical Blank End  
(VBLANK_A register bits 27:16), Vertical Sync Start (VSYNC_A register bits 11:0) and Vertical  
Sync End (VSYNC_A register bits 27:16) must be programmed to a value 1 less than that of  
progressive case, which is described in Section 4.5. For example, for VBLANK end at line 525,  
program the register (VBLANK_A register bits 27:16) as 523 (note that it is 524 for progressive  
case). This is needed as the line counter is stalled for one line when the Vsync assertion is shifted  
between field1 and field2.  
6.5.2  
6.5.3  
Blend Function  
The blending unit is responsible for combining display planes onto a display pipe. This is done  
using an alpha blending technique that is described as "pre-multiplied source over destination" or a  
simple mux operation.  
Interlaced Video Field display  
®
The Intel 82854 GMCH provides interlace timing support for only Plane A and the Video  
Overlay window. Interlace timing is not available for Plane B, Plane C, Hardware Cursor A,  
Hardware Cursor B and the VGA plane. The Pipe A timing generator provides the interlace timing  
for Plane A and the Video Overlay.  
6.5.3.1  
Interlace support for Plane A graphics  
®
In the Intel 82854 GMCH, all the graphic features in Native Graphic mode are supported in Plane  
A, under progressive mode.  
In interlace mode, support for Field1 and Field2 timing generation is supported by Plane A. Plane  
A makes use of the DPODPfieldID signal generated by the Pipe A timing generator to synchronize  
the field timing. This signal is used to indicate which field of the picture should be scanned out.  
When DPODPfieldID is high, Field1 is scanned out. The DPODPfieldID is used to set the vertical  
line counters to the first line. The counters then increment by two until the end of the field is  
reached. During the VBI interval, the DPODPfieldID transitions to low indicating that Field2 is  
being processed next. This sets the vertical line counters to the second line and Field2 is then  
scanned out.  
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®
Intel 82854 Graphics Memory Controller Hub (GMCH)  
6.5.3.2  
ARIB 960 X 540 support  
In order to support the conversion of a 960x540 or a 960x1080 Plane A buffer to 1920x1080i, the  
GMCH supports pixel doubling in the horizontal direction and field replication in the vertical  
direction. In order to activate this functionality, interlace mode bit 20 in the DVOC- Digital  
Display Port C Register must be programmed to a 1. Register DSPACNTR-Display A Plane  
Control Register bits 21:20 are used to program the pixel doubling functionality. The following  
depicts the bit programming:  
00 -  
01 -  
10 -  
11 -  
No pixel/line multiplication  
Pixel AND Line doubling (not valid in interlaced mode)  
Reserved  
Pixel doubling ONLY (not validated in Native Graphic Mode)  
The Field replication mode is used to create two fields of data from Plane A. This is accomplished  
by scanning out Plane A once to produce Field1 and then rescanned out to produce Field2. In  
normal interlaced mode, the DSPABASE Register is programmed to the frame buffer start address,  
the DSPASTER Register is programmed with the frame buffer start address plus one line, and the  
DSPASTRIDE Register is programmed to 2x the line increment of the image in the frame buffer.  
For Field1, the DSPABASE and DSPASTRIDE Registers generate addresses into the frame buffer  
for even lines of the image. For Field2, the DSPASTER and DSPASTRIDE Registers generate  
addresses into the frame buffer to read odd lines of the image. In field replication mode, the  
DSPABASE and DSPASTER Registers are programmed with the same start address of the image  
in the frame buffer. The DSPASTRIDE register is programmed to the 1x line-to-line increment  
value. With interlaced mode enabled, this will effectively scan out the identical frame buffer for  
both Field1 and Field2.  
Please note that programming bits 21:20 of the DSPACNTR Register to "01" while the interlaced  
mode is enabled is illegal. In other words, Line doubling is undefined for the interlaced mode of  
operation.  
In order to archieve this, program the PLL to generate Dpclk/2 internally when the following bits  
of the DSPACNTR-Display A Plane Control Register, bit 21:20, are programmed for pixel  
duplication mode.  
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Functional Description  
6.5.4  
Interlace support for Video Overlay Window  
In interlace mode, support for Field1 and Field2 timing generation is supported by the Video  
Overlay. The Video Overlay makes use of the DPODPfieldID signal generated by the Pipe A  
timing generator to synchronize the field timing. This signal is used to indicate which field should  
be scanned out. The Video Overlay determines the correct lines to be used to assemble Field1 and  
Field2 during on the fly up and down scaling. The Bob method is used to generate the missing  
field information for Field2 when an interlaced source is used.  
Table 32.  
DVO Control Data Bits  
After rising edge of  
1st pixel clock  
2nd pixel clock  
VSYNC  
DVOB [23]  
DVOB [22:12]  
DVOB [10:0]  
Buffer ID  
Undefined  
Undefined  
Buffer ID  
Horizontal image size  
Vertical image size  
The Display Pipe A timing registers:  
HTOTAL_A  
VBLANK_A  
HBLANK_A  
VSYNC_A  
HSYNC_A  
PIPEASRC  
VTOTAL_A  
will hold data associated with physical buffer 0.  
The Display Pipe B timing registers:  
HTOTAL_B  
VBLANK_B  
HBLANK_B  
VSYNC_B  
HSYNC_B  
PIPEBSRC  
VTOTAL_B  
will hold data associated with physical buffer 1.  
The start address of physical buffer 0 will be in DSPABASE and the start address of physical buffer  
1 will be in DSPASEC. The stride for both buffers will be in DSPASTRIDE. Refer to Section 4.0,  
“Register Description” on page 41 for programming details.  
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®
Intel 82854 Graphics Memory Controller Hub (GMCH)  
Figure 11 shows how the timing registers switch while the buffer 0 and buffer 1 are scanned out.  
Timing Register Switching  
Figure 11.  
VSYNC_A  
VBLANK_A  
VTOTAL_A  
Buffer 0  
MP@ML 720x480(i) / 720x480(p)  
timing register switching  
occurs on VBLANK rising edge  
VSYNC_B  
VBLANK_B  
Buffer 1  
VTOTAL_B  
VBLANK  
VTOTAL  
04650438h  
04650438h  
062705A0h  
062705A0h  
VTOTAL_A  
VTOTAL_B  
As shown in the above figure, buffer switching in Multi-display mode occurs on VBLANK. Once  
VBLANK is detected, horizontal and vertical counters are reset and register switching occurs.  
These operations result in an extended HSYNC following the VBLANK. The HSYNC interval  
following VBLANK rising edge in MTV mode can be calculated as follows:  
When switching from Buffer0 to Buffer1:  
HSYNC INTERVAL = HSYNC_B[27:16] + 8  
When switching from Buffer1 to Buffer0:  
HSYNC INTERVAL = HSYNC_A[27:16] + 8  
Where HSYNC_A[27:16] and HSYNC_B[27:16] are the Horizontal Sync End values programmed  
in the PipeA and PipeB Horizontal Sync Registers.  
In addition, VBLANK is effectively started twice as a result of the counter reset. This results in  
two lines of inactive data being repeated. VSYNC will start two lines later then the programmed  
value, and the total number of lines is extended by two.  
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Functional Description  
6.5.5  
Analog Display Port Characteristics  
The Analog display port provides an RGB signal output along with an HSYNC and VSYNC  
signal. There is an associated DDC signal pair that is implemented using GPIO pins dedicated to  
the analog port. The intended target device is for a CRT based monitor with a VGA connector.  
6.5.5.1  
6.5.5.2  
Integrated RAMDAC  
The display function contains a 350-MHz, integrated, 24-bit, RAM-based Digital-to-Analog  
Converter (RAMDAC) that transforms up to 2048X1536 digital pixels at a maximum refresh rate  
of 75-Hz. Three, 8-bit DACs provide the R, G, and B signals to the monitor.  
DDC (Display Data Channel)  
DDC is defined by VESA. It allows communication between the host system and display. Both  
configuration and control information can be exchanged allowing plug-and-play systems to be  
realized. Support for DDC 1 and 2 is implemented.  
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®
Intel 82854 Graphics Memory Controller Hub (GMCH)  
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Power and Thermal Management  
7.0  
Power and Thermal Management  
®
The Intel 82854 GMCH is intended to be compliant with the following specifications and  
technologies:  
APM Rev 1.2  
PCI Power Management Rev 1.0  
PC'99, Rev 1.0, PC'99A, and PC'01, Rev 1.0  
ACPI 1.0b and 2.0 support  
ACPI S0, S1-M, S3, S4, S5, C0, C1, C2, C3 states  
Internal Graphics Adapter D0, D1, D3 (Hot/Cold)  
On Die Thermal sensor, enabling core and system memory Write Thermal throttling for  
prevention of catastrophic thermal conditions  
External Thermal sensor input pin  
Enabling DDR DIMM Thermal throttling  
The GMCH also reduces I/O power dynamically, by disabling sense amps on input buffers, as  
well as tristating output buffers when possible  
Dynamic Clock Power Down reduces power in all modes of operation  
System memory Self-Refresh in C3 state  
®
The Intel 82854 GMCH reduces I/O power dynamically by disabling sense amps on the input  
buffers, as well as tri-stating the output buffers when possible  
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Intel 82854 Graphics Memory Controller Hub (GMCH)  
7.1  
General Description of Supported CPU States  
C0 (Full On): This is the only state that runs software. All clocks are running, STPCLK is  
deasserted, and the processor core is active. The processor can service snoops and maintain cache  
coherency in this state.  
C1 (Auto Halt): The first level of power reduction occurs when the processor executes an Auto-  
Halt instruction. This stops the execution of the instruction stream and reduces the processor's  
power consumption. The processor can service snoops and maintain cache coherency in this state.  
C2 (Stop Grant): To enter this low power state, STPCLK is asserted. The processor can still  
service snoops and maintain cache coherency in this state.  
C3 (Sleep or Deep Sleep): In these states the processor clock is stopped. The GMCH assumes that  
no Hub interface cycles (except special cycles) will occur while the GMCH is in this state. The  
processor cannot snoop its caches to maintain coherency while in the C3 state. The GMCH will  
transition from the C0 state to the C3 state when software reads the Level 3 Register. This is an  
ACPI defined register but BIOS or APM (via BIOS) can use this facility when entering a low  
power state. The Host Clock PLL within the GMCH can be programmed to be shut off for  
increased power savings and the GMCH uses the DPSLP signal input for this purpose.  
C4 (Deeper Sleep): The C4 state appears to the GMCH as identical to the C3 state, but in this state  
the processor core voltage is lowered. There are no internal events in GMCH for the C4 state that  
differ from the C3 state. (The C4 state is not supported by the Intel Celeron M Processor, or  
Genuine Intel Processor).  
7.2  
General Description of ACPI States  
Internal Graphics Adapter:  
D0 Full on, display active  
D1 Low power state, low latency recovery. No display, system memory retained  
D3 Hot - All state lost other than PCI config. system memory lost (optionally)  
D3 Cold - Power off  
CPU:  
C0 Full On  
C1 Auto Halt  
C2 Stop Clock. Clk to CPU still running. Clock stopped to CPU core.  
C3 Deep Sleep. Clock to CPU stopped.  
C4 Deeper Sleep. Same as C3 with reduced voltage on the CPU.  
System States:  
G0/S0 Full On  
G1/S1-MPower On Suspend (POS). System Context Preserved  
G1/S2Not supported.  
G1/S3Suspend to RAM (STR). Power and context lost to chipset.  
G1/S4Suspend to Disk (STD). All power lost (except wakeup on ICH4-M)  
G2/S5Soft off. Total reboot.  
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Power and Thermal Management  
7.3  
Internal Thermal Sensor  
This section describes the new on-die Thermal sensor capability.  
7.3.1  
Overview  
The Thermal sensor functions are provided below:  
Catastrophic Trip Point: This trip point is programmed through the BIOS during initialization.  
This trip point is set at the temperature at which the GMCH should be shut down immediately with  
minimal software support. The settings for this are lockable.  
High Temperature Trip Point: This trip point is nominally 14ºC below the Catastrophic trip  
point. The BIOS can be programmed to provide an interrupt when it is crossed in either direction.  
Upon the trip event, Hardware Throttling may be enabled when the temperature is exceeded.  
7.3.2  
Hysteresis Operation  
Hysteresis provides a small amount of positive feedback to the Thermal sensor circuit to prevent a  
trip point from flipping back and forth rapidly when the temperature is right at the trip point.  
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®
Intel 82854 Graphics Memory Controller Hub (GMCH)  
7.4  
External Thermal Sensor Input  
An External Thermal sensor with a serial interface may be placed next to DDR SDRAM DIMM (or  
any other appropriate platform location), or a remote Thermal Diode may be placed next to the  
DDR DIMM (or any other appropriate platform location) and connected to the External Thermal  
sensor. Intel advises that the External Thermal sensor contains some form of hysteresis, since none  
is provided by the GMCH hardware.  
The external sensor can be connected to the ICH4-M via the SMBus interface to allow  
programming and setup by BIOS software over the serial interface. The External sensor's output  
should include an Active-Low Open-Drain signal indicating an Over-Temp condition, which  
remains asserted for as long as the Over-Temp Condition exists, and deasserts when temperature  
has returned to within normal operating range. This External sensor output will be connected to the  
GMCH input (EXTTS_0) and will trigger a Preset Interrupt and/or Read-Throttle on a level-  
sensitive basis.  
Additional External Thermal sensor's outputs, for multiple sensors, can be wire-OR'ed together  
allow signaling from multiple sensors located physically separately. Software can, if necessary,  
distinguish which DDR DIMM(s) is the source of the over-temp through the serial interface.  
However, since the DDR DIMM(s) will be located on the same System Memory Bus Data lines,  
any GMCH-based Read Throttle will apply equally.  
Note: The use of external sensors that include an internal pull-up resistor on the open-drain Thermal trip  
output is discouraged. However, it may be possible depending on the size of the pull-up and the  
voltage of the sensor. Please refer to the Intel® 854 Chipset Platform Design Guide For Use with  
Ultra Low Voltage Intel® Celeron® M Processor at 600 MHz (contact your Intel representative for  
the latest version of this document).  
7.4.1  
Usage  
External sensor(s) used for dynamic temperature feedback control:  
Sensor on DDR DIMMs, which can be used to dynamically control read throttling.  
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Intel 82854 GMCH Strap Pins  
®
8.0  
Intel 82854 GMCH Strap Pins  
8.1  
Strapping Configuration  
Table 33.  
Strapping Signals and Configuration  
Pin Name  
Strap Description  
Configuration  
I/F Type Buffer Type  
ADDID[0]  
Native Graphic Mode  
select  
ADDID[0] = 0, Reserved  
DVO  
IN  
ADDID[0] = 1, the Intel® 82854  
GMCH is strapped to operate  
under Native Graphic Mode  
HSYNC  
XOR Chain Test  
ALL Z Test  
Low = Normal Ops (Default)  
High = XOR Test On  
GPIO  
GPIO  
GPIO  
DVO  
OUT  
OUT  
OUT  
BI  
VSYNC  
Low = Normal Ops (Default)  
High = AllZ Test On  
LCLKCTLB  
DVODETECT  
VTT Voltage Select  
Low = Default  
High = Reserved  
*DVO Select (If  
Low = DVO (Default)  
High = Reserved  
DVODETECT=0 during  
Reset, ADDID[7:0] is  
latched to the ADDID  
Register)  
GST[2]  
* Clock Config: Bit_2  
Please refer to Device #0  
DVO  
Out:  
Function #3 (HPLLCC Register)  
for proper GST[2:0] settings  
0) Before CPURST#, there is an  
internal pull-down  
Please refer to Table 34 for  
detail configurations on Intel  
854 Straps for Frequency/CPU  
1) Just out of CPURST#: These  
pins are Hi-Z  
2) C3: these pins are Hi-Z  
3) S1-M: these pins are Hi-Z  
4) Internal GFX D1/D3: these pins  
are Hi-Z  
5) S3: these pins are Power down  
6) S4/S5: these pins are Power  
down  
GST[1]  
GST[0]  
*
* Clock Config: Bit_1  
* Clock Config: Bit_0  
Please refer to Device #0 Function #2 (ADD_ID – ADD Identification Register) for proper Native Graphic  
Mode settings.  
External pull-ups/downs will be required on the board to enable the non-default state of the straps.  
®
Note: All strap signals are sampled with respect to the leading edge of the Intel 82854 GMCH PWROK  
In signal.  
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Intel 82854 Graphics Memory Controller Hub (GMCH)  
®
Table 34.  
Intel 82854 GMCH Straps for Frequency/CPU Configuration  
GST[2:0]  
LCLKCTLB  
CPU  
FSB Freq  
DDR Freq  
Gfx Freq  
Core Vcc  
000  
0
Intel Celeron M Processor  
Family, Genuine Intel  
Processor  
400MHz  
266MHz  
200MHz  
1.5V  
111  
0
Intel Celeron M Processor  
Family, Genuine Intel  
Processor  
400MHz  
333MHz  
250MHz  
1.5V  
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Ballout and Package Information  
9.0  
Ballout and Package Information  
®
Figure 12.  
Intel 82854 GMCH Ballout Diagram (Top View)  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
SMVREF  
_0  
SMVSWI  
NGL  
SMVSWI  
NGH  
VCCQS  
M
VCCQS  
M
AJ  
AH  
AG  
AF  
AE  
AD  
AC  
AB  
AA  
Y
NC  
NC  
NC  
VSS  
VSS  
VCCSM  
VSS  
VCCSM  
VSS  
VSS  
VCCSM  
VCCSM  
VSS  
VSS  
VSS  
VCCSM  
VSS  
VCCSM  
NC  
VSS  
NC  
VSS  
NC  
AJ  
AH  
AG  
AF  
AE  
AD  
AC  
AB  
AA  
Y
SDM[7] SDQS[7] SDQ[56] SDQ[51] SDQS[6] SDQ[49] SDQ[43] SDQ[46] SDQ[40] SDQ[45] SDQ[38] SDQS[4] SDQ[32] SDM[8]  
RSVD SDQ[31] SDM[3] SDQ[25] SDQ[24] SDQ[18] SDQS[2] SDQ[20] SDQ[15] SDQS[1] SDQ[13] SDQ[7] SDQ[3]  
VCCSM SDQ[58]  
VSS  
SDQ[60] SDQ[55]  
VSS  
SDQ[52] SDQ[47]  
VSS  
SDQ[41] SDQ[39]  
VSS  
SDQ[33] RSVD  
VSS  
RSVD SDQ[26]  
VSS  
SDQ[28] SDQ[19]  
VSS  
SDQ[17] SDQ[10]  
VSS  
SDQ[9] SDQ[6]  
VSS  
SDQS[0] VCCSM  
VCCAS  
VCCSM SDQ[59] VCCSM SDQ[61] SDQ[54] VCCSM SDQ[53] SDQ[42] VCCSM SDQ[44] SDQ[34] VCCSM RSVD  
RSVD VCCSM SDQ[27] SDQ[30] VCCSM SMAB[4] SDQ[22] VCCSM SDQ[16] SDQ[14] VCCSM SDQ[12] SDQ[2] VCCSM SDQ[0]  
M
BCLK  
VSS  
SDQ[62] SDQ[57]  
VSS  
SDQ[50] SDQ[48]  
VSS  
SDQS[5] SDQ[35]  
VSS  
SDQ[37] RSVD  
VSS  
RSVD  
RSVD  
VSS  
SDQS[3] SDQ[23]  
VSS  
SDM[2] SDQ[11]  
VSS  
SDM[1] SDM[0]  
VSS  
SDQ[1] SDQ[5]  
VSS  
VCCAS  
M
BCLK# RSTIN# SDQ[63] SCS[1]# SWE# SDM[6] SCS[0]# SBA[0] SDM[5] SBA[1] SDM[4] SDQ[36] SMA[3] SMAB[1] SDQS[8] SMA[1] SMA[2] SDQ[29] SMA[4] SMAB[5] SDQ[21] SMA[6] SMA[7] SDQ[8] SMA[11] SCK[2]# SDQ[4] SCK[3]#  
RCVENI RCVEN  
VCCSM  
VSS  
VSS  
SCK[1] SCS[3]# SCAS#  
VSS  
SCS[2]# SRAS#  
VSS  
VCCSM  
VSS  
SMA[10] SMA[0]  
VSS  
VSS  
VCC  
VSS  
VCCSM  
VSS  
SMA[5] SMAB[2]  
VSS  
VSS  
SCKE[3] SCKE[2]  
VSS  
SCKE[0] SMA[8] SMA[9]  
VSS  
SCK[2] SCK[3] VCCSM  
SMRCO  
VCCSM SCKE[1] VCCSM SMA[12] SCK[5]# VCCSM SCK[0]  
N#  
OUT  
VTTLF HA[31]# HA[29]#  
VSS  
SCK[1]# SCK[4]# SCK[4] VCCSM  
VSS  
VSS  
VSS  
VCC  
VCCSM  
VSS  
VCCSM  
VSS  
VSS  
VCCSM  
VSS  
VCCSM  
VSS  
VSS  
NC  
MP  
HADSTB  
[1]#  
VSS  
VTTLF  
VSS  
HA[27]# HA[22]#  
HCCVRE  
VSS  
VSS  
VSS  
RSVD  
VSS  
VCC  
VCCSM  
VCCSM  
VCCSM  
VSS  
VSS  
VCCSM  
HL[7]  
VCCSM RSVD  
VSS  
SCK[5] SCK[0]#  
VCCAGP  
VSS  
HA[26]# HA[30]# HA[21]# HA[17]# DPSLP# HAVREF  
VSS  
VCCSM  
VSS  
VSS  
HL[5]  
VSS  
VCCHL  
HL[9]  
VCCSM GCLKIN  
VCCHL  
F
LL  
W
V
HA[28]# HA[25]#  
VSS  
HA[20]# HA[23]# HA[24]#  
VSS  
VCC  
VCCHL  
VSS  
VSS  
HL[10]  
HL[1]  
VSS  
HLSTB  
HL[4] HLVREF  
W
V
VTTHF HA[11]# HA[14]# HA[16]# HA[18]#  
VSS  
HA[19]# VTTLF  
VSS  
VCCHL  
VSS  
VCCHL  
HL[0]  
HL[6]  
HL[3] HLSTB# VCCHL  
U
VSS  
HA[10]# HA[12]#  
HA[5]# HA[13]#  
VSS  
HA[15]# HA[8]#  
HA[7]#  
VSS  
VTTLF  
VSS  
VTTLF  
VSS  
VSS  
VCC  
VSS  
VCC  
VSS  
VCC  
VSS  
VCC  
VSS  
VCC  
VSS  
VCC  
VSS  
VCC  
VSS  
VCC  
VSS  
VCC  
VSS  
VCC  
VSS  
VCC  
VSS  
VCC  
VSS  
VCCHL  
VSS  
VCCHL  
RSVD  
RSVD  
RSVD  
VSS  
HL[2] PSWING  
VSS  
U
HADSTB  
[0]#  
HREQ[4]  
#
MDDCD  
ATA  
HLRCO  
T
HA[4]#  
VSS  
HA[9]#  
VSS  
VSS  
RSVD  
RSVD  
RSVD  
RSVD  
RSVD  
HL[8]  
MP  
T
HREQ[0]  
HA[6]#  
#
HREQ[3]  
#
HREQ[2]  
#
VCCDV  
O
R
VSS  
VTTLF  
VSS  
VSS  
VSS  
RSVD  
RSVD  
VSS  
RSVD  
RSVD  
RSVD  
VSS  
R
HREQ[1]  
#
VCCDV  
O
MDDCC  
LK  
P
BPRI# HLOCK# RS[1]#  
HA[3]#  
VTTLF  
VSS  
VSS  
RSVD  
RSVD  
RSVD  
RSVD  
P
VCCDV MDVICL MI2CDA  
VCCDV  
O
N
VSS  
HITM#  
HIT#  
VSS  
BNR#  
DRDY# RS[0]#  
VTTLF  
VSS  
VSS  
N
O
K
TA  
VCCDV VCCDV  
MDVIDA  
TA  
VCCDV DVOBC  
M
L
VTTHF DEFER# RS[2]# DBSY# HTRDY#  
VSS  
BREQ0# VTTLF  
VSS  
RSVD  
VSS  
M
L
O
O
O
CLKINT  
VCCDV DVODET  
DVOCVS  
YNC  
DVOCBL  
ANK#  
VSS  
VTTLF  
VSS  
ADS#  
HD[6]#  
VSS  
HD[8]# HD[3]# HD[7]#  
VSS  
VTTLF  
VSS  
VSS  
RSVD  
O
ECT  
HYSWIN HDSTBP  
HDVREF  
[0]  
VCCDV  
O
MI2CCL DVOCH DVOCD[  
DVOCD[ DVOCD[ DVOCD[  
2] 3] 1]  
K
HD[13]# HD[2]#  
VSS  
HD[11]# HD[0]#  
VSS  
VSS  
K
G
[0]#  
K
SYNC  
0]  
HDSTBN  
[0]#  
HDVREF  
[1]  
HDVREF  
[2]  
VCCDV  
O
DVOCD[ DVOCD[ VCCDV DVOCCL DVOCCL VCCDV  
4] 5] K#  
J
HD[4]#  
VSS  
DINV[0]# HD[9]# HD[14]#  
VSS  
VSS  
VTTLF  
VSS  
VSS  
VSS  
VCC  
VSS  
VSS  
VCC  
VCC1_5  
VSS  
VSS  
PWROK  
VSS  
VSS  
HSYNC  
RSVD  
VSYNC  
VSS  
J
O
K
O
HYRCO  
MP  
LCLKCT  
LA  
VCCDV DVOCD[ DVOCFL DVOCD[ DVOCD[ DVOCD[ DVOCD[  
H
VTTHF  
VSS  
HD[1]# HD[15]# HD[10]#  
VSS  
HD[19]# VTTLF  
VSS  
VTTLF  
VTTLF  
VSS  
VTTLF  
RSVD  
VSS  
H
O
10]  
DSTL  
9]  
8]  
6]  
7]  
DDCADA  
TA  
DVOCD[ DVOBCI  
11] NTR#  
G
HD[5]# HD[12]#  
VSS  
HD[21]# HD[24]# HD[30]# HD[27]# HD[33]# HD[40]# DINV[3]# HD[48]# HD[51]# HD[58]# VTTLF  
CPURST  
RSVD VCC1_5 RSVD  
RSVD  
VSS  
RSVD  
VSS ADDID[6] ADDID[4] VSS  
VSS  
G
F
VTTLF HD[22]#  
VSS  
HD[17]# HD[16]#  
VSS  
HD[44]#  
VSS  
HD[45]#  
VSS  
HD[53]#  
VSS  
HD[56]#  
VSS  
RSVD  
RSVD  
RSVD  
RSVD  
VSS  
RSVD  
VSS  
RSVD  
RSVD  
RSVD  
RSVD  
RSVD  
RSVD VCC2_5 RSVD  
RSVD ADDID[7] ADDID[1] ADDID[5] RSVD  
RSVD GVREF  
VCCDV  
F
#
HDSTBN HDSTBP  
HDSTBP  
[3]#  
VCCDV  
O
VCCDV  
O
E
VSS  
VSS  
VSS  
HD[20]# HD[29]# DINV[1]# HD[38]# HD[41]#  
HDSTBP  
HD[50]# HD[49]#  
HD[61]# HD[59]# RSVD  
RSVD  
VSS  
RSVD  
VSS  
REFSET  
VSS  
ADDID[0]  
DPMS  
RSVD  
VSS  
ADDID[2] ADDID[3]  
E
[2]#  
[2]#  
O
VCCAHP  
LL  
HDSTBN  
[3]#  
EXTTS_  
0
DVORC  
OMP  
D
HD[23]#  
VSS  
HD[39]#  
VSS  
HD[36]#  
VSS  
HD[52]#  
VSS  
VSS  
HD[62]#  
VSS  
VCC2_5 BLUE# GREEN# RSVD  
VSS  
RSVD  
RSVD  
D
[1]#  
HDSTBN  
[1]#  
LCLKCT  
LB  
C
VSS  
NC  
NC  
29  
HD[25]#  
HD[28]# HD[37]# HD[34]# HD[35]#  
VSS  
HD[47]# HD[46]# HD[54]# HD[63]# HD[55]# HD[60]# RSVD  
RSVD  
RSVD  
VSS  
BLUE GREEN  
VSS  
GST[0] GST[1] GST[2]  
VSS  
NC  
C
HXRCO  
MP  
HXSWIN  
G
VCCADP  
LLB  
VCCADA VSSADA DREFCL DDCACL  
B
HD[31]# HD[18]# HD[26]# DINV[2]#  
VSS  
VTTHF  
24  
HD[43]# HD[42]# HD[32]#  
HD[57]#  
VSS  
RSVD  
VSS  
17  
VCC1_5 VCC1_5 RSVD  
VSS  
VSSA VCC2_5  
RSVD  
RSVD  
RSVD  
NC  
B
C
C
K
K
VCCADA  
C
VCCADP  
LLA  
VCCGPI VCCGPI  
A
NC  
28  
VSS  
27  
VTTLF  
26  
VSS  
25  
VSS  
23  
VTTHF  
22  
VSS  
21  
VTTLF  
20  
VTTLF  
18  
VCC2_5 VCCA  
RSVD  
10  
RED#  
RED  
RSVD  
5
A
O
O
19  
16  
15  
14  
13  
12  
11  
9
8
7
6
4
3
2
1
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Intel 82854 Graphics Memory Controller Hub (GMCH)  
9.1  
VCC/VSS Voltage Groups  
Table 35.  
Voltage Levels and Ball Out for Voltage Groups  
Name  
Voltage Level  
Ball out  
VCC  
1.5  
H14,J15,N14,N16,P13,P15,P17,R14,R16,T13,T15,  
T17,U14,U16,W21,AA15,AA17,AA19  
VCCADAC  
VCCDVO  
VCCASM  
VCC1_5  
VCCGPIO  
VCCHL  
1.5  
1.5  
1.5  
1.5  
3.3  
1.5  
2.5  
2.5  
A9,B9  
E1,E4,E6,H7,J1,J4,J8,K9,L8,M4,M8,M9,N1,N8,P9,R8  
AD1,AF1  
B14,B15,G13,J13  
A3,A4  
U6,U8,V1,V7,V9,W5,W8,Y1  
AJ6,AJ8  
VCCQSM  
VCCSM  
Y4,Y7,Y9,AA6,AA8,AA11,AA13,AB3,AB6,AB8,AB10,  
AB12,AB14,AB16,AB18,AB20,AB22,AC1,AC29,AF3,  
AF6,AF9,AF12,AF15,AF18,AF21,AF24,AF27,AF29,  
AG1,AG29,AJ5,AJ9,AJ13,AJ17,AJ21,AJ25  
VCC2_5  
VTTHF  
VTTLF  
2.5  
1.5  
1.5  
A12,B10,D10,F9  
A22,A24,H29,M29,V29  
A18,A20,A26,F29,G15,H16,H18,H20,H22,J19,K29,L21,  
M22,N21,P22,R21,T22,U21,V22,Y29,AB29  
VSS  
GND  
A13,A17,A19,A21,A23,A25,A27,B5,B24,C1,C7,C10,C22,C29,  
D4,D11,D13,D15,D17,D19,D21,D23,D25,D28,E7,E9,E28,E29,  
F11,F13,F16,F18,F20,F22,F24,F27,G1,G4,G7,G26,G29,H8,H11,  
H13,H15,H17,H19,H21,H24,J7,J10,J12,J14,J16,J18,J20,J22,J26,  
J29,K4,K8,K24,L1,L6,L9,L22,L26,L29,M7,M21,M24,N4,N9,N13,  
N15,N17,N22,N26,N29,P8,P14,P16,P21,P24,R2,R7,R9,R13,R15,  
R17,R22,R26,T4,T8,T9,T14,T16,T21,T24,U1,U5,U9,U13,U15,  
U17,U22,U26,U29,V8,V21,V24,W4,W9,W22,W26,W29,Y5,Y6,  
Y8,Y21,AA1,AA4,AA7,AA10,AA12,AA14,AA16,AA18,AA20,  
AA21,AA23,AA24,AA25,AA29,AB9,AB11,AB13,AB15,AB17,  
AB19,AB21,AB26,AC4,AC8,AC11,AC14,AC17,AC20,AC23,  
AC27,AC28,AE1,AE4,AE7,AE10,AE13,AE16,AE19,AE22,AE25,  
AE28,AG3,AG6,AG9,AG12,AG15,AG18,AG21,AG24,AG27,AJ1,  
AJ3,AJ7,AJ10,AJ11,AJ12,AJ18,AJ20,AJ23,AJ26,AJ27  
154  
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Ballout and Package Information  
Table 36.  
Ballout Table  
Row  
Column  
Signal Name  
Row  
Column  
Signal Name  
Row  
Column  
Signal Name  
E
5
ADDID[0]  
ADDID[1]  
ADDID[2]  
ADDID[3]  
ADDID[4]  
ADDID[5]  
ADDID[6]  
ADDID[7]  
ADS#  
AA  
N
B
B
L
22  
24  
7
DPWR#  
G
K
K
J
3
DVOCD[11]  
DVOCD[2]  
DVOCD[3]  
DVOCD[4]  
DVOCD[5]  
DVOCD[6]  
DVOCD[7]  
DVOCD[8]  
DVOCD[9]  
DVOCFLDSTL  
DVOCHSYNC  
DVOCVSYNC  
DVODETECT  
DVORCOMP  
EXTTS_0  
GCLKIN  
F
5
DRDY#  
3
E
3
DREFCLK  
RSVD  
2
E
2
17  
2
6
G
F
5
DVOBBLANK#  
DVOBCCLKINT  
DVOBCINTR#  
DVOBCLK  
DVOBCLK#  
DVOBD[0]  
DVOBD[1]  
DVOBD[10]  
DVOBD[11]  
DVOBD[2]  
DVOBD[3]  
DVOBD[4]  
DVOBD[5]  
DVOBD[6]  
DVOBD[7]  
DVOBD[8]  
DVOBD[9]  
DVOBFLDSTL  
DVOBHSYNC  
DVOBVSYNC  
DVOCBLANK#  
DVOCCLK  
DVOCCLK#  
DVOCD[0]  
DVOCD[1]  
DVOCD[10]  
J
5
4
M
G
P
P
R
R
M
M
R
R
P
P
N
P
N
N
M
T
3
H
H
H
H
H
K
L
2
G
F
6
2
1
6
3
3
L
28  
7
4
4
F
RSVD  
3
5
AE  
AD  
C
D
N
P
29  
29  
9
BCLK  
5
6
BCLK#  
1
5
BLUE  
5
L
7
9
BLUE#  
6
D
D
Y
C
D
F
1
25  
28  
23  
15  
26  
6
BNR#  
4
6
BPRI#  
6
3
M
F
BREQ0#  
CPURST#  
DBSY#  
5
8
GREEN  
5
8
GREEN#  
GVREF  
M
B
2
1
DDCACLK  
DDCADATA  
RSVD  
2
U
V
U
T
28  
28  
27  
27  
27  
25  
26  
24  
25  
23  
25  
HA[10]#  
G
B
9
3
HA[11]#  
4
2
HA[12]#  
C
M
J
5
RSVD  
6
HA[13]#  
28  
25  
25  
25  
19  
5
DEFER#  
DINV[0]#  
DINV[1]#  
DINV[2]#  
DINV[3]#  
DPMS  
T
5
V
U
V
Y
V
V
W
HA[14]#  
L
3
HA[15]#  
E
J
3
HA[16]#  
B
J
2
HA[17]#  
G
D
Y
K
K
H
5
HA[18]#  
1
HA[19]#  
23  
DPSLP#  
6
HA[20]#  
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Intel 82854 Graphics Memory Controller Hub (GMCH)  
Row  
Column  
Signal Name  
Row  
Column  
Signal Name  
Row  
Column  
Signal Name  
Y
25  
27  
24  
23  
27  
27  
28  
28  
27  
23  
26  
28  
25  
28  
27  
23  
24  
24  
26  
26  
22  
28  
22  
27  
25  
23  
27  
26  
23  
26  
HA[21]#  
HA[22]#  
HA[23]#  
HA[24]#  
HA[25]#  
HA[26]#  
HA[27]#  
HA[28]#  
HA[29]#  
HA[3]#  
F
25  
26  
27  
23  
25  
27  
25  
28  
27  
24  
28  
26  
22  
26  
26  
24  
23  
28  
21  
21  
24  
23  
22  
25  
24  
24  
27  
20  
23  
22  
HD[16]#  
HD[17]#  
HD[18]#  
HD[19]#  
HD[2]#  
B
F
F
C
C
G
E
G
E
G
D
F
C
C
F
B
G
E
L
23  
23  
21  
20  
21  
18  
19  
28  
20  
17  
20  
19  
19  
17  
17  
19  
16  
16  
27  
16  
17  
16  
18  
23  
25  
24  
28  
27  
22  
18  
HD[43]#  
HD[44]#  
HD[45]#  
HD[46]#  
HD[47]#  
HD[48]#  
HD[49]#  
HD[5]#  
AA  
W
W
W
Y
F
B
H
K
E
G
F
HD[20]#  
HD[21]#  
HD[22]#  
HD[23]#  
HD[24]#  
HD[25]#  
HD[26]#  
HD[27]#  
HD[28]#  
HD[29]#  
HD[3]#  
AA  
W
AB  
P
D
G
C
B
G
C
E
L
HD[50]#  
HD[51]#  
HD[52]#  
HD[53]#  
HD[54]#  
HD[55]#  
HD[56]#  
HD[57]#  
HD[58]#  
HD[59]#  
HD[6]#  
Y
HA[30]#  
HA[31]#  
HA[4]#  
AB  
T
T
HA[5]#  
R
HA[6]#  
U
HA[7]#  
U
HA[8]#  
G
B
B
G
C
C
D
C
E
D
J
HD[30]#  
HD[31]#  
HD[32]#  
HD[33]#  
HD[34]#  
HD[35]#  
HD[36]#  
HD[37]#  
HD[38]#  
HD[39]#  
HD[4]#  
R
HA[9]#  
T
HADSTB[0]#  
HADSTB[1]#  
HAVREF  
HCCVREF  
HD[0]#  
AA  
Y
C
E
D
C
L
HD[60]#  
HD[61]#  
HD[62]#  
HD[63]#  
HD[7]#  
Y
K
H
HD[1]#  
H
HD[10]#  
HD[11]#  
HD[12]#  
HD[13]#  
HD[14]#  
HD[15]#  
L
HD[8]#  
K
J
HD[9]#  
G
K
J
HDSTBN[0]#  
HDSTBN[1]#  
HDSTBN[2]#  
HDSTBN[3]#  
G
E
B
HD[40]#  
HD[41]#  
HD[42]#  
C
E
D
J
H
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Ballout and Package Information  
Row  
Column  
Signal Name  
Row  
Column  
Signal Name  
Row  
Column  
Signal Name  
K
D
E
E
K
J
27  
26  
21  
18  
21  
21  
17  
27  
28  
7
HDSTBP[0]#  
HDSTBP[1]#  
HDSTBP[2]#  
HDSTBP[3]#  
HDVREF[0]  
HDVREF[1]  
HDVREF[2]  
HIT#  
H
M
B
B
H
K
D
E
E
F
10  
25  
20  
18  
28  
28  
14  
13  
10  
10  
14  
15  
15  
13  
14  
14  
14  
13  
12  
12  
12  
11  
12  
11  
11  
10  
9
HSYNC  
HTRDY#  
HXRCOMP  
HXSWING  
HYRCOMP  
HYSWING  
RSVD  
T
7
MDDCDATA  
MDVICLK  
MDVIDATA  
MI2CCLK  
MI2CDATA  
NC  
N
7
M
K
6
7
N
6
AJ  
AH  
B
29  
29  
29  
29  
28  
28  
9
J
NC  
N
N
U
U
V
U
V
W
W
V
W
T
RSVD  
NC  
HITM#  
RSVD  
A
NC  
HL[0]  
RSVD  
AJ  
A
NC  
4
HL[1]  
G
E
C
C
F
RSVD  
NC  
4
HL[10]  
RSVD  
AA  
AJ  
AJ  
A
NC  
3
HL[2]  
RSVD  
4
NC  
3
HL[3]  
RSVD  
2
NC  
2
HL[4]  
RSVD  
2
NC  
6
HL[5]  
E
C
B
H
E
C
G
G
E
C
G
H
C
A
P
RSVD  
AH  
B
1
NC  
6
HL[6]  
RSVD  
1
NC  
7
HL[7]  
RSVD  
G
8
RSVD  
RSVD  
RSVD  
PSWING  
PWROK  
RCVENIN#  
RCVENOUT#  
RED  
3
HL[8]  
RSVD  
F
8
V
P
T
5
HL[9]  
RSVD  
A
5
27  
2
HLOCK#  
HLRCOMP  
HLSTB  
RSVD  
U
2
RSVD  
J
11  
16  
15  
7
W
V
W
R
P
R
R
T
3
RSVD  
AC  
AC  
A
2
HLSTB#  
HLVREF  
HREQ[0]#  
HREQ[1]#  
HREQ[2]#  
HREQ[3]#  
HREQ[4]#  
RSVD  
1
RSVD  
28  
25  
23  
25  
23  
RSVD  
A
8
RED#  
REFSET  
RS[0]#  
RS[1]#  
RS[2]#  
LCLKCTLA  
LCLKCTLB  
RSVD  
E
8
6
N
23  
26  
27  
10  
7
P
MDDCCLK  
M
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Intel 82854 Graphics Memory Controller Hub (GMCH)  
Row  
Column  
Signal Name  
Row  
Column  
Signal Name  
Row  
Column  
Signal Name  
AD  
F
28  
12  
12  
12  
5
RSTIN#  
RSVD  
AB  
AC  
AB  
AC  
AC  
AD  
AD  
AC  
AC  
AE  
AE  
AE  
AH  
AD  
AD  
AD  
AH  
AH  
AF  
AE  
AG  
AE  
AF  
AH  
AF  
AH  
AF  
AG  
AH  
AG  
4
SCK[5]#  
SCKE[0]  
SCKE[1]  
SCKE[2]  
SCKE[3]  
SCS[0]#  
SCS[1]#  
SCS[2]#  
SCS[3]#  
SDM[0]  
SDM[1]  
SDM[2]  
SDM[3]  
SDM[4]  
SDM[5]  
SDM[6]  
SDM[7]  
SDM[8]  
SDQ[0]  
AF  
AH  
AD  
AF  
AE  
AH  
AH  
AG  
AF  
AG  
AD  
AH  
AF  
AH  
AH  
AG  
AF  
AE  
AD  
AE  
AH  
AG  
AD  
AH  
AG  
AF  
AH  
AF  
AH  
AH  
4
SDQ[2]  
7
7
SDQ[20]  
SDQ[21]  
SDQ[22]  
SDQ[23]  
SDQ[24]  
SDQ[25]  
SDQ[26]  
SDQ[27]  
SDQ[28]  
SDQ[29]  
SDQ[3]  
D
RSVD  
7
9
B
RSVD  
9
10  
11  
10  
11  
13  
14  
11  
12  
2
AA  
L
RSVD  
10  
23  
26  
22  
25  
5
4
RSVD  
C
4
GST[0]  
RSVD  
F
3
D
3
RSVD  
C
3
GST[1]  
RSVD  
B
3
6
F
2
RSVD  
9
D
2
RSVD  
12  
19  
21  
24  
28  
15  
2
13  
13  
16  
17  
19  
20  
18  
18  
18  
19  
3
SDQ[30]  
SDQ[31]  
SDQ[32]  
SDQ[33]  
SDQ[34]  
SDQ[35]  
SDQ[36]  
SDQ[37]  
SDQ[38]  
SDQ[39]  
SDQ[4]  
C
2
GST[2]  
RSVD  
B
2
D
7
RSVD  
AD  
AD  
AC  
AB  
AA  
AC  
AB  
AC  
AD  
AC  
AD  
AB  
AB  
AA  
22  
20  
24  
2
SBA[0]  
SBA[1]  
SCAS#  
SCK[0]  
SCK[0]#  
SCK[1]  
SCK[1]#  
SCK[2]  
SCK[2]#  
SCK[3]  
SCK[3]#  
SCK[4]  
SCK[4]#  
SCK[5]  
3
SDQ[1]  
2
7
SDQ[10]  
SDQ[11]  
SDQ[12]  
SDQ[13]  
SDQ[14]  
SDQ[15]  
SDQ[16]  
SDQ[17]  
SDQ[18]  
SDQ[19]  
26  
25  
3
8
5
4
20  
20  
22  
22  
20  
19  
21  
SDQ[40]  
SDQ[41]  
SDQ[42]  
SDQ[43]  
SDQ[44]  
SDQ[45]  
SDQ[46]  
4
7
2
6
2
8
23  
24  
3
8
9
10  
158  
D15343-003  
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Ballout and Package Information  
Row  
Column  
Signal Name  
Row  
Column  
Signal Name  
Row  
Column  
Signal Name  
AG  
AE  
AH  
AE  
AE  
AH  
AG  
AF  
AF  
AG  
AH  
AE  
AG  
AF  
AG  
AG  
AF  
AE  
AD  
AG  
AE  
AE  
AG  
AH  
AE  
AH  
AF  
AF  
AD  
AG  
22  
23  
23  
2
SDQ[47]  
SDQ[48]  
SDQ[49]  
SDQ[5]  
SDQ[50]  
SDQ[51]  
SDQ[52]  
SDQ[53]  
SDQ[54]  
SDQ[55]  
SDQ[56]  
SDQ[57]  
SDQ[58]  
SDQ[59]  
SDQ[6]  
SDQ[60]  
SDQ[61]  
SDQ[62]  
SDQ[63]  
RSVD  
AG  
AH  
AH  
AE  
AH  
AE  
AH  
AH  
AD  
AC  
AD  
AC  
AD  
AB  
AD  
AD  
AD  
AC  
AD  
AD  
AC  
AC  
AD  
AC  
AF  
AD  
AB  
AJ  
2
SDQS[0]  
SDQS[1]  
SDQS[2]  
SDQS[3]  
SDQS[4]  
SDQS[5]  
SDQS[6]  
SDQS[7]  
SDQS[8]  
SMA[0]  
AC  
AD  
W
AA  
AA  
T
21  
25  
21  
19  
17  
17  
17  
16  
16  
16  
15  
15  
15  
15  
14  
14  
14  
14  
13  
13  
9
SRAS#  
SWE#  
VCC  
5
8
12  
17  
21  
24  
27  
15  
18  
14  
19  
5
VCC  
24  
25  
23  
23  
25  
25  
26  
26  
28  
28  
4
VCC  
VCC  
P
VCC  
U
VCC  
R
VCC  
N
VCC  
SMA[1]  
AA  
T
VCC  
SMA[10]  
SMA[11]  
SMA[12]  
SMA[2]  
VCC  
P
VCC  
5
J
VCC  
13  
17  
11  
13  
8
U
VCC  
26  
26  
27  
27  
14  
14  
17  
16  
14  
15  
3
SMA[3]  
R
VCC  
SMA[4]  
N
VCC  
SMA[5]  
H
VCC  
SMA[6]  
T
VCC  
7
SMA[7]  
P
VCC  
RSVD  
6
SMA[8]  
B
VCCADAC  
VCCADAC  
VCCADPLLA  
VCCADPLLB  
VCCAGPLL  
VCCAHPLL  
VCCA  
VCCASM  
VCCASM  
VCC1_5  
RSVD  
5
SMA[9]  
A
9
RSVD  
16  
12  
11  
10  
1
SMAB[1]  
SMAB[2]  
SMAB[4]  
SMAB[5]  
SMRCOMP  
SMVREF_0  
SMVSWINGH  
SMVSWINGL  
A
6
RSVD  
B
16  
2
RSVD  
Y
SDQ[7]  
RSVD  
D
29  
11  
1
16  
17  
6
A
RSVD  
24  
19  
22  
AF  
AD  
B
SDQ[8]  
SDQ[9]  
AJ  
1
5
AJ  
15  
D15343-003  
159  
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®
Intel 82854 Graphics Memory Controller Hub (GMCH)  
Row  
Column  
Signal Name  
Row  
Column  
Signal Name  
Row  
Column  
Signal Name  
B
J
14  
13  
13  
9
VCC1_5  
VCC1_5  
VCC1_5  
VCCDVO  
VCCDVO  
VCCDVO  
VCCDVO  
VCCDVO  
VCCDVO  
VCCDVO  
VCCDVO  
VCCDVO  
VCCDVO  
VCCDVO  
VCCDVO  
VCCDVO  
VCCDVO  
VCCDVO  
VCCDVO  
VCCGPIO  
VCCGPIO  
VCCHL  
AJ  
AG  
AF  
AC  
AF  
AJ  
AF  
AB  
AJ  
AF  
AB  
AF  
AB  
AJ  
AB  
AF  
AB  
AJ  
AA  
AF  
AB  
AA  
AB  
AJ  
AF  
Y
6
VCCQSM  
VCCSM  
VCCSM  
VCCSM  
VCCSM  
VCCSM  
VCCSM  
VCCSM  
VCCSM  
VCCSM  
VCCSM  
VCCSM  
VCCSM  
VCCSM  
VCCSM  
VCCSM  
VCCSM  
VCCSM  
VCCSM  
VCCSM  
VCCSM  
VCCSM  
VCCSM  
VCCSM  
VCCSM  
VCCSM  
VCCSM  
VCCSM  
VCCSM  
VCCSM  
AB  
AA  
AJ  
Y
6
VCCSM  
VCCSM  
VCCSM  
VCCSM  
VCCSM  
VCCSM  
VCCSM  
VCCSM  
VCC2_5  
VCC2_5  
VCC2_5  
VCC2_5  
VSS  
29  
29  
29  
27  
25  
24  
22  
21  
21  
20  
18  
18  
17  
16  
15  
14  
13  
13  
12  
12  
11  
10  
9
6
G
P
M
K
R
N
M
L
5
4
9
AF  
AB  
AG  
AC  
A
3
9
3
8
1
8
1
8
12  
10  
10  
9
8
D
J
8
B
H
E
M
J
7
F
6
AA  
W
U
29  
29  
29  
29  
29  
29  
29  
29  
29  
28  
28  
28  
28  
27  
27  
27  
27  
27  
4
VSS  
4
VSS  
E
N
J
4
N
VSS  
1
L
VSS  
1
J
VSS  
E
A
A
V
W
U
V
U
W
Y
V
AJ  
1
G
VSS  
4
E
VSS  
3
C
VSS  
9
AE  
AC  
E
VSS  
8
VCCHL  
VSS  
8
VCCHL  
VSS  
7
VCCHL  
9
D
VSS  
6
VCCHL  
9
AJ  
AG  
AC  
F
VSS  
5
VCCHL  
AB  
AA  
Y
8
VSS  
1
VCCHL  
8
VSS  
1
VCCHL  
7
VSS  
8
VCCQSM  
AF  
6
A
VSS  
160  
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Ballout and Package Information  
Row  
Column  
Signal Name  
Row  
Column  
Signal Name  
Row  
Column  
Signal Name  
AJ  
AB  
W
U
26  
26  
26  
26  
26  
26  
26  
26  
26  
25  
25  
25  
25  
24  
24  
24  
24  
24  
24  
24  
24  
24  
24  
23  
23  
23  
23  
23  
22  
22  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
U
22  
22  
22  
22  
22  
22  
22  
21  
21  
21  
21  
21  
21  
21  
21  
21  
21  
21  
20  
20  
20  
20  
20  
19  
19  
19  
19  
19  
18  
18  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
AA  
J
18  
18  
18  
17  
17  
17  
17  
17  
17  
17  
17  
16  
16  
16  
16  
16  
16  
15  
15  
15  
15  
15  
15  
15  
14  
14  
14  
14  
14  
13  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
R
N
F
L
AC  
AB  
U
R
J
N
F
L
C
R
J
AG  
AB  
AA  
Y
N
G
H
AE  
AA  
D
D
A
V
AE  
AA  
T
A
T
AG  
AA  
V
P
M
H
P
J
T
D
F
P
A
AG  
AB  
U
M
K
AJ  
AC  
AA  
J
H
R
F
N
B
F
H
AJ  
AC  
AA  
D
AE  
AB  
H
D
AC  
AA  
T
D
A
A
P
AE  
W
AJ  
AG  
J
AE  
D15343-003  
161  
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®
Intel 82854 Graphics Memory Controller Hub (GMCH)  
Row  
Column  
Signal Name  
Row  
Column  
Signal Name  
Row  
Column  
Signal Name  
AB  
U
13  
13  
13  
13  
13  
13  
13  
13  
12  
12  
12  
12  
11  
11  
11  
11  
11  
11  
10  
10  
10  
10  
10  
9
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
L
9
9
8
8
8
8
8
8
8
7
7
7
7
7
7
7
7
7
6
6
6
5
5
5
4
4
4
4
4
4
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
K
4
VSS  
E
G
D
4
VSS  
R
AC  
Y
4
VSS  
N
AJ  
AG  
R
3
VSS  
H
V
3
VSS  
F
T
2
VSS  
D
P
AJ  
AE  
AA  
U
1
VSS  
A
K
1
VSS  
AJ  
AG  
AA  
J
H
1
VSS  
AJ  
AE  
AA  
R
1
VSS  
L
1
VSS  
G
C
1
VSS  
AJ  
AC  
AB  
H
1
VSS  
M
J
B
8
VSSADAC  
VSSA  
VSYNC  
VTTHF  
VTTHF  
VTTHF  
VTTHF  
VTTHF  
VTTLF  
VTTLF  
VTTLF  
VTTLF  
VTTLF  
VTTLF  
VTTLF  
VTTLF  
VTTLF  
B
11  
9
G
J
F
E
V
29  
29  
29  
24  
22  
29  
29  
29  
29  
26  
22  
22  
22  
22  
D
C
M
H
AJ  
AE  
AA  
J
AG  
Y
A
L
A
Y
AB  
Y
C
U
AG  
AB  
W
U
B
K
9
AE  
AC  
AA  
W
T
F
9
A
9
V
T
9
T
R
9
P
N
9
N
M
162  
D15343-003  
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Ballout and Package Information  
Row  
Column  
Signal Name  
H
U
R
N
L
22  
21  
21  
21  
21  
20  
20  
19  
18  
18  
16  
15  
VTTLF  
VTTLF  
VTTLF  
VTTLF  
VTTLF  
VTTLF  
VTTLF  
VTTLF  
VTTLF  
VTTLF  
VTTLF  
VTTLF  
H
A
J
H
A
H
G
D15343-003  
163  
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®
Intel 82854 Graphics Memory Controller Hub (GMCH)  
9.2  
Package Mechanical Information  
Figure 13 through Figure 15 provide detail on the package information and dimensions of the  
®
®
Intel 82854 GMCH. The Intel 82854 GMCH comes in a Micro-FCBGA package, which is  
similar to the mobile processors. The package consists of a silicon die mounted face down on an  
organic substrate populated with solder balls on the bottom side. Capacitors may be placed in the  
area surrounding the die. Because the die-side capacitors are electrically conductive, and only  
slightly shorter than the die height, care should be taken to avoid contacting the capacitors with  
electrically conductive materials. Doing so may short the capacitors and possibly damage the  
device or render it inactive.  
The use of an insulating material between the capacitors and any thermal solution should be  
considered to prevent capacitor shorting. An exclusion, or keepout area, surrounds the die and  
capacitors, and identifies the contact area for the package. Care should be taken to avoid contact  
with the package inside this area.  
®
Figure 13.  
Intel 82854 GMCH Micro-FCBGA Package Dimensions (Top View)  
164  
D15343-003  
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Ballout and Package Information  
®
Figure 14.  
Intel 82854 GMCH Micro-FCBGA Package Dimensions (Side View)  
D15343-003  
165  
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®
Intel 82854 Graphics Memory Controller Hub (GMCH)  
®
Figure 15.  
Intel 82854 GMCH Micro-FCBGA Package Dimensions (Bottom View)  
166  
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