Cypress CY8C29x66 User Manual

Power Management - Low-Cost, Two-Cell  
Li-Ion/Li-Pol Battery Charger with  
Cell-Balancing Support  
AN2309  
Author: Oleksandr Karpin  
Associated Project: Yes  
Associated Part Family: CY8C24x23A, CY8C24794, CY8C27x43, CY8C29x66  
Software Version: PSoC Designer5.0 SP1  
Associated Application Notes: AN2107, AN2258, AN2267, AN2294  
Application Note Abstract  
This application note describes a low cost, two-cell Li-Ion/Li-Pol battery charger. An effective cell-balancing algorithm during  
both charge and discharge phases is presented. This charger can be used either as a standalone application to charge a  
battery pack with two serial connected Li-Ion/Li-Pol batteries or embedded in residential, office, and industrial applications.  
This application note describes a two-cell Li-Ion/Li-Pol  
Introduction  
battery charger. An effective cell-balancing algorithm is  
A modern portable system requires more operating voltage  
designed. It avoids the issues that appear in battery packs  
than a single-cell Lithium-ion (Li-Ion) or Lithium-polymer (Li-  
with two cells in series. Through modification of the  
Pol) battery can provide. A serial connection results in a  
configuration parameters, the cell-balancing algorithm can  
pack voltage equal to the sum of the cell voltages. To  
easily be adapted for various applications and selected  
batteries. The unique architecture of the PSoC® device  
increase the battery pack capacity, the cells are connected  
in parallel. For many applications, two cells in series are  
provides an integrated hardware solution for a two-cell  
sufficient, with one or more cells in parallel. This  
battery charger and a flexible μC-based, cell-balancing  
combination gives nominal voltage and the necessary power  
algorithm with minimal external components at a very  
for laptop computers and medical and industrial  
affordable price. The CY8C24x23A PSoC device family  
applications. Problems can occur when the cells have  
used in this implementation reduces the total device cost  
different capacities or charge levels. During charging or  
even further.  
discharging, the cells in the battery pack do not have  
When you want to use algorithms for the latest charging or  
cell-balancing technologies, only the firmware needs to be  
modified. PSoC Designer’s in-circuit and self-programming  
capabilities make these operations simple.  
matched voltage every cell. Therefore, the battery pack is  
not balanced. The unbalanced charge between cells causes  
the following problems:  
.
Reduced overall battery pack capacity to the value of  
the cell with the least capacity. During the charge  
process, this cell reaches the maximum charge level  
before the other cells, and during the discharge process  
this cell is depleted before the other cells in the pack.  
Specifications for a two-cell Li-Ion/Li-Pol battery charger with  
cell-balancing support are listed in Table 1 on page 2.  
.
.
Reduced overall battery pack life. The charge or  
discharge of cells at different values increases pack  
imbalance.  
Cell damage, which occurs if the charger monitors only  
the summary voltage. For example, if the lower cell has  
a capacity deficiency of at least 10 percent, its cell  
voltage begins to rise into the dangerous area above  
4.3 volts. This can result in additional degradation of the  
cell or a safety system response that greatly reduces  
pack capacity.  
November 25, 2007  
Document No. 001-17394 Rev. *B  
- 1 -  
AN2309  
The balancing circuit is represented by (R1, Q1) and (R2,  
Q2). These transistors and resistors dissipate energy and  
control the amount of balancing current.  
.
Temperature gradient across the battery pack.  
Temperature mismatches of 15 degrees Celsius can  
cause up to 5- percent capacity differential among cells.  
Such a temperature gradient is relatively common in  
densely packed products, where multiple heat sources  
are located close to the battery pack. An example of  
this is a laptop computer.  
If cell balancing is performed during the charge phase, the  
charge current on the balanced cells is reduced on the  
shunted current value (Equation 7 and Equation 8) and  
remains unchanged on other cells:  
The main causes of variation in cell charge levels are:  
V
cellN  
Equation 7  
Equation 8  
I
.
Variations in self-discharge rates. Even at room  
temperature, two similar cells self-discharge at different  
rates, resulting in a mismatch. For example, one cell  
could lose 3 percent per month, while another cell loses  
a different amount.  
balN  
R
N
QN  
I
chargeN  
charge balN  
The value  
I
is the current that flows through the  
.
Variations in internal cell impedance. These impedance  
variations cause otherwise similar battery cells to have  
different charge acceptance levels. This error is minute  
(about 0.1 percent).  
balN  
balancing circuit of the cell N, and  
V
is the battery  
cellN  
electro chemical potential. The value  
R
is the balancing  
N
Cell balancing is achieved by connecting a parallel load to  
each cell that must be balanced. Typically, a series  
combination of a power transistor (MOSFET) and a current-  
limiting resistor are connected in parallel to each cell. If a  
cell has a higher voltage than the other cells, the bypass  
load to the cell is connected by closing the MOSFET so that  
a fraction of the charging current bypasses that cell. It is  
possible to balance the cells during the discharge phase, the  
charge phase, or both phases.  
resistor, and  
R
is the transistor resistance. The value  
QN  
is the charge current of cell N, and  
I
I
is  
chargeN  
the battery pack charge current.  
charge  
If cell balancing is performed during the discharge phase,  
the current that flows through the balancing circuit depends  
on the system load resistance. If the load resistance is high,  
by comparison with a balancing circuit resistance, most of  
the discharge current flows through the balancing circuit. But  
if the load resistance is low, most of the discharge current  
flows through the load, making the balancing operation less  
efficient.  
Balancing the charge levels among cells must be done  
during the charge or discharge phase. This balancing  
process is simple and has been well investigated. Balancing  
the cells’ capacity variation must be done during both the  
charge and discharge phases. Cells with different capacities  
must be charged or discharged by using an absolute value  
rather than a relative value. The process of balancing cell  
capacity variation is difficult to implement in practice and is  
not intuitively obvious.  
The current that flows through the balancing circuit is shown  
in Equation 7 and the equivalent discharge resistance is  
equated as:  
(R  
The charge in dV/dQ for Li-Ion batteries has a maximum  
level when the cells are nearly fully charged or discharged. It  
takes less time to correct voltage mismatch during this  
period of complete or nearly complete charge/discharge  
than during the middle period of battery charge/discharge.  
Thus, it is advisable to perform the balancing routine when  
the cells are nearly fully charged or nearly fully discharged.  
See also Cell-Balancing Algorithm on page 14. The cell-  
balancing technique is shown in Figure 1.  
N
QN  
load  
R
Equation 9  
dischargeN  
R
N
QN  
load  
The value  
R
is the equivalent discharge  
dischargeN  
resistance of the balanced cell N, and  
resistance.  
R
is the load  
load  
Components for the cell-balancing circuit are selected by  
taking the following factors into account:  
Figure 1. Cell-Balancing Technique Schematic  
.
Amount of Imbalance: This factor is described earlier  
in this section and consists of variations in capacity and  
charge level. Typically, cell imbalance is about 1  
percent. An imbalance as great as 5 percent to 15  
percent can occur only with a high temperature gradient  
or if a battery pack has been stored and not used for a  
long period of time.  
R1  
CELL1  
Charger,  
Monitor,  
Safety,  
Q1  
Fuel Gauge,  
Cell Balance  
Software  
Load  
R2  
Q2  
CELL2  
November 25, 2007  
Document No. 001-17394 Rev. *B  
- 3 -  
     
AN2309  
for most applications it is not necessary to use this  
algorithm.  
.
Cell Balancing Time: If C is the cell capacity and Vb is  
the battery voltage, and the requirement is to eliminate  
The cell-balancing technique is explained in detail in  
AN2258, “Cell Balancing in a Multi-Cell Li-Ion/Li-Pol Battery  
Charger.”  
the amount of imbalance  
balancing time, then the power dissipation on balancing  
circuit is:  
(in percent) in one hour of  
P
bal  
Two-Cell Battery Charger Hardware  
C
100%  
P
Equation 10  
Li-based batteries use a two-stage charge profile (activation  
and rapid-charge). If the battery voltage is less than 2.9 to  
3.0 volts per cell, the battery must be activated first. In the  
activation stage, the battery is charged with a constant  
current (0.05-0.15 CA, where CA is the nominal battery  
capacity) until the battery voltage reaches a predefined  
level. The activation charge time-out is set to 1.5 to 2 hours.  
The activation charge can diagnose battery health and  
identify troubles such as damaged or shorted cells.  
bal  
For example, balancing the cells for one hour with a  
battery capacity of 2000 mAh and an imbalance of 15  
percent results in the following approximate amount of  
power dissipation on the balancing circuit:  
2000mAh
Equation 11  
P
bal  
100%  
The rapid-charge stage starts after the activation charge  
finishes without error. This stage consists of two modes:  
constant current and constant voltage. When the battery  
voltage is less than the predefined level (4.1V or 4.2V  
depending on battery type), the charge is processed in  
constant current mode (0.5-1.0 CA). When the battery  
voltage reaches this level, the charge source switches to  
constant voltage mode and the charge process is terminated  
when the current drops below a predefined limit (0.07-  
0.2 CA).  
Thus, there is a tradeoff between the rate of balancing  
and power dissipation. Faster balancing provides more  
options and flexibility, but it also results in increased  
power dissipation, which increases cost and board  
space. The one charge/discharge period can be  
selected as a favorable time for cell balancing.  
.
Cell Capacity: If n is the count of cells connected in  
parallel, C is the cell capacity, and  
is the amount of  
imbalance in percent (capacity and charge level  
variation), then the highest required balancing current  
during one hour is the following:  
The rapid-charge stage must be protected by time limits.  
The rapid-charge time is limited to three hours. The charge  
profile for Li-Ion/Li-Pol batteries is shown in Figure 2. The  
technique to charge Li-Ion and Li-Pol batteries is explained  
in detail in AN2107 “A Multi-Chemistry Battery Charger.”  
C
I
Equation 12  
bal  
100%  
Figure 2. Li-Ion/Li-Pol Battery Charge Profile  
For example, the initial balancing level is:  
2000mAh
I
Equation 13  
bal  
100%  
If the balancing circuit resistance is set to equal 100Ω,  
then:  
I
Equation 14  
Equation 15  
bal  
P
Using a four hour discharge time and a two hour charge  
time during one complete discharge/charge cycle with full  
time cell balancing on both phases, 42 mA*(4+2)=252 mA  
is removed from one unbalanced cell. Therefore, the  
balancing level from this example can be removed during  
three discharge/charge cycles with a balancing circuit  
resistance of 100Ω or during one complete cycle with 40Ω.  
Legend:  
Ich - Battery charge current  
Iact - Battery activation charge current, 0.1-0.2 CA  
1
Irap - Battery rapid charge current, 0.7-1 CA  
2
Vb - Battery voltage  
For maximum cell balancing, use a balancing circuit  
resistance of 40Ω to 200Ω and perform cell balancing during  
both charge and discharge phases. Note that the overnight  
conditioning cell-balancing algorithm is not implemented in  
this project. The reason is that the CY8C24xxxA device  
used in this implementation does not have enough ROM  
memory space. If you choose another PSoC device family  
for the same project, the overnight conditioning cell-  
balancing algorithm can easily be added (see AN2258, “Cell  
Balancing in a Multi-Cell Li-Ion/Li-Pol Battery Charger”). But  
Vrs - Rapid start voltage, typically 3 V/cell  
3
4
- Constant-current / constant voltage switching point  
Vmax - Emergency shutdown voltage, 4.3 V/cell  
5
- Rapid charge termination current, typically 0.1 CA  
6
Trmax - Battery rapid charge maximum temperature, 45 o  
С
7
8
Trmin - Battery rapid charge minimum temperature, 0 o  
C
Tb - Battery temperature  
trch - Rapid charge termination time  
tcv - Constant voltage charge time  
November 25, 2007  
Document No. 001-17394 Rev. *B  
- 4 -  
 
AN2309  
A two-cell battery charger structure with cell-balancing support is shown in Figure 3. Similar battery charger structures are  
explained in detail in AN2258, AN2294, and AN2267. Note that the fuel gauge function can easily be added to this project  
without changing any hardware: It is only necessary to switch from the CY8C24423A to a PSoC device with more program  
memory. The main fuel gauge calculation parameters are described in AN2294, “The Li-Ion/Li-Pol Battery Charger with Fuel  
Gauge Function.  
Figure 3. Two-Cell Battery Charger with Cell-Balancing Support  
D1  
Q1  
POWER+  
C1  
R1  
R4  
Q2  
R5  
C4  
SERIAL_TX  
Li-Ion  
Battery  
Pack  
R7  
C5  
C6  
C7  
R6  
R8  
Q3  
RS_TX  
(For Debug  
Only)  
R9  
Q4  
PWM  
Vbias  
bal2  
Cell2  
CPU  
R10  
bal2  
bal1  
R11  
R13  
VREF  
Vref  
TIMERs  
R12  
R14  
Q5  
Vbias  
bal1  
AMUX  
AMUX  
Cell1  
Incremental  
ADC  
INAMP  
R17  
R18  
PSoC internals  
R19  
T
Vbias  
Vref  
R15  
Vbias  
R16  
R21  
C8  
R24  
R20  
R23  
Vref  
POWER-  
Current Sense  
The following abbreviations are used in Figure 3:  
Incremental ADC: Analog-to-digital converter to digitize the  
analog signals.  
RS_TX: RS232 transmitter for debug purposes (uses  
external level translator). It monitors temperature, voltage,  
current and cell-balancing statistics. RS_TX is used only in  
the debug stage and may be removed in the released  
product.  
INAMP: Instrumentation amplifier to measure charge  
voltage, current, and temperature.  
AMUX: Analog multiplexers.  
Figure 3 also contains a two-cell Li-Ion battery pack, a linear  
regulator (based on Q1, Q2), a cell-balancing circuit (based  
on Q4, Q5), a current-sense resistor, and other elements  
that allow the PSoC device to use and interpret battery  
current, voltage, and temperature.  
CPU: Central processor to implement charge and cell-  
balancing algorithms, and perform charge control functions.  
PWM: Pulse width modulator to regulate the charge current.  
VREF: Reference voltage source.  
TIMERs: Several timers are used by the CPU in charge and  
cell-balancing algorithms.  
November 25, 2007  
Document No. 001-17394 Rev. *B  
- 5 -  
   
AN2309  
The resistive network (R6, R7, R12, R13, R15, R16, and  
R18-R22) and the reference voltage Vbias from the divider on  
R29 and D8, allow transformation of the battery current,  
voltage, and temperature into signals suitable for the PSoC  
device. The 100 mΩ resistor R23 is a current-sense resistor  
that is in the battery pack current path.  
Device Schematic  
The schematics shown in Figure 4 on page 7 and Figure 5  
on page 8 constitute a complete two-cell battery charger.  
A signal from the PWM goes to the RC-filter, which consists  
of resistor R4 and capacitor C4. A constant voltage signal  
proportional to the PWM duty cycle value forms at the Q2  
gate. Therefore, the PWM and RC-filter is a simple  
implementation of a PWM-DAC. The bipolar transistor Q2 is  
driven by an analog signal from the PWM-DAC. This bipolar  
transistor and resistors R1 and R5 form a resistive divider.  
Therefore, the voltage drop on the resistor R1 is directly  
dependent on the Q2 base voltage; that is, on the PWM-  
DAC level. The MOSFET transistor Q1 is driven by the  
voltage drop on resistor R1 and regulates the battery charge  
current. The PWM period was set to 2048 for an accurate  
current level setting, and can easily be adjusted in the  
firmware.  
The two-cell charger user interface uses two LEDs to  
display internal status. In this application configuration, the  
green LED indicates the charge phase, and the yellow LED  
indicates the discharge phase. The Error state is indicated  
when both LEDs are on and the idle status is indicated when  
both LEDs are off.  
To provide a processor power supply from a high voltage  
level, the linear current regulator U2 is used. Alternatively, a  
switching regulator can be used, as explained in AN2258.  
Or, the regulated step-down converter from an internal SMP  
can be used, as explained in AN2180, “Using the PSoC  
Switch Mode Pump in a Step-Down Converter.” An external  
voltage supply is applied to the connector J4. The SW1  
switch allows the device to be disconnected from the  
external power supply. Two diodes in the D6 package allow  
the processor to operate during the charge phase from the  
external power supply and during the discharge phase from  
the battery pack power supply. The external load is  
connected to the connector J3 LOAD. The diodes D4 and  
D5 provide an uninterrupted power supply (UPS) to the  
LOAD connector, much as D6 provides power to the  
processor. The switch-on transistors Q6 and Q7 allow the  
power supply to be disconnected from the LOAD connector  
and protect the battery from overdischarge. This switch is  
optional and can be removed to reduce total device cost  
further. The ground level is connected to the external ground  
level POWER (during the charge phase or discharge phase)  
and to the battery pack ground that follows the current-  
sense resistor. Only in this way can the charge battery pack  
current and the total battery pack discharge current pass  
through the current-sense resistor. This ground-level  
position is used to supplement the battery fuel gauging  
functionality in the PSoC software, as shown in AN2294.  
Note that the charger proposed in this application note is  
based on a linear current regulator. The advantages of this  
regulator are low cost and small size. However, to charge a  
battery with a capacity of over 1000 mAh with a charge  
current of 1 CA (where CA is the nominal battery capacity)  
the linear regulator can be nonoptimal due to the large  
voltage drop on the MOSFET and the consequent high  
MOSFET temperature. In this case, a step down regulator is  
preferable to a linear current regulator. The step-down  
regulator is explained in detail in Application Notes AN2107  
Diode D1 is used to prevent a reverse current that can  
discharge the battery when the charger is disconnected from  
the supply voltage. The cell-balancing circuit is represented  
by MOSFETs Q4 and Q5, and by balancing resistors R11  
and R14. The MOSFETs are directly controlled from the  
PSoC device port (high level - close, low level - open). The  
resistors R8-R10 and the bipolar transistor Q3 act as a level  
translator and allow opening the MOSFET Q4 by a logic  
signal from the PSoC.  
November 25, 2007  
Document No. 001-17394 Rev. *B  
- 6 -  
AN2309  
Figure 4. Two-Cell Battery Charger Schematic CPU, Cell Balancing, and Measuring Equipment  
Q1  
IRLML6402  
D1  
POWER+  
BAT+  
C1  
R1  
C2  
47uF  
C3  
MBR360  
+
0.01uF  
10K  
1uF CER  
R4 1K  
Q2  
DRIVE  
BC817  
C4  
R5  
0.1uF  
15K  
R7 150K 0.1%  
V2  
C5  
0.01u  
R6  
50K 0.1%  
VCC  
U1  
R8  
1M  
28  
Vcc  
1
2
3
4
27  
26  
25 V2  
Vbias  
Vi2  
Vi1  
Tbat  
P0[7]  
P0[5]  
P0[3]  
P0[1]  
P0[6]  
P0[4]  
P0[2]  
P0[0]  
TP1  
Q4  
IRLML6402  
Vref  
V1  
24 BAT_GND  
R9  
5
6
7
8
23  
22  
21  
20  
Q3  
BC817  
BAL2  
P2[7]  
P2[5]  
P2[3]  
P2[1]  
P2[6]  
P2[4]  
P2[2]  
P2[0]  
330R  
R10  
10K  
R11  
LED_YELLOW  
LED_GREEN  
100  
9
19  
XRES  
SMP  
Xres  
10  
11  
12  
13  
18  
17  
16  
15  
J1  
P1[7]  
P1[5]  
P1[3]  
P1[1]  
P1[6]  
P1[4]  
P1[2]  
P1[0]  
BAT2  
1
2
3
4
5
BAL1  
BAL2  
DRIVE  
LOAD_EN  
R13 150K 0.1%  
V1  
BAT1  
GND  
TERMO  
14  
C6  
0.01u  
R12  
50K 0.1%  
Vss  
R14  
100  
BAT_CON  
CY8C24423A  
Vbias  
J2  
VCC  
1
2
3
4
5
Q5  
IRLML2502  
BAL1  
XRES  
TX  
CALIBRATION  
R17  
1M  
ISSP/DEBUG  
Vref  
R18 150K 0.1%  
BAT_GND  
C7  
0.01u  
R19  
R22  
10K  
R15  
R16  
50K 0.1%  
Tbat  
1M 1%  
1M 1%  
Vbias  
R24  
Vi2  
Vi1  
C8 0.1u  
10K 1%  
R20  
200K 1%  
R21  
200K 1%  
R23  
Vref  
POWER-  
100mOh 1%  
November 25, 2007  
Document No. 001-17394 Rev. *B  
- 7 -  
 
AN2309  
Figure 5. Two-Cell Battery Charger Schematic Power Supply and User Interface  
VCC  
Close to PSoC  
VCC  
SW1  
J4  
+
R29  
1K  
POWER+  
POWER-  
1
2
C9  
C10  
+
C15  
0.1u  
Vbias  
POWER 12V DC  
100u 16V  
0.1u 16V  
D8  
BAS16  
D6  
VCC  
BAT+  
U2 L78L05/TO  
1
3
R30  
33  
IN  
OUT  
R28  
470  
D7  
POWER+  
BAT54C  
C12  
0.33u 16V  
C11  
C13  
+
C14  
0.1u  
+
100u 16V  
22u  
POWER  
PSoC  
J3  
D4  
Q6  
1
2
POWER+  
BAT+  
MBR360  
D5  
R25  
1M  
IRLML6402  
LOAD  
MBR360  
R26  
R2  
D2  
Q7  
BC817  
LOAD_EN  
LED_YELLOW  
LED_GREEN  
470  
330R  
R27  
10K  
LED  
D3  
R3  
470  
LED  
The ADC resolution is set to 12 bits, and the integration time  
is adjusted to be precisely equal to the integer number of the  
PWM signal. All of the switched capacitor user modules use  
the same column frequency to eliminate aliasing problems.  
In this project, the analog ground bias was set to bandgap or  
1.3V (RefMux is BandGap ± BandGap).  
PSoC Device Internals  
The internal structure of the PSoC device is shown in Figure  
6 on page 9. The PWM is placed on DBB01 and DCB02.  
The module is configured in the software as an 11-bit PWM,  
which provides for a sufficient number of regulation steps.  
The TIMER User Module is based on the internal sleep  
timer and configured to generate interrupts every one  
second. This real clock is used to calculate other time  
intervals. The serial transmitter is placed into DCB03. The  
default exchange speed is set to 115200 baud.  
Note that if you require more program memory and analog  
pins, or require USB support, in your user-defined projects,  
you can import this charger to the CY8C24794 or the  
CY8C27x43 PSoC device family. The CY8C24794 device  
includes a full-featured, full-speed (12 Mbps) USB port and  
can have up to seven IO ports that connect to the global  
digital and analog interconnects, providing access to four  
digital blocks and six analog blocks. For additional  
information, see “Products: PSoC Mixed-Signal Controllers:  
The cell-balancing MOSFETS Q4, Q5 are controlled directly  
from the CPU (high level - close, low level - open).  
The three-opamp topology of the instrumental amplifier  
(INA) is used in this implementation. The INA is placed in  
ACB00, ACB01, and ASD11. The incremental ADC is  
placed in the ASC10 and DBB00 blocks.  
PSoC  
Mixed-Signal  
Array:  
CY8C24794”  
on  
November 25, 2007  
Document No. 001-17394 Rev. *B  
- 8 -  
 
AN2309  
Figure 6. PSoC Internal User Module Configuration  
The following equation represents the current measurement  
scheme:  
Battery Measurement  
To provide a correct implementation of the charge and cell-  
balancing algorithms, the charge current, battery voltage  
and temperature must be measured accurately.  
V
G
ADC  
ina I bat sense  
Equation 16  
max  
max  
V
V
ref  
ref  
These three parameters are measured as the voltage drops  
on corresponding resistors by using the instrumental  
amplifier INA. The measurement is implemented as a two-  
stage procedure to eliminate any voltage offset from the INA  
and ADC inputs. The INA inputs are shorted together in the  
first stage. This state is used to measure INA and ADC  
offset voltage. Then the real signal is measured. At this point  
the difference between the ADC codes corresponding to the  
first and second stages is directly proportional to the battery  
measurement parameter without the influence of the INA  
and ADC offset voltage.  
The value  
is the ADC code without the influence of the  
INA and ADC offset voltage and without the voltage bias on  
the current-sense resistor ( ).  
meas offset  
bias  
The value  
n
is the maximum ADC code, which is equal  
max  
to 2048 for the 12-bit incremental ADC in bipolar mode.  
The value is the battery current, is INA gain (4),  
I
G
bat  
ina  
V
is the bandgap reference voltage (1.3V), and  
is  
ref  
I
To transform the battery current (voltage drop on the  
current-sense resistor) and battery voltage into levels  
suitable for PSoC signals, precise resistive dividers are  
used. To limit the current flow from the battery to the  
powered-down battery charger, divider resistors of large  
nominal resistance are employed.  
the resistive divider coefficient (0,833333):  
1
R
Equation 17  
I
20  
1
R
15  
To provide higher current measurement accuracy, a current-  
sense resistor was put in the pack current path close to the  
negative battery voltage. In this case, the voltage drop on  
the resistive divider (R15, R16, R20, and R21) is  
independent of the battery pack voltage level. This is not  
true if a current-sense resistor is placed close to the positive  
voltage. At the beginning of the charging process, the  
voltage bias on the current-sense resistor is measured and  
during subsequent processes it is subtracted from the  
measured values. In this way, the difference between  
resistor values in the resistive divider is partly compensated.  
November 25, 2007  
Document No. 001-17394 Rev. *B  
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AN2309  
The voltage measurement also is performed by the INA on  
the corresponding resistor. The resistive dividers (R7, R6),  
(R13, R12), and (R18, R19) transform cell voltage into  
signals suitable for the PSoC device. It is very important to  
use the high precision resistors in the resistive divider to  
obtain a high value common mode signal rejection. The  
recommended R6, R7, R12, R13, R18, and R19 tolerances  
are 0.1 percent. The following equation depicts the voltage  
measurement scheme:  
For temperature measurement, a reference voltage resistive  
divider is employed based on a thermistor and a precision  
resistor (R6). Thermistor resistance is calculated according  
to the voltage drop on the precision resistor and the value of  
the reference voltage. To provide the necessary  
temperature measurement accuracy, the RefHI reference  
voltage is first set, and then AGND. After this, the second  
value of the resistor voltage drop is subtracted from the first.  
Bias voltages RefHi (2.6V) level in the first step and AGND  
(1.3V) in the next step are formed by using the continuous  
time user module TestMux. This technique allows  
compensation for both the ADC/INA offset error and the  
variation in the voltage drop on the current-sense resistor  
during the charging/discharging process. The following  
equations represent the temperature measurement scheme:  
V
G
ADC  
ina V bat  
V
Equation 18  
max  
max  
V
ref  
ref  
The value  
is the ADC code without influence of the INA  
and the ADC offset voltage (
. The  
meas offset  
R
ref  
2
1
Equation 21  
Equation 22  
V
value  
2048 for 12-bit incremental ADC in bipolar mode. The value  
is  
n
is the maximum ADC code and is equal to  
t
t
AGND  
R
max  
ref  
term  
is the battery voltage,  
G
is INA gain (1),  
V
V
R
ref  
is the  
2
1
bat  
ina  
term  
n
t
t
AGND  
R
the bandgap reference voltage (1.3V), and  
resistive divider coefficient (0.25):  
ref  
term  
V
1
t
V
The value  
is the voltage level on the temperature  
1
Equation 19  
reference resistor during application of the  
V
(1.3V)  
V
R
AGND  
7
1
2
R
V
reference voltage.  
is the voltage level on the  
6
t
temperature reference resistor during application of  
To provide higher voltage measurement accuracy in  
decision-making charging voltages, the following calibration  
technique is used. All voltage thresholds are stored as  
calibrated ADC codes. During operation, the ADC code of  
the battery voltage is compared with these calibrated values.  
For this purpose, an external precision 4.2V voltage source  
and calibration procedure after assembly are used. All  
voltage thresholds are tuned from this precision voltage:  
V
(2.6V) reference voltage. is the thermistor  
R
REFHI  
term  
resistance.  
R
is the temperature reference resistance  
ref  
1
2
1
n
n
V
R24 (10K).  
and  
are the ADC codes of  
and  
t
t
t
2
V
, respectively. The value  
n
is the ADC code of  
t
AGND  
n
the AGND input level and is equal to 2048 for 12-bit  
incremental ADC in unipolar mode.  
4.2V _ new  
n
Equation 20  
new  
old  
n
4.2V _ old  
The battery charge/discharge algorithm only needs to check  
for temperatures that fall in allowed ranges: during charging  
(typical values are 0 to 45 degrees Celsius) and discharging  
(typical values are -20 to 60 degrees Celsius). During the  
charge phase a hysteresis is added for the lower and upper  
bounds in/out temperature. This prevents multiple triggering  
when the temperature is close to the preset range. If the  
temperature is outside the discharge range, the LOAD  
connector is turned off and the PSoC device goes into sleep  
mode. Therefore, a hysteresis for the discharge range is not  
needed. The temperature profile is shown in Figure 7 on  
The value  
The value  
n
is the new voltage threshold ADC code.  
is the old voltage threshold ADC code that  
new  
n
old  
is calculated by using Equation 16 on page 9. The value  
n
is the input ADC code during the calibration  
4.2V _ new  
procedure. The value  
n
is the old voltage  
4.2V _ old  
threshold ADC code for 4.2V, which is calculated by using  
Equation 16 on page 9. In this way, the calibration is  
performed for all decision-making charging voltages  
simultaneously. All devices must be calibrated during the  
manufacturing process by using external reference.  
November 25, 2007  
Document No. 001-17394 Rev. *B  
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AN2309  
Figure 7. Temperature Profile  
No Discharge  
TDISCH_HOT_STOP  
THOT_STOP  
THOT_RESTART  
No Charge  
TBATT  
Charge in  
process  
Charge in  
Process  
TCOLD_RESTART  
TCOLD_STOP  
TDISCH_COLD_STOP  
No Discharge  
Two-Cell Battery Charger Algorithm  
Two-Cell Battery Charger Firmware  
The two-cell battery charge algorithm is implemented in the  
charger firmware as a state machine. The following states  
are used:  
The two-cell battery charger firmware is separated into  
several modules that serve distinct functions, such as  
performing measurements, regulating the battery charge  
process and timer functions, implementing the charge and  
cell-balancing algorithms, checking the charge termination  
conditions, storing calibration settings into the PSoC device  
Flash memory, and transmitting debugging data. Most of  
these modules are described in AN2107, AN2258, and  
AN2294. Therefore, in this section only the charge and cell-  
balancing algorithms are described.  
.
.
.
.
Initialization: Indicates charge process initialization.  
Activation: Depicts battery activation charging.  
Rapid: Depicts rapid battery charging.  
Charge Complete: Indicates that the battery pack is  
charged completely.  
.
.
.
.
Wait For Temperature: Used to depict the idle state  
when the battery pack temperature is outside the  
allowed temperature range.  
Error: Indicates that during the charge process an error  
has occurred. There are three error types: over-voltage,  
over-current and stage time-out exceptions.  
Discharge: Indicates that the battery pack discharge  
process and the storage device state are without  
external power supply.  
Full Discharge: Indicates that the battery pack is  
discharged completely and is not suitable for further  
use.  
The two-cell battery charger state diagram is shown in  
Figure 8 on page 12.  
November 25, 2007  
Document No. 001-17394 Rev. *B  
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AN2309  
Figure 8. Two-Cell Battery Charger State Diagram  
10  
Initialization  
7
6
9
1
13  
Wait For  
Temperature  
Activation  
Discharge  
4
2
11  
12  
8
5
Rapid  
Error  
Full  
Discharge  
3
Charge  
Complete  
Initially the charger is in the Initialization state. After some  
device preparation, the charger goes to the Activation  
state (1). When the battery voltage reaches the rapid start  
voltage, the charger leaves the Activation state and  
switches to the Rapid state (2). If the charge current drops  
below a predefined charge-terminate level, the charger goes  
to the Charge Complete (3) state. The charger remains in  
the Charge Complete state and the charging process can  
be restarted if the voltage drops below some predefined  
level (8). The charging process can be terminated with an  
error if a total charge time-out or an operation charge time-  
out occurs, or if the battery voltage or charge current is  
higher than the charge termination voltage/current levels (4),  
(5).  
Regardless of the state of the charger, it jumps to the  
Discharge state when the external power supply is switched  
off (9). If the external power supply is switched on, the  
charger goes to the Initialization state (10, 13). When the  
battery pack discharges completely (11), the charger  
switches to the Full Discharge state.  
If the system load resistance decreases and the battery  
pack voltage level re-establishes to the predefined voltage  
level, then the charger returns to the Discharge state (12).  
A
two-cell battery charger firmware flowchart that  
corresponds to the state diagram is shown in Figure 9 on  
page 13 and Figure 10 on page 14. The invocation points of  
the cell-balancing procedures are also shown. The charge  
profile example is presented in the Appendix, Figure 13 on  
page 18.  
The charger from all states jumps to the Wait For  
Temperature state when the battery temperature is outside  
the allowed temperature range. For the Activation and  
Rapid states, the allowed temperature range is the charge  
range. For other states, the allowed temperature range is  
the discharge range (6). In the case of the charge range,  
when temperatures fall into the defined range with some  
hysteresis value, the charger goes to the Initialization state  
(7).  
November 25, 2007  
Document No. 001-17394 Rev. *B  
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