IBM Network Card EM78P809N User Manual

EM78P809N

8-BIT

Microcontroller

Product

Specification

DOC. VERSION 1.0

ELAN MCCROELECTRONICS CORP.

July 2005

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Contents

1 General Description ··························································································· 1

2 Features ·············································································································· 1

2.1 CPU········································································································································ 1

2.2 Applications···························································································································· 2

3 Pin Assignment ·································································································· 3

4 Pin Description··································································································· 3

4 Function Description·························································································· 5

4.1 Functional Block Diagram ······································································································ 5

4.2 Operating Registers ··············································································································· 6

4.3 Special Purpose Registers··································································································· 23

4.4 CPU Operation Mode··········································································································· 27

4.5 AD Converter························································································································ 29

4.6 Time Base Timer and Keytone Generator············································································ 31

4.7 UART (Universal Asynchronous Receiver/Transmitter)······················································· 33

4.8 SPI (Serial Peripheral Interface) ·························································································· 36

4.9 Timer/Counter 2 ··················································································································· 40

4.10 Timer/Counter 3 ··················································································································· 42

4.11 Timer/Counter 4 ··················································································································· 44

4.12 TCC/WDT & Prescaler········································································································· 46

4.13 I/O Ports ······························································································································· 47

4.14 RESET and Wake-up··········································································································· 47

4.15 Interrupt································································································································ 54

4.16 Oscillator ······························································································································ 55

4.17 Code Option Register··········································································································· 58

4.18 Power-on Considerations····································································································· 59

4.19 Instruction Set ······················································································································ 61

Product Specification (V1.0) 07.26.2005

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Contents

5 Absolute Maximum Ratings ············································································ 63

5.1 Absolute Maximum Ratings ································································································· 63

5.2 Recommended Operating Conditions·················································································· 63

6 Electrical Characteristics················································································· 64

6.1 DC Electrical Characteristics································································································ 64

6.2 AC Electrical Characteristic·································································································· 67

6.3

Timing Diagram··················································································································· 68

APPENDIX ·············································································································· 69

Package Types:······························································································································ 69

Specification Revision History

Version

Revision Description

Date

Preliminary

0.9

1.0

2004/03/04

2005/07/26

Initial Version

iv •

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EM78P809N

8-Bit Microcontroller

1 General Description

The EM78P809N is an 8-bit microprocessor with low-power, high-speed CMOS

technology and high noise immunity. It has a built-in 8K×13-bits Electrical One Time

Programmable Read Only Memory (OTP-ROM). It provides multi-protection bits to

prevent intrusion of user’s OTP memory codes. Seven Option bits are also available to

meet user’s requirements.

With its OTP-ROM feature, the EM78P809N is able to offer a convenient way of

developing and verifying user’s programs. Moreover, user can take advantage of

ELAN Writer to easily program his development code.

2 Features

2.1 CPU

„

Operating voltage: 2.5V~5.5V

Operating temperature range: -40°C~85°C

Operating frequency range (base on 2 clocks)

Crystal mode: 1MHz ~ 8MHz at 4.5V, 1MHz ~ 4MHz at 2.5V

RC mode: 1MHz ~ 4MHz at 2.5V

„

Low power consumption:

Typically 0.8 μA, during sleep mode

„

8K × 13 bits on-chip ROM

Multi-security bits to prevent intrusion of OTP memory codes

One configuration register accommodates user’s requirements

144 × 8 bits on-chip registers (SRAM, general purpose register)

4 bi-directional I/O ports (22 pins)

High sink current output pin: 14 pins

10 programmable pull high I/O pins

10 programmable pull low I/O pins

„

8 level stacks for subroutine nesting

High performance MCU: Two clocks per instruction cycle

15 interrupts (External: 9, Internal: 6)

Programmable free running watchdog timer

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EM78P809N

8-Bit Microcontroller

„

16 bits Counter/Timer

TC2: Timer/Counter/Window

8 bits Timer/Counter

„

TCC: 8-bit real time clock/counter with overflow interrupt

TC3: Timer/Counter/Capture

TC4: Timer/Counter/ PWM (pulse width modulation)/PDO (Programmable

divider output)

„

Time Base Timer: (1Hz ~16kHz at 8MHz)

Key tone output: (1kHz ~ 8kHz at 8MHz)

Serial transmitter/receiver interface

Serial Peripheral Interface (SPI): Three-wire synchronous communication

Universal asynchronous receiver transmitter interface (UART): Two wire

asynchronous communication

„

AD converter

8 channel 10 bits resolution AD converter

Operating mode:

Normal mode: Oscillation circuit turned on, CPU and Peripheral circuit in

operation

Idle mode: Oscillation circuit turned on, CPU halt and Peripheral circuit in

operation

Sleep mode: Oscillation circuit turned off, CPU and Peripheral circuit halt

„

Package types:

28-pin DIP 600 mil: EM78P809NP

28-pin SOP 300 mil: EM78P809NM

28-pin SSOP 209 mil: EM78P809NS

99.9% single instruction cycle commands

2.2 Applications

„

General purpose

2 •

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EM78P809N

8-Bit Microcontroller

3 Pin Assignment

(ACLK) OSCO

VDD

OSCI

TEST

(AD0) P90

(AD1) P91

(AD2) P92

(AD3) P93

(AD4) P94

(AD5) P95

/RESET (VPP)

P67 (DINCK)

P66 (DATAIN)

P65 (PGMB)

P64 (/SS)(OEB)

P63 (/TONE)

P62 (TC2)

P61 (INT1)

P60 (/INT0)

P73 (/SLEEP, /INT5)

(AD6) P96

(AD7/VREF) P97

(TC3, INT3) P80

(TC4, /PWM, /PDO) P81

VSS

P72 (TX,SO)

P71(RX,SI)

P70 (/SCK)

EM78P809N

Fig. 1. Pin Assignment

4 Pin Description

Table 1

Symbol Pin No.

Type

Function

VDD

* Power supply

* Crystal type: Crystal input terminal

* RC type: RC oscillator input pin

OSCI

* Crystal type: Output terminal for crystal oscillator

* RC type: Instruction clock output

* External clock signal input

OSCO

I/O

* Input pin with Schmitt trigger. If this pin remains at logic low, the

controller will also remain in reset condition.

/RESET

* P60~P67 are bi-directional I/O pins

* P60 can be used as external interrupt 0 (/INT0)

* P61 can be used as external interrupt 1 (INT1)

* P62 can be used as 16-bit Timer/Counter 2 (TC2)

* P63 can be used as divider output (/TONE)

* P64 slave mode enable (/SS)

P60~P67

19~26

I/O

* P60 ~ P63 can be used as pull high or pull low pins

* P70~P77 are bi-directional I/O pins

* P70 can be used as SPI serial clock input/output (/SCK)

* P71 can be used as SPI serial data input (SI) or UART data receive

input (RX)

P70~P73

15~18

I/O

* P72 can be used as SPI serial data output (SO) or UART data

transmit output (TX)

* P73 can be used as SLEEP mode release input (/SLEEP) or external

interrupt input 5 (/INT5)

* P70 ~ P73 can be used as pull high or pull low pins

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EM78P809N

8-Bit Microcontroller

Symbol Pin No.

Type

Function

* P80~P83 are bi-directional I/O pins

* P80 can be used as 8-bit Timer/Counter 3 (TC3) or external Interrupt

Input 3 (INT3)

P80~P81

12~13

I/O

* P81 can be used as 8-bit Timer/Counter 4 (TC4) or programmable

divider output (PDO)

* P80 ~ P81 can be used as pull high or pull low pins

* P90~P97 are bi-directional I/O pins

P90~P97

4~11

I/O

* P90~P97 can be used as 8 channel 10-bit resolution A/D converter

* P97 can be used as AD reference power supply input (VREF)

VSS

* Ground

* No connection

OTP Programming Pins

VPP

ACLK

Programming voltage input

CLK for OTP memory address increment

ROM code series input and series output pin

ROM code input clock

DATAIN

DINCK

PGMB

OEB

I/O

Program write enable pin. Active low.

Output enable pin. Active low.

4 •

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EM78P809N

8-Bit Microcontroller

4 Function Description

4.1 Functional Block Diagram

OSCI

OSCO

WDT timer

Stack

ROM

WDT Prescaler

TCC Prescaler

Oscillator

Timing Control

R1 (TCC)

ALU

Interrupt

Control

Instruction

General RAM

ACC

Control Sleep and

Wake-up I/O Port

Instruction

Decoder

DATA and CONTROL BUS

PORT6

PORT7

PORT8

PORT9

TC 2 (16-bit Timer/Counter)

TC 3 (8-bit Timer/Counter, Capture Mode)

TC 4 (8-bit Timer/Counter, PWM, PDO)

SPI (Serial Peripheral Interface)

UART (Universal Asynchronous

Receiver/Transmitter)

IOC6

IOC7

IOC8

IOC9

8 channel 10 bit ADC

P60 ~ P67

P70 ~ P73

P80 ~ P81

P90 ~ P97

Keytone

TBT (Time Base Timer)

Fig. 2. Functional Block Diagram

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EM78P809N

8-Bit Microcontroller

4.2 Operating Registers

BANK 0

BANK 1

BANK 2

BANK 3

CONTROL

Address

R0/ IAR

R1/ TCC

R2/ PC

R3/ SR

R4/ RSR

SCR

R3 (7,6)= (0,1)

R3 (7,6)= (1,0)

R3 (7,6)= (1,1)

TC3CR

TC3DA

URC1

URC2

SPIC1

SPIC2

Reserved

IOC6

PORT6

PORT7

PORT8

PORT9

Reserved

TC4CR

TC4D

TC3DB

URS

SPID

IOC7

TC2CR/ ADDL

TC2DH

URRD

Reserved

PHC1

IOC8

URTD

IOC9

TC2DL

Reserved

INTCR

ADOSCR

Reserved

IMR1

ADCR

PLC1

ADIC

PHC2

ISFR0

ADDH

PLC2

ISFR1

TBKTC

Reserved

ISFR2

IMR2

16 Byte

Common Register

BANK 0

R4 (7,6) = (0,0)

BANK 1

R4 (7,6) = (0,1)

BANK2

R4 (7,6) = (1,0)

BANK 3

R4 (7,6) = (1,1)

32 Byte

Common Register

32 Byte

Common Register

32 Bytes

Common Register

32 Bytes

Common Register

Fig. 3. Operating Registers

6 •

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EM78P809N

8-Bit Microcontroller

R0/IAR − Indirect Addressing Register ( Address: 00h )

R0 is not a physically implemented register. Its major function is to act as an indirect

addressing pointer. Any instruction using R0 as a pointer actually accesses data

pointed by the RAM Select Register (R4).

R1/TCC − Time Clock /Counter ( Address: 01h )

This register is writable and readable just like the other registers. The contents of the

prescaler counter are cleared only when a value is written into the TCC register.

R2/PC − Program Counter & Stack ( Address: 02h )

—

Depending on the device type, R2 and hardware stack are 10-bit wide. The

structure is depicted in Fig.4.

—

Generates 8192 ×13 bits on-chip OTP ROM addresses to the relative

programming instruction codes. One program page is 1024 words long.

—

R2 is set as all "0"s when under RESET condition

"JMP" instruction allows direct loading of the lower 10 program counter bits.

Thus, "JMP" allows the PC to go to any location within a page.

—

"CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is

pushed into the stack. Thus, the subroutine entry address can be located

anywhere within a page.

—

"RET" ("RETL k", "RETI") instruction loads the program counter with the

contents of the top-level stack.

All instructions are single instruction cycle (fclk/2 or fclk/4) except for the

instruction that would change the contents of R2. Such instruction will need

one more instruction cycle.

—

For an interrupt trigger, the program ROM will jump to individual interrupt

vector at Page 0. The CPU will store ACC, R3 status and R5 PAGE

automatically, it will restore after instruction RETI.

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EM78P809N

8-Bit Microcontroller

PC A12 A11 A10 A9 A8 A7

0000h

0003h

0006h

0009h

000Fh

0012h

0015h

0018h

001Bh

0021h

0024h

0027h

0030h

0033h

0036h

Reset Vector

CALL

RET

000 : PAGE0 0000~03FF

WDT Timer Overflow

RETL

RETI

Store ACC, R3, R5

001 : PAGE1 0400~07FF

010 : PAGE2 0800~0BFF

011 : PAGE3 0C00~0FFF

100 : PAGE4 1000~13FF

101 : PAGE5 1400~17FF

110 : PAGE6 1800~1BFF

111 : PAGE7 1C00~1FFF

External INT0 Pin Interrupt Occurs

TCC Overflow

STACK LEVEL 1

STACK LEVEL 2

STACK LEVEL 3

STACK LEVEL 4

STACK LEVEL 5

STACK LEVEL 6

STACK LEVEL 7

STACK LEVEL 8

External INT1 pin Interrupt Occurs

Time Base Timer Interrupt

UART Transmit Data Buffer Empty

UART Receive Data Buffer Full

UART Receive Error

TC3 Interrupt

SPI Interrupt

TC4 Interrupt

External INT3 Pin Interrupt Occurs

AD Conversion Complete

External INT5 Pin Interrupt Occurs

On-chip Program Memory

1FFFh

Fig. 4. Program Counter Organization

R3/SR − Status Register ( Address: 03h )

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RBS1

RBS0

Bit 7 ~ Bit 6 (RBS1 ~ RBS0) : R-Register page select

RBS1

RBS0

Bank 0

Bank 1

Bank 2

Bank 3

Bit 5 : Not used

Bit 4 (T) : Time-out bit. Set to “1” with the "SLEP" and "WDTC" commands, or

during power up, and reset to “0” with the WDT time-out.

8 •

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EM78P809N

8-Bit Microcontroller

Bit 3 (P) : Power down bit. Set to “1” during power on or by a "WDTC" command

and reset to “0” by a "SLEP" command.

Bit 2 (Z) : Zero flag. Set to "1" if the result of an arithmetic or logic operation is

zero.

Bit 1 (DC) : Auxiliary carry flag

Bit 0 (C) : Carry flag

R4/RSR − RAM Select Register ( Address: 04h )

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

GRBS1

RBS0

RSR5

RSR4

RSR3

RSR2

RSR1

RSR0

Bit 7: 6 ( GRBS1 : GRBS0 ) : determine which general purpose banks are

activated among the 4 banks. Use BANK instruction (e.g. BABK 1) to

change bank.

GRBS1

GRBS0

General Purpose Register Bank (Address 20H ~ 3FH)

Bank 0

Bank 1

Bank 2

Bank 3

Bit 5: 0 ( RSR5 : RSR0 ) : are used to select the registers (address: 00h~3Fh) in

the indirect addressing mode. If no indirect addressing is used, the RSR

can be used as an 8-bit general-purpose read/write register. See the

data memory configuration in Fig. 3.

SCR − System Control Register, Program ROM Page Select ( Address: 05h )

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PS2

PS1

PS0

SIS

REM

Bit 6 (PS2) ~ 4 (PS0) : ROM Page select bits. User can use PAGE instruction (e.g.

PAGE 1) or set PS2~PS0 bits to change the ROM page. When

executing a "JMP", "CALL", or other instructions which cause the

program counter to change (e.g. MOV R2, A), PS2~PS0 are loaded into

the 13th to 11th bits of the program counter and select one of the

available program memory pages. Note that RET (RETL, RETI)

instruction does not change the PS2~PS0 bits. That is, return will

always be to the page from where the subroutine was called, regardless

of the PS2~PS0 bits current setting.

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EM78P809N

8-Bit Microcontroller

PS2

PS1

PS0

Program Memory Page [Address]

Page 0 [0000~03FF]

Page 1 [0400~07FF]

Page 2 [0800~0BFF]

Page 3 [0C00~0FFF]

Page 4 [1000~13FF]

Page 5 [1400~17FF]

Page 6 [1800~1BFF]

Page 7 [1C00~1FFF]

Bit 1 ( SIS ) : SLEEP and IDLE mode select.

SIS = “0” : IDLE mode

SIS = “1” : SLEEP mode

Bit 0 ( REM ) : Release method for sleep mode.

REM = “0” : /SLEEP pin input rising edge release

REM = “1” : /SLEEP pin input “H” level release

PORT6 − Port 6 I/O Data Register ( Address: 06h )

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

P67

P66

P65

P64

P63

P62

P61

P60

Bit 7 ~ Bit 0 ( P67 ~ P60 ) : 8-bits Port 6 I/O data register

User can use IOC6 register to define each bit whether input or output.

PORT7 — Port 7 I/O Data Register ( Address: 07h )

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

P73

P72

P71

P70

Bit 3 ~ Bit 0 ( P73 ~ P70 ) : Port 73 ~ Port 70 I/O data register

User can use IOC7 register to define each bit whether input or output.

PORT8 − Port 8 I/O Data Register ( Address: 08h )

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

P81

P80

Bit 1 ~ Bit 0 ( P81 ~ P80 ) : Port 81 ~ Port 80 I/O data register

User can use IOC8 register to define input or output each bit.

10 •

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EM78P809N

8-Bit Microcontroller

PORT9 − Port 9 I/O Data Register ( Address: 09h )

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

P97

P96

P95

P94

P93

P92

P91

P90

Bit 7 ~ Bit 0 ( P97 ~ P90 ) : 8-bit Port 97 ~ Port 90 I/O data register

User can use IOC9 register to define each bit whether input or output.

TC4CR — Timer/Counter 4 Control Register ( Address: 0Bh )

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

TC4FF1

TC4FF0

TC4S

TC4CK2 TC4CK1 TC4CK0

TC4M1

TC4M0

Bit 7 ~ Bit 6 ( TC4FF1 ~ TC4FF0 ) : Timer/Counter4 flip-flop control.

TC4FF1

TC4FF0

Operating Mode

Clear

Toggle

Set

Reserved

Bit 5 ( TC4S ) : Timer/Counter 4 start control.

TC4S = “0” : Stop and clear counter

TC4S = “1” : Start

Bit 4 ~ Bit 2 ( TC4CK2 ~ TC4CK 0 ) : Timer/Counter 4 Clock Source Select

Clock Source

( Normal, Idle )

Resolution

( Fosc=8M )

Max. Time

TC4CK2 TC4CK1 TC4CK0

( Fosc=8M )

Fc/2^11

250uS

16uS

4uS

64mS

4mS

Fc/2^7

Fc/2^5

1mS

Fc/2^3

1uS

255uS

127.5uS

63.8uS

31.9uS

Fc/2^2

500nS

250nS

125nS

Fc/2^1

External clock (TC4 pin)

Bit 1 ~ Bit 0 ( TC4M1 ~ TC4M0 ) : Timer/Counter 4 Operating Mode Select

TC4M1

TC4M0

Operating Mode

Timer/Counter

Reserved

Programmable Divider output

Pulse Width Modulation output

Product Specification (V1.0) 07.26.2005

• 11

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EM78P809N

8-Bit Microcontroller

TC4D − Timer 4 Data Buffer ( Address: 0Ch )

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

TC4D7

TC4D6

TC4D5

TC4D4

TC4D3

TC4D2

TC4D1

TC4D0

Bit 7 ~ Bit 0 ( TC4D7 ~ TC4D0 ) : Data buffer of 8-bit Timer/Counter 4.

ISFR0 − Interrupt Status Flag Register 0 and INT3 Edge Detect Flag.

( Address : 0Dh )

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INT3F

INT3R

WDTIF

EXIF0

Bit 5 ( INT3F ) : External interrupt 3 falling edge detect flag.

INT3F = “0” : Falling edge is not detected

INT3F = “1” : Falling edge is detected

Bit 4 ( INT3R ) : External interrupt 3 rising edge detect flag.

INT3R = “0” : Rising edge is not detected

INT3R = “1” : Rising edge is detected

Bit 1 ( WDTIF ) : WDT time-out flag, flag cleared by software.

Bit 0 ( EXIF0 ) : External interrupt flag (INT0). Flag cleared by software. If the

INT0EN is reset to “0”, the flag is cleared.

ISFR1 − Interrupt Status Flag Register 1 ( Address: 0Eh )

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

EXIF5

TCIF2

ADIF

EXIF3

TCIF4

SPIF

TCIF3

Bit 7 ( EXIF5 ) : External Interrupt Flag (/INT5), flag cleared by software.

Bit 6 ( TCIF2 ) : 16-bit Timer/Counter 2 Interrupt Flag, flag cleared by software.

Bit 5 ( ADIF ) : AD conversion complete flag, flag cleared by software.

Bit 3 ( EXIF3 ) : External Interrupt Flag (/INT3), flag cleared by software.

Bit 2 ( TCIF4 ) : 8-bit Timer/Counter 4 Interrupt Flag, flag cleared by software.

Bit 1 ( SPIF ) : SPI Mode Interrupt Flag, flag cleared by software.

Bit 0 ( TCIF3 ) : 8-bit Timer/Counter 3 interrupt flag, flag cleared by software.

"1" means interrupt request, "0" means non-interrupt

—

ISFR1 can be cleared by instruction, but cannot be set by instruction

IMR1 is the interrupt mask register

Note that reading ISFR1 will obtain the result of the ISFR1 "logic AND" and

IMR1.

12 •

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EM78P809N

8-Bit Microcontroller

ISFR2 − Interrupt Status Flag Register 2 ( Address: 0Fh )

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

UERRIF

RBFF

TBEF

TBIF

EXIF1

TCIF0

Bit 6 (UERRIF) : UART Receiving Error Interrupt, cleared by software or UART

disabled.

Bit 5 (RBFF) : UART Receive Mode Data Buffer Full Interrupt Flag. Flag cleared

by software.

Bit 4 (TBEF) : UART Transmit Mode Data Buffer Empty Interrupt Flag. Flag

cleared by software.

Bit 3 (TBIF) : Time Base Timer Interrupt Flag. Flag cleared by software.

Bit 2 (EXIF1) : External Interrupt Flag (INT1). Flag cleared by software.

Bit 0 (TCIF0) : TCC Overflow Interrupt Flag. Set as TCC overflows; flag cleared

by software.

"1" means interrupt request, "0" means non-interrupt

—

ISFR2 can be cleared by instruction, but cannot be set by instruction

IMR2 is the interrupt mask register

Note that reading ISFR2 will obtain the result of the ISFR2 "logic AND" and

IMR2

TC3CR − Timer/Counter 3 Control Register ( Address: 05h )

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

TC3CAP

TC3S

TC3CK1 TC3CK0

TC3M

Bit 7 ( TC3CAP ) : Software capture control

TC3CAP = “0” : -

TC3CAP = “1” : Software capture

Bit 6 ( TC3S ) : Timer/Counter 3 start control

TC3S = “0” : Stop and counter clear

TC3S = “1” : Start

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EM78P809N

8-Bit Microcontroller

Bit 5 ~ Bit 4 ( TC3CK1 ~ TC3CK0 ) : Timer/Counter3 Clock Source Select

Clock source

Resolution

( Fc=8M )

Max. time

( Fc=8M )

TC3CK1

TC3CK0

( Normal, Idle )

Fc/2¹²

Fc/2¹⁰

Fc/2⁷

512μS

128μS

16μS

131.1mS

32.6mS

4.1mS

External clock (TC3 pin)

Bit 3 ( TC3M ) : Timer/Counter 3 mode select

TC3M = “0” : Timer/Counter3 mode

TC3M = “1” : Capture mode

TC3DA − Timer 3 Data Buffer A ( Address: 06h )

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

TC3DA7 TC3DA6 TC3DA5 TC3DA4 TC3DA3 TC3DA2 TC3DA1 TC3DA0

Bit 7 ~ Bit 0 ( TC3DA7 ~ TC3DA0 ) : Data buffer of 8-bit Timer/Counter 3.

Reset does not affect this register.

TC3DB − Timer 3 Data Buffer B ( Address: 07h )

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

TC3DB7 TC3DB6 TC3DB5 TC3DB4 TC3DB3 TC3DB2 TC3DB1 TC3DB0

Bit 7 ~ Bit 0 ( TC3DB7 ~ TC3DB0 ) : Data buffer of 8-bit Timer/Counter 3

Reset does not affect this register.

TC2CR/ ADDL — Timer/Counter 2 Control Register, AD Low 2 bits Data

Buffer ( Address: 08h )

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ADD1

ADD0

TC2M

TC2S

TC2CK2

TC2CK1

TC2CK0

Bit 7 ~ Bit 6 ( ADD1 ~ ADD0 ) : AD low 2-bit data buffer

Bit 4 ( TC2M ) : Timer/Counter 2 mode select

TC2M = “0” : Timer/counter mode

TC2M = “1” : Window mode

Bit 3 ( TC2S ) : Timer/Counter 2 start control

TC2S = “0” : Stop and counter clear

TC2S = “1” : Start

14 •

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EM78P809N

8-Bit Microcontroller

Bit 2 ~ Bit 0 ( TC2CK2 ~ TC2CK0 ) : Timer/Counter 2 Clock Source Select

Clock Source

( Normal, Idle )

Resolution

( Fc=8M )

Max. Time

( Fc=8M )

TC2CK2 TC2CK1 TC2CK0

Fc/2²³

Fc/2¹³

Fc/2⁸

Fc/2³

1.05s

1.02ms

32μs

1μs

19.1h

1.1min

2.1s

65.5ms

7.9ms

125ns

External clock (TC2 pin)

TC2DH − Timer 2 Data Buffer High Byte ( Address: 09h )

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

TC2D15

TC2D14

TC2D13

TC2D12

TC2D11

TC2D10

TC2D9

TC2D8

Bit 7 ~ Bit 0 ( TC2D15 ~ TC2D8 ) : 16-bit Timer/Counter 2 data buffer high byte.

TC2DL − Timer 2 Data Buffer Low Byte ( Address: 0Ah )

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

TC2D7

TC2D6

TC2D5

TC2D4

TC2D3

TC2D2

TC2D1

TC2D0

Bit 7 ~ Bit 0 ( TC2D7 ~ TC2D0 ) : 16-bit Timer/Counter 2 data buffer low byte.

ADCR − AD Control Register ( Address: 0Bh )

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ADREF

ADRUN

ADCK1

ADCK0

ADP

ADIS2

ADIS1

ADIS0

Bit 7 ( ADREF ) : AD reference voltage input select.

ADREF = “0” : Internal VDD, P97 is used as IO.

ADREF = “1” : External reference pin, P97 is used as reference input pin.

Bit 6 ( ADRUN ) : AD Conversion start

ADRUN = “0” : Reset on completion of the conversion by hardware, this bit

cannot be reset by software.

ADRUN = “1” : Conversion starts

Product Specification (V1.0) 07.26.2005

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EM78P809N

8-Bit Microcontroller

Bit 5~ Bit 4 ( ADCK1 ~ ADCK0 ) : AD Conversion Time Select

Clock Source

( Normal, Idle )

Max. Operating

Frequency (Fc)

ADCK1

ADCK0

Fc/4

Fc/16

1MHz

4MHz

8MHz

Fc/32

Reserved

Bit 3 ( ADP ) : AD power control

ADP = “0” : Power on

ADP = “1” : Power down

Bit 2 ~ Bit 0 ( ADIS2 ~ ADIS0 ) : Analog Input Pin Select

ADIS2

ADIS1

ADIS0

Analog Input Pin

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

ADIC − AD Input Pin Control ( Address: 0Ch )

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ADE7 ADE6

ADE5

ADE4

ADE3

ADE2

ADE1

ADE0

Bit 7 ~ Bit 0 ( ADE7 ~ ADE0 ) : AD input pin enable control.

ADEx = “0” : PORT9.x act as I/O pin.

ADEx = “1” : PORT9.x act as analog input pin.

ADDH − AD High 8-bit Data Buffer ( Address: 0Dh )

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ADD9

ADD8

ADD7

ADD6

ADD5

ADD4

ADD3

ADD2

Bit 7 ~ Bit 0 ( ADD9 ~ ADD2 ) : AD high 8-bit data buffer.

16 •

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EM78P809N

8-Bit Microcontroller

TBKTC − TBT/Keytone Control ( Address: 0Eh )

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

TEN

TCK1

TCK0

TBTEN

TBTCK2 TBTCK1 TBTCK0

Bit 7 ( TEN ) : Keytone enable control

TEN = “0” : Disable

TEN = “1” : Enable

Bit 6 ~ Bit 5 ( TCK1 ~ TCK0 ) : Keytone Output Clock Source Select

Clock Source

( Normal, Idle )

Keytone Output Frequency

TCK1

TCK0

( Fc = 8MHz )

0.976kHz

1.953kHz

3.906kHz

7.812kHz

Fc/2¹³

Fc/2¹²

Fc/2¹¹

Fc/2¹⁰

Bit 3 ( TBTEN ) : Time Base Timer Enable Control

TBTEN = “0” : Disable

TBTEN = “1” : Enable

Bit 2 ~ Bit 0 ( TBTCK2 ~ TBTCK0 ) : Time Base Timer Clock Source Select

Clock Source

( Normal, Idle )

Interrupt Frequency

( Fc = 8MHz )

TBTCK2

TBTCK1

TBTCK0

Fc/2²³

Fc/2²¹

Fc/2¹⁶

Fc/2¹⁴

Fc/2¹³

Fc/2¹²

Fc/2¹¹

Fc/2⁹

0.95Hz

3.81Hz

122.07Hz

488.28Hz

976.56Hz

1953.12Hz

3906.25Hz

15625Hz

URC1 − UART Control Register 1 ( Address: 05h )

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

URTD8 UMODE1 UMODE0 BRATE2 BRATE1 BRATE0

UTBE

TXE

Bit 7 ( URTD8 ) : Transmission data bit 8

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EM78P809N

8-Bit Microcontroller

Bit 6 ~ Bit 5 ( UMODE1 ~ UMODE0 ) : UART Transmission Mode Select Bit

UMODE1

UMODE0

UART Mode

Mode1: 7-bits

Mode2: 8-bits

Mode3: 9-bits

Reserved

Bit 4 ~ Bit 2 ( BRATE2 ~ BRATE1 ) : Transmit Baud Rate Select

BRATE2

BRATE1

BRATE0

Baud Rate

Fc/13

e.g. Fc=8MHz

38400

19200

9600

Fc/26

Fc/52

Fc/104

Fc/208

Fc/416

TC4

4800

2400

1200

Fc/96

Bit 1 ( UTBE ) : UART transfer buffer empty flag. Set to 1 when transfer buffer is

empty. Reset to 0 automatically when writing into the URTD register. UTBE bit will

be cleared by hardware when enabling the transmission. UTBE bit is read-only.

Therefore, writing to the URTD register is necessary when we want to start

transmission shifting.

Bit 0 ( TXE ) : Enable transmission

TXE = “0” : Disable

TXE = “1” : Enable

URC2 − UART Control Register 2 ( Address: 06h )

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SBIM1

SBIM0

UINVEN

Bit 5 ~ Bit 4 ( SBIM1 ~ SBIM0 ) : Serial bus interface operation mode select.

TC2CK1

TC2CK0

Operation Mode

I/O mode

SPI mode

UART mode

Reserved

Bit 3 ( UINVEN ) : Enable UART TXD and RXD port inverse output.

UINVEN = “0” : Disable TXD and RXD port inverse output.

UINVEN = “1” : Enable TXD and RXD port inverse output.

18 •

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EM78P809N

8-Bit Microcontroller

URS − UART Status Register ( Address: 07h )

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

URRD8

EVEN

PRE

PRERR

OVERR

FMERR

URBF

RXE

Bit 7 ( URRD8 ) : Receiving data bit 8

Bit 6 ( EVEN ) : Select parity check

EVEN = “0” : Odd parity

EVEN = “1” : Even parity

Bit 5 ( PRE ) : Enable parity addition

PRE = “0” : Disable

PRE = “1” : Enable

Bit 4 ( PRERR ) : Parity error flag.

Set to 1 when parity error occurred, and cleared to 0 by software.

Bit 3 ( OVERR ) : Overrun error flag.

Set to 1 when overrun error occurred, and cleared to 0 by software.

Bit 2 ( FMERR ) : Framing error flag.

Set to 1 when framing error occurred, and cleared to 0 by software.

Bit 1 ( URBF ) : UART read buffer full flag.

Set to 1 when one character is received. Reset to 0 automatically when read

from the URS register. URBF will be cleared by hardware when receiving is

enabled. URBF bit is read-only. Therefore, reading the URS register is

necessary to avoid an overrun error.

Bit 0 ( RXE ) : Enable receiving

RXE = “0” : Disable

RXE = “1” : Enable

URRD − UART Receive Data Buffer ( Address: 08h )

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

URRD7 URRD6 URRD5 URRD4 URRD3 URRD2 URRD1 URRD0

Bit 7 ~ Bit 0 ( URRD7 ~ URRD0 ) : UART receive data buffer. Read only.

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EM78P809N

8-Bit Microcontroller

URTD − UART Transmit Data Buffer ( Address: 09h )

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

URTD 7 URTD 6

URTD 5

URTD 4

URTD 3

URTD 2

URTD 1

URTD0

Bit 7 ~ Bit 0 ( URTD 7 ~ URTD 0) : UART transmit data buffer. Write only.

SPIC1 − SPI Control Register 1 ( Address: 05h )

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SMP

DCOL

BRS2

BRS1

BRS0

EDS

DORD

WBE

Bit 7 ( SMP ) : SPI data input sample phase.

SMP = “0” : Input data sampled at middle of data output time

SMP = “1” : Input data sampled at the end of data output time

In using external clock, data input sample is fixed at the middle of data output time.

Bit 6 ( DCOL ) : SPI Data collision.

DCOL = “0” : Data collision didn’t occur

DCOL = “1” : Data collision occurred. It should be cleared by software.

Bit 5 ~ Bit 3 ( BRS0 ~ BRS2 ) : SPI Clock Source Select

Clock Source

( Normal, Idle )

Max. Transfer Rate

( Fc = 8MHz )

BRS2

BRS1

BRS0

Fc/2¹³

Fc/2¹¹

Fc/2¹⁰

Fc/2⁸

Fc/2⁶

0.95Kbit/s

3.8Kbit/s

7.6Kbit/s

30.5Kbit/s

122Kbit/s

244Kbit/s

Fc/2⁵

External clock (/SCK pin)

Bit 2 ( EDS ) : Data shift out edge select.

EDS = “0” : Rising edge

EDS = “1” : Falling edge

Bit 1 ( DORD ) : Data transmission order.

DORD = “0” : Shift left (MSB first)

DORD = “1” : Shift right (LSB first)

20 •

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EM78P809N

8-Bit Microcontroller

Bit 0 ( WBE ) : Write buffer empty flag. Read only.

WBE = “0” : Write buffer empty

WBE = “1” : Not empty, set to “1” automatically when writing data to the data

buffer.

SPIC2 − SPI Control Register 2 (Address : 06h )

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SPIS

SPIM1

SPIM0

RBF

Bit 7 ( SPIS ) : SPI start shift, set the bit to “1” and shift register starts to shift. It is

cleared by hardware when shifting is finished. In transferring the

next data, it must be set to “1” again.

SPIS = “0” : Shift finish

SPIS = “1” : Shift starts

Bit 2 ~ Bit 1 ( SPIM1 ~ SPIM0) : SPI Transfer Mode Select

TC2CK1

TC2CK0

Transfer Mode

8-bit Transmit/Receive mode

8-bit Transmit mode

8-bit Receive mode

Reserved

Bit 0 ( RBF ) : Set to 1 by Buffer Full Detector, and cleared to 0 automatically when

reading data from the SPID register. RBF bit will be cleared by

hardware when enabling SPI. And RBF bit is read-only. Therefore,

reading the SPRL register is necessary to avoid data collision to

occur (DCOL).

SPID (SPI Data Buffer ( Address: 07h )

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SPID7

SPID6

SPID5

SPID4

SPID3

SPID2

SPID1

SPID0

Bit 7 ~ Bit 0 ( SPID7 ~ SPID0 ) : SPI data buffer.

PHC1 − Pull High Control Register 1 ( Address: 0Ah )

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

/PHE81

/PHE80

/PHE63

/PHE62

/PHE61

/PHE60

Bit 5 ~ 4 ( /PHE81 ~ /PHE80 ) : bits 1, 0 of Port 8 Pull high enable bit

/PHE8x = “0” : Enable P8x pull high

/PHE8x = “1” : Disable P8x pull high

Product Specification (V1.0) 07.26.2005

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EM78P809N

8-Bit Microcontroller

Bit 3 ~ 0 ( /PHE63 ~ /PHE60 ) : bit 3 ~ 0 of Port 6 Pull high enable bit

/PHE6x = “0” : Enable P6x pull high

/PHE6x = “1” : Disable P6x pull high

PLC1 (Pull Low Control Register 1 ( Address : 0Bh )

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

/PLE81

/PLE80

/PLE63

/PLE62

/PLE61

/PLE60

Bit 5 ~ 4 ( /PLE81 ~ /PLE80 ) : bits 1, 0 of Port 8 Pull low enable bit

/PLE8x = “0” : Enable P8x pull low

/PLE8x = “1” : Disable P8x pull low

Bit 3 ~ 0 ( /PLE63 ~ /PLE60 ) : bits 3 ~ 0 of Port 6 Pull low enable bit

/PLE6x = “0” : Enable P6x pull low

/PLE6x = “1” : Disable P6x pull low

PHC2 − Pull High Control Register 2 ( Address: 0Ch )

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

/PHE73

/PHE72

/PHE71

/PHE70

Bit 3 ~ 0 ( /PHE73 ~ /PHE70 ) : bits 3 ~ 0 of Port 7 Pull high enable bit

/PHE7x = “0” : Enable P7x pull high

/PHE7x = “1” : Disable P7x pull high

PLC2 − Pull Low Control 2 ( Address: 0Dh )

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

/PLE73

/PLE72

/PLE71

/PLE70

Bit 3 ~ 0 ( /PLE73 ~ /PLE70 ) : bits 3 ~ 0 of Port 7 Pull low enable bit

/PLE7x = “0” : Enable P7x pull low

/PLE7x = “1” : Disable P7x pull low

R10~R1F and R20~R3F (including Banks 0~3) are General Purpose Register

22 •

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EM78P809N

8-Bit Microcontroller

4.3 Special Purpose Registers

(Accumulator)

—

Internal data transfer, or instruction operand holding.

It cannot be addressed.

CONT (Control Register)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

WDTO

/INT

WDTP1

WDTP0

WDTE

PSR2

PSR1

PSR0

CONT register is both readable and writable.

Bit 7 ( WDTO ) : WDT output select

WDTO = “0” : Interrupt request

WDTO = “1” : Internal reset

Bit 6 ( /INT ) : Interrupt enable flag

/INT = “0” : masked by DISI or hardware interrupt

/INT = “1” : enabled by ENI/RETI instructions

Bit 5 ~ Bit 4 ( WDTP1 ~ WDTP0 ) : WDT prescaler bits.

WDTP1

WDTP0

Operating Mode

1:4

1:16

1:64

1:256

Bit 3 ( WDTE ) : WDT enable control.

WDTE = “0” : Disable

WDTE = “1” : Enable

Bit 2 ( PSR2 ) ~ Bit 0 ( PSR0 ) : TCC prescaler bits.

PSR2

PSR1

PSR0

Operating Mode

1:2

1:4

1:8

1:16

1:32

1:64

1:128

1:256

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EM78P809N

8-Bit Microcontroller

IOC6 ~ IOC9 − I/O Port Control Register

—

"1" puts the relative I/O pin into high impedance, while "0" defines the relative

I/O pin as output.

—

IOC6 and IOC9 registers are both readable and writable.

INTCR − INT Control Register ( Address : 0Bh )

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INT1NR

INT0EN

INT3ES1 INT3ES0

INT1ES

TC2ES

Bit 7 ( INT1NR ) : INT1 noise reject time select

INT1NR = “0” : Pulses less than 63/fc are eliminated as noise

INT1NR = “1” : Pulses less than 15/fc are eliminated as noise

Bit 6 ( INT0EN ) : INT0 enable control

INT0EN = “0” : General I/O

INT0EN = “1” : /INT0 pin

Bit 5 : Reserved

Bit 4 ~ Bit 3 ( INT3ES1 ~ INT3ES0) : INT3 edge select

INT3ES1

INT3ES0

Edge Select

Rising

Falling

Both edge

Reserved

Bit 2 : Reserved

Bit 1 ( INT1ES ) : INT1 edge select

INT1ES = “0” : Rising edge

INT1ES = “1” : Falling edge

Bit 0 (TC2ES) : Timer/Counter 2 edge select.

TC2ES = “0” : Rising edge

TC2ES = “1” : Falling edge

24 •

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EM78P809N

8-Bit Microcontroller

External Interrupt

Secondary

Digital Noise

Reject

INT Pin

Enable Condition

Edge

Function Pin

P60

/INT0

INT1

ENI + INT0EN (IOCB)

ENI + EXIE1 (IMR2)

Falling

P61

Rising or Falling

15/Fc, 63/Fc

Rising or Falling or

Rising/Falling

INT3

P80, TC3

ENI + EXIE3 (IMR2)

ENI + EXIE5 (IMR2)

7/Fc

/INT5

P73, /SLEEP

ADOSCR − AD Offset Control Register ( Address : 0Ch )

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

CALI

SIGN

VOF[2]

VOF[1]

VOF[0]

Bit 7 (CALI) : Calibration enable bit for A/D offset

CALI = “0” : Calibration disable

CALI = “1” : Calibration enable

Bit 6 ( SIGN ) : Polarity bit of offset voltage

SIGN = “0” : Negative voltage

SIGN = “1” : Positive voltage

Bit 5 ~ Bit 3 ( VOF[2] ~ VOF[0] ) : Offset voltage bits

IMR1 − Interrupt Mask Register 1 ( Address : 0Eh )

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

EXIE5

TCIE2

ADIE

EXIE3

TCIE4

SPIE

TCIE3

Bit 7 ( EXIE5 ) : External/INT5 pin Interrupt enable bit.

EXIE5 = “0” : disable EXIF5 interrupt

EXIE5 = “1” : enable EXIF5 interrupt

Bit 6 ( TCIE2 ) : Timer/Counter 2 Interrupt enable bit.

TCIE2 = “0” : disable TCIF2 interrupt

TCIE2 = “1” : enable TCIF2 interrupt

Bit 5 ( ADIE ) : ADC complete interrupt enable bit.

ADIE = “0” : disable ADIF interrupt

ADIE = “1” : enable ADIF interrupt

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Bit 3 ( EXIE3 ) : External INT3 pin Interrupt enable bit.

EXIE3 = “0” : disable EXIF3 interrupt

EXIE3 = “1” : enable EXIF3 interrupt

Bit 2 ( TCIE4 ) : Timer/Counter 4 Interrupt enable bit.

TCIE4 = “0” : disable TCIF4 interrupt

TCIE4 = “1” : enable TCIF4 interrupt

Bit 1 ( SPIE ) : SPI Interrupt enable bit.

SPIE = “0” : disable SPIF interrupt

SPIE = “1” : enable SPIF interrupt

Bit 0 ( TCIE3 ) : Timer/Counter 3 Interrupt enable bit.

TCIE3 = “0” : disable TCIF3 interrupt

TCIE3 = “1” : enable TCIF3 interrupt

—

Individual interrupt is enabled by setting its associated control bit in the IMR1

to "1".

Global interrupt is enabled by the ENI instruction and is disabled by the DISI

instruction.

IMR1 register is both readable and writable.

IMR2 − Interrupt Mask Register 2( Address: 0Fh )

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

UERRIE

URIE

UTIE

TBIE

EXIE1

TCIE0

Bit 6 ( UERRIE ) : UART receive error interrupt enable bit.

UERRIE = “0” : disable UERRIF interrupt

UERRIE = “1” : enable UERRIF interrupt

Bit 5 ( URIE ) : UART receive mode interrupt enable bit.

URIE = “0” : disable RBFF interrupt

URIE = “1” : enable RBFF interrupt

Bit 4 ( UTIE ) : UART transmit mode interrupt enable bit.

UTIE = “0” : disable TBEF interrupt

UTIE = “1” : enable TBEF interrupt

26 •

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Bit 3 ( TBIE ) : Time base timer interrupt enable bit.

TBIE = “0” : disable TBIF interrupt

TBIE = “1” : enable TBIF interrupt

Bit 2 ( EXIE1 ) : External INT 1 Interrupt enable bit.

EXIE1 = “0” : disable EXIF1 interrupt

EXIE1 = “1” : enable EXIF1 interrupt

Bit 0 ( TCIE0 ) : TCC Interrupt enable bit.

TCIE0 = “0” : disable TCIF0 interrupt

TCIE0 = “1” : enable TCIF0 interrupt

—

Individual interrupt is enabled by setting its associated control bit in the IMR2

to "1".

Global interrupt is enabled by the ENI instruction and is disabled by the DISI

instruction.

IMR2 register is both readable and writable.

4.4 CPU Operation Mode

Registers for CPU operation mode

R_BANK Address

BANK 0 0X05

NAME

SCR

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

PS2

R/W

PS1

R/W

PS0

R/W

SIS

REM

R/W

* R_BANK: Register Bank (bits 7, 6 of R3), R/W: Read/Write

Reset Occurs

SIS=0 + SLEP

SIS=1 + SLEP

IDLE MODE

CPU : Halts

Fosc: Oscillates

NORMAL MODE

CPU : Operating

Fosc: Oscillates

SLEEP MODE

CPU : Halts

Fosc: Stops

Interrupt

/SLEEP Pin Input

Fig 5. Operation Mode and Switching

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Table 2. Mode Switching Control

Mode Switch

Normal Æ Sleep

Sleep Æ Normal

Normal Æ Idle

Idle Æ Normal

Switch Method

Set SIS = 1, execute SLEP instruction

/SLEEP pin wake up

Note

Set SIS = 0, execute SLEP instruction

Interrupt

Table 3. Operation Mode

On-chip

Operation Mode

Frequency

CPU Code

Peripherals

Reset

Fosc

Reset

Fosc

Halt

Turn on

Turn off

Normal

Idle

Signal

Clock

Halt

Sleep

In NORMAL mode, the CPU core and on-chip peripherals operate in oscillator

frequency.

In IDLE mode, the CPU core halts, but the on-chip peripheral and oscillator circuit

remain active. IDLE mode is released to NORMAL mode by any interrupt source. If the

ENI instruction is set, an interrupt will be serviced first followed by executing the next

instruction which is after the IDLE mode is released and the interrupt service is finished.

If the ENI instruction is not set, the next instruction will be executed which is after the

IDLE mode start instruction. IDLE mode can also be released by setting the /RESET

pin to low and executing a reset operation.

In SLEEP mode, the internal oscillator is turned off and all system operation is halted.

SLEEP mode is released by /SLEEP pin (level sensitive or edge sensitive can be set by

System Control Register (SCR) bit 0 (REM)). After a warm-up period, the next

instruction will be executed which is after the SLEEP mode start instruction. SLEEP

mode can also be released by setting the /RESET pin to low and executing a reset

operation. In level sensitive mode, the /SLEEP pin must be confirmed in low level

before entering SLEEP mode. In edge sensitive mode, SLEEP mode is started even

when the /SLEEP pin is in high level.

Table 4. Wake-up Methods

SLEEP Mode

IDLE Mode

NORMAL

Mode

Wake-up Signal

R5 (SIS) = 1+SLEP

Instruction

R5 (SIS)= 0 + SLEP

Instruction

R5 (SIS)=(*)

1. Individual interrupt source

in IMR1, IMR2

1. Wake-up

2. WDT interrupt request

3. /INT0

No effect

(**)

No effect

(**)

2. Jump to the next

instruction or enter

IDLE mode

4. ENI instruction is not

executed

28 •

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SLEEP Mode

IDLE Mode

NORMAL

Mode

Wake-up Signal

R5 (SIS) = 1+SLEP

Instruction

R5 (SIS)= 0 + SLEP

Instruction

R5 (SIS)=(*)

1. Wake-up

1. Individual interrupt source

in IMR1, IMR2

2. Jump to an Interrupt

vector after RETI

instruction, then jump

to the next instruction

or enter IDLE mode

No effect

(**)

2. WDT interrupt request

3. /INT0

Interrupt

4. Execute ENI instruction

1. Wake-up

2. Jump to the next

instruction or

enter SLEEP

mode

/SLEEP pin

No effect

/RESET pin

Reset

WDT time out

*→ Don’t care

** → Interrupt request flag will be recorded

4.5 AD Converter

Registers for AD Converter Circuit

R_BANK Address NAME Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

BANK 1

0X0B

0X0C

0X0D

ADCR ADREF ADRUN ADCK1 ADCK0 ADP

R/W R/W R/W R/W R/W

ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0

R/W R/W R/W R/W R/W R/W R/W R/W

ADD9 ADD8 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2

ADIS2 ADIS1 ADIS0

R/W R/W R/W

ADIC

ADDH

TC2CK TC2CK TC2CK

BANK 1

0X08

ADDL

ISFR1

ADD1 ADD0

TC2M TC2S

R/W

TCIF3

R/W

SPIF

R/W

BANK 0

SPR

0x0E

0x0C

0x0E

EXIF5 TCIF2

R/W R/W

ADIF

R/W

EXIF3 TCIF4

R/W

ADOSCR CALI

SIGN VOF[2] VOF[1] VOF[0]

R/W

SPR

IMR1

EXIE5 TCIE2 ADIE

R/W R/W R/W

EXIE3 TCIE4

R/W R/W

SPIE

R/W

TCIE3

R/W

* R_BANK : Register Bank (bits 7, 6 of R3), R/W: Read / Write

* SPR : Special Purpose Registers

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AD7 (P97)

AD6 (P96)

AD5 (P95)

AD4 (P94)

VDD

VREF

Power Down

ADC

Start to Convert

(Successive Approximation)

AD3 (P93)

AD2 (P92)

AD1 (P91)

AD0 (P90)

Fosc/4

Fosc/16

Fosc/32

4 to 1

MUX

7 - 0

ADIC

ADCR

ISFR1

IMR1

ADCR

DATA BUS

Fig. 6. AD Converter

It is a 10-bit successive approximation type AD converter. The upper side of analog

reference voltage can select either internal VDD or external input pin P97 (VREF) by

setting the ADREF bit in ADCR.

ADC Data Register:

When the A/D conversion is complete, the result is loaded to the ADDH (8 bit) and

ADDL (2 bit). The START/END bit is cleared, and the ADIF is set.

A/D Sampling Time:

The accuracy, linearity, and speed of the successive approximation A/D converter are

dependent on the properties of the ADC. The source impedance and the internal

sampling impedance directly affect the time required to charge the sample holding

capacitor. The application program controls the length of the sample time to meet the

specified accuracy. Generally speaking, the program should wait for 2 μs for each KΩ

of the analog source impedance and at least 2 μs for the low-impedance source. The

maximum recommended impedance for the analog source is 10KΩ at VDD =5V. After

the analog input channel is selected, this acquisition time must be done before A/D

conversion can be started.

A/D Conversion Time:

ADCK0 and ADCK1 select the conversion time (Tct), in terms of instruction cycles.

This allows the MCU to run at maximum frequency without sacrificing accuracy of A/D

conversion. For the EM78P809N, the conversion time per bit is about 4μs. Table 5

shows the relationship between Tct and the maximum operating frequencies.

30 •

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Table 5

Max. Frequency

(Fc)

Max. Conversion

Rate per Bit

Max. Conversion

Rate

ADCK1:0 Operation Mode

0 0

0 1

1 0

1 1

Fc/4

Fc/16

1MHz

4MHz

8MHz

250kHz (4μs)

48us(20.8kHz)

8us(20.8kHz)

Fc/32

Reserved

4.6 Time Base Timer and Keytone Generator

Registers for AD Converter Circuit

R_BANK Address NAME Bit 7

Bit 6 Bit 5 Bit 4 Bit 3

Bit 2

Bit 1

Bit 0

BANK 1

BANK 0

SPR

0X0E

0x0F

TBKTC TEN

TCK1

TCK0

TBTEN TBTCK2 TBTCK1 TBTCK0

R/W

EXIF1

R/W

TCIF0

R/W

ISFR2

IMR2

UERRIF RBFF TBEF TBIF

R/W

UERRIE URIE UTIE

R/W R/W R/W

R/W

TBIE

R/W

EXIE1

R/W

TCIE0

R/W

Output Enable (P63)

Output Latch

Data Output

/TONE Pin

Fosc/2

MUX

Fosc/2

TCK1:0

TEN

TBKTC

Fig. 7. TONE Output Pin Configuration

Keytone output can generate 50% duty pulse for driving a piezo-electric buzzer. The

P63 must be set to “1” before keytone enable and it can be halted by setting P63 to “0”.

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P63

TEN

TONE Pin

Fig. 8. TONE Output Pin Timing Chart

Fosc/2²³

Fosc/2²¹

Fosc/2¹⁶

Fosc/2¹⁴

Fosc/2¹³

Fosc/2¹²

Fosc/2¹¹

Fosc/2⁹

MUX

Falling Edge

Detector

TBT

Interrupt

TBTEN

TBTCK2:0

TBKTC

Fig. 9. TBT Configuration

Time Base Timer is used to generate the base time for key scan or dynamic display

processing. The interrupt is generated in the first falling edge of the source clock after

TBTEN is set to “1”.

Source Clock

TBTEN

TBT Interrupt

Fig. 10. Time Base Timer Timing Chart

32 •

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4.7 UART (Universal Asynchronous Receiver/Transmitter)

Registers for UART Circuit

R_BANK Address NAME Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1 Bit 0

BANK 2

BANK 0

SFR

0X05

0X06

0X07

0X08

0X09

0x0F

URC1 URTD8 UMODE1 UMODE0 BRATE2 BRATE1 BRATE0 UTBE

TXE

R/W

URC2

SBIM1 SBIM0 UINVEN

R/W

PRE

R/W

URS URRD8 EVEN

R/W R/W

PRERR OVERR FMERR URBF

R/W R/W R/W

RXE

R/W

URRD URRD7 URRD6 URRD5 URRD4 URRD3 URRD2 URRD1 URRD0

URTD URTD 7 URTD 6 URTD 5 URTD 4 URTD 3 URTD 2 URTD 1 URTD0

ISFR2

IMR2

UERRIF

R/W

RBFF

R/W

TBEF

R/W

UTIE

R/W

TBIF

R/W

TBIE

R/W

EXIF1

R/W

TCIF0

R/W

UERRIE

R/W

URIE

R/W

EXIE1

R/W

TCIE0

R/W

TC4

Baud rate

generator

Fsystem

RX Control

Interrupt

Control

TX Control

TXE

RXE

RX shift register

Parity control

URRD

URTD8

UINVEN

URRD8

Error flag

Data Bus

URTD

UINVEN

Fig. 11. Function Block Diagram

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In Universal Asynchronous Receiver Transmitter (UART), each transmitted or received

character is individually synchronized by framing it with a start bit and stop bit.

Full duplex data transfer is possible since the UART has independent transmit and

receive sections. Double buffering for both sections allows the UART to be

programmed for continuous data transfer.

The figure below shows the general format of one character sent or received. The

communication channel is normally held in the marked state (high). Character

transmission or reception starts with a transition to the space state (low).

The first bit transmitted or received is the start bit (low). It is followed by the data bits, in

which the least significant bit (LSB) comes first. The data bits are followed by the parity

bit. If present, then the stop bit or bits (high) confirm the end of the frame.

In receiving, the UART synchronizes on the falling edge of the start bit. When two or

three “0” are detected during three samples, it is recognized as normal start bit and the

receiving operation is started.

Idle state

(mark)

START

bit

Parity STOP

bit

1 bit

7 or 8 bits

One character or frame

1 bit

1 bits

Fig. 12. DATA Format in UART

4.7.1 UART MODE:

There are three UART modes. Mode 1 (7 bits data) and Mode 2 (8 bits data) allow the

addition of a parity bit. The parity bit addition is not available in Mode 3. The Figure

below shows the data format in each mode.

10 11

UMODE

PRE

7 bits DATA

STOP

START

Mode 1

Parity STOP

STOP

START

8 bits DATA

START

Mode 2

Mode 3

Parity STOP

9 bits DATA

STOP

START

Fig. 13. UART Mode

34 •

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4.7.2 Transmitting:

In transmitting serial data, the UART operates as follows:

1. Set the TXE bit of the URC1 register to enable the UART transmission function.

2. Write data into the URTD register and the UTBE bit of the URC1 register will be set

by hardware.

3. Then start transmitting.

4. Serially transmitted data are transmitted in the following order from the TX pin.

5. Start bit: one “0” bit is output.

6. Transmit data: 7, 8 or 9 bits data are output from the LSB to the MSB.

7. Parity bit: one parity bit (odd or even selectable) is output.

8. Stop bit: one “1” bit (stop bit) is output.

Mark state: output “1” continues until the start bit of the next transmitted data.

After transmitting the stop bit, the UART generates a TBEF interrupt (if enabled).

4.7.3 Receiving:

In receiving, the UART operates as follows:

Set RXE bit of the URS register to enable the UART receiving function.

The UART monitors the RX pin and synchronizes internally when it detects a start

bit.

2. Receive data is shifted into the URRD register in the order from LSB to MSB.

3. The parity bit and the stop bit are received.

After one character received, the UART generates a RBFF interrupt (if enable).

And URBF bit of URS register will be set to 1.

4. The UART makes the following checks:

(a) Parity check: The number of 1 of the received data must match the even or

odd parity setting of the EVEN bit in the URS register.

(b) Frame check: The start bit must be 0 and the stop bit must be 1.

means the URRD register should be read out) before next received data is loaded

into the URRD register.

If any checks failed, the UERRIF interrupt will be generated (if enabled), and an

error flag is indicated in PRERR, OVERR or FMERR bit. The error flag should be

cleared by software else the UERRIF interrupt will occur when the next byte is

received.

5. Read received data from URRD register. And URBF bit will be clear by hardware.

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4.7.4 Baud Rate Generator:

The baud rate generator is comprised of a circuit that generates a clock pulse to

determine the transfer speed for transmission/reception in the UART.

The BRATE2~BRATE0 bits of the URC1 register can determine the desired baud rate.

4.8 SPI (Serial Peripheral Interface)

Registers for the SPI Circuit

R_BANK Address NAME Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

BANK 3

BANK 0

SFR

0X05

0X06

0X07

0x0E

SPIC1

SPIC2

SPID

SMP

R/W

SPIS

R/W

DCOL BRS2 BRS1 BRS0

EDS

DORD WBE

R/W

RBF

SPIM1 SPIM0

R/W R/W

SPID7 SPID6 SPID5 SPID4 SPID3 SPID2 SPID1 SPID0

R/W

ISFR1 EXIF5 TCIF2

R/W R/W

R/W

ADIF

R/W

EXIF3 TCIF4

R/W R/W

R/W

SPIF

R/W

TCIF3

R/W

IMR1

EXIE5 TCIE2 ADIE

EXIE3 TCIE4 SPIE TCIE3

R/W R/W R/W R/W

R/W

RBFI

RBF

DCOL

Set to 1

Clear

Tx Empty

Collision

Detector

Buffer Full

Detector

SHIFT Register

SPID

reg

TLS0~1

(8 bits)

SDI

SMP

DORD

SDO

Master/Slave

EDS

Edge

Select

BRS2~0

/SS

BRS2~0

/SS enable

Prescaler

4, 16, 64, 256,1024

Tsystem

Edge

Select

SCK

EDS

TC1/2

Fig. 14. SPI Block Diagram

36 •

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The serial interface are connected to external devices via P70 (/SCK), P71 (SI), P72

(SO). The serial interface can also be used as I/O port. In the transmit mode, P71 can

be used as normal I/O port and in receive mode, P72 and P71 can be used as normal

I/O ports.

4.8.1 Serial Clock:

Six internal clocks can be selected by setting BRS0 ~ BRS2 and the clock output to the

outside from /SCK (P70) pin. The External clock can also be used and connected to

/SCK (P70) pin.

4.8.2 Shift Direction and Sample Phase:

Setting up the DORD bit of the SPIC1 register can determine the shift direction. Setting

up the EDS bit of the SPIC1 register can select the rising edge or falling edge and latch

the data. Setting up the SMP bit of the SPIC2 register can select the sample phase at

the middle or at the end of the data output time.

4.8.3 Transfer Mode:

The transmit, receive, transmit/receive mode can be selected by setting SPIM0 ~

SPIM1.

(a) 8-bit Transmit Mode:

Set SPIM0 ~ SPIM12 to transmit mode and write data to the data buffer SPID.

Set SPIS to “1” to start transmission. The data are output sequentially to the SO

pin in synchronous with the serial clock. When the final bit of transfer data has

been transferred, the SPI interrupt is generated and SPIS is cleared to “0” by

hardware. In order to transmit the next data, the SPIS must be set to “1” again by

software. If the next data is not written to the data buffer, the transfer is not

started when using the internal clock.

shi f t start

shif t start

SPI S

RBF

WBE

shif t fi nish

SO pin

a0 a1 a2 a3 a4 a5 a6 a7

b0 b1 b2 b3 b4 b5 b6 b7

SPIF

SPID

write data

Fig. 15. Transmit Mode (8-bit, 1 word)

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(b) 8-bit Receive Mode:

Setting SPIM0 ~ SPIM1 to receive mode and setting SPIS to “1” to start receiving.

The data are input sequentially from the SI pin in synchronous with the serial

clock. When the final bit of transfer data has been received, the SPI interrupt is

generated and SPIS is cleared to “0” by hardware. In order to receive the next

data, the SPIS must be set to “1” again by software. If the current data is not read

out from the data buffer, receiving is not started when using internal clock.

shift start

shi f t start

shift finish

RBF

WBE

/SCK pin

SI pi n

a0 a1 a2 a3 a4 a5 a6 a7

b0 b1 b2 b3 b4 b5 b6 b7

SPI F

SPI D

read data

Fig. 16. Receive Mode (8-bit, 1 word)

Set SPIM0 ~ SPIM1 to transmit/receive mode and write data to data buffer SPID.

Set SPIS to “1” to start transferring. The data are output to the SO pin and input

from the SI pin sequentially in synchronous with the serial clock. When the

number of data words specified has been transferred, the SPI interrupt is

generated and SPIS is cleared to “0” by hardware. In order to receive the next

data, the SPIS must be set to “1” again by software. Writing data in transmit

mode and reading data in receive mode use the same data buffer. If the current

data is not read out from the data buffer and then write the data to data buffer, the

transfer is not started when using internal clock. Always write the data to be

transmitted after reading the received data.

38 •

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shift start

SPI S

shift finish

RBF

WBE

/SCK pin

SO pi n

SI pi n

b0 b1 b2 b3 b4 b5 b6 b7

d0 d1 d2 d3 d4 d5 d6 d7

a0 a1 a2 a3 a4 a5 a6 a7

c0 c1 c2 c3 c4 c5 c6 c7

SPI F

SPI D

write data

read data writedata

read data

Fig. 17. Transmit/Receive Mode (8-bit, 1 word)

(d) Multiple Device Connect (/SS):

When selecting external clock for transfer clock source, the /SS function can be

used. This pin (/SS) will be active when the /SS function is enabled, else the /SS

pin is a general purpose I/O. Ignore the data on the SDI and SDO pins while /SS

is high, since the SDO is no longer driven.

SDO

SDI

SCK

/SS

PP.6677

Master

P66

P 65

P65

PP6644

/SS

SCK

SDO

SDI

/SS

SCK

SDO

SDI

/SS

SCK

SDO

SDI

/SS

SCK

SDO

SDI

Slave Device 1

Slave Device 2

Slave Device 3

Slave Device 4

Fig. 18. The SPI Configuration Example of Single-Master and Multi-Slaves

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4.9 Timer/Counter 2

Registers for Timer/Counter 2 Circuit

R_BANK Address NAME Bit 7 Bit 6

Bit 5

Bit 4

TC2M

R/W

Bit 3

TC2S TC2CK2 TC2CK1 TC2CK0

R/W R/W R/W R/W

Bit 2

Bit 1

Bit 0

BANK 1

BANK 0

SFR

0X08

0X09

0X0A

0x0E

0x0B

0x0E

TC2CR ADD1

ADD0

TC2DH TC2D15 TC2D14 TC2D13 TC2D12 TC2D11 TC2D10 TC2D9 TC2D8

R/W R/W R/W R/W R/W R/W R/W R/W

TC2DL TC2D7 TC2D6 TC2D5 TC2D4 TC2D3 TC2D2 TC2D1 TC2D0

R/W

EXIF5

R/W

TCIF2

R/W

ADIF

R/W

EXIF3

R/W

TCIF4

R/W

SPIF

R/W

TCIF3

R/W

ISFR1

INTCR INT1NR INT0EN

INT3ES1 INT3ES0

INT1ES TC2ES

R/W

EXIE5

R/W

TCIE2

R/W

EXIE3

R/W

SPIE

R/W

TCIE3

R/W

SFR

IMR1

ADIE

R/W

TCIE4

R/W

TC2ES

TC2

Window

fc/2²³

Clear

16-bit Up-counter

fc/2

fc/2⁸

fc/2³

MUX

TC2

Interrupt

Comparator

TC2CK

TC2S

TCR2H

TCR2L

TC2CR

Fig 19. Configuration of Timer/Counter 2

40 •

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EM78P809N

8-Bit Microcontroller

4.9.1 Timer Mode:

In Timer mode, counting up is performed using the internal clock. When the contents of

the up-counter matched with the TCR2 (TCR2H+TCR2L), then interrupt is generated

and the counter is cleared. Counting up resumes after the counter is cleared.

Internal clock

n-3

n-2

n-1

Up-counter

TCR2

counter

clear

match

TC2 interrupt

Fig. 20. Timer Mode Timing Chart

4.9.2 Counter Mode:

In Counter mode, counting up is performed using the external clock input pin (TC2 pin)

and either rising or falling can be selected by setting TC2ES. When the contents of

the up-counter matched with the TCR2 (TCR2H+TCR2L), then interrupt is generated

and the counter is cleared. Counting up resumes after the counter is cleared.

TC2 Pin

n-2

n-1

Up-counter

TCR2

counter

clear

match

TC2 interrupt

Fig. 21. Counter Mode Timing Chart (TC2ES = 1)

4.9.3 Window Mode

In Window mode, counting up is performed on the rising or falling edge of the pulse

that is logical AND of an internal clock and the TC2 pin (window pulse). When the

contents of the up-counter matched with the TCR2 (TCR2H+TCR2L), then interrupt is

generated and the counter is cleared. The frequency (window pulse) must be slower

than the selected internal clock.

Writing to the TCR2L, the comparison is inhibited until TCR2H is written.

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8-Bit Microcontroller

TC2 pin

Internal clock

n-3

n-1

Up-counter

TCR2

n-2

counter

cl ear

match

TC2 interrupt

Fig. 22. Window Mode Timing Chart

4.10 Timer/Counter 3

Registers for Timer/Counter 3 Circuit

R_BANK Address NAME Bit 7 Bit 6

TC3CR TC3CAP TC3S TC3CK1 TC3CK0 TC3M

R/W R/W R/W R/W R/W

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

BANK 1

BANK 0

SFR

0X05

0X06

0X07

0x0E

0x0B

0x0E

TC3DA TC3DA7 TC3DA6 TC3DA5 TC3DA4 TC3DA3 TC3DA2 TC3DA1 TC3DA0

R/W R/W R/W R/W R/W R/W R/W R/W

TC3DB TC3DB7 TC3DB6 TC3DB5 TC3DB4 TC3DB3 TC3DB2 TC3DB1 TC3DB0

R/W

EXIF5

R/W

TCIF2

R/W

ADIF

R/W

EXIF3

R/W

TCIF4

R/W

SPIF

R/W

TCIF3

R/W

ISFR1

INTCR INT1NR INT0EN

INT3ES1 INT3ES0

INT1ES TC2ES

R/W

EXIE5

R/W

TCIE2

R/W

EXIE3

R/W

SPIE

R/W

TCIE3

R/W

SFR

IMR1

ADIE

R/W

TCIE4

R/W

42 •

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8-Bit Microcontroller

Rising

Falling

Inhibit

Edge

Detector

Capture

Control

TC3

Interrupt

INT3ES

TC3M

TC3 pin

MUX

fc/2¹²fs/2

Overflow

fc/2¹⁰fs/2²

8-bit Up-counter

fc/2

TC3S

TC2CK

Comparator

CAP

Capture

TC3CR

TCR3B

TCR3A

Fig. 23. Configuration of Timer/Counter3

4.10.1 Timer Mode:

In Timer mode, counting up is performed using the internal clock. When the contents of

the up-counter matched with the TCR3DA, then interrupt is generated and the counter

is cleared. Counting up resumes after the counter is cleared. The current contents of

the up-counter are loaded into the TCR3DB by setting TC3CAP to “1” and the TC3CAP

is cleared to “0” after capture automatically.

4.10.2 Counter Mode:

In Counter mode, counting up is performed using the external clock input pin (TC3 pin)

and either rising or falling edge can be selected by INT3ES0 but both edge cannot

be used. When the contents of the up-counter matched with the TCR3DA, then

interrupt is generated and the counter is cleared. Counting up resumes after the

counter is cleared. The current contents of the up-counter are loaded into the TCR3DB

by setting TC3CAP to “1” and the TC3CAP is cleared to “0” after capture automatically.

4.10.3 Capture mode:

In Capture mode, the pulse width, period and duty of the TC3 input pin are measured in

this mode, which can be used in decoding the remote control signal. The counter is

free running by the internal clock. On the rising (falling) edge of TC3 pin input, the

contents of the counter is loaded into TCR3DA, then the counter is cleared and

interrupt is generated. On the falling (rising) edge of TC3 pin input, the contents of the

counter are loaded into TCR3DB. The counter is still counting, on the next rising edge

of the TC3 pin input, the contents of the counter are loaded into TCR3A, counter is

Product Specification (V1.0) 07.26.2005

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8-Bit Microcontroller

cleared and interrupt is generated again. If an overflow before the edge is detected,

the FFH is loaded into TCR3DA and an overflow interrupt is generated. During

interrupt processing, it can be determined whether or not there is an overflow by

checking whether the TCR3DA value is FFH. After an interrupt (capture to TCR3DA or

overflow detection) is generated, capture and overflow detection are halted until

TCR3DA is read out.

Source Clock

Up-counter

m-1

m+1

n-1

K-2

K-1

FE FF0

TC3 Pin Input

FF (Overflow)

Overflow

TCR3DA

TCR3DB

Capture

TC3 Interrupt

Reading TCR3DA

Fig. 24.Timing Chart of Capture Mode

4.11 Timer/Counter 4

Registers for Timer 4 Circuit

R_BANK Address NAME Bit 7

Bit 6

TC4CR TC4FF1 TC4FF0 TC4S TC4CK2 TC4CK1 TC4CK0 TC4M1 TC4M0

R/W R/W R/W R/W R/W R/W R/W R/W

TC4D7 TC4D6 TC4D5 TC4D4 TC4D3 TC4D2 TC4D1 TC4D0

R/W R/W R/W R/W

EXIF3 TCIF4 SPIF TCIF3

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

BANK 0

SFR

0X0B

0X0C

0x0E

TC4D

R/W

ISFR1 EXIF5 TCIF2 ADIF

R/W

EXIE5

R/W

TCIE2

R/W

ADIE

R/W

EXIE3

R/W

TCIE4

R/W

SPIE

R/W

TCIE3

R/W

IMR1

44 •

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EM78P809N

8-Bit Microcontroller

TC4FF

TC4M (1,1)

TC4 Interrupt

F/F

/PWM, /PDO Pin

Clear

Set

Clear

fc/2

TC4M(1,*)

fc/2 ⁷

fc/2 ³

Toggle

MUX

8-bit Up-counter

Overflow

Match

TC4 pin

Comparator

TC4CK

TC4S

TC4CR

TCR4

Fig. 25. Timer/Counter 4 Configuration

4.11.1 Timer Mode

In Timer mode, counting up is performed using the internal clock. When the contents of

the up-counter matched with the TCR4, then interrupt is generated and the counter is

cleared. Counting up resumes after the counter is cleared.

4.11.2 Counter Mode

In Counter mode, counting up is performed on the rising edge of the external clock

input pin (TC4 pin). When the contents of the up-counter matched with the TCR4, then

interrupt is generated and the counter is cleared. Counting up resumes after the

counter is cleared.

4.11.3 PDO Mode

In Programmable Divider Output (PDO) mode, counting up is performed using the

internal clock. The contents of TCR4 are compared with the contents of the

up-counter. The F/F output is toggled and the counter is cleared each time a match is

found. The F/F output is inverted and output to /PDO pin. This mode can generate

50% duty pulse output. The F/F can be initialized by the program and it is initialized to

“0” during a reset. A TC4 interrupt is generated each time the /PDO output is toggled.

Source Clock

Up-counter

TCR4

n-1

F/F

/PDO Pin

TC4 Interrupt

Fig. 26.Timing Chart for PDO Mode

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8-Bit Microcontroller

4.11.4 PWM Mode

In Pulse Width Modulation (PWM) Output mode, counting up is performed using the

internal clock. The contents of the TCR4 are compared with the contents of the

up-counter. The F/F is toggled when match is found. The counter is still counting, the

F/F is toggled again when the counter overflows, then the counter is cleared. The F/F

output is inverted and output to the /PWM pin. A TC4 interrupt is generated each time

an overflow occurs. TCR4 is configured as a 2-stage shift register and, during output,

will not switch until one output cycle is completed even if TCR4 is overwritten.

Therefore, the output can be changed continuously. TRC4 is also shifted the first time

by setting TC4S to “1” after data is loaded to TCR4.

Source Clock

m-1

Up-counter

TCR4

n-1

n+1 n+2

n-1

n+2

FE FF

n+1

FE FF

n/n

n/m

m/m

Shift

Overflow

Match

Overflow

Match

Overwrite

F/F

/PWM

1 Period

TC4 Interrupt

Fig. 27.Timing Chart for PWM Mode

4.12 TCC/WDT & Prescaler

An 8-bit counter is available as prescaler for the TCC. The PSR0~PSR2 bits determine

the ratio. The prescaler is cleared each time the instruction is written to TCC under

TCC mode.

R1 (TCC) is an 8-bit timer/counter. The clock source of TCC is the internal clock. If the

TCC signal source is from the internal clock, TCC will increase by 1 at every instruction

cycle (without prescaler). CLK=Fosc/2 or CLK=Fosc/4 selection is determined by the

CODE Option bit CLK status. CLK=Fosc/2 is used if CLK bit is "0", and CLK=Fosc/4 is

used if CLK bit is "1".

The watchdog timer is a free running on-chip RC oscillator. During normal operation

mode, a WDT time-out (if enabled) will cause the device to reset or interrupt by setting

WDTO. The WDT can be enabled or disabled any time during normal mode by

software programming. Without prescaler, the WDT time-out period is approximately

18 ms (default). The WDT can also be used as a timer to generate an interrupt at fixed

interval.

46 •

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8-Bit Microcontroller

4.13 I/O Ports

The I/O registers, Port 6, Port 7, Port 8, and Port 9 are bi-directional tri-state I/O ports.

Each I/O pin can be defined as “input” or “output” pin by the I/O control register (IOC6 ~

IOC9). The I/O registers and I/O control registers are both readable and writable. The

I/O interface circuits for Port 6, Port 7, Port 8, and Port 9 are shown in Fig. 27.

PCRD

CLK

PCWR

IOD

PORT

PDWR

PDRD

CLK

Fig. 28.The I/O Port and I/O Control Register Circuit

4.14 RESET and Wake-up

4.14.1 RESET

A RESET is initiated by one of the following events:

(1) Power-on reset

(2) /RESET pin input “low”

(3) WDT timeout. (if enabled)

The device is kept in a RESET condition for a period of approx. 18ms¹(one oscillator

start-up timer period) after the reset is detected. Once a RESET occurs, the following

functions are performed.

„

The oscillator starts or is running

The Program Counter (R2) is reset to all “0”.

When power is switched on, the upper 2 bits of R3, the upper 2 bits of R4 and the

bits 6 ~ 4 of R5 are cleared.

„

All I/O port pins are configured as input mode (high-impedance state).

¹NOTE: VDD = 5V, set up time period = 16.2ms ± 30%

VDD = 3V, set up time period = 19.6ms ± 30%

Product Specification (V1.0) 07.26.2005

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8-Bit Microcontroller

„

The Watchdog timer and prescaler are cleared.

Upon power on, the upper 2 bits of R3 are cleared.

Upon power on, the upper 2 bits of R4 are cleared.

Upon power on, the upper 3 bits of R5 are cleared.

The bits of CONT register are set to all “1” except bit 6 (INT flag).

ISFR0, ISFR1, ISFR2 register and IMR1, IMR2 registers are cleared.

The controller has two modes for power saving.

(1) SLEEP mode: R5 (SIS) = 1, SLEP instruction.

The internal oscillator is turned off and all system operation is halted.

(2) IDLE mode: R5 (SIS)= 0, SLEP instruction

The CPU core halts but the on-chip peripheral and oscillator circuit remain active.

4.14.2 Wake-up from SLEEP Mode:

(1) External /SLEEP pin

The controller will be waken up and execute the next instruction after entering SLEEP

mode. All the registers will maintain their original values before “SLEP” instruction was

executed.

(2) /RESET pin pull low

This will reset the controller and starts the program at address zero.

(3) WDT time out

This will reset the controller and run the program at address zero.

4.14.3 Wake-up from IDLE mode:

(1) All interrupt

In all these cases, user should always enable the circuit before entering IDLE mode.

After wake-up, all registers will maintain their original values before entering “SLEP”

instruction, then service an interrupt subroutine or proceed with next instruction by

setting individual interrupt enable bit. After servicing an interrupt sub-routine (“RETI”

instruction), the program will jump from “SLEP” instruction to the next instruction.

(2) /RESET pin pull low

This will reset the controller and run the program at address zero.

(3) WDT time out

This will reset the controller and run the program at address zero.

48 •

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8-Bit Microcontroller

Table 6. Summary of the Initialized Values for Registers

Address Name

Reset Type

Bit 7

C67

Bit 6

C66

Bit 5

C65

Bit 4

C64

Bit 3

C63

Bit 2

C62

Bit 1

C61

Bit 0

C60

Bit Name

Power-On

0x06

IOC6

/RESET and WDT time out

Wake-Up from SLEEP, IDLE mode

Bit Name

Power-on

/RESET and WDT time out

Wake-Up from SLEEP, IDLE mode

Bit Name

C95

C73

C72

C71

C81

C91

C70

C80

C90

0x07

0x08

0x09

0x0B

0x0C

0x0E

0x0F

N/A

IOC7

IOC8

Power-on

C92

/RESET and WDT time out

Wake-Up from SLEEP, IDLE mode

Bit Name

C97

C96

C94

C93

Power-On

IOC9

/RESET and WDT time out

Wake-Up from SLEEP, IDLE mode

Bit Name

INT1NR INT0EN

INT3ES1 INT3ES0

INT1ES TC2ES

Power-On

CALI

INTCR

/RESET and WDT time out

Wake-Up from SLEEP, IDLE mode

Bit Name

SIGN VOF2 VOF1 VOF0

ADOSC Power-on

UTIE

/RESET and WDT time out

Wake-Up from SLEEP, IDLE mode

Bit Name

EXIE5 TCIE2 ADIE

EXIE3 TCIE4 SPIE TCIE3

Power-on

IMR1

/RESET and WDT time out

Wake-Up from SLEEP, IDLE mode

Bit Name

UERRIE URIE

TBIE EXIE1

TCIE0

Power-on

IMR2

/RESET and WDT time out

Wake-Up from SLEEP, IDLE mode

Bit Name

WDT0

/INT WDTP1 WDTP0 WDTE PSR2 PSR1 PSR0

Power-on

CONT

/RESET and WDT time out

Wake-Up from SLEEP, IDLE mode

Bit Name

Power-on

(IAR)

0x00

/RESET and WDT time out

Wake-Up from SLEEP, IDLE mode

Bit Name

Power-on

(TCC)

0x01

0x02

/RESET and WDT time out

Wake-Up from SLEEP, IDLE mode

Bit Name

Power-on

(PC)

/RESET and WDT time out

Wake-Up from SLEEP, IDLE mode

Bit Name

Jump to interrupt vector or execute next instruction

RBS1 RBS0

(SR)

Power-on

0x03

0x04

/RESET and WDT time out

Wake-Up from SLEEP, IDLE mode

Bit Name

GRBS1 GRBS0 RSR5 RSR4 RSR3 RSR2 RSR1 RSR0

(RSR)

Power-On

/RESET and WDT time out

Wake-Up from SLEEP, IDLE mode

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8-Bit Microcontroller

Address Name

Bit Name

Reset Type

Bit 7

Bit 6

PS2

Bit 5

PS1

Bit 4

PS0

Bit 3

Bit 2

Bit 1

SIS

Bit 0

REM

Power-On

0x05

SCR

/RESET and WDT time out

Wake-Up from SLEEP, IDLE mode

Bit Name

P67

P66

P65

P64

P63

P62

P61

P60

Power-On

0x06 PORT6

0x07 PORT7

0x08 PORT8

0x09 PORT9

/RESET and WDT time out

Wake-Up from SLEEP, IDLE mode

Bit Name

P73

P72

P71

P70

Power-On

/RESET and WDT time out

Wake-Up from SLEEP, IDLE mode

Bit Name

P81

P80

Power-On

/RESET and WDT time out

Wake-Up from SLEEP, IDLE mode

Bit Name

P97

P96

P95

P94

P93

P92

P91

P90

Power-On

/RESET and WDT time out

Wake-Up from SLEEP, IDLE mode

Bit Name

TC4FF1 TC4FF0 TC4S TC4CK2 TC4CK1 TC4CK0 TC4M1 TC4M0

Power-On

0x0B TC4CR

/RESET and WDT time out

Wake-Up from SLEEP, IDLE mode

Bit Name

TC4D7 TC4D6 TC4D5 TC4D4 TC4D3 TC4D2 TC4D1 TC4D0

Power-On

0x0C

TC4D

/RESET and WDT time out

Wake-Up from SLEEP, IDLE mode

Bit Name

INT3F INT3R

WDTIF EXIF0

Power-On

0X0D ISFR0

/RESET and WDT time out

Wake-Up from SLEEP, IDLE mode

Bit Name

EXIF5 TCIF2 ADIF

EXIF3 TCIF4

SPIF TCIF3

Power-On

0X0E

0X0F

ISFR1

ISFR2

/RESET and WDT time out

Wake-Up from SLEEP, IDLE mode

Bit Name

UERRIF RBFF TBEF

TBIF

EXIF1

TCIF0

Power-On

/RESET and WDT time out

Wake-Up from SLEEP, IDLE mode

50 •

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8-Bit Microcontroller

Address Name

Reset Type

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bit Name

Power-On

TC3CAP TC3S TC3CK1 TC3CK0 TC3M

0x05 TC3CR

0x06 TC3DA

/RESET and WDT time out

Wake-Up from SLEEP, IDLE mode

Bit Name

TC3DA7 TC3DA6 TC3DA5 TC3DA4 TC3DA3 TC3DA2 TC3DA1 TC3DA0

Power-On

/RESET and WDT time out

Wake-Up from SLEEP, IDLE mode

Bit Name

TC3DB7 TC3DB6 TC3DB5 TC3DB4 TC3DB3 TC3DB2 TC3DB1 TC3DB0

Power-On

0x07 TC3DB

TC2CR

/RESET and WDT time out

Wake-Up from SLEEP, IDLE mode

Bit Name

ADD1 ADD0

TC2M TC2S TC2CK2 TC2CK1 TC2CK0

Power-On

0x08

/RESET and WDT time out

Wake-Up from SLEEP, IDLE mode

Bit Name

ADDL

TC2D15 TC2D14 TC2D13 TC2D12 TC2D11 TC2D10 TC2D9 TC2D8

Power-On

0x09 TC2DH

/RESET and WDT time out

Wake-Up from SLEEP, IDLE mode

Bit Name

TC2D7 TC2D6 TC2D5 TC2D4 TC2D3 TC2D2 TC2D1 TC2D0

Power-On

0x0A

0x0B

0x0C

0X0D

TC2DL

ADCR

ADIC

/RESET and WDT time out

Wake-Up from SLEEP, IDLE mode

Bit Name

ADREF ADRUN ADCK1 ADCK0 ADP

ADIS2 ADIS1 ADIS0

Power-On

/RESET and WDT time out

Wake-Up from SLEEP, IDLE mode

Bit Name

(*)

ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0

Power-On

/RESET and WDT time out

Wake-Up from SLEEP, IDLE mode

Bit Name

ADD9 ADD8 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2

Power-On

ADDH

/RESET and WDT time out

Wake-Up from SLEEP, IDLE mode

Bit Name

TEN

TCK1 TCK0

TBTEN TBTCK2 TBTCK1 TBTCK0

Power-On

0X0E TBKTC

/RESET and WDT time out

Wake-Up from SLEEP, IDLE mode

Product Specification (V1.0) 07.26.2005

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8-Bit Microcontroller

Address Name

Bit Name

Reset Type

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

TXE

URTD8 UMODE1 UMODE0 BRATE2 BRATE1 BRATE0 UTBE

Power-On

0x05

URC1

/RESET and WDT time out

Wake-Up from SLEEP, IDLE mode

Bit Name

SBIM1 SBIM0 UINVEN

Power-On

0x06

URC2

/RESET and WDT time out

Wake-Up from SLEEP, IDLE mode

Bit Name

URRD8 EVEN

PRE PRERR OVERR FMERR URBF

RXE

Power-On

0x07

0x08

0x09

URS

URRD

URTD

/RESET and WDT time out

Wake-Up from SLEEP, IDLE mode

Bit Name

URRD7 URRD6 URRD5 URRD4 URRD3 URRD2 URRD1 URRD0

Power-On

/RESET and WDT time out

Wake-Up from SLEEP, IDLE mode

Bit Name

URTD 7 URTD 6 URTD 5 URTD 4 URTD 3 URTD 2 URTD 1 URTD0

Power-On

/RESET and WDT time out

Wake-Up from SLEEP, IDLE mode

Address Name

Reset Type

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bit Name

Power-On

/RESET and WDT time out

Wake-Up from SLEEP, IDLE mode

Bit Name

SMP

SPIS

DCOL BRS2 BRS1 BRS0

EDS DORD WBE

0x05

0x06

0x07

0x0A

0x0B

0x0C

SPIC1

SPIC2

SPID1

PHC1

PLC2

PHC2

SPIM1 SPIM0 RBF

Power-On

/RESET and WDT time out

Wake-Up from SLEEP, IDLE mode

Bit Name

SPID17 SPID16 SPID15 SPID14 SPID13 SPID12 SPID11 SPID10

Power-On

/RESET and WDT time out

Wake-Up from SLEEP, IDLE mode

Bit Name

/PHE81 /PHE80 /PHE63 /PHE62 /PHE61 /PHE60

Power-On

/RESET and WDT time out

Wake-Up from SLEEP, IDLE mode

Bit Name

/PLE81 /PLE80 /PLE63 /PLE62 /PLE61 /PLE60

Power-On

/RESET and WDT time out

Wake-Up from SLEEP, IDLE mode

Bit Name

/PHE73 /PHE72 /PHE71 /PHE70

Power-On

/RESET and WDT time out

Wake-Up from SLEEP, IDLE mode

Bit Name

/PLE73 /PLE72 /PLE71 /PLE70

Power-On

0x0D

PLC2

/RESET and WDT time out

Wake-Up from SLEEP, IDLE mode

52 •

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EM78P809N

8-Bit Microcontroller

General Purpose Registers

Address Name

Reset Type

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bit Name

0x10

R10

Power-On

/RESET and WDT time out

Wake-Up from SLEEP, IDLE mode

0x3F

R3F

X: Not used. U: Unknown or don’t care. P: Previous value before reset. t: Check Table 7

(*) 0: Wake-Up from SLEEP P: Wake-Up from IDLE

4.14.4

The Status of RST, T, and P of STATUS Register

The values of T and P are used to verify the event that triggered the processor to wake

up. Table 7 shows the events that may affect the status of T and P.

Table 7. The Values of RST, T and P after RESET

Reset Type

Power on

/RESET during Operation mode

/RESET wake-up during SLEEP mode

/RESET wake-up during IDLE mode

WDT during Operation mode

WDT wake-up during SLEEP mode

WDT wake-up during IDLE mode

*P: Previous status before reset

Table 8 The Events that may Affect the T and P Status

Event

Power on

WDTC instruction

WDT time-out

SLEP instruction

Wake-Up during SLEEP mode

*P: Previous value before reset

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8-Bit Microcontroller

VDD

CLK

Oscillator

CLR

Power-on

Reset

Voltage

Detector

WDTE

WDT Timeout

Setup Time

RESET

WDT

/RESET

Fig. 29.Controller Reset Block Diagram

4.15 Interrupt

The EM78P809N has 15 interrupts (9 external, 6 internal) listed below:

Table 9.. Interrupt Vector

Interrupt Source

Enable Condition Int. Flag Int. Vector Priority

Internal /

Reset

0000

High 0

External

Internal

External

Internal

External

Internal

External

Internal

External

Internal

External

Internal

External

WDT

WDTEN

WDTIF

EXIEF0

TCIF0

EXIF1

TBIF

0003

0006

0009

000F

0012

0015

0018

001B

0021

0024

0027

002A

0030

0033

0036

INT0

ENI + INT0EN=1

ENI + TCIE0=1

ENI + EXIE1=1

ENI + TBIE=1

ENI + UTIE=1

ENI + URIE=1

ENI+UERRIE=1

ENI + TCIE3=1

ENI + SPIE=1

ENI + TCIE4=1

ENI + EXIE3=1

ENI + ADIE=1

ENI + TCIE2=1

ENI + EXIE5=1

TCC

INT1

TBT

UART Transmit

TBEF

TBFF

UART Receive

UART Receive error

UERRIF

TCIF3

SPIF

TC3

SPI

TC4

INT3

TCIF4

EXIF3

ADIF

TC2

INT5

TCIF2

EXIF5

Low 15

ISFR0, ISFR1 and ISFR2 are the interrupt status registers that record the interrupt

requests in the relative flags/bits. IMR1 and IMR2 are the interrupt mask registers. The

global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction.

54 •

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When one of the interrupts (enabled) occurs, the next instruction will be fetched from

individual address. The interrupt flag bit must be cleared by instructions before leaving

the interrupt service routine and before interrupts are enabled to avoid recursive

interrupts.

The flag (except ICIF bit) in the Interrupt Status Register (ISFR 2) is set regardless of

the status of its mask bit or the execution of ENI. The RETI instruction ends the

interrupt routine and enables the global interrupt (the execution of ENI).

4.16 Oscillator

4.16.1

Oscillator Modes

The EM78P809N can operate in two different oscillator modes, i.e., Crystal oscillator

mode and External RC oscillator mode (ERC) oscillator mode. User can select which

mode by Code Option Register. The maximum limit for operational frequencies of the

crystal/resonator under different VDDs is listed below.

Table 10 Oscillator Modes Defined by SDCS and OSC

Mode

OSC

Oscillator

High frequency oscillator

ERC

Single Clock

Table 11 The Summary of Maximum Operating Speeds

Condition

VDD

Max. Fxt. (MHz)

3.0

5.0

4.0

High frequency oscillator

10.0

4.16.2

Crystal Oscillator/Ceramic Resonators (Crystal)

EM78P809N has a clock generator. i.e. Fc (high frequency) which can be driven by an

external clock signal through the OSCI pin.

In most applications, Pin OSCI and Pin OSCO can be connected with a crystal or

ceramic resonator to generate oscillation. Table 12 provides the recommended values

of C1 and C2. Since each resonator has its own attribute, user should refer to its

specification for appropriate values of C1 and C2. A serial resistor Rs may be

necessary for AT strip cut crystal.

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EM78P809N

8-Bit Microcontroller

OSCI

Ext. Clock

OSCO

EM78P809N

Fig. 30. Crystal/Resonator Circuit

OSCI

XTAL

EM78P809N

OSCO

Fig. 31. Crystal/Resonator Circuit

Table12. Capacitor Selection Guide for Crystal Oscillator or Ceramic Resonator

Oscillator Type

Frequency Mode

Frequency C1 (pF)

C2 (pF)

20~40

10~30

15~30

2.0 MHz

4.0 MHz

1.0MHz

2.0MHz

4.0MHz

20~40

10~30

15~30

Ceramic Resonator

HXT

Crystal Oscillator

HXT

OSCI

740

EM78P809N

XTAL

Fig. 32. Crystal/Resonator-Series Mode Circuit

56 •

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EM78P809N

8-Bit Microcontroller

4.7

Vdd

OSCI

740

EM78P809N

XTAL

Fig. 33. Crystal/Resonator-Parallel Mode Circuit

4.16.3

External RC Oscillator Mode

For applications that do not need very precise timing calculation, the RC oscillator

offers a lot of cost savings. Nevertheless, it should be noted that the frequency of the

RC oscillator is influenced by the supply voltage, the values of the resistor (Rext), the

capacitor (Cext), and even by the operation temperature. Moreover, the frequency

also varies slightly from one chip to another due to the manufacturing process variation.

In order to maintain a stable system frequency, the values of the Cext should not be

less than 20pF, and the value of Rext should not be greater than 1 MΩ, otherwise, the

frequency is easily affected by noise, humidity, and leakage.

The smaller the Rext in the RC oscillator, the faster its frequency will be. On the

contrary, for very low Rext values, for instance, 1 KΩ, the oscillator becomes unstable

because the NMOS cannot correctly discharge the current of the capacitance.

Hence, it must be noted that the supply voltage, the operation temperature, the RC

oscillator components, the package types, and the PCB layout, will affect the system

frequency.

Vdd

Rext

OSCI

Cext

EM78P809N

Fig. 34. External RC Oscillator Mode Circuit

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Table13. RC Oscillator Frequencies

Cext

Rext

3.3k

5.1k

10k

Average Fosc 5V, 25°C Average Fosc 3V, 25°C

4.32 MHz

2.83 MHz

1.62 MHz

184kHz

1.39 MHz

950kHz

500kHz

54kHz

3.56 MHz

2.8 MHz

1.57 MHz

187kHz

1.35 MHz

930kHz

490kHz

55kHz

20 pF

100 pF

300 pF

100k

3.3k

5.1k

10k

100k

3.3k

5.1k

10k

580kHz

390kHz

200kHz

21kHz

550kHz

380kHz

200kHz

21kHz

100k

Note: 1. Measured on DIP packages.

2. For design reference only.

4.17 Code Option Register

The EM78P809N has one CODE option word that is not part of the normal program

memory. The option bits cannot be accessed during normal program execution.

Code Option Register and Customer ID Register arrangement distribution:

Word 0

Word 1

Word 2

Bit 12~Bit 0

4.17.1 Code Option Register (Word 0)

Word 0

Bit 12 ~ 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

PR1

Bit 0

CLKS

ENWDTB CYES

OSC

HLP

PR2

PR0

Bit 12 ~ 9 : Not used

Bit 8 (CLKS) : Instruction period option bit.

CLKS = “0” : two oscillator periods.

CLKS = “1” : four oscillator periods.

Refer to the Instruction Set section.

Bit 7 (ENWDTB) : Watchdog timer enable bit.

ENWDTB = “0” : Enable

ENWDTB = “1” : Disable

58 •

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8-Bit Microcontroller

Bit 6 (CYES) : Cycle selection for JMP, CALL instruction

CYES = “0” : One cycle

CYES = “1” : Two cycles

Bit 4 (OSC) : Oscillator type selection.

OSC = “0” : RC type

OSC = “1” : Crystal type

Bit 3 (HLP) : Power selection.

HLP = “0” : Low power

HLP = “1” : High power

Bit 2~0 (PR2~PR0) : Protect Bit

PR2~PR0 are write-protect bits, configured as follows:

PR2

PR1

Others

PR0

Protect

Enable

Disable

4.17.2 Customer ID Register

Word 1

Bit 12~Bit 0

XXXXXXXXXXXXX

Word 2

Bit 12~Bit 0

XXXXXXXXXXXXX

Bits 12 ~ 0: Customer’s ID code

4.18 Power-on Considerations

Any microcontroller is not guaranteed to start and operate properly before the power

supply maintains at its steady state. The EM78P809N has a built-in Power On Voltage

Detector (POVD) with a detecting level of 2.1V. It will work well if VDD rises fast enough

(10 ms or less). In many critical applications, however, additional components are

required to provide solutions on probable power-up problems.

4.18.1 External Power-on Reset Circuit

The circuit shown in Fig. 34 use an external RC to produce the reset pulse. The pulse

width (time constant) should be kept long enough for VDD to reach minimum operation

voltage. This circuit is used when the power supply has slow rise time. Because the

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8-Bit Microcontroller

current leakage from the /RESET pin is about 5μA, it is recommended that R should

not be greater than 40K. In this way, the /RESET pin voltage is held below 0.2V. The

diode (D) acts as a short circuit at the moment of power down. The capacitor C will

discharge rapidly and fully. Rin, the current-limited resistor, will prevent high current or

ESD (electrostatic discharge) from flowing to pin /RESET.

Vdd

/RESET

EM78P809N

Rin

Fig. 35. External Power-Up Reset Circuit

4.18.2 Residue-Voltage Protection

When battery is replaced, device power (VDD) is taken off but residue-voltage remains.

The residue-voltage may trip below VDD minimum, but not to zero. This condition may

cause a poor power-on reset. Fig.35 and Fig.36 show how to build the residue-voltage

protection circuit.

Vdd

33K

EM78P809N

10K

/RESET

40K

1N4684

Fig. 36. Residue Voltage Protection Circuit 1

60 •

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8-Bit Microcontroller

Vdd

EM78P809N

/RESET

40K

Fig 37. Residue Voltage Protection Circuit 2

4.19 Instruction Set

Each instruction in the instruction set is a 13-bit word divided into an OP code and one

or more operands. Normally, all instructions are executed within one single instruction

cycle (one instruction consists of 2 oscillator periods), unless the program counter is

changed by instruction "MOV R2,A", "ADD R2,A", or by instructions of arithmetic or

logic operation on R2 (e.g. "SUB R2,A", "BS(C) R2,6", "CLR R2", ⋅⋅⋅⋅). In this case, the

execution takes two instruction cycles.

In case the instruction cycle specification is not suitable for certain applications, try to

modify the instruction as follows:

(A) Change one instruction cycle to consist of 4 oscillator periods.

(B) The following commands are executed within two instruction cycles; "JMP",

"CALL", "RET", "RETL", "RETI", including the conditional skip ("JBS", "JBC", "JZ",

"JZA", "DJZ", "DJZA") instructions. In addition, instructions that are written to the

program counter are executed within two instruction cycles.

Case (A) is selected by the CODE Option bit, called CLK. One instruction cycle

consists of two oscillator clocks if CLK is low, and four oscillator clocks if CLK is high.

Note that once the 4 oscillator periods within one instruction cycle is selected as in

Case (A), the internal clock source to TCC should be CLK=Fosc/4, not Fosc/2.

Furthermore, the instruction set has the following features:

(1) Every bit of any register can be set, cleared, or tested directly.

(2) The I/O register can be regarded as general register. That is, the same instruction

can operate on I/O register.

The symbol "R" represents a register designator that specifies which one of the

registers (including operational registers and general purpose registers) is to be utilized

by the instruction. "b" represents a bit field designator that selects the value for the bit

which is located in the register "R", and affects the operation. "k" represents an 8 or

10-bit constant or literal value.

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8-Bit Microcontroller

Binary Instruction

Hex

Mnemonic

NOP

Operation

Status Affected

0000 0000 0000

0000 0000 0001

0000 0000 0010

0000 0000 0011

0000 0000 0100

0000

0001

0002

0003

0004

000r

0010

0011

0012

No Operation

Decimal Adjust A

A → CONT

None

T,P

DAA

CONTW

SLEP

WDTC

IOW

0 → WDT, Stop oscillator

0 → WDT

0000 0000

rrrr

A → IOCR

None <Note1>

None

0000 0001 0000

0000 0001 0001

0000 0001 0010

ENI

DISI

RET

Enable Interrupt

Disable Interrupt

[Top of Stack] → PC

[Top of Stack] → PC,

Enable Interrupt

CONT → A

None

0000 0001 0011

0000 0001 0100

0000 0001

0000 01rr

0013

RETI

None

0014

001r

00rr

0080

00rr

01rr

02rr

03rr

04rr

05rr

CONTR

IOR

None

None <Note1>

rrrr

IOCR → A

MOV

CLRA

CLR

SUB

DECA

DEC

A → R

None

Z,C,DC

0000 1000 0000

0 → A

0000 11rr

0001 00rr

0001 01rr

0001 10rr

0001 11rr

0010 00rr

0010 01rr

0010 10rr

0010 11rr

0011 00rr

0011 01rr

0011 10rr

0011 11rr

0100 00rr

0100 01rr

0100 10rr

0100 11rr

0101 00rr

0101 01rr

0101 10rr

0101 11rr

rrrr

0 → R

R-A → A

R-A → R

R-1 → A

R-1 → R

A ∨ R → A

A ∨ R → R

A & R → A

A & R → R

A ⊕ R → A

AND

XOR

ADD

MOV

COMA

COM

INCA

INC

A ⊕ R → R

A + R → A

Z,C,DC

A + R → R

R → A

R → R

/R → A

/R → R

R+1 → A

R+1 → R

None

DJZA

DJZ

R-1 → A, skip if zero

R-1 → R, skip if zero

R(n) → A(n-1),

R(0) → C, C → A(7)

R(n) → R(n-1),

R(0) → C, C → R(7)

R(n) → A(n+1),

R(7) → C, C → A(0)

R(n) → R(n+1),

R(7) → (C), C → (R(0)

R(0-3) → ( A(4-7),

R(4-7) → ( A(0-3)

R(0-3) → ( R(4-7)

R+1 → A, skip if zero

R+1 → R, skip if zero

0→ ( R(b)

0110 00rr

0110 01rr

0110 10rr

0110 11rr

0111 00rr

rrrr

06rr

07rr

RRCA

RRC

RLCA

RLC

SWAPA

None

0111 01rr

0111 10rr

0111 11rr

100b bbrr

101b bbrr

110b bbrr

111b bbrr

rrrr

07rr

0xxx

SWAP

JZA

None

JBC

JBS

1→ ( R(b)

if R(b)=0, skip

if R(b)=1, skip

PC+1 → [SP],

(Page, k) → (PC)

00kk kkkk kkkk

01kk kkkk kkkk

1kkk

CALL

JMP

None

62 •

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Binary Instruction

Hex

Mnemonic

Operation

Status Affected

1000 kkkk kkkk

1001 kkkk kkkk

1010 kkkk kkkk

1011 kkkk kkkk

1100 kkkk kkkk

1101 kkkk kkkk

1111 kkkk kkkk

1110 1000 kkkk

1110 1001 kkkk

18kk

19kk

1Akk

1Bkk

1Ckk

1Dkk

1Fkk

1E8k

1E9k

MOV

AND

XOR

RETL

SUB

ADD

PAGE

BANK

None

k → A

A v k → A

A & k → A

A ⊕ k → A

None

Z,C,DC

None

k → A, [Top of Stack] → PC

k-A → A

k+A → A

K->R5(6:4)

K->R4(7:6)

None

Note1: This instruction is applicable to IOC6 ~ IOCA, IMR1, IMR2 only.

5 Absolute Maximum Ratings

5.1 Absolute Maximum Ratings

Items

Rating

Temperature under bias

Storage temperature

Input voltage

-40°C

-65°C

-0.3V

85°C

150°C

+6.0V

10MHz

Output voltage

Operating Frequency (2clk)

5.2 Recommended Operating Conditions

( Vss = 0V )

Symbol

Parameter

Condition

Fc = 10MHz

Fc = 4MHz

Min.

4.0

2.5

Typ. Max. Unit

VDD

Supply Voltage

5.5

Crystal: VDD 4.5 to 5.5V

Crystal: VDD 2.5 to 5.5V

Two cycles with two clocks

MHz

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6 Electrical Characteristics

6.1 DC Electrical Characteristics

(Ta= 25 °C, VDD= 5.0V 5%, VSS= 0V)

Symbol

Parameter

Condition

Min.

Typ.

Max.

Unit

XTAL: 4.5V to VDD

Two cycles with two clocks

MHz

kHz

ERC ERC: VDD = 5V

Input High Threshold Voltage

R: 5.1KΩ, C: 100 pF

630

900

1170

VIHRC

OSCI in RC mode

2.8

15.5

1.3

4.5

28.5

2.7

(Schmitt trigger )

IRC1 Sink current

Input Low Threshold Voltage

VI from low to high , VI=5V

OSCI in RC mode

1.8

VILRC

(Schmitt trigger )

IRC2 Sink current

VI from high to low , VI=2V

VIN = VDD, VSS

μA

Input Leakage Current for input

pins

IIL

-1

Input High Voltage (Schmitt

trigger)

VIH1

VIL1

Ports 6,7,8,9

0.7VDD

-0.3V

VDD +0.3V

0.3 VDD

Input Low Voltage (Schmitt

trigger)

Ports 6,7,8,9,

Input High Threshold Voltage

(Schmitt trigger)

VIHT1

VILT1

/RESET, TCC, INT

0.7 VDD

-0.3V

VDD +0.3V

0.3 VDD

Input Low Threshold Voltage

(Schmitt trigger)

VIHX1 Clock Input High Voltage

VILX1 Clock Input Low Voltage

OSCI in crystal mode

0.7VDD

-0.3V

VDD+0.3V

0.3VDD

Output High Voltage

IOH1

VOH = VDD-0.4V

VOL = VSS+0.4V

-3.5

-5

-6.5

(Ports 6, 7, 8, 9)

Output Low Voltage

(Port9)

IOL1

Output Low Voltage

IOL2

(Ports 6,Port7, Port8)

IPH Pull-high current

IPL Pull-Low current

Pull-high active, input pin at VSS

Pull-high active, input pin at VDD

-50

-75

-100

100

μA

Sleep mode

ISB1

WDT

All input and I/O

disabled

0.8

1.5

μA

Power down current

pins at VDD,

Sleep mode

ISB2

WDT

output pin floating

Power down current

enabled

Idle mode

ICC3 Operating supply current

at two clocks

1.1

3.0

1.5

3.5

VDD=5V, /RESET= 'High',

Fc=8MHz, CLKS="0", output pin

floating, WDT enabled

Normal mode

ICC4 Operating supply current

at two clocks

*The typical value is based on characterization results at 25°C

64 •

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(Ta= 25 °C, VDD= 3.0V 5%, VSS= 0V)

Symbol

Parameter

Condition

Min.

Typ.

Max.

Unit

XTAL: 2.5V to VDD

ERC: VDD = 3V

Two cyclea with two clocks

MHz

kHz

ERC

R: 5.1KΩ, C: 100 pF

600

850

2.3

9.5

1100

Input High Threshold

Voltage (Schmitt trigger)

Sink current

VIHRC

IRC1

VILRC

IRC2

IIL

OSCI in RC mode

VI from low to high , VI=5V

OSCI in RC mode

1.6

2.8

1.3

Input Low Threshold

Voltage (Schmitt trigger)

Sink current

0.7

VI from high to low , VI=2V

VIN = VDD, VSS

8.5

μA

Input Leakage Current for

input pins

-1

Input High Voltage

(Schmitt trigger)

VIH1

VIL1

Ports 6,7,8,9,A

/RESET, TCC

0.7VDD

-0.3V

VDD+0.3V

0.3VDD

Input Low Voltage

(Schmitt trigger)

Input High Threshold

Voltage (Schmitt trigger)

Input Low Threshold

Voltage (Schmitt trigger)

Clock Input High Voltage

Clock Input Low Voltage

Output High Voltage

(Ports 6, 7, 8, 9)

VIHT2

VILT2

0.7 VDD

-0.3V

VDD +0.3V

0.3 VDD

VIHX1

VILX1

LOSCI,OSCI in crystal mode

0.7 VDD

-0.3V

VDD +0.3V

0.3 VDD

IOH1

IOL1

IOL2

VOH = VDD-0.4V

VOL = VSS+0.4V

-2

-3.5

3.5

-5

Output Low Voltage

(Ports9)

Output Low Voltage

(Ports 6,Port7, Port8)

Pull-high current

IPH

IPL

Pull-high active, input pin at VSS

Pull-low active, input pin at VDD

-15

-23

-31

Pull-low current

Sleep mode

Power down current

Sleep mode

Power down current

Idle mode

ISB1

ISB2

All input and I/O WDT disabled

pins at VDD,

0.4

1.5

0.8

μA

output pin floating

WDT enabled

ICC3

ICC4

Operating supply current

at two clocks

0.3

1.1

0.5

1.5

VDD=3V, /RESET= 'High',

Fc=4MHz, CLKS="0", output pin

floating, WDT enabled

Normal mode

Operating supply current at

two clocks

*The typical value is based on characterization results at 25°C

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A/D Converter Characteristic (VDD =2.5V to 5.5V, Vss=0V, Ta = -40 to 85℃)

Symbol

VAREF

VASS

VAI

Parameter

Condition

Min.

Typ.

Max.

VDD

Unit

2.5

Analog reference voltage VAREF - VASS≧2.5V

Vss

VASS

750

-10

500

200

Vss

Analog input voltage

VAREF

1000

+10

IVDD

850

Bits

LSB

VDD =VAREF=5.0V, VASS =0.0V

IAI1

IAI2

Analog supply current

(V reference from VDD)

Ivref

IVDD

IVref

600

250

820

VDD =VAREF=5.0V, VASS =0.0V

(V reference from VREF)

300

Resolution

VDD =VAREF=5.0V, VASS =0.0V

Linearity error

VDD = 2.5 to 5.5V Ta=25℃

±1

±2

Differential nonlinear

error

DNL

VDD = 2.5 to 5.5V Ta=25℃

±0.5

±0.9

LSB

FSE

Full scale error

Offset error

VDD =VAREF=5.0V, VASS =0.0V

±0

±1

±2

±1

LSB

±0.5

Recommended

ZAI

impedance of analog

voltage source

KΩ

TAD

TCN

ADIV

A/D clock period

VDD =VAREF=5.0V, VASS =0.0V

TAD

A/D conversion time

VAREF

0.3

A/D input voltage range VDD =VAREF=5.0V, VASS =0.0V

0.2

4.8

VDD =VAREF=5.0V, VASS =0.0V,

RL=10KΩ

ADOV

PSR

A/D output voltage swing

4.7

±0

Power Supply Rejection VDD =5.0V±0.5V

±2

LSB

66 •

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EM78P809N

8-Bit Microcontroller

6.2 AC Electrical Characteristic

(Ta=- 40°C ~ 85 °C, VDD=5V 5%, VSS=0V)

Symbol

Parameter

Conditions

Min

Typ Max Unit

50 55

Dclk

Input CLK duty cycle

Crystal type (high frequency)

RC type

200

500

DC ns

Instruction cycle time

(CLKS="0")

Tins

Ttcc

(Tins+20)/

TCC input period

Device reset hold

time

Tdrh

Trst

Ta = 25°C

11.3

2000

11.3

16.2 21.6 ms

/RESET pulse width Ta = 25°C

Watchdog timer

Ta = 25°C

period

Twdt

16.2 21.6 ms

Tset

Input pin setup time

Thold Input pin hold time

Tdelay Output pin delay time Cload=20pF

Tstup1 SDI data setup time Setup time of SDI data input to SCK↑or SCK↓

25 50

Thold1 SDI data hold time

Hold time of SDI data input to SCK↓or SCK↑

Tvalid1 SDO output valid time SCK↑or SCK↓to SDO data output

Tsckh SCK input high time Slave mode (Fmain=8 MHz)

200

400

Tsckl SCK input low time

Slave mode (Fmain=8 MHz)

Tsetup2 Slave mode setup

time

/SS↓ to SCK↑or SCK↓(Fmain=8 MHz)

Tdelay1 Slave mode unselect

delay time

25 50

/SS↑ to SDO output hi-impedance delay time

* N= selected prescaler ratio

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EM78P809N

8-Bit Microcontroller

6.3 Timing Diagram

AC Test Input/Output Waveform

2.4

0.4

2.0

0.8

2.0

0.8

TEST POINTS

AC Testing : Input is driven at 2.4V for logic "1",and 0.4V for logic "0".Timing measurements are

made at 2.0V for logic "1",and 0.8V for logic "0".

RESET Timing (CLK="0")

Instruction 1

Executed

NOP

CLK

/RESET

Tdrh

TCC Input Timing (CLKS="0")

Tins

CLK

TCC

Ttcc

68 •

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EM78P809N

8-Bit Microcontroller

APPENDIX

Package Types:

OTP MCU

Package Type

DIP

Pin Count

Package Size

600 mil

EM78P809NP

EM78P809NM

EM78P809NS

SOP

300 mil

SSOP

209 mil

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EM78P809N

8-Bit Microcontroller

CONTENTS.............................................................................................................III

4.6 Time Base Timer and Keytone Generator············································································ 31

4.7 UART (Universal Asynchronous Receiver/Transmitter)······················································· 33

5 Absolute Maximum Ratings ············································································ 63

6 Electrical Characteristics················································································· 64

6.3

70 •

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8-Bit Microcontroller

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