LSI Specification
MB86617A
IEEE1394 Serial Bus Controller
for DTV
MB86617A
LSI Specification
Rev. 1.0 August 16, 2001
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LSI Specification
MB86617A
7.3. INSTRUCTION FETCH REGISTER
........................................................................................................................................................... 31
7.4. INTERRUPT-FACTOR INDICATE REGISTER/INTERRUPT-MASK SETTING REGISTER........................................................................ 32
7.5. RECEIVE ACKNOWLEDGE INDICATE REGISTER................................................................................................................................. 33
7.6. A-BUFFER DATA PORT RECEIVE /TRANSMIT ...................................................................................................................................... 34
7.7. TSP T RANSMIT INFORMATION SETTING REGISTER [A] ................................................................................................................... 35
7.8. TSP T RANSMIT INFORMATION SETTING REGISTER [B] ................................................................................................................... 37
7.9. T RANSMIT OFFSET SETTING REGISTER [A] ....................................................................................................................................... 39
7.10. TRANSMIT OFFSET SETTING REGISTER [B] ..................................................................................................................................... 40
7.11. TSP RECEIVE INFORMATION SETTING REGISTER........................................................................................................................... 41
7.12. RECEIVE DSS PACKET HEADER INDICATE REGISTER [A]/TRANSMIT DSS PACKET HEADER SETTING REGISTER [A] ....... 44
7.13. RECE IVE DSS PACKET HEADER INDICATE REGISTER [B]/T RANSMIT DSS PACKET HEADER SETTING REGISTER [B] ........ 45
7.14. TSP STATUS REGISTER....................................................................................................................................................................... 46
7.15. DATA BRIDGE TRANSMIT INFORMATION SETTING REGISTER 1 [A]............................................................................................. 48
7.16. DATA BRIDGE TRANSMIT INFORMATION SETTING REGISTER 2 [A]............................................................................................. 49
7.17. DATA BRIDGE TRANSMIT INFORMATION SETTING REGISTER 3 [B]............................................................................................. 50
ATA RIDGE RANSMIT NFORMATION ETTING EGISTER
7.18. D
B
T
I
S
R
4 [B]............................................................................................. 51
.......................................................................................................... 52
...................................................................................................................... 53
ATA RIDGE ECEIVE NFORMATION ETTING EGISTER
7.19. D
B
R
I
S
R
7.20. TRANSMIT PACKET LINK /SPLIT SETTING REGISTER
7.21. LATE PACKET DECISION RANGE SETTING REGISTER [A] .............................................................................................................. 55
7.22. LATE PACKET DECISION RANGE SETTING REGISTER [B] .............................................................................................................. 56
7.23. RECEIVE ISOCHRONOUS PACKET HEADER INDICATE REGISTER 1 [A] ........................................................................................ 57
7.24. RECEIVE ISOC HRONOUS PACKET HEADER INDICATE REGISTER 2 [A] ........................................................................................ 58
7.25. RECEIVE ISOCHRONOUS PACKET HEADER INDICATE REGISTER 3 [B]......................................................................................... 59
7.26. RECEIVE ISOCHRONOUS PACKET HEADER INDICATE REGISTER 4 [B]......................................................................................... 60
7.27. FIFO RESET SETTING REGISTER....................................................................................................................................................... 61
7.28. DATA BRIDGE TRANSMIT /RECEIVE STATUS REGISTER [A] ........................................................................................................... 62
7.29. DATA BRIDGE TRANSMIT /RECEIVE STATUS REGISTER [B] ........................................................................................................... 65
7.30. ISOCHRONOUS CHANNEL M ONITOR REGISTER ............................................................................................................................... 68
7.31. CYCLE-TIMER -MONITOR INDICATE REGISTER................................................................................................................................. 69
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LSI Specification
MB86617A
7.32. PING TIME MONITOR REGISTER
........................................................................................................................................................ 70
7.33. PHY/LINK REGISTER/ADDRESS SETTING REGISTER ................................................................................................................... 71
7.34. PHY/LINK REGISTER ACCESS PORT ............................................................................................................................................... 72
7.35. REVISION INDICATE REGISTER .......................................................................................................................................................... 73
7.36. TRANSMIT CGMS/TSCH INDICATE REGISTER [A] ....................................................................................................................... 74
7.37. TRANSMIT CGMS/TSCH INDICATE REGISTER [B]........................................................................................................................ 75
7.38. TRANSMIT CGMS/TSCH INDICATE STATUS REGISTER ................................................................................................................ 76
7.39. TRANSMIT EMI/OE SETTING REGISTER.......................................................................................................................................... 78
CHAPTER 8 PHY/INK REGISTER FUNCTION DESCRIPTION................................................................................................ 80
8.1. PHY/LINK REGISTER TABLE.............................................................................................................................................................. 81
8.2. PHYSICAL REGISTER #00 (READ)......................................................................................................................................................... 83
8.3. PHYSICAL REGISTER #01 (READ/WRITE) ............................................................................................................................................ 84
8.4. PHYSICAL REGISTER #02 (READ)......................................................................................................................................................... 85
8.5. PHYSICAL REGISTER #03 (READ)......................................................................................................................................................... 86
8.6. PHYSICAL REGISTER #04 (READ/WRITE) ............................................................................................................................................ 87
HYSICAL REGISTER
HYSICAL REGISTER
READ WRITE
) ............................................................................................................................................ 88
8.7. P
8.8. P
#05 (
/
READ
#07, 08, 09 (
) ........................................................................................................................................... 90
8.9. PHYSICAL REGISTER #0A, 0B, 0C (READ/WRITE)
............................................................................................................................ 91
8.10. PHYSICAL REGISTER #0D, 0E, 0F (READ/WRITE) ........................................................................................................................... 92
8.11. PHYSICAL REGISTER #10 (READ)....................................................................................................................................................... 93
8.12. PHYSICAL REGISTER #11, 12, 13 (READ) ......................................................................................................................................... 94
8.13. PHYSICAL REGISTER #14, 15, 16 (READ) ......................................................................................................................................... 95
8.14. PHYSICAL REGISTER #17, 18, 19, 1A, 1B, 1C, 1D, 1E (READ/WRITE) ....................................................................................... 96
8.15. LINK REGISTER #00 (READ/WRITE)................................................................................................................................................... 97
8.16. LINK REGISTER #01 (READ/WRITE)................................................................................................................................................... 98
8.17. LINK REGISTER #02 (READ/WRITE)................................................................................................................................................... 99
8.18. LINK REGISTER #03 (READ/WRITE)................................................................................................................................................. 100
CHAPTER 9 INSTRUCTIO N ................................................................................................................................................................ 101
9.1. INSTRUCTION C ODE TABLE..............................................................................................................................................................102
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MB86617A
9.2. DESCRIPTION OF EACH INSTRUCTION
............................................................................................................................................... 103
CHAPTER 10 INTERRUPT
..................................................................................................................................................................... 106
10.1. INTERRUPT-FACTOR INDICATOR REGISTER & INTERRUPT-MASK SETTING REGISTER.............................................................107
10.2. INTERRUPT.......................................................................................................................................................................................... 108
10.3. DESCRIPTION OF INTERRUPT............................................................................................................................................................ 109
CHAPTER 11 OPERATION ...................................................................................................................................................................112
11.1. INITIALIZATION ................................................................................................................................................................................ 113
11.2. SELF -ID PACKET RECEIVING .........................................................................................................................................................114
11.2.1
11.2.2
Self -ID Packet Receive at Bus Reset Process .............................................................................................................115
Self-ID Packet Receive after Transmitting Ping Packet Ping................................................................................ 118
11.3. ASYNCHRONOUS PACKET TRANSMITTING................................................................................................................................. 120
11.4. ASYNCHRONOUS PACKET RECEIVING .........................................................................................................................................122
11.5. ISOCHRONOUS PACKET TRANSMITTING ..................................................................................................................................... 125
11.6. ISOCHRONOUS PACKET RECEIVING .............................................................................................................................................128
CHAPTER 12 SYSTEM CO NFIGURATION ...................................................................................................................................130
12.1. RECOMMENDED CONNECTION FOR 1934 PORT (FOR ONE PORT) .......................................................................................... 131
12.2. RECOMMENDED CONNECTION FOR CABLE POWER SUPPLY ..................................................................................................132
12.3. RECOMMENDED CONNECTION FOR BUILD-IN PLL LOOP FILTER.........................................................................................133
ONFIGURATION OF EEDBACK IRCUIT AT RYSTAL SCILLATOR
12.4. C
F
C
C
O
...................................................................................134
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LSI Specification
MB86617A
Chapter 1 Overview
This chapter explains the overview of MB86617A.
MB86617A is Fujitsu’s IEEE1394 serial bus controller based on both IEEE1394 Standard (IEEE Std. 1394-1995) and P1394.a
Standard Draft (rev.2.0).
This MB86617A has three ports for network under the 1394 cable environment, differential transceiver, and comparator, and the
transfer data rate supports S400.
MB86617A integrates PHY and LINK layers into single-chip, and plans for degression of component side product and saving power
consumption.
MB86617A has two exclusive ports (one is the combined use for receiving a message of interface for DV) for MPEG2 and DSS data
transfer, and performs isolating and packeting of Header and Data department with these two ports automatically. This function is
suited for maintaining continuum of transfer.
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LSI Specification
MB86617A
Chapter 2 Features
This chapter explains the features of MB86617A.
> Compliant with IEEE1394 high performance serial bus standard and P1394.a standard draft
> Integrates PHY and LINK layers into single-chip
> 1394 port number : 3 ports
> Transfer Data Rate: S100, S200, S400
> On-chip PLL (corresponding to Crystal Osci llator) : generate internal clock
> 4K Byte X 2 channels Isochronous transmit and receive data buffer
> 256Byte Asynchronous exclusive buffer for transmit/receive
> Auto isolating and packetingfor received header and data of packet
> Two exclusive ports for Isochronous transfer (8 bit bus)
> Loading interface with copy protection LSI (8 bits I/O)
> Generating and Checking Function for 32bit CRC
> 6-pin cable supported
> Power supply system : 3.3V size-D battery
> Package : LQFP -176 (FPT-176P-M03)
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LSI Specification
MB86617A
Chapter 3 Chip Block
This chapter explains the MB86617A block diagram and the function of each block.
3.1. Block Diagram
3.2. Function of Each Block
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MB86617A
3.1. Block Diagram
MB86617A block diagram is shown below.
<Normal Operation Mode
Asynch Transmit
Exclusive FIFO
(256 byte)
TPA0
XTPA0
TPB0
Asynch Transmit
Packet Process
XTPB0
TPBIAS0
Asynch Transmit
Packet Process
Asynch Transmit
Exclusive FIFO
(256 byte)
TPA1
XTPA1
TPB1
PHY/
LINK
Layer
Control
Circuit
FIFO
FIFO
(2KByte)
(2KByte)
XTPB1
TPBIAS1
TPA2
XTPA2
TPB2
XTPB2
TPBIAS2
FIFO
FIFO
CP IC
(2KByte)
(2KByte)
Interface
Fig.3.1.1 Block Diagram - Normal Operation Mode -
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MB86617A
<Asynchronous Transmit FIFO Extended Mode
Asynch Transmit
Exclusive FIFO
TPA0
XTPA0
TPB0
(256 byte)
Asynch Transmit
PacketProcess
XTPB0
TPBIAS0
Asynch Transmit
PacketProcess
Asynch Transmit
Exclusive FIFO
(256 byte)
TPA1
XTPA1
TPB1
PHY/
LINK
Layer
Control
Circuit
FIFO
FIFO
(2KByte)
(2KByte)
XTPB1
TPBIAS1
TPA2
XTPA2
TPB2
XTPB2
TPBIAS2
FIFO
FIFO
CP IC
(2KByte)
(2KByte)
Interface
Fig.3.1.2 Block Diagram - Asynchronous Transmit FIFO Extended Mode-
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MB86617A
<Asynchronous Receive FIFO Extended Mode
Asynch Transmit
Exclusive FIFO
TPA0
XTPA0
TPB0
(256 byte)
Asynch Transmit
Packet Process
XTPB0
TPBIAS0
Asynch Transmit
Packet Process
Asynch Transmit
Exclusive FIFO
(256 byte)
TPA1
XTPA1
TPB1
PHY/
LINK
Layer
Control
Circuit
FIFO
FIFO
(2KByte)
(2KByte)
XTPB1
TPBIAS1
TPA2
XTPA2
TPB2
XTPB2
TPBIAS2
FIFO
FIFO
CP IC
(2KByte)
(2KByte)
Interface
Fig.3.1.3 Block Diagram - Asynchronous Receive FIFO Extended Mode -
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MB86617A
3.2. Function of Each Block
This section explains the function of each block for MB86617A.
<PHY Layer Control Circuit
This circuit is for the Physical layer of IEEE 1394with the following functions.
> Asynchronous transfer is supported under cable environment.
> Maximum transfer data rate : 393.216Mbit/sec.
> with three ports for transceiver/receiver : transfer IEEE1394 packet
> with bus monitor, initial performance for occurring bus reset, speed signaling, arbitration, encode/decode : transfer/receive data
<LINK Layer Control Circuit
This circuit generates standard packet for IEEE1394, controls transfer, and performs the following functions.
> Generates and checks 32 bit CRC for header and data of packet.
> Activates cycle master function with integrated 32 bit cycle timer register
<TSP IC Interface
This TSP IC Interface has two exclusive ports with the following functions for transmitting/receiving TSP IC, MPEG2-TS and DSS
data, and receiving DV data.
> Adds time stamp to both MPEG2 -TS and DSS data.
> Outputs received data just when the value of time stamp (SPH) and cycle timer is matched with each other.
> Integrated transmit/receive (dual purpose) FIFO for transferring Isochronous by 2K byte X 2 channels.
<CP IC Interface
This interface adds the copy information to CP IC so as to correspond to copy protect.
<Data Bridge
This Data Bridge packets MPEG2-TS, DSS, and DVC, and re-builds the receiving data.
At data transmission, this section adds Isochronous packet header and CIP header, and connects/ separates source packet
When transmitting 2ch, it connects Isochronous packet.
At data receipt, it deletes Isochronous packet header and CIP header, restores by unit of source packet.
When receiving 2ch, it separates Isochronous packet and divide them to each FIFO.
> Integrated transmit/receive (dual purpose) FIFO for transferring Isochronous by 2K byte X 2 channels.
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MB86617A
Chapter 4 Pin Assignment
This chapter explains the pin assignment and table of pin function of MB86617A.
4.1. Pin Assignment
4.2. Corresponding Table of MB86617A Pin
4.3. Outline Drawing of Package
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MB86617A
4.1. Pin Assignment
The following diagram shows the MB86617A pin assignment.
XRESET
MODE1
MODE0
XCS
1
5
132
130
SELIOA
IERRA
TSDA0
TSDA1
TSDA2
TSDA3
VSS
XWR(XDS)
XRD(R/XW)
ALE
XINT
DREQ
XDACK
VDD
125
120
115
110
105
100
95
VDD
TSDA4
TSDA5
TSDA6
TSDA7
TSVALA
TSCGMSA
TSSYNCA
TSCLKA
VSS
10
15
20
25
30
35
VSS
D15
D14
D13
D12
D11
D10
VDD
D9
D8
M B 8 6 6 1 7
VDD
VSS
AD7
F P T - 1 7 6 P - M 0 3
AD6
AD5
AD4
AD3
VSS
VDD
AD2
AD1
D0
TEST1
TEST2
VSS
XI
VDD
VSS
VDD
XO
AVSS
AVDD
FIL
RF
40
44
AVSS
AVDD
RO
90
89
CPS
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4.2. Corresponding Table of MB86617A Pin
The following table shows the corresponding items of MB86617A pin.
Pin
Pin
Pin
Pin
I/O
Pin Name
I/O
Pin Name
I/O
Pin Name
I/O
Pin Name
No.
No.
No.
No.
1
I
I
XRE SET
MODE1
MODE0
XCS
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
-
-
AVSS
AVDD
XTPB2
TPB2
89
90
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
O
I
SELTSPA
DSSCLKA
VDD
2
3
I
I/O
I/O
I/O
I/O
O
-
91
-
4
I
92
-
VSS
5
I
XWR(XDS)
XRD(R/XW)
ALE
XTPA2
TPA2
93
I/O
I
TSCLKB
TSSYNCB
TSCGMSB
TSVALB
TSDB7
TSDB6
TSDB5
TSDB4
VDD
6
I
94
7
I
TPBIAS2
AVDD
AVSS
95
I
8
O
XINT
DREQ
XDACK
VDD
VSS
96
-
-
VDD
VSS
I/O
I/O
I/O
I/O
I/O
-
9
O
-
97
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
I
-
AVSS
98
-
-
AVDD
XTPB1
TPB1
99
-
I/O
I/O
I/O
I/O
O
-
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
D15
D14
XTPA1
TPA1
-
VSS
D13
I/O
I/O
I/O
I/O
O
O
O
I
TSDB3
TSDB2
TSDB1
TSDB0
IERRB
SELIOB
SELTSPB
DSSCLKB
VDD
D12
TPBIAS1
AVDD
AVSS
D11
-
-
VDD
VSS
D10
-
D9
-
AVSS
D8
-
AVDD
XTPB0
TPB0
VDD
VSS
I/O
I/O
I/O
I/O
O
-
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
AD7
XTPA0
TPA0
-
AD6
-
VSS
AD5
TPBIAS0
AVDD
AVSS
I/O
I/O
O
O
I
TEST3
TEST4
XFP
AD4
AD3
-
-
VDD
VSS
AD2
-
VSS
-
XILWRE
XIV
AD1
-
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
TSCLKA
TSSYNCA
TSCGMSA
TSVALA
TSDA7
TSDA6
TSDA5
TSDA4
VDD
D0
I
PWR1
PWR2
PWR3
LINKON
PMODE
I
ICLK
TEST1
TEST2
VSS
I
-
VDD
I
-
VSS
O
I
I/O
I/O
I
TEST5
TEST6
A7
I
XI
-
VDD
XO
I/O
-
I
A6
AVSS
AVDD
FIL
I
A5
-
-
VSS
I
A4
O
I/O
I/O
I/O
TSDA3
TSDA2
TSDA1
I
A3
O
RF
I
A2
-
AVSS
-
-
VDD
VSS
I
A1
42
43
44
-
O
I
AVDD
RO
86
87
88
130
131
132
I/O
O
TSDA0
IERRA
174
175
176
I/O
TEST7
VDD
VSS
-
-
CPS
O
SELIOA
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LSI Specification
MB86617A
4.3. Outline Drawing of Package
This section shows the outline drawing of MB86617A package (LQFP -176).
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LSI Specification
MB86617A
Chapter 5 Pin Function
This chapter explains the MB86617A pin function.
5.1. IEEE1394 Interface
5.2. Isochronous (TSP-IC,DV-IC) Interface
5.4. MPU Interface
5.5. Other Pins
5.6. Power/GND Pin
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LSI Specification
MB86617A
5.1. IEEE1394 Interface
This section explains the pin function of IEEE1394 interface.
Signal Name
TPA0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
Function
I/O pin of TPA + (plus) signal on cable port 0
XTPA0
TPB0
I/O pin of TPA - (minus) signal on cable port 0
I/O pin of TPB + (plus) signal on cable port 0
XTPB0
TPA1
I/O pin of TPB - (minus) signal on cable port 0
I/O pin of TPA + (plus) signal on cable port 1
XTPA1
TPB1
I/O pin of TPA - (minus) signal on cable port 1
I/O pin of TPB + (plus) signal on cable port 1
XTPB1
TPA2
I/O pin of TPB - (minus) signal on cable port 1
I/O pin of TPA + (plus) signal on cable port 2
XTPA2
TPB2
I/O pin of TPA - (minus) signal on cable port 2
I/O pin of TPB + (plus) signal on cable port 2
XTPB2
TPBIAS0
TPBIAS1
TPBIAS2
I/O pin of TPB - (minus) signal on cable port 2
Output pin of reference voltage for common voltage on cable port 0
Output pin of reference voltage for common voltage on cable port 1
Output pin of reference voltage for common voltage on cable port 2
O
O
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MB86617A
5.2. Isochronous Interface
This section explains the pin function of Isochronous interface.
Signal Name
TSVALIDA
TSSYNCA
I/O
I/O
I/O
Function
I.O pin for indicating effective data period of TS packet (on port A)
‘H’ active signal
Input/Output pin for indicating leading data of TS packet (on port A)
‘H’ active signal
On transmitting: sync clock input pin for input data of TS packet
On receiving : sync clock output pin for output data of TS packet
(switchable either 6.144MHz or 3.072MHz)
TSCLKA
I/O
TSDA7 - 0
TSCGMSA
I/O
I
I/O pin for TS packet data (on Port A)
Serial input pin for CGMS and TSCH information (on port A)
Effective for 8 clocks since TSSYNCA input signal rising
Output pin for switching I/O on port A
Outputs ‘L’ at transmitting and ‘H’at receiving
SELIOA
SELTSPA
TSVALIDB
TSSYNCB
O
O
Output pin for switching output device from port A
I.O pin for indicating effective data period of TS packet (on port B)
‘H’ active signal
I/O
I/O
Input/Output pin for indicating leading data of TS packet (on port B)
‘H’ active signal
On transmitting: sync clock input pin for input data of TS packet
On receiving : sync clock output pin for output data of TS packet
(switchable either 6.144MHz or 3.072MHz)
TSCLKB
I/O
TSDB7 - 0
TSCGMSB
I/O
I
I/O pin for TS packet data (on port B)
Serial input pin for CGMS and TSCH information (on port B)
Effective for 8 clocks since TSSYNCA input signal rising
Output pin for switching I/O on port B
Outputs ‘L’ at transmitting and ‘H’at receiving
SELIOB
O
O
SELTSPB
Output pin for switching output device from port B
Clock input pin from DV-IC
ICLK
I
Output pin for signal to be allowed accessing to Isochronous-FIFO
Asserted by completing reception of data for one source packet
‘L’ active signal
XILWRE
O
Input signal for enable signal of Isochronous data
Output Isochronous-FIFO data to data output pin while this signal in active.
Switch data synchronizing with rise edge of ICLK
XIV
XFP
I
Output pin of time stamp trigger signal
‘L’ active signal
O
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MB86617A
Output pin for noticing error of receive data (on port A)
‘H’ active signal
IERRA
IERRB
O
O
Output pin for noticing error of receive data (on port B)
‘H’ active signal
Clock input pin for DSS data (27MHz)
Clock input pin for DSS data (27MHz)
DSSCLKA
DSSCLKB
I
I
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MB86617A
5.4. MPU Interface
This section explains the pin function of MPU interface.
Signal Name
A7 – 1
I/O
I
Function
Address input pin for selecting internal register
Available only when selecting non-multi mode
When selecting multiplex mode, set this signal in fixed ‘L’
D15 - 8,0
AD7 – 1
Data I/O pin
I/O
Corresponding to address input signal when selecting multiplex mode
XCS
I
I
Chip enable input pin for this device
80 system mode: read out strobe input pin for this device
68 system mode: input pin for controlling read out/write for this device
XRD(R/W)
80 system mode: strobe input pin for writing into this device
68 system mode: input pin of XDS signal to be output with data bus in available
XWR(XDS)
ALE
I
I
Input pin of ALE signal to be output with its address in available when selecting
multiplex mode
When selecting non-multiplex mode, set this signal in fixed ‘L’
DREQ
XDACK
XINT
O
I
Output pin of DMA transfer requiring signal for DMAC
Input pin of DMA allowance signal from DMAC
Output pin for interruption request
O
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LSI Specification
MB86617A
5.5. Other Pins
This section explains the pin function like internal PLL.
Signal Name
XRESET
I/O
I
Function
Input signal for resetting signal
When operating with cable supply power, set this pin to ‘L’.
This pin is used for setting operating mode of MPU.
MODE1
MODE0
This device is operated as follows depending on the setting of MODE1 and MODE0
pins;
I
‘00’ input: TX1940 mode
‘01’ input: MB90F574 mode
‘10’ input: 80 system non-multiplex mode
‘11’ input: 68 system non-multiplex mode
XO
XI
I/O
I
Exterior type crystal connecting pin for oscillator circuit (24.576MHz)
RF
FIL
RO
O
O
O
Connect t o GND through 5.1kW register.
Exterior type filter circuit connecting pin for internal PLL
Connect to GND through 5.1kW register.
Power supply input pin from IEEE1394 cable
Detect cable supply power 0 to 33V (requiring of lowering/dividing voltage)
CPS
I
I
Criterion pin for inputting power
PMODE
‘L’ input : operate with power supplying through IEEE1394 cable
‘H’ input: operate with system power
Setting pin got POWER_CLASS of Self-ID packet to be transmitted when operating
with supply power through cable.
PWR3 - 1
I
Note) The POWER_CLASS of the Self_ID packet to be sent when operating
under the system power does not use this pin, but follows the setting of
Pwr bit (Bit2 to 0) of Physical Register#4.
Output pin for detecting Link-on packet receive
Output ‘H’ when receiving Link-on packet under operating with supply power
through IEEE1394 cable. When PMODE becomes ‘H’, ‘L’ is output. With the
LINKON
O
PMODE in ‘H’, the output of this pin is not changed.
If not using this pin, set this pin as open one.
TEST1 - 7
I/O
This pin is for test. Use this pin as open one.
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MB86617A
5.6. Power/GND Pin
This section explains the power/GND pin.
Signal Name
VDD
I/O
Function
-
-
-
-
3.3V digital power pin
Digital ground pin
VSS
AVDD
AVSS
3.3V analog power pin
Analog ground pin
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MB86617A
Chapter 6 Internal Register
This chapter explains the MB86617A internal register.
Note that the access of internal register is applied only 16 bits access.
WRITE
Address
READ
(HEX)
Register Name
Register Name
00
02
04
06
08
0A
0C
0E
10
12
14
16
18
1A
1C
1E
mode-control
(reserved)
mode-control
flag & status
Instruction-fetch
Instruction-fetch
Interrupt indicate [A]
Interrupt-mask setting [A]
Interrupt-mask setting [B]
(reserved)
Interrupt indicate [B]
Receive Acknowledge
A-buffer data port transmit
(reserved)
A-buffer data port receive
(reserved)
TSP transmit information setting [A]
TSP transmit information setting [B]
transmit offset setting [A] (upper)
transmit offset setting [A] (lower)
transmit offset setting [B] (upper)
transmit offset setting [B] (lower)
TSP receive information setting
TSP transmit information setting [A]
TSP transmit information setting [B]
transmit offset setting [A] (upper)
transmit offset setting [A] (lower)
transmit offset setting [B] (upper)
transmit offset setting [B] (lower)
TSP receive information setting
transmit DSS packet header setting [A]
(most significant)
receive DSS packet header setting [A]
(most significant)
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MB86617A
WRITE
READ
Address
(HEX)
Register Name
Register Name
20
22
24
26
28
2A
2C
2E
30
32
34
36
38
3A
3C
3E
40
42
44
46
48
4A
4C
4E
transmit DSS packet header setting [A] (upper)
transmit DSS packet header setting [A] (medium)
transmit DSS packet header setting [A] (lower)
receive DSS packet header setting [A] (upper)
receive DSS packet header setting [A] (medium)
receive DSS packet header setting [A] (lower)
transmit DSS packet header setting [A]
(least significant)
receive DSS packet header setting [A]
(least significant)
transmit DSS packet header setting [B]
(most significant)
receive DSS packet header setting [B]
(most significant)
transmit DSS packet header setting [B] (upper)
transmit DSS packet header setting [B] (medium)
transmit DSS packet header setting [B] (lower)
receive DSS packet header setting [B] (upper)
receive DSS packet header setting [B] (medium)
receive DSS packet header setting [B] (lower)
transmit DSS packet header setting [B]
(least significant)
receive DSS packet header setting [B]
(least significant)
(reserved)
data bridge transmit information setting 1 [A]
data bridge transmit information setting 2 [A]
data bridge transmit information setting 3 [B]
data bridge transmit information setting 4 [B]
data bridge receive information setting
transmit packet concatenate/split setting
Late packet criterion range setting [A]
Late packet criterion range setting [B]
(reserved)
TSP status
data bridge transmit information setting 1 [A]
data bridge transmit information setting 2 [A]
data bridge transmit information setting 3 [B]
data bridge transmit information setting 4 [B]
data bridge receive information setting
transmit packet concatenate/split setting
Late packet criterion range setting [A]
Late packet criterion range setting [B]
receive Isochronous packet header indicate 1 [A]
receive Isochronous packet header indicate 2 [A]
receive Isochronous packet header indicate 3 [B]
receive Isochronous packet header indicate 4 [B]
FIFO reset
(reserved)
(reserved)
(reserved)
FIFO reset
(reserved)
data bridge transmit/receive status [A]
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MB86617A
WRITE
READ
Address
(HEX)
Register Name
Register Name
50
52
54
56
58
5A
5C
5E
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
data bridge transmit/receive status [B]
Isochronous channel monitor 1
Isochronous channel monitor 2
Isochronous channel monitor 3
Isochronous channel monitor 4
cycle-time-monitor (upper)
cycle-time-monitor (lower)
Ping time monitor
PHY/LINK register address setting
PHY/LINK register access port
Revision indicate register (upper)
Revision indicate register (lower)
(reserved)
60
62
64
66
68
6A
6C
6E
70
72
74
76
78
7A
7C
7E
PHY/LINK register address setting
PHY/LINK register access port
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
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MB86617A
WRITE
Register Name
(reserved)
READ
Address
(HEX)
Register Name
80
82
transmit CGMS/TSCH indicate [A]
(reserved)
transmit CGMS/TSCH indicate [B]
transmit CGMS/TSCH indicate status
transmit EMI/OE setting
(reserved)
84
86
transmit CGMS/TSCH indicate status
transmit EMI/OE setting
(reserved)
88
8A
8C
8E
90
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
92
(reserved)
(reserved)
94
(reserved)
(reserved)
96
(reserved)
(reserved)
98
(reserved)
(reserved)
9A
9C
9E
A0
A2
A4
A6
A8
AA
AC
AE
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
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MB86617A
WRITE
READ
Address
(HEX)
Register Name
Register Name
B0
B2
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
B4
B6
B8
BA
BC
BE
C0
C2
C4
C6
C8
CA
CC
CE
D0
D2
D4
D6
D8
DA
DC
DE
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MB86617A
WRITE
READ
Address
(HEX)
Register Name
Register Name
E0
E2
E4
E6
E8
EA
EC
EE
F0
F2
F4
F6
F8
FA
FC
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
FE
(reserved)
(reserved)
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LSI Specification
MB86617A
Chapter 7 Internal Register Function Description
This chapter explains the details of the internal register of MB86617A.
7.1. mode-control Register
7.2. flag & status Register
7.3. instruction fetch Register
7.4. interrupt-factor Indicate Register/interrupt-mask Setting Register
7.5. Receive Acknowledge Indicate Register
7.6. A-buffer Data Port Receive/Transmit
7.7. TSP Transmit Information Setting Register [A]
7.8. TSP Transmit Information Setting Register [B]
7.9. Transmit Offset Setting Register [A]
7.10. Transmit Offset Setting Register [B]
7.11. TSP Receive Information Setting Register
7.12. Transmit DSS Packet Header Setting Register [A]
7.13. Transmit DSS Packet Header Setting Register [B]
7.14. TSP Status Register
7.15. Data Bridge Transmit Information Setting Register 1 [A]
7.16. Data Bridge Transmit Information Setting Register 2 [A]
7.17. Data Bridge Transmit Information Setting Register 3 [B]
7.18. Data Bridge Transmit Information Setting Register 4 [B]
7.19. Data Bridge Receive Information Setting Register
7.20. Transmit Packet Link/Split Setting Register
7.21. Late Packet Decision Range Setting Register [A]
7.22. Late Packet Decision Range Setting Register [B]
7.23. Receive Isochronous Packet Header Indicate Register 1 [A]
7.24. Receive Isochronous Packet Header Indicate Register 2 [A]
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MB86617A
7.25. Receive Isochronous Packet Header Indicate Register 3 [B]
7.26. Receive Isochronous Packet Header Indicate Register 4 [B]
7.27. FIFO Reset Setting Register
7.28. Data Bridge Transmit/Receive Status Register [A]
7.29. Data Bridge Transmit/Receive Status Register [B]
7.30. Isochronous channel monitor Register
7.31. cycle-timer-monitor Indicate Register
7.32. Ping time monitor Register
7.33. PHY/LINK Register/Address Setting Register
7.34. PHY/LINK Register/Access Port
7.35. Revision Indicate Register
7.36. Transmit CGMS/TSCH Indicate Register [A]
7.37. Transmit CGMS/TSCH Indicate Register [B]
7.38. Transmit CGMS/TSCH Indicate Status Register
7.39. Transmit EMI/OE Setting Register
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7.1. M ode-control Register
Mode-control register is the register that performs the relative setting of various operation mode of this LSI.
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
AD
00h
R/W
R/W
CPS
soft
reset
Cp_
trhrou
gh
Iso-FI Asyn-
FO no FIFOs
clr
TSP
stand- stand-
by
CP
clk
off
s-ID
store
send/re
c
-
-
-
-
-
-
-
el
by
Initial Value
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘1’
‘0’
‘0’
‘0’
‘0’
‘1’
‘0’
‘1’
‘1’
‘1’
BIT
Bit Name
reserved
Action
Value
Function
Read
-
-
Always indicate ‘0’.
Always write in ‘0’.
15 - 12
Write
PHY/LINK is reset by writing ‘0’ after writing ‘1’ (not automatic clear)
Note:
1) Perform read modify write so as not to re-write other bit.
2) Write ‘0’ after 500 ns minimum passed after writing ‘1’.
Read/
Write
11
10
9
CPS soft reset
clk off
-
0
1
0
Not stop clock for providing to TSP I/F, CP I/F and data bridge.
Read/
Write
Stop clock for providing to TSP I/F, CP I/F and data bridge when PMODE input
terminal is in ‘H’.
Deletes Self-ID packet in spite of receiving it during bus reset.
s-ID store
Note 1)
Read/
Write
In case of receiving Self-ID packet during bus reset process, this bit stores 512 byte
at maximum accompanying with both Asynchronous receive FIFO and
Asynchronous transmit FIFO.
1
0
1
Enable CP -IC interface.(Needs external CP IC)
Read/
Write
8
7
Cp_through
Sync_in
Disable CP -IC interface. CP-IC interface i s internally by passed.
TSSYNCA and TSSYNCB signals are neccesary to detect the first byte of the input
data to TSP interface.
0
Read/
Write
TSSYNCA and TSSYNCB signals are not neccesary to detect the first byte of the
input data to TSP interface.
1
0
1
TSSYNCA and TSSYNCB signals are not asserted when the data is outputted from
TSP interface.
Read/
Write
6
5
Sync_out
reserved
TSSYNCA and TSSYNCB signals are asserted when the data is outputted from TSP
interface.
Read
0
0
0
1
Always indicate ‘0’.
Write
Always write in ‘0’.
Clears receive Isochronous-FIFO when bus reset occurred.
Does not clear Isochronous-FIFO when bus reset occurred.
Iso-FIFO
no clr
Read/
Write
4
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MB86617A
BIT
3
Bit Name
Action
value
0
Function
Uses 2K byte FIFO on LINK I/F side of bridge for Isochronous transmit/receive.
Uses 2K byte FIFO on LINK I/F side of bridge for Asynchronous transmit/receive.
Uses 2K byte FIFO for Asynchronous transmit with Asyn-FIFO sel (bit3) ‘1’.
Asyn-FIFO
sel
Read/
Write
1
0
Read/
Write
2
send/rec
1
0
1
Uses 2K byte FIFO for Asynchronous receive with Asyn-FIFO sel (bit3) ‘1’.
Activates TSP -IC I/F terminal output.
Read/
Write
1
0
TSP stand-by
CP stand-by
Disables TSP-IC I/F terminal output, and brings it in high impedance status.
0
0
Activates CP I/F terminal output.
Read/
Write
Disables CP I/F terminal output, and brings it in high impedance status.
Note 1) Refer to “Self-ID Packet Receive Operation” for the internal operation flow and read-out flow of with this bit set at ‘1’.
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MB86617A
7.2. flag & status Register
flag & status register indicates the status of this LSI and data access inquiries.
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
AD
02h
R/W
R
A-Tx- A-Rx-
buff buff
empty empty
IPC
busy
tran
ready
tran
busy
ISO
cycle
data
req
recv
busy
sleep
‘0’
cmstr
‘0’
INT
‘0’
-
-
-
-
-
Initial Value
‘0’
‘0’
‘0’
‘0’
‘1’
‘1’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
BIT
15
Bit Name
IPC busy
Action
Value
Function
0
1
Indicates that receipt of instruction is available.
Indicates that receipt of instruction is not available.
Read
Read
Indicates that bus reset or forced sleep is being executed, and transmit/receive of
packet is unavailable.
0
1
0
14
13
tran ready
Indicates that bus reset is completed and forced sleep is not being executed, and
transmit/receive of packet is available.
Indicates that packet transmit is not being executed or in the process of packet
receive addressed to this node.
tran busy
ISO cycle
Read
Indicates that packet transmit is being executed or in the process of packet receive
addressed to this node.
1
0
1
Indicates that Isochronous cycle is not being executed.
12
11
Read
Read
Indicates that Isochronous cycle is being executed by transmit or receive of cycle
start packet.
0
1
0
Indicates that Asynchronous transmit specific buffer is not empty.
Indicates that Asynchronous transmit specific buffer is empty.
Indicates that Asynchronous receive specific buffer is not empty.
A-Tx-buff
Empty
A-Rx-buff
Empty
10
Read
Read
1
0
Indicates that Asynchronous receive specific buffer is empty.
Always indicate ‘0’.
9 – 5
reserved
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MB86617A
BIT
4
Bit Name
sleep
Action
Read
Value
0
Function
Indicates that the device is not in forced sleep.
Indicates that the device is in forced sleep by accepting “Start sleep” (01h)
instruction.
1
0
1
Indicates that no data is stored in ASYNC receive specific buffer.
Indicates that data is stored in ASYNC receive specific buffer.
Indicates that packet receive is not in busy mode.
3
2
1
0
data req
Read
Read
Read
Read
0
1
0
recv busy
Note 2)
Indicates that packet receive is in busy mode due to receipt of Asynchronous
packet and self-ID packet.
Indicates that node is not the cycle master now.
cmstr
INT
1
Node is the cycle master now.
0
1
Interrupt indicate register does not have interrupt.
Interrupt indicate register has interrupt.
Note 1) IEEE1394 block is in internal reset status until integrated PLL is locked after turning the power ON. PHY layer and Link
layer do not operate during this period.
Note 2) In case that Asynchronous packet addressed to this node is received with this Bit indicate ‘1’, it transmits “ack busy X”.
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MB86617A
7.3. instruction-fetch Register
instruction-fetch register is the register that writes in instructions for this LSI, and consists of the instruction code and operand.
Refer to “Chapter 9 Instruction” for each instruction code and operand code.
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
AD
04h
R/W
R/W
Instruction code
“00 h”
operand
“00 h”
Initial Value
BIT
Bit Name
Action
Value
-
Function
instruction
code
Read/
Write
15 - 8
Specify each instruction code.
Read/
Write
Specify required operand for each instruction code.
Write ‘0’ into all bits for instructions without operand.
7 - 0
operand
-
Note) Before writing in instruction for this register, read out IPC busy Bit (bit15) of “7.2. flag & status Register”, and confirm that the
IPC busy value is ‘0’.
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7.4. interrupt-factor Indicate Register/interrupt-mask Setting Register
interrupt-factor indicate register is the register that indicates interrupt reported by this LSI.
Refer to “Chapter 10 Interrupt” for measure against and details of each Bit and interrupt factor.
interrupt-mask setting register is the register that controls mask of each interrupt factor generated by this LSI.
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
AD
06h
R/
R
Interrupt-factor
interrupt-mask
Interrupt-factor
interrupt-mask
W
R
08h
W
Initial Value
BIT
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
Bit Name
Action
Value
0
Function
Indicate that interrupt factors are not generated.
interrupt-facto
r
Read
Indicate that interrupt factors are generated.
1
0
After reading out this register, clear to ‘0’ automatically.
Do not mask interrupt factors.
15 - 0
interrupt-mask
Write
Mask interrupt factors.
1
Interrupt factors masked by setting of this register are neither stored in interrupt
indicate register nor assert INT signal.
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LSI Specification
MB86617A
7.5. Receive Acknowledge Indicate Register
Receive Acknowledge indicate register is the register that indicates received Acknowledge packet addressed to itself.
Read out this register after interrupt report of “Asynchronous packet send”.
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
AD
R/W
R
0Ah
-
-
-
-
-
-
-
-
Receive ack-code
“0 h”
Receive ack-parity
“0 h”
Initial Value
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
BIT
Bit Name
reserved
Action
Value
-
Function
15 - 8
Read
Read
Always indicate ‘0’.
Receive
Acknowledge-co
de
Indicate code of received Acknowledge packet addressed to it.
(MSB: bit7, LSB: bit5)
7 - 4
3 - 0
-
-
Receive
Acknowledge-par
ity
Indicate parity of received Acknowledge packet addressed to it.
(MSB: bit3, LSB: bit0)
Read
Note) In case of not receiving Acknowledge within specified time, this register indicates “00h ” and reports interrupt of “Acknowledge
missing”.
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LSI Specification
MB86617A
7.6. A-bufferData Port Receive/Transmit
This integrated register is the buffer access port for both ASYNC receive specific buffer and ASYNC transmit specific one.
Read data is able to be read out IEEE1394 packet data in the order received. (MSB: 1ST read)
Write data is transmitted as IEEE1394 packet data in the order written in. (MSB: 1ST write)
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
AD
0Ch
R/W
R
ASYNC Receive Specific Buffer Data
W
ASYNC Transmit Specific Buffer Data
Undefined
Initial Value
BIT
Bit Name
Action
Read
Value
Function
ASYNC Receive
Specific Buffer
Data
Read out port of Asynchronous receive specific buffer.
(MSB: bit15, LSB: bit0)
-
-
15 - 0
ASYNC Transmit
Specific Buffer
Data
Write in port of Asynchronous transmit specific buffer.
(MSB: bit15, LSB: bit0)
Write
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LSI Specification
MB86617A
7.7. TSP Transmit Information Setting Register [A]
TSP transmit information setting register [A] is the register that makes settings for transmit packet processed by bridge-Ach.
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
AD
10h
R/W
R/W
Tx
start
-A
Tx
end
-A
Tx
select
-A
Tx
form
-A
input
DSS
size-A
EMI
select
-A
27M
count mask-
-A
port
set TS-ID-A
“00 h”
set EMI-A
“00 b”
A
Initial Value
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
BIT
15
Bit Name
Action
Value
Function
Automatically clears when transmit process is started with bridge-Ach after setting
at ‘1’.
0
1
0
Read/
Write
Tx start-A
Tx end-A
Starts transmit processing with bridge-Ach.
Automatically clears when transmit process is stopped by bridge-Ach after setting
at ‘1’.
Read/
Write
14
13
1
0
1
Stops transmit process by bridge-Ach.
Outputs ‘L’ to SELTSPA output terminal.
Outputs ‘H’ to SELTSPA output terminal.
Read/
Write
Tx select-A
Read/
Write
Set TSCH classification ID to be stored at FIFO of bridge-Ach.
(MSB: bit12, LSB: bit7)
12 - 7
set TS-ID-A
Tx form-A
-
0
1
0
1
Processes transmit data as MPEG2-TS.
Processes transmit data as DSS packet.
Processes transmit DSS packet as 140 byte.
Processes transmit DSS packet as 130 byte.
Read/
Write
6
inputDSS
size-A
Read/
Write
5
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LSI Specification
MB86617A
BIT
Bit Name
Action
Value
0
Function
Selects CGMS information input from TSP -IC as EMI information to be output to
CP-IC.
Read/
Write
4
EMI select-A
Selects setting value of set EMI-A (bit3 to 2) as EMI information to be output to
CP-IC.
1
-
Set EMI information to be output to CP-IC.
Valid only when EMI select -A (bit4) is ‘1’.
(MSB: bit3, LSB: bit2)
Read/
Write
3 - 2
set EMI-A
Does not insert internal 27 MHz counter value to System clock count ran ge of DSS
packet header.
0
Read/
Write
1
27M count-A
Inserts internal 27 MHz counter value to System clock count range of DSS packet
header.
1
0
Does not mask port A input of TSP-IC interface.
Read in input data from port A at transmit.
Read/
Write
0
port mask -A
Masks port A input of TSP -IC interface.
Does not read in input data from port A at transmit.
1
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LSI Specification
MB86617A
7.8. TSP Transmit Information Setting Register [B]
TSP transmit information setting register [B] is the register that makes settings for transmit packet processed by bridge -Bch.
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
AD
12h
R/W
R/W
Tx
start
-B
Tx
end
-B
Tx
select
-B
Tx
form
-B
input
DSS
size-B
EMI
select
-B
27M
count mask-
-B
port
set TS-ID-B
“00 h”
set EMI-B
“00 b”
B
Initial Value
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
BIT
15
Bit Name
Action
Value
Function
Automatically clears when transmit process is started with bridge -Bch after setting
at ‘1’.
0
1
0
Read/
Write
Tx start-B
Tx end-B
Starts transmit process with bridge -Bch.
Automatically clears when transmit process is stopped by bridge-Bch after setting
at ‘1’.
Read/
Write
14
13
1
0
1
Stops transmit process by bridge-Bch.
Outputs ‘L’ to SELTSPB output terminal.
Outputs ‘H’ to SELTSPB output terminal.
Read/
Write
Tx select-B
Read/
Write
Set TSCH classification ID to be stored at FIFO of bridge-Bch.
(MSB: bit12, LSB: bit7)
12 - 7
set TS-ID-B
Tx form-B
-
0
1
0
1
Processes transmit data as MPEG2 -TS packet.
Processes transmit data as DSS packet.
Read/
Write
6
Processes transmit DSS packet as 140 byte.
Processes transmit DSS packet as 130 byte.
inputDSS
size-B
Read/
Write
5
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LSI Specification
MB86617A
BIT
Bit Name
Action
Value
0
Function
Selects CGMS information input from TSP -IC as EMI information to be output to
CP-IC.
Read/
Write
4
EMI select-B
Selects setting value of set EMI-A (bit3 to 2) as EMI information to be output to
CP-IC.
1
-
Set EMI information to be output to CP-IC.
Valid only when EMI select -A (bit4) is ‘1’.
(MSB: bit3, LSB: bit2)
Read/
Write
3 - 2
set EMI-B
Does not insert internal 27 MHz counter to System clock count range of DSS
packet header.
0
Read/
1
27M count-B
Write
1
0
Inserts internal 27 MHz counter to System clock count range of DSS packet header.
Does not mask port B input of TSP-IC interface.
Reads in input data from port A at transmit.
Read/
Write
0
port mask -B
Masks port B input of TSP-IC interface.
Does not read in input data from port A at transmit.
1
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LSI Specification
MB86617A
7.9. Transmit Offset Setting Register [A]
Transmit offset setting register [A] is the register that sets offset value added to cycle-time-monitor value. Its aim is to generate source
packet header (Time-stamp) added to transmit packet processed by bridge -Ach. (Max. 32 ms)
Time-stamp value is generated on the basis of cycle-time-monitor value at input of first byte of source packet from TSP -IC.
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
AD
R/W
14h
16h
R/W
R/W
reserved
transmit-offset-A (high)
transmit-offset-A (low)
“0000 h”
Initial Value
BIT
Bit Name
reserved
Action
Value
-
Function
Read
Always indicate ‘0’.
Always write in ‘0’.
15 - 4 (high)
Write
-
3 - 0 (high)
Set value to be added to cycle-count range of cycle-time-monitor.
15 - 12 (low)
Setting range is 0h to FFh. (unit=125mS).
transmit-offset
-A
Read/
Write
-
Set value to be added to cycle-offset range of cycle-time-monitor.
Setting range is 0h to C00h. (unit=1/24.576 MHz).
11 - 0
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LSI Specification
MB86617A
7.10. Transmit Offset Setting Register [B]
Transmit off set setting register [B] is the register that sets offset value added to cycle-time-monitor value Its aim is to generate source
packet header (Time-stamp) added to transmit packet processed by bridge -Bch. (Max. 32 ms)
Time-stamp value is generated on the basis of cycle-time-monitor value at input of first byte of source packet from TSP -IC.
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
AD
R/W
18h
R/W
R/W
reserved
transmit-offset-B (high)
1Ah
transmit-offset-B (low)
“0000 h”
Initial Value
BIT
Bit Name
reserved
Action
Value
-
Function
Read
Always indicate ‘0’.
Always write in ‘0’.
15 - 4 (high)
Write
-
3 - 0 (high)
Set value to be added to cycle-count range of cycle-time-monitor.
15 - 12 (low)
Setting range is 0h to FFh. (unit=125mS).
transmit-offset
-B
Read/
Write
-
Set value to be added to cycle-offset range of cycle-time-monitor.
Setting range is 0h to C00h. (unit=1/24.576MHz).
11 - 0
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LSI Specification
MB86617A
7.11. TSP Receive Information Setting Register
TSP receive information setting register performs the setting for outputting received packet to TSP -IC
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
AD
1Ch
R/W
R/W
output
DSS
size -B
output
DSS
size-A
DV-
EN
DSS-
EN
TS-E
N
TCL CMP
KSL
TSC
MP
TV2B TV1B
-
-
TV2A TV1A
-
-
SEL
Initial Value
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘1’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
BIT
15
Bit Name
TV2B
Action
Value
0
Function
Does not output packet received by bridge -Bch to port B of TSP -IC I/F.
Outputs packet received by bridge-Bch to port B of TSP -IC I/F.
Does not output packet received by bridge -Bch to port A of TSP -IC I/F.
Outputs packet received by bridge-Bch to port A of TSP-IC I/F.
Read/
Write
1
0
1
Read/
Write
14
TV1B
Read
-
-
Always indicates ‘0’.
Always write in ‘0’.
13 - 12
reserved
Write
Outputs DSS packet received by bridge -Bch, with DSS packet header attached, to
TSP -IC in unit of 140 byte.
0
output DSS
size-B
Read/
Write
Outputs DSS packet received by bridge-Bch, without attachment of DSS packet
header, to TSP-IC in unit of 130 byte.
Removed DSS packet header is stored at receive DSS packet header indicate
register [B].
11
1
Deletes received data and reports FMT error when DV data is received.
ISO packet header and CIP header are indicated in register.
0
1
Read/
Write
10
DV-EN
DSS-EN
Allows receiving DV data.
Deletes received data and reports FMT error when DSS data is received.
ISO packet header and CIP header are indicated in register.
0
1
Read/
Write
9
Allows receiving DSS data.
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LSI Specification
MB86617A
BIT
Bit Name
Action
Value
0
Function
Deletes received data and reports FMT error when MPEG2 -TS data is received.
ISO packet header and CIP header are indicated in register.
Read/
Write
8
TS-EN
1
0
1
0
1
Allows receiving MPEG2 -TS data.
Does not output the packet received by bridge-Ach to port B of TSP-IC I/F.
Outputs the packet received by bridge-Ach to port B of TSP -IC I/F.
Does not output the packet received by bridge-Ach to port A of TSP-IC I/F.
Outputs the packet received by bridge-Ach to port A of TSP -IC I/F.
Read/
Write
7
TV2A
Read/
Write
6
TV1A
Read
-
-
Always indicates ‘0’.
Always write in ‘0’.
5 - 4
reserved
Write
Outputs DSS packet with DSS packet header received by bridge-Bch to TSP-IC in
unit of 140 byte.
0
1
output DSS
size-
Read/
Write
3
Outputs DSS packet without DSS packet header received by bridge-Ach to TSP -IC
in unit of 130 byte.
Removed DSS packet header is stored at receive DSS packet header indicate register
[A].
0
1
0
1
0
1
Outputs received data to TSP -IC in synchronization with 6.144 MHz TSCLK.
Outputs received data to TSP -IC in synchronization with 3.072 MHz TSCLK.
Outputs to port A when TSCMP (bit0) is ‘1’.
Read/
Write
2
1
0
TCLKSL
CMPSEL
TSCMP
Read/
Write
Outputs to port B when TSCMP (bit0) is ‘1’.
Does not merge packet received by Ach and Bch.
Read/
Write
Outputs to one TSP-IC after merging packets received by Ach and Bch.
Note 1) Do not set TV2B (bit15), TV1B (bit14), and DV1B (bit12) to ‘1’ simultaneously.
Note 2) Do not set TV2A (bit7), TV1A (bit6), and DV1A (bit4) to‘1’ simultaneously.
Note 3) Do not set TV2B (bit15) and TV2A (bit7) to ‘1’ simultaneously.
Note 4) Do not set TV1B (bit14) and TV1A (bit6) to ‘1’ simultaneously.
Note 5) Do not set‘1’ to TV2B (bit15), TV1B (bit14), TV2A (bit7) and TV1A(bit6) when TSCMP (bit0) is set to ‘1’.
Note 6) FMT error is reported when receiving data format other than DV-EN (bit10), DSS-EN (bit9) and TS-EN (bit8) regardless of
their settings.
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LSI Specification
MB86617A
Register setting value and selection of output port are shown in the table below.
Bit 15
TV2B
Bit 14
TV1B
Bit 7
Bit 6
Bit 1
Bit 0
Receive
Status
TSP -IC I/F
Port A
TSP -IC I/F
Port B
CMP
SEL
TS
CMP
TV2A
TV1A
Processing-Ach
Receive data
0
0
0
1
1
0
0
0
1
0
0
1
0
1
0
0
0
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
-
Processing-Ach
Receive data
-
1ch receive
Processing-Bch
Receive data
-
Processing-Bch
Receive data
-
Processing-Ach
Receive data
Processing-Bch
Receive data
Processing-Bch
Receive data
Processing-Ach
Receive data
Processing-Ach+Bc
2ch receive
0
0
0
0
0
0
0
0
0
1
1
1
-
h
Receive data
Processing-Ach+Bc
-
h
Receive data
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LSI Specification
MB86617A
7.12. Receive DSS Packet Header Indicate Register [A]/Transmit DSS Packet Header
Setting Register [A]
Receive DSS packet header indicate register [A] indicates DSS packet header range of DSS packet received by bridge-Ach.
Transmit DSS packet header setting register [A] sets DSS packet header range of DSS packet received by bridge -Ach.
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
AD
1Eh
R/W
Rx-SI
F-A
R
W
R
Rx-System clock count-A(high)
Tx-System clock count-A(high)
Tx-SIF
-A
Rx-E
F-A
Rx-System clock count-A(low)
Tx-System clock count-A(low)
Reserved
reserved
20h
22h
24h
26h
Tx-E
F-A
W
R
reserved
reserved
reserved
reserved
reserved
reserved
“0000 h”
W
R
W
R
W
Initial Value
BIT
Bit Name
Rx-SIF-A
Tx-SIF-A
Active
Read
Value
Function
Indicates SIF range of received DSS packet header.
Write in SIF range of transmits DSS packet header.
-
-
-
-
15 (1Eh)
Write
Read
Rx-System
clock count-A
Indicate System clock count range of received DSS packet header.
(MSB: 1Eh-bit14 , LSB: 20h-bit8)
14 - 0 (1Eh)
15 - 8(20h)
Tx-System
clock count-A
Write in System clock count range of transmit DSS packet header.
(MSB: 1Eh-bit14 , LSB: 20h-bit8)
Write
Rx-EF-A
Tx-EF-A
Read
Write
Read
-
-
-
-
Indicates EF range of received DSS packet header.
Write in EF range of transmits DSS packet header.
Indicates reserved range of received DSS packet header.
Write in reserved range of transmit DSS packet header.
7(20h)
6 - 0(20h)
15 - 0(22h)
15 - 0(24h)
15 - 0(26h)
reserved
Write
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LSI Specification
MB86617A
7.13. Receive DSS Packet Header Indicate Register [B]/Transmit DSS Packet Header
Setting Register [B]
Receiv e DSS packet header indicate register [B] indicates DSS packet header range of DSS packet received by bridge-Bch.
Transmit DSS packet header setting register [B] sets DSS packet header range of DSS packet received by bridge-Bch.
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
AD
28h
R/W
Rx-SI
F-B
R
W
R
Rx-System clock count-B (high)
Tx-System clock count-B (high)
Tx-SIF
-B
Rx-E
F-B
Rx-maximum bit rate-B (low)
Tx-maximum bit rate-B (low)
reserved
reserved
2Ah
2Ch
2Eh
30h
Tx-E
F-B
W
R
reserved
reserved
reserved
reserved
reserved
reserved
“0000 h”
W
R
W
R
W
Initial Value
BIT
Bit Name
Rx-SIF-B
Tx-SIF-B
Action
Read
Value
Function
-
-
-
-
Indicates SIF range of receive DSS packet header.
Write in SIF range of transmit DSS packet header.
15 (28h)
Write
Read
Rx-System
clock count-B
Indicate System clock count range of receive DSS packet header.
(MSB: 28h-bit14, LSB: 2Ah-bit8)
14 - 0 (28h)
15 - 8(2Ah)
Tx-System
clock count-B
Write in System clock count range of transmit DSS packet header.
(MSB: 28h-bit14, LSB: 2Ah-bit8)
Write
Rx-EF-B
Tx-EF-B
Read
Write
Read
-
-
-
-
Indicates EF range of received DSS packet header.
Write in EF range of transmit DSS packet header.
Indicates reserved range of receive DSS packet header.
Write in reserved range of transmit DSS packet header.
7(2Ah)
6 - 0 (2Ah)
7 - 0 (2Ch)
15 - 0 (2Eh)
15 - 0 (30h)
reserved
Write
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LSI Specification
MB86617A
7.14. TSP Status Register
TSP status register indicates status of TSP -IC I/F.
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
AD
32h
R/W
R
TSP
FIFOf
ull-B
TSP
FIFO
emp-B
Tx-len
gth-err-
B
TSP
FIFO
full -A emp-A
TSP
Tx-len
CG
TS
no
CG
TS
no
-
-
-
-
FIFO gth-err-
chg-B chg-B 47h-B
chg-A chg-A 47h-A
A
Initial Value
BIT
‘0’
‘0’
‘0’
‘0’
‘1’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’ ‘1’
‘0’
‘0’
‘0’
Bit Name
Action
Value
0
Function
Indicates that CGMS information input from port B of TSP IC I/F is not changed.
15
14
13
CG chg-B
TS chg-B
no 47h-B
Read
Read
Read
Indicates that CGMS information corresponding to TSCH classification ID of same
type input from port B of TSP IC I/F is changed.
Clears to ‘0’ by lead of this register.
1
0
Indicates that TS classification ID input from port B of TSP IC I/F is not changed.
Indicates that TSCH classification ID input from port B of TSP IC I/F is not
consistent with TSCH classification ID (10h-bit12 to 7 set TS-ID-A or 12h-bit12 to
7 set TS-ID-B) to be stored to FIFO.
1
Clears to ‘0’ by lead of this register.
Indicates that synchronization byte of received MPEG2-TS input from CP-IC by
bridge-Bch is 47h
0
1
Indicates that synchronization byte of received MPEG2-TS input from CP-IC by
bridge-Bch is not 47h
Clears to ‘0’ by lead of this register.
0
1
0
1
0
Indicates that FIFO on TSP IC I/F side of bridge-Bch is not full.
Indicates that FIFO on TSP IC I/F side of bridge-Bch is full.
Indicates that FIFO on TSP IC I/F side of bridge-Bch is not empty.
Indicates that FIFO on TSP IC I/F side of bridge -Bch is empty.
Indicates that transmit data length input from TSP IC I/F is normal.
TSP FIFO
full-B
12
11
Read
Read
TSP FIFO
emp-B
Tx-length-err -
B
Indicates that transmit data length input from TSP IC I/F is not consistent with
specified format data length.
Deletes transmit data without writing into FIFO.
Clears to ‘0’ by lead of this register.
10
Read
1
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LSI Specification
MB86617A
BIT
9~8
Bit Name
reserved
Active
Read
Value
-
Function
Always indicate ‘0’.
0
1
0
Indicates that CGMS information input from port A of TSP IC I/F is not changed.
7
CG chg-A
Read
Indicates that CGMS information input from port A of TSP IC I/F is changed.
Clears to ‘0’ by lead of this register.
Indicates that TS classification ID input from port A of TSP IC I/F is not changed.
6
TS chg-A
Read
Indicates that TSCH classification ID input from port B of TSP IC I/F is not
consistent with TSCH classification ID (10h-bit12 to 7 set TS-ID-A or 12h-bit12 to
7 set TS-ID-B) to be stored to FIFO.
1
Clears to ‘0’ by lead of this register.
Indicates that synchronization byte of received MPEG2-TS input from CP-IC by
bridge-Bch is 47h
0
1
5
no 47h-A
Read
Indicates that synchronization byte of received MPEG2-TS input from CP-IC by
bridge-Bch is not 47h
Clears to ‘0’ by lead of this register.
0
1
0
1
0
Indicates that FIFO on TSP IC I/F side of bridge-Ach is not full.
Indicates that FIFO on TSP IC I/F side of bridge-Ach is full.
Indicates that FIFO on TSP IC I/F side of bridge-Ach is not empty.
Indicates that FIFO on TSP IC I/F side of bridge-Ach is empty.
Indicates transmit data length input from TSP IC I/F is normal.
TSP FIFO
full-A
4
3
Read
Read
TSP FIFO
emp-A
Tx-length-err -
A
Indicates transmit data length input from TSP IC I/F is not consistent with
specified format data length.
Deletes transmit data without writing into FIFO.
Clears to ‘0’ by lead of this register.
2
Read
Read
1
-
1 - 0
reserved
Always indicate ‘0’.
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LSI Specification
MB86617A
7.15. Data Bridge Transmit Information Setting Register 1 [A]
Data bridge transmit information setting register 1 [A] is the register that sets CIP header range added to transmit packet processed by
bridge-Ach.
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
AD
34h
R/W
R/W
Tx SID-A
“00 h”
Tx DBS-A
“00 h”
Tx FN-A
“00 b”
Initial Value
BIT
Bit Name
Tx SID-A
Action
Value
-
Function
Read/
Write
Writein SID range of transmit CIP header.
(MSB: bit15, LSB: bit10)
15 - 10
Writein DBS range of transmit CIP header.
(MSB: bit9, LSB: bit2)
MPEG2-TS at transmit: “00000110” b
Read/
Write
9 - 2
Tx DBS-A
Tx FN-A
-
-
DSS at transmit: “00001001” b
Write in FN range of transmit CIP header.
(MSB: bit1, LSB: bit0)
MPEG2-TS at transmit: “11” b
Read/
Write
1 - 0
DSS at transmit: “10” b
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LSI Specification
MB86617A
7.16. Data Bridge Transmit Information Setting Register 2 [A]
Data bridge transmit information setting register 2 [A] is the register that sets CIP header range, transmit channel, and speed added to
transmit packet processed by bridge-Ach.
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
AD
36h
R/W
R/W
Tx
TSF -
A
Tx FMT-A
“00” h
Tx channel-A
“00” h
Tx speed-A
“00” b
-
Initial Value
‘0’
‘0’
BIT
Bit Name
Action
Value
-
Function
Writein FMT range of transmit CIP header.
(MSB: bit15, LSB: bit10)
Read/
Write
15 - 10
Tx FMT -A
MPEG2-TS at transmit: “100000” b
DSS at transmit: “100001” b
Read/
Write
9
Tx TSF-A
-
-
Writein TSF range of transmitsCIP header.
Read/
Write
Write in channel range of transmit Isochronous packet header.
(MSB: bit8, LSB: bit 3)
8 - 3
Tx channel-A
Write in transmit packet speed.
(MSB: bit2, LSB: bit1)
s100 at transmit: “00” b
s200 at transmit: “01” b
s400 at transmit: “10” b
Read/
Write
2 - 1
Tx speed-A
reserved
-
Read
-
-
Always indicates ‘0’.
Always writes in ‘0’.
0
Write
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LSI Specification
MB86617A
7.17. Data Bridge Transmit Information Setting Register 3 [B]
Data bridge transmit information setting register 3 [B] is the register that sets CIP header range added to transmit packet processed by
bridge-Bch.
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
AD
38h
R/W
R/W
Tx SID-B
Tx DBS-B
“00 h”
Tx FN-B
“00 b”
Initial Value
“00 h”
BIT
Bit Name
Tx SID-B
Action
Value
-
Function
Read/
Write
Writein SID range of transmit CIP header.
(MSB: bit15, LSB: bit10)
15 - 10
Writein DBS range of transmit CIP header.
(MSB: bit9, LSB: bit2)
MPEG2-TS at transmit: “00000110” b
Read/
Write
9 - 2
Tx DBS-B
Tx FN-B
-
-
DSS at transmit: “00001001” b
Write in FN range of transmit CIP header.
(MSB: bit1, LSB: bit0)
MPEG2-TS at transmit: “11” b
Read/
Write
1 - 0
DSS at transmit: “10” b
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LSI Specification
MB86617A
7.18. Data Bridge Transmit Information Setting Register 4 [B]
Data bridge transmit information setting register 4 [B] is the register that sets CIP header range, transmit channel and speed added to transmit
packet processed by bridge-Bch.
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
AD
R/W
R/W
Tx
TSF -
B
3Ah
Tx FMT-B
“00” h
Tx channel-B
“00” h
Tx speed-B
“00” b
-
Initial Value
‘0’
‘0’
BIT
Bit Name
Action
Value
-
Function
Writein FMT range of transmit CIP header.
(MSB: bit15, LSB: bit10)
Read/
Write
15 - 10
Tx FMT -B
MPEG2-TS at transmit: “100000” b
DSS at transmit: “100001” b
Read/
Write
9
Tx TSF-B
-
-
Writein TSF range of transmit CIP header.
Read/
Write
Writein channel range of transmit Isochronous packet header.
(MSB: bit8, LSB: bit3)
8 - 3
Tx channel-B
Writein transmit packet speed.
(MSB: bit2, LSB: bit1)
s100 at transmit: “00” b
s200 at transmit: “01” b
s400 at transmit: “10” b
Read/
Write
2 - 1
Tx speed-B
reserved
-
Read
-
-
Always indicates ‘0’.
Always writes in ‘0’.
0
Write
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LSI Specification
MB86617A
7.19. Data Bridge Receive Information Setting Register
Data bridge receive information register performs the setting of receive packet.
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
AD
3Ch
R/W
R/
Rx
start
-B
Rx
end
-B
Rx
start
-A
Rx
end
-A
Rx channel-B
“00 h”
Rx channel-A
“00 h”
Initial Value
‘0’
‘0’
‘0’
‘0’
BIT
15
Bit Name
Action
Value
Function
Automatically clears when receive process is executed by bridge-Bch after setting
at ‘1’.
0
1
0
Read/
Write
Rx start-B
Rx end-B
Executes receive process by bridge -Bch.
Automatically clears when receive process is stopped by bridge -Bch after setting at
‘1’.
Read/
Write
14
13~8
7
1
-
Stops receive process by bridge -Bch.
Read/
Write
Write in Isochronous packet channel to be received by bridge-Bch.
(MSB: bit8, LSB: bit3)
Rx channel-B
Rx start-A
Automatically clears when receive process is executed by bridge-Ach after setting
at ‘1’.
0
1
0
1
Read/
Write
Starts receive process by bridge -Ach.
Automatically clears when receive process is stopped by bridge -Ach after setting at
‘1’.
Read/
Write
6
Rx end-A
Stops receive process by bridge -Ach.
Read/
Write
Write in Isochronous packet channel to be received by bridge-Ach
(MSB: bit5, LSB: bit0)
5 - 0
Rx-channel-A
-
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LSI Specification
MB86617A
7.20. Transmit Packet Link/Split Setting Register
Transmit packet link/split setting register is the register that sets number of link and split of source packets to be transmitted.
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
AD
3Eh
R/W
R/W
o/e
select-
B
o/e
select-
A
Tx
o/e-B
NF5
SPB
Tx
o/e-A
NF5
SPA
SPQB
DBQB
SPQA
DBQA
Initial Value
‘0’
‘0’
‘0’
“000 b”
“00 b”
‘0’
‘0’
‘0’
“000 b”
“00 b”
BIT
15
Bit Name
Action
Value
0
Function
Selects odd/even value to be input from CP-IC as odd/even range of Isochronous
packet header to be transmitted by bridge -Bch.
Read/
Write
o/e select-B
Selects Tx o/e-B (bit14) setting value as odd/even range of Isochronous packet
header to be transmitted by bridge -Bch
1
-
Write in odd/even range of transmit Isochronous packet header.
Valid with o/e select-B (bit15) setting value ‘1’, and reads in this setting value to
transmit Isochronous packet header.
Read/
Write
14
13
Tx o/e-B
NF5SPB
Executes 2SP combined transmission as FIFO NFULL operation when setting of
2SP separated transmission or combined transmission for less than 2SP.
With more than 3 SP, executes according to setting.
0
1
-
Read/
Write
Executes 5 SP combined transmission at FIFO FULL.
Read/
Write
12 - 10
9 - 8
SPQB
Write in number of link of source packet processed by bridge-Bch.
Read/
Write
DBQB
-
Write in number of split of source packet processed by bridge-Bch.
Selects odd/even value to be input from CP-IC as odd/even range of Isochronous
packet header to be transmitted by bridge -Bch.
0
1
Read/
Write
7
6
o/e select-A
Tx o/e-A
Selects Tx o/e-B b (bit6) setting value as odd/even range of Isochronous packet
header to be transmitted by bridge-Bch
Write in odd/even range of transmit Isochronous packet header.
Valid with o/e select-B (bit7) setting value ‘1’, and reads in this setting value to
transmit Isochronous packet header.
Read/
Write
-
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LSI Specification
MB86617A
BIT
5
Bit Name
NF5SPA
Action
Value
Function
Executes 2SP combined transmission as FIFO NFULL operation when setting of
2SP separated transmission or combined transmission for less than 2SP.
With more than 3 SP, executes according to setting.
0
1
Read/
Write
Executes 5 SP combined transmission at FIFO FULL.
Read/
Write
4 - 2
1 - 0
SPQA
-
-
Write in number of links for source packet processed by bridge-Ach.
Read/
Write
DBQA
Write in number of links for source packet processed by bridge-Ach.
Note)
>SPQ[2:0] -----Please specify link number of source packet.
Valid setting values are 0 - 5.
Processes assuming there are no settings from microcomputer during ‘0’ setting.
When 6 - 7 are set, it is regarded to be 5 source packet link.
>DBQ[1:0] ---- Please specify split number of source packet.
‘00’ ---No setting from microcomputer.
‘01’ ---2 splits
‘10’ ---4 splits
‘11’ ---8 splits, 4 splits at DSS
> When the setting values of both SPQ [2:0] and DBQ [1:0] are not ‘0’, follow the setting of SPQ [2:0].
When the setting values of both SPQ [2:0] and DBQ [1:0] are ‘0’ (no setting from microcomputer), LSI automatically executes link
process in 1 source packet unit.
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LSI Specification
MB86617A
7.21. Late Packet Decision Range Setting Register [A]
Late packet decision range setting register [A] is the register that sets Late decision range of source packet to be transmitted by bridge -Ach.
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
AD
40h
R/W
R/W
late range-A
“0000 h”
Initial Value
BIT
Bit Name
Action
Value
Function
Write in Late packetdecision range.
Setting range is 0h to FFh (unit: 125mS).
15 - 8
Read/
Write
late range-A
-
Write in Late packetdecision range.
Setting range is 0h to C0h (unit: 16/24.576MHz).
7 - 0
Note)
Late packet decision is performed by comparing the time difference between SPH (Source Packet Header) and CTR (Cycle Time Monitor).
-Transmit:
Packet is transmitted normally when calculation result of “SPH” minus “CTR” for source packet transmitted from Bridhe-Ach is within the
“late range-A + ‘0000’h”.
If it is out of range, Late packet process is performed. The packet concerned is deleted and transmit late is reported.
Set the upper 16 bit of the setting value for transmit offset setting register[A] (14h to 16h).
-Receive:
Received packet is output at the point of “SPH = CTR” when calculation result of “SPH” minus “CTR” for source packet received at
Bridhe -Ach is within the “late range-A + ‘0000’h” (the value this register is shifted 4 bits to the left).
If it is out of range, Late packet process is performed. The packet concerned is deleted and receive late is reported.
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LSI Specification
MB86617A
7.22. Late Packet Decision Range Setting Register [B]
Late packet decision range setting register [B] is the register that sets Late decision range of source packet to be transmitted by bridge -Bch.
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
AD
42h
R/W
R/W
late range-B
“0000 h”
Initial Value
BIT
Bit Name
Action
Value
Function
Write in Late packetdecision range.
Setting range is 0h to FFh (unit: 125mS).
15 - 8
Read/
Write
late range-B
-
Write in Late packetdecision range.
Setting range is 0h to C0h (unit: 16/24.576MHz).
7 - 0
Note)
Late packet decision is performed by comparing the time difference between SPH (Source Packet Header) and CTR (Cycle Time Monitor).
-Transmit:
Packet is transmitted normally when calculation result of “SPH” minus “CTR” for source packet transmitted from Bridhe-Bch is within the
“late range-B + ‘0000’h”.
If it is out of range, Late packet process is performed. The packet concerned is deleted and transmit late is reported.
Set the upper 16 bit of the setting value for transmit offset setting register[B] (14h to 16h).
-Receive:
Received packet is output at the point of “SPH = CTR” when calculation result of “SPH” minus “CTR” for source packet received at
Bridhe -Bch is within the “late range-B + ‘0000’h” (the value this register is shifted 4 bits to the left).
If it is out of range, Late packet process is performed. The packet concerned is deleted and receive late is reported.
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LSI Specification
MB86617A
7.23. Receive Isochronous Packet Header Indicate Register 1 [A]
Receive Isochronous packet header indicate register 1 [A] is the register that indicates Isochronous packet header information received by
bridge-Ach.
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
AD
44h
R/W
R
Rx
o/e-A
-
-
-
-
-
-
-
Rx EMI-A
“00 b”
Rx SID-A
“00 h”
Initial Value
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
BIT
Bit Name
reserved
Action
Value
-
Function
15 - 9
Read
Read
Read
Read
Always indicate‘0’.
Indicate EMI range of receive Isochronous packet header.
(MSB: bit8, LSB: bit7)
8 - 7
6
Rx EMI-A
Rx o/e-A
Rx SID-A
-
-
-
Indicates odd/even range of receive Isochronous packet header.
Indicate SI range of CIP header of receive Isochronous packet.
(MSB: bit8, LSB: bit3)
5 - 0
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LSI Specification
MB86617A
7.24. Receive Isochronous Packet Header Indicate Register 2 [A]
Receive Isochronous packet header indicate register 2 [A] is the register that indicates Isochronous packet CIP header information received
by bridge-Ach.
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
AD
46h
R/W
R
Rx
56-A
-
-
-
-
Rx FMT -A
“3F”
Rx STYPE-A
“00 h”
Initial Value
‘0’
‘0’
‘0’
‘0’
‘0’
BIT
Bit Name
reserved
Action
Value
-
Function
15 - 12
Read
Read
Always indicate‘0’.
Indicate FMT range of receive Isochronous packet CIP header.
(MSB: bit11, LSB: bit6)
11 - 6
Rx FMT -A
Rx 56-A
-
-
-
Indicates 50/60 range of receive Isochronous packet CIP header when receiving
DV.
5
Read
Read
Indicates TSF range of receive Isochronous packet CIP header when receiving
MPEG2-TS or DSS.
Indicate STYPE range of CIP header of receive Isochronous packet.
(MSB: bit4, LSB: bit0)
4 - 0
Rx STYPE-A
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LSI Specification
MB86617A
7.25. Receive Isochronous Packet Header Indicate Register 3 [B]
Receive Isochronous packet header indicate register 3 [B] is the register that indicates Isochronous packet header information received by
bridge-Bch.
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
AD
48h
R/W
R
Rx
o/e-B
-
-
-
-
-
-
Rx EMI-B
“00 b”
Rx SID-B
“00 h”
Initial Value
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
BIT
Bit Name
reserved
Action
Value
-
Function
15 - 9
Read
Read
Read
Read
Always indicate‘0’.
Indicate EMI range of receive Isochronous packet header.
(MSB: bit8, LSB: bit7)
8 - 7
6
Rx EMI-B
Rx o/e-B
Rx SID-B
-
-
-
Indicates odd/even range of receive Isochronous packet header.
Indicate SI range of CIP header of receive Isochronous packet.
(MSB: bit5, LSB: bit0)
5 - 0
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LSI Specification
MB86617A
7.26. Receive Isochronous Packet Header Indicate Register 4 [B]
Receive Isochronous packet header indicate register 4 [B] is the register that indicates Isochronous packet CIP header information received
by bridge-Bch.
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
AD
R/W
R
Rx
56-B
4Ah
-
-
-
-
Rx FMT -B
“3F”
Rx STYPE-B
“00 h”
Initial value
‘0’
‘0’
‘0’
‘0’
‘0’
BIT
Bit Name
reserved
Action
Value
-
Function
15 - 12
Read
Read
Always indicate‘0’.
Indicate FMT range of receive Isochronous packet CIP header.
(MSB: bit11, LSB: bit6)
11 - 6
Rx FMT -B
Rx 56-B
-
-
-
Indicates 50/60 range of receive Isochronous packet CIP header when receiving
DV.
5
Read
Read
Indicates TSF range of receive Isochronous packet CIP header when receiving
MPEG2-TS or DSS.
Indicate STYPE range of CIP header of receive Isochronous packet.
(MSB: bit4, LSB: bit0)
4 - 0
Rx STYPE-B
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LSI Specification
MB86617A
7.27. FIFO Reset Setting Register
FIFO reset setting register sets force reset of bridge and each FIFO.
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
AD
4Ch
R/W
R/W
resetT reset
SP BRG
FIFO- FIFO-
reset
TSP
FIFO- FIFO-
reset
BRG
reset-
A
reset-B
‘0’
-
-
-
-
-
-
-
-
-
-
B
B
A
A
Initial Value
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
BIT
15
Bit Name
reset-B
Action
Value
0
Function
Releases forced reset of bridge-Bch.
Executes forced reset of bridge-Bch.
Read/
Write
1
0
1
0
1
-
Releases FIFO reset on TSP -IC I/F side of bridge-Bch.
Resets FIFO on TSP-IC I/F side of bridge-Bch.
Releases FIFO reset on LINK-I/F side of bridge-Bch.
Resets FIFO on LINK I/F side of bridge-Bch.
Always indicate ‘0’.
reset TSP
FIFO-B
Read/
Write
14
13
resetBRG
FIFO-B
Read/
Write
Read
12 - 8
reserved
reset-A
Write
-
Always write in ‘0’.
0
Releases forced reset of bridge-Ach.
Read/
Write
7
1
0
Execute forced reset of bridge-Ach.
Releases FIFO reset on TSP -IC I/F side of bridge-Ach.
reset TSP
FIFO-A
Read/
Write
6
5
1
0
Resets FIFO on TSP-IC I/F of bridge-Ach.
Releases FIFO reset on LINK-I/F side of bridge-Ach.
resetBRG
FIFO-A
Read/
Write
1
-
Resets FIFO on LINK I/F side of bridge-Ach.
Always indicate ‘0’.
Read
4 - 0
Reserved
Write
-
Always write in ‘0’.
Note 1) This register is not cleared automatically.
After writing ‘1’, check the state and then write ‘0’.
Note 2) Do not set ‘1’ to this register during transmit/receive execution.
61
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LSI Specification
MB86617A
7.28. Data Bridge Transmit/Receive Status Register [A]
Data bridge transmit/receive status register indicates status of packet to be transmitted/received by bridge-Ach.
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
AD
4Eh
R/W
R
BRG
FIFO
emp-
A
Tx
busy -
A
Rx
Rx
Rx
Rx
dlen
err-A
Rx
stype
err-A
BRG
FIFO
full-A
Rx
DBC
Rx
CIP
Rx
FMT
Rx o/e
chg-A
Tx
Rx
Rx 56
-
busy - 1STP- EMI
A
late-A late-A err-A
A
chg-A
err-A err-A err-A
Initial Value
BIT
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘1’
‘0’ ‘0’ ‘0’
Bit Name
Tx busy-A
Action
Value
0
Function
Indicates that bridge-Ach is not in the process of transmit.
Indicates ‘0’ when Tx end-A (10h-bit14) is set at ‘1’ and transmit process is
stopped.
15
Read
Indicates that bridge-Ach is in the process of transmit.
1
0
Indicates ‘1’ when Tx start -A (10h-bit15) is set at ‘1’ and transmit process is
started.
Indicates that bridge-Ach is not in the process of receive.
Indicates ‘0’ when Rx end-A (3Ch -bit6) is set at ‘1’ and receive process is stopped.
14
Rx busy-A
Read
Indicates that bridge-Ach is in the process of receive.
Indicates ‘1’ when Rx start-A (3Ch -bit7) is set at ‘1’ and receive process is started.
1
0
1
0
1
0
1
Indicates that Isochronous packet received after starting receive process is not the
first packet received.
13
12
11
Rx 1STP-A
Read
Read
Read
Indicates that the first Isochronous packet is received after receive process is
started.
Clears to ‘0’ by lead of this register.
Indicates that EMI information of received Isochronous packet header is not
changed.
Rx EMI
chg-A
Indicates that EMI informatio n of received Isochronous packet header has changed
from just former EMI information of packet received by Isochronous-cycle.
Clears to ‘0’ by lead of this register.
Indicates that odd/even information of received Isochronous packet header is not
changed.
Rx o/e chg-A
Indicates that odd/even information of received Isochronous packet header has
changed from just former odd/even information of packet received by
Isochronous-cycle.
Clears to ‘0’ by lead of this register.
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LSI Specification
MB86617A
BIT
Bit Name
Action
Read
Value
0
Function
Indicates that the data length of received packet is same as specified data length in
format.
10
Rx dlen-err-A
Indicates that the data length of received packet differs to the specified data length
in the format.
1
Clears to ‘0’ by lead of this register.
9
8
reserved
Read
Read
-
Always indicates ‘0’.
0
Indicates that transmit packet is transmitted normally.
Tx late-A
Indicates that transmit packet became Late packet. Delete packet, and not
transmit.
Clears to ‘0’ by lead of this register.
1
0
1
Indicates that the received packet is normal.
7
6
5
Rx late-A
Read
Read
Read
Indicates that received packet was Late packet.
Delete packet, and not output to TSP-IC.
Clears to ‘0’ by lead of this register.
0
1
Indicates that 50/60 range of CIP header for received Isochronous packet is ‘0’.
Rx 56 err-A
Indicates that 50/60 range of CIP header of received Isochronous packet is ‘1’
Clears to ‘0’ by lead of this register.
Indicates that STYPE range of CIP hea der of received Isochronous packet is
‘00000’ or ‘00001’.
0
1
Rx stype
err-A
Indicates that STYPE range of CIP header of received Isochronous packet is other
than ‘00000’ or ‘00001’.
Clears to ‘0’ by lead of this register.
0
1
Indicates that FIFO on LINK I/F side of bridge-Ach is not full.
Indicates that FIFO on LINK I/F side of bridge-Ach is full.
BRG FIFO
full-A
4
3
Read
Read
0
1
Indicates that FIFO on LINK I/F side of bridge-Ach is not empty.
Indicates that FIFO on LINK I/F side of bridge-Ach is empty.
BRG FIFO
emp-A
0
1
Indicates that DBC range of CIP header of received Isochronous packet is normal.
2
Rx DBC err-A
Read
Indicates that DBC range of CIP header of received Isochronous packet received is
not consecutive.
Clears to ‘0’ by lead of this register.
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LSI Specification
MB86617A
BIT
Bit Name
Action
Read
Value
0
Function
Indicates that CIP header of received Isochronous packet is normal.
1
Rx CIP err-A
Indicates that CIP header of received Isochronous packet has an error.
Clears to ‘0’ by lead of this register.
1
0
1
Indicates that FMT range of CIP header of received Isochronous packet is the value
allowed to be received at DV-EN, DSS-EN or TS-EN (1Ch –bit10 to 8)
(DV=‘00000’, MPEG2=‘10000’ or DSS=‘100001’).
0
Rx FMT err-A
Read
Indicates that FMT range of CIP header of received Isochronous packet is other
than the value allowed to be received at DV-EN, DSS-EN or TS-EN (1Ch –bit10 to
8) (DV=‘00000’, MPEG2=‘10000’ or DSS=‘100001’).
Clears to ‘0’ by reading of this register.
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LSI Specification
MB86617A
7.29. Data Bridge Transmit/Receive Status Register [B]
Data bridge transmit/receive status register [B] indicates status of packet transmitted/received by bridge-Bch.
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
AD
50h
R/W
R
BRG
FIFO
emp-
B
Tx
busy -
B
Rx
Rx
Rx
Rx
dlen
err-B
Rx
stype
err-B
BRG
FIFO
full-B
Rx
DBC
err-B err-B
Rx
CIP
Rx
FMT
err-B
Rx o/e
chg-B
Tx
Rx
Rx 56
-
busy - 1STP- EMI
B
late-B late-B err-B
B
chg-B
Initial Value
BIT
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘1’
‘0’ ‘0’
‘0’
Bit Name
Tx busy-B
Action
Value
0
Function
Indicates that bridge-Bch is not in the process of transmit.
Indicates ‘0’ when Tx end-B (12h-bit14) is set at ‘1’ and transmit process is
stopped.
15
Read
Indicates that bridge-Bch is in the process of transmit.
1
0
Indicates ‘1’ when Tx start -B (12h-bit15) is set at ‘1’ and transmit process is
started.
Indicates that bridge-Bch is not in the process of receive.
Indicates ‘0’ when Rx end-B (3Ch-bit14) is set at ‘1’ and receive process is
stopped.
14
Rx busy-B
Read
Indicates that bridge-Bch is in the process of receive.
1
0
1
0
1
0
1
Indicates ‘1’ when Rx start -B (3Ch-bit15) is set at ‘1’ and receive process is
started.
Indicates that received Isochronous packet after starting receive process is not the
first receive packet.
13
12
11
Rx 1STP-B
Read
Read
Read
Indicates that the first Isochronous packet is received after starting receive process.
Clears to ‘0’ by lead of this register.
Indicates that EMI information of receive Isochronous packet header is not
changed.
Rx EMI
chg-B
Indicates that EMI information of receive Isochronous packet header has changed
from just former EMI information of packet received by Isochronous-cycle.
Clears to ‘0’ by lead of this register.
Indicat es that odd/even information of receive Isochronous packet header is not
changed.
Rx o/e chg-B
Indicates that odd/even information of receive Isochronous packet header has
changed from just former odd/even information of packet received by
Isochronous-cycle.
Clears to ‘0’ by lead of this register.
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LSI Specification
MB86617A
BIT
Bit Name
Action
Read
Value
0
Function
Indicates that data length of receive packet is same as specified data length in
format.
10
Rx dlen-err-B
Indicates that data length of receive packet differs to the specified data length in the
format.
1
Clears to ‘0’ by lead of this register.
9
8
Reserved
Tx late-B
Read
Read
-
Always indicates ‘0’.
0
Indicates that transmit packet is transmitted normally.
Indicates that transmit packet became Late packet. Delete packet, and not
transmit.
Clears to ‘0’ by lead of this register.
1
0
Indicates that received packet is normal.
7
6
Rx late-B
Read
Read
Indicates that received packet was Late packet.
Deletes packet, and does not output to TSP-IC.
Clears to ‘0’ by lead of this register.
1
0
1
Indicates that 50/60 range of CIP header of received Isochronous packet is ‘0’.
Rx 56 err-B
Indicates that 50/60 range of CIP header of received Isochronous packet is ‘1’
Clears to ‘0’ by lead of this register.
Indicates that STYPE range of CIP header of received Isochronous packet is
‘00000’ or ‘00001’.
0
1
5
Rx stype err-B
Read
Indicates that STYPE range of CIP header of received Isochronous packet is other
than ‘00000’ or ‘00001’.
Clears to ‘0’ by lead of this regist er.
0
1
0
1
Indicates that FIFO on LINK I/F side of bridge-Ach is not full.
Indicates that FIFO on LINK I/F side of bridge-Ach is full.
Indicates that FIFO on LINK I/F side of bridge-Ach is not empty.
Indicates that FIFO on LINK I/F side of bridge-Ach is empty.
BRG FIFO
full-B
4
3
Read
Read
BRG FIFO
emp-B
0
1
Indicates that DBC range of CIP header of received Isochronous packet is normal.
2
Rx DBC err-B
Read
Indicates that DBC range of CIP header of received Isochronous packet is not
consecutive.
Clears to ‘0’ by lead of this register.
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LSI Specification
MB86617A
BIT
Bit Name
Action
Read
Value
0
Function
Indicates that CIP header of received Isochronous packet is normal.
1
Rx CIP err-B
Indicates that CIP header of received Isochronous packet has an error.
Cleared to ‘0’ by lead of this register.
1
0
1
Indicates that FMT range of CIP header of received Isochronous packet is the value
allowed to be received at DV-EN, DSS-EN or TS-EN (1Ch –bit10 to 8)
(DV=‘00000’, MPEG2=‘10000’ or DSS=‘100001’).
0
Rx FMT err-B
Read
Indicates that FMT range of CIP header of received Isochronous packet is other
than the value allowed to be received at DV-EN, DSS-EN or TS-EN (1Ch –bit10 to
8) (DV=‘00000’, MPEG2=‘10000’ or DSS=‘100001’).
Clears to ‘0’ by reading of this register.
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LSI Specification
MB86617A
7.30. Isochronous Channel Monitor Register
Isochronous channel monitor register is the register that indicates Isochronous packet channel flowing through 1394 bus.
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
AD
R/W
52h
54h
56h
58h
R
R
R
R
Isochronous channel monitor1
Isochronous channel monitor2
Isochronous channel monitor3
Isochronous channel monitor4
“0000 h”
Initial Value
BIT
Bit Name
Action
Value
Function
Indicate that ‘1’ at Bit corresponding to channel number of Isochronous packet
flowing through 1394 bus.
52h-bit15 - 0: channel0 - channel15
54h-bit15 - 0: channel16 - channel31
56h-bit15 - 0: channel32 - channel47
58h-bit15 - 0: channel48 - channel63
Isochronous
channel
monitor
15 - 0
Read
-
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LSI Specification
MB86617A
7.31. Cycle-timer-monitor Indicate Register
Cycle-timer-monitor indicate register indicates value of integrated cycle-timer register.
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
AD
R/W
5Ah
5Ch
R
R
cycle-timer-monitor (hi)
cycle-timer-monitor (lo)
“0000 h”
Initial Value
BIT
Bit Name
Action
Value
-
Function
cycle-timer-m
onitor
Indicate value of built-in cycle-timer register.
(MSB: bit15, LSB: bit0)
15 - 0
Read
Note) This register latches the lower word(5A h) by reading out lower word (5Ch), and releases latch by reading out upper word.
To read out this register, make sure to read out in the order of 5Ch ® 5A h, two as a set.
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LSI Specification
MB86617A
7.32. Ping Time Monitor Register
Ping time monitor register is the register that indicates time period of transmitting request packet to receiving response packet to the request.
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
AD
5Eh
R/W
R
Ping time monitor
“0000 h”
Initial Value
BIT
Bit Name
Action
Value
-
Function
Indicate time period from transmitting request packet to receiving response packet
Ping time
monitor
15 - 0
Read
to the request. Counts by 20ns unit.
(MSB: bit15, LSB: bit0)
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LSI Specification
MB86617A
7.33. PHY/LINK Register/Address Setting Register
PHY/LINK register/address setting register is the register that sets address in order to access PHY/LINK register indirectly. PHY/LINK
register indicated with address set by this register can be accessed from PHY/LINK register/access port.
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
AD
60h
R/W
R/W
-
-
-
-
-
-
-
-
-
phy/link-addr
“00 h”
Initial Value
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
BIT
Bit Name
reserved
Action
Value
-
Function
Read
Always indicate‘0’.
Always write in ‘0’.
15 - 7
Write
-
-
Read/
Write
Set address of PHY/LINK register to be accessed.
(MSB: 6, LSB: 0)
6 - 0
phy/link-addr
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LSI Specification
MB86617A
7.34. PHY/LINK Register Access Port
PHY/LINK register access port is the port to access PHY/LINK register indirectly. PHY/LINK register indicated with address set by
PHY/LINK register/address setting register can be accessed from this port.
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
AD
62h
R/W
R/W
phy/link-data
“0000 h”
Initial Value
BIT
Bit Name
Action
Value
-
Function
Indicates PHY/LINK register contents defined by address set by PHY/LINK
register/address setting register. (MSB: 15, LSB: 0)
Read
15 - 0
phy/link-data
Executes write in the process of register defined by this address set by PHY/LINK
register/address setting register. (MSB: 15, LSB: 0)
Write
-
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LSI Specification
MB86617A
7.35. Revision Indicate Register
Revision indicate register is the register that indicates chip revision of this LSI.
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
AD
R/W
64h
66h
Revision code (hi)
Revision code (lo)
Fixed
R
Initial Value
BIT
Bit Name
Action
Value
-
Function
Indicate Revision code.
(MSB: bit15, LSB: bit0)
15 - 0
Revision code
Read
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LSI Specification
MB86617A
7.36. Transmit CGMS/TSCH Indicate Register [A]
Transmit CGMS/TSCH indicate register [A] indicates CGMS information and identification of TS type for source packet input from port A
at TSP IC I/F.
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
AD
80h
R/W
R
CGMSA -2
“00 b”
TSCHA-2
“00 h”
CGMSA -1
“00 b”
TSCHA-1
“00 h”
Initial Value
BIT
Bit Name
CGMSA -2
Action
Value
-
Function
Indicates CGMS information for source packet indicated in TSCHA-2 (bit13 to 8).
(MSB: bit15, LSB: bit14)
15 - 14
Read
Read
Read
Read
Indicates if ID of TS type for source packet input from port A at TSP IC I/F is
different from that in low bit (TSCHA-1).
13 - 8
7 - 6
5 - 0
TSCHA-2
CGMSA -1
TSCHA-1
-
-
-
(MSB: bit13, LSB: bit8)
Indicates CGMS information for source packet indicated in TSCHA-1 (bit5 to 0).
(MSB: bit7, LSB: bit6)
Indicates ID of TS type for source packet input first from port A at TSP IC I/F
(MSB: bit5, LSB: bit0)
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LSI Specification
MB86617A
7.37. Transmit CGMS/TSCH Indicate Register [B]
Transmit CGMS/TSCH indicate register [B] indicates CGMS information and identification of TS type for source packet input from port B
at TSP IC I/F.
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
AD
82h
R/W
R
CGMSB -2
“00 b”
TSCHB-2
“00 h”
CGMSB -1
“00 b”
TSCHB-1
“00 h”
Initial Value
BIT
Bit Name
CGMSB -2
Action
Value
-
Function
Indicates CGMS information for source packet indicated in TSCHB-2 (bit13 to 8).
(MSB: bit15, LSB: bit14)
15 - 14
Read
Read
Read
Read
Indicates if ID of TS type for source packet input from port B at TSP IC I/F is
different from that in low bit (TSCHB-1).
13 - 8
7 - 6
5 - 0
TSCHB-2
CGMSB -1
TSCHB-1
-
-
-
(MSB: bit13, LSB: bit8)
Indicates CGMS information for source packet indicated in TSCHB-1 (bit5 to 0).
(MSB: bit7, LSB: bit6)
Indicates ID of TS type for source packet input first from port B at TSP IC I/F
(MSB: bit5, LSB: bit0)
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LSI Specification
MB86617A
7.38. Transmit CGMS/TSCH Indicate Status Register
Transmit CGMS/TSCH indicate status register indicates validity of source packet input from TSP IC I/F.
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
AD
84h
R/W
R/W
act -
TSC
HB
act -
TSC
HA
vld-T vld-T
SC
HB-2
vld-T vld-T
SC
HA-2
-
-
-
-
-
-
-
-
-
-
SC
HB-1
SC
HA-1
Initial Value
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
BIT
Bit Name
reserved
Action
Value
Function
Read
-
-
Always indicate ‘0’.
Always write in ‘0’.
15 - 11
Write
Indicates that the packet indicated in CGMSB-1 and TSCHB-1 (82h-bit7 to 0) was
finally input from port B at TSP IC I/F.
0
1
Read
Indicates that the packet indicated in CGMSB-2 and TSCHB-2 (82h-bit15 to 8)
was finally input from port B at TSP IC I/F.
10
Act -TSCHB
Write
Read
-
Clears to ‘0’ by writing “1”.
Indicates that the value indicated in CGMSB-2 and TSCHB-2 (82h-bit15 to 8) is
invalid.
0
1
Indicates that the value indicated in CGMSB-2 and TSCHB-2 (82h-bit15 to 8) is
valid.
9
Vld-TSCHB-2
Write
-
Clears to ‘0’ by writing “1”.
Indicates that the value indicated in CGMSB -1 and TSCHB-1 (82h-bit7 to 0) is
invalid.
0
Read
Indicates that the value indicated in CGMSB -1 and TSCHB-1 (82h-bit7 to 0) is
valid.
8
Vld-TSCHB-1
reserved
1
-
Write
Clears to ‘0’ by writing “1”.
Read
-
-
Always indicate ‘0’.
Always write in ‘0’.
7 - 3
Write
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BIT
Bit Name
Action
Read
Value
0
Function
Indicates that the packet indicated in CGMSA-1 and TSCHA-1 (80h-bit7 to 0) was
finally input from port A at TSP IC I/F.
Indicates that the packet indicated in CGMSA-2 and TSCHA-2 (80h-bit15 to 8)
was finally input from port A at TSP IC I/F.
2
act -TSCHA
1
-
Write
Clears to ‘0’ by writing “1”.
Indicates that the value indicated in CGMSA-2 and TSCHA-2 (80h-bit15 to 8) is
invalid.
0
Read
Indicates that the value indicated in CGMSA-2 and TSCHA-2 (80h-bit15 to 8) is
valid.
1
vld-TSCHA-2
vld-TSCHA-1
1
Write
Read
-
Clears to ‘0’ by writing “1”.
Indicates that the value indicated in CGMSA-1 and TSCHA-1 (80h-bit7 to 0) is
invalid.
0
Indicates that the value indicated in CGMSA-1 and TSCHA-1 (80h-bit7 to 0) is
valid.
0
1
-
Write
Clears to ‘0’ by writing “1”.
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LSI Specification
MB86617A
7.39. Transmit EMI/OE Setting Register
Transmit EMI/OE setting register sets EMI information and Odd/Even value added to empty packet until valid data is transmitted.
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
AD
86h
R/W
R/W
IPH
OE-
B
IPH
OE-
A
IPH
select
-B
IPH
select
-A
IPH EMI-B
“00 b”
-
-
IPH EMI-A
“00 b”
-
-
-
-
-
-
Initial Value
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
BIT
Bit Name
Action
Value
0
Function
Sets the default value (EMI=‘00’, OE = ‘0’) as EMI information and Odd/Even
value added to IPH of empty packet until valid data is transmitted after starting
transmission.
Read/
Write
15
IPH select -B
Selects the setting value of IPH EMI-B (bit14 to 13) and IPH OE-B (bit 12) as EMI
information and Odd/Even value added to IPH of empty packet until valid data is
transmitted after starting transmission.
1
-
Set EMI information which are set in IPH of empty packet transmitted from
bridge-Bch.
Valid only when IPH select-B (bit15) is set to ‘1’.
Read/
Write
14 - 13
IPH EMI-B
(MSB: bit14, LSB: bit13)
EMI information after transmitting valid data depends on the setting of EMI
select-B (12h-bit4).
Set Odd/Even value which is set in IPH of empty packet transmitted from
bridge-Bch.
Read/
Write
12
IPH OE-B
reserved
-
Valid only when IPH select-B (bit15) is set to ‘1’.
EMI information after transmitting valid data depends on the setting of o/e select-B
(3Eh-bit15).
Read
-
-
Always indicate ‘0’.
Always write in ‘0’.
11 - 8
Write
Sets the default value (EMI=‘00’, OE = ‘0’) as EMI information and Odd/Even
value added to IPH of empty packet until valid data is transmitted after starting
transmission.
0
1
Read/
Write
7
IPH select -A
Selects the setting value of IPH EMI-A (bit6 to 5) and IPH OE-A (bit 4) as EMI
information and Odd/Even value added to IPH of empty packet until valid data is
transmitted after starting transmission.
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MB86617A
BIT
Bit Name
Action
Value
Function
Set EMI information which are set in IPH of empty packet transmitted from
bridge-Ach.
Valid only when IPH select-A (bit7) is set to ‘1’.
(MSB: bit6, LSB: bit5)
Read/
Write
6 - 5
IPH EMI-A
-
EMI information after transmitting valid data depends on the setting of EMI
select-A (10h-bit4).
Set Odd/Even value which is set in IPH of empty packet transmitted from
bridge-Ach.
Read/
Write
4
IPH OE-A
reserved
-
Valid only when IPH select-A (bit7) is set to ‘1’.
EMI information after transmitting valid data depends on the setting of o/e select-A
(3Eh-bit8).
Read
-
-
Always indicate ‘0’.
Always write in ‘0’.
3 - 0
Write
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LSI Specification
MB86617A
Chapter 8 PHY/INK Register Function Description
This chapter explains the Physical Register and Link register that enables to access from PHY/LINK register access port (address 62h) by
setting PHYT/LINK register address setting register (address 60h) in detail.
8.1.
8.2.
PHY/LINK Register Table
Physical Register#00
8.3.
Physical Register#01
8.4.
Physical Register#02
8.5.
Physical Register#03
8.6.
Physical Register#04
8.7.
Physical Register#05
8.8.
8.9.
Physical Register#07, 08, 09
Physical Register#0A, 0B, 0C
Physical Register#0D, 0E, 0F
Physical Register#10
Physical Register#11, 12, 13
Physical Register#14, 15, 16
Physical Register#17, 18, 19, 1A, 1B, 1C, 1D, 1E
Link Register#00
8.10.
8.11.
8.12.
8.13.
8.14.
8.15.
8.16.
8.17.
8.18.
Link Register#01
Link Register#02
Link Register#03
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LSI Specification
MB86617A
8.1. PHY/LINK Register Table
Table of Physical Register and Link Register is shown below.
PHY/LINK
Write
Read
addr
00h
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
12h
14h
16h
18h
1Ah
1Ch
1Dh
1Eh
20h
24h
26h
28h
2Ah
(reserved)
Physical register #01
(reserved)
Physical register #00
¬
Physical register #02
Physical register #03
(reserved)
Physical register #04
Physical register #05
(reserved)
¬
¬
Physical r egister #07
(reserved)
Physical register #08
(reserved)
Physical register #09
Physical register #0A
Physical register #0B
Physical register #0C
Physical register #0D
Physical register #0E
Physical register #0F
(reserved)
¬
¬
¬
¬
¬
¬
Physical register #10
Physical register #11
Physical register #12
Physical register #13
Physical register #14
Physical register #15
Physic al register #16
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
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LSI Specification
MB86617A
PHY/LINK
addr
Write
Read
2Ch
2Eh
30h
32h
34h
36h
38h
3Ah
3Ch
3Eh
40h
42h
Physical register #17
Physical register #18
Physical register #19
Physical register #1A
Physical register #1B
Physical register #1C
Physical register #1D
Physical register #1E
Link register #00
¬
¬
¬
¬
¬
¬
¬
¬
¬
¬
¬
¬
Link register #01
Link register #02
Link register #03
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LSI Specification
MB86617A
8.2. Physical register #00 (read)
Physical Register#00 is the register that indicates Physical ID, root status, and cable power st atus of this node.
phy/
link-
addr
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
R/W
R
00 h
-
-
-
-
-
-
-
-
Physical_ID
“00 h”
R
PS
‘0’
Initial value
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
Description of Each Bit
BIT
Bit name
Reserved
Action
Value
0
Function
15 – 8
Read
Read
Always indicate ‘0’.
Indicate node No. of this node determined by Self-identify during processing bus
reset. (MSB : 7 , LSB : 2)
7 – 2
Physical_ID
-
Effective after completion of bus reset.
0
1
0
1
Indicates that this node is not root.
1
0
R
Read
Read
Indicates that this node is root.
Indicates that the supplied cable power is below specification.
Indicates that the supplied cable power is over specification.
PS
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MB86617A
8.3. Physical register #01 (read/write)
Physical Register#01 is the register that set s/indicates force-root and gap-count.
Do not write into this register except for the case that the node is Bus manager or Isochronous resource manager in the environment with
no Bus manager.
phy/
link-
addr
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
R/W
R/W
02 h
-
-
-
-
-
-
-
-
RHB
‘0’’
IRB
‘0’
Gap_count
“3F h”
Initial Value
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
Description of Each Bit
BIT
Bit Name
Action
Value
Function
Read
-
-
Always indicate ‘0’.
Always write‘0’.
15 - 8
reserved
Write
0
1
0
This node does not try to be root during next bus reset.
This node tries to be root during next bus reset.
Does not perform bus reset.
RHB
Note 1)
Read/
Write
7
6
Read/
Write
IRB
1
Performs bus reset. Automatically clears to “0” at the completion of bus reset.
Read
-
-
Indicate current gap-count value (MSB: 5 , LSB: 0).
Set gap-count value (MSB: 5 , LSB: 0).
Gap_count
Note 2)
5 - 0
Write
Note 1) This bit is automatically set by receiving the PHY configuration packet, too.
Note 2) This bit is automatically set by receiving the PHY configuration packet, too.
Also, this bit value returns to initial value at the second next bus reset.
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LSI Specification
MB86617A
8.4. Physical register #02 (read)
Physical Register#02 is the register that indicates if the extended PHY register map is in existence or not, and the number of ports (3
port).
phy/
link-
addr
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
R/W
R
04 h
-
-
-
-
-
-
-
-
Extended
“7 h”
-
Total_ports
“3h”
Fixed value
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
Description of each Bit
<
BIT
Bit Name
Action
Value
-
Function
15 - 8
reserved
Read
Read
Always indicate ‘0’.
Indicate that this node has the extended PHY register map. (MSB: 7 , LSB: 5)
Always indicate fixed value “7 h”.
7 - 5
Extended
-
4
reserved
Read
Read
-
-
Always indicates ‘0’.
Indicate the number of ports held by this node (MSB: 4 , LSB: 0).
Always indicate fixed value “3 h”.
3 - 0
Total_ports
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MB86617A
8.5. Physical register #03 (read)
Physical Register#03 is the register that indicates max. transfer speed (S400) of this node.
phy/
link-
addr
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
R/W
R
06 h
-
-
-
-
-
-
-
-
Max _speed
‘1’
-
Delay
‘0’
Fixed value
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
Description of Each Bit
<
BIT
Bit Name
Action
Value
-
Function
15 - 8
reserved
Read
Read
Read
Read
Always indicate ‘0’.
Indicate max. transfer speed supporting PHY of this node (MSB: 7 , LSB: 5).
Always indicates fixed value “010 b” (= S400).
7 - 5
4
Max_speed
reserved
Delay
-
-
-
Always indicates ‘0’.
Indicate Delay value at the receive signal repeat (MSB: 3 , LSB: 0).
Always indicate fixed value “0000 b”.
3 - 0
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MB86617A
8.6. Physical register #04 (read/write)
Physical Register#04 is the register that sets the parameter of Self-ID packet to be transmitted by this node.
phy/
link-
addr
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
R/W
R
Jitter
Link_a Conte
08 h
-
-
-
-
-
-
-
-
Pwr _class
‘0’
ctive
nder
W
-
-
-
Initial Value
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘1’
‘1’
‘0’
‘0’
‘0’
‘0’
‘0’
< Description of Each Bit
BIT
Bit Name
Action
Value
Function
Read
-
-
Always indicate ‘0’.
Always write in ‘0’.
15 - 8
reserved
Write
Link_active
Note 1)
Read/
Write
Set L bit (Link_active) value of Self-ID packet automatically transmitted by this
node with the system power ON.
7
6
-
-
Contender
Note 2)
Read/
Write
Set c bit (CONTENDER) value of Self-ID packet automatically transmitted by this
node with the system power ON.
Indicate Jitter value at receive signal repeat.
(MSB : 5 , LSB : 3)
Read
-
5 - 3
2 - 0
Jitter
Always indicates fixed value “000 b”.
Write
-
-
Always write in ‘0’.
Pwr _class
Note 3)
Read/
Write
Set pwr field (POWER_CLASS) value of Self-ID packet automatically transmitted
by this node with the system power ON.
Note 1) L bit value of Self-ID packet that is automatically transmitted by this node with the cable supply power ON is always set at ‘0’
regardless of the setting of this bit.
Note 2) c bit value of Self-ID packet that is automatically transmitted by this node with the cable supply power ON is always set at ‘0’
regardless of the setting of this bit.
Note 3) pwr field value of Self-ID packet which is automatically transmitted by this node with the cable supply power ON is always set
at the value of PWR3 - 1 terminal regardless of the setting of this bit.
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LSI Specification
MB86617A
8.7. Physical register #05 (read/write)
Physical Register#05 is the register indicating availability of cable supply power standard and timeout detect of arbitration state machine.
phy/
link-
addr
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
R/W
R/W
Resume
_Int
Pwr
_fail
Time Port_
out
Enab
Enab_
multi
0A h
-
-
-
-
-
-
-
-
ISBR Loop
event _accel
Initial Value
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’’
‘0’
‘0’
‘0’
‘0’
‘0’ ‘0’
‘0’
< Description of Each Bit
BIT
Bit Name
Action
Value
-
Function
Read
Always indicate ‘0’.
Always write in ‘0’.
15 - 8
reserved
Write
-
0
1
0
Does not indicate ‘1’ at Port_event bit during resume processing.
Indicates ‘1’ at Port_event bit during resume processing.
Does not perform short bus reset.
Read/
Write
7
6
Resume_Int
ISBR
Read/
Write
Performs short bus reset. Automatically clears to ‘0’ at the completion of bus
reset.
1
0
1
-
Indicates that port connection is in a loop.
Read
Write
Read
5
4
Loop
Indicates that port connection is in a loop.
Clears the bit value to ‘0’ by writing in ‘1’.
0
1
-
Indicates that the cable supply power satisfies the standard.
Indicates that the cable supply power does notsatisfy the standard.
Clears the bit value to ‘0’ by writing in ‘1’.
Pwr_fail
Write
0
Indicates that timeout is not detected by arbitration state machine.
Read
3
Timeout
1
-
Indicates that timeout is det ected byarbitration state machine.
Clears the bit value to ‘0’ by writing in ‘1’.
Write
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MB86617A
BIT
Bit Name
Action
Read
Value
0
Function
Indicates that port event and resume processing have notoccurred.
Indicates that Connected, Bias, Disabled, Fault bit has changed when Int_enable bit
is set at‘1’.
2
Port_event
1
Indicates that resume processing was performed when Resume_Int bit is set at‘1’.
Write
-
Clears the bit value to ‘0’ by writing in ‘1’.
Disables arbitration acceleration function.
0
Read/
1
0
Enab_accel
Enab_multi
Write
1
0
1
Enables arbitration acceleration function.
Disables multi-speed packet concatenation function.
Enables multi-speed packet concatenation function.
Read/
Write
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MB86617A
8.8. Physical register #07, 08, 09 (read)
Physical Register#07, 08, 09 are the registers that indicate signal condition of IEEE1394 port and cable connection condition.
phy/
link-
addr
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
R/W
Child- Connec
ted-0
Child- Connec
ted-1
Child- Connec
0C h
0E h
10 h
R
R
R
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Astat-0
Bstate-0
-
-
-
-
0
Astat-1
Astat-2
Bstate-1
Bstate-2
1
-
-
-
-
-
-
-
-
-
-
2
ted-2
Initial Value
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
< Description of Each Bit
BIT
Bit Name
Action
Value
-
Function
15 - 8
reserved
Read
Always indicate ‘0’.
Indicate TPA line state of 1394 port n (MSB : 7 , LSB : 6).
00
01
10
=
=
=
invalid
‘1’
‘0’
7 - 6
Astat-n
Read
-
-
11
=
‘Z’
Indicate TPB line state of 1394 port n (MSB : 5 , LSB : 4).
00
01
10
11
=
=
=
=
invalid
‘1’
‘0’
5 - 4
Bstat-n
Child-n
Read
Read
‘Z’
0
1
0
1
-
Indicates that 1394 port n is parent port.
Indicates that 1394 port n is children port.
Indicates that cable is not connected to 1394 port n.
Indicates that cable is connected to 1394 port n.
Always indicate ‘0’
3
2
Connected-n
reserved
Read
Read
1 - 0
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LSI Specification
MB86617A
8.9. Physical register #0A, 0B, 0C (read/write)
Physical Register#0A, 0B, 0C are the registers that indicate bias detect condition of IEEE1394 installed in this node and performs setting
of enable/disable of IEEE1394 port.
phy/
link-
addr
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
R/W
R
W
R
Bias-0
Disabl
ed-0
12 h
14h
16h
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Bias-1
-
Disabl
ed-1
W
R
Bias-2
-
Disabl
ed-2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
W
Initial Value
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
< Description of Each Bit
BIT
Bit Name
Action
Value
Function
Read
-
-
Always indicates’0’.
Always write in ‘0’.
15 - 2
reserved
Write
0
1
-
Indicates that bias voltage is not detected at 1394 port n.
Indicates that bias voltage is detected at 1394 port n.
Always indicates ‘0’.
Read
1
0
Bias-n
Write
0
1
Enables 1394 port n.
Read/
Write
Disabled-n
Disable 1394 port n.
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LSI Specification
MB86617A
8.10. Physical register #0D, 0E, 0F (read/write)
Physical Register#0D, 0E, 0F are the registers that indicate maximum transfer speed of the node connected to IEEE1394 port installed in
this node.
phy/
link-
addr
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
R/W
R
W
R
Negotiated_speed-0
Int_en
able-0
18 h
1A h
1C h
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Fault-0
Fault-1
-
-
-
-
-
-
-
-
-
Negotiated_speed-1
Int_en
able-1
W
R
-
-
-
Negotiated_speed-2
Int_en
able-2
-
-
-
-
-
-
-
-
Fault-2
‘0’
-
-
-
W
-
-
-
Initial value
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’’
‘0’’
‘0’
‘0’
‘0’
‘0’
‘0’
< Description of Each Bit
BIT
Bit Name
Action
Read
Value
Function
-
-
Always indicates’0’.
Always write in ‘0’.
15 - 8
reserved
Write
Indicate max. transfer speed between nodes connected to 1394 port n.
(MSB: 7, LSB: 5)
000
001
010
=
=
=
S100
S200
S400
=
Read
-
Negotiated_
speed-n
7 - 5
011 - 111
invalid
Write
-
Always write in ‘0’.
Does not indicate ‘1’ at Port_event bit when Connected, Bias, Disabled, Fault bit
changed.
0
Read/
Write
4
Int_enable-n
1
0
Indicates ‘1’ at Port_event bit when Connected, Bias, Disabled, Fault bit changed.
Indicates that suspend or resume processing is normal.
Read
3
Fault
1
Indicates that suspend or resume processing occurred error.
Write
-
-
-
Clears the bit value to ‘0’ by writing in ‘1’.
Always indicates’0’.
Read/
Write
2 - 0
reserved
Always write in ‘0’.
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LSI Specification
MB86617A
8.11. Physical register #10 (read)
Physical Register#10 is the register that indicates Compliance_level of this node.
phy/
link-
addr
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
R/W
R
1E h
-
-
-
-
-
-
-
-
Compliance_level
“01 h”
Fixed value
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
Description of Each Bit
BIT
Bit Name
reserved
Action
Value
-
Function
15 - 8
Read
Read
Always indicate ‘0’.
Indicate that this node supports P1394a standard.
(MSB: 7 , LSB: 0)
Compliance_l
evel
7 - 0
-
Always indicate fixe value “01 h”.
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LSI Specification
MB86617A
8.12. Physical register #11, 12, 13 (read)
Physical Register#11, 12, 13 are the registers that indicate Vendor_ID of this node.
phy/
link-
addr
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
R/W
R
20 h
-
‘0’
-
-
‘0’
-
-
-
‘0’
-
-
‘0’
-
-
‘0’
-
-
‘0’
-
-
‘0’
-
Vendor_ID-hi
“00 h”
Fixed Value
‘0’
-
22 h
R
Vendor_ID-mid
“00 h”
Fixed Value
‘0’
-
‘0’
-
‘0’
-
‘0’
-
‘0’
-
‘0’
-
‘0’
-
‘0’
-
24 h
R
Vendor_ID-lo
“0E h”
Fixed Value
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
Description of Each Bit
BIT
Bit Name
reserved
Action
Value
-
Function
15 - 8
Read
Read
Always indicate ‘0’.
Indicate Vendor ID of Fujitsu (MSB: 7, LSB: 0).
Always indicate fixed value “00000E h”.
7 - 0
Vendor_ID
-
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LSI Specification
MB86617A
8.13. Physical register #14, 15, 16(read)
Physical Register#14, 15, 16 are the registers that indicate Product_ID of this node.
phy/
link-
addr
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
R/W
R
26 h
-
‘0’
-
-
‘0’
-
-
-
‘0’
-
-
‘0’
-
-
‘0’
-
-
‘0’
-
-
‘0’
-
Product_ID-hi
“08 h”
Fixed Value
‘0’
-
28 h
R
Product_ID-mid
“66 h”
Fixed Value
‘0’
-
‘0’
-
‘0’
-
‘0’
-
‘0’
-
‘0’
-
‘0’
-
‘0’
-
2A h
R
Product_ID-lo
“17 h”
Fixed Value
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
< Description of Each Bit
BIT
Bit Name
Action
Value
-
Function
15 - 8
reserved
Read
Read
Always indicate ‘0’.
Indicate Product ID of this chip (MSB: 7, LSB: 0).
Always indicate fixed value “086617 h”.
7 - 0
Vendor_ID
-
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LSI Specification
MB86617A
8.14. Physical register #17, 18, 19, 1A, 1B, 1C, 1D, 1E (read/write)
Physical Register#17, 18, 19, 1A, 1B, 1C, 1D, 1E are in the range of 8 bit X 8 Free_RAM.
phy/
link-
addr
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
R/W
2Ch
2E h
30 h
32 h
34 h
36 h
38 h
3A h
R/
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Free_RAM-0
Free_RAM-1
Free_RAM-2
Free_RAM-3
Free_RAM-4
Free_RAM-5
Free_RAM-6
Free_RAM-7
“00 h”
R/W
R/
-
-
-
-
-
-
-
-
R/
-
-
-
-
-
-
-
-
R/
-
-
-
-
-
-
-
-
R/
-
-
-
-
-
-
-
-
R/
-
-
-
-
-
-
-
-
R/
-
-
-
-
-
-
-
-
Initial value
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
< Description of Each Bit
BIT
15 - 8
7 - 0
Bit Name
Action
Value
Function
Read
-
-
-
Always indicates’0’.
Always write in ‘0’.
reserved
Write
Read/
Write
Free_RAM
Range of 8 bit X 8 Free RAM.
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LSI Specification
MB86617A
8.15. Link register#00 (read/write)
Link Register#00 is the register that sets this node to operate as cycle master.
phy/
link-
addr
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
R/W
R/W
cycle
master
3Ch
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial Value
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’’
‘0’
‘1’
‘0’
‘0’
‘0’
‘0’
‘0’
< Description of Each Bit
BIT
Bit Name
Action
Read
Value
Function
-
-
Always indicate ‘0’.
Always write in ‘0’.
Does not cycle master.
15 - 6
reserved
Write
0
1
Read
5
cycle master
reserved
Operates as cycle master if it is root.
Write
Read
-
-
-
Sets the value of this bit at ‘1’ by writing in ‘1’.
Always indicate ‘0’.
4 - 0
Write
Always write in ‘0’.
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LSI Specification
MB86617A
8.16. Link register#01 (read/write)
Link Register#00 is the register that sets this node to perform as cycle master.
phy/
link-
addr
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
R/W
R/W
cycle
master
3E h
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial Value
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’’
‘0’
‘1’
‘0’
‘0’
‘0’
‘0’
‘0’
< Description of Each Bit
BIT
Bit Name
Action
Read
Value
Function
-
-
Always indicate ‘0’.
Always write in ‘0’.
Does not cycle master.
15 - 6
reserved
Write
0
1
Read
5
cycle master
reserved
Performs as cycle master if it is root.
Write
Read
-
-
-
Sets the value of this bit at ‘0’ by writing in ‘1’.
Always indicate ‘0’.
4 - 0
Write
Always write in ‘0’.
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LSI Specification
MB86617A
8.17. Link register #02 (read/write)
Link Register#02 is the register that sets transfer mode of acknowledge packet transmitted by this node and disable setting
of Link layer.
phy/
link-
addr
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
R/W
R/W
ack
mode
Link
Enable
40 h
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial Value
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’’
‘0’
‘0’
‘0’
‘1’
‘0’
‘1’
‘0’
< Description of Each Bit
BIT
Bit Name
Action
Read
Value
Function
-
-
Always indicate ‘0’.
Always write in ‘0’.
15 - 4
reserved
Write
At receipt of normal packet.
Automatically transmits Acknowledge packet of “ack_pending” to all
request packet.
Automatically transmits Acknowledge packet of “ack _complete” to
all response packet.
0
Automatically transmits packet.
Code value of Acknowledge packet, automatically transmitted when
error is detected, depends on the kind of error.
At receipt of normal packet.
Read/
Write
3
ack mode
Automatically transmits Acknowledge packet of “ack_pending” to
Read request and Lock request.
Automatically transmits Acknowledge packet of “ack_complete” to
Write request packet and all response packet.
1
Code value of Acknowledge packet automatically transmitted when
error is detected depends on the kind of error.
Read
-
-
Always indicates ‘0’.
Always write in ‘0’.
LINK layer is disabled.
LINK layer is enabled.
Always indicates ‘0’.
Always write in ‘0’.
2
1
0
reserved
Link Enable
reserved
Write
0
1
-
Read/
Write
Read
Write
-
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LSI Specification
MB86617A
8.18. Link register #03 (read/write)
Link Register#03 is the register that performs Link layer reset and initializes setting of the node.
phy/
link-
addr
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
R/W
R/W
Link
init
Link
reset
42 h
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial Value
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
< Description of Each Bit
BIT
Bit Name
Action
Read
Value
Function
-
-
Always indicate ‘0’.
Always write in ‘0’.
15 - 2
reserved
Write
0
1
0
1
Releases initialize of LINK layer.
Initializes LINK layer.
Read/
Write
1
0
Link init
Releases reset of LINK layer.
Resets LINK layer.
Read/
Write
Link reset
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MB86617A
Chapter 9 Instruction
This chapter explains the instruction codes and details for respective instructions.
9.1.
9.2.
Instruction Code Table
Description of Each Instruction
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MB86617A
9.1. Instruction Code Table
Instruction name
code
Operand
Start sleep
01
02
03
Remove sleep
Asynchronous receive
Remove busy mode
Send PHY packet
04
21
Asynchronous Send
31
63
71
72
73
Speed code
FIFO select code
Data-FIFO init
DMA Transmit (Asynchronous)
DMA Transmit (PHY packet)
DMA Receive
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MB86617A
9.2.
Description of Each Instruction
< Start sleep (01 h)
This instruction changes this device into forced sleep, stops the driver/receiver function of 1394 port, and then changed into the status
with this device’s cable cut.
Also, it stops the clock to be input from integrated PLL to IEEE1394 block.
Access to each register is available.
No interrupt this instruction is reported.
Confirm the sleep condition using sleep Bit (Bit4) of flag & status register (address 02h).
< Remove sleep (02 h)
This instruction releases this device from forced sleep condition.
No interrupt to this instruction is reported.
Confirm the sleep condition release using sleep Bit (Bit4) of flag & status register (address 02h)
< Asynchronous Receive (03 h)
This instruction reads the out data stored at ASYNC receive specific buffer.
Even though the receive data length does not satisfy with the quadlet unit, this instruction stores up to quadlet unit.
The receive data does not have CRC code and Logical inverse part.
< Remove busy mode (04 h)
This instruction releases the busy mode set due to receiving normal Asynchronous packet or Self-ID packet addressed to this node.
<
Send PHY packet (21 h)
This instruction transmits the data stored at ASYNC receive specific buffer.
Do not issue this instruction in case that this instruction is not Bus manager node, or not Isochronous resource manager no de without
existence of Bus manager.
When packet transmit operation is completed normally, this instruction report s the interrupt of “Physical packet send” (INT25).
Store the transmit data at ASYNC transmit specific buffer beforehand.
Logical inverse part is added automatically by this device.
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LSI Specification
MB86617A
< Asynchronous Send (31 h)
This instruction transmits the data stored at the ASYNC transmit specific buffer.
This instruction performs the following serial actions, from access to arbitration by detecting arb-reset-gap, generation and transfer of
packet, to receipt of Acknowledge packet.
When the performances from packet transmit to Acknowledge receive are normally completed, this instruction reports interrupt of
“Asynchronous packet send” (INT17).
In case of occurring an error, it reports interrupt of error, and completes performance.
Store the transmit data at ASYNC transmit specific buffer beforehand.
In case that the transmit data length does not satisfy with the quadlet unit, write in ‘0’ until quadlet unit.
The CRC code is to be added automatically.
Received Acknowledge is indicated at receive Acknowledge indicate register (address 08h).
Note) When destination-ID is set at Broadcast, it is completed without waiting for receipt of Acknowledge.
BIT
Operand Name
Reserved
Meaning
7 - 2
Always specify ‘0’.
Specify transmit Speed code . (MSB: 1, LSB: 0)
00
01
10
11
= S100
= S200
= S400
1 - 0
Speed code
=
(reserved)
< Data -FIFO init (63h)
This instruction clears the contents of buffer specified by Operand.
BIT
Operand Name
Meaning
Specify buffer to be cleared. (MSB: 7, LSB: 0)
“11 h”
“12 h”
= ASYNC receive specific buffer
= ASYNC transmit specific buffer
7 - 0
FIFO select code
Other than above
=
(reserved)
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LSI Specification
MB86617A
< DMA Transmit (Asynchronous) (71h)
This instruction writes in the transmit Asynchronous packet to ASYNC transmit specific buffer using DMA transmit.
Assert DREQ signal after issuing this instruction.
Determine the transmit bite value by transmit data length within packet header, write in up to quadlet unit, then negate DREQ signal.
After completion of writing in, issue the Asynchronous send instruction (31h).
< DMA Transmit (PHY packet) (72h)
This instruction writes in the transmit PHY packet to ASYNC transmit specific buffer using DMA transfer.
Assert the DREQ signal after issuing this instruction.
Negate the DREQ signal after writing in 2 bites.
After completion of writing in, issue the Send PHY packet instruction (21h).
< DMA Receive (73h)
This instruction reads out the data stored in ASYNC receive specific FIFO using DMA transfer.
Issue Asynchronous receive instruction (03h) before issuing this instruction.
Assert DREQ signal after issuing this instruction.
Negate DREQ signal when ASYNC receive specific FIFO is empty.
105
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LSI Specification
MB86617A
Chapter 10 Interrupt
This chapter explains the inturrput-factors and method for interrupt-mask.
10.1.
Interrupt-factor Indicator Register & interrupt-mask Setting Register
10.2.
Interrupt
10.3.
Description of Interrupt
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MB86617A
10.1. Interrupt-factor Indicator Register & interrupt-mask Setting Register
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
AD
06h
R/
INT INT
1
INT
3
INT
4
INT
5
INT
6
INT
7
INT
8
INT
9
INT
10
INT
11
INT
12
INT
13
INT
14
INT
15
INT
16
R
2
W
R
interrupt-mask
INT
17
INT
18
INT
19
INT
20
INT
21
INT
22
INT
23
INT
24
INT
25
INT
26
INT
27
INT
28
INT
29
INT
30
INT
31
INT
32
08h
W
Interrupt-mask
‘0’ ‘0’
Intial Value
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
>
>
interrupt-factor Indicate Register
This register indicate the interrupt content reported by this device. Do not indicate the interrupt code specified MASK. Do not reflect
its code to XINT terminal either.
interrupt-mask setting register
This register masks the interrupt reported by this device. Do not report the interrupt if ‘1’ is set for Bit corresponding to interrupt factor.
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MB86617A
10.2. Interrupt
Interrupt
INT1
Interrupt Item
Loop detected
INT2
INT3
INT4
INT5
INT6
INT7
INT8
INT9
INT10
INT11
INT12
Self-ID packet error
Bus reset complete
Bus reset detected
Isochronous packet receive error (A-ch)
Isochronous packet receive error (B-ch)
Isochronous cycle too long
Bus occupancy violation
Asynchronous packet received
CPIF output header is no 47h (Transmit)
Data length short error
Data length long error
INT13
INT14
INT15
INT16
Packet format error
Header CRC error
Data CRC error
Asynchronous receive FIFO full
INT17
INT18
INT19
INT20
INT21
INT22
INT23
INT24
INT25
INT26
Asynchronous packet send
Input CGMS or TSCH changed
Acknowledge missing
Acknowledge send
Receive EMI or ODD/EVEN changed
First packet received
Cycle start packet received
Cycle start packet send
Physical packet send
Extended PHY packet received
INT27
INT28
INT29
INT30
INT31
INT32
Physical configuration packet received
Link-on packet received
Self-ID packet received
Receive late occurred
Instruction abort
Transmit late occurred
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10.3. Description of Interrupt
Each interrupt items are described below.
Interrupt
INT1
Interrupt Item
Description
Topology is in Loop.
> Need to issue “Bus reset”.
Loop detected
Occurred convention failure like Physical-ID did not count up each
Self-ID packet received during Self Identify process.
> Continues to receive Self-ID packet after reporting interrupt, but
reports “Bus reset complete” (05h) interrupt.
INT2
Self-ID packet error
Detected logical inverse error while receiving Self-ID packet after
sending Ping packet in normal transfer mode.
>Delete receive packet.
This device has completed Bus reset process and able to perform packet
transfer.
> All the follows, Bus reset, Tree Identify, and Self Identify, are
completed by this interrupt information.
INT3
INT4
Bus reset complete
Bus reset detected
Reset Bus reset in any of the following conditions.
>Detected BUSRESET signal from other node.
>Received “Bus reset”
The following errors occurred at bridge-Ach during packet receiving.
>Data length value differs from that specified in the format.
>The value of 50/60 range at CIP header is ‘1’ at DV receiving.
>The value of STYPE range at CIP header is other than ‘00000’
or ‘00001’ at DV receiving.
INT5
Isochronous packet receive error (A-ch)
>The value of DBC range at CIP header is discontinuous.
>Header error in CIP header.
>The value of FMT range at CIP header is other than that all owed to
be received at DV-EN, DSS-EN or TS-EN (1Ch-bit10 to 8)
(DV= ‘000000’, MPEG2-TS= ‘100000’, DSS=‘100001’).
The following errors occurred at bridge-Bch during packet receiving.
>Data length value differs f rom that specified in the format.
>The value of 50/60 range at CIP header is ‘1’ at DV receiving.
>The value of STYPE range at CIP header is other than ‘00000’
or ‘00001’ at DV receiving.
INT6
Isochronous packet receive error (B-ch)
>The value of DBC range at CIP header is discontinuous.
>Header error in CIP header.
>The value of FMT range at CIP header is other than that allowed to
be received at DV-EN, DSS-EN or TS-EN (1Ch-bit10 to 8)
(DV= ‘000000’, MPEG2-TS= ‘100000’, DSS=‘100001’).
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Interrupt
INT7
Interrupt Item
Description
Isochronous cycle exceeded specified time.
>Informs only if this node is Cycle master.
Isochronous cycle too long
Node occupied longer time than MAX_DATA_TIME.
>Need to issue “Bus reset”.
INT8
INT9
Bus occupancy violation
Received Asynchronous packet addressed to self-node normally, and
stored data at ASYNC receive specific buffer.
Asynchronous packet received
Header byte of source packet output from CPIF at transmitting
MPSG2 -TS is not ‘47h’.
INT10
CPIF output header is no 47h (Transmit)
>Valid only when transmitting MPSG2-TS.
INT11
INT12
Data length short error
Data length long error
Receive packet data length is shorter than data-length of packet header.
Receive packet data length is longer than data-length of packet header.
>Store only data indicated by data-length value to buffer.
Detected format error in packet received.
Occurred convention failure of packet format like Reserved range is not
‘0’.
INT13
Packet format error
>Delete packet received.
Detected CRC error in the header of packet received.
>Delete packet received.
INT14
INT15
INT16
INT17
Header CRC error
Detected CRC error in the data range of packet received.
>Do not delete packet received.
Data CRC error
ASYNC receive specific buffer is full.
>Delete following packet received.
Asynchronous receive FIFO full
Asynchronous packet send
Completed sending Asynchronous packet by issueing instruction.
CGMS or TSCH information input from TSP IC I/F was not consistent
with the souce packet input just before.
INT18
INT19
Input CGMS or TSCH changed
Acknowledge missing
Not returned Acknowledge packet in correspondance with Asynchronous
packet of non-broadcast sent from self-node within specified limit.
INT20
INT21
INT22
Acknowledge send
Completed sending Acknowledge packet.
Changede EMI data or ODD/EVEN value of received Isochronous
packet.
Receive EMI or ODD/EVEN changed
First packet received
Received the first packet after setting receive ISO channel.
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Interrupt
INT23
Interrupt Item
Description
Received cycle start packet normally when self node is not root
> Isochronous cycle starts.
Set ISO cycle Bit (Bit12) of flag & status register (address 02h) at ‘1’
simaltaneously with this interrupt report.
Cycle start packet received
INT24
INT25
INT26
Cycle start packet send
Physical packet send
Completed to send Cycle start packet when self node is root.
Completed to send Physical packet.
Extended PHY packet received
Received Extended PHY packet normally.
Received Physical configuration packet normally.
> Reflect to Physical register#01(address Phy/Link-reg 02h) and switch
to specified performance automatically.
Physical configuration packet
received
INT27
Received Link-on packet addressed to self-node normally.
> Assert LINKON terminal output simultaneously.
INT28
INT29
INT30
Link on packet received
Self-ID packet received
Receive late occurred
Received Self -ID packet normally.
Store data at ASYNC receive specific buffer.
Receive-late was occured.
Delete packet received.
Though Instruction was issued, it was not accepted bec ause the content
was not appropriate for this device.
e.g.) >Issued “Remove sleep” (02h) instruction in spite of not in sleep
condition.
INT31
INT32
Instruction abort (State)
Transmit late occurred
>Issued “Instruction suspend”(62h) instruction without instruction
to be stopped.
>Used undefine operand against issued instruction.
>Issued instruction was undefined.
etc.
Transmit-late was occured.
>Delete packet transmitted.
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Chapter 11 Operation
This chapter explains the operation of this device and displays the examples of control flow.
11.1. Initialization
11.2. Self-ID Packet Receiving
11.3. Asynchronous Packet Transmitting
11.4. Asynchronous Packet Receiving
11.5. Isochronous Packet Transmitting
11.6. Isochronous Packet Receiving
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11.1. Initialization
The example of control flow from the system power on to the packet transmitting/ receiving possible state is shown below.
In this examle, the device is not operated with cable power supply before turning on the power of system.
<Host>
<Device>
System power ON
START
Power CPS terminal to ‘L’, up to 500ns.
Power XRESET terminal to ‘L’, up to
400ns.
Inner reset and release reset.
Start internal PLL.
Receive BUS_RESET
Yes
No
Start bus reset process.
Read Bus reset detected (INT4)
interrupt.
Report Bus reset detected(INT4) interrupt (assert
XINT).
Complete bus reset process.
Read Bus reset complete (INT3)
interrupt.
Report Bus reset complete (INT3)
interrupt (assert XINT).
Packet
transmitting/ receiving
possible
Figure 11.1 Example of flow for Initialization
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11.2. Self-ID Packet Receiving
The example of control flow for receiving Self -ID packet is shown below.
11.2.1
11.2.2
Self-ID Packet Receive during Bus Reset Process
Self-ID Packet Receive after Ping Packet Transmitting
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11.2.1 Self-ID Packet Receive at Bus Reset Process
This section explains the receiving process of Self-ID packet.
The MB86617A device is capable of receiving self-ID packets that each mode transmit in the self-identity stage of bus reset
process. When ‘1’ is written to the s-ID store bit of mode-control register (refer to 7.1), the self-ID packet in the bus reset
process can be received and the data removing the logical inverse section is stored in the Asynchronous receive-FIFO and
Asynchronous transmit -FIFO (512 bytes maxixum). When the number of total data exceeds 512 bytes, the overflown data
are discarded.
Bus reset force-clears FIFO for Asynchronous receiving and FIFO for Asynchronous transmitting to store Self-ID packet.
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< Flow chart before bus reset completion
<Host>
MB86617A
<Device>
Start bus reset.
Read Bus reset detected (INT4) interrupt.
Report Bus reset detected (INT4)
interrupt. (assert XINT)
-ID store
‘0’
‘1’
Bus reset completed .
Yes
No
Read Bus reset completed (INT3)
interrupt.
Report Bus reset completed (INT3)
interrupt.
END
Set FIFO according to FIFO mode.
Clear Asynchronous receive buffer.
(Note 1)
recv busy bit=0
Store received Self-ID packet to
Asynchronous receive buffer.
Bus reset completed.
Yes
No
Read Bus reset completed (INT3)
interrupt.
Report Bus reset completed (INT3)
(assert XINT) interrupt.
recv busy bit=1
Figure 11.2.1.1 Flow example for Self-ID packet receiving before bus reset completion
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< Flow chart after bus reset completion
<Host>
MB86617A
<Device>
Read Self -ID?
Yes
No
Issue Asynchronous receive (03h)
instruction.
Prepare for reading received data.
Read one word from receive
Asynchronous data port.
Read one word of the received data
and increment the read pointer of
buffer.
data req bit
‘1’
‘0’
Issue Remove busy (04h) instruction.
Receive Remove busy(04h) instruction.
recv busy bit=0
Clear the receive Asynchronous buffer
and set FIFO according to FIFO mode.
(Note 2)
Figure 11.2.1.2 Flow example for Self-ID packet receiving after bus reset completed
Note1: When Asyn-FIFO sel (mode-control register[3]) is 1 and send/ rec (mode-control register [2]) is 1, Asynchronous receive
FIFO (256 byte) and Bridge FIFO (2048 byte) are used with combined as Asynchronous receive buffer.
In other case, Asynchronous receive FIFO (256 byte) and Asynchronous transmit FIFO (256 byte) are used with
combined.
Note2: When Asyn-FIFO sel is 1 and transmit/ rec is 1, Asynchronous transmitting FIFO (256 byte) and Bridge FIFO (2048 byt)
are cleared,
When Asyn-FIFO SEL is 1 and transmit/ rec is 0, Asynchronous receiving FIFO (256 byte) and Asynchronous
transmitting FIFO (256 byte) are cleared. Asynchronous transmit FIFO and Bridge FIFO are combined to be set in
Asynchronous transmit buffer. Set Asynchronous receive FIFO to Asynchronous receive buffer.
When Asyn-FIFO sel is 0, Asynchronous receive FIFO (256 byte) and Asynchronous transmit FIFO (256 byte) are cleared
and re-set Asynchronous receive FIFO to Asynchronous receive buffer, Asynchronous transmit FIFO to Asynchronous
transmit buffer.
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11.2.2 Self-ID Packet Receive after Transmitting Ping Packet Ping
Regardless of s-ID store bit setting in the mode-control register (refer to 7.1), the device receives self-ID packet after a ping
packet transmitted and stores the data removing logical inverse section in the Asynchronous receive-FIFO.
< Flow chart from transmitting of Pig packet to receiving Self-ID packet Ping
<Host>
<Device>
Store pin packet (two word) to be
transmitted in Asynchronous transmit
buffer.
Store ping packet to be transmitted in
Asynchronous receive buffer.
Issue Send PHY packet(21h)
Issue instruction.
Receive Transmit PHY packet (21h)instruction.
Read Asynchronous transmit buffer.
Arbitration procedure
Arbitration result
Won
Lost
Transmit Ping packet.
Read Physical packet send interrupt
(INT25)
Report Physical packet send interrupt (INT25)
(assert XINT).
Store received Self-ID packet in
Asynchronous receive buffer.
recv busy=1
Read Self -ID packet received interrupt
(INT29)
Report Self-ID packet received
interrupt(INT29) (assert XINT)
Figure 11.2.2.1 Flow example of operation from Pin packet transmitting to Self -ID packet receiving
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< Flow chart after receiving Self-ID packet
<Host>
MB86617A
<Device>
Issue Asynchronous receive (03h)
instruction.
Prepare for reading received data
Read the data of one word from
receive Asynchronous data port.
Read one word of received data and
increment the read pointer
Read flag & status register.
1
data req bit
0
Issue Remove busy (04h) instruction.
Receive Remove busy (04h) instruction.
FIFO remote mode for receiving
completed.
recv busy bit=0
Figure 11.2.2.2 Flow example after receiving Self-ID packet.
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11.3. Asynchronous Packet Transmitting
The example of control flow for transmitting of Asynchronous packet is shown below.
< Flow chart before storing transmitting data into Asynchronous transmit FIFO
<Host>
<Device>
Write data for 1 word for
Write one word the data to be
transmitted in Asynchronous transmit
data port.
Asynchronous transmit buffer and
increment the write pointer.
Number of residual transfer byte =
Number of residual transfer byte
–(minus) 2.
Number of residual transfer
byte > 0
Figure 11.3.1 Flow chart before storing transmitting data in Asynchronous transmit FIFO
Note1: Store the data to be transmit previously in Asynchronous transmit FIFO.
Note2: If the transmitting length is below the digit of quadret, write “0” there up to quadret unit.
Note3: The device can automatically attaches CRC code.
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< Flow chart after storing transmitting data into Asynchronous transmit FIFO
<Host>
<Device>
Receive Asynchronous transmit (31h) instruction.
Issue Asynchronous transmit (31h) instruction.
Read Asynchronous transmit buffer.
Arbitration procedure
Arbitration result
Won
Lost
Transmit Asynchronous packet.
After the transfer of DATA_END,
release bus and wait Asynchronous
Acknowledge received?
Yes
No
Store receive Acknowledge packet in
receive Acknowledge indication
register.
Read Asynchronous packet transmit
(INT17) interrupt.
Report Asynchronous packet send
(INT17) interrupt (assert XINT).
Read Acknowledge missing (INT20)
interrupt.
Report Acknowledge missing (INT20)
interrupt (assert XINT).
Figure 11.3.2 Flow chart after storing transmitting data in Asynchronous transmit FIFO
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11.4. Asynchronous Packet Receiving
The example of control flow for receiving Asynchronous packet is shown below.
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< Flow chart for received data before storing in Asynchronous receive FIFO
<Host>
<Device>
Receive packet to self-node.
Check Header CRC.
NG
OK
Report Header CRC Error(INT14)
Read Header CRC Error (INT14)
interrupt.
interrupt and duscard received packet.
Packet receiving process
completed
recv busy bit
‘0’
‘1’
Transmit “Ack_busy_X” and
discard received packet.
Packet receiving process
Store Asynchronous packet into
Async hronous receive buffer.
Transmit Acknowledge packet
Receive buffer=full
No
Yes
Read Asynchronous Receive FIFO
Report Asynchronous Receive FIFO full
(INT16) interrupt(assert XINT).
full(INT16)
Read Asynchronous packet
received(INT9)
Report Asynchronous packet receive
(INT9) interrupt(assert XINT).
recv busy bit=1
Packet receiving process
completed
Figure 11.4.1 Flow example for received data before storing in Asynchronous receive FIFO
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< Flow chart for received data after storing in Asynchronous receive FIFO
<Host>
<Device>
Issue Asynchronous receive(03h)
instruction.
Prepare for reading received data.
Read 1 word of the data from receive
Asynchronous data port
Read 1 word of received data and
increment read pointer of receive
buffer.
Read flag & status register.
1
data req bit
0
Issue Remove busy(04h)
instruction
Receive Remove busy(04h) instruction.
Receive FIFO read mode completed.
recv busybit=0
Figure 11.4.2 Flow chart for received data after storing in Asynchronous receive FIFO
Note1: If the length of received data is below quadret digid, it is stored by quadret unit????.
Note2: CRC code is not included in the data.
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11.5. Isochronous Packet Transmitting
The example of control flow for transmitting Isochronous packet is shown below.
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<Host>
<Device>
Set necessary data to registers such as
Bridg and TSPIF(Note).
Set value to registers such as Bridge and
TSPIF.
Input the source packet data and clock
into TSPIF port.
Store source packet in FIFO at TSPIF.
Transmit source packet to CP LSI.
Receive processed source packet from
CP LSI and store it in FIFO at Bridge.
Isocycle
Yes
No
Arbitration procedure
Arbitration result
Won
Lost
Transmit Late evaluation
Transmit Late
Yes
Read Transmit late occurred (INT32)
interrupt.
Report Transmit late occurred (INT32)
interrupt(assert XINT).
Discard source packet and transmit
empty packet.
Connect source packet according to
register setting and transmit.
Figure 11.5 Flow example for transmitting Isochronous packet
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(Note)Register and bit necessary for transmitting are as follows.
Data
Address
MPEG-TS
DSS
00h
TSPSB=0, CPSB=0
14h,16h
18h,1Ah
34h
Set value of transmit Offset(Ach).
Set value of transmit Offset (Bch)
DBSA=06h, FNA=3h
DBSA=09h, FNA=2h
36h
TXFMTA=20h, TXCHA(Iso channel No.)
DBSB=06h, FNB=3h
TXFMTA=21h, TXCHA(Iso channel No.)
DBSB=09h, FNB=2h
38h
3Ah
TXFMTB=20h, TXCHB(Iso channel No.)
Set criteria for Late packet (Ach).
Set criteria for Late packet (Bch).
TXFMTB=21h, TXCHB(Iso channel No.)
40h
42h
Set at Ach transmitting.
TXSTA=1, TFA, TXFMTA=1,
IDSIZEA=1(DSS130)
Set at Ach transmitting.
TXSTA=1, TFA
10h
12h
Set at Bch transmitting.
TXSTB=1, TFB, TXFMTB=1,
IDSIZEB=1(DSS130)
Set at Bch transmitting.
TXSTB=1, TFB
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11.6. Isochronous Packet Receiving
The example of control flow for receiving Isochronous packet is shown below.
<Host>
<Device>
Set necessary data to registers such as
Bridg and TSPIF.
Set value to registers such as Bridge and
TSPIF(Note).
Receive Iso packet.
Store source packet in FIFO at Bridge.
Transmit source packet to CP LSI.
Receive processed source packet from
CP LSI and store it in FIFO at TSPIF.
Receive Late evaluation
Receive Late
Yes
No
Read Receive late occurred (INT30)
interrupt.
Report Receive late occurred(INT30)
interrupt(assert XINT).
Discard source packet.
Output source packet from the TSPIF port
when the value of source packet header
equals to the value of cycle timer.
Figure 11.6 Flow example for transmitting Isochronous packet
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(Note)Register and bit necessary for receiving are as follows.
Data
DSS
Address
MPEG-TS
DV
00h
TSPSB=0, CPSB=0
TSEN=1,
DSSEN=1,
DVEN=1,
Set
TV1A,TV1B,TV2A,TV2B Set
TV1A,TV1B,TV2A,TV2B Set
TV1A,TV1B,TV2A,TV2B
1Ch
according to Ch received and according to Ch received and according to Ch received and
port.
port.
port.
40h
42h
Set criteria for Late packet (Ach).
Set criteria for Late packet (Bch).
-
-
Ach received : RXSTA=1h, RXCHA(Iso channel No.)
Bch received : RXSTB=1h, RXCHB(Iso channel No.)
3Ch
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Chapter 12 System Configuration
This chapter explains the system configuration of this chip.
12.1. Recommended Connection for 1934 Port (for one port)
12.2. Recommended Connection for Cable Power Supply
12.3. Recommended Connection for Build-in PLL Loop Filter
12.4. Configuration of Feedback Circuit at Crystal Oscillator
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12.1. Recommended Connection for 1934 Port (for one port)
The example of recommended connection of 1934 port terminal for one port is shown below.
1 F
56
56
56
56
5.1k
250pF
5.1k ｱ1%
Figure 12.1 Recommended connection for 1934 port (for one port)
For unused 1394 port, TPBIAS should be open and TPA, XTPA, TPB and XTPB should be be connected to GND.
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12.2 Recommended Connection for Cable Power Supply
The example of recommended connection of cable power supply for 1394 cable is shown below.
Power
Cable
(max 33V)
510KW ±5%
CPS
91KW ±5%
2.2uF
Figure 12.2 Recommended connection for cable power supply
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12.3. Recommended Connection for Build-in PLL Loop Filter
The example of recommended connection for build-in PLL loop filter is shown below.
RF
FIL
390W ±5%
5.1KW ±5%
3300pF ±5%
Figure 12.3 Recommended connection for build-in PLL loop filter
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12.4. Configuration of Feedback Circuit at Crystal Oscillator
The example of configuration of feedback circuit at crystal oscillator is shown below.
No outside resistance is needed because the feedback resistance is built -in.???
XO
XI
20pF
20pF
Figure 12.4 Configuration of feedback circuit at crystal oscillator
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