Cypress Computer Hardware STK14C88 5 User Manual

STK14C88-5  
256 Kbit (32K x 8) AutoStore nvSRAM  
Features  
Functional Description  
35 ns and 45 ns access times  
The Cypress STK14C88-5 is a fast static RAM with a nonvolatile  
element in each memory cell. The embedded nonvolatile  
Hands off automatic STORE on power down with external 68  
µF capacitor  
elements incorporate QuantumTrap technology producing the  
world’s most reliable nonvolatile memory. The SRAM provides  
unlimited read and write cycles, while independent, nonvolatile  
data resides in the highly reliable QuantumTrap cell. Data  
transfers from the SRAM to the nonvolatile elements (the  
STORE operation) takes place automatically at power down. On  
power up, data is restored to the SRAM (the RECALL operation)  
from the nonvolatile memory. Both the STORE and RECALL  
operations are also available under software control. A hardware  
STORE is initiated with the HSB pin.  
STORE to QuantumTrap™ nonvolatile elements is initiated by  
software, hardware, or AutoStore™ on power down  
RECALL to SRAM initiated by software or power up  
Unlimited READ, WRITE, and RECALL cycles  
1,000,000 STORE cycles to QuantumTrap  
100 year data retention to QuantumTrap  
Single 5V+10% operation  
Military temperature  
32-pin (300 mil) CDIP and LCC (450 mil) packages  
Logic Block Diagram  
V
CC  
V
CAP  
Quantum Trap  
512 X 512  
POWER  
CONTROL  
A5  
STORE  
A6  
A7  
A8  
RECALL  
STORE/  
RECALL  
CONTROL  
STATIC RAM  
ARRAY  
512 X 512  
HSB  
A9  
A11  
A12  
A13  
A14  
SOFTWARE  
DETECT  
A13  
-A0  
DQ0  
COLUMN I/O  
DQ1  
DQ2  
DQ3  
COLUMN DEC  
DQ4  
DQ5  
A0  
A4  
A10  
A1  
A3  
A2  
DQ6  
DQ7  
OE  
CE  
WE  
Cypress Semiconductor Corporation  
Document Number: 001-51038 Rev. **  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised March 02, 2009  
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STK14C88-5  
having a capacitor of between 68uF and 220uF (+ 20%) rated at  
Device Operation  
6V should be provided. The voltage on the V  
pin is driven to  
CAP  
5V by a charge pump internal to the chip. A pull up is placed on  
WE to hold it inactive during power up.  
The STK14C88-5 nvSRAM is made up of two functional compo-  
nents paired in the same physical cell. These are an SRAM  
memory cell and a nonvolatile QuantumTrap cell. The SRAM  
memory cell operates as a standard fast static RAM. Data in the  
SRAM is transferred to the nonvolatile cell (the STORE  
operation) or from the nonvolatile cell to SRAM (the RECALL  
operation). This unique architecture enables the storage and  
recall of all cells in parallel. During the STORE and RECALL  
operations, SRAM READ and WRITE operations are inhibited.  
The STK14C88-5 supports unlimited reads and writes similar to  
a typical SRAM. In addition, it provides unlimited RECALL opera-  
tions from the nonvolatile cells and up to one million STORE  
operations.  
Figure 3. AutoStore Mode  
SRAM Read  
The STK14C88-5 performs a READ cycle whenever CE and OE  
are LOW while WE and HSB are HIGH. The address specified  
on pins A  
determines the 32,768 data bytes accessed. When  
0–14  
the READ is initiated by an address transition, the outputs are  
valid after a delay of t (READ cycle 1). If the READ is initiated  
AA  
by CE or OE, the outputs are valid at t  
or at t  
, whichever  
ACE  
DOE  
is later (READ cycle 2). The data outputs repeatedly respond to  
address changes within the t access time without the need for  
AA  
transitions on any control input pins, and remains valid until  
another address change or until CE or OE is brought HIGH, or  
WE or HSB is brought LOW.  
In system power mode, both V and V  
are connected to the  
CAP  
CC  
SRAM Write  
+5V power supply without the 68 μF capacitor. In this mode, the  
AutoStore function of the STK14C88-5 operates on the stored  
system charge as power goes down. The user must, however,  
A WRITE cycle is performed whenever CE and WE are LOW and  
HSB is HIGH. The address inputs must be stable prior to entering  
the WRITE cycle and must remain stable until either CE or WE  
goes HIGH at the end of the cycle. The data on the common IO  
guarantee that V does not drop below 3.6V during the 10 ms  
CC  
STORE cycle.  
To reduce unnecessary nonvolatile stores, AutoStore and  
Hardware Store operations are ignored, unless at least one  
WRITE operation has taken place since the most recent STORE  
or RECALL cycle. Software initiated STORE cycles are  
performed regardless of whether a WRITE operation has taken  
place. An optional pull-up resistor is shown connected to HSB.  
The HSB signal is monitored by the system to detect if an  
AutoStore cycle is in progress.  
pins DQ  
are written into the memory if it has valid t , before  
0–7  
SD  
the end of a WE controlled WRITE or before the end of an CE  
controlled WRITE. Keep OE HIGH during the entire WRITE cycle  
to avoid data bus contention on common IO lines. If OE is left  
LOW, internal circuitry turns off the output buffers t  
goes LOW.  
after WE  
HZWE  
AutoStore Operation  
If the power supply drops faster than 20 us/volt before Vcc  
The STK14C88-5 stores data to nvSRAM using one of three  
storage operations:  
reaches V  
, then a 2.2 ohm resistor should be connected  
SWITCH  
between V and the system supply to avoid momentary excess  
CC  
of current between V and V  
.
1. Hardware store activated by HSB  
CC  
CAP  
2. Software store activated by an address sequence  
3. AutoStore on device power down  
AutoStore Inhibit mode  
If an automatic STORE on power loss is not required, then V  
CC  
AutoStore operation is a unique feature of QuantumTrap  
technology and is enabled by default on the STK14C88-5.  
is tied to ground and + 5V is applied to V  
(Figure 4). This is  
CAP  
the AutoStore Inhibit mode, where the AutoStore function is  
disabled. If the STK14C88-5 is operated in this configuration,  
During normal operation, the device draws current from V to  
CC  
charge a capacitor connected to the V  
pin. This stored  
CAP  
references to V  
are changed to V  
throughout this data  
CC  
CAP  
charge is used by the chip to perform a single STORE operation.  
If the voltage on the V pin drops below V , the part  
sheet. In this mode, STORE operations are triggered through  
software control or the HSB pin. To enable or disable Autostore  
using an I/O port pin see “” on page 5. It is not permissible to  
change between these three options” on the fly”.  
CC  
SWITCH  
automatically disconnects the V  
pin from V . A STORE  
CAP  
CC  
operation is initiated with power provided by the V  
capacitor.  
CAP  
Figure 3 shows the proper connection of the storage capacitor  
(V ) for automatic store operation. A charge storage capacitor  
CAP  
Document Number: 001-51038 Rev. **  
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STK14C88-5  
Figure 4. AutoStore Inhibit Mode  
If the STK14C88-5 is in a WRITE state at the end of power up  
RECALL, the SRAM data is corrupted. To help avoid this  
situation, a 10 Kohm resistor is connected either between WE  
and system V or between CE and system V  
.
CC  
CC  
Software STORE  
Data is transferred from the SRAM to the nonvolatile memory by  
a software address sequence. The STK14C88-5 software  
STORE cycle is initiated by executing sequential CE controlled  
READ cycles from six specific address locations in exact order.  
During the STORE cycle, an erase of the previous nonvolatile  
data is first performed followed by a program of the nonvolatile  
elements. When a STORE cycle is initiated, input and output are  
disabled until the cycle is completed.  
Because a sequence of READs from specific addresses is used  
for STORE initiation, it is important that no other READ or WRITE  
accesses intervene in the sequence. If they intervene, the  
sequence is aborted and no STORE or RECALL takes place.  
To initiate the software STORE cycle, the following READ  
sequence is performed:  
1. Read address 0x0E38, Valid READ  
2. Read address 0x31C7, Valid READ  
3. Read address 0x03E0, Valid READ  
4. Read address 0x3C1F, Valid READ  
5. Read address 0x303F, Valid READ  
6. Read address 0x0FC0, Initiate STORE cycle  
Hardware STORE (HSB) Operation  
The STK14C88-5 provides the HSB pin for controlling and  
acknowledging the STORE operations. The HSB pin is used to  
request a hardware STORE cycle. When the HSB pin is driven  
The software sequence is clocked with CE controlled READs.  
When the sixth address in the sequence is entered, the STORE  
cycle commences and the chip is disabled. It is important that  
READ cycles and not WRITE cycles are used in the sequence.  
It is not necessary that OE is LOW for a valid sequence. After the  
LOW, the STK14C88-5 conditionally initiates  
a
STORE  
operation after t . An actual STORE cycle only begins if a  
DELAY  
WRITE to the SRAM takes place since the last STORE or  
RECALL cycle. The HSB pin also acts as an open drain driver  
that is internally driven LOW to indicate a busy condition, while  
the STORE (initiated by any means) is in progress. Pull up this  
t
cycle time is fulfilled, the SRAM is again activated for  
READ and WRITE operation.  
STORE  
pin with an external 10K ohm resistor to V  
a driver.  
if HSB is used as  
CAP  
Software RECALL  
SRAM READ and WRITE operations, that are in progress when  
HSB is driven LOW by any means, are given time to complete  
before the STORE operation is initiated. After HSB goes LOW,  
Data is transferred from the nonvolatile memory to the SRAM by  
a software address sequence. A software RECALL cycle is  
initiated with a sequence of READ operations in a manner similar  
to the software STORE initiation. To initiate the RECALL cycle,  
the following sequence of CE controlled READ operations is  
performed:  
the STK14C88-5 continues SRAM operations for t  
. During  
DELAY  
t
, multiple SRAM READ operations take place. If a WRITE  
DELAY  
is in progress when HSB is pulled LOW, it allows a time, t  
DELAY  
to complete. However, any SRAM WRITE cycles requested after  
HSB goes LOW are inhibited until HSB returns HIGH.  
1. Read address 0x0E38, Valid READ  
2. Read address 0x31C7, Valid READ  
3. Read address 0x03E0, Valid READ  
4. Read address 0x3C1F, Valid READ  
5. Read address 0x303F, Valid READ  
6. Read address 0x0C63, Initiate RECALL cycle  
During any STORE operation, regardless of how it is initiated,  
the STK14C88-5 continues to drive the HSB pin LOW, releasing  
it only when the STORE is complete. After completing the  
STORE operation, the STK14C88-5 remains disabled until the  
HSB pin returns HIGH.  
If HSB is not used, it is left unconnected.  
Internally, RECALL is a two step procedure. First, the SRAM data  
is cleared, and then the nonvolatile information is transferred into  
Hardware RECALL (Power Up)  
the SRAM cells. After the t  
cycle time, the SRAM is once  
During power up or after any low power condition (V  
<
RECALL  
CC  
again ready for READ and WRITE operations. The RECALL  
operation does not alter the data in the nonvolatile elements. The  
nonvolatile data can be recalled an unlimited number of times.  
V
), an internal RECALL request is latched. When V  
RESET  
CC  
once again exceeds the sense voltage of V  
cycle is automatically initiated and takes t  
, a RECALL  
SWITCH  
to complete.  
HRECALL  
Document Number: 001-51038 Rev. **  
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STK14C88-5  
Figure 5. Current Versus Cycle Time (READ)  
Data Protection  
The STK14C88-5 protects data from corruption during low  
voltage conditions by inhibiting all externally initiated STORE  
and WRITE operations. The low voltage condition is detected  
when V  
is less than V  
. If the STK14C88-5 is in a  
CC  
SWITCH  
WRITE mode (both CE and WE are low) at power up after a  
RECALL or after a STORE, the WRITE is inhibited until a  
negative transition on CE or WE is detected. This protects  
against inadvertent writes during power up or brown out condi-  
tions.  
Noise Considerations  
The STK14C88-5 is a high speed memory. It must have a high  
frequency bypass capacitor of approximately 0.1 µF connected  
between V and V  
using leads and traces that are as short  
CC  
SS,  
as possible. As with all high speed CMOS ICs, careful routing of  
power, ground, and signals reduce circuit noise.  
Figure 6. Current Versus Cycle Time (WRITE)  
Hardware Protect  
The STK14C88-5 offers hardware protection against inadvertent  
STORE operation and SRAM WRITEs during low voltage condi-  
tions. When V  
<V  
, all externally initiated STORE  
CAP  
SWITCH  
operations and SRAM WRITEs are inhibited. AutoStore can be  
completely disabled by tying VCC to ground and applying + 5V  
to V  
. This is the AutoStore Inhibit mode; in this mode,  
CAP  
STOREs are only initiated by explicit request using either the  
software sequence or the HSB pin.  
Low Average Active Power  
CMOS technology provides the STK14C88-5 the benefit of  
drawing significantly less current when it is cycled at times longer  
than 50 ns. Figure 5 and Figure 6 shows the relationship  
between I and READ or WRITE cycle time. Worst case current  
CC  
Preventing Store  
The STORE function is disabled by holding HSB high with a  
driver capable of sourcing 30 mA at a V  
because it has to overpower the internal pull down device. This  
device drives HSB LOW for 20 μs at the onset of a STORE.  
When the STK14C88-5 is connected for AutoStore operation  
consumption is shown for both CMOS and TTL input levels  
(commercial temperature range, VCC = 5.5V, 100% duty cycle  
on chip enable). Only standby current is drawn when the chip is  
disabled. The overall average current drawn by the STK14C88-5  
depends on the following items:  
of at least 2.2V,  
OH  
The duty cycle of chip enable  
The overall cycle rate for accesses  
The ratio of READs to WRITEs  
CMOS versus TTL input levels  
The operating temperature  
(system V connected to V and a 68 μF capacitor on V )  
CC  
crosses V  
CC  
CAP  
and V  
on the way down, the STK14C88-5  
CC  
SWITCH  
attempts to pull HSB LOW. If HSB does not actually get below  
V , the part stops trying to pull HSB LOW and abort the STORE  
IL  
attempt.  
The V level  
CC  
IO loading  
Document Number: 001-51038 Rev. **  
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STK14C88-5  
manufacturing test to ensure these system routines work  
consistently.  
Best Practices  
nvSRAM products have been used effectively for over 15 years.  
While ease of use is one of the product’s main system values,  
experience gained working with hundreds of applications has  
resulted in the following suggestions as best practices:  
Power up boot firmware routines should rewrite the nvSRAM  
into the desired state. While the nvSRAM is shipped in a preset  
state, best practice is to again rewrite the nvSRAM into the  
desired state as a safeguard against events that might flip the  
bit inadvertently (program bugs, incoming inspection routines,  
and so on).  
The nonvolatile cells in an nvSRAM are programmed on the  
test floor during final test and quality assurance. Incoming  
inspection routines at customer or contract manufacturer’s  
sitessometimesreprogramthesevalues. FinalNVpatternsare  
typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End  
product’s firmware should not assume an NV array is in a set  
programmed state. Routines that check memory content  
values to determine first time system configuration, cold or  
warm boot status, and so on should always program a unique  
NV pattern (for example, complex 4-byte pattern of 46 E6 49  
53 hex or more random bytes) as part of the final system  
TheV  
valuespecifiedinthisdatasheetincludesaminimum  
CAP  
and a maximum value size. Best practice is to meet this  
requirementandnotexceedthemaximumV valuebecause  
CAP  
the higher inrush currents may reduce the reliability of the  
internal pass transistor. Customers that want to use a larger  
V
value to make sure there is extra store charge should  
CAP  
discuss their V  
size selection with Cypress to understand  
CAP  
any impact on the V  
period.  
voltage level at the end of a t  
CAP  
RECALL  
Table 1. Hardware Mode Selection  
CE  
H
WE  
X
HSB  
H
A13–A0  
Mode  
IO  
Power  
X
X
Not Selected  
Read SRAM  
Output High Z  
Output Data  
Standby  
L
H
H
Active  
L
L
H
L
X
X
Write SRAM  
Input Data  
Active  
X
X
Nonvolatile STORE Output High Z  
I
CC2  
L
H
H
0x0E38  
0x31C7  
0x03E0  
0x3C1F  
0x303F  
0x0FC0  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Active I  
CC2  
Nonvolatile STORE Output High Z  
L
H
H
0x0E38  
0x31C7  
0x03E0  
0x3C1F  
0x303F  
0x0C63  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Active  
Nonvolatile RECALL Output High Z  
Notes  
1. I/O state assumes OE < V . Activation of nonvolatile cycles does not depend on state of OE.  
IL  
2. HSB STORE operation occurs only if an SRAM WRITE has been done since the last nonvolatile cycle. After the STORE (if any) completes, the part goes into standby  
mode, inhibiting all operations until HSB rises.  
3. CE and OE LOW and WE HIGH for output behavior.  
4. The six consecutive addresses must be in the order listed. WE must be high during all six consecutive CE controlled cycles to enable a nonvolatile cycle.  
5. While there are 15 addresses on the STK14C88-5, only the lower 14 are used to control software modes.  
Document Number: 001-51038 Rev. **  
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STK14C88-5  
Voltage on DQ or HSB .......................–0.5V to Vcc + 0.5V  
Maximum Ratings  
0-7  
Power Dissipation.......................................................... 1.0W  
DC output Current (1 output at a time, 1s duration) .... 15 mA  
Exceeding maximum ratings may shorten the useful life of the  
device. These user guidelines are not tested.  
Storage Temperature ................................. –65°C to +150°C  
Temperature under Bias ............................. –55°C to +125°C  
Voltage on Input Relative to GND.....................–0.5V to 7.0V  
Operating Range  
Range  
Military  
Ambient Temperature  
V
CC  
-55°C to +125°C  
4.5V to 5.5V  
Voltage on Input Relative to Vss............0.6V to V + 0.5V  
CC  
DC Electrical Characteristics  
Over the operating range (V = 4.5V to 5.5V)  
CC  
Parameter  
Description  
Average V Current  
Test Conditions  
Min  
Max  
Unit  
I
t
t
= 35 ns  
= 45 ns  
85  
70  
mA  
mA  
CC1  
CC  
RC  
RC  
Dependent on output loading and cycle rate. Values obtained  
without output loads.  
I
= 0 mA.  
OUT  
I
I
Average V Current  
during STORE  
All Inputs Do Not Care, V = Max  
3
mA  
mA  
CC2  
CC  
CC  
Average current for duration t  
STORE  
Average V Current at  
WE > (V – 0.2V). All other inputs cycling.  
10  
CC3  
CC  
CC  
t
= 200 ns, 5V, 25°C  
Dependent on output loading and cycle rate. Values obtained  
RC  
Typical  
without output loads.  
I
I
Average V  
during AutoStore Cycle  
Current  
All Inputs Do Not Care, V = Max  
2
mA  
CC4  
CAP  
CC  
Average current for duration t  
STORE  
V
Standby Current  
t
t
= 35 ns, CE > V  
= 45 ns, CE > V  
26  
23  
mA  
mA  
CC  
RC  
RC  
IH  
IH  
SB1  
(Standby, Cycling TTL  
Input Levels)  
V
Standby Current  
CE > (V – 0.2V). All others V < 0.2V or > (V – 0.2V).  
Standby current level after nonvolatile cycle is complete.  
Inputs are static. f = 0 MHz.  
1.5  
mA  
I
CC  
CC  
IN  
CC  
SB2  
I
I
Input Leakage Current  
V
V
= Max, V < V < V  
CC  
-1  
-5  
+1  
+5  
μA  
μA  
IX  
CC  
CC  
SS  
IN  
Off State Output Leakage  
Current  
= Max, V < V < V , CE or OE > V or WE < V  
SS IN CC IH IL  
OZ  
V
V
Input HIGH Voltage  
2.2  
V
0.5  
+
V
V
IH  
IL  
CC  
Input LOW Voltage  
V
0.8  
SS  
0.5  
V
V
V
Output HIGH Voltage  
Output LOW Voltage  
I
I
I
= –4 mA  
= 8 mA  
= 3 mA  
2.4  
V
V
V
OH  
OL  
BL  
OUT  
OUT  
OUT  
0.4  
0.4  
Logic ‘0’ Voltage on HSB  
Output  
V
Storage Capacitor  
Between V  
pin and Vss, 6V rated. 68 µF +20% nom.  
CAP  
54  
260  
uF  
CAP  
Data Retention and Endurance  
Parameter  
Description  
Min  
100  
Unit  
DATA  
Data Retention  
Years  
K
R
NV  
Nonvolatile STORE Operations  
1,000  
C
Notes  
6.  
V
reference levels throughout this data sheet refer to V if that is where the power supply connection is made, or V  
if V is connected to ground.  
CC  
CC  
CAP CC  
7. CE > V does not produce standby current levels until any nonvolatile cycle in progress has timed out.  
IH  
Document Number: 001-51038 Rev. **  
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STK14C88-5  
Capacitance  
In the following table, the capacitance parameters are listed.  
Parameter  
Description  
Input Capacitance  
Output Capacitance  
Test Conditions  
Max  
Unit  
pF  
C
T = 25°C, f = 1 MHz,  
CC  
5
7
IN  
A
V
= 0 to 3.0V  
C
pF  
OUT  
Thermal Resistance  
In the following table, the thermal resistance parameters are listed.  
Parameter  
Description  
Test Conditions  
32-CDIP  
32-LCC  
Unit  
ΘJA  
Thermal Resistance  
(Junction to Ambient)  
Test conditions follow standard test methods  
and procedures for measuring thermal  
impedance, per EIA / JESD51.  
TBD  
TBD  
°C/W  
ΘJC  
Thermal Resistance  
(Junction to Case)  
TBD  
TBD  
°C/W  
Figure 7. AC Test Loads  
For Tri-state Specs  
R1 963  
Ω
R1 963Ω  
5.0V  
5.0V  
Output  
Output  
R2  
512  
R2  
512  
30 pF  
5 pF  
Ω
Ω
AC Test Conditions  
Input Pulse Levels....................................................0V to 3V  
Input Rise and Fall Times (10% - 90%)........................ <5 ns  
Input and Output Timing Reference Levels.................... 1.5V  
Note  
8. These parameters are guaranteed by design and are not tested.  
Document Number: 001-51038 Rev. **  
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STK14C88-5  
AC Switching Characteristics  
SRAM Read Cycle  
Parameter  
35 ns  
45 ns  
Description  
Unit  
Cypress  
Alt  
Min  
Max  
Min  
Max  
Parameter  
t
t
t
t
Chip Enable Access Time  
Read Cycle Time  
35  
45  
ns  
ns  
ACE  
ELQV  
t
35  
45  
AVAV, ELEH  
AVQV  
RC  
AA  
t
Address Access Time  
35  
15  
45  
20  
ns  
t
t
t
t
Output Enable to Data Valid  
ns  
ns  
DOE  
OHA  
GLQV  
AXQX  
Output Hold After Address Change  
5
5
5
5
t
t
t
t
t
t
t
t
t
t
t
t
t
Chip Enable to Output Active  
Chip Disable to Output Inactive  
Output Enable to Output Active  
Output Disable to Output Inactive  
Chip Enable to Power Active  
Chip Disable to Power Standby  
ns  
ns  
ns  
ns  
ns  
ns  
ELQX  
LZCE  
HZCE  
LZOE  
HZOE  
13  
13  
35  
15  
15  
45  
EHQZ  
0
0
0
0
GLQX  
GHQZ  
ELICCH  
EHICCL  
PU  
PD  
Switching Waveforms  
Figure 8. SRAM Read Cycle 1: Address Controlled  
W5&  
$''5(66  
W$$  
W2+$  
'4ꢀꢁ'$7$ꢀ287ꢂ  
'$7$ꢀ9$/,'  
[9]  
Figure 9. SRAM Read Cycle 2: CE and OE Controlled  
W5&  
$''5(66  
&(  
W$&(  
W3'  
W+=&(  
W/=&(  
2(  
W+=2(  
W'2(  
W/=2(  
'4ꢀꢁ'$7$ꢀ287ꢂ  
'$7$ꢀ9$/,'  
$&7,9(  
W38  
67$1'%<  
,&&  
Notes  
9. WE and HSB must be HIGH during SRAM Read cycles.  
10. Device is continuously selected with CE and OE both Low.  
11. Measured ±200 mV from steady state output voltage.  
Document Number: 001-51038 Rev. **  
Page 9 of 17  
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STK14C88-5  
SRAM Write Cycle  
Parameter  
35 ns  
45 ns  
Description  
Write Cycle Time  
Unit  
Cypress  
Alt  
Min  
Max  
Min  
Max  
Parameter  
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
35  
25  
25  
12  
0
45  
30  
30  
15  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
WC  
PWE  
SCE  
SD  
AVAV  
t
Write Pulse Width  
WLWH, WLEH  
t
Chip Enable To End of Write  
Data Setup to End of Write  
Data Hold After End of Write  
Address Setup to End of Write  
Address Setup to Start of Write  
Address Hold After End of Write  
Write Enable to Output Disable  
ELWH, ELEH  
t
DVWH, DVEH  
t
HD  
WHDX, EHDX  
t
25  
0
30  
0
AW  
SA  
AVWH, AVEH  
t
AVWL, AVEL  
t
0
0
HA  
WHAX, EHAX  
[11,12]  
13  
15  
t
t
WLQZ  
WHQX  
HZWE  
t
Output Active After End of Write  
5
5
ns  
LZWE  
Switching Waveforms  
Figure 10. SRAM Write Cycle 1: WE Controlled  
tWC  
ADDRESS  
CE  
tHA  
tSCE  
tAW  
tSA  
tPWE  
WE  
tHD  
tSD  
DATA VALID  
DATA IN  
tHZWE  
tLZWE  
HIGH IMPEDANCE  
PREVIOUS DATA  
DATA OUT  
Figure 11. SRAM Write Cycle 2: CE Controlled  
tWC  
ADDRESS  
tHA  
tSCE  
tSA  
CE  
WE  
tAW  
tPWE  
tSD  
tHD  
DATA IN  
DATA VALID  
HIGH IMPEDANCE  
DATA OUT  
Notes  
12. If WE is Low when CE goes Low, the outputs remain in the high impedance state.  
13. HSB must be high during SRAM WRITE cycles.  
14.  
CE or WE must be greater than V during address transitions.  
IH  
Document Number: 001-51038 Rev. **  
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STK14C88-5  
AutoStore or Power Up RECALL  
STK14C88-5  
Parameter  
Alt  
Description  
Unit  
Min  
Max  
t
t
t
Power up RECALL Duration  
STORE Cycle Duration  
550  
10  
μs  
ms  
μs  
t
t
t
RESTORE  
HLHZ  
HRECALL  
STORE  
DELAY  
t
Time Allowed to Complete SRAM Cycle  
1
HLQZ , BLQZ  
V
V
t
Low Voltage Trigger Level  
Low Voltage Reset Level  
4.0  
4.5  
3.6  
V
V
SWITCH  
RESET  
V
Rise Time  
150  
μs  
ns  
VCCRISE  
CC  
Low Voltage Trigger (V  
) to HSB low  
300  
t
SWITCH  
VSBL  
Switching Waveforms  
Figure 12. AutoStore/Power Up RECALL  
WE  
Notes  
15. t  
starts from the time V rises above V  
.
SWITCH  
HRECALL  
CC  
16. CE and OE low and WE high for output behavior.  
17. HSB is asserted low for 1us when V  
drops through V  
. If an SRAM WRITE has not taken place since the last nonvolatile cycle, HSB is released and no store  
CAP  
SWITCH  
takes place.  
Document Number: 001-51038 Rev. **  
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STK14C88-5  
Software Controlled STORE/RECALL Cycle  
The software controlled STORE/RECALL cycle follows.  
35 ns  
45 ns  
Parameter  
Alt  
Description  
Unit  
Max  
Min  
Max  
Min  
t
t
t
t
STORE/RECALL Initiation Cycle Time  
Address Setup Time  
35  
45  
ns  
ns  
ns  
ns  
t
t
t
AVAV  
RC  
0
0
AVEL  
ELEH  
ELAX  
SA  
Clock Pulse Width  
25  
20  
30  
20  
CW  
Address Hold Time  
t
t
HACE  
RECALL Duration  
20  
20  
μs  
RECALL  
Switching Waveforms  
Figure 13. CE Controlled Software STORE/RECALL Cycle  
tRC  
tRC  
ADDRESS # 1  
ADDRESS # 6  
ADDRESS  
CE  
tSA  
tSCE  
tHACE  
OE  
t
STORE / tRECALL  
HIGH IMPEDANCE  
DATA VALID  
DATA VALID  
DQ (DATA)  
Notes  
18. The software sequence is clocked on the falling edge of CE without involving OE (double clocking aborts the sequence).  
19. The six consecutive addresses must be read in the order listed in the Mode Selection table. WE must be HIGH during all six consecutive cycles.  
Document Number: 001-51038 Rev. **  
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STK14C88-5  
Hardware STORE Cycle  
STK14C88-5  
Parameter  
Alt  
Description  
Unit  
Min  
Max  
t
t
t
Hardware STORE High to Inhibit Off  
700  
ns  
t
t
t
RECOVER, HHQX  
DHSB  
Hardware STORE Pulse Width  
15  
ns  
ns  
PHSB  
HLBL  
HLHX  
Hardware STORE Low to STORE Busy  
300  
Switching Waveforms  
Figure 14. Hardware STORE Cycle  
Note  
20. t  
is only applicable after t  
is complete.  
DHSB  
STORE  
Document Number: 001-51038 Rev. **  
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STK14C88-5  
Part Numbering Nomenclature  
STK14C88 - 5 C 35 M  
Temperature Range:  
M - Military (-55 to 125°C)  
Speed:  
35 - 35 ns  
45 - 45 ns  
Package:  
C = Ceramic 32-pin 300 mil DIP  
K = Ceramic 32-pin 300 mil DIP (Solder dip finish)  
L = Ceramic 32-pin LLC  
Retention / Endurance  
5 = Military (10 years or 105 cycles)  
Ordering Information  
Speed  
(ns)  
Operating  
Range  
Ordering Code  
Package Diagram  
Package Type  
35  
STK14C88-5C35M  
STK14C88-5K35M  
STK14C88-5L35M  
STK14C88-5C45M  
STK14C88-5K45M  
STK14C88-5L45M  
001-51694  
001-51694  
51-80068  
001-51694  
001-51694  
51-80068  
32-pin CDIP (300 mil)  
32-pin CDIP (300 mil)  
32-pin LCC (450 mil)  
32-pin CDIP (300 mil)  
32-pin CDIP (300 mil)  
32-pin LCC (450mil)  
Military  
45  
The above table contains Final information. Please contact your local Cypress sales representative for availability of these parts  
Document Number: 001-51038 Rev. **  
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STK14C88-5  
Package Diagram  
Figure 15. 32-Pin (300-Mil) Side Braze DIL (001-51694)  
001-51694 **  
Document Number: 001-51038 Rev. **  
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STK14C88-5  
Package Diagram (continued)  
Figure 16. 32-Pad (450-Mil) LCC (51-80068)  
51-80068-**  
Document Number: 001-51038 Rev. **  
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STK14C88-5  
Document History Page  
Document Title: STK14C88-5 256 Kbit (32K x 8) AutoStore nvSRAM  
Document Number: 001-51038  
Orig. of  
Change  
Submission  
Date  
Rev  
ECN No.  
Description of Change  
**  
2666844  
GVCH/PYRS  
03/02/09  
New data sheet  
Sales, Solutions, and Legal Information  
Worldwide Sales and Design Support  
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office  
closest to you, visit us at cypress.com/sales  
Products  
PSoC  
PSoC Solutions  
General  
Clocks & Buffers  
Wireless  
Low Power/Low Voltage  
Precision Analog  
LCD Drive  
Memories  
Image Sensors  
CAN 2.0b  
USB  
© Cypress Semiconductor Corporation, 2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any  
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,  
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical  
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems  
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),  
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,  
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress  
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without  
the express written permission of Cypress.  
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES  
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not  
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where  
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer  
assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Use may be limited by and subject to the applicable Cypress software license agreement.  
Document Number: 001-51038 Rev. **  
Revised March 02, 2009  
Page 17 of 17  
AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective  
holders.  
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