CY7C6431x
CY7C64345, CY7C6435x
enCoRe™ V Full Speed USB Controller
Features
■ Powerful Harvard Architecture Processor
❐ M8C processor speeds running up to 24 MHz
❐ Low power at high processing speeds
❐ Interrupt controller
■ Programmable Pin Configurations
❐ 25 mA sink current on all GPIO
❐ Pull Up, High Z, Open Drain, CMOS drive modes on all GPIO
❐ Configurable inputs on all GPIO
❐ 3.0V to 5.5V operating voltage without USB
❐ Operating voltage with USB enabled:
• 3.15 to 3.45V when supply voltage is around 3.3V
• 4.35 to 5.25V when supply voltage is around 5.0V
❐ Temperature range: 0°C to 70°C
❐ Low dropout voltage regulator for Port 1 pins. Programmable
to output 3.0, 2.5, or 1.8V at the I/O pins
❐ Selectable, regulated digital I/O on Port 1
• Configurable input threshold for Port 1
• 3.0V, 20 mA total Port 1 source current
• Hot-swappable
■ Flexible On-Chip Memory
❐ 5 mA strong drive mode on Ports 0 and 1
❐ Up to 32K Flash program storage
• 50,000 erase and write cycles
• Flexible protection modes
❐ Up to 2048 bytes SRAM data storage
❐ In-System Serial Programming (ISSP)
■ Full-Speed USB (12 Mbps)
❐ Eight unidirectional endpoints
❐ One bidirectional control endpoint
❐ USB 2.0 compliant
❐ Dedicated 512 bytes buffer
❐ No external crystal required
■ Complete Development Tools
❐ Free development tool (PSoC Designer™)
❐ Full featured, in-circuit emulator and programmer
❐ Full speed emulation
❐ Complex breakpoint structure
❐ 128K trace memory
■ Additional System Resources
❐ Configurable communication speeds
2
❐ I C slave
• Selectable to 50 kHz, 100 kHz, or 400 kHz
• Implementation requires no clock stretching
• Implementation during sleep modes with less than 100 μA
• Hardware address detection
❐ SPI master and SPI slave
• Configurable between 93.75 kHz and 12 MHz
❐ Three 16-bit timers
■ Precision, Programmable Clocking
❐ Crystal-less oscillator with support for an external crystal or
resonator
❐ Internal ±5.0% 6, 12, or 24 MHz main oscillator
• 0.25% accuracy with Oscillator Lock to USB data, no
external components required
❐ 8-bit ADC used to monitor battery voltage or other signals -
• Internal low speed oscillator at 32 kHz for watchdog and
sleep. The frequency range is 19 to 50 kHz with a 32 kHz
typical value
with external components
❐ Watchdog and sleep timers
❐ Integrated supervisory circuit
enCoRe V Block Diagram
Port 4
Port 3 Port 2 Port 1 Port 0 Prog. LDO
enCoRe V
CORE
System Bus
SRAM
2048 Bytes
SROM
Flash 32K
CPU Core
(M8C)
Sleep and
Watchdog
Interrupt
Controller
6/12/24 MHz Internal Main Oscillator
POR and LVD
I2C Slave/SPI
Full
Speed
USB
3 16-Bit
Timers
Master-Slave
System Resets
SYSTEM RESOURCES
Cypress Semiconductor Corporation
Document Number: 001-12394 Rev *G
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 30, 2009
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CY7C6431x
CY7C64345, CY7C6435x
Development Tools
PSoC Designer™ is a Microsoft® Windows-based, integrated
development environment for the enCoRe and PSoC devices.
The PSoC Designer IDE and application runs on Windows XP
and Windows Vista.
Assemblers. The assemblers allow assembly code to be
merged seamlessly with C code. Link libraries automatically use
absolute addressing or are compiled in relative mode, and linked
with other software modules to get absolute addressing.
This system provides design database management by project,
an integrated debugger with In-Circuit Emulator, in-system
programming support, and built-in support for third-party assem-
blers and C compilers.
C Language Compilers. C language compilers are available
that support the enCoRe and PSoC families of devices. The
products enable you to create complete C programs for the
PSoC family devices.
PSoC Designer also supports C language compilers developed
specifically for the devices in the enCoRe and PSoC families.
The optimizing C compilers provide all the features of C tailored
to the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
PSoC Designer Software Subsystems
Chip-Level View
Debugger
The chip-level view is a traditional integrated development
environment (IDE) based on PSoC Designer 4.4. You choose a
base device to work with and then select different onboard
analog and digital components called user modules that use the
PSoC blocks. Examples of user modules are ADCs, DACs,
Amplifiers, and Filters. You configure the user modules for your
chosen application and connect them to each other and to the
proper pins. Then you generate your project. This prepopulates
your project with APIs and libraries that you can use to program
your application.
PSoC Designer has a debug environment that provides
hardware in-circuit emulation, allowing you to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow the designer to read and
program flash, read and write data memory, read and write I/O
registers, read and write CPU registers, set and clear break-
points, and provide program run, halt, and step control. The
debugger also allows the designer to create a trace buffer of
registers and memory locations of interest.
Online Help System
The tool also supports easy development of multiple configura-
tions and dynamic reconfiguration. Dynamic reconfiguration
allows for changing configurations at run time.
The online help system displays online, context-sensitive help
for the user. Designed for procedural help and quick reference,
each functional subsystem has its own context-sensitive help.
This system also provides tutorials and links to FAQs and an
Online Support Forum to aid the designer in getting started.
System-Level View
The system-level view is a drag-and-drop visual embedded
system design environment based on PSoC Designer.
In-Circuit Emulator
Hybrid Designs
A low cost, high functionality ICE (In-Circuit Emulator) is
available for development support. This hardware has the
capability to program single devices.
You can begin in the system-level view, allow it to choose and
configure your user modules, routing, and generate code, then
switch to the chip-level view to gain complete control over
on-chip resources. All views of the project share common code
editor, builder, and common debug, emulation, and programming
tools.
The emulator consists of a base unit that connects to the PC by
way of a USB port. The base unit is universal and operates with
all enCoRe and PSoC devices. Emulation pods for each device
family are available separately. The emulation pod takes the
place of the PSoC device in the target board and performs full
speed (24 MHz) operation.
Code Generation Tools
PSoC Designer supports multiple third-party C compilers and
assemblers. The code generation tools work seamlessly within
the PSoC Designer interface and have been tested with a full
range of debugging tools. The choice is yours.
Document Number: 001-12394 Rev *G
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CY7C6431x
CY7C64345, CY7C6435x
Designing with PSoC Designer
The development process for the enCoRe V device differs from
that of a traditional fixed function microprocessor. Powerful
PSoC Designer tools get the core of your design up and running
in minutes instead of hours.
Generate, Verify, and Debug
When you are ready to test the hardware configuration or move
on to developing code for the project, you perform the “Generate
Configuration Files” step. This causes PSoC Designer to
generate source code that automatically configures the device to
your specification and provides the software for the system.
The development process can be summarized in the following
four steps:
1. Select Components
Both system-level and chip-level designs generate software
based on your design. The chip-level design provides application
programming interfaces (APIs) with high level functions to
control and respond to hardware events at run time and interrupt
service routines that you can adapt as needed. The system-level
design also generates a C main() program that completely
controls the chosen application and contains placeholders for
custom code at strategic positions allowing you to further refine
the software without disrupting the generated code.
2. Configure Components
3. Organize and Connect
4. Generate, Verify, and Debug
Select Components
The chip-level view provides a library of pre-built, pre-tested
hardware peripheral components. These components are called
“user modules.” User modules make selecting and implementing
peripheral devices simple, and come in analog, digital, and
mixed-signal varieties.
A complete code development environment allows you to
develop and customize your applications in C, assembly
language, or both.
The last step in the development process takes place inside
PSoC Designer’s Debugger (access by clicking the Connect
icon). PSoC Designer downloads the HEX image to the In-Circuit
Emulator (ICE) where it runs at full speed. PSoC Designer
debugging capabilities rival those of systems costing many times
more. In addition to traditional single-step, run-to-breakpoint and
watch-variable features, the debug interface provides a large
trace buffer and allows you to define complex breakpoint events
that include monitoring address and data bus values, memory
locations and external signals.
Configure Components
Each of the components you select establishes the basic register
settings that implement the selected function. They also provide
parameters and properties that allow you to tailor their precise
configuration to your particular application.
The chip-level user modules are documented in data sheets that
are viewed directly in PSoC Designer. These data sheets explain
the internal operation of the component and provide perfor-
mance specifications. Each data sheet describes the use of each
user module parameter and contains other information you may
need to successfully implement your design.
Organize and Connect
You build signal chains at the chip level by interconnecting user
modules to each other and the I/O pins, or connect system-level
inputs, outputs, and communication interfaces to each other with
valuator functions. In the chip-level view, you perform the
selection, configuration, and routing so that you have complete
control over the use of all on-chip resources.
Document Number: 001-12394 Rev *G
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CY7C64345, CY7C6435x
Document Conventions
Acronyms Used
Units of Measure
The following table lists the acronyms that are used in this
document.
A units of measure table is located in the Electrical Specifications
measure the enCoRe V devices.
Acronym
API
Description
application programming interface
central processing unit
general purpose IO
Numeric Naming
Hexadecimal numbers are represented with all letters in
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (for example, 01010100b’ or
‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or 0x are
decimal.
CPU
GPIO
ICE
in-circuit emulator
ILO
internal low speed oscillator
internal main oscillator
input/output
IMO
IO
LSb
least significant bit
LVD
low voltage detect
MSb
POR
PPOR
PSoC®
SLIMO
SRAM
most significant bit
power on reset
precision power on reset
Programmable System-on-Chip™
slow IMO
static random access memory
Document Number: 001-12394 Rev *G
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CY7C6431x
CY7C64345, CY7C6435x
Pin Configuration
The enCoRe V USB device is available in a variety of packages which are listed and illustrated in the subsequent tables.
16-Pin Part Pinout
Figure 1. CY7C64315/CY7C64316 16-Pin enCoRe V Device
P0[4]
P2[3]
P1[7]
P1[5]
P1[1]
12
11
10
9
1
2
3
4
QFN
XRES
(Top View)
P1[4]
P1[0]
Table 1. 16-Pin Part Pinout (QFN)
Pin No.
Type
I/O
Name
Description
1
2
P2[3]
P1[7]
P1[5]
P1[1]
Vss
Digital I/O, Crystal Input (Xin)
Digital I/O, SPI SS, I2C SCL
Digital I/O, SPI MISO, I2C SDA
IOHR
IOHR
IOHR
Power
USB line
USB line
Power
IOHR
IOHR
Input
IOH
3
4
Digital I/O, ISSP CLK, 12C SCL, SPI MOSI
5
Ground connection
6
D+
USB PHY
7
D–
USB PHY
8
Vdd
Supply
9
P1[0]
P1[4]
Digital I/O, ISSP DATA, I2C SDA, SPI CLK
10
11
12
13
14
15
16
Digital I/O, optional external clock input (EXTCLK)
XRES
P0[4]
P0[7]
P0[3]
P0[1]
P2[5]
Active high external reset with internal pull down
Digital I/O
IOH
Digital I/O
IOH
Digital I/O
IOH
Digital I/O
I/O
Digital I/O, Crystal Output (Xout)
LEGEND I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output
Notes
1. During power up or reset event, device P1[0] and P1[1] may disturb the I2C bus. Use alternate pins if issues are encountered.
2. These are the in-system serial programming (ISSP) pins that are not High Z at power on reset (POR).
Document Number: 001-12394 Rev *G
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CY7C6431x
CY7C64345, CY7C6435x
32-Pin Part Pinout
Figure 2. CY7C64343/CY7C64345 32-Pin enCoRe V USB Device
P0[1]
1
2
24
23
P0[0]
P2[6]
P2[5]
P2[3]
P2[1]
P1[7]
3
4
5
6
7
8
22
21
20
P2[4]
P2[2]
P2[0]
P3[2]
QFN
( Top View)
P1[5]
P1[3]
P1[1]
19
18
17
P3[0]
XRES
Table 2. 32-Pin Part Pinout (QFN)
Pin No.
1
Type
IOH
Name
P0[1]
Description
Digital I/O
2
3
4
5
6
7
8
9
I/O
I/O
I/O
IOHR
IOHR
IOHR
IOHR
Power
I/O
P2[5]
P2[3]
P2[1]
P1[7]
P1[5]
P1[3]
P1[1]
Vss
Digital I/O, Crystal Output (Xout)
Digital I/O, Crystal Input (Xin)
Digital I/O
Digital I/O, I2C SCL, SPI SS
Digital I/O, I2C SDA, SPI MISO
Digital I/O, SPI CLK
Digital I/O, ISSP CLK, I2C SCL, SPI MOSI
Ground
USB PHY
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
CP
D+
I/O
D–
Vdd
P1[0]
P1[2]
P1[4]
P1[6]
XRES
P3[0]
P3[2]
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
USB PHY
Supply voltage
Digital I/O, ISSP DATA, I2C SDA, SPI CLK
Digital I/O
Digital I/O, optional external clock input (EXTCLK)
Digital I/O
Active high external reset with internal pull down
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Power
IOHR
IOHR
IOHR
IOHR
Reset
I/O
I/O
I/O
I/O
I/O
I/O
IOH
IOH
IOH
IOH
Power
IOH
IOH
IOH
Digital I/O
Supply voltage
Digital I/O
Digital I/O
Digital I/O
Ground
P0[7]
P0[5]
P0[3]
Vss
Power
Power
Vss
Ensure the center pad is connected to ground
LEGEND I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output
Document Number: 001-12394 Rev *G
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CY7C6431x
CY7C64345, CY7C6435x
48-Pin Part Pinout
Figure 3. CY7C64355/CY7C64356 48-Pin enCoRe V USB Device
P2[6]
P2[4]
P2[2]
P2[0]
P4[2]
P4[0]
P3[6]
36
35
34
33
32
31
30
NC
P2[7]
P2[5]
1
2
3
4
P2[3]
P2[1]
P4[3]
5
6
QFN
(Top View)
P4[1]
P3[7]
P3[5]
P3[3]
7
P3[4]
P3[2]
P3[0]
XRES
29
28
27
8
9
10
P3[1]
P1[7]
26
25
11
12
P1[6]
Table 3. 48-Pin Part Pinout (QFN)
Pin No.
1
Type
NC
Pin Name
Description
NC
No connection
Digital I/O
2
I/O
P2[7]
P2[5]
P2[3]
P2[1]
P4[3]
P4[1]
P3[7]
P3[5]
P3[3]
P3[1]
P1[7]
P1[5]
NC
3
I/O
Digital I/O, Crystal Out (Xout)
Digital I/O, Crystal In (Xin)
Digital I/O
4
I/O
5
I/O
6
I/O
Digital I/O
7
I/O
Digital I/O
8
I/O
Digital I/O
9
I/O
Digital I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
I/O
Digital I/O
I/O
Digital I/O
IOHR
IOHR
NC
Digital I/O, I2C SCL, SPI SS
Digital I/O, I2C SDA, SPI MISO
No connection
NC
NC
No connection
IOHR
IOHR
Power
I/O
P1[3]
P1[1]
Vss
Digital I/O, SPI CLK
Digital I/O, ISSP CLK, I2C SCL, SPI MOSI
Supply ground
D+
USB
I/O
D–
USB
Power
IOHR
IOHR
IOHR
IOHR
Vdd
Supply voltage
P1[0]
P1[2]
P1[4]
P1[6]
Digital I/O, ISSP DATA, I2C SDA, SPI CLK
Digital I/O,
Digital I/O, optional external clock input (EXTCLK)
Digital I/O
Document Number: 001-12394 Rev *G
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CY7C6431x
CY7C64345, CY7C6435x
Table 3. 48-Pin Part Pinout (QFN) (continued)
Pin No.
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Type
XRES
I/O
Pin Name
Ext Reset
Description
Active high external reset with internal pull down
Digital I/O
P3[0]
P3[2]
P3[4]
P3[6]
P4[0]
P4[2]
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
I/O
Digital I/O
I/O
Digital I/O
I/O
Digital I/O
I/O
Digital I/O
I/O
Digital I/O
I/O
Digital I/O
I/O
Digital I/O
I/O
Digital I/O
I/O
Digital I/O
IOH
IOH
IOH
IOH
Power
NC
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Supply voltage
No connection
No connection
Digital I/O
NC
NC
NC
IOH
IOH
IOH
Power
IOH
P0[7]
P0[5]
P0[3]
Vss
Digital I/O
Digital I/O
Supply ground
Digital I/O
P0[1]
LEGEND I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output
Document Number: 001-12394 Rev *G
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CY7C64345, CY7C6435x
Register Reference
The section discusses the registers of the enCoRe V device. It lists all the registers in mapping tables, in address order.
Register Conventions
Register Mapping Tables
The register conventions specific to this section are listed in the
following table.
The enCoRe V device has a total register address space of 512
bytes. The register space is also referred to as IO space and is
broken into two parts: Bank 0 (user space) and Bank 1 (configu-
ration space). The XIO bit in the Flag register (CPU_F) deter-
mines which bank the user is currently in. When the XIO bit is
set, the user is said to be in the “extended” address space or the
“configuration” registers.
Table 4. Register Conventions
Convention
Description
Read register or bits
R
W
L
Write register or bits
Logical register or bits
Clearable register or bits
Access is bit specific
C
#
Document Number: 001-12394 Rev *G
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Table 5. Register Map Bank 0 Table: User Space
Name
PRT0DR
PRT0IE
Addr (0,Hex) Access
Name
Addr (0,Hex) Access
Name
Addr (0,Hex) Access
Name
Addr (0,Hex) Access
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
RW
RW
EP1_CNT0
EP1_CNT1
EP2_CNT0
EP2_CNT1
EP3_CNT0
EP3_CNT1
EP4_CNT0
EP4_CNT1
EP5_CNT0
EP5_CNT1
EP6_CNT0
EP6_CNT1
EP7_CNT0
EP7_CNT1
EP8_CNT0
EP8_CNT1
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
#
RW
#
RW
#
RW
#
RW
#
RW
#
RW
#
RW
#
RW
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
C0
C1
C2
C3
C4
C5
C6
C7
PRT1DR
PRT1IE
RW
RW
PRT2DR
PRT2IE
RW
RW
I2C_XCFG
I2C_XSTAT
I2C_ADDR
I2C_BP
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
RW
R
RW
R
R
RW
R
RW
RW
RW
PRT3DR
PRT3IE
RW
RW
I2C_CP
CPU_BP
CPU_CP
I2C_BUF
CUR_PP
STK_PP
PRT4DR
PRT4IE
RW
RW
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
IDX_PP
RW
RW
RW
RW
#
MVR_PP
MVW_PP
I2C_CFG
I2C_SCR
I2C_DR
PMA0_DR
PMA1_DR
PMA2_DR
PMA3_DR
PMA4_DR
PMA5_DR
PMA6_DR
PMA7_DR
RW
RW
RW
RW
RW
RW
RW
RW
RW
INT_CLR0
INT_CLR1
INT_CLR2
INT_CLR3
INT_MSK2
INT_MSK1
INT_MSK0
INT_SW_EN
INT_VC
RW
RW
RW
RW
RW
RW
RW
RW
RC
W
RES_WDT
INT_MSK3
PMA8_DR
PMA9_DR
PMA10_DR
PMA11_DR
PMA12_DR
PMA13_DR
PMA14_DR
PMA15_DR
TMP_DR0
TMP_DR1
TMP_DR2
TMP_DR3
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
SPI_TXR
SPI_RXR
SPI_CR
W
R
#
PT0_CFG
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
RW
RW
RW
RW
RW
RW
RW
RW
RW
USB_SOF0
USB_SOF1
USB_CR0
USBIO_CR0
USBIO_CR1
EP0_CR
EP0_CNT0
EP0_DR0
EP0_DR1
EP0_DR2
EP0_DR3
EP0_DR4
EP0_DR5
EP0_DR6
EP0_DR7
R
R
RW
#
#
#
PT0_DATA1
PT0_DATA0
PT1_CFG
PT1_DATA1
PT1_DATA0
PT2_CFG
#
PT2_DATA1
PT2_DATA0
CPU_F
RL
RW
RW
RW
RW
RW
RW
RW
RW
CPU_SCR1
CPU_SCR0
#
#
Gray fields are reserved; do not access these fields.
# Access is bit specific.
Document Number: 001-12394 Rev *G
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CY7C6431x
CY7C64345, CY7C6435x
Table 6. Register Map Bank 1 Table: Configuration Space
Name
PRT0DM0
PRT0DM1
Addr (1,Hex) Access
Name
PMA4_RA
PMA5_RA
PMA6_RA
PMA7_RA
PMA8_WA
PMA9_WA
PMA10_WA
PMA11_WA
PMA12_WA
PMA13_WA
PMA14_WA
PMA15_WA
PMA8_RA
PMA9_RA
PMA10_RA
PMA11_RA
PMA12_RA
PMA13_RA
PMA14_RA
PMA15_RA
EP1_CR0
EP2_CR0
EP3_CR0
EP4_CR0
EP5_CR0
EP6_CRO
EP7_CR0
EP8_CR0
Addr (1,Hex) Access
Name
Addr (1,Hex) Access
Name
Addr (1,Hex) Access
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
RW
RW
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
#
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
PRT1DM0
PRT1DM1
RW
RW
PRT2DM0
PRT2DM1
RW
RW
PRT3DM0
PRT3DM1
RW
RW
PRT4DM0
PRT4DM1
RW
RW
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
#
#
#
#
#
#
#
IO_CFG
OUT_P1
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
RW
RW
OSC_CR0
ECO_CFG
OSC_CR2
VLT_CR
RW
#
RW
RW
R
VLT_CMP
IMO_TR
ILO_TR
W
W
SPI_CFG
USB_CR1
RW
SLP_CFG
SLP_CFG2
SLP_CFG3
RW
RW
RW
TMP_DR0
TMP_DR1
TMP_DR2
TMP_DR3
RW
RW
RW
RW
#
USBIO_CR2
PMA0_WA
PMA1_WA
PMA2_WA
PMA3_WA
PMA4_WA
PMA5_WA
PMA6_WA
PMA7_WA
PMA0_RA
PMA1_RA
PMA2_RA
PMA3_RA
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
CPU_F
RL
Gray fields are reserved; do not access these fields.
# Access is bit specific.
Document Number: 001-12394 Rev *G
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CY7C6431x
CY7C64345, CY7C6435x
Electrical Specifications
This section presents the DC and AC electrical specifications of the enCoRe V USB devices. For the most up to date electrical
specifications, verify that you have the most recent data sheet available by visiting the company web site at http://www.cypress.com
Figure 4. Voltage versus CPU Frequency
Figure 5. IMO Frequency Trim Options
5.5V
5.5V
SLIMO
Mode
SLIMO SLIMO
Mode
Mode
= 01
= 00
= 10
3.0V
3.0V
750 kHz
3 MHz
CPU Frequency
24 MHz
750 kHz
3 MHz
6 MHz 12 MHz 24 MHz
IMO Frequency
The following table lists the units of measure that are used in this section.
Table 7. Units of Measure
Symbol
Unit of Measure
Symbol
μW
mA
ms
mV
nA
Unit of Measure
o
C
degree Celsius
decibels
microwatts
milli-ampere
milli-second
milli-volts
dB
fF
femto farad
hertz
Hz
KB
1024 bytes
1024 bits
nanoampere
nanosecond
nanovolts
Kbit
kHz
kΩ
ns
kilohertz
nV
kilohm
Ω
ohm
MHz
MΩ
μA
μF
μH
μs
μV
μVrms
megahertz
megaohm
microampere
microfarad
microhenry
microsecond
microvolts
pA
picoampere
picofarad
pF
pp
peak-to-peak
parts per million
picosecond
ppm
ps
sps
s
samples per second
sigma: one standard deviation
volts
microvolts root-mean-square
V
Document Number: 001-12394 Rev *G
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CY7C6431x
CY7C64345, CY7C6435x
ADC Electrical Specifications
Table 8. ADC Electrical Specifications
Symbol
Description
Min
Typ
Max
Units
Conditions
Input
Input Voltage Range
Input Capacitance
Vss
1.3
5
V
pF
This gives 72% of maximum code
Resolution
8-Bit Sample Rate
8
Bits
23.4375
ksps Data Clock set to 6 MHz. Sample
Rate = 0.001/(2^Resolution/Data
clock)
DC Accuracy
DNL
-1
-2
0
+2
+2
LSb For any configuration
INL
LSb For any configuration
Offset Error
15
90
mV
Operating Current
Data Clock
275
350
12
μA
2.25
MHz Source is chip’s internal main oscil-
lator. See AC chip level specifica-
tions for accuracy.
Monotonicity
Not guaranteed. See DNL
Power Supply Rejection Ratio
PSRR (Vdd>3.0V)
PSRR (2.2 < Vdd < 3.0)
PSRR (2.0 < Vdd < 2.2)
PSRR (Vdd < 2.0)
Gain Error
24
30
12
0
dB
dB
dB
dB
1
5
%FSR For any resolution
Input Resistance
1/(500fF*D 1/(400fF*D 1/(300fF*D
ata-Clock) ata-Clock) ata-Clock)
Ω
Equivalent switched cap input
resistance for 8-, 9-, or 10-bit
resolution.
Document Number: 001-12394 Rev *G
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CY7C6431x
CY7C64345, CY7C6435x
Electrical Characteristics
Absolute Maximum Ratings
Operating Conditions
Ambient Temperature (T ).................................. 0 C to 70 C
(3)
o
o
o
o
o
Storage Temperature (T
)
-55 C to 125 C (Typical +25 C)
Supply Voltage Relative to Vss (Vdd)............. -0.5V to +6.0V
DC Input Voltage (V )....................Vss - 0.5V to Vdd + 0.5V
STG
A
o
o
Operational Die Temperature (T ) ................... 0 C to 85 C
J
IO
DC Voltage Applied to Tri-state (V )Vss - 0.5V to Vdd + 0.5V
IOZ
Maximum Current into any Port Pin (I
). -25mA to +50 mA
MIO
Electrostatic Discharge Voltage (ESD) .................... 2000V
(5)
Latch-up Current (LU) .......................................... 200 mA
DC Electrical Characteristics
DC Chip Level Specifications
Table 9 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 9. DC Chip Level Specifications
Parameter
Description
Supply Voltage
Conditions
Min
Typ
Max
Units
Vdd
See table titled DC POR and LVD
3.0
–
5.5
V
o
I
I
I
Supply Current, IMO = 24 MHz
Supply Current, IMO = 12 MHz
Supply Current, IMO = 6 MHz
Conditions are Vdd = 3.0V, T = 25 C,
–
–
–
–
–
–
3.1
2.0
1.5
mA
mA
mA
DD24,3
DD12,3
DD6,3
A
CPU = 24 MHz,
No USB/I2C/SPI.
o
Conditions are Vdd = 3.0V, T = 25 C,
A
CPU = 12 MHz,
No USB/I2C/SPI.
o
Conditions are Vdd = 3.0V, T = 25 C,
A
CPU = 6 MHz,
No USB/I2C/SPI.
o
I
I
I
Standby Current with POR, LVD, and
Sleep Timer
Vdd = 3.0V, T = 25 C, I/O regulator
–
–
–
–
1.5
–
μA
μA
SB1,3
SB0,3
DD24,5
A
turned off.
o
Deep Sleep Current
Vdd = 3.0V, T = 25 C, I/O regulator
0.1
A
turned off.
o
Supply Current, IMO = 24 MHz
Conditions are Vdd = 5.0V, T = 25 C,
mA
A
CPU = 24 MHz,
No USB/I2C/SPI.
o
I
I
Supply Current, IMO = 12 MHz
Supply Current, IMO = 6 MHz
Conditions are Vdd = 5.0V, T = 25 C,
–
–
mA
mA
DD12,5
DD6,5
A
CPU = 12 MHz,
No USB/I2C/SPI.
o
Conditions are Vdd = 5.0V, T = 25 C,
A
CPU = 6 MHz,
No USB/I2C/SPI.
o
I
I
Standby Current with POR, LVD, and
Sleep Timer
Vdd = 5.0V, T = 25 C, I/O regulator
–
–
μA
μA
SB1,5
A
turned off.
o
Deep Sleep Current
Vdd = 5.0V, T = 25 C, I/O regulator
–
SB0,5
A
turned off.
Notes
o
3. Higher storage temperatures reduce data retention time. Recommended storage temperature is +25°C ± 25°C. Extended duration storage temperatures above 85 C
degrade reliability.
4. Human Body Model ESD.
5. According to JESD78 standard.
6. The temperature rise from ambient to junction is package specific. See Package Handling on page 25. The user must limit the power consumption to comply with this
requirement.
Document Number: 001-12394 Rev *G
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CY7C6431x
CY7C64345, CY7C6435x
Table 10.DC Characteristics – USB Interface
Symbol
Rusbi
Rusba
Vohusb
Volusb
Vdi
Description
USB D+ Pull Up Resistance
USB D+ Pull Up Resistance
Static Output High
Conditions
Min
0.900
1.425
2.8
Typ
Max
1.575
3.090
3.6
Units
kΩ
kΩ
V
With idle bus
-
While receiving traffic
-
-
Static Output Low
-
0.3
V
Differential Input Sensitivity
Differential Input Common Mode Range
Single Ended Receiver Threshold
Transceiver Capacitance
0.2
0.8
0.8
-
V
Vcm
-
2.5
2.0
50
V
Vse
-
V
Cin
-
-
pF
μA
kΩ
Ω
Iio
High Z State Data Line Leakage
PS/2 Pull Up Resistance
On D+ or D- line
-10
3
+10
7
Rps2
Rext
5
External USB Series Resistor
In series with each USB pin
21.76
24.0
24.24
DC General Purpose IO Specifications
Table 11 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0V to 5.5V and 0°C ≤ T
A
Table 11. 3.0V and 5.5V DC GPIO Specifications
Symbol
Description
Pull Up Resistor
Conditions
Min
Typ
5.6
–
Max
8
Units
kΩ
V
R
4
PU
V
V
V
High Output Voltage
Port 0, 2, or 3 Pins
IOH < 10 µA, Vdd > 3.0V, maximum of 10 mA Vdd - 0.2
source current in all I/Os.
–
OH1
High Output Voltage
Port 0, 2, or 3 Pins
IOH = 1 mA Vdd > 3.0, maximum of 20 mA
source current in all I/Os.
Vdd - 0.9
–
–
–
–
V
V
OH2
OH3
High Output Voltage
IOH < 10 µA, Vdd > 3.0V, maximum of 10 mA Vdd - 0.2
Port 1 Pins with LDO Regulator source current in all I/Os.
Disabled
V
V
V
V
V
V
V
High Output Voltage
Port 1 Pins with LDO Regulator source current in all I/Os.
Disabled
IOH = 5 mA, Vdd > 3.0V, maximum of 20 mA Vdd - 0.9
–
3.00
–
–
3.3
–
V
V
V
V
V
V
V
OH4
OH5
OH6
OH7
OH8
OH9
OH10
High Output Voltage
Port 1 Pins with LDO Regulator all sourcing 5 mA
Enabled for 3V Out
IOH < 10 μA, Vdd > 3.1V, maximum of 4 I/Os
2.85
2.20
2.35
1.90
1.60
1.20
High Output Voltage
Port 1 Pins with LDO Regulator source current in all I/Os
Enabled for 3V Out
IOH = 5 mA, Vdd > 3.1V, maximum of 20 mA
High Output Voltage
Port 1 Pins with LDO Enabled for source current in all I/Os
2.5V Out
IOH < 10 μA, Vdd > 3.0V, maximum of 20 mA
2.50
–
2.75
–
High Output Voltage
Port 1 Pins with LDO Enabled for source current in all I/Os
2.5V Out
IOH = 2 mA, Vdd > 3.0V, maximum of 20 mA
High Output Voltage
Port 1 Pins with LDO Enabled for source current in all I/Os
1.8V Out
IOH < 10 μA, Vdd > 3.0V, maximum of 20 mA
1.80
–
2.1
–
High Output Voltage
Port 1 Pins with LDO Enabled for source current in all I/Os
IOH = 1 mA, Vdd > 3.0V, maximum of 20 mA
1.8V Out
Document Number: 001-12394 Rev *G
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CY7C6431x
CY7C64345, CY7C6435x
Table 11. 3.0V and 5.5V DC GPIO Specifications
Symbol
Description
Conditions
Min
Typ
Max
Units
V
Low Output Voltage
IOL = 20 mA, Vdd > 3.3V, maximum of 60 mA
sink current on even port pins (for example,
P0[2] and P1[4]) and 60 mA sink current on odd
port pins (for example, P0[3] and P1[5]).
–
–
0.75
V
OL
V
V
V
Input Low Voltage
Vdd = 3.3 to 5.5.
Vdd = 3.3 to 5.5.
–
–
–
0.8
V
V
IL
IH
H
Input High Voltage
2.0
50
–
Input Hysteresis Voltage
Input Leakage (Absolute Value)
Pin Capacitance
60
200
1
mV
µA
pF
I
0.001
1.7
IL
C
Package and pin dependent.
0.5
5
PIN
o
Temp = 25 C.
DC POR and LVD Specifications
Table 12 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 12. DC POR and LVD Specifications
Symbol
Description
Min
Typ
Max
Units
Vdd Value for PPOR Trip
PORLEV[1:0] = 10b, HPOR = 1
V
–
2.82
2.95
V
PPOR
Vdd Value for LVD Trip
VM[2:0] = 000b
V
V
V
V
V
V
V
V
–
–
2.85
2.95
3.06
–
–
–
2.92
3.02
3.13
–
–
–
2.99
3.09
3.20
–
–
–
V
V
V
–
LVD0
LVD1
LVD2
LVD3
LVD4
LVD5
LVD6
LVD7
VM[2:0] = 001b
VM[2:0] = 010b
(7)
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
–
4.62
–
4.73
–
4.83
–
V
Note
7. Always greater than 50 mV above V
(PORLEV = 10) for falling supply.
PPOR
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CY7C6431x
CY7C64345, CY7C6435x
DC Programming Specifications
Table 13 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 13. DC Programming Specifications
Symbol
Vdd
Description
Min
3.0
–
Typ
–
Max
–
Units
V
Supply Voltage for Flash Write Operations
IWRITE
I
Supply Current During Programming or Verify
Input Low Voltage During Programming or Verify
Input High Voltage During Programming or Verify
5
25
mA
V
DDP
V
V
–
–
V
IL
ILP
IHP
V
–
–
V
IH
I
–
–
0.2
mA
ILP
(8)
Programming or Verify
I
Programming or Verify
–
–
1.5
mA
IHP
(8)
V
V
Output Low Voltage During Programming or Verify
Output High Voltage During Programming or Verify
–
–
–
Vss + 0.75
V
V
OLV
Vdd - 0.9
50,000
10
Vdd
–
OHV
Flash
Flash
Flash Write Endurance
–
Cycles
Years
ENPB
DR
Flash Data Retention
20
–
AC Electrical Characteristics
AC Chip Level Specifications
The following tables list guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 14. AC Chip Level Specifications
Symbol
Description
Min
24
Typ
–
Max
–
Units
MHz
MHz
kHz
MHz
MHz
MHz
%
(11)
F
F
F
F
F
F
Maximum Operating Frequency
MAX
(12)
Maximum Processing Frequency
24
–
–
CPU
Internal Low Speed Oscillator Frequency
19
32
24
12
6.0
50
–
50
32K1
IMO24
IMO12
IMO6
Internal Main Oscillator Stability for 24 MHz ± 5%
22.8
11.4
5.7
40
25.2
12.6
6.3
60
Internal Main Oscillator Stability for 12 MHz
(13)
Internal Main Oscillator Stability for 6 MHz
DC
T
Duty Cycle of IMO
Supply Ramp Time
IMO
0
–
μs
RAMP
Notes
8. Driving internal pull down resistor.
9. Erase/write cycles per block.
10. Following maximum Flash write cycles at Tamb = 55C and Tj = 70C
o
11. Vdd = 3.0V and T = 85 C, digital clocking functions.
J
o
12. Vdd = 3.0V and T = 85 C, CPU speed.
J
13. Trimmed for 3.3V operation using factory trim values.
Document Number: 001-12394 Rev *G
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CY7C6431x
CY7C64345, CY7C6435x
Table 15.AC Characteristics – USB Data Timings
Symbol Description
Tdrate Full speed data rate
Conditions
Average bit rate
Min
9
Typ
12
–
Max
15
Units
MHz
ns
Tdjr1
Tdjr2
Tudj1
Tudj2
Tfdeop
Tfeopt
Tfeopr
Tfst
Receiver data jitter tolerance
Receiver data jitter tolerance
Driver differential jitter
To next transition
To pair transition
To next transition
To pair transition
To SE0 transition
-18.5
-9
18.5
9
–
ns
-3.5
-4.0
-2
–
3.5
4.0
5
ns
Driver differential jitter
–
ns
Source jitter for differential transition
Source SE0 interval of EOP
Receiver SE0 interval of EOP
–
ns
160
82
–
175
ns
–
ns
Width of SE0 interval during differential
transition
–
14
ns
Table 16.AC Characteristics – USB Driver
Symbol Description
Tr Transition rise time
Conditions
50 pF
Min
4
Typ
–
Max
20
Units
ns
Tf
Transition fall time
50 pF
4
–
20
ns
TR
Vcrs
Rise/fall time matching
Output signal crossover voltage
90.00
1.3
–
111.1
2.0
%
–
V
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CY7C6431x
CY7C64345, CY7C6435x
AC General Purpose I/O Specifications
Table 17 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 17. AC GPIO Specifications
Symbol
Description
Conditions
Min
0
Typ
–
Max
12
Units
MHz
ns
F
GPIO Operating Frequency
Normal Strong Mode, Ports 0, 1
Vdd = 3.3 to 5.5V, 10% - 90%
GPIO
TRise23 Rise Time, Strong Mode
Ports 2, 3
15
–
80
TRise01 Rise Time, Strong Mode
Ports 0, 1
Vdd = 3.3 to 5.5V, 10% - 90%
Vdd = 3.3 to 5.5V, 10% - 90%
10
10
–
–
50
50
ns
ns
TFall
Fall Time, Strong Mode
All Ports
Figure 6. GPIO Timing Diagram
90%
GPIO
Pin
Output
Voltage
10%
TFall
TRise23
TRise01
AC External Clock Specifications
Table 18 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 18. AC External Clock Specifications
Symbol
Description
Min
0.750
20.6
20.6
150
Typ
–
Max
25.2
5300
–
Units
MHz
ns
F
Frequency
OSCEXT
–
–
–
High Period
–
Low Period
–
ns
Power Up IMO to Switch
–
–
μs
Document Number: 001-12394 Rev *G
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CY7C6431x
CY7C64345, CY7C6435x
AC Programming Specifications
Table 19 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 19. AC Programming Specifications
Symbol
Description
Min
1
Typ
–
Max
20
20
–
Units
ns
T
T
T
T
F
T
T
T
T
Rise Time of SCLK
Fall Time of SCLK
RSCLK
FSCLK
SSCLK
HSCLK
SCLK
1
–
ns
Data Setup Time to Falling Edge of SCLK
Data Hold Time from Falling Edge of SCLK
Frequency of SCLK
40
40
0
–
ns
–
–
ns
–
8
MHz
ms
ms
ns
Flash Erase Time (Block)
–
–
18
25
60
85
ERASEB
WRITE
DSCLK1
DSCLK2
Flash Block Write Time
–
–
Data Out Delay from Falling Edge of SCLK, Vdd > 3.6V
Data Out Delay from Falling Edge of SCLK, 3.0V<Vdd<3.6V
–
–
–
–
ns
Figure 7. Timing Diagram - AC Programming Cycle
AC SPI Specifications
Table 20 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 20. AC SPI Specifications
Symbol
Description
Maximum Input Clock Frequency Selection, Master
Maximum Input Clock Frequency Selection, Slave
Width of SS_ Negated Between Transmissions
Min
–
Typ
–
Max
12
12
–
Units
MHz
MHz
ns
F
SPIM
SPIS
SS
F
T
–
–
50
–
Notes
14. Output clock frequency is half of input clock rate.
Document Number: 001-12394 Rev *G
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CY7C6431x
CY7C64345, CY7C6435x
2
AC I C Specifications
Table 21 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
2
Table 21. AC Characteristics of the I C SDA and SCL Pins
Standard Mode
Fast Mode
Symbol
Description
Units
Min
0
Max
100
–
Min
0
Max
400
–
F
SCL Clock Frequency
kHz
SCLI2C
T
Hold Time (repeated) START Condition. After this period, the first
clock pulse is generated.
4.0
0.6
μs
HDSTAI2C
T
T
T
T
T
T
T
T
LOW Period of the SCL Clock
4.7
4.0
4.7
0
–
–
–
–
–
–
–
–
1.3
0.6
0.6
0
–
–
μs
μs
μs
μs
ns
μs
μs
ns
LOWI2C
HIGH Period of the SCL Clock
HIGHI2C
SUSTAI2C
HDDATI2C
SUDATI2C
SUSTOI2C
BUFI2C
Setup Time for a Repeated START Condition
Data Hold Time
–
–
(15)
Data Setup Time
250
4.0
4.7
–
100
–
Setup Time for STOP Condition
0.6
1.3
0
–
Bus Free Time Between a STOP and START Condition
Pulse Width of spikes are suppressed by the input filter.
–
50
SPI2C
2
Figure 8. Definition of Timing for Fast/Standard Mode on the I C Bus
SDA
SCL
TSPI2C
T
LOWI2C
TSUDATI2C
THDSTAI2C
TBUFI2C
TSUSTOI2C
TSUSTAI2C
THDDATI2C
THDSTAI2C
THIGHI2C
S
Sr
P
S
Notes
15. A Fast mode I2C bus device can be used in a standard mode I2C bus system, but the requirement t
≥ 250 ns must then be met. This is automatically the case if the device does not stretch the
SU;DAT
LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line t
standard mode I2C bus specification) before the SCL line is released.
+ t
= 1000 + 250 = 1250 ns (according to the
rmax SU;DAT
Document Number: 001-12394 Rev *G
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CY7C6431x
CY7C64345, CY7C6435x
Package Diagram
This section illustrates the packaging specifications for the enCoRe V USB device, along with the thermal impedances for each
package.
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of
Packaging Dimensions
Figure 9. 16-Pin (3 x 3 mm) QFN
001-09116 *D
Document Number: 001-12394 Rev *G
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CY7C6431x
CY7C64345, CY7C6435x
Figure 10. 32-Pin (5 x 5 x 0.55 mm) QFN
001-42168 *C
Document Number: 001-12394 Rev *G
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CY7C6431x
CY7C64345, CY7C6435x
Figure 11. 48-Pin (7 x 7 x 0.9 mm) QFN
001-13191 *C
Package Handling
Some IC packages require baking before they are soldered onto a PCB to remove moisture that may have been absorbed after leaving
the factory. A label on the package has details about the actual bake temperature and the minimum bake time to remove this moisture.
The maximum bake time is the aggregate time that the parts exposed to the bake temperature. Exceeding this exposure may degrade
device reliability.
Table 22.Package Handling
Parameter
TBAKETEMP
TBAKETIME
Description
Bake Temperature
Bake Time
Minimum
Typical
Maximum
See package label
72
Unit
o
125
C
See package label
hours
Document Number: 001-12394 Rev *G
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CY7C6431x
CY7C64345, CY7C6435x
Thermal Impedances
Table 23. Thermal Impedances per Package
Package
Typical θ
JA
o
16 QFN
32.69 C/W
(17)
o
32 QFN
48 QFN
19.51 C/W
(17)
o
17.68 C/W
Solder Reflow Peak Temperature
Following is the minimum solder reflow peak temperature to achieve good solderability.
Table 24.Solder Reflow Peak Temperature
Package
16 QFN
32 QFN
48 QFN
Minimum Peak Temperature
Maximum Peak Temperature
o
o
240 C
260 C
o
o
240 C
260 C
o
o
240 C
260 C
Ordering Information
Package
Information
Ordering Code
Flash SRAM No. of GPIOs
Target Applications
CY7C64315-16LKXC
CY7C64315-16LKXCT
CY7C64316-16LKXC
CY7C64316-16LKXCT
16-Pin QFN (3x3 mm)
16K
1K
1K
2K
2K
11
11
11
11
Mid-tier FS USB dongle, RC-host
module
16-Pin QFN (Tape and Reel)
(3x3 mm)
16K
32K
32K
Mid-tier FS USB dongle, RC-host
module
16-Pin QFN (3x3 mm)
Hi-end FS USB dongle, RC-host
module
16-Pin QFN (Tape and Reel)
(3x3 mm)
Hi-end FS USB dongle, RC-host
module
CY7C64343-32LQXC
CY7C64343-32LQXCT
CY7C64345-32LQXC
32-Pin QFN (3x3 mm)
32-Pin QFN (3X3 mm)
8K
8K
1K
1K
1K
25
25
25
Full speed USB mouse
Full speed USB mouse
Full speed USB mouse
32-Pin QFN
(5x5x0.55 mm)
16K
CY7C64345-32LQXCT
CY7C64355-48LTXC
CY7C64355-48LTXCT
CY7C64356-48LTXC
CY7C64356-48LTXCT
32-Pin QFN (Tape and Reel)
(5x5x0.55 mm)
16K
16K
16K
32K
32K
1K
1K
1K
2K
2K
25
36
36
36
36
Full speed USB mouse
Full speed USB keyboard
Full speed USB keyboard
Hi-end FS USB keyboard
Hi-end FS USB keyboard
48-Pin QFN
(7x7x0.9 mm)
48-Pin QFN (Tape and Reel)
(7x7x0.9 mm)
48-Pin QFN
(7x7x0.9 mm)
48-Pin QFN (Tape and Reel)
(7x7x0.9 mm)
Notes
16. T = T + Power x θ
J
A
JA.
17. To achieve the thermal impedance specified for the package, solder the center thermal pad to the PCB ground plane.
18. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5°C with Sn-Pb or 245 ± 5°C with Sn-Ag-Cu paste.
Refer to the solder manufacturer specifications.
Document Number: 001-12394 Rev *G
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CY7C6431x
CY7C64345, CY7C6435x
Document History Page
Document Title: CY7C6431x, CY7C64345, CY7C6435x, enCoRe™ V Full Speed USB Controller
Document Number: 001-12394
Orig. of
Change
Submission
Date
Rev. ECN No.
Description of Change
**
626256
735718
TYJ
See ECN New data sheet.
*A
TYJ/ARI
See ECN Filled in TBDs, added new block diagram, and corrected some values. Part numbers
updated as per new specifications.
*B 1120404
ARI
See ECN Corrected the block diagram and Figure 3, which is the 16-pin enCoRe V device.
Corrected the description to pin 29 on Table 2, the Typ/Max values for I
on the DC
SB0
chip-level specifications, the current value for the latch-up current in the Electrical
Characteristics section, and corrected the 16 QFN package information in the
Thermal Impedance table.
Corrected some of the bulleted items on the first page.
Added DC Characteristics–USB Interface table.
Added AC Characteristics–USB Data Timings table.
Added AC Characteristics–USB Driver table.
Corrected Flash Write Endurance minimum value in the DC Programming Specifica-
tions table.
Corrected the Flash Erase Time max value and the Flash Block Write Time max value
in the AC Programming Specifications table.
Implemented new latest template.
Include parameters: Vcrs, Rpu (USB, active), Rpu (USB suspend), Tfdeop, Tfeopr2,
Tfeopt, Tfst.
Added register map tables.
Corrected a value in the DC Chip-Level Specifications table.
*C 1241024
*D 1639963
TYJ/ARI
AESA
See ECN Corrected Idd values in Table 6 - DC Chip-Level Specifications.
*E 2138889 TYJ/PYRS
See ECN Updated Ordering Code table:
- Ordering code changed for 32-QFN package: From -32LKXC to -32LTXC
- Added a new package type – “LTXC” for 48-QFN
- Included Tape and Reel ordering code for 32-QFN and 48-QFN packages
Changed active current values at 24, 12 and 6MHz in table “DC Chip-Level Specifi-
cations”
- IDD24: 2.15 to 3.1mA
- IDD12: 1.45 to 2.0mA
- IDD6: 1.1 to 1.5mA
Added information on using P1[0] and P1[1] as the I2C interface during POR or reset
events
*F 2583853 TYJ/PYRS/
HMT
10/10/08
Converted from Preliminary to Final
Added operating voltage ranges with USB
ADC resolution changed from 10-bit to 8-bit
Rephrased battery monitoring clause in page 1 to include “with external components”
Included ADC specifications table
Included Voh7, Voh8, Voh9, Voh10 specs
Flash data retention – condition added to Note [11]
Input leakage spec changed to 25 nA max
Under AC Char, Frequency accuracy of ILO corrected
GPIO rise time for ports 0,1 and ports 2,3 made common
AC Programming specifications updated
Included AC Programming cycle timing diagram
AC SPI specification updated
Spec change for 32-QFN package
Input Leakage Current maximum value changed to 1 μA
Updated V
parameter in Table 13
OHV
Updated thermal impedances for the packages
Update Development Tools, add Designing with PSoC Designer. Edit, fix links and
table format. Update TMs.
Document Number: 001-12394 Rev *G
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CY7C6431x
CY7C64345, CY7C6435x
Document Title: CY7C6431x, CY7C64345, CY7C6435x, enCoRe™ V Full Speed USB Controller
Document Number: 001-12394
*G 2653717 DVJA/PYRS
02/04/09
Updated Features, Functional Overview, Development Tools, and Designing with
PSoC Designer sections with edits.
Removed ‘GUI - graphical user interface’ from Document Conventions acronym table.
Removed ‘O - Only a read/write register or bits’ in Table 4
Edited Table 8: removed 10-bit resolution information and corrected units column.
Added ‘Package Handling’ section.
Added 8K part ‘CY7C64343-32LQXC’ to Ordering Information.
Sales, Solutions, and Legal Information
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closest to you, visit us at cypress.com/sales.
Products
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© Cypress Semiconductor Corporation, 2006-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
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United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
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the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-12394 Rev *G
Revised January 30, 2009
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enCoRe™, PSoC Designer™ and Programmable System-on-Chip™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corporation. All other trademarks or registered
trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the
Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names
mentioned in this document may be the trademarks of their respective holders.
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