CY7C1018CV33
128K x 8 Static RAM
device has an automatic power-down feature that significantly
reduces power consumption when deselected.
Features
• Pin- and function-compatible with CY7C1018BV33
• High speed
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O through I/O ) is then written into the location
— t = 10 ns
0
7
AA
specified on the address pins (A through A ).
0
16
• CMOS for optimum speed/power
• Center power/ground pinout
• Data retention at 2.0V
• Automatic power-down when deselected
• Easy memory expansion with CE and OE options
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
• Available in Pb-free and non Pb-free 300-mil-wide
32-pin SOJ
The eight input/output pins (I/O through I/O ) are placed in a
0
7
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
Functional Description[1]
The CY7C1018CV33 is a high-performance CMOS static
RAM organized as 131,072 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and tri-state drivers. This
The CY7C1018CV33 is available in a standard 300-mil-wide
SOJ.
Logic Block Diagram
Pin Configurations
SOJ
Top View
A
A
1
A
A
32
1
0
16
31
30
2
3
4
5
6
15
A
A
14
A
13
2
A
3
29
28
I/O
0
CE
OE
I/O
I/O
INPUT BUFFER
27
26
I/O
0
1
7
I/O
1
A
0
I/O
V
7
8
9
10
11
12
13
6
A
A
2
25
24
23
22
21
1
V
CC
SS
I/O
2
V
V
CC
I/O
SS
A
3
I/O
I/O
2
3
5
4
A
I/O
4
3
128K x 8
ARRAY
I/O
A
A
5
A
WE
A
4
12
6
I/O
4
A
A
11
7
20
19
A
8
A
5
A
10
14
15
16
I/O
5
A
6
A
9
A
8
18
17
A
7
I/O
6
POWER
DOWN
COLUMN
DECODER
CE
I/O
7
WE
OE
Note:
Cypress Semiconductor Corporation
Document #: 38-05131 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 3, 2006
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CY7C1018CV33
AC Test Loads and Waveforms[4]
ALL INPUT PULSES
90%
10%
R 317Ω
3.0V
3.3V
90%
10%
OUTPUT
GND
R2
351Ω
30 pF
Fall Time: 1 V/ns
Rise Time: 1 V/ns
(a)
(b)
High-Z characteristics:
R 317Ω
3.3V
OUTPUT
R2
351Ω
5 pF
(c)
[5]
Switching Characteristics Over the Operating Range
-10
-12
-15
Parameter
Description
Min.
10
3
Max.
Min.
12
Max.
Min.
15
3
Max.
Unit
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
10
12
15
AA
3
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
10
5
12
6
15
7
0
3
0
0
3
0
0
3
0
[6, 7]
OE HIGH to High-Z
5
5
6
6
7
7
[7]
CE LOW to Low-Z
[6, 7]
CE HIGH to High-Z
[8]
CE LOW to Power-up
PU
[8]
CE HIGH to Power-down
10
12
15
PD
[9, 10]
Write Cycle
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
10
8
12
9
15
10
10
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
CE LOW to Write End
SCE
AW
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
8
9
0
0
HA
0
0
0
SA
7
8
10
8
PWE
SD
Data Set-up to Write End
Data Hold from Write End
5
6
0
0
0
HD
[7]
WE HIGH to Low-Z
3
3
3
LZWE
HZWE
[6, 7]
WE LOW to High-Z
5
6
7
Notes:
4. AC characteristics (except High-Z) for all speeds are tested using the Thèvenin load shown in Figure (a). High-Z characteristics are tested for all speeds using
the test load shown in Figure (c).
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
6.
t
, t
, and t
are specified with a load capacitance of 5 pF as in (d) of AC Test Loads. Transition is measured ± 500 mV from steady-state voltage.
HZOE HZCE
HZWE
7. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
HZCE
LZCE HZOE
LZOE
HZWE
LZWE
8. This parameter is guaranteed by design and is not tested.
9. The internal Write time of the memory is defined by the overlap of CELOW and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of any of these
signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write.
10. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
and t
.
HZWE
SD
Document #: 38-05131 Rev. *D
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CY7C1018CV33
Switching Waveforms
[11, 12]
Read Cycle No. 1
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
[12, 13]
Read Cycle No. 2 (OE Controlled)
ADDRESS
t
RC
CE
OE
t
ACE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
ICC
t
PU
V
CC
50%
50%
SUPPLY
CURRENT
ISB
[14, 15]
Write Cycle No. 1 (CE Controlled)
t
WC
ADDRESS
CE
t
SCE
t
SA
t
SCE
t
t
HA
AW
t
PWE
WE
t
t
HD
SD
DATA I/O
DATA VALID
Notes:
11. Device is continuously selected. OE, CE = V .
IL
12. WE is HIGH for Read cycle.
13. Address valid prior to or coincident with CE transition LOW.
14. Data I/O is high impedance if OE = V
.
IH
15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Document #: 38-05131 Rev. *D
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CY7C1018CV33
Switching Waveforms (continued)
[14, 15]
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)
t
WC
ADDRESS
t
SCE
CE
t
t
HA
AW
t
t
PWE
SA
WE
OE
t
t
SD
HD
DATA VALID
DATA I/O
IN
NOTE 16
t
HZOE
[10, 15]
Write Cycle No. 3 (WE Controlled, OE LOW)
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
NOTE 16
DATA I/O
DATA VALID
t
t
LZWE
HZWE
Truth Table
CE
H
L
OE
WE
X
I/O –I/O
Mode
Power
0
7
X
L
High-Z
Power-down
Read
Standby (I
)
SB
H
Data Out
Data In
High-Z
Active (I
Active (I
Active (I
)
CC
L
X
H
L
Write
)
CC
L
H
Selected, Outputs Disabled
)
CC
Note:
16. During this period the I/Os are in the output state and input signals should not be applied.
Document #: 38-05131 Rev. *D
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CY7C1018CV33
Ordering Information
Speed
(ns)
Package
Diagram
Operating
Range
Ordering Code
Package Type
10
CY7C1018CV33-10VC
CY7C1018CV33-12VC
CY7C1018CV33-12VXI
CY7C1018CV33-15VXC
51-85041 32-lead 300-mil Molded SOJ
32-lead 300-mil Molded SOJ
Commercial
Commercial
Industrial
12
32-lead 300-mil Molded SOJ (Pb-Free)
15
32-lead 300-mil Molded SOJ (Pb-Free)
Commercial
Package Diagram
32-lead (300-mil) Molded SOJ (51-85041)
51-85041-*A
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05131 Rev. *D
Page 6 of 7
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implDiesotwhantlothaedmfarnoumfacWturwerwa.sSsuommeasnaullarilssk.cofosmuc.hAulsleMaannduinadlsoinSgesaoricnhdeAmnndifieDsoCwypnrelosasda.gainst all charges.
CY7C1018CV33
Document History Page
Document Title: CY7C1018CV33 128K x 8 Static RAM
Document Number: 38-05131
Issue
Date
Orig. of
Change
REV.
**
ECN NO.
109426
113432
115046
116476
493543
Description of Change
12/14/01
04/10/02
05/30/02
09/16/02
See ECN
HGK
NSL
HGK
CEA
NXR
New Data Sheet
AC Test Loads split based on speed
and I modified
*A
*B
I
CC
SB1
*C
Add applications foot note on data sheet, pg 1
*D
Added Industrial Operating Range
Removed 8 ns speed bin from Product offering
Changed the description of I from Input Load Current to
IX
Input Leakage Current in DC Electrical Characteristics table
Removed I parameter from DC Electrical Characteristics table
OS
Updated the Ordering Information Table
Document #: 38-05131 Rev. *D
Page 7 of 7
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