CY62157E MoBL®
8-Mbit (512K x 16) Static RAM
also has an automatic power-down feature that significantly
reduces power consumption when addresses are not toggling.
The device can also be put into standby mode when
Features
• Very high speed: 45 ns
deselected (CE HIGH or CE LOW or both BHE and BLE are
1
2
• Wide voltage range: 4.5V–5.5V
• Ultra-low standby power
HIGH). The input/output pins (IO through IO ) are placed in
0
15
a high-impedance state when: deselected (CE HIGH or CE
1
2
LOW), outputs are disabled (OE HIGH), both Byte High
Enable and Byte Low Enable are disabled (BHE, BLE HIGH),
—Typical Standby current: 2 µA
—Maximum Standby current: 8 µA (Industrial)
• Ultra-low active power
or during a write operation (CE LOW, CE HIGH and WE
1
2
LOW).
Writing to the device is accomplished by taking Chip Enable
(CE LOW and CE HIGH) and Write Enable (WE) input LOW.
— Typical active current: 1.8 mA @ f = 1 MHz
• Ultra-low standby power
1
2
If Byte Low Enable (BLE) is LOW, then data from IO pins (IO
0
• Easy memory expansion with CE , CE and OE features
through IO ), is written into the location specified on the
1
2
7
address pins (A through A ). If Byte High Enable (BHE) is
• Automatic power-down when deselected
• CMOS for optimum speed/power
0
18
LOW, then data from IO pins (IO through IO ) is written into
8
15
the location specified on the address pins (A through A ).
0
18
• Available in Pb-free 44-pin TSOP II and 48-ball VFBGA
package
Reading from the device is accomplished by taking Chip
Enable (CE LOW and CE HIGH) and Output Enable (OE)
1
2
LOW while forcing the Write Enable (WE) HIGH. If Byte Low
Enable (BLE) is LOW, then data from the memory location
Functional Description[1]
specified by the address pins will appear on IO to IO . If Byte
0
7
The CY62157E is a high-performance CMOS static RAM
organized as 512K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL ) in
portable applications such as cellular telephones. The device
High Enable (BHE) is LOW, then data from memory will appear
on IO to IO . See the truth table at the back of this data sheet
8
15
for a complete description of read and write modes.
®
Logic Block Diagram
DATA IN DRIVERS
A
10
A
A
9
8
7
A
A
A
A
A
6
5
4
3
512K x 16
RAM Array
IO –IO
0
7
IO –IO
8
15
A
A
A
2
1
0
COLUMN DECODER
BHE
WE
CE
CE
2
1
OE
BLE
POWER-DOWN
CIRCUIT
CE
CE
BHE
BLE
2
1
Note:
Cypress Semiconductor Corporation
Document #: 38-05695 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 21, 2006
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CY62157E MoBL®
[6, 7]
DC Input Voltage
........................................–0.5V to 6.0V
Maximum Ratings
Output Current into Outputs (LOW) ............................ 20 mA
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Static Discharge Voltage ..........................................> 2001V
(per MIL-STD-883, Method 3015)
Storage Temperature ................................–65°C to + 150°C
Latch-Up Current ...................................................> 200 mA
Ambient Temperature with
Power Applied ...........................................–55°C to + 125°C
Operating Range
Supply Voltage to Ground
Ambient
Temperature
Potential .......................................................... –0.5V to 6.0V
[8]
Device
Range
V
CC
DC Voltage Applied to Outputs
CY62157E
Industrial –40°C to +85°C
Automotive –40°C to +125°C
4.5V to 5.5V
[6, 7]
in High Z State
........................................... –0.5V to 6.0V
Electrical Characteristics (Over the Operating Range)
45 ns (Industrial)
55 ns (Automotive)
[4]
[4]
Parameter
Description
Test Conditions
Min Typ
Max
Min Typ
Max
Unit
V
V
V
V
I
Output HIGH
Voltage
I
I
= –1 mA
V
= 4.5V
2.4
2.4
V
OH
OL
IH
OH
OL
CC
Output LOW
Voltage
= 2.1 mA
V
= 4.5V
0.4
0.4
V
V
CC
Input HIGH
Voltage
V
= 4.5V to 5.5V
= 4.5V to 5.5V
2.2
–0.5
–1
V
+ 0.5 2.2
V
+ 0.5
CC
CC
CC
CC
Input LOW
Voltage
V
0.8
+1
+1
–0.5
–1
0.8
+1
+1
V
IL
Input Leakage
Current
GND < V < V
CC
µA
µA
IX
I
I
Output Leakage GND < V < V , Output Disabled –1
Current
–1
OZ
O
CC
I
V
Operating
f = f
= 1/t
V
= V
CCmax
= 0 mA
18
25
3
18
35
4
CC
CC
max
RC CC
Supply
Current
I
mA
OUT
f = 1 MHz
1.8
1.8
CMOS levels
I
Automatic CE
Power-Down
Current —
2
8
2
30
µA
CE > V − 0.2V, CE < 0.2V,
SB1
1
CC
2
V
> V – 0.2V, V < 0.2V,
IN
f = f
CC IN
(Address and Data Only),
max
CMOS Inputs
f = 0 (OE, BHE, BLE and WE),
= 3.60V
V
CC
I
Automatic CE
Power-Down
Current —
2
8
2
30
µA
CE > V – 0.2V or CE < 0.2V,
SB2
1
CC
2
V
> V – 0.2V or V < 0.2V,
IN
CC IN
f = 0, V = 3.60V
CC
CMOS Inputs
Capacitance[9]
Parameter
Description
Test Conditions
Max
10
Unit
C
C
Input Capacitance
Output Capacitance
T = 25°C, f = 1 MHz, V = V
CC(typ)
pF
pF
IN
A
CC
10
OUT
Notes:
6. V
7. V
= –2.0V for pulse durations less than 20 ns for I < 30 mA.
IL(min)
= V + 0.75V for pulse durations less than 20 ns.
IH(max)
CC
8. Full device AC operation assumes a 100 µs ramp time from 0 to V (min) and 200 µs wait time after V stabilization.
CC
CC
9. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05695 Rev. *C
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CY62157E MoBL®
Thermal Resistance[9]
Parameter
Description
Test Conditions
TSOP II VFBGA Unit
Θ
Thermal Resistance
(Junction to Ambient)
Still Air, soldered on a 3 × 4.5 inch,
two-layer printed circuit board
77
72
°C/W
JA
Θ
Thermal Resistance
(Junction to Case)
13
8.86
°C/W
JC
AC Test Loads and Waveforms
R1
ALL INPUT PULSES
90%
V
CC
3V
OUTPUT
90%
10%
10%
GND
Rise Time = 1 V/ns
R2
30 pF
Fall Time = 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to:
OUTPUT
THEVENIN EQUIVALENT
R
TH
V
Parameters
Values
Unit
Ω
R1
R2
1800
990
Ω
R
639
Ω
TH
TH
V
1.77
V
Data Retention Characteristics (Over the Operating Range)
[4]
Parameter
Description
Conditions
Min Typ
Max Unit
V
V
for Data Retention
2
V
DR
CC
I
Data Retention Current
Industrial
8
µA
V
=2V, CE > V – 0.2V,
CC
CCDR
CC
1
CE < 0.2V, V > V – 0.2V or V < 0.2V
2
IN
CC
IN
Automotive
30
[9]
t
t
Chip Deselect to Data
Retention Time
0
ns
ns
CDR
[10]
R
Operation Recovery Time
t
RC
Data Retention Waveform[11]
DATA RETENTION MODE
> 2 V
V
V
CC(min)
V
DR
CC(min)
VCC
t
t
R
CDR
CE1or
BHE.BLE
CE2
Notes:
10. Full device operation requires linear V ramp from V to V
> 100 µs or stable at V
> 100 µs.
CC(min)
CC
DR
CC(min)
11. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
Document #: 38-05695 Rev. *C
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CY62157E MoBL®
[12]
Switching Characteristics Over the Operating Range
45 ns
55 ns
Parameter
Description
Min
45
Max
Min
55
Max
Unit
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
45
55
Address to Data Valid
AA
10
10
Data Hold from Address Change
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
CE LOW and CE HIGH to Data Valid
45
22
55
25
1
2
OE LOW to Data Valid
[13]
OE LOW to LOW Z
5
10
0
5
10
0
[13, 14]
OE HIGH to High Z
CE LOW and CE HIGH to Low Z
18
18
20
20
[13]
1
2
[13, 14]
CE HIGH and CE LOW to High Z
1
2
CE LOW and CE HIGH to Power-Up
1
2
CE HIGH and CE LOW to Power-Down
45
45
55
55
PD
1
2
BLE/BHE LOW to Data Valid
DBE
LZBE
HZBE
[13]
BLE/BHE LOW to Low Z
10
45
10
55
[13, 14]
BLE/BHE HIGH to HIGH Z
18
20
[15]
Write Cycle
t
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
CE LOW and CE HIGH to Write End
35
35
40
40
SCE
AW
1
2
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
0
0
0
0
HA
SA
35
35
25
0
40
40
25
0
PWE
BW
BLE/BHE LOW to Write End
Data Set-Up to Write End
Data Hold from Write End
SD
HD
[13, 14]
WE LOW to High-Z
18
20
HZWE
LZWE
[13]
WE HIGH to Low-Z
10
10
Notes:
12. Test conditions for all parameters other than Tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of V
/2, input pulse
CC(typ)
levels of 0 to V
, and output loading of the specified I /I as shown in the “AC Test Loads and Waveforms” section.
CC(typ)
OL OH
13. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, t
is less than t
, and t
is less than t
for any
LZWE
HZCE
LZCE HZBE
LZBE HZOE
LZOE
HZWE
given device.
14. t
, t
, t
, and t
transitions are measured when the outputs enter a high-impedance state.
HZOE HZCE HZBE
HZWE
15. The internal Write time of the memory is defined by the overlap of WE, CE = V , BHE and/or BLE = V , and CE = V . All signals must be ACTIVE to initiate
1
IL
IL
2
IH
a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal
that terminates the Write.
Document #: 38-05695 Rev. *C
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CY62157E MoBL®
Switching Waveforms
Read Cycle 1 (Address Transition Controlled)
[16, 17]
t
RC
ADDRESS
t
AA
t
OHA
PREVIOUS DATA VALID
DATA VALID
DATA OUT
[17, 18]
Read Cycle 2 (OE Controlled)
ADDRESS
t
CE
RC
1
t
PD
t
HZCE
CE
2
t
ACE
BHE/BLE
OE
t
t
DBE
HZBE
t
LZBE
t
HZOE
t
DOE
t
HIGH
IMPEDANCE
LZOE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
I
t
CC
V
PU
CC
50%
50%
SUPPLY
CURRENT
I
SB
Notes:
16. The device is continuously selected. OE, CE = V , BHE and/or BLE = V , and CE = V .
1
IL
IL
2
IH
17. WE is HIGH for read cycle.
18. Address valid prior to or coincident with CE , BHE, BLE transition LOW and CE transition HIGH.
1
2
Document #: 38-05695 Rev. *C
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CY62157E MoBL®
Switching Waveforms (continued)
[15, 19, 20, 21]
Write Cycle 1 (WE Controlled)
t
WC
ADDRESS
t
SCE
CE
CE
1
2
t
t
HA
AW
t
t
PWE
SA
WE
BHE/BLE
OE
t
BW
t
t
SD
HD
VALID DATA
IO
See Note 21
DATA
t
HZOE
[15, 19, 20, 21]
Write Cycle 2 (CE or CE Controlled)
1
2
t
WC
ADDRESS
t
SCE
CE
CE
1
2
t
SA
t
t
HA
AW
t
PWE
WE
t
BHE/BLE
BW
OE
t
t
SD
HD
VALID DATA
See Note 21
DATA IO
t
HZOE
Notes:
19. Data IO is high impedance if OE = V
.
IH
20. If CE goes HIGH and CE goes LOW simultaneously with WE = V , the output remains in a high-impedance state.
1
2
IH
21. During this period, the IOs are in output state and input signals should not be applied.
Document #: 38-05695 Rev. *C
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CY62157E MoBL®
Switching Waveforms (continued)
Write Cycle 3 (WE Controlled, OE LOW)
[20, 21]
t
WC
ADDRESS
t
SCE
CE
1
CE
2
t
BW
BHE/BLE
t
t
HA
AW
t
t
PWE
SA
WE
t
t
HD
SD
DATA IO
See Note 21
VALID DATA
t
t
LZWE
HZWE
[20, 21]
Write Cycle 4 (BHE/BLE Controlled, OE LOW)
t
WC
ADDRESS
CE
1
CE
2
t
SCE
t
t
HA
AW
t
BW
BHE/BLE
WE
t
SA
t
PWE
t
t
HD
SD
See Note 21
DATA IO
VALID DATA
Document #: 38-05695 Rev. *C
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CY62157E MoBL®
Truth Table
CE
H
X
CE
X
WE
X
OE
X
BHE
X
BLE
X
Inputs/Outputs
High Z
Mode
Power
1
2
Deselect/Power-Down
Deselect/Power-Down
Deselect/Power-Down
Read
Standby (I
Standby (I
Standby (I
)
)
)
SB
SB
SB
L
X
X
X
X
High Z
High Z
X
X
X
X
H
H
L
H
H
H
L
L
L
Data Out (IO –IO
)
Active (I
Active (I
)
)
0
15
CC
CC
L
H
L
H
L
Data Out (IO –IO );
Read
0
7
High Z (IO –IO
)
8
15
L
H
H
L
L
H
High Z (IO –IO );
Read
Active (I
)
0
7
CC
Data Out (IO –IO
)
8
15
L
L
L
L
L
H
H
H
H
H
H
H
H
L
H
H
H
X
X
L
H
L
H
L
L
L
L
High Z
High Z
High Z
Output Disabled
Output Disabled
Output Disabled
Write
Active (I
Active (I
Active (I
Active (I
Active (I
)
)
)
)
)
CC
CC
CC
CC
CC
L
Data In (IO –IO
)
15
0
L
H
Data In (IO –IO );
High Z (IO –IO )
Write
0
7
8
15
L
H
L
X
L
H
High Z (IO –IO );
Write
Active (I
)
0
7
CC
Data In (IO –IO )
8
15
Ordering Information
Speed
Package
Diagram
Operating
Range
(ns)
Ordering Code
CY62157ELL-45ZSXI
CY62157ELL-55ZSXE
Package Type
45
51-85087 44-pin Thin Small Outline Package Type II (Pb-free)
51-85087 44-pin Thin Small Outline Package Type II (Pb-free)
Industrial
55
Automotive
CY62157ELL-55BVXE 51-85150 48-ball Very Fine Pitch Ball Grid Array (Pb-free)
Document #: 38-05695 Rev. *C
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CY62157E MoBL®
Package Diagrams
44-pin TSOP II (51-85087)
51-85087-*A
Document #: 38-05695 Rev. *C
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CY62157E MoBL®
Package Diagrams (continued)
48-ball VFBGA (6 x 8 x 1 mm) (51-85150)
BOTTOM VIEW
A1 CORNER
TOP VIEW
Ø0.05 M C
Ø0.25 M C A B
Ø0.30 0.05(48X)
A1 CORNER
1
2
3
4
5
6
6
5
4
3
2
1
A
A
B
C
D
B
C
D
E
E
F
F
G
G
H
H
1.875
A
A
0.75
B
6.00 0.10
3.75
B
6.00 0.10
0.15(4X)
51-85150-*D
SEATING PLANE
C
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor Corporation. All product and
company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05695 Rev. *C
Page 11 of 12
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implDiesotwhantlothaedmfarnoumfacWturwerwa.sSsuommeasnaullarilssk.cofosmuc.hAulsleMaannduinadlsoinSgesaoricnhdeAmnndifieDsoCwypnrelosasda.gainst all charges.
CY62157E MoBL®
Document History Page
®
Document Title: CY62157E MoBL , 8-Mbit (512K x 16) Static RAM
Document Number: 38-05695
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
291273
457689
See ECN
See ECN
PCI
New data sheet
*A
NXR
Added Automotive Product
Removed Industrial Product
Removed 35 ns and 45 ns speed bins
Removed “L” bin
Updated AC Test Loads table
Corrected t in Data Retention Characteristics from 100 µs to t ns
R
RC
Updated the Ordering Information and replaced the Package Name column
with Package Diagram
*B
*C
467033
569114
See ECN
See ECN
NXR
VKN
Added Industrial Product (Final Information)
Removed 48 ball VFBGA package and its relevant information
Changed the I
Changed the I
Modified footnote #4 to include current limit
Updated the Ordering Information table
value of Automotive from 2 mA to 1.8 mA for f = 1MHz
CC(typ)
value of Automotive from 5 µA to 1.8 µA
SB2(typ)
Added 48 ball VFBGA package
Updated Logic Block Diagram
Added footnote #3
Updated the Ordering Information table
Document #: 38-05695 Rev. *C
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