CY62157CV30/33
512K x 16 Static RAM
significantly reduces power consumption by 80% when
addresses are not toggling. The device can also be put into
standby mode reducing power consumption by more than 99%
Features
• Temperature Ranges
when deselected (CE HIGH or CE LOW or both BLE and
1
2
— Automotive-A: –40°C to 85°C
— Automotive-E: –40°C to 125°C
• Voltage range:
BHE are HIGH). The input/output pins (I/O through I/O ) are
0
15
placed in a high-impedance state when: deselected (CE
1
HIGH or CE LOW), outputs are disabled (OE HIGH), both
2
Byte High Enable and Byte Low Enable are disabled (BHE,
— CY62157CV30: 2.7V–3.3V
— CY62157CV33: 3.0V–3.6V
• Ultra-low active power
BLE HIGH), or during a write operation (CE LOW and CE
1
2
HIGH and WE LOW).
Writing to the device is accomplished by taking Chip Enable 1
(CE ) and Write Enable (WE) inputs LOW and Chip Enable 2
1
— Typical active current: 1.5 mA @ f = 1 MHz
(CE ) HIGH. If Byte Low Enable (BLE) is LOW, then data from
2
— Typical active current: 5.5 mA @ f = f
I/O pins (I/O through I/O ), is written into the location
max
0
7
specified on the address pins (A through A ). If Byte High
• Low standby power
0
18
Enable (BHE) is LOW, then data from I/O pins (I/O through
8
• Easy memory expansion with CE , CE and OE features
1
2
I/O ) is written into the location specified on the address pins
15
• Automatic power-down when deselected
• CMOS for optimum speed/power
(A through A ).
0
18
Reading from the device is accomplished by taking Chip
Enable 1 (CE ) and Output Enable (OE) LOW and Chip
1
• Available in Pb-free and non Pb-free 48-ball FBGA
package
Enable 2 (CE ) HIGH while forcing the Write Enable (WE)
2
HIGH. If Byte Low Enable (BLE) is LOW, then data from the
Functional Description[1]
memory location specified by the address pins will appear on
I/O to I/O . If Byte High Enable (BHE) is LOW, then data from
0
7
memory will appear on I/O to I/O . See the truth table at the
back of this data sheet for a complete description of read and
write modes.
The CY62157CV30/33 are high-performance CMOS static
RAMs organized as 512K words by 16 bits. These devices
feature advanced circuit design to provide ultra-low active
current. This is ideal for providing More Battery Life™
(MoBL™) in portable applications such as cellular telephones.
The devices also have an automatic power-down feature that
8
15
The CY62157CV30/33 are available in a 48-ball FBGA
package.
Logic Block Diagram
DATA IN DRIVERS
A
A
A
A
A
A
A
A
A
10
9
8
7
6
512K × 16
RAM Array
5
4
3
2
I/O –I/O
0
7
I/O –I/O
8
15
A
A
1
0
COLUMN DECODER
BHE
WE
CE2
CE1
OE
BLE
Power-down
Circuit
CE2
CE1
BHE
BLE
Note:
Cypress Semiconductor Corporation
Document #: 38-05014 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 31, 2006
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CY62157CV30/33
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-up Current ................................................... > 200 mA
Operating Range
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Ambient
Temperature
[6]
Device
Range
[T ]
V
CC
A
Supply Voltage to Ground Potential...–0.5V to V
+ 0.5V
ccmax
CY62157CV30 Automotive-E –40°Cto+125°C 2.7V – 3.3V
CY62157CV33 Automotive-A –40°C to +85°C 3.0V – 3.6V
Automotive-E –40°Cto+125°C
DC Voltage Applied to Outputs
in High-Z State ....................................–0.5V to V + 0.3V
[5]
CC
[5]
DC Input Voltage .................................–0.5V to V + 0.3V
CC
Output Current into Outputs (LOW) .............................20 mA
Electrical Characteristics Over the Operating Range
CY62157CV30-70
[2]
Parameter
Description
Output HIGH Voltage I = –1.0 mA
Test Conditions
Min.
Typ.
Max.
Unit
V
V
V
V
V
I
V
V
= 2.7V
= 2.7V
2.4
OH
OL
IH
OH
CC
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
I
= 2.1 mA
0.4
V
OL
CC
2.2
–0.3
–10
V
+ 0.3V
V
CC
0.8
V
IL
Input Leakage
Current
GND < V < V
CC
+10
µA
IX
I
I
I
Output Leakage
Current
GND < V < V , Output Disabled
–10
+10
µA
OZ
O
CC
V
Operating
f = f
= 1/t
V
I
= 3.3V
= 0 mA
7
15
3
mA
CC
CC
MAX
RC
CC
Supply
Current
OUT
f = 1 MHz
CE > V – 0.2V or CE < 0.2V
1.5
CMOS Levels
I
I
Automatic CE
Power-Down
Current— CMOS
Inputs
8
70
µA
µA
SB1
1
CC
2
V
f = f
> V – 0.2V or V < 0.2V,
IN
CC IN
(Address and Data Only),
max
f = 0 (OE, WE, BHE and BLE)
Automatic CE
Power-Down
Current—CMOS
Inputs
CE > V – 0.2V or CE < 0.2V
8
70
SB2
1
CC
2
V
> V – 0.2V or V < 0.2V,
IN
CC IN
f = 0, V = 3.3V
CC
Notes:
5. V
= –2.0V for pulse durations less than 20 ns.
IL(min.)
6. T is the “Instant-On” case temperature.
A
Document #: 38-05014 Rev. *F
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CY62157CV30/33
Electrical Characteristics Over the Operating Range
CY62157CV33-70
[2]
Parameter
Description
Test Conditions
Min.
Typ.
Max.
Unit
V
Output HIGH
Voltage
I
V
= –1.0 mA
OH
2.4
V
OH
= 3.0V
CC
V
Output LOW
Voltage
I
V
= 2.1 mA
0.4
V
OL
OL
= 3.0V
CC
V
V
I
Input HIGH Voltage
Input LOW Voltage
2.2
–0.3
–1
V
+ 0.3V
CC
V
V
IH
0.8
+1
+10
+1
+10
12
IL
Input Leakage
Current
GND < V < V
CC
Auto-A
Auto-E
µA
µA
µA
µA
mA
IX
I
–10
–1
I
I
Output Leakage
Current
GND < V < V , Output Disabled
Auto-A
OZ
O
CC
Auto-E
–10
V
Operating
f = f
= 1/t
V
= 3.6V Auto-A
5.5
7
CC
CC
MAX
RC
CC
Supply
Current
I
= 0 mA
OUT
Auto-E
15
CMOS Levels
f = 1 MHz
CE > V – 0.2V or
Auto-A/
Auto-E
1.5
3
I
Automatic CE
Power-Down
Current—CMOS
Inputs
Auto-A
Auto-E
10
10
30
80
µA
µA
SB1
1
CC
CE < 0.2V
2
V
> V – 0.2V or
IN
CC
V
< 0.2V,
IN
f = f
(Address and Data
max
Only),
f = 0 (OE,WE,BHE,and BLE)
I
Automatic CE
Power-Down
Current—CMOS
Inputs
CE > V – 0.2V or
Auto-A
Auto-E
10
10
30
80
µA
µA
SB2
1
CC
CE < 0.2V
2
V
> V – 0.2V or
IN
CC
V
< 0.2V,
IN
f = 0, V = 3.6V
CC
Thermal Resistance[7]
Parameter
Description
Test Conditions
FBGA
Unit
Θ
Thermal Resistance
(Junction to Ambient)
Still Air, soldered on a 3 x 4.5 inch, two-layer printed
circuit board
55
°C/W
JA
Θ
Thermal Resistance
(Junction to Case)
16
°C/W
JC
Note:
7. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05014 Rev. *F
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CY62157CV30/33
Capacitance[7]
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
T = 25°C, f = 1 MHz,
Max.
Unit
pF
C
C
6
8
IN
A
V
= V
CC
CC(typ.)
pF
OUT
AC Test Loads and Waveforms
R1
V
CC
ALL INPUT PULSES
90%
V
Typ
OUTPUT
CC
90%
10%
10%
GND
Rise TIme: 1 V/ns
R2
30 pF
Fall Time: 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to:
THÉVENIN EQUIVALENT
R
TH
OUTPUT
V
TH
Parameters
3.0V
1.105
1.550
0.645
1.75
3.3V
Unit
ΚΩ
ΚΩ
ΚΩ
V
R1
R2
1.216
1.374
0.645
1.75
R
TH
V
TH
Data Retention Characteristics (Over the Operating Range)
[2]
Parameter
Description
Conditions
Min. Typ.
Max. Unit
V
V
for Data Retention
1.5
V
DR
CC
I
Data Retention Current
V
= 1.5V, CE > V – 0.2V or
Auto-A
Auto-E
4
20
60
µA
µA
CCDR
CC
1
CC
CE < 0.2V,
V
2
4
> V – 0.2V or V < 0.2V
IN
CC IN
[8]
t
t
Chip Deselect to Data
Retention Time
0
ns
ns
CDR
[8]
R
Operation Recovery Time
t
RC
Data Retention Waveform[9]
DATA RETENTION MODE
> 1.5 V
V
V
V
CC
V
CC(min.)
CC(min.)
DR
t
t
R
CDR
CE or
1
BHE.BLE
or
CE
2
Notes:
8. Full Device AC operation requires linear V ramp from V to V
9. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
> 100 µs or stable at V >100 µs.
CC(min.)
CC
DR
CC(min.)
Document #: 38-05014 Rev. *F
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CY62157CV30/33
[10]
Switching Characteristics Over the Operating Range
70 ns
Parameter
Read Cycle
Description
Min.
70
Max.
Unit
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
Address to Data Valid
70
AA
Data Hold from Address Change
10
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
CE LOW and CE HIGH to Data Valid
70
35
1
2
OE LOW to Data Valid
[11]
OE LOW to Low-Z
5
10
0
[11, 12]
OE HIGH to High-Z
25
25
[11]
CE LOW and CE HIGH to Low-Z
1
2
[11, 12]
CE HIGH or CE LOW to High-Z
1
2
CE LOW and CE HIGH to Power-up
1
2
CE HIGH or CE LOW to Power-down
70
70
PD
1
2
BHE/BLE LOW to Data Valid
DBE
[11]
[13]
BHE/BLE LOW to Low-Z
5
LZBE
[11, 12]
BHE/BLE HIGH to High-Z
25
HZBE
[14]
Write Cycle
t
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
70
60
60
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
CE LOW and CE HIGH to Write End
SCE
AW
1
2
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
HA
0
SA
50
60
30
0
PWE
BW
BHE/BLE Pulse Width
Data Set-up to Write End
Data Hold from Write End
SD
HD
[11, 12]
WE LOW to High-Z
25
HZWE
LZWE
[11]
WE HIGH to Low-Z
5
Notes:
10. Test conditions assume signal transition time of 5 ns or less, timing reference levels of V
/2, input pulse levels of 0 to V
, and output loading of the
CC(typ.)
CC(typ.)
specified I /I and 30-pF load capacitance.
OL OH
11. At any given temperature and voltage condition, t
given device.
is less than t
, t
is less than t
, t
is less than t
, and t
is less than t
for any
LZWE
HZCE
LZCE HZBE
LZBE HZOE
LZOE
HZWE
12. t
, t
, t
, and t
transitions are measured when the outputs enter a high-impedance state.
HZOE HZCE HZBE
HZWE
13. When both byte enables are toggled together this value is 10 ns.
14. The internal Write time of the memory is defined by the overlap of WE, CE = V , BHE and/or BLE = V , CE = V . All signals must be ACTIVE to initiate a
1
IL
IL
2
IH
Write and any of these signals can terminate a Write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal
that terminates the Write.
Document #: 38-05014 Rev. *F
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CY62157CV30/33
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)
[15, 16]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
[16, 17]
Read Cycle No. 2 (OE Controlled)
ADDRESS
t
RC
CE
1
CE
2
t
ACE
OE
t
HZBE
BHE/BLE
t
LZBE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
ICC
t
PU
V
CC
50%
50%
SUPPLY
CURRENT
ISB
Notes:
15. Device is continuously selected. OE, CE = V , BHE and/or BLE = V , CE = V .
IH
1
IL
IL
2
16. WE is HIGH for Read cycle.
17. Address valid prior to or coincident with CE , BHE, BLE transition LOW and CE transition HIGH.
1
2
Document #: 38-05014 Rev. *F
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CY62157CV30/33
Switching Waveforms (continued)
[14, 18, 19]
Write Cycle No. 1 (WE Controlled)
t
WC
ADDRESS
t
SCE
CE
1
CE
2
t
t
HA
AW
t
t
PWE
SA
WE
t
BW
BHE/BLE
OE
t
t
SD
HD
DATAIN
DATA I/O
VALID
NOTE 20
t
HZOE
Notes:
18. Data I/O is high-impedance if OE = V
.
IH
19. If CE goes HIGH or CE goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state.
1
2
20. During this period, the I/Os are in output state and input signals should not be applied.
Document #: 38-05014 Rev. *F
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CY62157CV30/33
Switching Waveforms (continued)
[14, 18, 19]
Write Cycle No. 2 (CE or CE Controlled)
1
2
t
WC
ADDRESS
t
SCE
CE
1
CE
2
t
SA
t
t
HA
AW
tPWE
WE
t
BW
BHE/BLE
OE
t
t
SD
HD
VALID
DATAIN
DATA I/O
NOTE 20
t
HZOE
[19]
Write Cycle No. 3 (WE Controlled, OE LOW)
t
WC
ADDRESS
t
SCE
CE
1
CE
2
t
BW
BHE/BLE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
NOTE 20
DATAI/O
DATAIN VALID
t
LZWE
t
HZWE
Document #: 38-05014 Rev. *F
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CY62157CV30/33
Switching Waveforms (continued)
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)
[19]
t
WC
ADDRESS
CE1
CE
2
t
SCE
t
t
HA
AW
tBW
BHE/BLE
WE
t
SA
tPWE
t
t
HD
SD
DATA I/O
VALID
DATAIN
NOTE 20
Truth Table
CE
H
X
CE
X
WE
X
OE
X
BHE
X
BLE
X
Inputs/Outputs
Mode
Power
Standby (I
1
2
High Z
High Z
High Z
Deselect/Power-Down
Deselect/Power-Down
Deselect/Power-Down
Read
)
SB
L
X
X
X
X
Standby (I
Standby (I
)
SB
X
X
X
X
H
H
)
SB
L
H
H
H
L
L
L
Data Out (I/O –I/O
)
Active (I
Active (I
)
CC
O
15
L
H
L
H
L
Data Out (I/O –I/O ); Read
)
CC
O
7
I/O –I/O in High Z
8
15
L
H
H
L
L
H
Data Out (I/O –I/O ); Read
Active (I
)
CC
8
15
I/O –I/O in High Z
0
7
L
L
L
L
L
H
H
H
H
H
H
H
H
L
H
H
H
X
X
L
H
L
L
L
H
L
L
High Z
Output Disabled
Output Disabled
Output Disabled
Write
Active (I
Active (I
Active (I
Active (I
Active (I
)
CC
High Z
High Z
)
CC
)
CC
L
Data In (I/O –I/O
)
)
CC
O
15
L
H
Data In (I/O –I/O );
Write
)
CC
O
7
I/O –I/O in High Z
8
15
L
H
L
X
L
H
Data In (I/O –I/O );
Write
Active (I
)
CC
8
15
I/O –I/O in High Z
0
7
Document #: 38-05014 Rev. *F
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CY62157CV30/33
Typical DC and AC Characteristics[2]
Operating Current vs. Supply Voltage
14.0
12.0
10.0
14.0
12.0
10.0
14.0
12.0
10.0
MoBL
MoBL
MoBL
8.0
6.0
4.0
8.0
6.0
4.0
8.0
6.0
4.0
(f = fmax, 70ns)
(f = 1 MHz)
(f = fmax, 70ns)
(f = 1 MHz)
(f = fmax, 70ns)
(f = 1 MHz)
2.0
0.0
2.0
0.0
2.0
0.0
3.0
2.7
3.3
2.7
2.2
2.5
3.3
3.0
3.6
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Standby Current vs. Supply Voltage
12.0
12.0
10.0
12.0
10.0
MoBL
10.0
8.0
MoBL
MoBL
8.0
8.0
6.0
4.0
2.0
0
6.0
4.0
2.0
0
6.0
4.0
2.0
0
3.3
3.6
3.0
2.2
3.3
2.7
3.0
2.5
2.7
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Access Time vs. Supply Voltage
60
60
60
MoBL
MoBL
MoBL
50
40
30
50
40
30
50
40
30
20
20
20
10
0
10
0
10
0
3.6
3.0
3.3
2.2
2.5
2.7
3.0
2.7
3.3
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Document #: 38-05014 Rev. *F
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CY62157CV30/33
Ordering Information
Speed
(ns)
Package
Diagram
Operating
Range
Ordering Code
Package Type
70
CY62157CV30LL-70BAE
CY62157CV33LL-70BAXA
CY62157CV33LL-70BAE
51-85128
48-Ball (6 mm x 10 mm x 1.2 mm) FBGA
Automotive-E
Automotive-A
Automotive-E
Package Diagram
48-Ball (6 mm x 10 mm x 1.2 mm) FBGA (51-85128)
BOTTOM VIEW
A1 CORNER
TOP VIEW
Ø0.05 M C
Ø0.25 M C A B
Ø0.30 0.05(48X)
A1 CORNER
1
2
3
4
5
6
6
5
4
3
2
1
A
A
B
C
D
B
C
D
E
E
F
F
G
G
H
H
1.875
A
A
0.75
B
6.00 0.10
3.75
B
6.00 0.10
0.15(4X)
SEATING PLANE
C
51-85128-*D
MoBL, MoBL2, and More Battery Life are trademarks of Cypress Semiconductor Corporation. All product and company names
mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05014 Rev. *F
Page 12 of 13
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implDiesotwhantlothaedmfarnoumfacWturwerwa.sSsuommeasnaullarilssk.cofosmuc.hAulsleMaannduinadlsoinSgesaoricnhdeAmnndifieDsoCwypnrelosasda.gainst all charges.
CY62157CV30/33
Document History Page
Document Title: CY62157CV30/33 512K x 16 Static RAM
Document Number: 38-05014
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
106184
107241
05/10/01 HRT/MGN New data sheet – Advance Information
*A
07/24/01
MGN
Made corrections to Advance Information
Added 55 ns bin
*B
*C
*D
*E
109621
114218
238448
269729
03/11/02
MGN
Changed from Advance Information to Final
05/01/02 GUG/MGN Improved Typical and Max I values
CC
See ECN
See ECN
AJU
SYT
Added Automotive Product Information
Added Automotive Product information for CY62157CV30 – 70 ns
Added I and I values for Automotive range of CY62157CV33 – 70 ns
IX
OZ
*F
498575
See ECN
NXR
Removed Industrial Operating Range
Removed 55 ns speed bin
Removed CY62157CV25 part number from the Product Offering
Added Automotive-A operating range
Updated the Ordering Information Table
Document #: 38-05014 Rev. *F
Page 13 of 13
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