National Semiconductor
User’s Guide
December 2004
Revision 0.2
LMX9820ADEV:
LMX9820A Simply Blue Mod-
ule Kit User’s Guide
Scope
The Simply Blue module kit (LMX9820ADEV) is for evalua-
tion and demonstration of the National Semiconductor
— USB connector and interface circuitry (not used for
LMX9820A)
®
LMX9820A Simply Blue Serial Port module. This user’s
guide provides platform setup procedures and configura-
tion options for the Simply Blue module kit.
— Test points of baseband and radio signals
— 50-pin connector (to Austin Daughterboard)
■ Austin Daughterboard Rev. 1
— LMX9820A serial port module
— On-board 12 MHz crystal
General Description
The Simply Blue module kit contains two boards:
— On-board 32.768 kHz crystal for low power modes
— Internal use only test points of module signals
— SMA connectors for antenna and clock
— 50-pin connector (to Texas motherboard)
■ Texas Motherboard Rev. 2
— Serial connector and RS-232 interface circuitry
— JTAG connector and interface circuitry
— Audio Codec interface for Sedona Board
— Three power regulators
■ Sedona Audio Codec Daughterboard Rev. R1B
— 2 OKI Codecs, default operation
— 2 Motorola Codecs, supported
— 1 Speaker connection
— Power and link status LED indicators
— 2 Mic connections, only 1 used
LMX9820A Simply Blue Module Kit
National Semiconductor ia a registered trademark of National Semiconductor Corporation.
Bluetooth is a trademark of Bluetooth SIG, Inc. and is used under license by National Semiconductor.
© 2003 National Semiconductor Corporation
1.0 Kit Setup
2) Set ISEL1 and ISEL2 to UART at 115200 kbps or
921600 kbps, depending on the UART card in the PC.
Reference Table 2-16 on page 9 for details on setting
the UART interface.
1.1 KIT CONTENTS
The Simply Blue module kit (LMX9820ADEV) contains the
following items:
• Texas Motherboard
3) Insert the kit CD. If the installation does not start auto-
matically, double click Setup.exe on the root of the CD
drive.
• Austin Daughterboard
• Sedona Board
• Null modem cable
4) Click the Install Software button. Reference Figure 1-3
on page 5. This will install CRISP, documentation, SB
Smart and Simply Blue Commander. Please browse
the CD.
• 100V - 240V AC to 5V DC power supply
• Antenna
• CD-ROM containing documentation and software
5) Shortcuts are installed at Start->Programs->Simply
Blue 2.0. Reference Figure 1-4 on page 6.
1.2 REQUIREMENTS AND SETUP
For usage of the Simply Blue Commander refer to the
“LMX982x Serial Port Module: Simply Blue Commander
User’s Guide”
1.2.1 Basic Requirements
• x86 PC with serial port
• One of the following Microsoft Windows Operating
Systems is required:
1.2.4 CRISP In System Programmer (ISP) - Updating
Firmware
— Windows 2000
— Windows XP
Updating the firmware is possible by using the CRISP tool
included on the CD-ROM. Kits are shipped with the current
revision of firmware, so it is not necessary to update the kit
immediately. Firmware updates will be released via the
Wireless Developer’s site or are available from local FAEs.
1.2.2 Software Included in Kit
• Simply Blue Commander:
— Command oriented tool to generate commands and
watch events on the Simply Blue Command interface
1) Assemble the kit as shown in Figure 1-1.
2) Launch CRISP from the installed short cuts. Start-
• CRISP In System Programmer (ISP)
— Windows tool to update the on-chip firmware over the
command interface
>Programs->Simply Blue 2.0->CRISP
3) Follow the CRISP User’s Guide instructions. The guide
must be followed closely.
• SB Smart Demo Application
If further assistance is required, contact your FAE or local
National sales representative.
— Windows tool for quick demo setup.
1.2.3 PC - Simply Blue Module Kit Setup
To set up the Simply Blue Commander:
1.2.5 SB Smart
Reference the SB Smart User Guide.
1) Assemble the kit as shown in Figure 1-1.
Speaker
Mic/
Audio In
Null Modem Cable
PC
5V Power Supply
4
(Confidential) Revision 0.2
Figure 1-1. PC - Simply Blue Module Connection
12 MHz
(Optional)
5V Power
Supply
Austin
Daughterboard
Texas Motherboard
TX/RX
50 pin
Connector
Antenna
Speaker
Sedona Codec
Daughterboard
Mic/
Audio In
Figure 1-2. System Connection Diagram
Figure 1-3. Simply Blue Default Directory
Revision 0.2 (Confidential)
5
2.0 Board Components and Pin Assignments
A summary of the configuration and selection jumpers is
provided in the tables that follow. Reference both the sche-
matic and BOM (Bill of Materials) (included on the CD in
the kit) and also available on the Wireless Developer’s web
site.
2.1 TEXAS MOTHERBOARD
• Table 2-1 lists the primary devices on the board.
• Table 2-2 lists the connectors, configuration, and selec-
tion jumpers.
• Table 2-3 lists the switches and LEDs.
Table 2-1. Texas Motherboard Primary Devices
Device #
Name
U2
U4
National LP2986 Low-Dropout Voltage Regulator - IOVCC
National LP2986 Low-Dropout Voltage Regulator - UVCC
National LP2986 Low-Dropout Voltage Regulator - VCC
Maxim MAX3245 1 Mbps High Speed UART Driver
U5
U46
U55
Toshiba TC7WH14FU Schmitt Inverter - Used for POR (Power On Reset) circuitry
Table 2-2. Connectors, Configuration, and Selection Jumpers Summary
Jumper #
Name
Details
P3
JP1
J1
DP9 Serial Connector – Male
Table 2-4 on page 8
JTAG Connector (10x2)
Table 2-5 on page 8
50-pin Connector to Austin Daughterboard
Table 2-23 on page 11
Table 2-6 on page 8
J4
Test Points and General Purpose Outputs
J5
USB (not used for LMX9820A)
Table 2-7 on page 8
J6
ENV0
Table 2-8 on page 8 and Table 2-10 on page 9
Table 2-9 on page 8 and Table 2-10 on page 9
GND
J7
ENV1
J9/J22
J10
J11
J12
J14
J15
J16
J17
J23
GND
LSTAT_0
Internal Use Only
LSTAT_1
Internal Use Only
Audio Codec Header (4x2)
USB or DC Power Supply Jumper
DC Power Jack
Table 2-12 on page 9
Table 2-13 on page 9
Figure 2-2 on page 9
Section 2.1.9 on page 9
Section 2.1.9 on page 9
Table 2-12 on page 9
ISEL1
ISEL2
Audio Codec Optional Test Point - User defined
(not used for LMX9820A)
Table 2-3. Switches and LEDs
Name
Description
SW1
D1
D2
D3
D4
D5
D6
Reset# - Reset
LED for LSTAT_0 (not used for LMX9820A)
LED for LSTAT_1 - When illuminated, firmware has loaded properly
LED for VCC
LED for IOVCC
LED for UVCC
LED for TX/RX Activity
Revision 0.2 (Confidential)
7
2.1.1 Schmitt Trigger for POR (Power On Reset)
A Schmitt Trigger for POR has been added to the Texas
Motherboard to allow control of delay between VCC/IOVCC
and RESET#. A minimum of 2 ms is required between
VCC/IOVCC at rail and RESET# transition from low to high
to have proper startup of the module.
2.1.4 J4 Test Points and General Purpose Output
J4 is a test point header and general purpose output con-
nector. Test points are for internal use only and general
purpose outputs are not currently utilized, not configured in
firmware.
Table 2-6. J4 Pin Assignment
2.1.2 P3 DP9 Serial Connector
Pin # Signal Name
Description
P3 is a DP9 serial port connector that interfaces to the
LMX9820A’s full duplex UART. It supports up to 921.6 kbps
transfer rates. Refer to Table 2-4 for selecting and setting
the UART and transfer rate.
1
2
3
TIO4_BB
TIO3_BB
GPO2
Test Point - internal use only
Test Point - internal use only
General Purpose Output - not currently
utilized
Table 2-4. P1 DP9 Pin Assignments
4
GPO1
General Purpose Output - not currently
utilized
Pin # Signal Name
Description
1
2
3
4
5
6
7
8
9
NC
No Connect
2.1.5 J5 USB Connector
Note: Not used for LMX9820A.
RDX
TDX
NC
UART Receive Data input
UART Transmit Data output
No Connect
J5 is a USB (female), PCB mounting, 90° angled connector
that interfaces with the USB transport layer in baseband.
The on-chip USB module is compatible with USB specifica-
tions v1.0 and 1.1.
GND
NC
Ground
No Connect
RTS#
CTS#
NC
UART Ready-To-Send output
UART Clear-To-Send input
No Connect
Table 2-7. J5 Pin Assignment
Pin # Signal Name Description
1
2
3
4
UVCC_5V
D-
VCC USB
2.1.3 JP1 JTAG Connector
USB D- upstream port
USB D+ upstream port
Ground USB
JP1 is a JTAG based serial on-chip debug interface. The
JTAG interface allows the user fast program code download
into the on-chip Flash program memory (e.g., firmware
updates could be done via this interface).
D+
GND
2.1.6 Mode Selection/ISP (In-System Programming)
Configuration Header
Table 2-5. JP1 JTAG Connector Pin Assignments
Programming of the internal Flash can either be done over
the JTAG interface or by starting a special ISP code,
located in the boot area of the Flash. For normal Bluetooth
operation, no jumpers are required on J6 or J7.
Pin # Signal Name
Description
1
2
RESET#
IOVCC
NC
Reset - active low
IOVCC
3
No Connect
4
GND
NC
Ground
Table 2-8. J6 Pin Assignments
5
No Connect
Pin # Signal Name
Description
6
GND
TMS
GND
TDI
Ground
1
2
3
GND
Ground
7
JTAG Test Mode Select
Ground
ENV0
IOVCC
Refer to Table 2-10 for logic matrix
VCC
8
9
JTAG Test Data input
Ground
10
11
12
13
14
15
16
17
18
19
20
GND
TCK
GND
TDO
GND
NC
Table 2-9. J7 Pin Assignments
JTAG Test Clock input
Ground
Pin # Signal Name
Description
1
2
3
GND
Ground
JTAG Test Data output
Ground
ENV1
IOVCC
Refer to Table 2-10 for logic matrix
VCC
No Connect
GND
NC
Ground
No Connect
GND
RDY#
NC
Ground
JTAG Test Ready output - active low
No Connect
8
(Confidential) Revision 0.2
2.1.8 J14 USB or DC Power Supply
1
J14 selects between USB or DC (wall) power supply.
Table 2-10. Operation Environment
ENV0
Input
ENV1
Input
Table 2-13. J14 Jumper Pin Assignments
Mode
Pin #
Description
0
1
1
1
ISP Firmware Upgrade
Normal Operation2
1-2
2-3
USB Power
DC (wall) Power Supply
1. Refer to the LMX9820A datasheet for additional mode
boot-up details.
2. A weak internal pull-up pulls ENV0/1 to VCC.
DC (Wall) Power to J14, Pin 3
J15
1
2
2.1.7 J12 Audio Header (4x2) and J23 Test Point
J12 provides access to the Advanced Audio Interface (AAI)
signals that connect an external codec. The AAI is an
advanced version of the SSI (Synchronous Serial Interface)
that provides a full-duplex communications port to a variety
of industry-standard 13-, 14-, 15-, and 16-bit linear or 8-bit
log PCM codecs, DSPs, and other serial audio devices.
Figure 2-2. J15 DC Power Jack
2.1.9 J16 ISEL1 and J17 ISEL2 Interface Selection for
UART and USB
Note: USB is not used for LMX9820A.
Table 2-11. J12 Pin Assignment
The interface selection pins ISEL1 and ISEL2 are used to
provide different configurations after boot-up. See Table 2-
14, Table 2-15, and Table 2-16 for the specific settings. The
interface selection pin is used for transport layer selection.
The USB interface is the standard 12 Mbps. The UART
default baud rate is 921.6 kbps. If the UART is selected, the
host controller must begin communications at 921.6 kbps.
After communications are established, the host controller
can then select baud rates between 38.4 kbps and 921.6
kbps via proprietary commands.
Pin # Signal Name
Description
1
2
3
4
5
6
7
8
GND
SCK
VCC
SFS
J23
Ground
AAI Clock
VCC
AAI Frame Synchronization
Optional Test Point - user defined
AAI Transmit Data output
Ground
STD
GND
SRD
AAI Receive Data input
Table 2-14. J16 ISEL1 Pin Assignment
Table 2-12. J23 Pin Description
Pin # Signal Name
Description
Pin # Signal Name
Description
1
2
3
IOVCC
ISEL1
GND
IOVCC
ISEL1
1
User Defined
J23 is user defined. Can be connected
to one of the AAI signals for a test point
or used for an external clock input.
Ground
Table 2-15. J17 ISEL2 Pin Assignment
Pin # Signal Name
Description
2
4
6
8
1
3
5
1
2
3
IOVCC
ISEL2
GND
IOVCC
ISEL2
Ground
7
J23
1
Table 2-16. J17 Pin Assignments
J12
InterfaceSpeed
ISEL1 ISEL2
(baud)
UART Settings
Figure 2-1. J12 and J23 Pin Identification
1
0
1
0
1
1
0
0
921.6
Check NVS
115.2
Check NVS
9.6 k
No parity, one stop bit
Check NVS
Check NVS
1. Default pins are internally set to 1 by weak pull-up.
Revision 0.2 (Confidential)
9
2.2 AUSTIN DAUGHTERBOARD SUMMARY
The Austin Rev. 1 Daughterboard is populated with a 12 MHz crystal. Reference the schematic, BOM, and board for more
details. Table 2-17 lists the primary devices on the board and Table 2-18 lists the connectors and headers.
Table 2-17. Austin Daughterboard Device Summary
Device #
Name
U1
Y1
Y2
National LMX9820A Serial Port Module - Reference the device datasheet.
12 MHz Crystal - Reference the crystal device datasheet and the LMX9820A datasheet for details.
32.768 kHz Crystal for low power modes - Reference the crystal device datasheet and the LMX9820A
datasheet for more details.
Table 2-18. Connector and Header Summary
Connector/Header #
Name
Details
J1
J2
50-pin Connector to Texas Motherboard
2-pin Test Point
Table 2-23 on page 11
Table 2-19 on page 10
Figure 2-3 on page 11
Table 2-20 on page 10
Figure 2-4 on page 11
Table 2-21 on page 10
Table 2-22 on page 10
J3
SMA TX/RX Signal
J4
5-pin Test Point
J5
SMA Optional External Clock
32.768 kHz 2-pin Test Point
10-pin Test Point
J7
J26
2.2.1 J2 Test Point Header
2.2.3 J7 Test Point Header
J2 is a 2-pin test point header for internal use only.
J7 is a 2-pin test point header for a 32.768 kHz crystal.
Table 2-19. J2 Pin Assignments
Table 2-21. J6 Pin Assignment
Pin # Signal Name
Description
Pin # Signal Name
Description
1
2
Reset_5100
P12
Reset to baseband - internal use only
Test Point - internal use only
1
2
32.768 kHz +
32.768 kHz -
32.768 kHz crystal
32.768 kHz crystal
2.2.2 J4 Test Point Header
J4 is a 5-pin test point header for different voltage rails on
the board.
2.2.4 J26 Test Point Header
J26 is a 10-pin test point header for the CCB interface, TR
Switch, Reset#, and BBCLK. These are provided for debug
purposes.
Table 2-20. J4 Pin Assignments
Table 2-22. J26 Pin Assignment
Pin # Signal Name
Description
Pin # Signal Name
Description
1
2
3
4
IOVCC
Test point for IOVCC
1
2
GND
Ground
VCC
Test point for VCC
BBCLK
12 Mhz Baseband Clock Test Point
Serial Data Latch Test Point
Test Point - internal use only
Serial Data Test Point
VDD_ANA_OUT
Analog LDO output test point
3
CCB_LATCH
TX_RX_SYNC
SDAT
VDD_DIG_PWR_D# Digital LDO power down test
point
4
5
VDD_DIG_OUT
Digital LDO power output test
point
5
6
RF_DATA
CCB_CLOCK
RESET#
Test Point - internal use only
Serial Data Clock Test Point
Reset - active low
7
8
9
TR_SWITCH
TR Switch Test Point
10
TX_RX_CLOCK Test Point - internal use only
10
(Confidential) Revision 0.2
2.2.5 J3 SMA RF Signal Connector
Table 2-23. J1 Pin Assignments (Continued)
Connect antenna or test equipment to the SMA.
Signal
Pin # Name
Description
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
STD
AAI - Transmit Data output
No Connect
C1
10 pF
J3
NC
RF_SIGNAL
SMA
SRD
AAI - Receive Data input
No Connect
NC
GND
Ground
GND
Ground
RESET#
NC
Reset for LMX5100
No Connect
LSTAT_0
GND
Link Status Bit 0 output
Ground
Figure 2-3. J3 SMA Connection - Single TX/RX
2.2.6 J5 Optional External Clock
LSTAT_1
NC
Link Status Bit 1 output
No Connect
An optional external clock can be used. C29, 100 pF, must
be placed for proper operation. It is recommended to set
the signal generator to 12 MHz @ 2 dBm output. Refer to
Figure 2-4.
ENV0
GND
Module Operating Environment Input Bit 0
Ground
ENV1
TIO3_BB
SDAT
GND
Module Operating Environment Input Bit 1
Internal use only
100 pF
C29
Serial Data
Ground
GND
Ground
RDX
UART Receive Data input
Interface Select 2
UART Transport - Transmit Data
Interface Select 1
UART Transport - Clear-to-Send
Internal use only
ISEL2
TDX
J5
ISEL1
CTS#
TIO4_BB
RTS#
Ext Clk
Figure 2-4. J5 SMA Connection -
(Optional) External Clock Input
UART Transport - Request-to-Send
GPIO1_RF Internal use only
GND Ground
GPIO2_RF Internal use only
2.2.7 J1 Connector
J1 is a 50-pin board-to-board connector. See Table 2-23 for
pin assignments.
RFDATA
RF Antenna Port - 50Ω nominal
impedance
47
48
49
50
GND
Ground
Table 2-23. J1 Pin Assignments
GND
Ground
GND
Ground
Signal
Pin # Name
Description
TR Switch
TR Switch
1
2
TMS
D+
JTAG - Test Mode Select input
USB DATA+
3
TDI
JTAG - Test Data input
USB DATA-
4
D-
5
TDO
UVCC
TCK
GND
RDY#
VCC
GND
GND
SCK
IOVCC
SFS
GND
JTAG - Test Data output
UVCC
6
7
JTAG - Test Clock input
Ground
8
9
JTAG - Ready output (active low)
VCC
10
11
12
13
14
15
16
Ground
Ground
AAI - Clock
IOVCC
AAI - Frame Synchronization
Ground
Revision 0.2 (Confidential)
11
2.3 SEDONA CODEC DAUGHTERBOARD SUMMARY
The Sedona codec Rev. R1B Daughterboard is populated with a 2 OKI codecs and 2 Motorola codes. Oki codec is the only
supported device. Also, no configuration is needed for board so full details are not provided. Reference the schematic,
BOM, and board for more details. Table 2-24 lists the primary devices on the board
Table 2-24. Sedona Codec Daughterboard Device Summary
Device #
U1, U2
Name
Oki codec MSM7717
U3, U4
Motorola codec MC145483
Table 2-25. Connector and Header Summary
Name Details
Connector/Header #
P3
Connector to Texas Board
Connector for speaker or headset
Connector for microphone
Table 2-26 on page 12
Figure 2-5 on page 12
Figure 2-6 on page 12
Speaker Jack
Microphone Jack
2.3.1 P3 Connector to Texas Board
P3 is a 8-pin connector to connect to the Texas board
codec interface.
Table 2-26. P3 Pin Assignments
Pin # Signal Name
Description
1
2
3
4
5
6
SCK
GND
SFS
AAI Clock
Ground
AAI Frame Synchronization
VCC
VCC
STD
SFS1
Figure 2-6. Microphone Jack
AAI Transmit Data output
Not used since only single chan-
nel used
7
8
SRD
GND
AAI Receive Data input
Ground
2.3.2 Speaker Jack
Connect to headset or speaker.
Figure 2-5. Speaker Jack
2.3.3 Microphone Jack
Connect to microphone.
12
(Confidential) Revision 0.2
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