MPC8260 PowerQUICC™ II
Family Reference Manual
Supports
MPC8250
MPC8255
MPC8260
MPC8264
MPC8265
MPC8266
MPC8260RM
Rev. 2, 12/2005
Part I—Overview
I
1
2
3
Part II—Configuration and Reset
II
4
5
Part III—The Hardware Interface
III
6
7
8
9
10
11
12
13
IV
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
I
Part I—Overview
1
2
3
II
Part II—Configuration and Reset
4
5
III
Part III—The Hardware Interface
6
7
8
9
10
11
12
13
IV
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Contents
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Chapter 1
Features............................................................................................................................ 1-1
Communications Processor Module (CPM)................................................................ 1-9
Software Compatibility Issues......................................................................................... 1-9
Differences between MPC860 and PowerQUICC II..................................................... 1-12
Remote Access Server........................................................................................... 1-14
LAN-to-WAN Bridge Router ................................................................................ 1-16
1.7.2.4
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PCI with 155-Mbps ATM ...................................................................................... 1-22
Chapter 2
Instruction Unit............................................................................................................ 2-5
Branch Processing Unit (BPU).................................................................................... 2-5
Integer Unit (IU)...................................................................................................... 2-6
Programming Model........................................................................................................ 2-8
Register Set.................................................................................................................. 2-8
Processor Version Register (PVR)..................................................................... 2-15
PowerPC Instruction Set and Addressing Modes...................................................... 2-15
Calculating Effective Addresses............................................................................ 2-15
Instruction Cache................................................................................................... 2-20
Cache Locking....................................................................................................... 2-20
2.5
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Differences between the PowerQUICC II’s G2 Core and the
2.8
MPC603e Microprocessor......................................................................................... 2-28
Chapter 3
Chapter 4
System Configuration and Protection.............................................................................. 4-2
Interrupt Controller.......................................................................................................... 4-7
Interrupt Configuration................................................................................................ 4-8
SCC, FCC, and MCC Relative Priority................................................................. 4-12
Interrupt Vector Generation and Calculation............................................................. 4-14
Programming Model...................................................................................................... 4-17
Interrupt Controller Registers.................................................................................... 4-17
SIU Interrupt Vector Register (SIVEC)................................................................. 4-24
4.3.1.6
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System Configuration and Protection Registers........................................................ 4-26
Software Service Register (SWSR)....................................................................... 4-38
Periodic Interrupt Timer Count Register (PITC)................................................... 4-46
PCI Control Registers................................................................................................ 4-48
Chapter 5
Power-On Reset Flow.................................................................................................. 5-2
HRESET Flow............................................................................................................. 5-3
SRESET Flow.............................................................................................................. 5-3
5.1.3
5.1.4
5.4.2.1
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Chapter 6
Functional Pinout............................................................................................................. 6-1
Signal Descriptions.......................................................................................................... 6-2
Chapter 7
Signal Descriptions.......................................................................................................... 7-2
Bus Request (BR)—Output ..................................................................................... 7-3
Address Bus Request (BR)—Output................................................................... 7-3
Address Bus Request (BR)—Input...................................................................... 7-3
Bus Grant (BG)—Output..................................................................................... 7-4
Address Bus Busy (ABB)........................................................................................ 7-5
Address Bus Busy (ABB)—Output..................................................................... 7-5
Transfer Start (TS)—Output................................................................................ 7-5
Transfer Start (TS)—Input....................................................................................... 7-6
7.2.1.1
7.2.1.1.1
7.2.1.1.2
7.2.1.2.2
7.2.1.3
7.2.1.3.1
7.2.2.2
7.2.4.4.1
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Address Acknowledge (AACK).............................................................................. 7-9
Address Retry (ARTRY)—Input....................................................................... 7-10
Data Bus Busy (DBB)—Input........................................................................... 7-12
Data Bus Parity (DP[0–7])—Input.................................................................... 7-14
Transfer Acknowledge (TA).................................................................................. 7-14
Transfer Acknowledge (TA)—Output............................................................... 7-15
Partial Data Valid Indication (PSDVAL)............................................................... 7-16
Partial Data Valid (PSDVAL)—Input................................................................ 7-16
Partial Data Valid (PSDVAL)—Output............................................................. 7-17
Chapter 8
8.2.1
Terminology..................................................................................................................... 8-1
Single-PowerQUICC II Bus Mode.............................................................................. 8-2
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60x Bus Protocol Overview............................................................................................. 8-4
Transfer Code Signals TC[0–2]............................................................................. 8-12
Address Tenure Timing Configuration.................................................................. 8-24
Chapter 9
9.5
PCI Bridge Initialization.................................................................................................. 9-3
Interrupts from PCI Bridge.............................................................................................. 9-4
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PCI Interface Operation............................................................................................... 9-6
Bus Commands........................................................................................................ 9-6
Bus Driving and Turnaround............................................................................... 9-9
Read and Write Transactions............................................................................... 9-9
Transaction Termination.................................................................................... 9-11
Device Selection................................................................................................ 9-13
Fast Back-to-Back Transactions........................................................................ 9-14
Interrupt Acknowledge...................................................................................... 9-17
Address Map Programming....................................................................................... 9-24
PCI Outbound Translation..................................................................................... 9-26
Memory-Mapped Configuration Registers................................................................ 9-27
9.11.1.4
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9.11.2.13
Discard Timer Control Register (PTCR) .............................................................. 9-32
General Purpose Control Register (GPCR) .......................................................... 9-33
Error Mask Register (EMR) ................................................................................. 9-37
PCI Error Data Capture Register (PCI_EDCR) .................................................... 9-40
Vendor ID Register ............................................................................................... 9-46
Device ID Register ............................................................................................... 9-47
PCI Bus Programming Interface Register ............................................................ 9-50
PCI Bus Cache Line Size Register ....................................................................... 9-51
Header Type Register ........................................................................................... 9-52
PCI Bus Internal Memory-Mapped Registers Base Address
Subsystem Vendor ID Register ............................................................................. 9-55
Subsystem Device ID Register ............................................................................. 9-56
PCI Bus Interrupt Line Register ........................................................................... 9-56
PCI Bus Interrupt Pin Register ............................................................................. 9-57
PCI Bus MAX LAT .............................................................................................. 9-58
PCI Bus Function Register ................................................................................... 9-58
PCI Hot Swap Register Block .............................................................................. 9-60
PCI Configuration Register Access from the Core ............................................... 9-62
9.11.2.26
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Notes on GPCR[LE_MODE] ........................................................................... 9-63
Initializing the PCI Configuration Registers ........................................................ 9-64
Message Unit (I2O) ...................................................................................................... 9-65
9.12.3
I O Unit .................................................................................................................... 9-69
2
9.12.3.2.1
Inbound Free_FIFO Head Pointer Register (IFHPR) and
Inbound Post_FIFO Head Pointer Register (IPHPR) and
9.12.3.2.2
Outbound FIFOs ................................................................................................... 9-74
Outbound Free_FIFO Head Pointer Register (OFHPR) and
9.12.3.3.1
Outbound Post_FIFO Head Pointer Register (OPHPR) and
9.12.3.3.2
Queue Base Address Register (QBAR) ............................................................ 9-84
DMA Operation......................................................................................................... 9-85
DMA Chaining Mode............................................................................................ 9-86
9.13.1.6.1
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Descriptor in Big Endian Mode............................................................................. 9-96
Descriptor in Little Endian Mode.......................................................................... 9-97
System Error (SERR) ........................................................................................ 9-98
Parity Error (PERR)........................................................................................... 9-98
Illegal Register Access Error................................................................................. 9-98
PCI Interface.......................................................................................................... 9-98
9.14.1.1.1
9.14.1.1.2
Chapter 10
10.4.3.1
10.4.3.2
10.5
Main PLL....................................................................................................................... 10-2
PCI Bridge as a Host and Generating the PCI System Clock................................ 10-4
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General System Clocks.............................................................................................. 10-5
Chapter 11
Features.......................................................................................................................... 11-3
Parity Generation and Checking................................................................................ 11-8
Data Buffer Controls (BCTLx and LWR) ................................................................. 11-9
Data Pipelining ......................................................................................................... 11-9
External Memory Controller Support...................................................................... 11-10
External Address Latch Enable Signal (ALE)......................................................... 11-10
Partial Data Valid Indication (PSDVAL) ..................................................................11-11
Register Descriptions................................................................................................... 11-12
Base Registers (BRx)............................................................................................... 11-13
Memory Data Register (MDR)................................................................................ 11-28
60x Bus-Assigned UPM Refresh Timer (PURT)..................................................... 11-30
11.2.7
11.3.1
11.3.14
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Activate to Read/Write Interval........................................................................... 11-39
SDRAM Mode-Set Command Timing.................................................................... 11-47
SDRAM Configuration Examples........................................................................... 11-48
Programmable Wait State Configuration............................................................. 11-58
Extended Hold Time on Read Accesses.............................................................. 11-59
External Access Termination................................................................................... 11-61
Requests................................................................................................................... 11-64
11.6.1.3
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RAM Words......................................................................................................... 11-70
Byte-Select Signals (BxTx)............................................................................. 11-75
General-Purpose Signals (GxTx, GOx)........................................................... 11-76
Data Valid and Data Sample Control................................................................... 11-77
The Wait Mechanism........................................................................................... 11-78
Handling Devices with Slow or Variable Access Times............................................ 11-101
Hierarchical Bus Interface Example...................................................................... 11-101
Slow Devices Example.......................................................................................... 11-101
Extended Controls in 60x-Compatible Mode........................................................ 11-102
Chapter 12
L2 Cache Configurations............................................................................................... 12-1
Copy-Back Mode....................................................................................................... 12-1
Write-Through Mode................................................................................................. 12-2
L2 Cache Interface Parameters...................................................................................... 12-6
System Requirements When Using the L2 Cache Interface.......................................... 12-7
L2 Cache Operation....................................................................................................... 12-7
12.5
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Chapter 13
TAP Controller............................................................................................................... 13-2
PowerQUICC II Restrictions......................................................................................... 13-7
Nonscan Chain Operation.............................................................................................. 13-7
Chapter 14
Features.......................................................................................................................... 14-1
CP Block Diagram..................................................................................................... 14-5
RISC Controller Configuration Register (RCCR)..................................................... 14-8
RISC Time-Stamp Register (RTSR)........................................................................ 14-11
RISC Timer Command Register (TM_CMD) ......................................................... 14-24
14.6.6
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RISC Timer Interrupt Handling............................................................................... 14-26
Chapter 15
Features.......................................................................................................................... 15-3
Serial Interface RAM..................................................................................................... 15-8
One Multiplexed Channel with Static Frames........................................................... 15-9
Static and Dynamic Routing.................................................................................... 15-14
SIx RAM Shadow Address Registers (SIxRSR)..................................................... 15-23
Serial Interface GCI Programming.......................................................................... 15-32
Normal Mode GCI Programming........................................................................ 15-32
Chapter 16
16.4.2
Features.......................................................................................................................... 16-2
Enabling Connections to TSA or NMSI........................................................................ 16-3
NMSI Configuration...................................................................................................... 16-4
CMX SI1 Clock Route Register (CMXSI1CR)....................................................... 16-12
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CMX SI2 Clock Route Register (CMXSI2CR)....................................................... 16-12
Chapter 17
Chapter 18
Features.......................................................................................................................... 18-1
Timer Capture Registers (TCR1–TCR4)................................................................... 18-7
Chapter 19
SDMA Bus Arbitration and Bus Transfers.................................................................... 19-2
IDMA Transfers............................................................................................................. 19-6
Working with a PCI Bus........................................................................................ 19-9
19.5.1.3
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Peripheral to Memory...................................................................................... 19-10
Memory to Peripheral...................................................................................... 19-10
Single Address (Fly-By) Transfers...................................................................... 19-10
Peripheral-to-Memory Fly-By Transfers......................................................... 19-11
Memory-to-Peripheral Fly-By Transfers......................................................... 19-11
IDMA Interface Signals............................................................................................... 19-13
Level-Sensitive Mode.......................................................................................... 19-14
IDMA Operation.......................................................................................................... 19-16
stop_idma Command............................................................................................... 19-28
IDMA Programming Examples................................................................................... 19-30
Chapter 20
20.1.2
Features.......................................................................................................................... 20-2
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Controlling SCC Timing with RTS, CTS, and CD.................................................. 20-17
Switching Protocols............................................................................................. 20-25
Chapter 21
Features.......................................................................................................................... 21-2
SCC UART Parameter RAM......................................................................................... 21-3
Receiving Control Characters........................................................................................ 21-7
Handling Errors in the SCC UART Controller............................................................ 21-11
21.17
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SCC UART Transmit Buffer Descriptor (TxBD)........................................................ 21-18
SCC UART Programming Example............................................................................ 21-22
Chapter 22
SCC HDLC Channel Frame Transmission.................................................................... 22-2
SCC HDLC Commands................................................................................................. 22-5
SCC HDLC Receive Buffer Descriptor (RxBD)........................................................... 22-8
Accessing the HDLC Bus........................................................................................ 22-18
Chapter 23
23.4
Features.......................................................................................................................... 23-2
SCC BISYNC Parameter RAM..................................................................................... 23-3
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SCC BISYNC Commands............................................................................................. 23-4
SCC BISYNC Control Character Recognition.............................................................. 23-5
Sending and Receiving the Synchronization Sequence................................................. 23-9
SCC BISYNC Receive BD (RxBD) ........................................................................... 23-12
Programming the SCC BISYNC Controller................................................................ 23-17
SCC BISYNC Programming Example........................................................................ 23-18
23.12
Chapter 24
Features.......................................................................................................................... 24-1
SCC Transparent Channel Frame Reception Process.................................................... 24-2
Synchronization and the TSA.................................................................................... 24-5
End of Frame Detection............................................................................................. 24-5
Transparent Mode and the PSMR.................................................................................. 24-8
SCC Transparent Receive Buffer Descriptor (RxBD)................................................... 24-8
SCC Status Register in Transparent Mode (SCCS)..................................................... 24-12
24.14
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Chapter 25
Features.......................................................................................................................... 25-2
SCC Ethernet Parameter RAM...................................................................................... 25-7
Ethernet Mode Register (PSMR)................................................................................. 25-14
SCC Ethernet Receive BD........................................................................................... 25-16
Chapter 26
26.4.4
Features.......................................................................................................................... 26-2
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Chapter 27
Features.......................................................................................................................... 27-2
Disabling SMCs On-the-Fly...................................................................................... 27-8
SMC Receiver Full Sequence................................................................................ 27-9
Switching Protocols............................................................................................... 27-9
SMC in UART Mode................................................................................................... 27-10
Programming the SMC UART Controller............................................................... 27-11
Sending a Break....................................................................................................... 27-12
Handling Errors in the SMC UART Controller....................................................... 27-13
SMC UART RxBD.................................................................................................. 27-13
SMC Transparent Channel Transmission Process................................................... 27-21
SMC Transparent TxBD.......................................................................................... 27-27
27.4.10
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Chapter 28
Global MCC Parameters................................................................................................ 28-4
Channel-Specific Parameters......................................................................................... 28-5
Channel-Specific HDLC Parameters......................................................................... 28-5
Channel-Specific Transparent Parameters............................................................... 28-11
28.3.4.2.1
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AERM in Japanese SS7................................................................................... 28-25
Disabling SUERM........................................................................................... 28-26
Filtering Limitations........................................................................................ 28-27
Superchannels and Receiving.................................................................................. 28-30
MCC Initialization........................................................................................... 28-41
28.11
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Chapter 29
FCC Protocol-Specific Mode Registers (FPSMRx)...................................................... 29-7
FCC Function Code Registers (FCRx).................................................................... 29-13
FCC Event Registers (FCCEx)................................................................................ 29-14
FCC Interrupt Handling............................................................................................... 29-16
Re-Initialization Procedure.................................................................................. 29-16
FCC Receiver Full Sequence................................................................................... 29-21
Chapter 30
AAL0, AAL1, and AAL5
30.2.1.3
Features.......................................................................................................................... 30-1
ATM Controller Overview............................................................................................. 30-4
Transmitter Overview................................................................................................ 30-5
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ATM Pace Control (APC) Unit...................................................................................... 30-8
APC Modes and ATM Service Types........................................................................ 30-8
APC Unit Scheduling Mechanism............................................................................. 30-9
ATM Traffic Type .................................................................................................... 30-11
Determining the Priority of an ATM Channel ......................................................... 30-13
RM Cell Structure.................................................................................................... 30-25
RM Cell Rate Representation.............................................................................. 30-26
30.6
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30.10.2.3.4
ATM-Layer OAM Definitions................................................................................. 30-27
Receiving OAM F4 or F5 Cells............................................................................... 30-28
BRC Performance Calculations........................................................................... 30-32
ATM Layer Statistics ................................................................................................... 30-33
ATM-to-TDM Interworking ........................................................................................ 30-33
Timing Issues........................................................................................................... 30-35
CAS Support............................................................................................................ 30-35
ATM-to-ATM Data Forwarding............................................................................... 30-36
ATM Memory Structure............................................................................................... 30-36
VCI Filtering (VCIF)........................................................................................... 30-39
ATM Channel Code ............................................................................................. 30-41
AAL5-ABR Protocol-Specific RCT................................................................ 30-46
AAL1 CES Protocol-Specific RCT................................................................. 30-50
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VBR Protocol-Specific TCTE......................................................................... 30-57
ABR Protocol-Specific TCTE......................................................................... 30-59
OAM Performance Monitoring Tables.................................................................... 30-62
APC Parameter Tables......................................................................................... 30-64
ATM Controller Buffer Descriptors (BDs).............................................................. 30-66
Receive Buffer Operation.................................................................................... 30-67
Static Buffer Allocation................................................................................... 30-67
Free Buffer Pools............................................................................................. 30-69
ATM Controller Buffers....................................................................................... 30-71
ATM Exceptions .......................................................................................................... 30-81
UTOPIA Master Multiple PHY Operation.......................................................... 30-85
UTOPIA Slave Multiple PHY Operation............................................................ 30-87
30.12.2.2
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UTOPIA Loop-Back Modes................................................................................ 30-87
ATM Registers ............................................................................................................. 30-87
ATM Transmit Command............................................................................................ 30-93
Chapter 31
Features.......................................................................................................................... 31-1
Signaling Path............................................................................................................ 31-3
AAL1 CES Receiver Overview..................................................................................... 31-4
ATM-to-TDM ........................................................................................................ 31-7
TDM-to-ATM ........................................................................................................ 31-7
Timing Issues............................................................................................................. 31-8
Channel Associated Signaling (CAS) Support........................................................ 31-10
TDM-to-ATM CAS Support................................................................................ 31-13
ATM-to-TDM CAS Support................................................................................ 31-14
CAS Updates Using the Core (Optional) ........................................................ 31-15
ATM-to-TDM Adaptive Slip Control.......................................................................... 31-15
3-Step-SN Algorithm................................................................................................... 31-20
Pointer Verification Mechanism .................................................................................. 31-21
31.7
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Receive and Transmit Connection Tables (RCT, TCT)............................................... 31-25
AAL1 CES Protocol-Specific RCT..................................................................... 31-28
Outgoing CAS Status Register (OCASSR) ................................................................ 31-35
ATM Controller Buffers............................................................................................... 31-38
CES-Specific Additions to the MCC........................................................................... 31-44
Chapter 32
Features.......................................................................................................................... 32-3
Transmitter Overview................................................................................................ 32-5
Fixed Priority......................................................................................................... 32-6
AAL2 Tx Data Structures.......................................................................................... 32-8
32.4
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AAL2 Switching...................................................................................................... 32-22
AAL2 RX Data Structures....................................................................................... 32-23
SSSAR Receive Buffer Descriptor...................................................................... 32-33
AAL2 Parameter RAM................................................................................................ 32-35
Chapter 33
Features.......................................................................................................................... 33-1
IMA Versions Supported ........................................................................................... 33-3
PowerQUICC II Versions Supported......................................................................... 33-3
PHY-Layer Devices Supported.................................................................................. 33-3
ATM Features Not Supported.................................................................................... 33-4
IMA Protocol Overview ............................................................................................... 33-4
Transmit Architecture.............................................................................................. 33-11
33.3.2.3
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Differences in CTC Operation............................................................................. 33-16
Cell Reception Task............................................................................................. 33-17
IMA FCC Programming.......................................................................................... 33-26
FTIRRx............................................................................................................ 33-26
FCC Parameters................................................................................................... 33-26
IMA Root Table....................................................................................................... 33-27
IMA Group Tables................................................................................................... 33-29
ICP Cell Templates.......................................................................................... 33-33
IMA Receive Group Frame Size .................................................................... 33-39
IMA Link Transmit Table Entry.......................................................................... 33-41
IMA Link Receive Statistics Table...................................................................... 33-48
Transmit Queues.................................................................................................. 33-48
33.4.6.1
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IDCR FCC Parameter Shadow............................................................................ 33-52
IDCR Table Entry................................................................................................ 33-54
IDCR Events........................................................................................................ 33-55
Changing IMA Version............................................................................................ 33-58
System Definition................................................................................................ 33-59
Receive Group State Machine Control................................................................ 33-60
Receive Link Start-up Procedure......................................................................... 33-62
33.5.4.3.1
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Rx Steps........................................................................................................... 33-65
Rx Steps........................................................................................................... 33-67
Receive Event Response Procedures................................................................... 33-70
Transmit........................................................................................................... 33-74
Chapter 34
Features.......................................................................................................................... 34-1
Receive ATM Cell Functions..................................................................................... 34-4
Receive ATM 2-Cell FIFO .................................................................................... 34-6
Transmit ATM Cell Functions ................................................................................... 34-6
Transmit ATM 2-Cell FIFO................................................................................... 34-6
TC Layer Registers.................................................................................................... 34-7
34.4.1.2
34.4.2
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TC Layer General Event Register (TCGER)....................................................... 34-11
Transmit............................................................................................................... 34-13
Implementation Example............................................................................................. 34-15
Chapter 35
35.14
Fast Ethernet on the PowerQUICC II............................................................................ 35-2
Features.......................................................................................................................... 35-2
Ethernet Channel Frame Transmission.......................................................................... 35-5
Programming Model.................................................................................................... 35-11
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FCC Ethernet Mode Register (FPSMR).................................................................. 35-18
Chapter 36
Programming Model...................................................................................................... 36-5
Chapter 37
Features.......................................................................................................................... 37-1
External Synchronization Signals.............................................................................. 37-3
Transparent Synchronization Example...................................................................... 37-3
Chapter 38
38.3
Features.......................................................................................................................... 38-1
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The SPI as a Master Device....................................................................................... 38-3
Programming the SPI Registers..................................................................................... 38-6
SPI Buffer Descriptors (BDs).................................................................................. 38-13
SPI Transmit BD (TxBD).................................................................................... 38-15
Chapter 39
2
I C Controller
39.2
39.3
Features.......................................................................................................................... 39-2
2
I C Controller Clocking and Signal Functions.............................................................. 39-2
2
I C Controller Transfers ................................................................................................ 39-2
2
39.3.1
39.3.2
39.3.3
39.3.4
39.4
39.4.1
39.4.2
39.4.3
39.4.4
39.4.5
39.5
39.6
39.7
39.7.1
39.7.1.1
39.7.1.2
I C Master Write (Slave Read).................................................................................. 39-3
2
I C Loopback Testing................................................................................................ 39-4
2
I C Master Read (Slave Write).................................................................................. 39-4
2
I C Multi-Master Considerations .............................................................................. 39-5
2
I C Registers.................................................................................................................. 39-6
2
I C Mode Register (I2MOD)..................................................................................... 39-6
2
I C Address Register (I2ADD).................................................................................. 39-6
2
I C Baud Rate Generator Register (I2BRG) ............................................................. 39-7
2
I C Event/Mask Registers (I2CER/I2CMR) ............................................................. 39-7
2
I C Command Register (I2COM).............................................................................. 39-8
2
I C Parameter RAM....................................................................................................... 39-9
2
I C Commands............................................................................................................. 39-11
2
The I C Buffer Descriptor (BD) Table ........................................................................ 39-11
2
I C Buffer Descriptors (BDs) .................................................................................. 39-12
2
I C Receive Buffer Descriptor (RxBD)............................................................... 39-12
2
I C Transmit Buffer Descriptor (TxBD) ............................................................. 39-13
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Chapter 40
Features.......................................................................................................................... 40-1
Port Registers................................................................................................................. 40-1
Port Open-Drain Registers (PODRA–PODRD)........................................................ 40-1
Port Data Registers (PDATA–PDATD) ..................................................................... 40-2
Ports Tables.................................................................................................................... 40-7
Appendix A
MPC8260-Specific SPRs................................................................................................ A-3
Appendix B
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PowerQUICC II External Signals......................................................................................... 1-11
Remote Access Server Configuration................................................................................... 1-15
LAN-to-WAN Bridge Router Configuration ........................................................................ 1-17
PCI Configuration................................................................................................................. 1-22
PCI with 155-Mbps ATM Configuration.............................................................................. 1-22
PowerQUICC II as PCI Agent.............................................................................................. 1-23
PowerQUICC II Programming Model—Registers............................................................... 2-10
System Configuration and Protection Logic........................................................................... 4-3
Software Watchdog Timer Block Diagram............................................................................. 4-7
SIU Interrupt Configuration Register (SICR)....................................................................... 4-17
SIU Interrupt Priority Register (SIPRR)............................................................................... 4-18
SIPNR_L............................................................................................................................... 4-22
SIMR_H................................................................................................................................ 4-23
SIU Interrupt Vector Register (SIVEC) ................................................................................ 4-24
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SIU External Interrupt Control Register (SIEXR)................................................................ 4-26
Bus Configuration Register (BCR)....................................................................................... 4-27
LCL_ACR............................................................................................................................. 4-31
SIU Model Configuration Register (SIUMCR).................................................................... 4-33
Internal Memory Map Register (IMMR).............................................................................. 4-36
System Protection Control Register (SYPCCR)................................................................... 4-37
Local Bus Transfer Error Status and Control Register 1 (L_TESCR1)................................ 4-42
Local Bus Transfer Error Status and Control Register 2 (L_TESCR2)................................ 4-43
Time Counter Status and Control Register (TMCNTSC)..................................................... 4-44
Configuring Multiple Chips.................................................................................................. 5-12
PowerQUICC II External Signals........................................................................................... 6-2
Single-Beat and Burst Data Transfers................................................................................... 8-27
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9-8
28-Bit Extended Transfer to 32-Bit Port Size....................................................................... 8-28
MEI Cache Coherency Protocol—State Diagram (WIM = 001).......................................... 8-31
PCI Bridge Structure............................................................................................................... 9-2
Single Beat Write Example................................................................................................... 9-11
Burst Write Example............................................................................................................. 9-11
Target-Initiated Terminations................................................................................................ 9-12
PCI Configuration Type 0 Translation (Top = CONFIG_ADDR)
PCI Parity Operation............................................................................................................. 9-18
Address Decode Flow Chart for Embedded Utilities (DMA, Message Unit) Mastered
Address Map Example.......................................................................................................... 9-24
PCI Outbound Translation Address Registers (POTARx).................................................... 9-30
Discard Timer Control register (PTCR)................................................................................ 9-33
PCI Error Data Capture Register (PCI_EDCR).................................................................... 9-40
PCI Inbound Base Address Registers (PIBARx).................................................................. 9-43
PCI Bridge PCI Configuration Registers.............................................................................. 9-46
Vendor ID Register................................................................................................................ 9-47
9-13
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Revision ID Register............................................................................................................. 9-50
Subclass Code Register......................................................................................................... 9-51
PCI Bus Base Class Code Register....................................................................................... 9-51
Header Type Register............................................................................................................ 9-53
Subsystem Vendor ID Register ............................................................................................. 9-55
PCI Bus MAX LAT............................................................................................................... 9-58
PCI Bus Arbiter Configuration Register............................................................................... 9-59
Hot Swap Register Block...................................................................................................... 9-60
Data Structure for Register Initialization.............................................................................. 9-64
Outbound Message Registers (OMRx)................................................................................. 9-67
Outbound Doorbell Register (ODR)..................................................................................... 9-68
I2O Message Queue.............................................................................................................. 9-70
Inbound Free_FIFO Tail Pointer Register (IFTPR).............................................................. 9-72
Outbound Free_FIFO Head Pointer Register (OFHPR)....................................................... 9-74
Outbound FIFO Queue Port Register (OFQPR)................................................................... 9-78
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Inbound Message Interrupt Mask Register (IMIMR)........................................................... 9-82
DMA Byte Count Register [0–3] (DMABCRx)................................................................... 9-93
DMA Chain of Segment Descriptors.................................................................................... 9-96
PCI Bridge as an Agent, Operating from the PCI System Clock ......................................... 10-4
PCI Bridge as a Host, Generating the PCI System Clock..................................................... 10-4
System Clock Control Register (SCCR)............................................................................... 10-8
System Clock Mode Register (SCMR)................................................................................. 10-9
Partial Data Valid for 32-Bit Port Size Memory, Double-Word Transfer............................11-11
Base Registers (BRx) .......................................................................................................... 11-13
Option Registers (ORx)—SDRAM Mode .......................................................................... 11-15
ORx —GPCM Mode........................................................................................................... 11-17
ORx—UPM Mode .............................................................................................................. 11-19
Machine x Mode Registers (MxMR).................................................................................. 11-26
60x Bus-Assigned SDRAM Refresh Timer (PSRT)........................................................... 11-31
ACTTORW = 2 (2 Clock Cycles)....................................................................................... 11-40
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SDRAM Single-Beat Read, Page Closed, CL = 3.............................................................. 11-43
SDRAM Three-Beat Burst Write, Page Closed.................................................................. 11-45
Mode Data Bit Settings....................................................................................................... 11-47
GPCM Memory Device Interface....................................................................................... 11-55
GPCM Read Followed by Write (ORx[29–30] = 01)......................................................... 11-60
GPCM Read Followed by Write (ORx[29–30] = 10)......................................................... 11-61
RAM Array Indexing.......................................................................................................... 11-65
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Refresh Cycle (CBR) to EDO DRAM................................................................................ 11-99
External Master Configuration with SDRAM Device...................................................... 11-106
TAP Controller State Machine.............................................................................................. 13-3
Observe-Only Input Pin Cell (I.Obs).................................................................................... 13-4
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Various Configurations of a Single TDM Channel............................................................... 15-5
SI Status Registers (SIxSTR).............................................................................................. 15-25
Dual IDL Bus Application Example................................................................................... 15-26
IDL Bus Signals.................................................................................................................. 15-28
GCI Bus Signals.................................................................................................................. 15-31
Bank of Clocks...................................................................................................................... 16-5
Connection of the Slave Address.......................................................................................... 16-9
CMX SI1 Clock Route Register (CMXSI1CR).................................................................. 16-12
CMX SI2 Clock Route Register (CMXSI2CR).................................................................. 16-13
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19-6
Timer Global Configuration Register 1 (TGCR1)................................................................ 18-4
Timer Global Configuration Register 2 (TGCR2)................................................................ 18-5
Timer Event Registers (TER1–TER4).................................................................................. 18-8
SDMA Data Paths................................................................................................................. 19-1
Example IDMA Transfer Buffer States for a Memory-to-Memory Transfer
(Size = 128 Bytes)............................................................................................................ 19-8
IDMA BD Structure............................................................................................................ 19-25
SCC BD and Buffer Memory Structure.............................................................................. 20-12
DPLL Receiver Block Diagram.......................................................................................... 20-21
UART Character Format....................................................................................................... 21-1
Control Character Table........................................................................................................ 21-8
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SCC UART Interrupt Event Example................................................................................. 21-20
SCC Status Register for UART Mode (SCCS)................................................................... 21-21
SCC HDLC Transmit Buffer Descriptor (TxBD)............................................................... 22-11
CC HDLC Status Register (SCCS)..................................................................................... 22-14
Delayed RTS Mode............................................................................................................. 22-21
Classes of BISYNC Frames.................................................................................................. 23-1
SCC BISYNC Transmit BD (TxBD).................................................................................. 23-14
SCC Transparent Transmit Buffer Descriptor (TxBD)....................................................... 24-10
SCC Transparent Event Register (SCCE)/Mask Register (SCCM).................................... 24-11
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Ethernet Interrupt Events Example..................................................................................... 25-21
Synchronization with SMSYNx.......................................................................................... 27-23
Synchronization with the TSA............................................................................................ 27-24
SMC Transparent RxBD..................................................................................................... 27-26
TSTATE High Byte............................................................................................................... 28-7
Rx Internal State (RSTATE) High Byte.............................................................................. 28-10
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Interrupt Circular Table Entry............................................................................................. 28-38
Output Delay from CTS Asserted....................................................................................... 29-18
Using CD to Control Reception.......................................................................................... 29-20
General VCOFFSET Formula for Contiguous VCLTs....................................................... 30-16
ATM Address Recognition Flowchart ................................................................................ 30-19
ABR Transmit Flow............................................................................................................ 30-22
FMC, BRC Insertion........................................................................................................... 30-31
Format of User-Defined Cells............................................................................................. 30-32
External CAM Address in UDC Extended Address Mode................................................. 30-33
ATM-to-TDM Interworking................................................................................................ 30-34
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Example of a 1024-Entry Receive Connection Table......................................................... 30-42
Transmit Connection Table (TCT) Entry............................................................................ 30-50
AAL5 Protocol-Specific TCT............................................................................................. 30-55
AAL1 Protocol-Specific TCT............................................................................................. 30-56
AAL0 Protocol-Specific TCT............................................................................................. 30-57
OAM Performance Monitoring Table................................................................................. 30-62
ATM Pace Control Data Structure ...................................................................................... 30-64
Control Slot......................................................................................................................... 30-66
Free Buffer Pool Entry........................................................................................................ 30-70
User-Defined Cell—RxBD Extension................................................................................ 30-76
AAL0 TxBDs...................................................................................................................... 30-79
AAL1 Sequence Number (SN) Protection Table................................................................ 30-80
UTOPIA Master Mode Signals........................................................................................... 30-84
FCC ATM Mode Register (FPSMR) .................................................................................. 30-88
ATM Event Register (FCCE)/FCC Mask Register (FCCM) .............................................. 30-91
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AAL1 Transmit Cell Format................................................................................................. 31-3
AAL1 CES Receiver Data flow............................................................................................ 31-6
ATM-to-TDM Interworking.................................................................................................. 31-7
TDM-to-ATM Interworking.................................................................................................. 31-8
CAS Flow TDM-to-ATM.................................................................................................... 31-13
CAS Flow ATM-to-TDM.................................................................................................... 31-14
Data Structure for ATM-to-TDM Adaptive Slip Control ................................................... 31-16
Recoverable Sync Fail sequence options............................................................................ 31-20
3-Step-SN-Algorithm.......................................................................................................... 31-21
AAL1 CES RxBD............................................................................................................... 31-39
AAL1 Sequence Number (SN) Protection Table................................................................ 31-43
TDM-to-ATM Timing Issue................................................................................................ 31-45
AAL2 Switching Example.................................................................................................... 32-3
Round Robin Priority............................................................................................................ 32-6
Fixed Priority Mode.............................................................................................................. 32-7
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CPS Tx Queue Descriptor (TxQD)..................................................................................... 32-14
AAL2 Protocol-Specific Receive Connection Table (RCT)............................................... 32-24
Switch Receive/Transmit Buffer Descriptor....................................................................... 32-30
UDC Header Table.............................................................................................................. 32-38
AAL2 Interrupt Queue Entry CID ≠ 0................................................................................ 32-39
AAL2 Interrupt Queue Entry CID = 0................................................................................ 32-39
Transmit Queue Behavior: Link Clock Rate Same as TRL................................................ 33-14
Transmit Queue Behavior: Link Clock Rate Slower than TRL.......................................... 33-15
Transmit Queue Behavior: Link Clock Rate Faster than TRL, Worst-Case
33-9
IMA Group Transmit State (IGTSTATE)............................................................................ 33-32
IMA Group Receive State (IGRSTATE)............................................................................. 33-39
IMA Receive Group Frame Size (IGRSTATE) .................................................................. 33-40
IMA Link Transmit Control (ILTCNTL)............................................................................ 33-42
IMA Link Transmit State (ILTSTATE)............................................................................... 33-43
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IMA Transmit Interrupt Status (ITINTSTAT)..................................................................... 33-43
IMA Link Receive State (ILRSTATE)................................................................................ 33-47
IMA Delay Compensation Buffer....................................................................................... 33-49
Near-End versus Far-End.................................................................................................... 33-65
Serial ATM Using FCC2 and TC Blocks (Single Channel).................................................. 34-1
TC Layer Mode Register (TCMODEx)................................................................................ 34-8
TC Layer General Status Register (TCGSR)...................................................................... 34-12
Example of Serial ATM Application .................................................................................. 34-16
Ethernet Interrupt Events Example..................................................................................... 35-22
HDLC Address Recognition Example.................................................................................. 36-5
FCC HDLC Transmit Buffer Descriptor (TxBD)............................................................... 36-12
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SPMODE—SPI Mode Register............................................................................................ 38-6
SPIE/SPIM—SPI Event/Mask Registers.............................................................................. 38-9
SPI TxBD............................................................................................................................ 38-15
2
I C Controller Block Diagram.............................................................................................. 39-1
2
I C Master/Slave General Configuration.............................................................................. 39-2
2
I C Transfer Timing.............................................................................................................. 39-3
2
I C Master Write Timing ...................................................................................................... 39-3
2
I C Master Read Timing....................................................................................................... 39-4
2
I C Mode Register (I2MOD)................................................................................................ 39-6
2
I C Address Register (I2ADD)............................................................................................. 39-7
2
I C Baud Rate Generator Register (I2BRG)......................................................................... 39-7
2
I C Command Register (I2COM)......................................................................................... 39-8
2
I C Function Code Registers (RFCR/TFCR)..................................................................... 39-10
2
I C Memory Structure......................................................................................................... 39-12
2
I C RxBD............................................................................................................................ 39-13
2
I C TxBD............................................................................................................................ 39-14
Port Data Registers (PDATA–PDATD) ................................................................................ 40-3
Port Pin Assignment Register (PPARA–PPARD)................................................................. 40-4
Special Options Registers (PSORA–POSRD)...................................................................... 40-5
Port Functional Operation..................................................................................................... 40-6
Primary and Secondary Option Programming...................................................................... 40-8
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Serial Performance............................................................................................................... 1-13
Exception Classifications for the Processor Core................................................................. 2-22
Encoding the Interrupt Vector............................................................................................... 4-14
SCPRR_H Field Descriptions............................................................................................... 4-20
PPC_ACR Field Descriptions............................................................................................... 4-30
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Configuration EPROM Addresses.......................................................................................... 5-7
DP[0–7] Signal Assignments................................................................................................ 7-14
Transfer Type Encoding........................................................................................................ 8-10
Address and Size State Calculations..................................................................................... 8-19
POTARx Field Descriptions ................................................................................................. 9-31
POBARx Field Descriptions................................................................................................. 9-31
ESR Field Descriptions......................................................................................................... 9-36
PCI_EDCR Field Description............................................................................................... 9-40
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PITARx Field Descriptions................................................................................................... 9-42
PCI Bridge PCI Configuration Registers.............................................................................. 9-45
Vendor ID Register Description............................................................................................ 9-47
PCI Bus Programming Interface Register Description......................................................... 9-50
PCI Bus Cache Line Size Register Description.................................................................... 9-52
Subsystem Vendor ID Register Description.......................................................................... 9-56
PCI Bus Interrupt Line Register Description....................................................................... 9-57
PCI Bus Interrupt Pin Register Description.......................................................................... 9-57
PCI Bus MAX LAT Description........................................................................................... 9-58
PCI Bus Arbiter Configuration Register Field Description.................................................. 9-60
IFHPR Field Descriptions..................................................................................................... 9-71
IPHPR Field Descriptions..................................................................................................... 9-73
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OPTPR Field Descriptions.................................................................................................... 9-77
IFQPR Field Descriptions..................................................................................................... 9-78
DMASRx Field Descriptions................................................................................................ 9-91
SCCR Field Descriptions...................................................................................................... 10-8
60x Bus-to-Core Frequency................................................................................................ 10-11
Number of PSDVAL Assertions Needed for TA Assertion.................................................11-11
BRx Field Descriptions....................................................................................................... 11-13
ORx—GPCM Mode Field Descriptions............................................................................. 11-17
Option Register (ORx)—UPM Mode................................................................................. 11-19
Machine x Mode Registers (MxMR).................................................................................. 11-27
60x Bus-Assigned SDRAM Refresh Timer (PSRT)........................................................... 11-31
SDRAM Interface Commands............................................................................................ 11-36
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SDRAM Address Multiplexing (A16–A31)....................................................................... 11-38
SDRAM Device Address Port during read/write Command.............................................. 11-49
SDRAM Device Address Port during read/write Command.............................................. 11-51
Register Settings (Bank-Based Interleaving)...................................................................... 11-51
. Boot Bank Field Values after Reset .................................................................................. 11-62
UPM Routines Start Addresses........................................................................................... 11-65
RAM Word Bit Settings...................................................................................................... 11-71
UPM Address Multiplexing................................................................................................ 11-77
EDO Connection Field Value Example .............................................................................. 11-92
RISC Timer Table Parameter RAM.................................................................................... 14-23
SIx RAM Entry Descriptions.............................................................................................. 15-14
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GCI Signals......................................................................................................................... 15-31
Typical Baud Rates for Asynchronous Communication....................................................... 17-5
TMR1–TMR4 Field Descriptions......................................................................................... 18-6
IDMA Transfer Parameters................................................................................................... 19-6
Valid Memory-to-Memory STS/DTS Values...................................................................... 19-22
Valid STS/DTS Values for Peripherals ............................................................................... 19-23
IDMA BD Field Descriptions............................................................................................. 19-25
IDMA Bus Exceptions........................................................................................................ 19-28
GSMR_H Field Descriptions................................................................................................ 20-3
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UART-Specific SCC Parameter RAM Memory Map........................................................... 21-4
Control Character Table, RCCM, and RCCR Descriptions.................................................. 21-8
DSR Fields Descriptions..................................................................................................... 21-11
PSMR UART Field Descriptions........................................................................................ 21-13
SCCE/SCCM Field Descriptions for UART Mode ........................................................... 21-21
UART SCCS Field Descriptions......................................................................................... 21-22
Transmit Errors ................................................................................................................... 22-6
SCC HDLC RxBD Status and Control Field Descriptions................................................... 22-8
SCC BISYNC Parameter RAM Memory Map..................................................................... 23-3
BSYNC Field Descriptions................................................................................................... 23-8
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SCCE/SCCM Field Descriptions........................................................................................ 23-16
SCC Transparent RxBD Status and Control Field Descriptions........................................... 24-9
SCC Transparent TxBD Status and Control Field Descriptions......................................... 24-10
SCCE/SCCM Field Descriptions........................................................................................ 25-20
SMC UART and Transparent Parameter RAM Memory Map ............................................. 27-6
RFCR/TFCR Field Descriptions........................................................................................... 27-8
SMC UART RxBD Field Descriptions............................................................................... 27-14
SMC Transparent TxBD Field Descriptions....................................................................... 27-27
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SMC GCI Parameter RAM Memory Map......................................................................... 27-31
TSTATE High-Byte Field Descriptions ................................................................................ 28-7
RSTATE High-Byte Field Descriptions............................................................................. 28-10
CHAMR Field Descriptions—CES Mode.......................................................................... 28-16
Channel-Specific Parameters for SS7................................................................................. 28-19
Parameter Values for SUERM in Japanese SS7.................................................................. 28-24
SS7 Configuration Register Fields Description.................................................................. 28-24
Channel Extra Parameters................................................................................................... 28-28
MCCE/MCCM Register Field Descriptions....................................................................... 28-37
GUN Error Recovery—.29µm (HiP3) Rev A.1 and B.2 Silicon........................................ 28-42
RxBD Field Descriptions.................................................................................................... 28-44
FCC Parameter RAM Common to All Protocols except ATM........................................... 29-12
ATM Service Types............................................................................................................... 30-9
VCOFFSET Calculation Examples for Contiguous VCLTs............................................... 30-16
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Pre-Assigned Header Values at the UNI ............................................................................. 30-27
Pre-Assigned Header Values at the NNI ............................................................................. 30-28
ATM Parameter RAM Map................................................................................................. 30-36
Receive and Transmit Connection Table Sizes................................................................... 30-41
AAL5-Specific TCT Field Descriptions............................................................................. 30-55
AAL0-Specific TCT Field Descriptions............................................................................. 30-57
APC Parameter Table.......................................................................................................... 30-64
APC Priority Table Entry.................................................................................................... 30-65
Free Buffer Pool Parameter Table....................................................................................... 30-70
AAL5 TxBD Field Descriptions......................................................................................... 30-77
AAL1 TxBD Field Descriptions......................................................................................... 30-78
AAL0 TxBD Field Descriptions......................................................................................... 30-79
FCC ATM Mode Register (FPSMR) .................................................................................. 30-88
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FCCE/FCCM Field Descriptions........................................................................................ 30-91
CAS Routing Table Entry Field Descriptions..................................................................... 31-13
AAL1 CES Protocol-Specific RCT Field Descriptions...................................................... 31-29
SSSAR TxBD Field Descriptions....................................................................................... 32-19
Switch RxBD Field Descriptions....................................................................................... 32-31
AAL2 Interrupt Queue Entry CID ≠ 0 Field Descriptions.................................................. 32-39
FCC Parameter RAM Additions......................................................................................... 33-26
IMACNTL Field Descriptions............................................................................................ 33-29
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IGRCNTL Field Descriptions............................................................................................. 33-39
IGRSTATE Field Descriptions............................................................................................ 33-39
IRGFS Field Descriptions................................................................................................... 33-40
IMA Link Transmit Table Entry ........................................................................................ 33-41
ILTCNTL Field Descriptions.............................................................................................. 33-42
ITINTSTAT Field Descriptions........................................................................................... 33-44
ILRSTATE Field Descriptions ............................................................................................ 33-47
TCERx Field Descriptions.................................................................................................. 34-10
Programming GFMR and FPSMR to Setup the FCC2....................................................... 34-17
Enable FCC2....................................................................................................................... 34-17
Programming the CPM MUX for a TI Application............................................................ 34-17
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FCCE/FCCM Field Descriptions........................................................................................ 35-21
RxBD Field Descriptions.................................................................................................... 35-23
Ethernet TxBD Field Definitions........................................................................................ 35-26
FPSMR Field Descriptions .................................................................................................. 36-8
RxBD field Descriptions..................................................................................................... 36-11
HDLC TxBD Field Descriptions ....................................................................................... 36-13
FCCE/FCCM Field Descriptions........................................................................................ 36-15
SPMODE Field Descriptions................................................................................................ 38-6
RFCR/TFCR Field Descriptions......................................................................................... 38-12
2
I C Parameter RAM Memory Map....................................................................................... 39-9
RFCR/TFCR Field Descriptions......................................................................................... 39-10
2
I C Transmit/Receive Commands....................................................................................... 39-11
2
I C TxBD Status and Control Bits...................................................................................... 39-14
PPAR Field Descriptions....................................................................................................... 40-4
Port A—Dedicated Pin Assignment (PPARA = 1) ............................................................... 40-8
Port B Dedicated Pin Assignment (PPARB = 1) ............................................................... 40-12
Port C Dedicated Pin Assignment (PPARC = 1) ............................................................... 40-14
Port D Dedicated Pin Assignment (PPARD = 1) .............................................................. 40-17
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Tables
Table
Page
Number
Title
Number
User-Level PowerPC SPRs.................................................................................................... A-1
Supervisor-Level PowerPC Registers.................................................................................... A-2
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About This Book
The primary objective of this manual is to help communications system designers build systems using the
PowerQUICC II™ and to help software designers provide operating systems and user-level applications
to take fullest advantage of the PowerQUICC II.
This manual supports the following devices: the MPC8250, the MPC8255, the MPC8260, the MPC8264,
the MPC8265, and the MPC8266. Throughout this manual they are collectively referred to as the
PowerQUICC II. Device numbers are cited only if information does not pertain to all devices (refer to
Table ii).
Although this book describes aspects regarding the PowerPC™ architecture that are critical for
understanding the PowerQUICC II core, it does not contain a complete description of the architecture.
Where additional information might help the reader, references are made to Programming Environments
Documentation” for ordering information.
The information in this book is subject to change without notice, as described in the disclaimers on the title
page of this book. As with any technical documentation, it is the readers’ responsibility to be sure they are
using the most recent version of the documentation. For more information, contact your sales
representative.
Reference Manual Revision History
Substantive differences between this revision and revision 1 of this manual are summarized in Table i.
Users who are familiar with revision 1 should verify if a given portion has changed by referring to the
corresponding portion in this current manual.
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lxxvii
Us
Table i. Changes to MPC8260 Family Reference Manual, Rev. 1
Substantive Changes
Additional New
Description
References
Previous supplemental documents supported
functionality chapter
They have been incorporated into this manual.
Note: The “References” list is a complete list.
Existing
chapter
Information from these previous supplemental
documents has also been incorporated into existing
chapters. This information includes new sections
Note: The “References” list includes the chapters that
contain the greatest additions, but it does not list
every chapter that has additions.
Errata (documentation)
Chapter updates
Incorporation of Errata to MPC8260 User’s Manual
(MPC8260UMAD/D). Errata that were not included in the
last version of MPC8260UMAD/D (Rev. 6, 10/2002) are
indicated in Appendix B.
Includes new or updated content as well as
organizational changes.
Note: The “References” list includes the chapters that
contain the greatest additions, but it does not list
every chapter that has been updated.
Some descriptions in this manual pertain only to specific devices or to all devices in a specific silicon
revision. Table ii provides examples of how these descriptions are indicated. Users should verify whether
a given portion of this manual pertains to their device.
Table ii. Device- and Silicon-Specific Notations
Format
Usage
Example
Text interrupt notes Placed at beginning of sections or chapters. Indicates that all Beginning of Chapter 28,
specific devices.
Note: This notation format is also used within chapters to
stress information that is common to all devices.
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Table ii. Device- and Silicon-Specific Notations (continued)
Usage
Format
Footnotes
Example
• Tables—Attached to rows, columns, or entries. Often used
to designate variation in bit definition.
Text in-line
Parenthetical comments placed within a paragraph or bullet
item list. Indicates a portion of the text pertains only to specific • First bullet item in Section 1.2.2,
Before Using this Manual—Important Note
Before using this manual, determine whether it is the latest revision and if there are errata or addenda. To
locate any published errata or updates for this document, refer to the world-wide web at
www.freescale.com.
Audience
This manual is intended for software and hardware developers and application programmers who want to
develop products for the PowerQUICC II. It is assumed that the reader has a basic understanding of
computer networking, OSI layers, and RISC architecture. In addition, it is assumed that the reader has a
basic understanding of the communications protocols described here. Where it is considered useful,
additional sources are provided that provide in-depth discussions of such topics.
Organization
Following is a summary and a brief description of the chapters of this manual:
•
operation and listing basic features.
features. It roughly follows the structure of this book, summarizing the relevant features and
providing references for the reader who needs additional information.
described in further detail in subsequent chapters.
mapped in memory. It includes cross references that indicate where the registers are described
in detail.
•
functions which provide various monitors and timers, and the 60x bus configuration.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
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lxxix
•
power management of the PowerQUICC II.
the PowerQUICC II signals.
implement the PowerPC architecture.
PowerQUICC II.
gluelessly bridge PCI agents to a host processor that implements the PowerPC architecture and
how it is compliant with PCI Specification Revision 2.2.
maximum of eight memory banks shared between a general-purpose chip-select machine
(GPCM) and three user-programmable machines (UPMs).
configuration of a level-2 cache.
access port (TAP), which is fully compatible with the IEEE 1149.1 Standard Test Access Port
and Boundary Scan Architecture.
•
operation of the various communications protocols supported by the PowerQUICC II.
CPM.
system start-up, initialization and operation, protection, as well as the external system bus.
connects the physical layer—UTOPIA, MII, modem lines,
baud-rate generators (BRGs) that can be used with the FCCs, SCCs, and SMCs.
identical 16-bit or two 32-bit general-purpose timers.
(SDMA) channels on the PowerQUICC II.
communications controllers (SCC), which can be configured independently to implement
different protocols for bridging functions, routers, and gateways, and to interface with a wide
variety of standard WANs, LANs, and proprietary networks.
asynchronous receiver transmitter (UART) protocol that is used for sending low-speed data
between devices.
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protocol.
byte-oriented BISYNC protocol developed by IBM for use in networking products.
transparent mode (also called totally transparent mode), which provides a clear channel on
which the SCC can send or receive serial data without bit-level manipulation.
protocol.
AppleTalk.
controllers, full-duplex ports that can be configured independently to support one of three
protocols—UART, transparent, or general-circuit interface (GCI).
multi-channel controller (MCC), which handles up to 128 serial, full-duplex data channels.
communications controllers (FCCs), which are SCCs optimized for synchronous high-rate
protocols.
ATM controller, which provides the ATM and AAL layers of the ATM protocol. The ATM
controller performs segmentation and reassembly (SAR) functions of AAL5, AAL1, and
AAL0, and most of the common parts convergence sublayer (CP-CS) of these protocols.
emulation service (CES) using ATM adaptation layer type 1 (AAL1) on the PowerQUICC II.
layer type 2 (AAL2) CPS, CPS switching, and SSSAR.
multiplexing for ATM (IMA) microcode.
support applications which receive ATM traffic over the standard serial protocols like E1, T1,
and xDSL via its serial interface (SIx TDMx and NMSI) ports because of its internally
implemented TC-layer functionality.
Ethernet IEEE 802.3 protocol.
protocol.
transparent protocol.
allows the PowerQUICC II to exchange data between other PowerQUICC II chips, the
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lxxxi
MC68360, the MC68302, the M68HC11, and M68HC05 microcontroller families, and
peripheral devices such as EEPROMs, real-time clocks, A/D converters, and ISDN devices.
inter-integrated circuit (I2C®) controller, which allows data to be exchanged with other I2C
devices, such as microcontrollers, EEPROMs, real-time clock devices, and A/D converters.
signal in the I/O ports can be configured as a general-purpose I/O signal or as a signal dedicated
to supporting communications devices, such as SMCs, SCCs. MCCs, and FCCs.
•
•
•
incorporated in the G2 core.
previous revision of this manual.
This book also includes an index and a glossary.
Suggested Reading
This section lists additional reading that provides background for the information in this manual as well as
general information about the PowerPC architecture.
MPC82xx Documentation
Supporting documentation for the PowerQUICC II can be accessed through the world-wide web at
www.freescale.com. This documentation includes technical specifications, reference materials, and
detailed applications notes.
Architecture Documentation
Architecture documentation is organized in the following types of documents:
•
Manuals—These books provide details about individual implementations of the PowerPC
architecture and are intended to be used in conjunction with the Programming Environments
Manual. These include the following:
— G2 Core Reference Manual (Freescale order #: G2CORERM/D, REV 0)
•
Programming environments manuals—These books provide information about resources defined
by the PowerPC architecture that are common to processors that implement the PowerPC
architecture. There are two versions, one that describes the functionality of the combined 32- and
64-bit architecture models and one that describes only the 32-bit model. The PowerQUICC II
adheres to the 32-bit architecture definition.
— Programming Environments for 32-Bit Implementations of the PowerPC Architecture, REV 2
(Freescale order #: MPCFPE32B/D)
•
The Programmer’s Pocket Reference Guide for the PowerPC Architecture:
MPCPRGREF/D—This provides an overview of registers, instructions, and exceptions for 32-bit
implementations.
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•
Application notes—These short documents contain useful information about specific design issues
useful to programmers and engineers working with Freescale’s processors.
For a current list of documentation, refer to www.freescale.com.
Conventions
This document uses the following notational conventions:
Table 1:
Bold entries in figures and tables showing registers and parameter RAM should
be initialized by the user.
mnemonics
Instruction mnemonics are shown in lowercase bold.
Italics indicate variable command parameters, for example, bcctrx.
Book titles in text are set in italics.
italics
0x0
Prefix to denote hexadecimal number
0b0
Prefix to denote binary number
rA, rB
rD
Instruction syntax used to identify a source GPR
Instruction syntax used to identify a destination GPR
REG[FIELD]
Abbreviations or acronyms for registers or buffer descriptors are shown in
uppercase text. Specific bits, fields, or numerical ranges appear in brackets. For
example, MSR[LE] refers to the little-endian mode enable bit in the machine state
register.
x
In certain contexts, such as in a signal encoding or a bit field, indicates a don’t
care.
n
¬
&
|
Used to express an undefined numerical value
NOT logical operator
AND logical operator
OR logical operator
Acronyms and Abbreviations
Table iii contains acronyms and abbreviations used in this document. Note that the meanings for some
acronyms (such as SDR1 and DSISR) are historical, and the words for which an acronym stands may not
be intuitively obvious.
Table iii. Acronyms and Abbreviated Terms
Term
Meaning
A/D
ALU
ATM
BD
Analog-to-digital
Arithmetic logic unit
Asynchronous transfer mode
Buffer descriptor
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Table iii. Acronyms and Abbreviated Terms (continued)
Meaning
Term
BIST
Built-in self test
BPU
BRI
Branch processing unit
Basic rate interface.
Bus unit ID
BUID
CAM
CEPT
Content-addressable memory
Conference des administrations Europeanes des Postes et Telecommunications (European
Conference of Postal and Telecommunications Administrations).
CMX
CPM
CR
CPM multiplexing logic
Communication processor module
Condition register
CRC
CTR
Cyclic redundancy check
Count register
DABR
DAR
Data address breakpoint register
Data address register
DEC
Decrementer register
DMA
DPLL
DRAM
DSISR
DTLB
EA
Direct memory access
Digital phase-locked loop
Dynamic random access memory
Register used for determining the source of a DSI exception
Data translation lookaside buffer
Effective address
EEST
EPROM
FPR
Enhanced Ethernet serial transceiver
Erasable programmable read-only memory
Floating-point register
FPSCR
FPU
Floating-point status and control register
Floating-point unit
GCI
General circuit interface
GPCM
GPR
GUI
General-purpose chip-select machine
General-purpose register
Graphical user interface
HDLC
High-level data link control
Inter-integrated circuit
2
I C
IDL
Inter-chip digital link
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Table iii. Acronyms and Abbreviated Terms (continued)
Meaning
Term
IEEE
Institute of Electrical and Electronics Engineers
Infrared Data Association
Integrated services digital network
Instruction translation lookaside buffer
Integer unit
IrDA
ISDN
ITLB
IU
JTAG
LIFO
LR
Joint Test Action Group
Last-in-first-out
Link register
LRU
LSB
Least recently used
Least-significant byte
lsb
Least-significant bit
LSU
MAC
MESI
MMU
MSB
msb
Load/store unit
Multiply accumulate
Modified/exclusive/shared/invalid—cache coherency protocol
Memory management unit
Most-significant byte
Most-significant bit
MSR
NaN
NIA
Machine state register
Not a number
Next instruction address
Nonmultiplexed serial interface
No operation
NMSI
No-op
OEA
OSI
Operating environment architecture
Open systems interconnection
Peripheral component interconnect
Personal Computer Memory Card International Association
Processor identification register
Primary rate interface
PCI
PCMCIA
PIR
PRI
PVR
RISC
RTOS
RWITM
Rx
Processor version register
Reduced instruction set computing
Real-time operating system
Read with intent to modify
Receive
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Table iii. Acronyms and Abbreviated Terms (continued)
Meaning
Term
SCC
Serial communication controller
SCP
SDLC
SDMA
SI
Serial control port
Synchronous Data Link Control
Serial DMA
Serial interface
SIMM
SIU
Signed immediate value
System interface unit
SMC
SNA
SPI
Serial management controller
Systems network architecture
Serial peripheral interface
SPR
SPRGn
SRAM
SRR0
SRR1
TAP
Special-purpose register
Registers available for general purposes
Static random access memory
Machine status save/restore register 0
Machine status save/restore register 1
Test access port
TB
Time base register
TDM
TLB
Time-division multiplexed
Translation lookaside buffer
Time-slot assigner
TSA
Tx
Transmit
UART
UIMM
UISA
UPM
USART
USB
VA
Universal asynchronous receiver/transmitter
Unsigned immediate value
User instruction set architecture
User-programmable machine
Universal synchronous/asynchronous receiver/transmitter
Universal serial bus
Virtual address
VEA
XER
Virtual environment architecture
Register used primarily for indicating conditions such as carries and overflows for integer operations
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PowerPC Architecture Terminology Conventions
Table iv lists certain terms used in this manual that differ from the architecture terminology conventions.
Table iv. Terminology Conventions
The Architecture Specification
Data storage interrupt (DSI)
This Manual
DSI exception
Simplified mnemonics
ISI exception
Extended mnemonics
Instruction storage interrupt (ISI)
Interrupt
Exception
Privileged mode (or privileged state)
Problem mode (or problem state)
Real address
Supervisor-level privilege
User-level privilege
Physical address
Translation
Relocation
Storage (locations)
Memory
Storage (the act of)
Access
Table v describes instruction field notation conventions used in this manual.
Table v. Instruction Field Conventions
The Architecture Specification
Equivalent to:
BA, BB, BT
BF, BFA
D
crbA, crbB, crbD (respectively)
crfD, crfS (respectively)
d
DS
ds
FLM
FM
FXM
CRM
RA, RB, RT, RS
rA, rB, rD, rS (respectively)
SI
SIMM
U
IMM
UI
UIMM
/, //, ///
0...0 (shaded)
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Part I
Overview
Intended Audience
Part I is intended for readers who need a high-level understanding of the PowerQUICC II.
Contents
Part I provides a high-level description of the PowerQUICC II, describing general operation and listing
basic features.
•
features. It roughly follows the structure of this book, summarizing the relevant features and
providing references for the reader who needs additional information.
•
•
in memory. It includes cross references that indicate where the registers are described in detail.
Conventions
Part I uses the following notational conventions:
mnemonics
Instruction mnemonics are shown in lowercase bold.
italics
Italics indicate variable command parameters, for example, bcctrx.
Book titles in text are set in italics.
0x0
Prefix to denote hexadecimal number
0b0
Prefix to denote binary number
rA, rB
rD
Instruction syntax used to identify a source GPR
Instruction syntax used to identify a destination GPR
REG[FIELD]
Abbreviations or acronyms for registers or buffer descriptors are shown in
uppercase text. Specific bits, fields, or numerical ranges appear in brackets. For
example, MSR[LE] refers to the little-endian mode enable bit in the machine state
register.
x
In certain contexts, such as in a signal encoding or a bit field, indicates a don’t
care.
n
Indicates an undefined numerical value
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
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I-1
Acronyms and Abbreviations
Table I-1 contains acronyms and abbreviations that are used in this document.
Table I-1. Acronyms and Abbreviated Terms
Term
Meaning
ATM
BD
Asynchronous Mode
Buffer descriptor
BPU
COP
CP
Branch processing unit
Common on-chip processor
Communications processor
Communications processor module
Cyclic redundancy check
Count register
CPM
CRC
CTR
DABR
DAR
DEC
DMA
DPLL
DRAM
DTLB
EA
Data address breakpoint register
Data address register
Decrementer register
Direct memory access
Digital phase-locked loop
Dynamic random access memory
Data translation lookaside buffer
Effective address
FCC‘
FPR
Fast communications controller
Floating-point register
GPCM
GPR
HDLC
General-purpose chip-select machine
General-purpose register
High-level data link control
Inter-integrated circuit
2
I C
IEEE
ISDN
ITLB
IU
Institute of Electrical and Electronics Engineers
Integrated services digital network
Instruction translation lookaside buffer
Integer unit
JTAG
LRU
LSU
MCC
Joint Test Action Group
Least recently used (cache replacement algorithm)
Load/store unit
Multi-channel controller
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Table I-1. Acronyms and Abbreviated Terms (continued)
Meaning
Term
MII
Media-independent interface
MMU
MSR
NMSI
OEA
OSI
Memory management unit
Machine state register
Nonmultiplexed serial interface
Operating environment architecture
Open systems interconnection
Peripheral component interconnect
Reduced instruction set computing
Real-time clock
PCI
RISC
RTC
RTOS
Rx
Real-time operating system
Receive
SCC
SDLC
SDMA
SI
Serial communications controller
Synchronous data link control
Serial DMA
Serial interface
SIU
System interface unit
SMC
SPI
Serial management controller
Serial peripheral interface
Special-purpose register
Static random access memory
Test access port
SPR
SRAM
TAP
TB
Time base register
TDM
TLB
Time-division multiplexed
Translation lookaside buffer
Time-slot assigner
TSA
Tx
Transmit
UART
UISA
UPM
VEA
Universal asynchronous receiver/transmitter
User instruction set architecture
User-programmable machine
Virtual environment architecture
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I-3
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Chapter 1
Overview
The PowerQUICC II™ is a versatile communications processor that integrates on one chip a
high-performance PowerPC™ RISC microprocessor, a very flexible system integration unit, and many
communications peripheral controllers that can be used in a variety of applications, particularly in
communications and networking systems.
The G2 core is an embedded variant of the MPC603e™ microprocessor with 16 Kbytes of instruction
cache and 16 Kbytes of data cache. The system interface unit (SIU) consists of a flexible memory
controller that interfaces to almost any user-defined memory system, a 60x-to-PCI bus bridge (MPC8250,
MPC8265, and MPC8266 only), and many other peripherals making this device a complete system on a
chip.
The communications processor module (CPM) includes all the peripherals found in the PowerQUICC
(MPC860), with the addition of three high-performance communication channels that support new
emerging protocols (for example, 155-Mbps ATM and Fast Ethernet). The PowerQUICC II has dedicated
hardware that can handle up to 256 full-duplex, time-division-multiplexed logical channels.
This document describes the functional operation of PowerQUICC II, with an emphasis on peripheral
functions. Chapter 2, “G2 Core,” is an overview of the microprocessor core; detailed information about
the core can be found in the G2 Core Reference Manual (order number: G2CORERM/D).
1.1
Features
The following is an overview of the PowerQUICC II feature set:
•
Dual-issue integer core
— A core version of the MPC603e microprocessor
— System core microprocessor supporting the following frequencies:
– 133–200 MHz (.29µm (HiP3) devices)
– 150–300 MHz (.25µm (HiP4) devices)
— Separate 16-Kbyte data and instruction caches:
– Four-way set associative
– Physically addressed
– LRU replacement algorithm
— PowerPC architecture-compliant memory management unit (MMU)
— Common on-chip processor (COP) test interface
— Supports bus snooping for cache coherency
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1-1
Overview
— Floating-point unit (FPU) supports floating-point arithmetic.
— Support for cache locking.
•
•
•
Low-power consumption
Separate power supply for internal logic (2.5 V) and for I/O (3.3 V)
Separate PLLs for G2 core and for the CPM
— G2 core and CPM can run at different frequencies for power/performance optimization
— Internal G2 core/bus clock multiplier that provides 1.5:1, 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 4.5:1, 5:1,
5.5:1, 6:1, 7:1, 8:1 ratios
— Internal CPM/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios
64-bit data and 32-bit address 60x bus
•
— Bus supports multiple master designs
— Supports single transfers and burst transfers
— 64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller
— Supports data parity or ECC and address parity
32-bit data and 18-bit address local bus
•
•
— Single-master bus, supports external slaves
— Eight-beat burst transfers
— 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller
60x-to-PCI bridge (MPC8250, MPC8265, and MPC8266 only)
— Programmable host bridge and agent
— 32-bit data bus, 66 MHz, 3.3 V
— Synchronous and asynchronous 60x and PCI clock modes
— All internal address space available to external PCI host
— DMA for memory block transfers
— PCI-to-60x address remapping
•
•
System interface unit (SIU)
— Clock synthesizer
— Reset controller
— Real-time clock (RTC) register
— Periodic interrupt timer
— Hardware bus monitor and software watchdog timer
— IEEE 1149.1 JTAG test access port
Twelve-bank memory controller
— Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash and other
user-definable peripherals
— Byte write enables and selectable parity generation
— 32-bit address decodes with programmable bank size
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Overview
— Three user programmable machines, general-purpose chip-select machine, and page mode
pipeline SDRAM machine
— Byte selects for 64-bit bus width (60x) and for 32-bit bus width (local)
— Dedicated interface logic for SDRAM
Disable CPU mode
•
•
Communications processor module (CPM)
— Embedded 32-bit communications processor (CP) uses a RISC architecture for flexible support
for communications peripherals
— Interfaces to G2 core through on-chip dual-port RAM and DMA controller. (Dual-port RAM
size is 24 Kbyte on 0.29µm (HiP3) silicon and 32 Kbyte on 0.25µm (HiP4) silicon.)
— Serial DMA channels for receive and transmit on all serial channels
— Parallel I/O registers with open-drain and interrupt capability
— Virtual DMA functionality executing memory to memory and memory to I/O transfers
— Three fast communication controllers (FCCs) (two on the MPC8255) supporting the following
protocols
– 10/100-Mbit Ethernet/IEEE 802.3 CDMA/CS interface through media independent
interface (MII)
– ATM (not on MPC8250)—full-duplex SAR at 155 Mbps, UTOPIA interface, AAL5,
AAL1, AAL0 protocols, TM 4.0 CBR, VBR, UBR, ABR traffic types, up to 64 K external
connections
– Transparent
– HDLC—up to T3 rates (clear channel)
— Two multichannel controllers (MCCs) (only MCC2 on the MPC8250 and the MPC8255)
– Two 128 serial full-duplex data channels (for a total of 256 64 Kbps channels). Each MCC
can be split into four subgroups of 32 channels each.
– Almost any combination of subgroups can be multiplexed to single or multiple TDM
interfaces
— Four serial communications controllers (SCCs) identical to those on the MPC860, supporting
the digital portions of the following protocols:
– Ethernet/IEEE 802.3 CDMA/CS
– HDLC/SDLC and HDLC bus
– Universal asynchronous receiver transmitter (UART)
– Synchronous UART
– Binary synchronous (BiSync) communications
– Transparent
— Two serial management controllers (SMCs), identical to those of the MPC860
– Provide management for BRI devices as general-circuit interface (GCI) controllers in time-
division-multiplexed (TDM) channels
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1-3
Overview
– Transparent
– UART (low-speed operation)
— One serial peripheral interface identical to the MPC860 SPI
2
2
— One I C controller (identical to the MPC860 I C controller)
– Microwire compatible
– Multiple-master, single-master, and slave modes
— Up to eight TDM interfaces (four on the MPC8250 and the MPC8255)
– Supports two groups of four TDM channels for a total of eight TDMs (one group of four on
the MPC8250 and the MPC8255)
– 2,048 bytes of SI RAM
– Bit or byte resolution
– Independent transmit and receive routing, frame synchronization.
– Supports T1, CEPT, T1/E1, T3/E3, pulse code modulation highway, ISDN basic rate, ISDN
primary rate, Freescale interchip digital link (IDL), general circuit interface (GCI), and
user-defined TDM serial interfaces
— Eight transfer transmission convergence (TC) layers between the TDMs and FCC2 to support
inverse multiplexing for ATM capabilities (IMA) (MPC8264 and MPC8266 only)
— Eight independent baud rate generators and 20 input clock pins for supplying clocks to FCC,
SCC, and SMC serial channels
— Four independent 16-bit timers that can be interconnected as two 32-bit timers
TC layer (MPC8264 and MPC8266 only)
•
— Each of the 8 TDM channels is routed in hardware to a TC layer block
– Protocol-specific overhead bits may be discarded or routed to other controllers by the SI
– Performing ATM TC layer functions (according to ITU-T I.432)
– Transmit (Tx) updates
– Cell HEC generation
– Payload scrambling using self synchronizing scrambler (programmable by the
user)
– Coset generation (programmable by the user)
– Cell rate by inserting idle/unassigned cells
– Receive (Rx) updates
– Cell delineation using bit by bit HEC checking and programmable ALPHA and
DELTA parameters for the delineation state machine
– Payload descrambling using self synchronizing scrambler (programmable by the
user)
– Coset removing (programmable by the user)
– Filtering idle/unassigned cells (programmable by the user)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
1-4
Freescale Semiconductor
Overview
– Performing HEC error detection and single bit error correction (programmable by
user)
– Generating loss of cell delineation status/interrupt (LOC/LCD)
— Operates with FCC2 (UTOPIA 8)
— Provides serial loop back mode
— Cell echo mode is provided
— Supports both FCC transmit modes
– External rate mode—Idle cells are generated by the FCC (microcode) to control data rate.
– Internal rate mode (sub-rate)—FCC transfers only the data cells using the required data rate.
The TC layer generates idle/unassigned cells to maintain the line bit rate.
— Supports TC-layer and PMD-WIRE interface (according to the ATM-Forum af-phy-0063.000)
— Cell counters for performance monitoring
– 16-bit counters count
– HEC error cells
– HEC single bit error and corrected cells
– Idle/unassigned cells filtered
– Idle/unassigned cells transmitted
– Transmitted ATM cells
– Received ATM cells
– Maskable interrupt is sent to the host when a counter expires
— Overrun (Rx cell FIFO) and underrun (Tx cell FIFO) condition produces maskable interrupt
— May be operated at E1 and DS-1 rates. In addition, xDSL applications at bit rates up to 10 Mbps
are supported
•
PCI bridge (MPC8250, MPC8265, and MPC8266 only)
— PCI Specification Revision 2.2 compliant and supports frequencies up to 66 MHz
— On-chip arbitration
— Support for PCI to 60x memory and 60x memory to PCI streaming
— PCI Host Bridge or Peripheral capabilities
— Includes 4 DMA channels for the following transfers:
– PCI-to-60x to 60x-to-PCI
– 60x-to-PCI to PCI-to-60x
– PCI-to-60x to PCI-to-60x
– 60x-to-PCI to 60x-to-PCI
— Includes all of the configuration registers (which are automatically loaded from the EPROM
and used to configure the PowerQUICC II) required by the PCI standard as well as message
and doorbell registers
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
1-5
Overview
— Supports the I O standard
2
— Hot-Swap friendly (supports the Hot Swap Specification as defined by PICMG 2.1 R1.0
August 3, 1998)
— Support for 66 MHz, 3.3 V specification
— 60x-PCI bus core logic which uses a buffer pool to allocate buffers for each port
— Makes use of the local bus signals, so there is no need for additional pins
1.2
Architecture Overview
The PowerQUICC II has two external buses to accommodate bandwidth requirements from the high-speed
system core and the very fast communications channels. As shown in Figure 1-1, the PowerQUICC II has
three major functional blocks:
•
•
•
A 64-bit G2 core derived from the MPC603e with MMUs and cache
A system interface unit (SIU)
A communications processor module (CPM)
Figure 1-1 shows the block diagram of the superset PowerQUICC II device. Features that are device- or
silicon-specific are noted.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
1-6
Freescale Semiconductor
Overview
16 Kbytes
I-Cache
I-MMU
System Interface Unit
(SIU)
60x Bus
PCI Bus2
G2 Core
16 Kbytes
D-Cache
Bus Interface Unit
32 bits, up to 66 MHz
60x-to-PCI
Bridge 2
D-MMU
or
60x-to-Local
Bridge
Local Bus3
32 bits
Communication Processor Module (CPM)
Memory Controller
Timers
Serial
DMAs
Interrupt
Controller
Dual-Port RAM1
Clock Counter
Parallel I/O
32-bit RISC Microcontroller
and Program ROM
Virtual
System Functions
IDMAs5
Baud Rate
Generators
IMA 4
Microcode
7
6,7
I2C
MCC2 FCC1 FCC2 FCC3
SCC1 SCC2 SCC3 SCC4 SMC1 SMC2
SPI
MCC1
TC Layer Hardware4
Time Slot Assigner
Serial Interface
Non-Multiplexed
I/O
8 TDM Ports8
3 MII
2 UTOPIA
Ports6
Ports9
Notes:
1
2
3
4
5
6
24 Kbytes on .29µm (HiP3) devices/ 32 Kbytes on .25µm (HiP4) devices
MPC8250, MPC8265, and MPC8266 only
Not on the MPC8250
7
8
9
Not on the MPC8255
Up to 66 MHz on .29µm devices/ Up to 83 MHz on .25µm devices
MPC8264 and MPC8266 only
4 on the MPC8250 and MPC8255
2 on the MPC8255
2 on .29µm devices/ 4 on .25µm devices
Figure 1-1. PowerQUICC II Block Diagram
Both the system core and the CPM have an internal PLL, which allows independent optimization of the
frequencies at which they run. The system core and CPM are both connected to the 60x bus.
1.2.1
G2 Core
The G2 core is derived from the MPC603e microprocessor with power management modifications. The
core is a high-performance low-power implementation of the family of reduced instruction set computer
(RISC) microprocessors. The G2 core implements the 32-bit portion of the PowerPC architecture, which
provides 32-bit effective addresses, integer data types of 8, 16, and 32 bits. The G2 cache provides
snooping to ensure data coherency with other masters. This helps ensure coherency between the CPM and
system core.
The core includes 16 Kbytes of instruction cache and 16 Kbytes of data cache. It has a 64-bit
split-transaction external data bus, which is connected directly to the external PowerQUICC II pins.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
1-7
Overview
The G2 core has an internal common on-chip (COP) debug processor. This processor allows access to
internal scan chains for debugging purposes. It is also used as a serial connection to the core for emulator
support.
The G2 core performance for the SPEC 95 benchmark for integer operations ranges between 4.4 and 5.1
at 200 MHz. In Dhrystone 2.1 MIPS, the G2 core is 280 MIPS at 200 MHz (compared to 86 MIPS of the
MPC860 at 66 MHz).
The G2 core can be disabled. In this mode, the PowerQUICC II functions as a slave peripheral to an
external core or to another PowerQUICC II device with its core enabled.
1.2.2
System Interface Unit (SIU)
The SIU consists of the following:
•
•
•
A 60x-compatible parallel system bus configurable to 64-bit data width. The PowerQUICC II
supports 64-, 32-, 16-, and 8-bit port sizes. The PowerQUICC II internal arbiter arbitrates between
internal components that can access the bus (system core, PCI bridge (MPC8250, MPC8265, and
MPC8266 only), CPM, and one external master). This arbiter can be disabled, and an external
arbiter can be used if necessary.
A local (32-bit data, 32-bit internal and 18-bit external address) bus. This bus is used to enhance
the operation of the very high-speed communication controllers. Without requiring extensive
manipulation by the core, the bus can be used to store connection tables for ATM or buffer
descriptors (BDs) for the communication channels or raw data that is transmitted between
channels. The local bus is synchronous to the 60x bus and runs at the same frequency.
The local bus can be configured as a 32-bit data and up to 66 MHz PCI (version 2.1) bus
(MPC8250, MPC8265, and MPC8266 only). In PCI mode the bus can be programmed as a host or
as an agent. The PCI bus can be configured to run synchronously or asynchronously to the 60x bus.
The PowerQUICC II has an internal PCI bridge with an efficient 60x-to-PCI DMA for memory
block transfers.
•
•
Applications that require both the local bus and PCI bus need to connect an external PCI bridge
(MPC8250, MPC8265, and MPC8266 only).
Memory controller supporting 12 memory banks that can be allocated for either the system or the
local bus. The memory controller is an enhanced version of the MPC860 memory controller. It
supports three user-programmable machines. Besides all MPC860 features, the memory controller
also supports SDRAM with page mode and address data pipeline.
•
•
Supports JTAG controller IEEE 1149.1 test access port (TAP).
A bus monitor that prevents 60x bus lock-ups, a real-time clock, a periodic interrupt timer, and
other system functions useful in embedded applications.
•
Glueless interface to L2 cache (MPC2605) and 4-/16-K-entry CAM
(MCM69C232/MCM69C432).
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
1-8
Freescale Semiconductor
Overview
1.2.3
Communications Processor Module (CPM)
The CPM contains features that allow the PowerQUICC II to excel in a variety of applications targeted
mainly for networking and telecommunication markets.
The CPM is a superset of the MPC860 PowerQUICC CPM, with enhancements on the CP performance
and additional hardware and microcode routines that support high bit rate protocols like ATM (up to 155
Mbps full-duplex) and Fast Ethernet (100-Mbps full-duplex).
The following list summarizes the major features of the CPM:
•
The CP is an embedded 32-bit RISC controller residing on a separate bus (CPM local bus) from
the 60x bus (used by the system core). With this separate bus, the CP does not affect the
performance of the G2 core. The CP handles the lower layer tasks and DMA control activities,
leaving the G2 core free to handle higher layer activities. The CP has an instruction set optimized
for communications, but can also be used for general-purpose applications, relieving the system
core of small often repeated tasks.
•
•
Two serial DMA (SDMA) that can do simultaneous transfers, optimized for burst transfers to the
60x bus and to the local bus.
Three full-duplex, serial fast communications controllers (FCCs) supporting ATM (155 Mbps)
protocol through UTOPIA2 interface (there are two UTOPIA interfaces on the PowerQUICC II),
IEEE 802.3 and Fast Ethernet protocols, HDLC up to E3 rates (45 Mbps) and totally transparent
operation. Each FCC can be configured to transmit fully transparent and receive HDLC or
vice-versa. (Note that the MPC8250 does not support ATM (155 Mbps) protocol.)
•
Two multichannel controllers (MCCs) (one on the MPC8250 and MPC8255) that can handle an
aggregate of 256 X 64 Kbps HDLC or transparent channels, multiplexed on up to eight TDM
interfaces. The MCC also supports super-channels of rates higher than 64 Kbps and subchanneling
of the 64-Kbps channels.
•
•
Four full-duplex serial communications controllers (SCCs) supporting IEEE802.3/Ethernet, high-
level synchronous data link control, HDLC, local talk, UART, synchronous UART, BISYNC, and
transparent.
Two full-duplex serial management controllers (SMC) supporting GCI, UART, and transparent
operations
2
•
•
Serial peripheral interface (SPI) and I C bus controllers
Time-slot assigner (TSA) that supports multiplexing of data from any of the four SCCs, three
FCCs, and two SMCs.
1.3
Software Compatibility Issues
As much as possible, the PowerQUICC II CPM features were made similar to those of the previous
PowerQUICC devices (MPC860). The code flow ports easily from previous devices to the PowerQUICC
II, except for new protocols supported by the PowerQUICC II.
Although many registers are new, most registers retain the old status and event bits, so an understanding
of the programming models of the MC68360, MPC860, or MPC85015 is helpful. Note that the
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
1-9
Overview
PowerQUICC II initialization code requires changes from the MPC860 initialization code (Freescale
provides reference code).
1.3.1
Signals
Figure 1-2 shows PowerQUICC II signals grouped by function. Note that many of these signals are
multiplexed and this figure does not indicate how these signals are multiplexed.
NOTE
A bar over a signal name indicates that the signal is active low—for
example, BB (bus busy). Active-low signals are referred to as asserted
(active) when they are low and negated when they are high. Signals that are
not active low, such as TSIZ[0–3] (transfer size signals) are referred to as
asserted when they are high and negated when they are low.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
1-10
Freescale Semiconductor
Overview
VCCSYN/GNDSYN/VCCSYN1//VDDH/
VDD/VSS
⎯⎯⎯>100
32 <⎯⎯> A[0–31]
PCI_PAR1/L_A14
SMI/PCI_FRAME1/L_A15
PCI_TRDY1/L_A16
<⎯⎯>
<⎯⎯>
<⎯⎯>
<⎯⎯>
<⎯⎯>
<⎯⎯>
<⎯⎯>
<⎯⎯>
<⎯⎯>
<⎯⎯>
<⎯⎯>
<⎯⎯>
<⎯⎯⎯
<⎯⎯>
<⎯⎯>
<⎯⎯>
<⎯⎯>
<⎯⎯>
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
5
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
<⎯⎯> TT[0–4]
<⎯⎯> TSIZ[0–3]
<⎯⎯> TBST
CKSTOP_OUT/PCI_IRDY1/L_A17
PCI_STOP1/L_A18
<⎯⎯> GBL/IRQ1
<⎯⎯> CI/BADDR29/IRQ2
<⎯⎯> WT/BADDR30/IRQ3
<⎯⎯⎯ L2_HIT/IRQ4
<⎯⎯> CPU_BG/BADDR31/IRQ5
⎯⎯⎯> CPU_DBG
⎯⎯⎯> CPU_BR
<⎯⎯> BR
<⎯⎯> BG
<⎯⎯> ABB/IRQ2
<⎯⎯> TS
<⎯⎯> AACK
<⎯⎯> ARTRY
PCI_DEVSEL1/L_A19
L
O
C
A
L
PCI_IDSEL1/L_A20
PCI_PERR1/L_A21
PCI_SERR/1L_A22
PCI_REQ01/L_A23
CPCI_HS_ES1/PCI_REQ11/L_A24
PCI_GNT01/L_A25
6
0
x
CPCI_HS_LED1/PCI_GNT11/L_A26
CPCI_HS_ENUM1/PCI_CLK1/L_A27
CORE_SRESET/PCI_RST1/L_A28
PCI_INTA1/L_A29
B
U
S
PCI_REQ21/L_A30
<⎯⎯> DBG
<⎯⎯> DBB/IRQ3
B
U
S
DLLOUT1/L_A31
PCI_AD[0–31]1/LCL_D[0–31]
PCI_C/BE[0–3]1/LCL_DP[0–3]
<⎯⎯> 32
64 <⎯⎯> D[0–63]
<⎯⎯>
4
1
1
1
<⎯⎯> NC/DP0/RSRV/EXT_BR2
<⎯⎯> IRQ1/DP1/EXT_BG2
<⎯⎯> IRQ2/DP2/TLBISYNC/EXT_DBG2
PCI_CFG[3–0]1/LBS[0–3]/
<⎯⎯⎯
4
1
<⎯⎯> IRQ3/DP3/CKSTP_OUT/EXT_BR3
LSDDQM[0–3]/LWE[0–3]
PCI_MODCK_H01/LGPL0/LSDA10
PCI_MODCK_H11/LGPL1/LSDWE
PCI_MODCK_H21/LGPL2/LSDRAS/LOE
PCI_MODCK_H31/LGPL3/LSDCAS
<⎯⎯⎯
<⎯⎯⎯
<⎯⎯⎯
<⎯⎯⎯
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
<⎯⎯> IRQ4/DP4/CORE_SRESET/EXT_BG3
<⎯⎯> IRQ5/DP5/TBEN/EXT_DBG3
<⎯⎯> IRQ6/DP6/CSE0
<⎯⎯> IRQ7/DP7/CSE1
<⎯⎯> PSDVAL
<⎯⎯> TA
<⎯⎯> TEA
<⎯⎯> IRQ0/NMI_OUT
<⎯⎯> IRQ7/INT_OUT/APE
M
E
M
C
LPBS/LGPL4/LUPMWAIT/LGTA <⎯⎯>
<⎯⎯>
LWR <⎯⎯>
PCI_MODCK1/LGPL5
PA[0–31] <⎯⎯> 32
PB[4–31] <⎯⎯> 28
PC[0–31] <⎯⎯> 32
PD[4–31] <⎯⎯> 28
P
I
O
10 ⎯⎯⎯> CS[0–9]
1
1
2
1
1
8
1
1
1
1
1
1
1
1
1
1
1
<⎯⎯> CS[10]/BCTL1
<⎯⎯> CS[11]/AP[0]
⎯⎯⎯> BADDR[27–28]
⎯⎯⎯> ALE
1
⎯⎯⎯> 1
PCI_RST /PORESET
M
E
M
C
RSTCONF⎯⎯⎯> 1
⎯⎯⎯> BCTL0
HRESET<⎯⎯>
1
1
⎯⎯⎯> PWE[0–7]/PSDDQM[0–7]/PBS[0–7]
⎯⎯⎯> PSDA10/PGPL0
⎯⎯⎯> PSDWE/PGPL1
⎯⎯⎯> POE/PSDRAS/PGPL2
⎯⎯⎯> PSDCAS/PGPL3
<⎯⎯> PGTA/PUPMWAIT/PGPL4/PPBS
⎯⎯⎯> PSDAMUX/PGPL5
<⎯⎯− TMS
R
S
T
SRESET<⎯⎯>
QREQ<⎯⎯⎯ 1
XFC⎯⎯⎯> 1
CLKIN1⎯⎯⎯> 1
TRIS⎯⎯⎯> 1
C
L
K
BNKSEL[0]/TC[0]/AP[1]/MODCK1<⎯⎯>
BNKSEL[1]/TC[1]/AP[2]/MODCK2<⎯⎯>
BNKSEL[2]/TC[2]/AP[3]/MODCK3<⎯⎯>
1
1
1
J
T
A
G
<⎯⎯⎯ TDI
<⎯⎯− TCK
<⎯⎯− TRST
−⎯⎯> TDO
PCI_MODE2
CLKIN22
⎯⎯⎯> 1
⎯⎯⎯> 1
NC ⎯⎯⎯> 2
1
2
MPC8250, MPC8265, and MPC8266 only.
MPC8250, MPC8265, and MPC8266 only. This is a spare pin on all other devices.
Figure 1-2. PowerQUICC II External Signals
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
1-11
Overview
1.4
Differences between MPC860 and PowerQUICC II
The following MPC860 features are not included in the PowerQUICC II.
•
•
•
•
•
•
•
•
•
•
•
•
•
On-chip crystal oscillators (must use external oscillator)
4-MHz oscillator (input clock must be at the bus speed)
Low power (stand-by) modes
Battery-backup real-time clock (must use external battery-backup clock)
BDM (COP offers most of the same functionality)
True little-endian mode
PCMCIA interface
Infrared (IR) port
QMC protocol in SCC (256 HDLC channels are supported by the MCCs)
Multiply and accumulate (MAC) block in the CPM
Centronics port (PIP)
Pulse-width modulated outputs
SCC Ethernet controller option to sample 1 byte from the parallel port when a receive frame is
complete
•
Parallel CAM interface for SCC (Ethernet)
1.5
Serial Protocol Table
Table 1-1 summarizes available protocols for each serial port.
Table 1-1. PowerQUICC II Serial Protocols
Port
Port
FCC
SCC
MCC
SMC
1
ATM (Utopia)
100BaseT
10BaseT
HDLC
√
√
√
√
√
√
√
√
√
√
√
√
HDLC_BUS
Transparent
UART
√
√
√
DPLL
Multichannel
√
1
Not on the MPC8250
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
1-12
Freescale Semiconductor
Overview
1.6
PowerQUICC II Configurations
The PowerQUICC II offers flexibility in configuring the device for specific applications. The functions
mentioned in the above sections are all available in the device, but not all of them can be used at the same
time. This does not imply that the device is not fully activated in any given implementation: The CPM
architecture has the advantage of using common hardware resources for many different protocols, and
applications. Two physical factors limit the functionality in any given system—pinout and performance.
1.6.1
Pin Configurations
Some pins have multiple functions. Choosing one function may preclude the use of another. Information
1.6.2
Serial Performance
Serial performance depends on a number of factors:
•
•
•
•
Serial rate versus CPM clock frequency for adequate sampling on serial channels
Serial rate and protocol versus CPM clock frequency for CP protocol handling
Serial rate and protocol versus bus bandwidth
Serial rate and protocol versus system core clock for adequate protocol handling
The second item above is addressed in this section—the CP’s ability to handle high bit-rate protocols in
parallel. Slow bit-rate protocols do not significantly affect those numbers.
Table 1-2 describes a few options to configure the fast communications channels on the PowerQUICC II.
The frequency specified is the minimum CPM frequency necessary to run the mentioned protocols
concurrently at full-duplex.
1
Table 1-2. Serial Performance
2
FCC1
FCC2
FCC3
MCC
CPM Clock
60x Bus Clock
155-Mbps ATM
100 BaseT
100 BaseT
100 BaseT
100 BaseT
100 BaseT
133 MHz
133 MHz
133 MHz
133 MHz
166 MHz
133 MHz
133 MHz
166 MHz
166 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
155-Mbps ATM
100 BaseT
128 * 64 Kbps channels
128 * 64 Kbps channels
256 * 64 Kbps channels
256 * 64 Kbps channels
256 * 64 Kbps
100 BaseT
155-Mbps ATM
100 BaseT
45-Mbps HDLC
45-Mbps HDLC
100 BaseT
100 BaseT
256 * 64 Kbps
16 * 576 Kbps
1
Not on the MPC8255.
2
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
1-13
Overview
Table 1-3. MPC8250 Serial Performance
60x Bus
Clock
FCC 1
FCC 2
FCC 3
MCC
CPM Clock
100 BaseT
100 BaseT
100 BaseT
45-Mbps
100 BaseT
133 MHz
133 MHz
133 MHz
133 MHz
133MHz
133 MHz
133 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
100 BaseT
128 * 64 Kbps channels
128 * 64 Kbps channels
128 * 64 Kbps channels
128 * 64 Kbps channels
8 * 576 Kbps channels
128 * 64 Kbps channels
100 BaseT
45-Mbps HDLC
45-Mbps HDLC
100 BaseT
45-Mbps
45-Mbps
100 BaseT
100 BaseT
100 BaseT
45-Mbps
100 BaseT
100 BaseT
FCCs can also be used to run slower HDLC or 10 BaseT, for example. The CP’s RISC architecture has the
advantage of using common hardware resources for all FCCs.
1.7
Application Examples
The PowerQUICC II can be configured to meet many system application needs, as described in the
NOTE: Differences between PowerQUICC II Devices
differences in features between a given device and the following
descriptions.
1.7.1
Communication Systems
The following sections describe the following examples of communication systems:
•
•
•
•
•
•
1.7.1.1
Remote Access Server
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
1-14
Freescale Semiconductor
Overview
PowerQUICC II
TDM0
SDRAM/DRAM/SRAM
Quad
T1
60x Bus
Channelized Data
(up to 256 channels)
Framer
TDM7
SDRAM/DRAM/SRAM
155 Mbps
ATM PHY
UTOPIA Multi PHY
10/100BaseT
ATM
Local Bus
Connection Tables
(optional)
or
or
MII
Transceiver
DSP Bank
E3 clear channel
(takes one TDM)
Framer
Slaves
on
Local
Bus
Slow
Comm
PHY
SMC/I2C/SPI/SCC
Figure 1-3. Remote Access Server Configuration
In this application, eight TDM ports are connected to external framers. In the PowerQUICC II, each group
of four ports support up to 128 channels. One TDM interface can support 32–128 channels. The
PowerQUICC II receives and transmits data in transparent or HDLC mode, and stores or retrieves the
channelized data from memory. The data can be stored either in memory residing on the 60x bus or in
memory residing on the local bus.
The main trunk can be configured as 155 Mbps full-duplex ATM, using the UTOPIA interface, or as
10/100 BaseT Fast Ethernet with MII interface, or as a high-speed serial channel (up to 45 Mbps). In ATM
mode, there may be a need to store connection tables in external memory on the local bus; for example,
128 active internal connections require 8 Kbytes of dual-port RAM. The need for local bus depends on the
total throughput of the system. The PowerQUICC II supports automatic (without software intervention)
cross connect between ATM and MCC, routing ATM AAL1 frames to MCC slots.
The local bus can be used as an interface to a bank of DSPs that can run code that performs analog modem
signal modulation. Data to and from the DSPs can be transferred through the parallel bus with the internal
virtual IDMA.
The PowerQUICC II memory controller supports many types of memories, including EDO DRAM and
page-mode, pipeline SDRAM for efficient burst transfers.
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Overview
1.7.1.2
Regional Office Router
Figure 1-4 shows a regional office router configuration (refer to note at the beginning of Section 1.7,
PowerQUICC II
TDM0
Quad
T1
Framer
TDM3
SDRAM/DRAM/SRAM
MII
10/100BaseT
10/100BaseT
60x Bus
Channelized Data
(up to 128 channels)
Transceiver
Slow
Comm
PHY
SMC/I2C/SPI/SCC
Figure 1-4. Regional Office Router Configuration
In this application, the PowerQUICC II is connected to four TDM interfaces channalizing up to 128
channels. Each TDM port supports 32–128 channels. If 128 channels are needed, each TDM port can be
configured to support 32 channels. This example has two MII ports for 10/100 BaseT LAN connections.
In all the examples, the SCC ports can be used for management.
1.7.1.3
LAN-to-WAN Bridge Router
Figure 1-5 shows a LAN-to-WAN router configuration, which is similar to the previous example (refer to
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Overview
PowerQUICC II
10/100BaseT
MII
Transceiver
SDRAM/DRAM/SRAM
Data
60x Bus
155 Mbps
UTOPIA Multi PHY
ATM PHY
SDRAM/DRAM/SRAM
155 Mbps
ATM PHY
UTOPIA Multi PHY
10/100BaseT
Local Bus
ATM Connection
Tables (optional)
or
MII
Transceiver
Slow
Comm
PHY
SMC/I2C/SPI/SCC
Figure 1-5. LAN-to-WAN Bridge Router Configuration
1.7.1.4
Cellular Base Station
Figure 1-6 shows a cellular base station configuration (refer to note at the beginning of Section 1.7,
PowerQUICC II
SDRAM/DRAM/SRAM
TDM0
Framer
60x Bus
Channelized Data
(up to 256 channels)
TDM1
DSP Bank
Local Bus
Slow
Comm
PHY
Slaves
on
Local
Bus
SMC/I2C/SPI/SCC
Figure 1-6. Cellular Base Station Configuration
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Overview
Here the PowerQUICC II channelizes two E1s (up to 256, 16-Kbps channels).
The local bus can control a bank of DSPs. Data to and from the DSPs can be transferred through the
parallel bus to the host port of the DSPs with the internal virtual IDMA.
2
The slow communication ports (SCCs, SMCs, I C, SPI) can be used for management and debug functions.
1.7.1.5
Telecommunications Switch Controller
Figure 1-7 shows a telecommunications switch controller configuration (refer to note at the beginning of
PowerQUICC II
155 Mbps
UTOPIA Multi PHY
ATM
PHY
SDRAM/DRAM/SRAM
60x Bus
10/100BaseT
10/100BaseT
MII
Transceiver
SDRAM/DRAM/SRAM
ATM
Connection
Tables
Local Bus
Slow
Comm
PHY
SMC/I2C/SPI/SCC
(10BaseT)
Figure 1-7. Telecommunications Switch Controller Configuration
The PowerQUICC II CPM supports a total aggregate throughput of 710 Mbps at 133 MHz. This includes
two full-duplex 100 BaseT and one full-duplex 155 Mbps for ATM. The MPC603e core can operate at a
different (higher) speed, if the application requires it.
1.7.1.6
SONET Transmission Controller
Figure 1-8 shows a SONET transmission controller configuration (refer to note at the beginning of
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Overview
PowerQUICC II
TDM0
576 Kbps
SONET
Transceivers
TDM3
SDRAM/DRAM/SRAM
60x Bus
Channelized Data
(up to 16 channels)
MII
10/100BaseT
Transceiver
SDRAM/DRAM/SRAM
ATM
Connection
Tables
Local Bus
Slow
Comm
PHY
SMC/I2C/SPI/SCC
(10BaseT)
Figure 1-8. SONET Transmission Controller Configuration
In this application, the PowerQUICC II implements super channeling with the MCC. Nine 64-Kbps
channels are combined to form a 576-Kbps channel. The PowerQUICC II at 133 MHz can support up to
sixteen 576-Kbps superchannels. The PowerQUICC II also supports subchanneling (under 64 Kbps) with
its MCC.
1.7.2
Bus Configurations
The following sections describe the following possible bus configurations:
•
•
•
•
•
•
1.7.2.1 Basic System
In the basic system configuration, shown in Figure 1-9, the PowerQUICC II core is enabled and uses the
64-bit 60x data bus. The 32-bit local bus data is needed to store connection tables for many active ATM
connections. The local bus may also be used to store data that does not need to be heavily processed by the
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Overview
core. The CP can store large data frames in the local memory without interfering with the operation of the
PowerQUICC II
SDRAM/SRAM/DRAM/Flash
60x Bus
PHY
Communication
Channels
SDRAM/SRAM/DRAM
155 Mbps
Local Bus
ATM
UTOPIA
ATM
PHY
Connection Tables
Figure 1-9. Basic System Configuration
1.7.2.2
High-Performance Communication
Figure 1-10 shows a high-performance communication configuration.
PowerQUICC II A
SDRAM/SRAM/DRAM
Local Bus
ATM
Communication
Channels
PHY
Connection Tables
SDRAM/SRAM/DRAM/Flash
155 Mbps
60x Bus
UTOPIA
ATM
PHY
PowerQUICC II B
(master/slave)
Communication
Channels
PHY
SDRAM/SRAM/DRAM
155 Mbps
ATM
Local Bus
ATM
UTOPIA
PHY
Connection Tables
or
PCI Bus
Figure 1-10. High-Performance Communication
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Overview
Serial throughput is enhanced by connecting one PowerQUICC II in master or slave mode (with system
core enabled or disabled) to another PowerQUICC II in master mode with the core enabled. The core in
PowerQUICC II A can access the memory on the local bus of PowerQUICC II B.
1.7.2.3
High-Performance System Microprocessor
Figure 1-11 shows a configuration with a high-performance system microprocessor (MPC750). (Refer to
MPC750
32-Kbyte I cache
32-Kbyte D cache
Backside
Cache
PowerQUICC II (slave)
SDRAM/SRAM/DRAM
60x Bus
Communication
Channels
PHY
SDRAM/SRAM/DRAM
155 Mbps
Local Bus
ATM
Connection Tables
UTOPIA
ATM
PHY
Figure 1-11. High-Performance System Microprocessor Configuration
In this system, the MPC603e core internal is disabled and an external high-performance microprocessor is
connected to the 60x bus.
1.7.2.4
PCI
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Overview
PowerQUICC II
SDRAM/SRAM/DRAM/Flash
60x Bus
Communication
Channels
PHY
PCI Bus
Host or Agent
Figure 1-12. PCI Configuration
In this system the local bus is configured as PCI (33-MHz 32-bit data bus version 2.1). The PowerQUICC
II can be configured as a host or as an agent on the PCI bus. The 60x bus and PCI bus are asynchronous;
there is no frequency dependency between the two. The PCI bus is a 3.3-V bus.
1.7.2.5
PCI with 155-Mbps ATM
PCI Bus
PCI Bridge
PowerQUICC II
SDRAM/SRAM/DRAM
60x Bus
Communication
Channels
PHY
SDRAM/SRAM/DRAM
ATM
PHY
Local Bus
ATM
UTOPIA
Connection Tables
Figure 1-13. PCI with 155-Mbps ATM Configuration
This system supports PCI and implements a 155-Mbps, full-duplex ATM with more than 128 active
connections. The PowerQUICC II cannot support both functions simultaneously. The local bus is needed
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Overview
to store ATM connection tables. Therefore, an external PCI bridge is necessary. In systems with fewer than
128 active connections or where the ATM average bit rate is lower that 155 Mbps, the local bus may not
be necessary to store connection tables, and it may be possible to use it as PCI bus.
1.7.2.6
PowerQUICC II as PCI Agent
Figure 1-14 shows the configuration when the PowerQUICC II acts as the PCI agent (refer to note at the
PowerQUICC II
SDRAM/SRAM/DRAM
ATM Connection Tables
and/or
Communication Data
60x Bus
Communication
Channels
PHY
PCI Bus
ATM
PHY
Agent
UTOPIA
Host
System Bus
PCI Bridge
Host
Processor
Memory
Figure 1-14. PowerQUICC II as PCI Agent
In this system, the PowerQUICC II is a PCI agent on an I/O card and the PCI host resides on the PCI bus.
An external PCI bridge is used to connect the host to the PCI bus. The internal PCI bridge in the
PowerQUICC II is used to bridge between the PCI bus and the 60x bus on the PowerQUICC II.
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Overview
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Chapter 2
G2 Core
The PowerQUICC II contains an embedded version of the MPC603e™ microprocessor. This chapter
provides an overview of the basic functionality of the processor core. For detailed information regarding
the processor refer to the following:
•
•
G2 Core Reference Manual
The Programming Environments for 32-Bit Implementation s of the PowerPC Architecture
This section describes the details of the processor core, provides a block diagram showing the major
functional units, and describes briefly how those units interact.
The signals associated with the processor core are described individually in Chapter 7, “60x Signals.”
2.1
Overview
The processor core is a low-power implementation of the family reduced instruction set computing (RISC)
microprocessors that implement the PowerPC architecture. The processor core implements the 32-bit
portion of the PowerPC architecture, which supports 32-bit effective addresses.
Figure 2-1 is a block diagram of the processor core.
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2-1
G2 Core
64-Bit (Two Instructions)
Branch
Processing
Unit
64-Bit
Sequential
Fetcher
64-Bit
CTR
CR
LR
Instruction
Queue
System
Register
Unit
64-Bit (Two Instructions)
Dispatch Unit
64-Bit
+
Instruction Unit
32-Bit
64-Bit
Floating-
Point Unit
Integer
Unit
GPR File
FPR File
Load/Store
Unit
GP Rename
Registers
FP Rename
Registers
/
+
+
/
*
*
+
XER
FPSCR
32-Bit
Completion
Unit
D MMU
I MMU
SRs
SRs
64-Bit
DBAT
Array
IBAT
Array
DTLB
ITLB
Power
Dissipation
Control
Time Base
Counter/
Decrementer
16-Kbyte
D Cache
16-Kbyte
I Cache
Tags
Tags
JTAG/COP
Interface
Clock
Multiplier
Touch Load Buffer
Copy-Back Buffer
Core Interface
32-Bit Address Bus
32-/64-Bit Data Bus
Figure 2-1. PowerQUICC II Integrated Processor Core Block Diagram
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G2 Core
The processor core is a superscalar processor that can issue and retire as many as three instructions per
clock. Instructions can execute out of order for increased performance; however, the processor core makes
completion appear sequential.
The processor core integrates four execution units—an integer unit (IU), a branch processing unit (BPU),
a load/store unit (LSU), and a system register unit (SRU). The ability to execute four instructions in
parallel and the use of simple instructions with rapid execution times yield high efficiency and throughput.
Most integer instructions execute in one clock cycle.
The processor core supports integer data types of 8, 16, and 32 bits, and floating-point data types of 32 and
64 bits. The 32 architecturally-defined floating point registers (FPRs) can be used to hold 32, 64-bit
operands that can in turn be transferred to and from the 32 general-purpose registers (GPRs), which can
hold 32, 32-bit operands.
The processor core provides separate on-chip, 16-Kbyte, four-way set-associative, physically addressed
caches for instructions and data and on-chip instruction and data memory management units (MMUs). The
MMUs contain 64-entry, two-way set-associative, data and instruction translation lookaside buffers
(DTLB and ITLB) that provide support for demand-paged virtual memory address translation and
variable-sized block translation. The TLBs and caches use a least recently used (LRU) replacement
algorithm. The processor core also supports block address translation through the use of two independent
instruction and data block address translation (IBAT and DBAT) arrays of four entries each. Effective
addresses are compared simultaneously with all four entries in the BAT array during block translation. In
accordance with the PowerPC architecture, if an effective address hits in both the TLB and BAT array, the
BAT translation takes priority.
As an added feature to the MPC603e core, the PowerQUICC II can lock the contents of 1–3 ways in the
instruction and data cache (or an entire cache). For example, this allows embedded applications to lock
interrupt routines or other important (time-sensitive) instruction sequences into the instruction cache. It
allows data to be locked into the data cache, which may be important to code that must have deterministic
execution.
The processor core has a 60x bus that incorporates a 64-bit data bus and a 32-bit address bus. The processor
core supports single-beat and burst data transfers for memory accesses and supports memory-mapped I/O
operations.
2.2
G2 Processor Core Features
This section describes the major features of the processor core:
•
High-performance, superscalar microprocessor
— As many as three instructions issued and retired per clock cycle
— As many as four instructions in execution per clock cycle
— Single-cycle execution for most instructions
Five independent execution units and two register files
— BPU featuring static branch prediction
•
— A 32-bit IU
— Fully IEEE 754-compliant FPU for both single- and double-precision operations
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G2 Core
— LSU for data transfer between data cache and GPRs and FPRs
— SRU that executes condition register (CR), special-purpose register (SPR), and integer
add/compare instructions
— Thirty-two GPRs for integer operands
— Thirty-two FPRs for floating-point operands. They also can be used for general operands using
floating-point load and store operations.
•
High instruction and data throughput
— Zero-cycle branch capability (branch folding)
— Programmable static branch prediction on unresolved conditional branches
— BPU that performs CR lookahead operations
— Instruction fetch unit capable of fetching two instructions per clock from the instruction cache
— A six-entry instruction queue that provides lookahead capability
— Independent pipelines with feed-forwarding that reduces data dependencies in hardware
— 16-Kbyte data cache—four-way set-associative, physically addressed; LRU replacement
algorithm
— 16-Kbyte instruction cache—four-way set-associative, physically addressed; LRU
replacement algorithm
— Cache write-back or write-through operation programmable on a per page or per block basis
— Address translation facilities for 4-Kbyte page size, variable block size, and 256-Mbyte
segment size
— A 64-entry, two-way set-associative ITLB
— A 64-entry, two-way set-associative DTLB
— Four-entry data and instruction BAT arrays providing 128-Kbyte to 256-Mbyte blocks
— Software table search operations and updates supported through fast trap mechanism
— 52-bit virtual address; 32-bit physical address
•
Facilities for enhanced system performance
— A 32- or 64-bit, split-transaction external data bus with burst transfers
— Support for one-level address pipelining and out-of-order bus transactions
— Hardware support for misaligned little-endian accesses
Integrated power management
•
•
— Three power-saving modes: doze, nap, and sleep
— Automatic dynamic power reduction when internal functional units are idle
Deterministic behavior and debug features
— On-chip cache locking options for the instruction and data caches (1–3 ways or the entire cache
contents can be locked)
— In-system testability and debugging features through JTAG and boundary-scan capability
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G2 Core
Figure 2-1 shows how the execution units—IU, BPU, LSU, and SRU—operate independently and in
parallel. Note that this is a conceptual diagram and does not attempt to show how these features are
physically implemented on the chip.
The processor core provides address translation and protection facilities, including an ITLB, DTLB, and
instruction and data BAT arrays. Instruction fetching and issuing is handled in the instruction unit. The
MMUs translate addresses for cache or external memory accesses.
2.2.1
Instruction Unit
As shown in Figure 2-1, the instruction unit, which contains a fetch unit, instruction queue, dispatch unit,
and the BPU, provides centralized control of instruction flow to the execution units. The instruction unit
determines the address of the next instruction to be fetched based on information from the sequential
fetcher and from the BPU.
The instruction unit fetches the instructions from the instruction cache into the instruction queue. The BPU
extracts branch instructions from the fetcher and uses static branch prediction on unresolved conditional
branches to allow the instruction unit to fetch instructions from a predicted target instruction stream while
a conditional branch is evaluated. The BPU folds out branch instructions for unconditional branches or
conditional branches unaffected by instructions in progress in the execution pipeline.
Instructions issued beyond a predicted branch do not complete execution until the branch is resolved,
preserving the programming model of sequential execution. If any of these instructions are to be executed
in the BPU, they are decoded but not issued. Instructions to be executed by the IU, LSU, and SRU are
issued and allowed to complete up to the register write-back stage. Write-back is allowed when a correctly
predicted branch is resolved, and instruction execution continues without interruption on the predicted
path. If branch prediction is incorrect, the instruction unit flushes all predicted path instructions, and
instructions are issued from the correct path.
2.2.2
Instruction Queue and Dispatch Unit
The instruction queue (IQ), shown in Figure 2-1, holds as many as six instructions and loads up to two
instructions from the instruction unit during a single cycle. The instruction fetch unit continuously loads
as many instructions as space in the IQ allows. Instructions are dispatched to their respective execution
units from the dispatch unit at a maximum rate of two instructions per cycle. Reservation stations at the
IU, LSU, and SRU facilitate instruction dispatch to those units. The dispatch unit checks for source and
destination register dependencies, determines dispatch serializations, and inhibits subsequent instruction
dispatching as required. Section 2.7, “Instruction Timing,” describes instruction dispatch in detail.
2.2.3
Branch Processing Unit (BPU)
The BPU receives branch instructions from the fetch unit and performs CR lookahead operations on
conditional branches to resolve them early, achieving the effect of a zero-cycle branch in many cases.
The BPU uses a bit in the instruction encoding to predict the direction of the conditional branch. Therefore,
when an unresolved conditional branch instruction is encountered, instructions are fetched from the
predicted target stream until the conditional branch is resolved.
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G2 Core
The BPU contains an adder to compute branch target addresses and three user-control registers—the link
register (LR), the count register (CTR), and the CR. The BPU calculates the return pointer for subroutine
calls and saves it into the LR for certain types of branch instructions. The LR also contains the branch
target address for the Branch Conditional to Link Register (bclrx) instruction. The CTR contains the
branch target address for the Branch Conditional to Count Register (bcctrx) instruction. The contents of
the LR and CTR can be copied to or from any GPR. Because the BPU uses dedicated registers rather than
GPRs or FPRs, execution of branch instructions is largely independent from execution of other
instructions.
2.2.4
Independent Execution Units
The PowerPC architecture’s support for independent execution units allows implementation of processors
with out-of-order instruction execution. For example, because branch instructions do not depend on GPRs
or FPRs, branches can often be resolved early, eliminating stalls caused by taken branches.
In addition to the BPU, the processor core provides three other execution units and a completion unit,
which are described in the following sections.
2.2.4.1
Integer Unit (IU)
The IU executes all integer instructions. The IU executes one integer instruction at a time, performing
computations with its arithmetic logic unit (ALU), multiplier, divider, and XER register. Most integer
instructions are single-cycle instructions. Thirty-two general-purpose registers are provided to support
integer operations. Stalls due to contention for GPRs are minimized by the automatic allocation of rename
registers. The processor core writes the contents of the rename registers to the appropriate GPR when
integer instructions are retired by the completion unit.
2.2.4.2
Floating-Point Unit (FPU)
The FPU contains a single-precision multiply-add array and the floating-point status and control register
(FPSCR). The multiply-add array allows the processor core to efficiently implement multiply and
multiply-add operations. The FPU is pipelined so that single-precision instructions and double-precision
instructions can be issued back-to-back. Thirty-two floating-point registers are provided to support
floating-point operations. Stalls due to contention for FPRs are minimized by the automatic allocation of
rename registers. The core writes the contents of the rename registers to the appropriate FPR when
floating-point instructions are retired by the completion unit.
The processor core supports all IEEE 754 floating-point data types (normalized, denormalized, NaN, zero,
and infinity) in hardware, eliminating the latency incurred by software exception routines.
2.2.4.3
Load/Store Unit (LSU)
The LSU executes all load and store instructions and provides the data transfer interface between the
GPRs, FPRs, and the cache/memory subsystem. The LSU calculates effective addresses, performs data
alignment, and provides sequencing for load/store string and multiple instructions.
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G2 Core
Load and store instructions are issued and translated in program order; however, the actual memory
accesses can occur out of order. Synchronizing instructions are provided to enforce strict ordering where
needed.
Cacheable loads, when free of data dependencies, execute in an out-of-order manner with a maximum
throughput of one per cycle and a two-cycle total latency. Data returned from the cache is held in a rename
register until the completion logic commits the value to a GPR or FPR. Store operations do not occur until
a predicted branch is resolved. They remain in the store queue until the completion logic signals that the
store operation is definitely to be completed to memory.
The processor core executes store instructions with a maximum throughput of one per cycle and a
three-cycle total latency. The time required to perform the actual load or store operation varies depending
on whether the operation involves the cache, system memory, or an I/O device.
2.2.4.4
System Register Unit (SRU)
The SRU executes various system-level instructions, including condition register logical operations and
move to/from special-purpose register instructions, and also executes integer add/compare instructions.
Because SRU instructions affect modes of processor operation, most SRU instructions are
completion-serialized. That is, the instruction is held for execution in the SRU until all prior instructions
issued have completed. Results from completion-serialized instructions executed by the SRU are not
available or forwarded for subsequent instructions until the instruction completes.
2.2.5
Completion Unit
The completion unit tracks instructions from dispatch through execution, and then retires, or completes
them in program order. Completing an instruction commits the processor core to any architectural register
changes caused by that instruction. In-order completion ensures the correct architectural state when the
processor core must recover from a mispredicted branch or any exception.
Instruction state and other information required for completion is kept in a first-in-first-out (FIFO) queue
of five completion buffers. A single completion buffer is allocated for each instruction once it enters the
dispatch unit. An available completion buffer is a required resource for instruction dispatch; if no
completion buffers are available, instruction dispatch stalls. A maximum of two instructions per cycle are
completed in order from the queue.
2.2.6
Memory Subsystem Support
The processor core supports cache and memory management through separate instruction and data MMUs
(IMMU and DMMU). The processor core also provides dual 16-Kbyte instruction and data caches, and an
efficient processor bus interface to facilitate access to main memory and other bus subsystems. The
memory subsystem support functions are described in the following subsections.
2.2.6.1
Memory Management Units (MMUs)
The processor core’s MMUs support up to 4 Petabytes (252) of virtual memory and 4 Gbytes (232) of
physical memory (referred to as real memory in the PowerPC architecture specification) for instructions
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G2 Core
and data. The MMUs also control access privileges for these spaces on block and page granularities.
Referenced and changed status is maintained by the processor for each page to assist implementation of a
demand-paged virtual memory system. A key bit is implemented to provide information about memory
protection violations prior to page table search operations.
The LSU calculates effective addresses for data loads and stores, performs data alignment to and from
cache memory, and provides the sequencing for load and store string and multiple word instructions. The
instruction unit calculates the effective addresses for instruction fetching.
The MMUs translate effective addresses and enforce the protection hierarchy programmed by the
operating system in relation to the supervisor/user privilege level of the access and in relation to whether
the access is a load or store.
2.2.6.2
Cache Units
The processor core provides independent 16-Kbyte, four-way set-associative instruction and data caches.
The cache block size is 32 bytes. The caches are designed to adhere to a write-back policy, but the
processor core allows control of cacheability, write policy, and memory coherency at the page and block
levels. The caches use a least recently used (LRU) replacement algorithm.
The load/store and instruction fetch units provide the caches with the address of the data or instruction to
be fetched. In the case of a cache hit, the cache returns two words to the requesting unit.
2.3
Programming Model
The following subsections describe the PowerPC instruction set and addressing modes.
2.3.1
Register Set
This section describes the register organization in the processor core as defined by the three programming
environments of the PowerPC architecture—the user instruction set architecture (UISA), the virtual
environment architecture (VEA), and the operating environment architecture (OEA), as well as the G2
core implementation-specific registers. Full descriptions of the basic register set defined by the PowerPC
architecture are provided in Chapter 2 in The Programming Environments Manual.
The PowerPC architecture defines register-to-register operations for all arithmetic instructions. Source
data for these instructions is accessed from the on-chip registers or is provided as an immediate value
embedded in the opcode. The three-register instruction format allows specification of a target register
distinct from the two source registers, thus preserving the original data for use by other instructions and
reducing the number of instructions required for certain operations. Data is transferred between memory
and registers with explicit load and store instructions only.
Figure 2-2 shows the complete PowerQUICC II register set and the programming environment to which
each register belongs. This figure includes both the PowerPC register set and the PowerQUICC II-specific
registers.
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G2 Core
Note that there may be registers common to other processors that implement the PowerPC architecture that
are not implemented in the PowerQUICC II’s processor core. Unsupported SPR values are treated as
follows:
•
•
Any mtspr with an invalid SPR executes as a no-op.
Any mfspr with an invalid SPR cause boundedly undefined results in the target register.
Conversely, some SPRs in the processor core may not be implemented or may not be implemented in the
same way as in other processors that implement the PowerPC architecture.
2.3.1.1
PowerPC Register Set
The PowerPC UISA registers, shown in Figure 2-2, can be accessed by either user- or supervisor-level
instructions. The general-purpose registers (GPRs) and floating-point registers (FPRs) are accessed
through instruction operands. Access to registers can be explicit (that is, through the use of specific
instructions for that purpose such as the mtspr and mfspr instructions) or implicit as part of the execution
(or side effect) of an instruction. Some registers are accessed both explicitly and implicitly.
The number to the right of the register name indicates the number that is used in the syntax of the
instruction operands to access the register (for example, the number used to access the XER is one). For
more information on the PowerPC register set, refer to Chapter 2 in The Programming Environments
Manual.
Note that the reset value of the MSR exception prefix bit (MSR[IP]), described in the G2 Core Reference
Manual, is determined by the CIP bit in the hard reset configuration word in the PowerQUICC II. This is
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SUPERVISOR MODEL—OEA
Configuration Registers
Hardware
Implementation
Registers
Processor Version
Register
Machine State
Register
1
USER MODEL
UISA
General-Purpose
Registers
HID0
HID1
HID2
SPR
SPR
SPR
MSR
PVR
SPR 287
GPR0
GPR1
Memory Management Registers
Instruction BAT
Registers
Software Table
Search Registers
1
Data BAT Registers
GPR31
IBAT0U SPR 528
IBAT0L SPR 529
IBAT1U SPR 530
IBAT1L SPR 531
IBAT2U SPR 532
IBAT2L SPR 533
IBAT3U SPR 534
DBAT0U SPR 536
DBAT0L SPR 537
DBAT1U SPR 538
DBAT1L SPR 539
DBAT2U SPR 540
DBAT2L SPR 541
DBAT3U SPR 542
DBAT3L SPR 543
DMISS
DCMP
HASH1
HASH2
IMISS
ICMP
SPR 976
SPR 977
SPR 978
SPR 979
SPR 980
SPR 981
SPR 982
Floating-Point
Registers
FPR0
FPR1
RPA
IBAT3L
SPR 535
Segment Registers
SDR1
FPR31
SR0
SR1
SDR1
SPR 25
Condition Register
CR
SR15
Exception Handling Registers
Data Address Register
XER
XER
R 1
DSISR
DSISR
Save and Restore Registers
DAR
SPR 18
SPR 19
Link Register
LR
SPRGs
R 8
SPRG0 SPR 272
SPRG1 SPR 273
SPRG2 SPR 274
SPRG3 SPR 275
SRR0
SRR1
SPR 26
SPR 27
Count Register
CTR
R 9
USER MODEL
VEA
Miscellaneous Registers
Time Base Facility
(For Writing)
Time Base Facility
(For Reading)
Decrementer
TBL
TBU
SPR 284
SPR 285
DEC
SPR 22
TBL
TBU
TBR 268
TBR 269
Instruction Address
Breakpoint Register
External Address
Register (Optional)
1
EAR
SPR 282
IABR
SPR
1
.
These implementation–specific registers may not be supported by other processors or processor cores.
Figure 2-2. PowerQUICC II Programming Model—Registers
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2.3.1.2
PowerQUICC II-Specific Registers
The set of registers specific to the MPC603e are also shown in Figure 2-2. Most of these are described in
the G2 Core Reference Manual and are implemented in the PowerQUICC II as follows:
•
MMU software table search registers: DMISS, DCMP, HASH1, HASH2, IMISS, ICMP, and RPA.
These registers facilitate the software required to search the page tables in memory.
•
IABR. This register facilitates the setting of instruction breakpoints.
The hardware implementation-dependent registers (HIDx) are implemented differently in the
PowerQUICC II, and they are described in the following subsections.
2.3.1.2.1
Hardware Implementation-Dependent Register 0 (HID0)
Figure 2-3 shows the PowerQUICC II implementation of HID0.
0
1
2
3
4
6
7
8
9
10
11
12
14
30
15
EMCP
–
EBA
EBD
–
PAR DOZE
–
SLEEP DPM
–
NHR
16
17
18
19
20
21
22
23
24
25
26
27
28
29
31
ICE DCE ILOCK DLOCK ICFI DCFI
–
IFEM
–
FBIOB ABE
–
NOOPTI
Figure 2-3. Hardware Implementation Register 0 (HID0)
Table 2-1 shows the bit definitions for HID0.
Table 2-1. HID0 Field Descriptions
Description
Bits
Name
0
EMCP
Enable machine check input pin
0 The assertion of the MCP does not cause a machine check exception.
1 Enables the entry into a machine check exception based on assertion of the MCP input,
detection of a Cache Parity Error, detection of an address parity error, or detection of a data
parity error.
Note that the machine check exception is further affected by MSR[ME], which specifies whether
the processor checkstops or continues processing.
1
2
—
Reserved
EBA
Enable/disable 60x bus address parity checking
0 Prevents address parity checking.
1 Allows a address parity error to cause a checkstop if MSR[ME] = 0 or a machine check
exception if MSR[ME] = 1.
EBA and EBD let the processor operate with memory subsystems that do not generate parity.
3
EBD
—
Enable 60x bus data parity checking
0 Parity checking is disabled.
1 Allows a data parity error to cause a checkstop if MSR[ME] = 0 or a machine check exception
if MSR[ME] = 1.
EBA and EBD let the processor operate with memory subsystems that do not generate parity.
4–6
Reserved
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Table 2-1. HID0 Field Descriptions (continued)
Description
Bits
Name
7
PAR
Disable precharge of ARTRY.
0 Precharge of ARTRY enabled
1 Alters bus protocol slightly by preventing the processor from driving ARTRY to high (negated)
state, allowing multiple ARTRY signals to be tied together. If this is done, the system must
restore the signals to the high state.
1
8
DOZE
—
Doze mode enable. Operates in conjunction with MSR[POW].
0 Doze mode disabled.
1 Doze mode enabled. Doze mode is invoked by setting MSR[POW] after this bit is set. In doze
mode, the PLL, time base, and snooping remain active.
9
Reserved, should be cleared.
1
10
SLEEP Sleep mode enable. Operates in conjunction with MSR[POW].
0 Sleep mode disabled.
1 Sleep mode enabled. Sleep mode is invoked by setting MSR[POW] while this bit is set. When
this occurs, the processor asserts QREQ to indicate that it is ready to enter Sleep mode. The
main PowerQUICC II’s PLL remains active and all the internal clocks—including the core’s
1
11
DPM
Dynamic power management enable.
0 Dynamic power management is disabled.
1 Functional units enter a low-power mode automatically if the unit is idle. This does not affect
operational performance and is transparent to software or any external hardware.
12–14
15
—
Reserved
NHR
Not hard reset (software-use only)—Helps software distinguish a hard reset from a soft reset.
0 A hard reset occurred if software had previously set this bit.
1 A hard reset has not occurred. If software sets this bit after a hard reset, when a reset occurs
and this bit remains set, software can tell it was a soft reset.
2
16
ICE
Instruction cache enable
0 The instruction cache is neither accessed nor updated. All pages are accessed as if they were
marked cache-inhibited (WIM = X1X). Potential cache accesses from the bus (snoop and
cache operations) are ignored. In the disabled state for the L1 caches, the cache tag state bits
are ignored and all accesses are propagated to the bus as single-beat transactions. For those
transactions, however, CI reflects the original state determined by address translation
regardless of cache disabled status. ICE is zero at power-up.
1 The instruction cache is enabled
2
17
DCE
Data cache enable
0 The data cache is neither accessed nor updated. All pages are accessed as if they were
marked cache-inhibited (WIM = X1X). Potential cache accesses from the bus (snoop and
cache operations) are ignored. In the disabled state for the L1 caches, the cache tag state bits
are ignored and all accesses are propagated to the bus as single-beat transactions. For those
transactions, however, CI reflects the original state determined by address translation
regardless of cache disabled status. DCE is zero at power-up.
1 The data cache is enabled.
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Table 2-1. HID0 Field Descriptions (continued)
Description
Bits
Name
18
ILOCK
Instruction cache lock
0 Normal operation
1 Instruction cache is locked. A locked cache supplies data normally on a hit, but an access is
treated as a cache-inhibited transaction on a miss. On a miss, the transaction to the bus is
single-beat, however, CI still reflects the original state as determined by address translation
independent of cache locked or disabled status.
To prevent locking during a cache access, an isync must precede the setting of ILOCK.
19
DLOCK Data cache lock
0 Normal operation
1 Data cache is locked. A locked cache supplies data normally on a hit but an access is treated
as a cache-inhibited transaction on a miss. On a miss, the transaction to the bus is single-beat,
however, CI still reflects the original state as determined by address translation independent
of cache locked or disabled status. A snoop hit to a locked L1 data cache performs as if the
cache were not locked. A cache block invalidated by a snoop remains invalid until the cache is
unlocked.
To prevent locking during a cache access, a sync must precede the setting of DLOCK.
2
20
ICFI
Instruction cache flash invalidate
0 The instruction cache is not invalidated. The bit is cleared when the invalidation operation
begins (usually the next cycle after the write operation to the register). The instruction cache
must be enabled for the invalidation to occur.
1 An invalidate operation is issued that marks the state of each instruction cache block as invalid
without writing back modified cache blocks to memory. Cache access is blocked during this
time. Bus accesses to the cache are signaled as a miss during invalidate-all operations. Setting
ICFI clears all the valid bits of the blocks and the PLRU bits to point to way L0 of each set. Once
the L1 flash invalidate bits are set through an mtspr instruction, hardware automatically resets
these bits in the next cycle (provided that the corresponding cache enable bits are set in HID0).
2
21
DCFI
Data cache flash invalidate
0 The data cache is not invalidated. The bit is cleared when the invalidation operation begins
(usually the next cycle after the write operation to the register). The data cache must be
enabled for the invalidation to occur.
1 An invalidate operation is issued that marks the state of each data cache block as invalid
without writing back modified cache blocks to memory. Cache access is blocked during this
time. Bus accesses to the cache are signaled as a miss during invalidate-all operations. Setting
DCFI clears all the valid bits of the blocks and the PLRU bits to point to way L0 of each set.
Once the L1 flash invalidate bits are set through an mtspr instruction, hardware automatically
resets these bits in the next cycle (provided that the corresponding cache enable bits are set
in HID0).
22–23
24
—
Reserved
IFEM
Enable M bit on 60x bus for instruction fetches
0 M bit not reflected on 60x bus. Instruction fetches are treated as nonglobal on the bus.
1 Instruction fetches reflect the M bit from the WIM settings on the 60x bus.
25–26
27
—
Reserved
FBIOB
• Force branch indirect on bus.
• 0Register indirect branch targets are fetched normally
• 1Forces register indirect branch targets to be fetched externally.
28
ABE
Address broadcast enable
0
1
dcbf, dcbi, and dcbst instructions are not broadcast on the 60x bus.
dcbf, dcbi, and dcbst generate address-only broadcast operations on the 60x bus.
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Table 2-1. HID0 Field Descriptions (continued)
Description
Bits
Name
29–30
31
—
Reserved
NOOPTI No-op the data cache touch instructions.
0 The dcbt and dcbtst instructions are enabled.
1 The dcbt and dcbtst instructions are no-oped globally.
1
2
See Chapter 10, “Power Management,” of the G2 Core Reference Manual for more information.
See Chapter 4, “Instruction and Data Cache Operation,” of the G2 Core Reference Manual for more information.
2.3.1.2.2
Hardware Implementation-Dependent Register 1 (HID1)
0
4
5
31
PLLCFG
—
Figure 2-4. Hardware Implementation-Dependent Register 1 (HID1)
Table 2-2 shows the bit definitions for HID1.
Table 2-2. HID1 Field Descriptions
Function
0–4 PLLCFG PLL configuration setting. These bits reflect the state of the PLL_CFG[0:4] signals.
Bits
Name
5–31
—
Reserved
2.3.1.2.3
Hardware Implementation-Dependent Register 2 (HID2)
The processor core implements an additional hardware implementation-dependent register, shown in
0
14
15
16
18 19
23 24
26 27
31
—
SFP
IWLCK
—
DWLCK
—
Figure 2-5. Hardware Implementation-Dependent Register 2 (HID2)
Table 2-3 describes the HID2 fields.
Table 2-3. HID2 Field Descriptions
Bits
Name
Function
0–14
15
—
Reserved
SFP
Speed for low power. Setting SFP reduces power consumption at the cost of reducing the maximum
frequency, which benefits power-sensitive applications that are not frequency-critical.
16–18 IWLCK Instruction cache way lock. Useful for locking blocks of instructions into the instruction cache for
time-critical applications that require deterministic behavior. See Section 2.4.2.3, “Cache Locking.”
19–23
—
Reserved
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Table 2-3. HID2 Field Descriptions (continued)
Function
Bits
Name
24–26 DWLCK Data cache way lock. Useful for locking blocks of data into the data cache for time-critical
27–31
—
Reserved
2.3.1.2.4
Processor Version Register (PVR)
Software can identify the PowerQUICC II’s processor core by reading the processor version register
(PVR). The processor version number for .29µm (HiP3) devices is 0x00810101 and 0x80811014 for
.25µm (HiP4) devices.
2.3.2
PowerPC Instruction Set and Addressing Modes
All PowerPC instructions are encoded as single-word (32-bit) opcodes. Instruction formats are consistent
among all instruction types, permitting efficient decoding to occur in parallel with operand accesses. This
fixed instruction length and consistent format greatly simplifies instruction pipelining.
2.3.2.1
Calculating Effective Addresses
The effective address (EA) is the 32-bit address computed by the processor when executing a memory
access or branch instruction or when fetching the next sequential instruction.
The PowerPC architecture supports two simple memory addressing modes:
•
•
EA = (rA|0) + offset (including offset = 0) (register indirect with immediate index)
EA = (rA|0) + rB (register indirect with index)
These simple addressing modes allow efficient address generation for memory accesses. Calculation of the
effective address for aligned transfers occurs in a single clock cycle.
For a memory access instruction, if the sum of the effective address and the operand length exceeds the
maximum effective address, the memory operand is considered to wrap around from the maximum
effective address to effective address 0.
Effective address computations for both data and instruction accesses use 32-bit unsigned binary
arithmetic. A carry from bit 0 is ignored in 32-bit implementations.
In addition to the functionality of the MPC603e, the PowerQUICC II has additional hardware support for
misaligned little-endian accesses. Except for string/multiple load and store instructions, little-endian
load/store accesses not on a word boundary generate exceptions under the same circumstances as
big-endian requests.
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2.3.2.2
PowerPC Instruction Set
The PowerPC instructions are divided into the following categories:
•
Integer instructions—These include arithmetic and logical instructions.
— Integer arithmetic
— Integer compare
— Integer logical
— Integer rotate and shift
•
Floating-point instructions—These include floating-point computational instructions, as well as
instructions that affect the FPSCR.
— Floating-point arithmetic
— Floating-point multiply/add
— Floating-point rounding and conversion
— Floating-point compare
— Floating-point status and control
•
•
Load/store instructions—These include integer and floating-point load and store instructions.
— Integer load and store
— Integer load and store with byte reverse
— Integer load and store string/multiple
— Floating-point load and store
Flow control instructions—These include branching instructions, condition register logical
instructions, trap instructions, and other synchronizing instructions that affect the instruction flow.
— Branch and trap
— Condition register logical
— Primitives used to construct atomic memory operations (lwarx and stwcx.)
— Synchronize
•
•
Processor control instructions—These instructions are used for synchronizing memory accesses
and management of caches, TLBs, and the segment registers.
— Move to/from SPR
— Move to/from MSR
— Instruction synchronize
Memory control instructions—These provide control of caches, TLBs, and segment registers.
— Supervisor-level cache management
— User-level cache management
— Segment register manipulation
— TLB management
Note that this grouping of the instructions does not indicate which execution unit executes a particular
instruction or group of instructions.
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Integer instructions operate on byte, half-word, and word operands. The PowerPC architecture uses
instructions that are four bytes long and word-aligned. It provides for byte, half-word, and word operand
loads and stores between memory and a set of 32 GPRs. Floating-point instructions operate on
single-precision (one word) and double-precision (one double word) floating-point operands. It also
provides for word and double-word operand loads and stores between memory and a set of 32
floating-point registers (FPRs).
Computational instructions do not modify memory. To use a memory operand in a computation and then
modify the same or another memory location, the memory contents must be loaded into a register,
modified, and then written back to the target location with separate instructions. Decoupling arithmetic
instructions from memory accesses increases throughput by facilitating pipelining.
Processors that implement the PowerPC architecture follow the program flow when they are in the normal
execution state. However, the flow of instructions can be interrupted directly by the execution of an
instruction or by an asynchronous event. Either kind of exception may cause one of several components
of the system software to be invoked.
2.3.2.3
PowerQUICC II Implementation-Specific Instruction Set
The PowerQUICC II processor core instruction set is defined as follows:
•
•
The processor core provides hardware support for all 32-bit PowerPC instructions.
The processor core provides two implementation-specific instructions used for software table
search operations following TLB misses:
— Load Data TLB Entry (tlbld)
— Load Instruction TLB Entry (tlbli)
•
The processor core implements the following instructions defined as optional by the PowerPC
architecture:
— Floating Select (fsel)
— Floating Reciprocal Estimate Single-Precision (fres)
— Floating Reciprocal Square Root Estimate (frsqrte)
— Store Floating-Point as Integer Word Indexed (stfiwx)
— External Control In Word Indexed (eciwx)
— External Control Out Word Indexed (ecowx)
The PowerQUICC II does not provide the hardware support for misaligned eciwx and ecowx
instructions provided by the MPC603e processor. An alignment exception is taken if these
instructions are not word-aligned.
2.4
Cache Implementation
The PowerQUICC II processor core has separate data and instruction caches. The cache implementation
is described in the following sections.
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2.4.1
PowerPC Cache Model
The PowerPC architecture does not define hardware aspects of cache implementations. For example, some
processors, including the PowerQUICC II’s processor core, have separate instruction and data caches
(Harvard architecture), while others implement a unified cache.
Microprocessors that implement the PowerPC architecture control the following memory access modes on
a page or block basis:
•
•
•
Write-back/write-through mode
Caching-inhibited mode
Memory coherency
The PowerPC cache management instructions provide a means by which the application programmer can
affect the cache contents.
2.4.2
PowerQUICC II Implementation-Specific Cache Implementation
As shown in Figure 2-1, the caches provide a 64-bit interface to the instruction fetch unit and load/store
unit. The surrounding logic selects, organizes, and forwards the requested information to the requesting
unit. Write operations to the cache can be performed on a byte basis, and a complete read-modify-write
operation to the cache can occur in each cycle.
Each cache block contains eight contiguous words from memory that are loaded from an 8-word boundary
(that is, bits A27–A31 of the effective addresses are zero); thus, a cache block never crosses a page
boundary. Misaligned accesses across a page boundary can incur a performance penalty.
The cache blocks are loaded in to the processor core in four beats of 64 bits each. The burst load is
performed as critical double word first.
To ensure coherency among caches in a multiprocessor (or multiple caching-device) implementation, the
processor core implements the MEI protocol. These three states, modified, exclusive, and invalid, indicate
the state of the cache block as follows:
•
•
•
Modified—The cache block is modified with respect to system memory; that is, data for this
address is valid only in the cache and not in system memory.
Exclusive—This cache block holds valid data that is identical to the data at this address in system
memory. No other cache has this data.
Invalid—This cache block does not hold valid data.
2.4.2.1
Data Cache
As shown in Figure 2-6, the data cache is configured as 128 sets of four blocks each. Each block consists
of 32 bytes, two state bits, and an address tag. The two state bits implement the three-state MEI
(modified/exclusive/invalid) protocol. Each block contains eight 32-bit words. Note that the PowerPC
architecture defines the term ‘block’ as the cacheable unit. For the PowerQUICC II’s processor core, the
block size is equivalent to a cache line.
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128 Sets
Address Tag 0
Address Tag 1
Address Tag 2
Address Tag 3
State
State
State
State
Words 0–7
Words 0–7
Block 0
Block 1
Block 2
Block 3
Words 0–7
Words 0–7
8 Words/Block
Figure 2-6. Data Cache Organization
Because the processor core data cache tags are single-ported, simultaneous load or store and snoop
accesses cause resource contention. Snoop accesses have the highest priority and are given first access to
the tags, unless the snoop access coincides with a tag write, in which case the snoop is retried and must
rearbitrate for access to the cache. Loads or stores that are deferred due to snoop accesses are executed on
the clock cycle following the snoop.
Because the caches on the processor core are write-back caches, the predominant type of transaction for
most applications is burst-read memory operations, followed by burst-write memory operations, and
single-beat (noncacheable or write-through) memory read and write operations. When a cache block is
filled with a burst read, the critical double word is simultaneously written to the cache and forwarded to
the requesting unit, thus minimizing stalls due to load delays.
Additionally, there can be address-only operations, variants of the burst and single-beat operations, (for
example, global memory operations that are snooped and atomic memory operations), and address retry
activity (for example, when a snooped read access hits a modified line in the cache).
Setting HID0[ABE] causes execution of the dcbf, dcbi, and dcbst instructions to be broadcast onto the
60x bus. The value of ABE does not affect dcbz instructions, which are always broadcast and snooped.
The cache operations are intended primarily for managing on-chip caches. However, the optional
broadcast feature is necessary to allow proper management of a system using an external copyback L2
cache.
The address and data buses operate independently to support pipelining and split transactions during
memory accesses. The processor core pipelines its own transactions to a depth of one level.
Typically, memory accesses are weakly ordered—sequences of operations, including load/store string and
multiple instructions, do not necessarily complete in the order they begin—maximizing the efficiency of
the internal bus without sacrificing coherency of the data. The processor core allows pending read
operations to precede previous store operations (except when a dependency exists, or in cases where a
non-cacheable access is performed), and provides support for a write operation to proceed a previously
queued read data tenure (for example, allowing a snoop push to be enveloped by the address and data
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tenures of a read operation). Because the processor can dynamically optimize run-time ordering of
load/store traffic, overall performance is improved.
2.4.2.2
Instruction Cache
The instruction cache also consists of 128 sets of four blocks, and each block consists of 32 bytes, an
address tag, and a valid bit. The instruction cache may not be written to except through a block fill
operation caused by a cache miss. In the processor core, internal access to the instruction cache is blocked
only until the critical load completes.
The processor core supports instruction fetching from other instruction cache lines following the
forwarding of the critical first double word of a cache line load operation. The processor core’s instruction
cache is blocked only until the critical load completes (hits under reloads allowed). Successive instruction
fetches from the cache line being loaded are forwarded, and accesses to other instruction cache lines can
proceed during the cache line load operation.
The instruction cache is not snooped, and cache coherency must be maintained by software. A fast
hardware invalidation capability is provided to support cache maintenance. The organization of the
2.4.2.3
Cache Locking
The processor core supports cache locking, which is the ability to prevent some or all of a microprocessor’s
instruction or data cache from being overwritten. Cache entries can be locked for either an entire cache or
for individual ways within the cache. Entire data cache locking is enabled by setting HID0[DLOCK], and
entire instruction cache locking is enabled by setting HID0[ILOCK]. For more information, refer to Cache
Locking on the G2 Core application note (order number: AN1767/D). Cache way locking is controlled by
the IWLCK and DWLCK bits of HID2.
2.4.2.3.1
Entire Cache Locking
When an entire cache is locked, hits within the cache are supplied in the same manner as hits to an
unlocked cache. Any access that misses in the cache is treated as a cache-inhibited access. Cache entries
that are invalid at the time of locking will remain invalid and inaccessible until the cache is unlocked. Once
the cache has been unlocked, all entries (including invalid entries) are available. Entire cache locking is
inefficient if the number of instructions or the size of data to be locked is small compared to the cache size.
2.4.2.3.2
Way Locking
Locking only a portion of the cache is accomplished by locking ways within the cache. Locking always
begins with the first way (way0) and is sequential. That is, it is valid to lock ways 0, 1, and 2 but it is not
possible to lock just way0 and way2). When using way locking at least one way must be left unlocked. The
maximum number of lockable ways is three.
Unlike entire cache locking, invalid entries in a locked way are accessible and available for data
placement. As hits to the cache fill invalid entries within a locked way, the entries become valid and
locked. This behavior differs from entire cache locking where nothing is placed in the cache, even if
invalid entries exist in the cache. Unlocked ways of the cache behave normally.
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2.5
Exception Model
This section describes the PowerPC exception model and implementation-specific details of the
PowerQUICC II core.
2.5.1
PowerPC Exception Model
The PowerPC exception mechanism allows the processor to change to supervisor state as a result of
external signals, errors, or unusual conditions arising in the execution of instructions. When exceptions
occur, information about the state of the processor is saved to certain registers and the processor begins
execution at an address (exception vector) predetermined for each exception. Processing of exceptions
occurs in supervisor mode.
Although multiple exception conditions can map to a single exception vector, a more specific condition
may be determined by examining a register associated with the exception—for example, the DSISR
identifies instructions that cause a DSI exception. Additionally, some exception conditions can be
explicitly enabled or disabled by software.
The PowerPC architecture requires that exceptions be handled in program order; therefore, although a
particular implementation may recognize exception conditions out of order, exceptions are taken in strict
order. When an instruction-caused exception is recognized, any unexecuted instructions that appear earlier
in the instruction stream, including any that have not yet entered the execute stage, are required to complete
before the exception is taken. Any exceptions caused by those instructions are handled first. Likewise,
exceptions that are asynchronous and precise are recognized when they occur, but are not handled until the
instruction currently in the completion stage successfully completes execution or generates an exception,
and the completed store queue is emptied.
Unless a catastrophic condition causes a system reset or machine check exception, only one exception is
handled at a time. If, for example, a single instruction encounters multiple exception conditions, those
conditions are handled sequentially. After the exception handler handles an exception, the instruction
execution continues until the next exception condition is encountered. However, in many cases there is no
attempt to re-execute the instruction. This method of recognizing and handling exception conditions
sequentially guarantees that exceptions are recoverable.
Exception handlers should save the information stored in SRR0 and SRR1 early to prevent the program
state from being lost due to a system reset or machine check exception or to an instruction-caused
exception in the exception handler. SRR0 and SRR1 should also be saved before enabling external
interrupts.
The PowerPC architecture supports four types of exceptions:
•
Synchronous, precise—These are caused by instructions. All instruction-caused exceptions are
handled precisely; that is, the machine state at the time the exception occurs is known and can be
completely restored. This means that (excluding the trap and system call exceptions) the address
of the faulting instruction is provided to the exception handler and that neither the faulting
instruction nor subsequent instructions in the code stream will complete execution before the
exception is taken. Once the exception is processed, execution resumes at the address of the
faulting instruction (or at an alternate address provided by the exception handler). When an
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G2 Core
exception is taken due to a trap or system call instruction, execution resumes at an address provided
by the handler.
•
•
Synchronous, imprecise—The PowerPC architecture defines two imprecise floating-point
exception modes, recoverable and nonrecoverable. These are not implemented on the
PowerQUICC II.
Asynchronous, maskable—The external, system management interrupt (SMI), and decrementer
interrupts are maskable asynchronous exceptions. When these exceptions occur, their handling is
postponed until the next instruction and any exceptions associated with that instruction complete
execution. If no instructions are in the execution units, the exception is taken immediately upon
determination of the correct restart address (for loading SRR0).
•
Asynchronous, nonmaskable—There are two nonmaskable asynchronous exceptions: system reset
and the machine check exception. These exceptions may not be recoverable, or may provide a
limited degree of recoverability. All exceptions report recoverability through MSR[RI].
2.5.2
PowerQUICC II Implementation-Specific Exception Model
As specified by the PowerPC architecture, all processor core exceptions can be described as either precise
or imprecise and either synchronous or asynchronous. Asynchronous exceptions (some of which are
maskable) are caused by events external to the processor’s execution. Synchronous exceptions, which are
all handled precisely by the processor core, are caused by instructions. The processor core exception
Table 2-4. Exception Classifications for the Processor Core
Synchronous/Asynchronous
Precise/Imprecise
Imprecise
Exception Type
Asynchronous, nonmaskable
Machine check
System reset
Asynchronous, maskable
Precise
External interrupt
Decrementer
System management interrupt
Synchronous
Precise
Instruction-caused exceptions
Although exceptions have other characteristics as well, such as whether they are maskable or
nonmaskable, the distinctions shown in Table 2-4 define categories of exceptions that the processor core
Table 2-5. Exceptions and Conditions
Exception
Type
Vector Offset
(hex)
Causing Conditions
Reserved
00000
00100
—
System reset
A system reset is caused by the assertion of either SRESET or HRESET. Note that
the reset value of the MSR exception prefix bit (MSR[IP]), described in the G2 Core
Reference Manual, is determined by the CIP bit in the hard reset configuration word.
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Table 2-5. Exceptions and Conditions (continued)
Exception
Type
Vector Offset
(hex)
Causing Conditions
Machine check 00200
A machine check is caused by the assertion of the TEA signal during a data bus
transaction, assertion of MCP, or an address or data parity error.
DSI
00300
The cause of a DSI exception can be determined by the bit settings in the DSISR,
listed as follows:
• 1 Set if the translation of an attempted access is not found in the primary hash
table entry group (HTEG), or in the rehashed secondary HTEG, or in the range of
a DBAT register; otherwise cleared.
• 4Set if a memory access is not permitted by the page or DBAT protection
mechanism; otherwise cleared.
• 5Set by an eciwx or ecowx instruction if the access is to an address that is
marked as write-through, or execution of a load/store instruction that accesses a
direct-store segment.
• 6Set for a store operation and cleared for a load operation.
• 11Set if eciwx or ecowx is used and EAR[E] is cleared.
ISI
00400
An ISI exception is caused when an instruction fetch cannot be performed for any of
the following reasons:
• The effective (logical) address cannot be translated. That is, there is a page fault
for this portion of the translation, so an ISI exception must be taken to load the
PTE (and possibly the page) into memory.
• The fetch access is to a direct-store segment (indicated by SRR1[3] set).
• The fetch access violates memory protection (indicated by SRR1[4] set). If the key
bits (Ks and Kp) in the segment register and the PP bits in the PTE are set to
prohibit read access, instructions cannot be fetched from this location.
External
interrupt
00500
00600
An external interrupt is caused when MSR[EE] = 1 and the INT signal is asserted.
Alignment
An alignment exception is caused when the processor core cannot perform a
memory access for any of the reasons described below:
• The operand of a floating-point load or store is to a direct-store segment.
• The operand of a floating-point load or store is not word-aligned.
• The operand of a lmw, stmw, lwarx, or stwcx. is not word-aligned.
• The operand of an elementary, multiple or string load or store crosses a segment
boundary with a change to the direct store T bit.
• The operand of dcbz instruction is in memory that is write-through required or
caching inhibited, or dcbz is executed in an implementation that has either no
data cache or a write-through data cache.
• A misaligned eciwx or ecowx instruction
• A multiple or string access with MSR[LE] set
The processor core differs from MPC603e User’s Manual in that it initiates an
alignment exception when it detects a misaligned eciwx or ecowx instruction and
does not initiate an alignment exception when a little-endian access is misaligned.
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Table 2-5. Exceptions and Conditions (continued)
Exception
Type
Vector Offset
(hex)
Causing Conditions
Program
00700
A program exception is caused by one of the following exception conditions, which
correspond to bit settings in SRR1 and arise during execution of an instruction:
• Illegal instruction—An illegal instruction program exception is generated when
execution of an instruction is attempted with an illegal opcode or illegal
combination of opcode and extended opcode fields (including PowerPC
instructions not implemented in the processor core), or when execution of an
optional instruction not provided in the processor core is attempted (these do not
include those optional instructions that are treated as no-ops).
• Privileged instruction—A privileged instruction type program exception is
generated when the execution of a privileged instruction is attempted and the
MSR register user privilege bit, MSR[PR], is set. In the processor core, this
exception is generated for mtspr or mfspr with an invalid SPR field if SPR[0] = 1
and MSR[PR] = 1. This may not be true for all processors that implement the
PowerPC architecture.
• Trap—A trap type program exception is generated when any of the conditions
specified in a trap instruction is met.
Floating-point 00800
unavailable
A floating-point unavailable exception is caused by an attempt to execute a
floating-point instruction (including floating-point load, store, and move instructions)
when the floating-point available bit is cleared (MSR[FP] = 0).
Decrementer
00900
The decrementer exception occurs when the most significant bit of the decrementer
(DEC) register transitions from 0 to 1. Must also be enabled with the MSR[EE] bit.
Reserved
System call
Trace
00A00–00BFF —
00C00
00D00
A system call exception occurs when a System Call (sc) instruction is executed.
A trace exception is taken when MSR[SE] = 1 or when the currently completing
instruction is a branch and MSR[BE] = 1.
Floating-point 00E00
Not implemented.
assist
Reserved
00E10–00FFF —
Instruction
translation
miss
01000
An instruction translation miss exception is caused when the effective address for an
instruction fetch cannot be translated by the ITLB.
Data load
translation
miss
01100
A data load translation miss exception is caused when the effective address for a
data load operation cannot be translated by the DTLB.
Data store
translation
miss
01200
A data store translation miss exception is caused when the effective address for a
data store operation cannot be translated by the DTLB, or when a DTLB hit occurs,
and the changed bit in the PTE must be set due to a data store operation.
Instruction
address
breakpoint
01300
An instruction address breakpoint exception occurs when the address (bits 0–29) in
the IABR matches the next instruction to complete in the completion unit, and the
IABR enable bit (bit 30) is set.
System
management
interrupt
01400
A system management interrupt is caused when MSR[EE] = 1 and the SMI input
signal is asserted.
Reserved
01500–02FFF
—
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G2 Core
2.5.3
Exception Priorities
The exception priorities for the processor core are unchanged from those described in the G2 Core
reference Manual except for the alignment exception, whose causes are prioritized as follows:
1. Floating-point operand not word-aligned
2. lmw, stmw, lwarx, or stwcx. operand not word-aligned
3. eciwx or ecowx operand misaligned
4. A multiple or string access is attempted with MSR[LE] set
2.6
Memory Management
The following subsections describe the memory management features of the PowerPC architecture and the
PowerQUICC II implementation.
2.6.1
PowerPC MMU Model
The primary functions of the MMU are to translate logical (effective) addresses to physical addresses for
memory accesses, and to provide access protection on blocks and pages of memory.
There are two types of accesses generated by the processor core that require address
translation—instruction accesses and data accesses to memory generated by load and store instructions.
The PowerPC MMU and exception models support demand-paged virtual memory. Virtual memory
management permits execution of programs larger than the size of physical memory; demand-paged
implies that individual pages are loaded into physical memory from system memory only when they are
first accessed by an executing program.
The PowerPC architecture supports the following three translation methods:
•
Address translations disabled. Translation is enabled by setting bits in the MSR—MSR[IR] enables
instruction address translations and MSR[DR] enables data address translations. Clearing these
bits disables translation and the effective address is used as the physical address.
•
Block address translation. The PowerPC architecture defines independent four-entry BAT arrays
for instructions and data that maintain address translations for blocks of memory. Block sizes range
from 128 Kbyte to 256 Mbyte and are software selectable. The BAT arrays are maintained by
system software. The BAT registers, defined by the PowerPC architecture for block address
•
Demand page mode. The page table contains a number of page table entry groups (PTEGs). A
PTEG contains eight page table entries (PTEs) of eight bytes each; therefore, each PTEG is 64 bytes
long. PTEG addresses are entry points for table search operations.
The hashed page table is a variable-sized data structure that defines the mapping between virtual
page numbers and physical page numbers. The page table size is a power of 2, and its starting
address is a multiple of its size.
On-chip instruction and data TLBs provide address translation in parallel with the on-chip cache
access, incurring no additional time penalty in the event of a TLB hit. A TLB is a cache of the most
recently used page table entries. Software is responsible for maintaining the consistency of the
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G2 Core
TLB with memory. In the PowerQUICC II, the processor core’s TLBs are 64-entry, two-way
set-associative caches that contain instruction and data address translations. The PowerQUICC II’s
core provides hardware assist for software table search operations through the hashed page table
on TLB misses. Supervisor software can invalidate TLB entries selectively.
The MMU also directs the address translation and enforces the protection hierarchy programmed by the
operating system in relation to the supervisor/user privilege level of the access and in relation to whether
the access is a load or store.
2.6.2
PowerQUICC II Implementation-Specific MMU Features
The instruction and data MMUs in the processor core provide 4-Gbytes of logical address space accessible
to supervisor and user programs with a 4-Kbyte page size and 256-Mbyte segment size.
The PowerQUICC II’s MMUs support up to 4 Petabytes (252) of virtual memory and 4 Gbytes (232) of
physical memory (referred to as real memory in the PowerPC architecture specification) for instructions
and data. Referenced and changed status is maintained by the processor for each page to assist
implementation of a demand-paged virtual memory system.
The PowerQUICC II’s TLBs are 64-entry, two-way set-associative caches that contain instruction and data
address translations. The processor core provides hardware assist for software table search operations
through the hashed page table on TLB misses. Supervisor software can invalidate TLB entries selectively.
After an effective address is generated, the higher-order bits of the effective address are translated by the
appropriate MMU into physical address bits. Simultaneously, the lower-order address bits (that are
untranslated and therefore, considered both logical and physical), are directed to the on-chip caches where
they form the index into the four-way set-associative tag array. After translating the address, the MMU
passes the higher-order bits of the physical address to the cache, and the cache lookup completes. For
caching-inhibited accesses or accesses that miss in the cache, the untranslated lower-order address bits are
concatenated with the translated higher-order address bits; the resulting 32-bit physical address is then
used by the system interface, which accesses external memory.
For instruction accesses, the MMU performs an address lookup in both the 64 entries of the ITLB, and in
the IBAT array. If an effective address hits in both the ITLB and the IBAT array, the IBAT array translation
takes priority. Data accesses cause a lookup in the DTLB and DBAT array for the physical address
translation. In most cases, the physical address translation resides in one of the TLBs and the physical
address bits are readily available to the on-chip cache.
When the physical address translation misses in the TLBs, the processor core provides hardware assistance
for software to search the translation tables in memory. When a required TLB entry is not found in the
appropriate TLB, the processor vectors to one of the three TLB miss exception handlers so that the
software can perform a table search operation and load the TLB. When this occurs, the processor
automatically saves information about the access and the executing context. Refer to the G2 Core reference
Manual for more detailed information about these features and the suggested software routines for
searching the page tables.
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G2 Core
2.7
Instruction Timing
The processor core is a pipelined superscalar processor. A pipelined processor is one in which the
processing of an instruction is broken into discrete stages. Because the processing of an instruction is
broken into a series of stages, an instruction does not require the entire resources of an execution unit at
one time. For example, after an instruction completes the decode stage, it can pass on to the next stage,
while the subsequent instruction can advance into the decode stage. This improves the throughput of the
instruction flow. The instruction pipeline in the processor core has four major stages, described as follows:
•
The fetch pipeline stage primarily involves retrieving instructions from the memory system and
determining the location of the next instruction fetch. Additionally, the BPU decodes branches
during the fetch stage and folds out branch instructions before the dispatch stage if possible.
•
The dispatch pipeline stage is responsible for decoding the instructions supplied by the instruction
fetch stage, and determining which of the instructions are eligible to be dispatched in the current
cycle. In addition, the source operands of the instructions are read from the appropriate register file
and dispatched with the instruction to the execute pipeline stage. At the end of the dispatch pipeline
stage, the dispatched instructions and their operands are latched by the appropriate execution unit.
•
During the execute pipeline stage, each execution unit that has an executable instruction executes
the selected instruction (perhaps over multiple cycles), writes the instruction's result into the
appropriate rename register, and notifies the completion stage that the instruction has finished
execution.
The execution unit reports any internal exceptions to the completion/writeback pipeline stage and
discontinues execution until the exception is handled. The exception is not signaled until that
instruction is the next to be completed. Execution of most load/store instructions is also pipelined.
The load/store unit has two pipeline stages. The first stage is for effective address calculation and
MMU translation and the second stage is for accessing the data in the cache.
•
The complete/writeback pipeline stage maintains the correct architectural machine state and
transfers the contents of the rename registers to the GPRs and FPRs as instructions are retired. If
the completion logic detects an instruction causing an exception, all following instructions are
cancelled, their execution results in rename registers are discarded, and instructions are fetched
from the correct instruction stream.
The processor core provides support for single-cycle store operations and it provides an adder/comparator
in the SRU that allows the dispatch and execution of multiple integer add and compare instructions on each
cycle.
Performance of integer divide operations has been improved in the processor core. A divide instruction
takes half the cycles to execute as described in the G2 Core reference Manual. The new latency is reflected
Table 2-6. Integer Divide Latency
Primary Opcode
Extended Opcode
Mnemonic
Form
Unit
Cycles
31
31
459
491
divwu[o][.]
xo
xo
IU
IU
20
20
divw[o][.]
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G2 Core
2.8
Differences between the PowerQUICC II’s
G2 Core and the MPC603e Microprocessor
The PowerQUICC II’s processor core is a derivative of the MPC603e microprocessor design. Some
changes have been made and are visible either to a programmer or a system designer. Any software
designed around an MPC603e is functional when replaced with the PowerQUICC II except for the specific
Software can distinguish between the MPC603e and the PowerQUICC II by reading the processor version
register (PVR). The PowerQUICC II’s processor version number is 0x0081; the processor revision level
starts at 0x0100 and is incremented for each revision of the chip.
Table 2-7. Major Differences between PowerQUICC II’s G2 Core and the
MPC603e User’s Manual
Description
Impact
Added bus multipliers of 4.5x, 5x, 5.5x, Occupies unused encodings of the PLL_CFG[0–4]
6x, 6.5x 7x, 7.5x, 8x
Added hardware support for misaligned Except for strings/multiples, little-endian load/store accesses not on a word
little endian accesses
boundary generate exceptions under the same circumstances as
big-endian accesses.
Removed misalignment support for
These instructions take an alignment exception if not on a word boundary.
eciwx and ecowx instructions.
Added ability to broadcast dcbf, dcbi,
and dcbst onto the 60x bus
Setting HID0[ABE] enables the new broadcast feature (new in the
PID7v-603e). The default is to not broadcast these operations.
Added ability to reflect the value of the M Setting HID0[IFEM] enables this feature. The default is to not present the M
bit onto the 60x bus during instruction
translations
bit on the bus.
Removed HID0[EICE]
There is no support for ICE pipeline tracking.
Added instruction and data cache
locking mechanism
Implements a cache way locking mechanism for both the instruction and
data caches. One to three of the four ways in the cache can be locked with
control bits in the HID2 register. See Section 2.3.1.2.3, “Hardware
Added pin-configurable reset vector
The value of MSR[IP], interrupt prefix, is determined at hard reset by the
hardware configuration word.
Addition of speed-for-power functionality The processor core implements an additional dynamic power management
mechanism. HID2[SFP] controls this function. See Section 2.3.1.2.3,
Improved access to cache during block The PowerQUICC II provides quicker access to incoming data and instruc-
fills
tion on a cache block fill. See Section 2.4.2, “PowerQUICC II Implementa-
Improved integer divide latency
Performance of integer divide operations has been improved in the
processor core. A divide takes half the cycles to execute as described in
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Chapter 3
Memory Map
The PowerQUICC II’s internal memory resources are mapped within a contiguous block of memory. The
size of the internal space is 128 Kbytes. The location of this block within the global 4-Gbyte real memory
space can be mapped on 128 Kbytes resolution through an implementation-specific special register called
the internal memory map register (IMMR). For more information, see Section 4.3.2.7, “Internal Memory
Table 3-1. Internal Memory Map
Address
(offset)
Register
R/W
Size
Reset
Section/Page
CPM Dual-Port RAM
0x00000– Dual-port RAM (DPRAM1)
0x03FFF
R/W
16
Kbytes
—
—
—
—
—
—
—
—
1
0x04000– Dual-port RAM (microcode only) (DPRAM)
0x05FFF
R/W 8 Kbytes
0x06000– Reserved
0x07FFF
—
8 Kbytes
0x08000– Dual-port RAM (DPRAM2)
0x08FFF
R/W 4 Kbytes
—
0x09000– Reserved
0x0AFFF
—
8 Kbytes
0x0B000– Dual-port RAM (DPRAM3)
0x0BFFF
R/W 4 Kbytes
—
0x0C000– Reserved
0x0FFFF
—
16
Kbytes
General SIU
0x10000 SIU module configuration register (SIUMCR)
0x10004 System protection control register (SYPCR)
0x10008 Reserved
R/W
R/W
—
—
32 bits
6 bytes
16 bits
0xFFFF_FF07
—
undefined
—
0x1000E Software service register (SWSR)
W
—
0x10010– Reserved
0x10023
—
20 bytes
0x10024 Bus configuration register (BCR)
R/W
R/W
32 bits
8 bits
reset
configuration
0x10028 60x bus arbiter configuration register (PPC_ACR)
see Figure 4-22
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3-1
Memory Map
Table 3-1. Internal Memory Map (continued)
Address
(offset)
Register
R/W
Size
Reset
Section/Page
0x10029 Reserved
—
24 bits
32 bits
—
—
0x1002C 60x bus arbitration-level register high (first 8 clients)
(PPC_ALRH)
R/W
0x0126_3457
0x10030 60x bus arbitration-level register low (next 8 clients)
(PPC_ALRL)
R/W
32 bits 0x89AB_CDEF
0x10034 Local arbiter configuration register (LCL_ACR)
0x10035 Reserved
R/W
—
8 bits
24 bits
32 bits
0x02
—
—
0x10038 Local arbitration-level register (first 8 clients) (LCL_ALRH) R/W
0x1003C Local arbitration-level register (next 8 clients) (LCL_ALRL) R/W
0x0126_3457
32 bits 0x89AB_ CDEF
0x10040 60x bus transfer error status control register 1 (TESCR1)
0x10044 60x bus transfer error status control register 2 (TESCR2)
R/W
R/W
R/W
32 bits
32 bits
32 bits
0x0000_0000
0x0000_0000
0x0000_0000
0x10048 Local bus transfer error status control register 1
(L_TESCR1)
0x1004C Local bus transfer error status control register 2
(L_TESCR2)
R/W
32 bits
0x0000_0000
0x10050 60x bus DMA transfer error address (PDTEA)
0x10054 60x bus DMA transfer error MSNUM (PDTEM)
0x10055 Reserved
R
R
32 bits
8 bits
undefined
undefined
—
—
—
R
24 bits
32 bits
8 bits
0x10058 Local bus DMA transfer error address (LDTEA)
0x1005C Local bus DMA transfer error MSNUM (LDTEM)
undefined
undefined
—
—
R
0x1005D– Reserved
0x100FF
—
163
bytes
Memory Controller
0x10100 Base register bank 0 (BR0)
0x10104 Option register bank 0 (OR0)
0x10108 Base register bank 1 (BR1)
0x1010C Option register bank 1 (OR1)
0x10110 Base register bank 2 (BR2)
0x10114 Option register bank 2 (OR2)
0x10118 Base register bank 3 (BR3)
0x1011C Option register bank 3 (OR3)
0x10120 Base register bank 4 (BR4)
0x10124 Option register bank 4 (OR4)
0x10128 Base register bank 5 (BR5)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
0xFE00_0EF4
0x0000_0000
undefined
0x0000_0000
undefined
0x0000_0000
undefined
0x0000_0000
undefined
0x0000_0000
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Memory Map
Table 3-1. Internal Memory Map (continued)
Address
(offset)
Register
R/W
Size
Reset
Section/Page
0x1012C Option register bank 5 (OR5)
0x10130 Base register bank 6 (BR6)
0x10134 Option register bank 6 (OR6)
0x10138 Base register bank 7 (BR7)
0x1013C Option register bank 7 (OR7)
0x10140 Base register bank 8 (BR8)
0x10144 Option register bank 8 (OR8)
0x10148 Base register bank 9 (BR9)
0x1014C Option register bank 9 (OR9)
0x10150 Base register bank 10 (BR10)
0x10154 Option register bank 10 (OR10)
0x10158 Base register bank 11 (BR11)
0x1015C Option register bank 11 (OR11)
0x10160 Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
8 bytes
32 bits
32 bits
32 bits
32 bits
32 bits
48 bits
16 bits
32 bits
32 bits
32 bits
32 bits
8 bits
undefined
0x0000_0000
undefined
0x0000_0000
undefined
0x0000_0000
undefined
0x0000_0000
undefined
0x0000_0000
undefined
0x0000_0000
undefined
—
—
0x10168 Memory address register (MAR)
0x1016C Reserved
R/W
—
undefined
—
—
0x10170 Machine A mode register (MAMR)
0x10174 Machine B mode register (MBMR)
0x10178 Machine C mode register (MCMR)
0x1017C Reserved
R/W
R/W
R/W
—
0x0004_0000
0x0004_0000
0x0004_0000
—
—
0x10184 Memory periodic timer prescaler (MPTPR)
0x10188 Memory data register (MDR)
0x1018C Reserved
R/W
R/W
—
undefined
undefined
—
—
0x10190 60x bus SDRAM mode register (PSDMR)
0x10194 Local bus SDRAM mode register (LSDMR)
0x10198 60x bus-assigned UPM refresh timer (PURT)
0x10199 Reserved
R/W
R/W
R/W
—
0x0000_0000
0x0000_0000
0x00
—
24 bits
8 bits
—
0x1019C 60x bus-assigned SDRAM refresh timer (PSRT)
0x1019D Reserved
R/W
—
0x00
—
24 bits
8 bits
—
0x101A0 Local bus-assigned UPM refresh timer (LURT)
0x101A1 Reserved
R/W
—
0x00
—
24 bits
8 bits
—
0x101A4 Local bus-assigned SDRAM refresh timer (LSRT)
R/W
0x00
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3-3
Memory Map
Table 3-1. Internal Memory Map (continued)
Address
(offset)
Register
R/W
Size
Reset
Section/Page
0x101A5 Reserved
—
24 bits
32 bits
—
—
0x101A8 Internal memory map register (IMMR)
R/W
reset
configuration
2
0x101AC PCI base register 0 (PCIBR0)
R/W
R/W
—
32 bits
32 bits
0x0000_0000
0x0000_0000
—
—
2
0x101B0 PCI base register 1 (PCIBR1)
0x101B4– Reserved
0x101C3
16 bytes
2
0x101C4 PCI mask register 0 (PCIMSK0)
R/W
R/W
—
32 bits
32 bits
0x0000_0000
0x0000_0000
—
—
2
0x101C8 PCI mask register 1 (PCIMSK1)
0x101CC– Reserved
0x101FF
52 bytes
System Integration Timers
0x10200– Reserved
0x10 21F
—
32 bytes
—
—
0x10220 Time counter status and control register (TMCNTSC)
0x10224 Time counter register (TMCNT)
0x10228 Reserved
R/W
R/W
—
16 bits
32 bits
32 bits
32 bits
16 bytes
0x0000
0x0000_0000
—
—
0x1022C Time counter alarm register (TMCNTAL)
R/W
—
0x0000_0000
—
—
0x10230– Reserved
0x1023F
0x10240 Periodic interrupt status and control register (PISCR)
0x10244 Periodic interrupt count register (PITC)
0x10248 Periodic interrupt timer register (PITR)
R/W
R/W
R
16 bits
32 bits
0x0000
0x0000_0000
0x0000_0000
—
—
32 bits
0x1024C– Reserved
0x102A8
—
92 bytes
0x102AA– Reserved
0x1042F
—
372
bytes
—
—
2
PCI
2
0x10430 Outbound interrupt status register (OMISR)
R/W
R/W
R/W
R/W
R/W
R/W
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
undefined
2
0x10434 Outbound interrupt mask register (OMIMR)
2
0x10440 Inbound FIFO queue port register (IFQPR)
2
0x10444 Outbound FIFO queue port register (OFQPR)
2
0x10450 Inbound message register 0 (IMR0)
2
0x10454 Inbound message register 1 (IMR1)
undefined
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
3-4
Freescale Semiconductor
Memory Map
Table 3-1. Internal Memory Map (continued)
Address
(offset)
Register
R/W
Size
Reset
Section/Page
2
2
0x10458 Outbound message register 0 (OMR0)
0x1045C Outbound message register 1 (OMR1)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
undefined
undefined
2
0x10460 Outbound doorbell register (ODR)
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0002
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
2
0x10468 Inbound doorbell register (IDR)
2
0x10480 Inbound message interrupt status register (IMISR)
2
0x10484 Inbound message interrupt mask register (IMIMR)
2
0x104A0 Inbound free_FIFO head pointer register (IFHPR)
2
0x104A8 Inbound free_FIFO tail pointer register (IFTPR)
2
0x104B0 Inbound post_FIFO head pointer register (IPHPR)
2
0x104B8 Inbound post_FIFO tail pointer register (IPTPR)
2
0x104C0 Outbound free_FIFO head pointer register (OFHPR)
2
0x104C8 Outbound free_FIFO tail pointer register (OFTPR)
2
0x104D0 Outbound post_FIFO head pointer register (OPHPR)
2
0x104D8 Outbound post_FIFO tail pointer register (OPTPR)
2
0x104E4 Message unit control register (MUCR)
2
0x104F0 Queue base address register (QBAR)
2
0x10500 DMA 0 mode register (DMAMR0)
2
0x10504 DMA 0 status register (DMASR0)
2
0x10508 DMA 0 current descriptor address register (DMACDAR0)
2
0x10510 DMA 0 source address register (DMASAR0)
2
0x10518 DMA 0 destination address register (DMADAR0)
2
0x10520 DMA 0 byte count register (DMABCR0)
2
0x10524 DMA 0 next descriptor address register (DMANDAR0)
2
0x10580 DMA 1 mode register (DMAMR1)
2
0x10584 DMA 1 status register (DMASR1)
2
0x10588 DMA 1 current descriptor address register (DMACDAR1)
2
0x10590 DMA 1 source address register (DMASAR1)
2
0x10598 DMA 1 destination address register (DMADAR1)
2
0x105A0 DMA 1 byte count register (DMABCR1)
2
0x105A4 DMA 1 next descriptor address register (DMANDAR1)
2
0x10600 DMA 2 mode register (DMAMR2)
2
0x10604 DMA 2 status register (DMASR2)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
3-5
Memory Map
Table 3-1. Internal Memory Map (continued)
Address
(offset)
Register
R/W
Size
Reset
Section/Page
2
0x10608 DMA 2 current descriptor address register (DMACDAR2)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0FFF
0x0000_00FF
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
2
0x10610 DMA 2 source address register (DMASAR2)
2
0x10618 DMA 2 destination address register (DAR2)
2
0x10620 DMA 2 byte count register (DMABCR2)
2
0x10624 DMA 2 next descriptor address register (DMANDAR2)
2
0x10680 DMA 3 mode register (DMAMR3)
2
0x10684 DMA 3 status register (DMASR3)
2
0x10688 DMA 3 current descriptor address register (DMACDAR3)
2
0x10690 DMA 3 source address register (DMASAR3)
2
0x10698 DMA 3 destination address register (DMADAR3)
2
0x106A0 DMA 3 byte count register (DMABCR3)
2
0x106A4 DMA 3 next descriptor address register (DMANDAR3)
2
0x10800 PCI outbound translation address register 0 (POTAR0)
2
0x10808 PCI outbound base address register 0 (POBAR0)
2
0x10810 PCI outbound comparison mask register 0 (POCMR0)
2
0x10818 PCI outbound translation address register 1 (POTAR1)
2
0x10820 PCI outbound base address register 1 (POBAR1)
2
0x10828 PCI outbound comparison mask register 1 (POCMR1)
2
0x10830 PCI outbound translation address register 2 (POTAR2)
2
0x10838 PCI outbound base address register 2 (POBAR2)
2
0x10840 PCI outbound comparison mask register 2 (POCMR2)
2
0x10878 Discard timer control register (PTCR)
2
0x1087C General purpose control register (GPCR)
2
0x10880 PCI general control register (PCI_GCR)
2
0x10884 Error status register (ESR)
2
0x10888 Error mask register (EMR)
2
0x1088C Error control register (ECR)
2
0x10890 PCI error address capture register (PCI_EACR)
2
0x10898 PCI error data capture register (PCI_EDCR)
2
0x108A0 PCI error control capture register (PCI_ECCR)
2
0x108D0 PCI inbound translation address register 1 (PITAR1)
2
0x108D8 PCI inbound base address register 1 (PIBAR1)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
3-6
Freescale Semiconductor
Memory Map
Table 3-1. Internal Memory Map (continued)
Address
(offset)
Register
R/W
Size
Reset
Section/Page
2
0x108E0 PCI inbound comparison mask register 1 (PICMR1)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
undefined
2
0x108E8 PCI inbound translation address register 0 (PITAR0)
2
0x108F0 PCI inbound base address register 0 (PIBAR0)
2
0x108F8 PCI inbound comparison mask register 0 (PICMR0)
2
0x10900 PCI CFG_ADDR
2
0x10904 PCI CFG_DATA
0x0000_0000
undefined
2
0x10908 PCI INT_ACK
Interrupt Controller
0x10C00 SIU interrupt configuration register (SICR)
R/W
—
16 bits
16 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
88 bytes
0x0000
—
—
0x10C02 Reserved
0x10C04 SIU interrupt vector register (SIVEC)
0x10C08 SIU interrupt pending register (high) (SIPNR_H)
0x10C0C SIU interrupt pending register (low) (SIPNR_L)
0x10C10 SIU interrupt priority register (SIPRR)
0x10C14 CPM interrupt priority register (high) (SCPRR_H)
0x10C18 CPM interrupt priority register (low) (SCPRR_L)
0x10C1C SIU interrupt mask register (high) (SIMR_H)
0x10C20 SIU interrupt mask register (low) (SIMR_L)
0x10C24 SIU external interrupt control register (SIEXR)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
0x0000_0000
undefined
—
0x0000_0000
0x0530_9770
0x0530_9770
0x0530_9770
0x0000_0000
0x0000_0000
0x0000_0000
—
0x10C28– Reserved
0x10C7F
Clocks and Reset
0x10C80 System clock control register (SCCR)
32 bits
R/W
0x10C88 System clock mode register (SCMR)
0x10C90 Reset status register (RSR)
0x10C94 Reset mode register (RMR)
R
32 bits
32 bits
32 bits
0x0000_0003
0x0000_0000
—
—
R/W
R/W
—
0x10C98– Reserved
0x10CFF
104
bytes
Input/Output Port
0x10D00 Port A data direction register (PDIRA)
0x10D04 Port A pin assignment register (PPARA)
0x10D08 Port A special options register (PSORA)
R/W
R/W
R/W
32 bits
32 bits
32 bits
0x0000_0000
0x0000_0000
0x0000_0000
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
3-7
Memory Map
Table 3-1. Internal Memory Map (continued)
Address
(offset)
Register
R/W
Size
Reset
Section/Page
0x10D0C Port A open drain register (PODRA)
0x10D10 Port A data register (PDATA)
R/W
R/W
—
32 bits
32 bits
0x0000_0000
0x0000_0000
—
—
0x10D14– Reserved
0x10D1F
12 bytes
0x10D20 Port B data direction register (PDIRB)
0x10D24 Port B pin assignment register (PPARB)
0x10D28 Port B special option register (PSORB)
0x10D2C Port B open drain register (PODRB)
0x10D30 Port B data register (PDATB)
R/W
R/W
R/W
R/W
R/W
—
32 bits
32 bits
32 bits
32 bits
32 bits
12 bytes
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
—
—
0x10D34– Reserved
0x10D3F
0x10D40 Port C data direction register (PDIRC)
0x10D44 Port C pin assignment register (PPARC)
0x10D48 Port C special option register (PSORC)
0x10D4C Port C open drain register (PODRC)
0x10D50 Port C data register (PDATC)
R/W
R/W
R/W
R/W
R/W
—
32 bits
32 bits
32 bits
32 bits
32 bits
12 bytes
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
—
—
0x10D54– Reserved
0x10D5F
0x10D60 Port D data direction register (PDIRD)
0x10D64 Port D pin assignment register (PPARD)
0x10D68 Port D special option register (PSORD)
0x10D6C Port D open drain register (PODRD)
0x10D70 Port D data register (PDATD)
R/W
R/W
R/W
R/W
R/W
32 bits
32 bits
32 bits
32 bits
32 bits
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
CPM Timers
0x10D80 Timer 1 and timer 2 global configuration register (TGCR1) R/W
0x10D81 Reserved
0x10D84 Timer 3 and timer 4 global configuration register (TGCR2) R/W
8 bits
24 bits
8 bits
0x00
—
—
—
—
0x00
—
0x10D85– Reserved
0x10D8F
—
11 bytes
0x10D90 Timer 1 mode register (TMR1)
0x10D92 Timer 2 mode register (TMR2)
0x10D94 Timer 1 reference register (TRR1)
0x10D96 Timer 2 reference register (TRR2)
R/W
R/W
R/W
R/W
16 bits
16 bits
16 bits
16 bits
0x0000
0x0000
0x0000
0x0000
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
3-8
Freescale Semiconductor
Memory Map
Table 3-1. Internal Memory Map (continued)
Address
(offset)
Register
R/W
Size
Reset
Section/Page
0x10D98 Timer 1 capture register (TCR1)
0x10D9A Timer 2 capture register (TCR2)
0x10D9C Timer 1 counter (TCN1)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
—
—
0x10D9E Timer 2 counter (TCN2)
0x10DA0 Timer 3 mode register (TMR3)
0x10DA2 Timer 4 mode register (TMR4)
0x10DA4 Timer 3 reference register (TRR3)
0x10DA6 Timer 4 reference register (TRR4)
0x10DA8 Timer 3 capture register (TCR3)
0x10DAA Timer 4 capture register (TCR4)
0x10DAC Timer 3 counter (TCN3)
0x10DAE Timer 4 counter (TCN4)
0x10DB0 Timer 1 event register (TER1)
0x10DB2 Timer 2 event register (TER2)
0x10DB4 Timer 3 event register (TER3)
0x10DB6 Timer 4 event register (TER4)
0x10DB8– Reserved
0x11017
608
bytes
SDMA–General
0x11018 SDMA status register (SDSR)
0x11019 Reserved
R/W
—
8 bits
24 bits
8 bits
0x00
—
—
—
0x1101C SDMA mask register (SDMR)
0x1101D Reserved
R/W
—
0x00
—
24 bits
IDMA
0x11020 IDMA 1 event register (IDSR1)
0x11021 Reserved
R/W
—
8 bits
24 bits
8 bits
0x00
—
—
—
0x11024 IDMA 1 mask register (IDMR1)
0x11025 Reserved
R/W
—
0x00
—
24 bits
8 bits
0x11028 IDMA 2 event register (IDSR2)
0x11029 Reserved
R/W
—
0x00
—
—
24 bits
8 bits
0x1102C IDMA 2 mask register (IDMR2)
0x1102D Reserved
R/W
—
0x00
—
—
24 bits
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
3-9
Memory Map
Table 3-1. Internal Memory Map (continued)
Address
(offset)
Register
R/W
Size
Reset
Section/Page
0x11030 IDMA 3 event register (IDSR3)
0x11031 Reserved
R/W
—
8 bits
24 bits
8 bits
0x00
—
—
—
0x11034 IDMA 3 mask register (IDMR3)
0x11035 Reserved
R/W
—
0x00
—
24 bits
8 bits
0x11038 IDMA 4 event register (IDSR4)
0x11039 Reserved
R/W
—
0x00
—
—
24 bits
8 bits
0x1103C IDMA 4 mask register (IDMR4)
R/W
—
0x00
—
—
0x1103D– Reserved
0x112FF
707
bytes
FCC1
0x11300 FCC1 general mode register (GFMR1)
R/W
R/W
32 bits
32 bits
0x0000_0000
0x0000_0000
0x11304 FCC1 protocol-specific mode register (FPSMR1)
(ATM)
(IMA)
(Ethernet)
(HDLC)
0x11308 FCC1 transmit on demand register (FTODR1)
0x1130A Reserved
R/W
—
16 bits
16 bits
16 bits
16 bits
16 bits
0x0000
—
—
0x1130C FCC1 data synchronization register (FDSR1)
0x1130E Reserved
R/W
—
0x7E7E
—
—
0x11310 FCC1 event register (FCCE1)
R/W
0x0000_0000
(ATM)
(Ethernet)
(HDLC)
0x11312 Reserved
—
16 bits
16 bits
—
—
0x11314 FCC1 mask register (FCCM1)
R/W
0x0000_0000
(ATM)
(Ethernet)
(HDLC)
0x11316 Reserved
—
R
16 bits
16 bits
—
—
0x11318 FCC1 status register (FCCS1)
0x00
(HDLC)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
3-10
Freescale Semiconductor
Memory Map
Table 3-1. Internal Memory Map (continued)
Address
(offset)
Register
R/W
Size
Reset
Section/Page
0x11319 Reserved
—
24 bits
8 bits
—
—
0x1131C FCC1 transmit internal rate registers for PHY0
(FTIRR1_PHY0)
R/W
0x00
(ATM)
(IMA)
0x1131D FCC1 transmit internal rate registers for PHY1
(FTIRR1_PHY1)
R/W
R/W
R/W
8 bits
8 bits
8 bits
0x00
0x00
0x00
0x1131E FCC1 transmit internal rate registers for PHY2
(FTIRR1_PHY2)
0x1131F FCC1 transmit internal rate registers for PHY3
(FTIRR1_PHY3)
FCC2
0x11320 FCC2 general mode register (GFMR2)
R/W
R/W
32 bits
32 bits
0x0000_0000
0x0000_0000
0x11324 FCC2 protocol-specific mode register (FPSMR2)
(ATM)
(IMA)
(Ethernet)
(HDLC)
0x11328 FCC2 transmit on-demand register (FTODR2)
0x1132A Reserved
R/W
—
16 bits
16 bits
16 bits
16 bits
16 bits
0x0000
—
—
0x1132C FCC2 data synchronization register (FDSR2)
0x1132E Reserved
R/W
—
0x7E7E
—
—
0x11330 FCC2 event register (FCCE2)
R/W
0x0000_0000
(ATM)
(Ethernet)
(HDLC)
0x11332 Reserved
—
16 bits
16 bits
—
—
0x11334 FCC2 mask register (FCCM2)
R/W
0x0000_0000
(ATM)
(Ethernet)
(HDLC)
0x11336 Reserved
—
R
16 bits
16 bits
—
—
0x11338 FCC2 status register (FCCS2)
0x00
(HDLC)
0x11339 Reserved
—
24 bits
—
—
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
3-11
Memory Map
Table 3-1. Internal Memory Map (continued)
Address
(offset)
Register
R/W
Size
Reset
Section/Page
0x1133C FCC2 transmit internal rate registers for PHY0
(FTIRR2_PHY0)
R/W
8 bits
0x00
(ATM)
(IMA)
0x1133D FCC2 transmit internal rate registers for PHY1
(FTIRR2_PHY1)
R/W
R/W
R/W
8 bits
8 bits
8 bits
0x00
0x00
0x00
0x11133E FCC2 transmit internal rate registers for PHY2
(FTIRR2_PHY2)
0x1133F FCC2 transmit internal rate registers for PHY3
(FTIRR2_PHY3)
3
FCC3
3
0x11340 FCC3 general mode register (GFMR3)
R/W
R/W
32 bits
32 bits
0x0000_0000
0x0000_0000
3
0x11344 FCC3 protocol-specific mode register (FPSMR3)
(ATM)
(IMA)
(Ethernet)
(HDLC)
3
0x11348 FCC3 transmit on-demand register (FTODR3)
R/W
—
16 bits
16 bits
16 bits
16 bits
16 bits
0x0000
—
—
0x1134A Reserved
3
0x1134C FCC3 data synchronization register (FDSR3)
R/W
—
0x7E7E
—
—
0x1134E Reserved
3
0x11350 FCC3 event register (FCCE3)
R/W
0x0000_0000
(ATM)
(Ethernet)
(HDLC)
0x11352 Reserved
—
16 bits
16 bits
—
—
3
0x11354 FCC3 mask register (FCCM3)
R/W
0x0000_0000
(ATM)
(Ethernet)
(HDLC)
0x11356 Reserved
—
R
16 bits
16 bits
—
—
3
0x11358 FCC3 status register (FCCS3)
0x00
(HDLC)
0x11359– Reserved
0x113FF
—
167
bytes
—
—
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
3-12
Freescale Semiconductor
Memory Map
Table 3-1. Internal Memory Map (continued)
Address
(offset)
Register
R/W
Size
Reset
Section/Page
4
4
4
TC Layer 1
4
0x11400 TC1 mode register (TCMODE1)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
12 bytes
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
—
—
4
0x11402 TC1 cell delineation state machine register (CDSMR1)
4
0x11404 TC1 event register (TCER1)
4
0x11406 TC1 received cells counter (TC_RCC1)
4
0x11408 TC1 mask register (TCMR1)
4
0x1140A TC1 filtered cells counter (TC_FCC1)
4
0x1140C TC1 corrected cells counter (TC_CCC1)
4
0x1140E TC1 idle cells counter (TC_ICC1)
4
0x11410 TC1 transmitted cells counter (TC_TCC1)
4
0x11412 TC1 error cells counter (TC_ECC1)
0x11414 Reserved
TC Layer 2
4
0x11420 TC2 mode register (TCMODE2)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
12 bytes
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
—
—
4
0x11422 TC2 cell delineation state machine register (CDSMR2)
4
0x11424 TC2 event register (TCER2)
4
0x11426 TC2 received cells counter (TC_RCC2)
4
0x11428 TC2 mask register (TCMR2)
4
0x1142A TC2 filtered cells counter (TC_FCC2)
4
0x1142C TC2 corrected cells counter (TC_CCC2)
4
0x1142E TC2 idle cells counter (TC_ICC2)
4
0x11430 TC2 transmitted cells counter (TC_TCC2)
4
0x11432 TC2 error cells counter (TC_ECC2)
0x11434 Reserved
TC Layer 3
4
0x11440 TC3 mode register (TCMODE3)
R/W
R/W
R/W
R/W
R/W
R/W
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
4
0x11442 TC3 cell delineation state machine register (CDSMR3)
4
0x11444 TC3 event register (TCER3)
4
0x11446 TC3 received cells counter (TC_RCC3)
4
0x11448 TC3 mask register (TCMR3)
4
0x1144A TC3 filtered cells counter (TC_FCC3)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
3-13
Memory Map
Table 3-1. Internal Memory Map (continued)
Address
(offset)
Register
R/W
Size
Reset
Section/Page
4
0x1144C TC3 corrected cells counter (TC_CCC3)
R/W
R/W
R/W
R/W
—
16 bits
16 bits
16 bits
16 bits
12 bytes
0x0000
0x0000
0x0000
0x0000
—
—
4
0x1144E TC3 idle cells counter (TC_ICC3)
4
0x11450 TC3 transmitted cells counter (TC_TCC3)
4
0x11452 TC3 error cells counter (TC_ECC3)
0x11454 Reserved
4
TC Layer 4
4
0x11460 TC4 mode register (TCMODE4)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
12 bytes
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
—
—
4
0x11462 TC4 cell delineation state machine register (CDSMR4)
4
0x11464 TC4 event register (TCER4)
4
0x11466 TC4 received cells counter (TC_RCC4)
4
0x11468 TC4 mask register (TCMR4)
4
0x1146A TC4 filtered cells counter (TC_FCC4)
4
0x1146C TC4 corrected cells counter (TC_CCC4)
4
0x1146E TC4 idle cells counter (TC_ICC4)
4
0x11470 TC4 transmitted cells counter (TC_TCC4)
4
0x11472 TC4 error cells counter (TC_ECC4)
4
0x11474 Reserved
4
TC Layer 5
4
0x11480 TC5 mode register (TCMODE5)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
12 bytes
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
—
—
4
0x11482 TC5 cell delineation state machine register (CDSMR5)
4
0x11484 TC5 event register (TCER5)
4
0x11486 TC5 received cells counter (TC_RCC5)
4
0x11488 TC5 mask register (TCMR5)
4
0x1148A TC5 filtered cells counter (TC_FCC5)
4
0x1148C TC5 corrected cells counter (TC_CCC5)
4
0x1148E TC5 idle cells counter (TC_ICC5)
4
0x11490 TC5 transmitted cells counter (TC_TCC5)
4
0x11492 TC5 error cells counter (TC_ECC5)
0x11494 Reserved
4
TC Layer 6
4
0x114A0 TC6 mode register (TCMODE6)
R/W
16 bits
0x0000
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
3-14
Freescale Semiconductor
Memory Map
Table 3-1. Internal Memory Map (continued)
Address
(offset)
Register
R/W
Size
Reset
Section/Page
4
0x114A2 TC6 cell delineation state machine register (CDSMR6)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
12 bytes
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
—
—
4
0x114A4 TC6 event register (TCER6)
4
0x114A6 TC6 received cells counter (TC_RCC6)
4
0x114A8 TC6 mask register (TCMR6)
4
0x114AA TC6 filtered cells counter (TC_FCC6)
4
0x114AC TC6 corrected cells counter (TC_CCC6)
4
0x114AE TC6 idle cells counter (TC_ICC6)
4
0x114B0 TC6 transmitted cells counter (TC_TCC6)
4
0x114B2 TC6 error cells counter (TC_ECC6)
0x114B4 Reserved
4
TC Layer 7
4
0x114C0 TC7 mode register (TCMODE7)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
12 bytes
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
—
—
4
0x114C2 TC7 cell delineation state machine register (CDSMR7)
4
0x114C4 TC7 event register (TCER7)
4
0x114C6 TC7 received cells counter (TC_RCC7)
4
0x114C8 TC7 mask register (TCMR7)
4
0x114CA TC7 filtered cells counter (TC_FCC7)
4
0x114CC TC7 corrected cells counter (TC_CCC7)
4
0x114CE TC7 idle cells counter (TC_ICC7)
4
0x114D0 TC7 transmitted cells counter (TC_TCC7)
4
0x114D2 TC7 error cells counter (TC_ECC7)
0x114D4 Reserved
4
TC Layer 8
4
0x114E0 TC8 mode register (TCMODE8)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
4
0x114E2 TC8 cell delineation state machine register (CDSMR8)
4
0x114E4 TC8 event register (TCER8)
4
0x114E6 TC8 received cells counter (TC_RCC8)
4
0x114E8 TC8 mask register (TCMR8)
4
0x114EA TC8 filtered cells counter (TC_FCC8)
4
0x114EC TC8 corrected cells counter (TC_CCC8)
4
0x114EE TC8 idle cells counter (TC_ICC8)
4
0x114F0 TC8 transmitted cells counter (TC_TCC8)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
3-15
Memory Map
Table 3-1. Internal Memory Map (continued)
Address
(offset)
Register
R/W
Size
Reset
Section/Page
4
0x114F2 TC8 error cells counter (TC_ECC8)
0x114F4 Reserved
R/W
—
16 bits
0x0000
—
—
12 bytes
4
TC Layer—General
4
0x11500 TC general status register (TCGSR)
R
16 bits
16 bits
0x0000
0x0000
4
0x11502 TC general event register (TCGER)
R/W
BRGs 5–8
0x115F0 BRG5 configuration register (BRGC5)
0x115F4 BRG6 configuration register (BRGC6)
0x1115F8 BRG7 configuration register (BRGC7)
0x115FC BRG8 configuration register (BRGC8)
R/W
R/W
R/W
R/W
—
32 bits
32 bits
32 bits
32 bits
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
—
0x11600– Reserved
0x1185F
608
bytes
—
2
I C
2
0x11860 I C mode register (I2MOD)
R/W
—
8 bits
24 bits
8 bits
0x00
—
0x11861 Reserved
—
—
2
0x11864 I C address register (I2ADD)
R/W
—
0x00
—
0x11865 Reserved
24 bits
8 bits
2
0x11868 I C BRG register (I2BRG)
R/W
—
0x00
—
—
0x11869 Reserved
24 bits
8 bits
2
0x1186C I C command register (I2COM)
R/W
—
0x00
—
—
0x1186D Reserved
24 bits
8 bits
2
0x11870 I C event register (I2CER)
R/W
—
0x00
—
—
0x11871 Reserved
24 bits
8 bits
2
0x11874 I C mask register (I2CMR)
R/W
—
0x00
—
—
0x11875– Reserved
0x119BF
315
bytes
Communications Processor
0x119C0 Communications processor command register (CPCR)
R/W
R/W
—
32 bits
32 bits
0x0000_0000
0x0000_0000
—
—
0x119C4 CP configuration register (RCCR)
0x119C8– Reserved
0x119D5
14 bytes
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
3-16
Freescale Semiconductor
Memory Map
Table 3-1. Internal Memory Map (continued)
Address
(offset)
Register
R/W
Size
Reset
Section/Page
0x119D6 CP timers event register (RTER)
0x119DA CP timers mask register (RTMR)
0x119DC CP time-stamp timer control register (RTSCR)
0x119DE Reserved
R/W
R/W
—
16 bits
16 bits
16 bits
16 bits
32 bits
0x0000_0000
0x0000_0000
0x0000
R/W
R/W
—
0x119E0 CP time-stamp register (RTSR)
0x0000
BRGs 1–4
0x119F0 BRG1 configuration register (BRGC1)
0x119F4 BRG2 configuration register (BRGC2)
0x119F8 BRG3 configuration register (BRGC3)
0x119FC BRG4 configuration register (BRGC4)
R/W
R/W
R/W
R/W
32 bits
32 bits
32 bits
32 bits
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
SCC1
0x11A00 SCC1 general mode register (GSMR_L1)
0x11A04 SCC1 general mode register (GSMR_H1)
R/W
R/W
R/W
32 bits
32 bits
16 bits
0x0000_0000
0x0000_0000
0x0000
0x11A08 SCC1 protocol-specific mode register (PSMR1)
(UART)
(HDLC)
(BISYNC)
(Transparent)
(Ethernet)
0x11A0A Reserved
—
16 bits
16 bits
16 bits
16 bits
16 bits
—
—
0x11A0C SCC1 transmit-on-demand register (TODR1)
0x11A0E SCC1 data synchronization register (DSR1)
0x11A10 SCC1 event register (SCCE1)
0x11A14 SCC1 mask register (SCCM1)
R/W
R/W
R/W
R/W
0x0000
0x7E7E
0x0000
0x0000
(UART)
(HDLC)
(BISYNC)
(Transparent)
(Ethernet)
0x11A16 Reserved
—
8 bits
—
—
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
3-17
Memory Map
Table 3-1. Internal Memory Map (continued)
Address
(offset)
Register
R/W
Size
Reset
Section/Page
0x11A17 SCC1 status register (SCCS1)
R/W
8 bits
0x00
(UART)
(HDLC)
(BISYNC)
(Transparent)
0x11A18– Reserved
0x11A1F
—
8 bytes
—
—
SCC2
0x11A20 SCC2 general mode register (low) (GSMR_L2)
R/W
R/W
R/W
32 bits
32 bits
16 bits
0x0000_0000
0x0000_0000
0x0000
0x11A24 SCC2 general mode register (high) (GSMR_H2)
0x11A28 SCC2 protocol-specific mode register (PSMR2)
(UART)
(HDLC)
(BISYNC)
(Transparent)
(Ethernet)
0x11A2A Reserved
—
16 bits
16 bits
16 bits
16 bits
16 bits
—
—
0x11A2C SCC2 transmit-on-demand register (TODR2)
0x11A2E SCC2 data synchronization register (DSR2)
0x11A30 SCC2 event register (SCCE2)
0x11A34 SCC2 mask register (SCCM2)
R/W
R/W
R/W
R/W
0x0000
0x7E7E
0x0000
0x0000
(UART)
(HDLC)
(BISYNC)
(Transparent)
(Ethernet)
0x11A36 Reserved
—
8 bits
—
—
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
3-18
Freescale Semiconductor
Memory Map
Table 3-1. Internal Memory Map (continued)
Address
(offset)
Register
R/W
Size
Reset
Section/Page
0x11A37 SCC2 status register (SCCS2)
R/W
8 bits
0x00
(UART)
(HDLC)
(BISYNC)
(Transparent)
0x11A38– Reserved
0x11A3F
—
8 bytes
—
—
SCC3
0x11A40 SCC3 general mode register (GSMR_L3)
0x11A44 SCC3 general mode register (GSMR_H3)
R/W
R/W
R/W
32 bits
32 bits
16 bits
0x0000_0000
0x0000_0000
0x0000
0x11A48 SCC3 protocol-specific mode register (PSMR3)
(UART)
(HDLC)
(BISYNC)
(Transparent)
(Ethernet)
0x11A4A Reserved
—
16 bits
16 bits
16 bits
16 bits
16 bits
—
—
0x11A4C SCC3 transmit on demand register (TODR3)
0x11A4E SCC3 data synchronization register (DSR3)
0x11A50 SCC3 event register (SCCE3)
0x11A54 SCC3 mask register (SCCM3)
R/W
R/W
R/W
R/W
0x0000
0x7E7E
0x0000
0x0000
(UART)
(HDLC)
(BISYNC)
(Transparent)
(Ethernet)
0x11A56 Reserved
—
8 bits
—
—
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
3-19
Memory Map
Table 3-1. Internal Memory Map (continued)
Address
(offset)
Register
R/W
Size
Reset
Section/Page
0x11A57 SCC3 status register (SCCS3)
R/W
8 bits
0x00
(UART)
(HDLC)
(BISYNC)
(Transparent)
0x11A58– Reserved
0x11A5F
—
8 bytes
—
—
SCC4
0x11A60 SCC4 general mode register (GSMR_L4)
0x11A64 SCC4 general mode register (GSMR_H4)
R/W
R/W
R/W
32 bits
32 bits
16 bits
0x0000_0000
0x0000_0000
0x0000
0x11A68 SCC4 protocol-specific mode register (PSMR4)
(UART)
(HDLC)
(BISYNC)
(Transparent)
(Ethernet)
0x11A6A Reserved
—
16 bits
16 bits
16 bits
16 bits
16 bits
—
—
0x11A6C SCC4 transmit on-demand register (TODR4)
0x11A6E SCC4 data synchronization register (DSR4)
0x11A70 SCC4 event register (SCCE4)
0x11A74 SCC4 mask register (SCCM4)
R/W
R/W
R/W
R/W
0x0000
0x7E7E
0x0000
0x0000
(UART)
(HDLC)
(BISYNC)
(Transparent)
(Ethernet)
0x11A77 SCC4 status register (SCCS4)
—
8 bits
0x00
(UART)
(HDLC)
(BISYNC)
(Transparent)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
3-20
Freescale Semiconductor
Memory Map
Table 3-1. Internal Memory Map (continued)
Address
(offset)
Register
R/W
Size
Reset
Section/Page
0x11A78– Reserved
0x11A7F
—
8 bytes
—
—
SMC1
SMC2
SPI
0x11A82 SMC1 mode register (SMCMR1)
0x11A84 Reserved
R/W
—
16 bits
16 bits
8 bits
0x0000
—
—
0x11A86 SMC1 event register (SMCE1)
0x11A87 Reserved
R/W
—
0x00
—
(UART)
(Transparent)
(GCI)
24 bits
8 bits
0x11A8A SMC1 mask register (SMCM1)
R/W
0x00
0x11A8B– Reserved
0x11A91
—
7 bytes
—
—
0x11A92 SMC2 mode register (SMCMR2)
0x11A94 Reserved
R/W
—
16 bits
16 bits
8 bits
0x0000
—
—
0x11A96 SMC2 event register (SMCE2)
0x11A97 Reserved
R/W
—
0x00
—
(UART)
(Transparent)
(GCI)
24 bits
8 bits
0x11A9A SMC2 mask register (SMCM2)
R/W
0x00
0x11A9B– Reserved
0x11A9F
—
5 bytes
—
—
0x11AA0 SPI mode register (SPMODE)
0x11AA2 Reserved
R/W
—
16 bits
4 bytes
8 bits
0x0000
—
—
—
0x11AA6 SPI event register (SPIE)
0x11AA7 Reserved
R/W
—
0x00
—
24 bits
8 bits
0x11AAA SPI mask register (SPIM)
0x11AAB Reserved
R/W
—
0x00
—
—
24 bits
8 bits
0x11AAD SPI command register (SPCOM)
W
0x00
—
—
0x11AAE– Reserved
0x11AFF
—
82 bytes
CPM Mux
0x11B00 CPM mux SI1 clock route register (CMXSI1CR)
0x11B02 CPM mux SI2 clock route register (CMXSI2CR)
R/W
R/W
8 bits
8 bits
0x00
0x00
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
3-21
Memory Map
Table 3-1. Internal Memory Map (continued)
Address
(offset)
Register
R/W
Size
Reset
Section/Page
0x11B03 Reserved
—
R/W
R/W
R/W
—
8 bits
32 bits
32 bits
8 bits
—
0x0000_0000
0x0000_0000
0x00
—
0x11B04 CPM mux FCC clock route register (CMXFCR)
0x11B08 CPM mux SCC clock route register (CMXSCR)
0x11B0C CPM mux SMC clock route register (CMXSMR)
0x11B0D Reserved
—
8 bits
—
5
0x11B0E CPM mux UTOPIA address register (CMXUAR)
R/W
—
16 bits
16 bytes
0x0000
—
—
0x11B10– Reserved
0x11B1F
SI1 Registers
0x11B20 SI1 TDMA1 mode register (SI1AMR)
0x11B22 SI1 TDMB1 mode register (SI1BMR)
0x11B24 SI1 TDMC1 mode register (SI1CMR)
0x11B26 SI1 TDMD1 mode register (SI1DMR)
0x11B28 SI1 global mode register (SI1GMR)
0x11B29 Reserved
R/W
R/W
R/W
R/W
R/W
—
16 bits
16 bits
16 bits
16 bits
8 bits
0x0000
0x0000
0x0000
0x0000
0x00
—
—
8 bits
0x11B2A SI1 command register (SI1CMDR)
0x11B2B Reserved
R/W
—
8 bits
0x00
—
—
8 bits
0x11B2C SI1 status register (SI1STR)
0x11B2D Reserved
R/W
—
8 bits
0x00
—
—
8 bits
0x11B2E SI1 RAM shadow address register (SI1RSR)
MCC1 Registers
R/W
16 bits
0x0000
6
6
0x11B30 MCC1 event register (MCCE1)
0x11B32 Reserved
R/W
—
16 bits
16 bits
16 bits
16 bits
8 bits
0x0000
—
6
0x11B34 MCC1 mask register (MCCM1)
0x11B36 Reserved
R/W
—
0x0000
—
—
—
6
0x11B38 MCC1 configuration register (MCCF1)
R/W
—
0x00
—
0x11B39– Reserved
0x11B3F
7 bytes
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
3-22
Freescale Semiconductor
Memory Map
Table 3-1. Internal Memory Map (continued)
Address
(offset)
Register
R/W
Size
Reset
Section/Page
SI2 Registers
0x11B40 SI2 TDMA2 mode register (SI2AMR)
0x11B42 SI2 TDMB2 mode register (SI2BMR)
0x11B44 SI2 TDMC2 mode register (SI2CMR)
0x11B46 SI2 TDMD2 mode register (SI2DMR)
0x11B48 SI2 global mode register (SI2GMR)
0x11B49 Reserved
R/W
R/W
R/W
R/W
R/W
—
16 bits
16 bits
16 bits
8 bits
0x0000
0x0000
0x0000
0x0000
0x00
—
8 bits
—
8 bits
0x11B4A SI2 command register (SI2CMDR)
0x11B4B Reserved
R/W
—
8 bits
0x00
—
—
8 bits
0x11B4C SI2 status register (SI2STR)
0x11B4D Reserved
R/W
—
8 bits
0x00
—
—
16 bits
16 bits
0x11B4E SI2 RAM shadow address register (SI2RSR)
MCC2 Registers
R/W
0x0000
0x11B50 MCC2 event register (MCCE2)
0x11B52 Reserved
R/W
—
16 bits
16 bits
16 bits
16 bits
8 bits
0x0000
—
—
—
0x11B54 MCC2 mask register (MCCM2)
0x11B56 Reserved
R/W
—
0x0000
—
0x11B58 MCC2 configuration register (MCCF2)
R/W
—
0x00
—
—
0x11B59– Reserved
0x11FFF
1,159
bytes
SI1 RAM
0x12000– SI 1 transmit routing RAM (SI1TxRAM)
0x121FF
R/W
—
512
bytes
undefined
—
0x12200– Reserved
0x123FF
512
bytes
—
—
0x12400– SI 1 receive routing RAM (SI1RxRAM)
0x125FF
R/W
—
512
bytes
undefined
—
0x12600– Reserved
0x127FF
512
bytes
SI2 RAM
0x12800– SI 2 transmit routing RAM (SI2TxRAM)
0x129FF
R/W
—
512
bytes
undefined
—
—
0x12A00– Reserved
0x12BFF
512
bytes
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
3-23
Memory Map
Table 3-1. Internal Memory Map (continued)
Address
(offset)
Register
R/W
Size
Reset
Section/Page
0x12C00– SI 2 receive routing RAM (SI2RxRAM)
0x12DFF
R/W
512
bytes
undefined
0x12E00– Reserved
0x12FFF
—
—
—
512
bytes
—
—
—
—
—
—
0x13000– Reserved
0x137FF
2048
bytes
0x13800– Reserved
0x13FFF
2048
bytes
1
2
3
4
5
6
.25 µm (HiP4) devices only. Reserved on.29 µm (HiP3) devices.
MPC8250, MPC8265, and MPC8266 only. Reserved on all other devices.
Reserved on the MPC8255.
MPC8264 and MPC8266 only. Reserved on all other devices.
Reserved on the MPC8250.
Reserved on the MPC8250 and the MPC8255.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
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Freescale Semiconductor
Part II
Configuration and Reset
Intended Audience
Part II is intended for system designers and programmers who need to understand the operation of the
PowerQUICC II at start up. It assumes understanding of the PowerPC programming model described in
the previous chapters and a high level understanding of the PowerQUICC II.
Contents
Part II describes start-up behavior of the PowerQUICC II.
It contains the following chapters:
•
functions which provide various monitors and timers, and the 60x bus configuration.
•
Suggested Reading
Supporting documentation for the PowerQUICC II can be accessed through the world-wide web at
www.freescale.com. This documentation includes technical specifications, reference materials, and
detailed applications notes.
Conventions
This chapter uses the following notational conventions:
Bold entries in figures and tables showing registers and parameter RAM should
be initialized by the user.
Bold
mnemonics
Instruction mnemonics are shown in lowercase bold.
Italics indicate variable command parameters, for example, bcctrx.
Book titles in text are set in italics.
italics
0x0
Prefix to denote hexadecimal number
0b0
Prefix to denote binary number
rA, rB
rD
Instruction syntax used to identify a source GPR
Instruction syntax used to identify a destination GPR
REG[FIELD]
Abbreviations or acronyms for registers or buffer descriptors are shown in
uppercase text. Specific bits, fields, or numerical ranges appear in brackets. For
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
II-1
example, MSR[LE] refers to the little-endian mode enable bit in the machine state
register.
x
In certain contexts, such as in a signal encoding or a bit field, indicates a don’t
care.
n
Indicates an undefined numerical value
Acronyms and Abbreviations
Table i contains acronyms and abbreviations that are used in this document. Note that the meanings for
some acronyms (such as SDR1 and DSISR) are historical, and the words for which an acronym stands may
not be intuitively obvious.
Table II-1. Acronyms and Abbreviated Terms
Term
BIST
Meaning
Built-in self test
DMA
DRAM
EA
Direct memory access
Dynamic random access memory
Effective address
GPR
IEEE
LSB
lsb
General-purpose register
Institute of Electrical and Electronics Engineers
Least-significant byte
Least-significant bit
LSU
MSB
msb
MSR
PCI
Load/store unit
Most-significant byte
Most-significant bit
Machine state register
Peripheral component interconnect
Real-time operating system
Receive
RTOS
Rx
SPR
SWT
Tx
Special-purpose register
Software watchdog timer
Transmit
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Freescale Semiconductor
Chapter 4
System Interface Unit (SIU)
The system interface unit (SIU) consists of several functions that control system start-up and initialization,
as well as operation, protection, and the external system bus. Key features of the SIU include the
following:
•
•
•
•
•
•
•
•
•
System configuration and protection
System reset monitoring and generation
Clock synthesizer
Power management
60x bus interface
Flexible, high-performance memory controller
Level-two cache controller interface
PCI interface (MPC8250, MPC8265, and MPC8266 only)
IEEE 1149.1 test-access port (TAP)
Figure 4-1 is a block diagram of the SIU.
60x Bus (32-Bit Address/64-Bit Data)
Core
Configuration Registers
Memory
Controller
Core
Control
Control
Counters
Bridge
Memory
Controller
Local
Interrupt
Controller
Communications
Processor
Local Bus (18-Bit Address/32-Bit Data)
Figure 4-1. SIU Block Diagram
The system configuration and protection functions provide various monitors and timers, including the bus
monitor, software watchdog timer, periodic interrupt timer, and time counter. The clock synthesizer
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
4-1
System Interface Unit (SIU)
generates the clock signals used by the SIU and other PowerQUICC II modules. The SIU clocking scheme
supports stop and normal modes.
The 60x bus interface is a standard pipelined bus. The PowerQUICC II allows external bus masters to
request and obtain system bus mastership. Chapter 8, “The 60x Bus,” describes bus operation, but 60x bus
configuration is explained in this section.
interface to many types of memory devices and peripherals. It supports up to twelve memory banks, each
with its own device and timing attributes. The PCI interface enables the use of standard peripherals.
The PowerQUICC II’s implementation supports circuit board test strategies through a user- accessible test
logic that is fully compliant with the IEEE 1149.1 test access port.
4.1
System Configuration and Protection
The PowerQUICC II incorporates many system functions that normally must be provided in external
circuits. In addition, it is designed to provide maximum system safeguards against hardware and/or
submodule.
Table 4-1. System Configuration and Protection Functions
Function
Description
System
The SIU allows the user to configure the system according to the particular requirements. The functions
configuration include control of parity checking and part and mask number constants.
60x bus
monitor
Monitors the transfer acknowledge (TA) and address acknowledge (AACK) response time for all bus
accesses initiated by internal or external masters. TEA is asserted if the TA/AACK response limit is
exceeded. This function can be disabled if needed.
Local bus
monitor
Monitors transfers between local bus internal masters and local bus slaves. An internal TEA assertion
occurs if the transfer time limit is exceeded. This function can be disabled.
Software
watchdog
timer
Asserts a reset or NMI interrupt, selected by the system protection control register (SYPCR) if the
software fails to service the software watchdog timer for a certain period of time (for example, because
software is lost or trapped in a loop). After a system reset, this function is enabled, selects a maximum
time-out period, and asserts a system reset if the time-out is reached. The software watchdog timer can
be disabled or its time-out period may be changed in the SYPCR. Once the SYPCR is written, it cannot
be written again until a system reset. For more information, see Section 4.1.5, “Software Watchdog
Timer.”
Periodic
interrupt
timer (PIT)
Generates periodic interrupts for use with a real-time operating system or the application software. The
periodic interrupt timer (PIT) is clocked by the timersclk clock, providing a period from 122 µs to
8 seconds. The PIT function can be disabled if needed. See Section 4.1.4, “Periodic Interrupt Timer
(PIT).”
Time
counter
Provides a time-of-day information to the operating system/application software. It is composed of a
45-bit counter and an alarm register. A maskable interrupt is generated when the counter reaches the
value programmed in the alarm register. The time counter (TMCNT) is clocked by the timersclk clock.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
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Freescale Semiconductor
System Interface Unit (SIU)
Figure 4-2 is a block diagram of the system configuration and protection logic.
Module
Configuration
System Reset
Bus
Monitors
Bus clock/8
timersclk
Core’s MCP
TEA
Periodic Interrupt
Timer
Interrupt
System Reset
Core’s MCP
Software
Watchdog Timer
Bus Clock
timersclk
Time
Counter
Interrupt
Figure 4-2. System Configuration and Protection Logic
Many aspects of system configuration are controlled by several SIU module configuration registers,
4.1.1
Bus Monitor
The PowerQUICC II has two bus monitors, one for the 60x bus and one for the local bus. The bus monitor
ensures that each bus cycle is terminated within a reasonable period. The bus monitor does not count when
the bus is idle. When a transaction starts (TS asserted), the bus monitor starts counting down from the
time-out value. For standard bus transactions with an address tenure and a data tenure, the bus monitor
counts until a data beat is acknowledged on the bus. It then reloads the time-out value and resumes the
count down. This process continues until the whole data tenure is completed. Following the data tenure
the bus monitor will idle in case there is no pending transaction; otherwise it will reload the time-out value
and resume counting.
For address-only transactions, the bus monitor counts until AACK is asserted. If the monitor times out for
a standard bus transaction, transfer error acknowledge (TEA) is asserted. If the monitor times out for an
address-only transaction, the bus monitor asserts AACK and a core machine check or reset interrupt is
generated, depending on SYPCR[SWRI]. To allow variation in system peripheral response times,
SYPCR[BMT] defines the time-out period, whose maximum value can be 2,040 system bus clocks. The
timing mechanism is clocked by the system bus clock divided by eight.
4.1.2
Timers Clock
The two SIU timers (the time counter and the periodic interrupt timer) use the same clock source,
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
4-3
System Interface Unit (SIU)
The user should select external clock and/or BRG1 programming
to yield either 4 MHz or 32 KHz at this point.
PISCR[PTF]
PC[26]
Divide by 4
timersclk for PIT
Divide by 512
Ports Programming
CPM clock
timersclk for TMCNT
PC[27]
BRG1
PC[29]
TMCNTSC[TCF]
Ports Programming
PC[25]
Figure 4-3. Timers Clock Generation
operation, the user must ensure that the frequency of timersclk for TMCNT is 8,192 Hz by properly
selecting the external clock and programming BRG1 and the prescaler control bits in the time counter
status and control register (TMCNTSC[TCF]) and periodic interrupt status and control register
(PISCR[PTF]).
4.1.3
Time Counter (TMCNT)
The time counter (TMCNT) is a 32-bit counter that is clocked by timersclk. It provides a time-of-day
indication to the operating system and application software. The counter is reset to zero on PORESET reset
or hard reset but is not effected by soft reset. It is initialized by the software; the user should set the
TMCNT can be programmed to generate a maskable interrupt when the time value matches the value in
its associated alarm register. It can also be programmed to generate an interrupt every second. The time
counter control and status register (TMCNTSC) is used to enable or disable the various timer functions
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
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Freescale Semiconductor
System Interface Unit (SIU)
SEC
Interrupt
timersclk for TMCNT (8,192 Hz)
Divide
by 8,192
32-Bit Counter
Alarm
Interrupt
=
32-Bit Register
Figure 4-4. TMCNT Block Diagram
4.1.4
Periodic Interrupt Timer (PIT)
The periodic interrupt timer consists of a 16-bit counter clocked by timersclk. The 16-bit counter
decrements to zero when loaded with a value from the periodic interrupt timer count register (PITC); after
the timer reaches zero, PISCR[PS] is set and an interrupt is generated if PISCR[PIE] = 1. At the next input
clock edge, the value in the PITC is loaded into the counter and the process repeats. When a new value is
loaded into the PITC, the PIT is updated, the divider is reset, and the counter begins counting.
Setting PS creates a pending interrupt that remains pending until PS is cleared. If PS is set again before
being cleared, the interrupt remains pending until PS is cleared. Any write to the PITC stops the current
countdown and the count resumes with the new value in PITC. If PTE = 0, the PIT cannot count and retains
PISCR[PTE]
PITC
timersclk
for PIT
Clock
Disable
16-Bit Modulus
Counter
PISCR[PS]
PISCR[PIE]
PIT
Interrupt
Figure 4-5. PIT Block Diagram
The time-out period is calculated as follows:
PITC + 1
PITC + 1
8192
PIT
= ----------------------------------- = ------------------------
period
F
timersclk
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Freescale Semiconductor
4-5
System Interface Unit (SIU)
This gives a range from 122 µs (PITC = 0x0000) to 8 seconds (PITC = 0xFFFF).
4.1.5
Software Watchdog Timer
The SIU provides the software watchdog timer option to prevent system lock in case the software becomes
trapped in loops with no controlled exit. Watchdog timer operations are configured in the SYPCR,
The software watchdog timer is enabled after reset to cause a hard reset if it times out. If the software
watchdog timer is not needed, the user must clear SYPCR[SWE] to disable it. If used, the software
watchdog timer requires a special service sequence to be executed periodically. Without this periodic
servicing, the software watchdog timer times out and issues a reset or a nonmaskable interrupt,
programmed in SYPCR[SWRI]. Once software writes SWRI, the state of SWE cannot be changed.
The software watchdog timer service sequence consists of the following two steps:
1. Write 0x556C to the software service register (SWSR)
2. Write 0xAA39 to SWSR
The service sequence clears the watchdog timer and the timing process begins again. If a value other than
0x556C or 0xAA39 is written to the SWSR, the entire sequence must start over. Although the writes must
occur in the correct order before a time-out, any number of instructions can be executed between the
writes. This allows interrupts and exceptions to occur between the two writes when necessary. Figure 4-6
shows a state diagram for the watchdog timer.
Reset
0x556C/Don’t reload
State 0
State 1
Waiting for 0xAA39
Waiting for 0x556C
0xAA39/Reload
Not 0x556C/Don’t reload
Not 0xAA39/Don’t reload
Figure 4-6. Software Watchdog Timer Service State Diagram
Although most software disciplines permit or even encourage the watchdog concept, some systems require
a selection of time-out periods. For this reason, the software watchdog timer must provide a selectable
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
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Freescale Semiconductor
System Interface Unit (SIU)
SWSR
Service
Logic
SYPCR[SWTC]
SWE
Clock
Disable
Bus
Clock
Divide By
2,048
Reload
16-Bit
MUX
SWP
SWR/Decrementer
Rollover = 0
Reset
or MCP
Time-out
Figure 4-7. Software Watchdog Timer Block Diagram
In Figure 4-7, the range is determined by SYPCR[SWTC]. The value in SWTC is then loaded into a 16-bit
decrementer clocked by the system clock. An additional divide-by-2,048 prescaler is used when needed.
The decrementer begins counting when loaded with a value from SWTC. After the timer reaches 0x0, a
software watchdog expiration request is issued to the reset or MCP control logic. Upon reset, SWTC is set
to the maximum value and is again loaded into the software watchdog register (SWR), starting the process
over. When a new value is loaded into SWTC, the software watchdog timer is not updated until the
servicing sequence is written to the SWSR. If SYPCR[SWE] is loaded with 0, the modulus counter does
not count.
4.2
Interrupt Controller
Key features of the interrupt controller include the following:
•
Communications processor module (CPM) interrupt sources (FCCs, SCCs, MCCs, timers, SMCs,
TC layers, I C, IDMA, SDMA, and SPI)
2
•
•
•
SIU interrupt sources (PIT, TMCNT, and PCI (MPC8250, MPC8265, and MPC8266 only))
24 external sources (16 port C and 8 IRQ)
Programmable priority between PIT, TMCNT, and PCI (MPC8250, MPC8265, and MPC8266
only)
•
•
•
•
Programmable priority between SCCs, FCCs, and MCCs
Two priority schemes for the SCCs: grouped, spread
Programmable highest priority request
Unique vector number for each interrupt source
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
4-7
System Interface Unit (SIU)
4.2.1
Interrupt Configuration
Figure 4-8 shows the PowerQUICC II interrupt structure. The interrupt controller receives interrupts from
internal sources, such as the PIT or TMCNT, from the CPM, the PCI bridge (with its own interrupt
controller), and from external pins (port C parallel I/O pins).
Software watchdog timer
Memory controller data errors
1
PCI
OR
Bus monitor address only
IRQ0
IRQ[0–7]
Fall/
Level
8
MCP
IRQ[1–7]
1
PCI
G2
Core
TMCNT
PIT
Port C[0–15]
Edge/
Fall
16
Timer1
Timer2
Timer3
Timer4
FCC1
INT
FCC2
FCC3
2
MCC1
MCC2
SCC1
SCC2
SCC3
SCC4
SMC1
SMC2
SPI
I2C
IDMA1
IDMA2
IDMA3
IDMA4
SDMA
Notes
1
MPC8250, MPC8265, and MPC8266 only
Not on MPC8250 and MPC8255
MPC8264 and MPC8266 only
2
3
RISC Timers
3
TC layers
Figure 4-8. PowerQUICC II Interrupt Structure
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
4-8
Freescale Semiconductor
System Interface Unit (SIU)
If the software watchdog timer is programmed to generate an interrupt, it always generates a machine
check interrupt to the core. The external IRQ0 can generate MCP as well. Note that the core takes the
machine check interrupt when MCP is asserted; it takes an external interrupt for any other interrupt
asserted by the interrupt controller.
The interrupt controller allows masking of each interrupt source. Multiple events within a CPM sub-block
event are also maskable.
All interrupt sources are prioritized and bits are set in the interrupt pending register (SIPNR). On the
PowerQUICC II, the prioritization of the interrupt sources is flexible in the following two aspects:
•
•
The relative priority of the FCCs, SCCs, and MCCs can be modified
One interrupt source can be assigned the highest priority
When an unmasked interrupt source is pending in the SIPNR, the interrupt controller sends an interrupt
request to the core. When an exception is taken, the interrupt mask bit in the machine state register
(MSR[EE]) is cleared to disable further interrupt requests until software can handle them.
The SIU interrupt vector register (SIVEC) is updated with a 6-bit vector corresponding to the sub-block
with the highest current priority.
4.2.1.1
Machine Check Interrupt
There are several sources for a machine check interrupt (MCP):
•
Software watchdog timer (when programmed to generate an interrupt—See Section 4.1.5,
•
•
IRQ0 signal (when the internal core is enabled)
Memory controller for parity/ECC errors (see Section 10.2.6, “Machine Check Interrupt (MCP)
Generation”)
•
•
PCI bridge (MPC8265 and MPC8266 only)
Bus monitor time out (on an address only transaction—see Section 4.1.1, “Bus Monitor”)
When the internal core is enabled, these sources cause the interrupt controller to send a MCP to the core.
When the core is disabled the MCP assertion is reflected on IRQ0/NMI_OUT so that an external core can
serve it.
4.2.1.2
INT Interrupt
Besides the MCP sources listed above, all other interrupts are taken by the core through the INT interrupt.
If the internal core is disabled, INT is reflected on IRQ7/INT_OUT so that an external core can serve it.
The interrupt controller allows masking of each interrupt source. Multiple events within a CPM sub-block
event are also maskable.
4.2.2
Interrupt Source Priorities
The interrupt controller has 37 interrupt sources that assert one interrupt request to the core. Table 4-2
shows prioritization of all interrupt sources. As described in following sections, flexibility exists in the
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
4-9
System Interface Unit (SIU)
relative ordering of the interrupts, but, in general, relative priorities are as shown. A single interrupt
priority number is associated with each table entry.
Table 4-2. Interrupt Source Priority Levels
Priority Level
Interrupt Source Description
Multiple Events
1
Highest
XSIU1
—
1
2
No (TMCNT,PIT,PCI = Yes)
1
3
XSIU2 (Grouped)
XSIU3 (Grouped)
XSIU4 (Grouped)
XCC1
No (TMCNT,PIT,PCI = Yes)
1
4
No (TMCNT,PIT,PCI = Yes)
1
5
No (TMCNT,PIT,PCI = Yes)
6
Yes
Yes
Yes
Yes
7
XCC2
8
XCC3
9
XCC4
1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
XSIU2 (Spread)
XCC5
No (TMCNT,PIT,PCI = Yes)
Yes
Yes
Yes
Yes
XCC6
XCC7
XCC8
1
XSIU5 (Grouped)
XSIU6 (Grouped)
XSIU7 (Grouped)
XSIU8 (Grouped)
XSIU3 (Spread)
YCC1 (Grouped)
YCC2 (Grouped)
YCC3 (Grouped)
YCC4 (Grouped)
YCC5 (Grouped)
YCC6 (Grouped)
YCC7 (Grouped)
No (TMCNT,PIT,PCI = Yes)
1
No (TMCNT,PIT,PCI = Yes)
1
No (TMCNT,PIT,PCI = Yes)
1
No (TMCNT,PIT,PCI = Yes)
1
No (TMCNT,PIT,PCI = Yes)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
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Freescale Semiconductor
System Interface Unit (SIU)
Table 4-2. Interrupt Source Priority Levels (continued)
Priority Level
Interrupt Source Description
Multiple Events
Yes
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
YCC8 (Grouped)
XSIU4 (Spread)
Parallel I/O–PC15
Timer 1
1
No (TMCNT,PIT,PCI = Yes)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Parallel I/O–PC14
YCC1 (Spread)
Parallel I/O–PC13
SDMA Bus Error
IDMA1
YCC2 (Spread)
Parallel I/O–PC12
Parallel I/O–PC11
IDMA2
No
Yes
Yes
No
Timer 2
Parallel I/O–PC10
XSIU5 (GSIU = 1)
YCC3 (Spread)
RISC Timer Table
I2C
1
No (TMCNT,PIT,PCI = Yes)
Yes
Yes
Yes
Yes
No
YCC4 (Spread)
Parallel I/O–PC9
Parallel I/O–PC8
IRQ6
No
No
IDMA3
Yes
No
IRQ7
Timer 3
Yes
1
XSIU6 (GSIU = 1)
YCC5 (Spread)
Parallel I/O–PC7
Parallel I/O–PC6
Parallel I/O–PC5
Timer 4
No (TMCNT,PIT,PCI = Yes)
Yes
No
No
No
Yes
Yes
YCC6 (Spread)
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4-11
System Interface Unit (SIU)
Table 4-2. Interrupt Source Priority Levels (continued)
Priority Level
Interrupt Source Description
Multiple Events
No
60
61
62
63
64
65
66
67
68
69
70
71
72
73
Parallel I/O–PC4
XSIU7 (GSIU = 1)
IDMA4
1
No (TMCNT,PIT,PCI = Yes)
Yes
Yes
No
SPI
Parallel I/O–PC3
Parallel I/O–PC2
SMC1
No
Yes
Yes
Yes
No
YCC7 (spread)
SMC2
Parallel I/O–PC1
Parallel I/O–PC0
XSIU8 (GSIU = 1)
YCC8(spread)
Reserved
No
1
No (TMCNT,PIT,PCI = Yes)
Yes
—
1
MPC8250, MPC8265, and MPC8266 only
Notice the lack of SDMA interrupt sources, which are reported through each individual FCC, SCC, SMC,
2
SPI, or I C channel. The only true SDMA interrupt source is the SDMA channel bus error entry that is
reported when a bus error occurs during an SDMA access. There are two ways to add flexibility to the table
of CPM interrupt priorities—the FCC, MCC, and SCC relative priority option, described in
Section 4.2.2.1, “SCC, FCC, and MCC Relative Priority,” and the highest priority option, described in
4.2.2.1
SCC, FCC, and MCC Relative Priority
The relative priority between the four SCCs, three FCCs, and MCC is programmable and can be changed
are entries for XCC1–XCC8 and YCC1–YCC8. Each SCC can be mapped to any YCC location and each
FCC and MCC can be mapped to any XCC location. The SCC, FCC, and MCC priorities are programmed
in the CPM interrupt priority registers (SCPRR_H and SCPRR_L) and can be changed dynamically to
implement a rotating priority.
In addition, the grouping of the locations of the YCC entries has the following two options
•
Group. In the group scheme, all SCCs are grouped together at the top of the priority table, ahead
of most other CPM interrupt sources. This scheme is ideal for applications where all SCCs, FCCs,
and MCCs function at a very high data rate and interrupt latency is very important.
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System Interface Unit (SIU)
•
Spread. In the spread scheme, priorities are spread over the table so other sources can have lower
interrupt latencies. This scheme is also programmed in the SICR but cannot be changed
dynamically.
4.2.2.2
PIT, TMCNT, PCI, and IRQ Relative Priority
The PowerQUICC II has seven general-purpose interrupt requests (IRQs), five of which, with the PIT, the
PCI interrupt controller, and TMCNT, can be mapped to any XSIU location. IRQ6 and IRQ7 have fixed
priority.
4.2.2.3
Highest Priority Interrupt
In addition to the FCC/MCC/SCC relative priority option, SICR[HP] can be used to specify one interrupt
source as having highest priority. This interrupt remains within the same interrupt level as the other
interrupt controller interrupts, but is serviced before any other interrupt in the table.
If the highest priority feature is not used, select the interrupt request in XSIU1 to be the highest priority
interrupt; the standard interrupt priority order is used. SICR[HP] can be updated dynamically to allow the
user to change a normally low priority source into a high priority-source for a certain period.
4.2.3
Masking Interrupt Sources
By programming the SIU mask registers, SIMR_H and SIMR_L, the user can mask interrupt requests to
the core. Each SIMR bit corresponds to an interrupt source. To enable an interrupt, set the corresponding
SIMR bit. When a masked interrupt source has a pending interrupt request, the corresponding SIPNR bit
is set, even though the interrupt is not generated to the core. The user can mask all interrupt sources to
implement a polling interrupt servicing scheme.
When an interrupt source has multiple interrupting events, the user can individually mask these events by
programming a mask register within that block. Table 4-2 shows which interrupt sources have multiple
interrupting events. Figure 4-9 shows an example of how the masking occurs, using an SCC as an example.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
4-13
System Interface Unit (SIU)
SCCE
SIPNR
Event
Bit
13 Input (or
13 Event Bits)
Request to
the core
(Other Unmasked Requests)
SCCM
SIMR
Mask
Bit
Mask
Bit
Figure 4-9. Interrupt Request Masking
4.2.4
Interrupt Vector Generation and Calculation
Pending unmasked interrupts are presented to the core in order of priority. The interrupt vector that allows
the core to locate the interrupt service routine is made available to the core by reading SIVEC. The
interrupt controller passes an interrupt vector corresponding to the highest-priority, unmasked, pending
Table 4-3. Encoding the Interrupt Vector
Interrupt Number
Interrupt Source Description
Interrupt Vector
0
1
2
3
4
5
Error (No interrupt)
0b00_0000
0b00_0001
0b00_0010
0b00_0011
0b00_0100
0b00_0101
2
I C
SPI
RISC Timers
SMC1
SMC2
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
4-14
Freescale Semiconductor
System Interface Unit (SIU)
Table 4-3. Encoding the Interrupt Vector (continued)
Interrupt Number
Interrupt Source Description
Interrupt Vector
6
7
IDMA1
IDMA2
IDMA3
IDMA4
SDMA
Reserved
Timer1
Timer2
Timer3
Timer4
TMCNT
PIT
0b00_0110
0b00_0111
0b00_1000
0b00_1001
0b00_1010
0b00_1011
0b00_1100
0b00_1101
0b00_1110
0b00_1111
0b01_0000
0b01_0001
0b01_0010
0b01_0011
0b01_0100
0b01_0101
0b01_0110
0b01_0111
0b01_1000
0b01_1001
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26–31
32
33
34
35
36
37
38
39
40
41
42
43
1
PCI
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
Reserved
FCC1
FCC2
FCC3
Reserved
0b01_1010–01_1111
0b10_0000
0b10_0001
0b10_0010
0b10_0011
0b10_0100
0b10_0101
0b10_0110
0b10_0111
0b10_1000
0b10_1001
0b10_1010
0b10_1011
2
MCC1
MCC2
Reserved
Reserved
SCC1
SCC2
SCC3
SCC4
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
4-15
System Interface Unit (SIU)
Table 4-3. Encoding the Interrupt Vector (continued)
Interrupt Number
Interrupt Source Description
Interrupt Vector
3
44
45–47
48
TC Layer
0b10_1100
0b10_11xx
0b11_0000
0b11_0001
0b11_0010
0b11_0011
0b11_0100
0b11_0101
0b11_0110
0b11_0111
0b11_1000
0b11_1001
0b11_1010
0b11_1011
0b11_1100
0b11_1101
0b11_1110
0b11_1111
Reserved
PC15
PC14
PC13
PC12
PC11
PC10
PC9
49
50
51
52
53
54
55
PC8
56
PC7
57
PC6
58
PC5
59
PC4
60
PC3
61
PC2
62
PC1
63
PC0
1
On MPC8250, MPC8265, and MPC8266 only. Reserved on all other devices.
Reserved on MPC8250 and MPC8255.
2
3
On MPC8264 and MPC8266 only. Reserved on all other devices.
Note that the interrupt vector table differs from the interrupt priority table in only two ways:
•
FCC, SCC, and MCC vectors are fixed; they are not affected by the SCC group mode, spread mode,
or the relative priority order of the FCCs, SCCs, and MCC.
•
An error vector exists as the last entry in Table 4-3. The error vector is issued when no interrupt is
requesting service.
4.2.4.1
Port C External Interrupts
There are 16 external interrupts, coming from the parallel I/O port C pins, PC[0–15]. When ones of these
pins is configured as an input, a change according to the SIU external interrupt control register (SIEXR)
causes an interrupt request signal to be sent to the interrupt controller. PC[0–15] lines can be programmed
to assert an interrupt request upon any change. Each port C line asserts a unique interrupt request to the
interrupt pending register and has a different internal interrupt priority level within the interrupt controller.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
4-16
Freescale Semiconductor
System Interface Unit (SIU)
Requests can be masked independently in the interrupt mask register (SIMR). Notice that the global SIMR
is cleared on system reset so pins left floating do not cause false interrupts.
4.3
Programming Model
The SIU registers are grouped into the following three categories:
•
Interrupt controller registers. These registers control configuration, prioritization, and masking of
interrupts. They also include registers for determining the interrupt sources. These registers are
•
System configuration and protection registers. These include registers for configuring the SIU,
defining the base address for the internal memory map, configuring the watchdog timer, specifying
bus characteristics, as well as general functionality of the 60x, and local buses such as arbitration,
error status, and control. These registers are described in Section 4.3.2, “System Configuration and
•
Periodic interrupt registers. These include registers for configuring and providing status for
4.3.1
Interrupt Controller Registers
There are seven interrupt controller registers, described in the following sections:
•
•
•
•
•
•
•
4.3.1.1
SIU Interrupt Configuration Register (SICR)
0
1
2
7
8
13
14
15
Field
Reset
R/W
—
HP
—
GSIU SPS
0000_0000_0000_0000
R/W
Addr
Figure 4-10. SIU Interrupt Configuration Register (SICR)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
4-17
System Interface Unit (SIU)
Table 4-4. SICR Field Descriptions
Bits Name
Description
0–1
2–7
—
Reserved, should be cleared.
HP Highest priority. Specifies the 6-bit interrupt number of the single interrupt controller interrupt source
that is advanced to the highest priority in the table. HP can be modified dynamically. To retain the
original priority, program HP to the interrupt number assigned to XSIU1.
8–13
14
—
Reserved, should be cleared.
GSIU Group SIU. Selects the relative XSIU priority scheme. It cannot be changed dynamically.
0 Grouped. The XSIUs are grouped by priority at the top of the table.
1 Spread. The XSIUs are spread by priority in the table.
15
SPS Spread priority scheme. Selects the relative YCC priority scheme. It cannot be changed dynamically.
0 Grouped. The YCCs are grouped by priority at the top of the table.
1 Spread. The YCCs are spread by priority in the table.
4.3.1.2
SIU Interrupt Priority Register (SIPRR)
IRQ1–IRQ5, PIT, PCI, and TMCNT.
0
2
3
5
6
8
9
11
12
15
Field
Reset
R/W
XS1P
000
XS2P
001
XS3P
010
XS4P
011
—
0000
R/W
Addr
16
18
19
21
22
24
25
27
28
31
Field
Reset
R/W
XS5P
100
XS6P
101
XS7P
XS8P
111
—
110
0000
R/W
Addr
0x10C12
Figure 4-11. SIU Interrupt Priority Register (SIPRR)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
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Freescale Semiconductor
System Interface Unit (SIU)
Table 4-5. SIPRR Field Descriptions
Description
Bits
Name
0–2
XS1P–XSIU1 Priority order. Defines which PIT/TMCNT/PCI/IRQs asserts its request in the XSIU1 priority
position. The user should not program the same PIT/TMCNT/PCI/IRQs to more than one
priority position (1–8). These bits can be changed dynamically.
000 TMCNT asserts its request in the XSIU1 position.
001 PIT asserts its request in the XSIU1 position.
010 PCI asserts its request in the XSIU1 position (MPC8250, MPC8265,and MPC8266
only). Reserved on all other devices.
011 IRQ1 asserts its request in the XSIU1 position.
100 IRQ2 asserts its request in the XSIU1 position.
101 IRQ3 asserts its request in the XSIU1 position.
110 IRQ4 asserts its request in the XSIU1 position.
111 IRQ5 asserts its request in the XSIU1 position.
3–11,
XS2P– XS8P Same as XS1P, but for XSIU2–XSIU8.
16–27
12–15,
28–31
—
Reserved, should be cleared.
4.3.1.3
CPM Interrupt Priority Registers (SCPRR_H and SCPRR_L)
The CPM high interrupt priority register (SCPRR_H), shown in Figure 4-12, define priorities between the
FCCs and MCCs.
0
2
3
5
6
8
9
11
12
15
Field
Reset
R/W
XC1P
000
XC2P
001
XC3P
010
XC4P
011
—
0000
R/W
Addr
16
18
19
21
22
24
25
27
28
31
Field
Reset
R/W
XC5P
100
XC6P
101
XC7P
XC8P
111
—
110
0000
R/W
Addr
0x10C16
Figure 4-12. CPM High Interrupt Priority Register (SCPRR_H)
Table 4-6 describes SCPRR_H fields.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
4-19
System Interface Unit (SIU)
Table 4-6. SCPRR_H Field Descriptions
Description
Bits
Name
0–2
XC1P–XCC1 Priority order. Defines which FCC/MCC asserts its request in the XCC1 priority position. The
user should not program the same FCC/MCC to more than one priority position (1–8). These
bits can be changed dynamically.
000 FCC1 asserts its request in the XCC1 position.
001 FCC2 asserts its request in the XCC1 position.
010 FCC3 asserts its request in the XCC1 position.
1
011 XCC1 position not active.
100 MCC1 asserts its request in the XCC1 position.
2
101 MCC2 asserts its request in the XCC1 position.
110 XCC1 position not active.
111 XCC1 position not active.
3–11
XC2P–XC4P Same as XC1P, but for XCC2–XCC4
12–15
—
Reserved, should be cleared.
16–27 XC5P–XC8P Same as XC1P, but for XCC5–XCC8
28–31 Reserved, should be cleared.
—
1
2
Reserved on the MPC8255.
Reserved on the MPC8250 and the MPC8255.
The CPM low interrupt priority register (SCPRR_L), shown in Figure 4-13, defines prioritization of SCCs
and TC layer.
0
2
3
5
6
8
9
11
12
15
Field
Reset
R/W
YC1P
000
YC2P
001
YC3P
010
YC4P
011
—
0000
R/W
Addr
16
18
19
21
22
24
25
27
28
31
Field
Reset
R/W
YC5P
100
YC6P
101
YC7P
YC8P
111
—
110
0000
R/W
Addr
0x10C20
Figure 4-13. CPM Low Interrupt Priority Register (SCPRR_L)
Table 4-7 describes SCPRR_L fields.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
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Freescale Semiconductor
System Interface Unit (SIU)
Table 4-7. SCPRR_L Field Descriptions
Description
Bits
Name
0–2 YC1P–YCC1 Priority order. Defines which SCC asserts its request in the YCC1 priority position. Do not
program the same SCC to multiple priority positions. This field can be changed dynamically.
000 SCC1 asserts its request in the YCC1 position.
001 SCC2 asserts its request in the YCC1 position.
010 SCC3 asserts its request in the YCC1 position.
011 SCC4 asserts its request in the YCC1 position.
100 TC layer asserts its request in the YCC1 position (MPC8264 and MPC8266 only).
Reserved on other devices.
1XX YCC1 position is not active.
3–11 YC2P–YC8P Same as YC1P, but for YCC2–YCC8
12–15
16–27 YC5P–YC8P Same as YC1P, but for YCC5–YCC8
28–31 Reserved, should be cleared.
—
Reserved, should be cleared.
—
4.3.1.4
SIU Interrupt Pending Registers (SIPNR_H and SIPNR_L)
Figure 4-15, corresponds to an interrupt source. When an interrupt is received, the interrupt controller sets
the corresponding SIPNR bit.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Field PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15
Reset
R/W
Undefined (the user should write 1s to clear these bits before using)
R/W
Addr
16
17
18
19
20
21
22
23
24
28
29
30
31
2
Field
Reset
R/W
—
IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7
—
TMCNT PIT PCI
1
1
1
Undefined (the user should write 1s to clear these bits before using)
0
0
0
R/W
Addr
0x10C10
1
2
These fields are zero after reset because their corresponding mask register bits are cleared (disabled).
MPC8250, MPC8265, and MPC8266 only. Reserved on all other devices.
Figure 4-14. SIPNR_H
Figure 4-15 shows SIPNR_L fields.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
4-21
System Interface Unit (SIU)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
15
2
Field FCC1 FCC2 FCC3
—
MCC1 MCC2
—
SCC1 SCC2 SCC3 SCC4
TC
—
1
Reset
R/W
0000_0000_0000_0000
R/W
Addr
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Field I2C SPI RTT SMC1 SMC2 IDMA1 IDMA2 IDMA3 IDMA4 SDMA
—
TIMER1 TIMER2 TIMER3 TIMER4 —
1
1
Reset
R/W
0000_0000_0000_000
R/W
0
Addr
0x10C0E
1
2
These fields are zero after reset because their corresponding mask register bits are cleared (disabled).
MPC8264 and MPC8266 only. Reserved on all other devices.
Figure 4-15. SIPNR_L
When a pending interrupt is handled, the user clears the corresponding SIPNR bit. However, if an event
register exists, the unmasked event register bits should be cleared instead, causing the SIPNR bit to be
cleared.
SIPNR bits are cleared by writing ones to them. Because the user can only clear bits in this register, writing
zeros to this register has no effect.
Note that the SCC/FCC/MCC SIPNR bit positions are not changed according to their relative priority.
4.3.1.5
SIU Interrupt Mask Registers (SIMR_H and SIMR_L)
Each bit in the SIU interrupt mask register (SIMR) corresponds to a interrupt source. The user masks an
interrupt by clearing and enables an interrupt by setting the corresponding SIMR bit. When a masked
interrupt occurs, the corresponding SIPNR bit is set, regardless of the SIMR bit although no interrupt
request is passed to the core.
If an interrupt source requests interrupt service when the user clears its SIMR bit, the request stops. If the
user sets the SIMR bit later, a previously pending interrupt request is processed by the core, according to
its assigned priority. The SIMR can be read by the user at any time.
Figure 4-16 shows the SIMR_H register.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
4-22
Freescale Semiconductor
System Interface Unit (SIU)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Field PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15
Reset
R/W
0000_0000_0000_0000
R/W
Addr
16
17
18
19
20
21
22
23
24
28
29
30
31
1
Field
Reset
R/W
—
IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7
—
TMCNT PIT PCI
0000_0000_0000_0000
R/W
Addr
0x10C1E
1
MPC8250, MPC8265, and MPC8266 only. Reserved on all other devices
Figure 4-16. SIMR_H
Figure 4-17 shows SIMR_L.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
15
1
2
3
Field FCC1 FCC2 FCC3
—
MCC1 MCC2
—
SCC1 SCC2 SCC3 SCC4
TC
—
Reset
R/W
0000_0000_0000_0000
R/W
Addr
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Field I2C SPI RTT SMC1 SMC2 IDMA1 IDMA2 IDMA3 IDMA4 SDMA
—
TIMER1 TIMER2 TIMER3 TIMER4 —
Reset
R/W
0000_0000_0000_0000
R/W
Addr
0x10C22
1
Reserved on the MPC8255.
Reserved on the MPC8250 and the MPC8255.
2
3
MPC8264 and MPC8266 only. Reserved on all other devices.
Figure 4-17. SIMR_L
Note the following:
•
•
SCC/TC/MCC/FCC SIMR bit positions are not affected by their relative priority.
The user can clear pending register bits that were set by multiple interrupt events only by clearing
all unmasked events in the corresponding event register.
•
If an SIMR bit is masked at the same time that the corresponding SIPNR bit causes an interrupt
request to the core, the error vector is issued (if no other interrupts pending). Thus, the user should
always include an error vector routine, even if it contains only an rfi instruction. The error vector
cannot be masked.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
4-23
System Interface Unit (SIU)
4.3.1.6
SIU Interrupt Vector Register (SIVEC)
The SIU interrupt vector register (SIVEC), shown in Figure 4-18, contains an 8-bit code representing the
unmasked interrupt source of the highest priority level.
0
5
6
7
8
9
10
11
12
13
14
15
Field
Reset
R/W
Interrupt Code
0
0
0
0
0
0
0
0
0
0
0000_0000_0000_0000
R
Addr
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Field
Reset
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0000_0000_0000_0000
R
Addr
0x10C06
Figure 4-18. SIU Interrupt Vector Register (SIVEC)
The SIVEC can be read as either a byte, half word, or a word. When read as a byte, a branch table can be
used in which each entry contains one instruction (branch). When read as a half word, each entry can
contain a full routine of up to 256 instructions. The interrupt code is defined such that its two lsbs are
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
4-24
Freescale Semiconductor
System Interface Unit (SIU)
INTR: • • •
Save state
INTR: • • •
Save state
R3 <- @ SIVEC
R3 <- @ SIVEC
R4 <-- BASE OF BRANCH TABLE
R4 <-- BASE OF BRANCH TABLE
• • •
• • •
lbz
RX, R3 (0) # load as byte
RX, RX, R4
CTR, RX
lhz
RX, R3 (0) # load as half
RX, RX, R4
CTR, RX
add
mtspr
bctr
add
mtspr
bctr
1st Instruction of Routine1
BASE
b
b
b
b
Routine1
Routine2
Routine3
Routine4
•
BASE
•
BASE + 4
BASE + 8
BASE + C
BASE +10
BASE + n
BASE + 400
BASE + 800
BASE + C00
BASE +1000
BASE + n
1st Instruction of Routine2
•
1st Instruction of Routine3
•
1st Instruction of Routine4
•
•
•
•
•
•
Figure 4-19. Interrupt Table Handling Example
NOTE
The PowerQUICC II differs from previous MPC8xx implementations in
that when an interrupt request occurs, SIVEC can be read. If there are
multiple interrupt sources, SIVEC latches the highest priority interrupt.
Note that the value of SIVEC cannot change while it is being read.
4.3.1.7
SIU External Interrupt Control Register (SIEXR)
Each defined bit in the SIU external interrupt control register (SIEXR), shown in Figure 4-20, determines
whether the corresponding port C line asserts an interrupt request upon either a high-to-low change or any
change on the pin. External interrupts can come from port C (PC[0-15]).
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
4-25
System Interface Unit (SIU)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
EDPC0 EDPC1 EDPC2 EDPC3 EDPC4 EDPC5 EDPC6 EDPC7 EDPC8 EDPC9 EDPC EDPC EDPC EDPC EDPC EDPC
Field
10
11
12
13
14
15
Reset
R/W
0000_0000_0000_0000
R/W
Addr
16
17
18
19
20
21
22
23
24
31
Field EDI0 EDI1 EDI2 EDI3 EDI4 EDI5 EDI6 EDI7
—
R
Reset
R/W
0000_0000_0000_0000
R/W
Addr
0x10C26
Figure 4-20. SIU External Interrupt Control Register (SIEXR)
Table 4-8 describes SIEXR fields.
Table 4-8. SIEXR Field Descriptions
Description
Bits
Name
0–15 EDPCx Edge detect mode for port Cx. The corresponding port C line (PCx) asserts an interrupt request
according to the following:
0 Any change on PCx generates an interrupt request.
1 High-to-low change on PCx generates an interrupt request.
16–23
EDIx
Edge detect mode for IRQx. The corresponding IRQ line (IRQx) asserts an interrupt request
according to the following:
0 Low assertion on IRQx generates an interrupt request.
1 High-to-low change on IRQx generates an interrupt request.
4.3.2
System Configuration and Protection Registers
The system configuration and protection registers are described in the following sections.
4.3.2.1 Bus Configuration Register (BCR)
features and wait states on the 60x bus.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
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Freescale Semiconductor
System Interface Unit (SIU)
0
1
3
4
5
7
8
9
10
11
12
13
14
15
1
Field EBM
APD
L2C
L2D
PLDP
—
DAM EAV ETM LETM EPAR LEPAR
Reset
R/W
—
000_0000_0000_0000
R/W
16
18
19
20
21
22
25
26
27
28
31
2
1
Field
Reset
R/W
NPQM
—
EXDD
—
SPAR ISPS
—
—
0000_0000_000
0000
R/W
Addr
1
2
MPC8250, MPC8265, and MPC8266 only. Reserved on all other devices.
Figure 4-21. Bus Configuration Register (BCR)
Figure 4-9 describes BCR fields.
Table 4-9. BCR Field Descriptions
Description
Bits
Name
0
EBM External bus mode.
0 Single PowerQUICC II bus mode is assumed
1–3
APD Address phase delay. Specifies the number of address tenure wait states for address operations
initiated by a 60x bus master. BCR[APD] specifies the number of address tenure wait states for
address operations initiated by 60x-bus devices. APD indicates how many cycles the PowerQUICC II
should wait for ARTRY, but because it is assumed that ARTRY can be asserted (by other masters)
only on cachable address spaces, APD is considered only on transactions that hit one of the
60x-assigned memory controller banks and have the GBL signal asserted during address phase.
4
0 No secondary cache controller is assumed.
1 An external secondary cache controller is assumed.
5–7
8
L2D L2 cache hit delay. Controls the number of clock cycles from the assertion of TS until HIT is valid.
0 The pipeline maximum depth is one.
1 The pipeline maximum depth is zero.
9
—
Reserved, should be cleared.
10
DAM Delay all masters. Applies to all the masters on the bus (CPU, EXT, CPM). This bit is similar to
BCR[EXDD] but with opposite polarity.
0 The memory controller asserts CS on the cycle following the assertion of TS when accessing an
address space controlled by the memory controller.
1 The memory controller inserts one wait state between the assertion of TS and the assertion of CS
when accessing an address space controlled by the memory controller.
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Freescale Semiconductor
4-27
System Interface Unit (SIU)
Table 4-9. BCR Field Descriptions (continued)
Description
Bits
Name
11
EAV Enable address visibility. Normally, when the PowerQUICC II is in single-PowerQUICC II bus mode,
the bank select signals for SDRAM accesses are multiplexed on the 60x bus address lines. So, for
SDRAM accesses, the internal address is not visible for debug purposes. However the bank select
signals can also be driven on dedicated pins (see SIUMCR[APPC]). In this case EAV can be used to
force address visibility.
0 Bank select signals are driven on 60x bus address lines. There is no full address visibility.
1 Bank select signals are not driven on address bus. During READ and WRITE commands to
SDRAM devices, the full address is driven on 60x bus address lines.
12
13
0 Strict 60x bus mode. Extended transfer mode is disabled.
1 Extended transfer mode is enabled.
0 Extended transfer mode is disabled on the local bus.
1 Extended transfer mode is enable on the local bus.
Note that if the local bus memory controller is configured to work with read-modify-write parity, LETM
must be cleared.
14
15
EPAR Even parity. Determines odd or even parity on the 60x bus.
0 Odd parity
1 Even parity
Writing the memory with EPAR = 1 and reading the memory with EPAR = 0 generates parity errors
for testing.
LEPAR Local bus even parity. Determines odd or even parity on the local bus.
0 Odd parity
1 Even parity
Writing the memory with LEPAR = 1 and reading the memory with LEPAR = 0 generates parity errors
for testing.
16–18 NPQM Non PowerQUICC II master. Identifies the type of bus masters which are connected to the arbitration
lines when the PowerQUICC II is in internal arbiter mode. Possible types are PowerQUICC II master
and non-PowerQUICC II master. This field is related to the data pipelining bits (BRx[DR]) in the
memory controller. Because an external bus master that is not a PowerQUICC II cannot use the data
pipelining feature, the PowerQUICC II, which controls the memory, needs to know when a
non-PowerQUICC II master is accessing the memory and handle the transaction differently.
NPQM[0] designates the type of master connected to the set of pins BR, BG, and DBG.
NPQM[1] designates the type of master connected to the set of pins EXT_BR2, EXT_BG2, and
EXT_DBG2.
NPQM[2] designates the type of master which is connected to the set of pins EXT_BR3, EXT_BG3
and EXT_DBG3
0 The bus master connected to the arbitration lines is a PowerQUICC II.
1 The bus master connected to the arbitration lines is not a PowerQUICC II.
19–20
—
Reserved, should be cleared.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
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Freescale Semiconductor
System Interface Unit (SIU)
Table 4-9. BCR Field Descriptions (continued)
Description
Bits
Name
21
EXDD External master delay disable. Generally, the PowerQUICC II adds one clock cycle delay for each
external master access to a region controlled by the memory controller. This occurs because the
external master drives the address on the external pins (compared to internal master, like
PowerQUICC II’s DMA, which drives the address on an internal bus in the chip). Thus, it is assumed
that an additional cycle is needed for the memory controllers banks to complete the address match.
However in some cases (when the bus is operated in low frequency), this extra cycle is not needed.
The user can disable the extra cycle by setting EXDD.
0 The memory controller inserts one wait state between the assertion of TS and the assertion of CS
when external master accesses an address space controlled by the memory controller.
1 The memory controller asserts CS on the cycle following the assertion of TS by external master
accessing an address space controlled by the memory controller.
22–25
26
—
—
Reserved, should be cleared.
.29µm (HiP3) devices: Reserved, should be cleared.
SPAR .25µm (HiP4) devices: Slave parity check. If set enables parity check on 60x bus transactions to the
MPC826xA's internal memory space. In case of a parity error a core machine check is asserted and
the error is reported in TESCR1[ISBE,PAR] and TESCR2[REGS,DPR,PCI0,PCI1,LCL].
Note: TESCR2[PCI0, PCI1] are only on the MPC8250, the MPC8265, and the MPC8266.
27
ISPS Internal space port size. Defines the port size of PowerQUICC II’s internal space region as seen to
external masters. Setting ISPS enables a 32-bit master to access PowerQUICC II internal space.
0 PowerQUICC II acts as a 64-bit slave to external masters accesses to its internal space.
1 PowerQUICC II acts as a 32-bit slave to external masters accesses to its internal space.
28–31
—
Reserved, should be cleared.
4.3.2.2
60x Bus Arbiter Configuration Register (PPC_ACR)
The 60x bus arbiter configuration register (PPC_ACR), shown in Figure 4-22, defines the arbiter modes
and parked master on the 60x bus.
0
1
2
3
4
7
1
Field
Reset
R/W
—
DBGD
EARB
PRKM
0010
000
See note
R/W
Addr
1
Figure 4-22. PPC_ACR
Table 4-10 describes PPC_ACR fields.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
4-29
System Interface Unit (SIU)
Table 4-10. PPC_ACR Field Descriptions
Description
Bits
Name
0–1
2
—
Reserved, should be cleared.
DBGD Data bus grant delay. Specifies the minimum number of data tenure wait states for 60x bus
master-initiated data operations. This is the minimum delay between TS and DBG.
0 DBG is asserted with TS if the data bus is free.
1 DBG is asserted one cycle after TS if the data bus is not busy.
3
EARB External arbitration.
1 External arbitration is assumed.
4–7
PRKM Parking master.
0000 CPM high request level refers to the IDMA which involves peripherals and the following serial
2
channels (SCC, SPI, SMC, and I C)
0001 CPM middle request level refers to all other serial channels (FCCs and MCCs)
0010 CPM low request level: it is possible to change the request level for all FCCs and MCCs to low
priority when PPC_ACR[4–7] = 0010 and FCRx[1] = 1 (See Section 29.7.1, “FCC Function
Code Registers (FCRx).”
0011 PCI request level (MPC8250, MPC8265, and MPC8266 only). Reserved on all other devices.
0100 Reserved
0101 Reserved
0110 Internal core
0111 External master 1
1000 External master 2
1001 External master 3
Values 1010–1111 are reserved.
4.3.2.3
60x Bus Arbitration-Level Registers (PPC_ALRH/PPC_ALRL)
The 60x bus arbitration-level registers, shown in Figure 4-23 and Figure 4-24, define arbitration priority
of PowerQUICC II bus masters. Priority field 0 has highest-priority. For information about
0
3
4
7
8
11
12
15
Field
Reset
R/W
Priority Field 0
0000
Priority Field 1
0001
Priority Field 2
0010
Priority Field 3
0110
R/W
Addr
16
19
20
23
24
27
28
31
Field
Reset
R/W
Priority Field 4
0011
Priority Field 5
0100
Priority Field 6
0101
Priority Field 7
0111
R/W
0x1002E
Figure 4-23. PPC_ALRH
Addr
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
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Freescale Semiconductor
System Interface Unit (SIU)
PPC_ALRL, shown in Figure 4-24, defines arbitration priority of 60x bus masters 8–15. Priority field 0 is
the highest-priority arbitration level. For information about the PowerQUICC II bus master indexes, see
0
3
4
7
8
11
12
15
Field
Reset
R/W
Priority Field 8
1000
Priority Field 9
1001
Priority Field 10
1010
Priority Field 11
1011
R/W
Addr
16
19
20
23
24
27
28
31
Field
Reset
R/W
Priority Field 12
1100
Priority Field 13
1101
Priority Field 14
1110
Priority Field 15
1111
R/W
0x10032
Figure 4-24. PPC_ALRL
Addr
4.3.2.4
Local Bus Arbiter Configuration Register (LCL_ACR)
The local bus arbiter configuration register (LCL_ACR), shown in Figure 4-25, defines the arbiter modes
and the parked master on the local bus.
0
1
2
3
4
7
Field
Reset
R/W
—
DBGD
—
PRKM
0000_0010
R/W
Addr
Figure 4-25. LCL_ACR
Table 4-11 describes LCL_ACR register bits.
Table 4-11. LCL_ACR Field Descriptions
Bits Name
Description
0–1
2
—
Reserved, should be cleared.
DBGD Data bus grant delay. Specifies the minimum number of data tenure wait states for PowerPC
master-initiated data operations. This is the minimum delay between TS and DBG.
0 DBG is asserted with TS if the data bus is free.
1 DBG is asserted one cycle after TS if the data bus is not busy.
3
—
Reserved, should be cleared.
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System Interface Unit (SIU)
Bits Name
Table 4-11. LCL_ACR Field Descriptions (continued)
Description
4–7 PRKM Parking master. Defines the parked master.
0000 CPM high request level refers to the IDMA which involves peripherals and the following serial
2
channels (SCC, SPI, SMC, and I C)
0001 CPM middle request level refers to all other serial channels (FCCs and MCCs)
0010 CPM low request level: it is possible to change the request level for all FCCs and MCCs to low
priority when PPC_ACR[4–7] = 0010 and FCRx[1] = 1 (See Section 28.7.1, “FCC Function
Code Registers (FCRx).”
0011 Host bridge
Values 0100–1111 are reserved.
4.3.2.5
Local Bus Arbitration Level Registers (LCL_ALRH and LCL_ACRL)
Figure 4-27, define arbitration priority for local bus masters 0–7. Priority field 0 has highest-priority. For
0
3
4
7
8
11
12
15
Field
Reset
R/W
Priority Field 0
0000
Priority Field 1
0001
Priority Field 2
0010
Priority Field 3
0110
R/W
Addr
16
19
20
23
24
27
28
31
Field
Reset
R/W
Priority Field 4
0011
Priority Field 5
0100
Priority Field 6
0101
Priority Field 7
0111
R/W
0x10040
Figure 4-26. LCL_ALRH
Addr
LCL_ALRL, shown in Figure 4-27, defines arbitration priority of PowerQUICC II local bus masters 8–15.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
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Freescale Semiconductor
System Interface Unit (SIU)
0
3
4
7
8
11
12
15
Field
Reset
R/W
Priority Field 8
1000
Priority Field 9
1001
Priority Field 10
1010
Priority Field 11
1011
R/W
Addr
16
19
20
23
24
27
28
31
Field
Reset
R/W
Priority Field 12
1100
Priority Field 13
1101
Priority Field 14
1110
Priority Field 15
1111
R/W
0x1003E
Figure 4-27. LCL_ALRL
Addr
4.3.2.6
SIU Module Configuration Register (SIUMCR)
various features in the SIU module.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Field BBD
ESE PBSE CDIS
00
DPPC
L2CPC
LBPC
see note
R/W
APPC
CS10PC
BCTLC
00
Reset see note
R/W
Addr
16
17
18
19
31
Field
Reset
R/W
MMR
see note
LPBSE
—
0
see note
R/W
Addr
0x10002
1
Figure 4-28. SIU Model Configuration Register (SIUMCR)
Table 4-12 describes SIUMCR fields.
Table 4-12. SIUMCR Register Field Descriptions
Bits
Name
Description
0
BBD
Bus busy disable.
0 ABB/IRQ2 pin is ABB, DBB/IRQ3 pin is DBB
1 ABB/IRQ2 pin is IRQ2, DBB/IRQ3 pin is IRQ3
1
ESE
External snoop enable. Configures GBL/IRQ1
0 External snooping disabled. (GBL/IRQ1 pin is IRQ1)
1 External snooping enabled. (GBL/IRQ1 pin is GBL)
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4-33
System Interface Unit (SIU)
Table 4-12. SIUMCR Register Field Descriptions (continued)
Description
Bits
Name
2
PBSE Parity byte select enable.
0 Parity byte select is disabled. GPL4 output of UPM is available for memory control.
1 Parity byte select is enabled. GPL4 pin is used as parity byte select output from the
PowerQUICC II.
3
CDIS
Core disable.
0 The PowerQUICC II core is enabled.
1 The PowerQUICC II core is disabled. PowerQUICC II functions as a slave device.
4–5
DPPC Data parity pins configuration. Note that the additional arbitration lines (EXT_BR2, EXT_BG2,
EXT_DBG2, EXT_BR3, EXT_BG3, and EXT_DBG3) are operational only when ACR[EARB] = 0.
Setting EARB (to choose external arbiter) combined with programming DPPC to 11 deactivates
these lines.
DPPC
Pin
00
01
10
11
DP(0)/RSRV
DP(1)/IRQ1
—
DP(0)
DP(1)
DP(2)
DP(3)
RSRV
IRQ1
EXT_BR2
EXT_BG2
EXT_DBG2
EXT_BR3
IRQ1
IRQ2
IRQ3
DP(2)/TLBISYNC/IRQ2
DP(3)/IRQ3
TLBISYNC
CKSTP_OU
T
DP(4)/IRQ4
IRQ4
DP(4)
CORE_SRE
SET
EXT_BG3
DP(5)/TBEN/IRQ5
DP(6)/CSE(0)/IRQ6
DP(7)/CSE(1)/IRQ7
IRQ5
IRQ6
IRQ7
DP(5)
DP(6)
DP(7)
TBEN
CSE(0)
CSE(1)
EXT_DBG3
IRQ6
IRQ7
6–7
L2CPC L2 cache pins configuration.
Multiplexing
Pin
L2CPC = 00 L2CPC = 01 L2CPC = 10
CI/BADDR(29)/IRQ2
WT/BADDR(30)/IRQ3
L2_HIT/IRQ4
CI
IRQ2
IRQ3
IRQ4
IRQ5
BADDR(29)
BADDR(30)
—
WT
L2_HIT
CPU_BG
CPU_BG/BADDR(31)/IRQ5
BADDR(31)
8–9
LBPC Local bus pins configuration.
Note: LBPC should be programmed only during the hard reset configuration sequence (using the
hard reset configuration word).
00 Local bus pins function as local bus
01 Local bus pins function as PCI bus (MPC8250, MPC8265, and MPC8266 only). Reserved on
all other devices.
10 Local bus pins function as core pins
11 Reserved
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System Interface Unit (SIU)
Table 4-12. SIUMCR Register Field Descriptions (continued)
Description
Bits
Name
10–11
APPC Address parity pins configuration. Note that during power on reset the MODCK pins are used for
PLL configuration. The pin multiplexing indicated in the table applies only to normal operation.
Selection between IRQ7 and INT_OUT is according to CPU state. If the core is disabled, the pin
is INT_OUT; otherwise it is IRQ7.
APPC
Pin
00
01
10
11
MODCK1/AP(1)/TC(0)/
BNKSEL(0)
TC(0)
AP(1)
BNKSEL(0)
—
MODCK2/AP(2)/TC(1)/
BNKSEL(1)
TC(1)
TC(2)
AP(2)
AP(3)
APE
BNKSEL(1)
BNKSEL(2)
MODCK3/AP(3)/TC(2)/
BNKSEL(2)
IRQ7/INT_OUT/APE
IRQ7/
IRQ7/
IRQ7/
INT_OUT
INT_OUT
INT_OUT
CS11/AP(0)
CS11
AP(0)
CS11
—
12–13
14–15
CS10PC Chip select 10-pin configuration.
CS10PC
01
Pin
00
10
CS10/BCTL1
CS10
BCTL1
—
BCTLC Configuration for the control lines for external buffers.
00 BCTL0 is used as W/R control for external buffers. BCTL1 is used as OE control for external
buffers.
01 BCTL0 is used as W/R control for external buffers. BCTL1 is used as OE control for external
buffers.
10 BCTL0 is used as WE control for external buffers. BCTL1 is used as RE control for external
buffers.
11 Reserved
16-17
MMR
Mask masters requests. In some systems, several bus masters are active during normal
operation; only one should be active during boot sequence. The active master, which is the boot
device, initializes system memories and devices and enables all other masters. MMR facilitates
such a boot scheme by masking the selected master’s bus requests. MMR can be configured
through the hard reset configuration sequence (see Section 5.4.2, “Hard Reset Configuration
initializes the system and then enables all other devices by writing 00 to MMR.
Note: It is not recommended to mask the request of a master which is defined as the parked
master in the arbiter, since this cannot prevent this master from getting a bus grant.
00 No masking on bus request lines.
01 Reserved
10 The PowerQUICC II’s internal core bus request masked and external bus requests two and
three masked (boot master connected to external bus request 1).
11 All external bus requests masked (boot master is the PowerQUICC II’s internal core).
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
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System Interface Unit (SIU)
Table 4-12. SIUMCR Register Field Descriptions (continued)
Description
Bits
Name
18
LPBSE Local bus parity byte select enable.
0 Parity byte select is disabled. LGPL4 output of UPM is available for memory control.
1 Parity byte select is enabled. LGPL4 pin is used as local bus parity byte select output from the
PowerQUICC II.
19–31
—
Reserved, should be cleared.
4.3.2.7
Internal Memory Map Register (IMMR)
The internal memory map register (IMMR), shown in Figure 4-29, contains identification of a specific
device as well as the base address for the internal memory map. Software can deduce availability and
location of any on-chip system resources from the values in IMMR. PARTNUM and MASKNUM are
mask programmed and cannot be changed for any particular device.
0
14
15
Field
Reset
R/W
ISB
—
R/W
Addr
16
23
24
31
Field
Reset
R/W
PARTNUM
MASKNUM
0x0011 (.29µm Rev A.1); 0x0023 (.29µm Rev B.3); 0x0024 (.29µm Rev C.2); 0x0060 (.25µm Rev A.0)
R
0x101AA
Addr
Figure 4-29. Internal Memory Map Register (IMMR)
Table 4-13 describes IMMR fields.
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Freescale Semiconductor
System Interface Unit (SIU)
Table 4-13. IMMR Field Descriptions
Description
Bits
Name
0–14
ISB
Internal space base. Defines the base address of the internal memory space. The value of ISB
is configured at reset to one of eight addresses; it can then be changed to any value by the
software. The default is 0, which maps to address 0x0000_0000. (See Section 5.4.1, “Hard
ISB defines the 15 msbs of the memory map register base address. IMMR itself is mapped in
the internal memory space region. As soon as the ISB is written with a new base address, the
IMMR base address is relocated according to the ISB. ISB can be configured to one of eight
possible addresses at reset to enable the configuration of multiple-PowerQUICC II systems.
The number of programmable bits in this field, and hence the resolution of the location of
internal space, depends on the internal memory space of a specific implementation. In the
values.
15
—
Reserved, should be cleared.
16–23 PARTNUM Part number. This read-only field is mask-programmed with a code corresponding to the part
number of the part on which the SIU is located. It is intended to help factory test and user code
which is sensitive to part changes. This changes when the part number changes. For example,
it would change if any new module is added or if the size of any memory module is changed. It
would not change if the part is changed to fix a bug in an existing module. The PowerQUICC II
has an ID of 0x00.
24–31 MASKNUM Mask number. This read-only field is mask-programmed with a code corresponding to the mask
number of the part on which the SIU is located. It is intended to help factory test and user code
which is sensitive to part changes. It is programmed in a commonly changed layer and should
be changed for all mask set changes.
4.3.2.8
System Protection Control Register (SYPCR)
The system protection control register, shown in Figure 4-30, controls the system monitors, software
watchdog period, and bus monitor timing. SYPCR can be read at any time but can be written only once
after system reset.
0
15
Field
Reset
R/W
SWTC
1111_1111_1111_1111
R/W
Addr
16
23
24
25
26
28
29
30
31
Field
Reset
R/W
BMT
PBME LBME
—
SWE SWRI SWP
1111_1111
0
0
00_0
1
1
1
R/W
0x10006
Addr
Figure 4-30. System Protection Control Register (SYPCCR)
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Freescale Semiconductor
4-37
System Interface Unit (SIU)
Table 4-14 describes SYPCR fields.
Table 4-14. SYPCR Field Descriptions
Description
0–15 SWTC Software watchdog timer count. Contains the count value for the software watchdog timer.
Bits
Name
16–23
BMT Bus monitor timing. Defines the time-out period for the bus monitor, the granularity of this field is 8
bus clocks. (BMT = 0xFF is translated to 0x7f8 clock cycles). BMT is used both in the 60x and local
bus monitors.
Note that the value 0 in invalid; an error is generated for each bus transaction.
24
25
PBME 60x bus monitor enable.
0 60x bus monitor is disabled.
1 The 60x bus monitor is enabled.
LBME Local bus monitor enable.
0 Local bus monitor is disabled.
1 The local bus monitor is enabled.
26–28
29
—
Reserved, should be cleared.
SWE Software watchdog enable. Enables the operation of the software watchdog timer. It should be
cleared by software after a system reset to disable the software watchdog timer.
30
SWRI Software watchdog reset/interrupt select.
0 Software watchdog timer and bus monitor time-out cause a machine check interrupt to the core.
1 Software watchdog timer and bus monitor time-out cause a hard reset (this is the default value
after soft reset).
31
SWP Software watchdog prescale. Controls the divide-by-2,048 software watchdog timer prescaler.
0 The software watchdog timer is not prescaled.
1 The software watchdog timer clock is prescaled.
4.3.2.9
Software Service Register (SWSR)
The software service register (SWSR) is the location to which the software watchdog timer servicing
sequence is written. To prevent software watchdog timer time-out, the user should write 0x556C followed
by 0xAA39 to this register, which resides at 0x0x1000E. SWSR can be written at any time, but returns all
zeros when read.
4.3.2.10 60x Bus Transfer Error Status and Control Register 1 (TESCR1)
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Freescale Semiconductor
System Interface Unit (SIU)
0
1
2
3
4
5
6
7
9
10
11
15
Field
Reset
R/W
BM
ISBE PAR ECC2 ECC1 WP EXT
TC
—
TT
0000_0000_0000_0000
R/W
Addr
16
17
18
19
20
21
22
23
24
31
1
2
2
2
2
Field
Reset
R/W
—
DMD
—
PCIMCP DER IRQ0 SWD ADO
ECNT
0000_0000_0000_0000
R/W
Addr
0x10042
1
2
MPC8250, MPC8265, and MPC8266 only. Reserved on all other devices.
Reserved on .29µm (HiP3) Rev A.1 devices.
Note: Bits 0–15 and 19–23 are status bits and are cleared by writing 1s.
Figure 4-31. 60x Bus Transfer Error Status and Control Register 1 (TESCR1)
Table 4-15 describes TESCR1 fields.
Table 4-15. TESCR1 Field Descriptions
Bits
Name
Description
0
1
BM
60x bus monitor time-out. Set when TEA is asserted due to the 60x bus monitor time-out.
ISBE
Internal space bus error. Indicates that one of the following occurred:
• TEA was asserted due to an error on a transaction to PowerQUICC II’s internal memory space
• An MCP was caused by a parity error on a transaction to PowerQUICC II’s internal memory
space. Possible only if BCR[SPAR] = 1(.25µm (HiP4) devices only) .
TESCR2[REGS,DPR, LCL, PCI0, PCI1] indicate which of PowerQUICC II’s internal slaves caused
the error. TESCR2[PCI0, PCI1] are only on the MPC8250, the MPC8265, and the MPC8266.
2
PAR
60x bus parity error. Indicates that an MCP was caused due to one of the following:
• Parity error on 60x bus access controlled by the memory controller. TESCR2[PB] indicates which
byte lane caused the error; TESCR2[BNK] indicates which memory controller bank was
accessed.
• Parity error on a transaction to PowerQUICC II’s internal memory space. Possible only if
BCR[SPAR] = 1 (.25µm (HiP4) devices only).
3
4
ECC2
ECC1
Double ECC error. Indicates that MCP was asserted due to double ECC error on the 60x bus.
TESCR2[BNK] indicates which memory controller bank was accessed.
Single ECC error. Indicates that MCP was asserted due to single bit ECC error on the 60x bus.
TESCR2[BNK] indicates which memory controller bank was accessed. Single-bit errors are fixed
by the ECC logic. However, if the ECC counter (ECNT) has reached its maximum value, all single-bit
errors cause the assertion of MCP.
5
6
WP
Write protect error. Indicates that a write was attempted to a 60x bus memory region that was
defined as read-only in the memory controller. Note that this alone does not cause TEA assertion.
Usually, in this case, the bus monitor will time-out.
EXT
External error. Indicates that TEA was asserted by an external bus slave.
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Freescale Semiconductor
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System Interface Unit (SIU)
Table 4-15. TESCR1 Field Descriptions (continued)
Description
Bits
Name
7–9
TC
Transfer code. Indicates the transfer code of the 60x bus transaction that caused the TEA or MCP.
codes.
10
—
Reserved, should be cleared.
11–15
TT
Transfer type. These bits indicates the transfer type of the 60x bus transaction that caused the TEA
various transfer types.
16
17
—
Reserved, should be cleared.
DMD
Data errors disable.
0 Errors are enabled.
1 All data errors (parity and single and double ECC errors) on the 60x bus are disabled.
18
19
—
—
Reserved, should be cleared.
All non-PCI devices: Reserved, should be cleared.
PCIMCP MPC8250, MPC8265, and MPC8266 only: PCI machine check. Set when a core machine check is
asserted from the PCI bridge.
20
21
22
—
.29µm (HiP3) Rev A.1 devices: Reserved, should be cleared.
DER
.29µm (HiP3) Rev B.3 silicon and forward: Data error. Set when a core machine check is asserted
due to ECC or parity errors.
—
.29µm (HiP3) Rev A.devices: Reserved, should be cleared.
IRQ0
.29µm (HiP3) Rev B.3 silicon and forward: External machine check. Set when a machine check is
asserted due to the external machine check pin (IRQ0).
—
.29µm (HiP3) Rev A.1 devices: Reserved, should be cleared.
SWD
.29µm (HiP3) Rev B.3 silicon and forward: Software watchdog time-out. Indicates that a core
machine check was asserted due to a time-out in the software watchdog. See Section 4.1.5,
“Software Watchdog Timer.”
23
—
.29µm (HiP3) Rev A.1 devices: Reserved, should be cleared.
ADO
.29µm (HiP3) Rev B.3 silicon and forward: 60x bus monitor address-only time-out. Set when a core
machine check is asserted due to time-out of the bus monitor in an address only transaction. See
Section 4.1.1, “Bus Monitor.”
24–31
ECNT Single ECC error counter. Indicates the number of single ECC errors that occurred in the system.
When the counter reaches its maximum value (255), MCP is asserted for all single ECC errors. This
feature gives the system the ability to withstand a few random errors yet react to a catastrophic
failure. The user can set a lower threshold to the number of tolerated single ECC errors by writing
some value to ECNT. The counter starts from this value instead of zero.
4.3.2.11 60x Bus Transfer Error Status and Control Register 2 (TESCR2)
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Freescale Semiconductor
System Interface Unit (SIU)
0
1
2
3
4
5
6
7
8
15
1
1
Field
Reset
R/W
—
REGS DPR
—
PCI0 PCI1
—
LCL
PB
0000_0000_0000_0000
R/W
Addr
16
27
28
31
Field
Reset
R/W
BNK
0000_0000_0000_0000
—
R/W
Addr
0x10046
1
MPC8250, MPC8265, and MPC8266 only. Reserved on all other devices.
Note: all bits are status bits and are cleared by writing 1s.
Figure 4-32. 60x Bus Transfer Error Status and Control Register 2 (TESCR2)
Table 4-16. TESCR2 Field Descriptions
Bits
Name
Description
0
1
2
3
4
—
Reserved, should be cleared.
REGS Internal registers error. An error occurred in a transaction to the PowerQUICC II’s internal registers.
DPR Dual port ram error. An error occurred in a transaction to the PowerQUICC II’s dual-port RAM.
—
—
Reserved, should be cleared.
Reserved, should be cleared.
PCI0 MPC8250, MPC8265, and MPC8266 only: PCI memory space 0 error. An error occurred in a
transaction to the PCI memory space configured by PCIBR0 and PCIMSK0.
5
—
Reserved, should be cleared.
PCI1 MPC8250, MPC8265, and MPC8266 only: PCI memory space 1 error. An error occurred in a
transaction to the PCI memory space configured by PCIBR1 and PCIMSK1.
6
7
—
Reserved, should be cleared.
LCL Local bus bridge error. An error occurred in a transaction to the PowerQUICC II’s 60x bus to local
bus bridge.
8–15
PB
Parity error on byte. There are eight parity error status bits, one per 8-bit lane. A bit is set for the
byte that had a parity error.
16–27
BNK Memory controller bank. There are twelve error status bits, one per memory controller bank. A bit
is set for the 60x bus memory controller bank that had an error. Note that this field is invalid if the
error was not caused by ECC or parity checks.
28–31
—
Reserved, should be cleared.
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Freescale Semiconductor
4-41
System Interface Unit (SIU)
4.3.2.12 Local Bus Transfer Error Status and Control Register 1 (L_TESCR1)
0
1
2
3
4
5
6
7
9
10
11
15
Field BM
—
PAR
—
WP
—
TC
—
TT
Reset
R/W
0000_0000_0000_0000
R/W
Addr
16
17
18
19
20
21
31
1
Field
Reset
R/W
—
DMD
—
DER
—
0000_0000_0000_0000
R/W
Addr
0x1004A
1
.29µm (HiP3) Rev B.3 silicon and forward. Reserved on .29µm Rev A.1 devices.
Note: Bits 0–15 and 19–23 are status bits and are cleared by writing 1s.
Figure 4-33. Local Bus Transfer Error Status and Control Register 1 (L_TESCR1)
Table 4-17. L_TESCR1 Field Descriptions
Bits
Name
Description
0
1
2
BM
—
Bus monitor time-out. Indicates that TEA was asserted due to the local bus monitor time-out.
Reserved, should be cleared.
PAR Parity error. Indicates that MCP was asserted due to parity error on the local bus. L_TESCR2[PB]
indicates the byte lane that caused the error and L_TESCR2[BNK] indicates which memory
controller bank was accessed.
3–4
5
—
Reserved, should be cleared.
WP
Write protect error. Indicates that a write was attempted to a local bus memory region that was
defined as read-only in the memory controller. Note that this alone does not cause TEA assertion.
Usually, in this case, the bus monitor will time-out.
6
—
Reserved, should be cleared.
7–9
TC
Transfer code. Indicates the transfer code of the local bus transaction that caused the TEA.
000 60x-local bridge
001 Reserved
010 Local DMA function code 0
011 Local DMA function code 1
1xx Reserved
10
—
Reserved, should be cleared.
11–15
TT
Transfer type. Indicates the transfer type of the local bus transaction that caused the TEA.
16
—
Reserved, should be cleared.
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Freescale Semiconductor
System Interface Unit (SIU)
Table 4-17. L_TESCR1 Field Descriptions (continued)
Description
Bits
Name
17
18–19
20
DMD
—
Data errors disable. Setting this bit disables parity errors on the local bus.
Reserved, should be cleared.
—
.29µm (HiP3) Rev A.1 silicon: reserved, should be cleared.
DER .29µm (HiP3) Rev B.3 silicon and forward: Data error. Set when a core machine check is asserted
due to parity errors in the local bus.
21–31
—
Reserved, should be cleared.
4.3.2.13 Local Bus Transfer Error Status and Control Register 2 (L_TESCR2)
0
11
12
15
Field
Reset
R/W
—
PB
0000_0000_0000_0000
R/W
Addr
16
27
28
31
Field
Reset
R/W
BNK
0000_0000_0000_0000
—
R/W
Addr
0x1004E
Note: all bits are status bits and are cleared by writing 1s.
Figure 4-34. Local Bus Transfer Error Status and Control Register 2 (L_TESCR2)
Table 4-18 describes L_TESCR2 fields.
Table 4-18. L_TESCR2 Field Descriptions
Bits
Name
Description
0–11
—
Reserved, should be cleared.
12–15
PB
Parity error on byte. There are four parity error status bits, one per 8-bit lane. A bit is set for the byte
that had a parity error.
16–27
28–31
BNK Memory controller bank. There are twelve error status bits, one per memory controller bank. A bit is
set for the local bus memory controller bank that had an error. Note that BNK is invalid if the error
was not caused by ECC or PARITY checks.
—
Reserved, should be cleared.
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Freescale Semiconductor
4-43
System Interface Unit (SIU)
4.3.2.14 Time Counter Status and Control Register (TMCNTSC)
different TMCNT functions and for reporting the source of the interrupts. The register can be read at any
time. Status bits are cleared by writing ones; writing zeros does not affect the value of a status bit.
.
0
7
8
9
10
11
12
13
14
15
Field
Reset
R/W
—
SEC ALR
—
SIE ALE TCF TCE
0000_0000_0000_0000
R/W
Addr
Figure 4-35. Time Counter Status and Control Register (TMCNTSC)
Table 4-19 describes TMCNTSC fields.
Table 4-19. TMCNTSC Field Descriptions
Bits
Name
Description
0–7
8
—
Reserved, should be cleared.
SEC Once per second interrupt. This status bit is set every second and should be cleared by software.
9
ALR Alarm interrupt. This status bit is set when the value of the TMCNT is equal to the value programmed
in the alarm register.
10–11
12
—
Reserved, should be cleared.
SIE
Second interrupt enable.
0 The time counter does not generate an interrupt when SEC is set.
1 The time counter generates an interrupt when SEC is set.
13
14
ALE Alarm interrupt enable. If ALE = 1, the time counter generates an interrupt when ALR is set.
TCF Time counter frequency. The input clock to the time counter may be either 4 MHz or 32 KHz. The
user should set the TCF bit according to the frequency of this clock.
0 The input clock to the time counter is 4 MHz.
1 The input clock to the time counter is 32 KHz.
15
TCE Time counter enable. Is not affected by soft or hard reset.
0 The time counter is disabled.
1 The time counter is enabled.
4.3.2.15 Time Counter Register (TMCNT)
The time counter register (TMCNT), shown in Figure 4-36, contains the current value of the time counter.
The counter is reset to zero on PORESET reset or hard reset but is not effected by soft reset.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
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Freescale Semiconductor
System Interface Unit (SIU)
0
15
Field
Reset
R/W
TMCNT
0000_0000_0000_0000
R/W
Addr
16
31
Field
Reset
R/W
TMCNT
0000_0000_0000_0000
R/W
0x10226
Addr
Figure 4-36. Time Counter Register (TCMCNT)
4.3.2.16 Time Counter Alarm Register (TMCNTAL)
value of TMCNT equals ALARM, a maskable interrupt is generated.
0
15
Field
Reset
R/W
ALARM
0000_0000_0000_0000
R/W
Addr
16
31
Field
Reset
R/W
ALARM
0000_0000_0000_0000
R/W
0x1222E
Addr
Figure 4-37. Time Counter Alarm Register (TMCNTAL)
Table 4-20 describes TMCNTAL fields.
Table 4-20. TMCNTAL Field Descriptions
Bits Name
Description
0–31 ALARM The alarm interrupt is generated when ALARM field matches the corresponding TMCNT bits. The
resolution of the alarm is 1 second.
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System Interface Unit (SIU)
4.3.3
Periodic Interrupt Registers
The periodic interrupt registers are described in the following sections.
4.3.3.1
Periodic Interrupt Status and Control Register (PISCR)
The periodic interrupt status and control register (PISCR), shown in Figure 4-38, contains the interrupt
request level and the interrupt status bit. It also contains the controls for the 16 bits to be loaded in a
modulus counter.
0
7
8
9
12
13
14
15
Field
Reset
R/W
—
PS
—
PIE PTF PTE
0000_0000_0000_0000
R/W
Addr
Figure 4-38. Periodic Interrupt Status and Control Register (PISCR)
Table 4-21 describes PISCR fields.
Table 4-21. PISCR Field Descriptions
Bits Name
Description
0–7
8
—
Reserved, should be cleared.
PS Periodic interrupt status. Asserted if the PIT issues an interrupt. The PIT issues an interrupt after the
modulus counter counts to zero. The PS bit can be negated by writing a one to PS. A write of zero has
no effect on this bit.
9–12
13
—
Reserved, should be cleared.
PIE Periodic interrupt enable. If PIE = 1, the periodic interrupt timer generates an interrupt when PS = 1.
14
PTF Periodic interrupt frequency. The input clock to the periodic interrupt timer may be either 4 MHz or
32 KHz. The user should set the PTF bit according to the frequency of this clock.
0 The input clock to the periodic interrupt timer is 4 MHz.
1 The input clock to the periodic interrupt timer is 32 KHz.
15
PTE Periodic timer enable. This bit controls the counting of the periodic interrupt timer. When the timer is
disabled, it maintains its old value. When the counter is enabled, it continues counting using the
previous value.
0 Disable counter.
1 Enable counter
4.3.3.2
Periodic Interrupt Timer Count Register (PITC)
The periodic interrupt timer count register (PITC), shown in Figure 4-39, contains the 16 bits to be loaded
in a modulus counter.
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Freescale Semiconductor
System Interface Unit (SIU)
0
15
Field
Reset
R/W
PITC
0000_0000_0000_0000
R/W
Addr
16
31
Field
Reset
R/W
—
0000_0000_0000_0000
R/W
0x10246
Addr
Figure 4-39. Periodic interrupt Timer Count Register (PITC)
Table 4-22 describes PITC fields.
Table 4-22. PITC Field Descriptions
Description
Bits Name
0–15 PITC Periodic interrupt timing count. Bits 0–15 are defined as the PITC, which contains the count for the
periodic timer. Setting PITC to 0xFFFF selects the maximum count period.
16–31
—
Reserved, should be cleared.
4.3.3.3
Periodic Interrupt Timer Register (PITR)
The periodic interrupt timer register (PITR), shown in Figure 4-40, is a read-only register that shows the
current value in the periodic interrupt down counter. The PITR counter is not affected by reads or writes
to it.
0
15
Field
Reset
R/W
PIT
0000_0000_0000_0000
Read Only
Addr
16
31
Field
Reset
R/W
—
0000_0000_0000_0000
Read Only
0x1024A
Addr
Figure 4-40. Periodic Interrupt Timer Register (PITR)
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Freescale Semiconductor
4-47
System Interface Unit (SIU)
Table 4-23 describes PITR fields.
Table 4-23. PITR Field Descriptions
Description
Bits
Name
0–15
PITC Periodic interrupt timing count. Bits 0–15 are defined as the PIT. It contains the current count
remaining for the periodic timer. Writes have no effect on this field.
16–31
—
Reserved, should be cleared.
4.3.4
PCI Control Registers
NOTE
This section applies only to the MPC8250, the MPC8265, and the
MPC8266.
Two pairs of registers detect accesses from the 60x bus side to the PCI bridge (other than PCI internal
registers accesses). Each pair consists of a PCI base register (PCIBRx) for comparing addresses and a
corresponding PCI mask register (PCIMSKx).
4.3.4.1
PCI Base Register (PCIBRx)
Figure 4-41 shows the PCI base register.
0
15
Field
BA
0000_0000_0000_0000
R/W
Reset
R/W
Addr
0x101AC (PCIBR0); 0x101B0 (PCIBR1)
16
17
30
31
—
0000_0000_0000_0000
R/W
Field BA
V
Reset
R/W
Addr
0x101AE (PCIBR0); 0x101B2 (PCIBR1)
Figure 4-41. PCI Base Registers (PCIBRx)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
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Freescale Semiconductor
System Interface Unit (SIU)
Table 4-24. PCIBRx Field Descriptions
Bits
Name
Description
0–16
BA
Base Address. The upper 17 bits of each base address register are compared to the address on the
60x bus address bus to determine if the access should be claimed by the PCI bridge. Used with
PCIMSKx[AM]
17–30
31
—
V
Reserved. Should be cleared.
Valid bit. Indicates that the contents of the PCIBRx and PCIMSKx pairs are valid.
0 This pair is invalid
1 This pair is valid
4.3.4.2
PCI Mask Register (PCIMSKx)
Figure 4-42 shows the PCI mask register.
0
15
Field
AM
0000_0000_0000_0000
R/W
Reset
R/W
Addr
0x101C4 (PCIBR0); 0x101C8 (PCIBR1)
16
17
31
Field AM
—
0000_0000_0000_0000
R/W
Reset
R/W
Addr
0x101C6 (PCIBR0); 0x101CA (PCIBR1)
Figure 4-42. PCI Mask Register (PCIMSKx)
Table 4-25. PCIMSKx Field Descriptions
Bits
Name
Description
31–17
16–0
—
Reserved. Should be cleared.
AM
Address Mask. Masks corresponding PCIBRx bits.
0 Corresponding address bits are masked.
1 Corresponding address bits are compared.
4.4
SIU Pin Multiplexing
Some functions share pins. The actual pinout of the PowerQUICC II is shown in the hardware
specifications. The control of the actual functionality used on a specific pin is shown in Table 4-26.
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Freescale Semiconductor
4-49
System Interface Unit (SIU)
Table 4-26. SIU Pins Multiplexing Control
Pin Configuration Control
Pin Name
GBL/IRQ1
CI/BADDR29/IRQ2
WT/BADDR30/IRQ3
L2_HIT/IRQ4
Controlled by SIUMCR programming see Section 4.3.2.6, “SIU Module
CPU_BG/BADDR31/IRQ5
ABB/IRQ2
DBB/IRQ3
NC/DP0/RSRV/EXT_BR2
IRQ1/DP1/EXT_BG2
IRQ2/DP2/TLBISYNC/EXT_DBG2
IRQ3/DP3/CKSTP_OUT/EXT_BR3
IRQ4/DP4/CORE_SRESET/EXT_BG3
IRQ5/DP5/TBEN/EXT_DBG3
IRQ6/DP6/CSE0
IRQ7/DP7/CSE1
CS[10]/BCTL1
CS[11]/AP[0]
PCI_PAR/L_A14
SMI/PCI_FRAME/L_A15
PCI_TRDY/L_A16
CKSTOP_OUT/PCI_IRDY/L_A17
PCI_STOP/L_A18
PCI_DEVSEL/L_A19
PCI_IDSEL/L_A20
PCI_PERR/L_A21
PCI_SERR/L_A22
PCI_REQ0/L_A23
PCI_REQ1/L_A24
PCI_GNT0/L_A25
PCI_GNT1/L_A26
PCI_CLK/L_A27
CORE_SRESET/PCI_RST/L_A28
PCI_INTA/L_A29
PCI_REQ2/L_A30
AD[0–31]/LCL_D[0–31]
C/BE[0–3]/LCL_DP[0–3]
BNKSEL[0]/TC[0]/AP[1]/MODCK1
BNKSEL[1]/TC[1]/AP[2]/MODCK2
BNKSEL[2]/TC[2]/AP[3]/MODCK3
PWE[0–7]/PSDDQM[0–7]/PBS[0–7]
PSDA10/PGPL0
Controlled dynamically according to the specific memory controller
machine that handles the current bus transaction.
PSDWE/PGPL1
POE/PSDRAS/PGPL2
PSDCAS/PGPL3
PGTA/PUPMWAIT/PGPL4/PPBS
PSDAMUX/PGPL5
LBS[0–3]/LSDDQM[0–3]/LWE[0–3]
LGPL0/LSDA10
LGPL1/LSDWE
LGPL2/LSDRAS/LOE
LGPL3/LSDCAS
LPBS/LGPL4/LUPMWAIT/LGTA
LGPL5/LSDAMUX
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Chapter 5
Reset
The PowerQUICC II has several inputs to the reset logic:
•
•
•
•
•
•
•
Power-on reset (PORESET)
External hard reset (HRESET)
External soft reset (SRESET)
Software watchdog reset
Bus monitor reset
Checkstop reset
JTAG reset
All of these reset sources are fed into the reset controller and, depending on the source of the reset, different
actions are taken. The reset status register, described in Section 5.2, “Reset Status Register (RSR),”
indicates the last sources to cause a reset.
5.1
Reset Causes
Table 5-1 describes reset causes.
Table 5-1. Reset Causes
Description
Name
Power-on reset
(PORESET)
Input pin. Asserting this pin initiates the power-on reset flow that resets all the chip and
configures various attributes of the chip including its clock mode.
Hard reset (HRESET)
Soft reset (SRESET)
Software watchdog reset
This is a bidirectional I/O pin. The PowerQUICC II can detect an external assertion of
HRESET only if it occurs while the PowerQUICC II is not asserting reset. During
HRESET, SRESET is asserted. HRESET is an open-collector pin.
Bidirectional I/O pin. The PowerQUICC II can only detect an external assertion of
SRESET if it occurs while the PowerQUICC II is not asserting reset. SRESET is an
open-drain pin.
After the PowerQUICC II’s watchdog counts to zero, a software watchdog reset is
signaled. The enabled software watchdog event then generates an internal hard reset
sequence.
Bus monitor reset
Checkstop reset
After the PowerQUICC IIs bus monitor counts to zero, a bus monitor reset is asserted.
The enabled bus monitor event then generates an internal hard reset sequence.
If the core enters checkstop state and the checkstop reset is enabled (RMR[CSRE] = 1),
the checkstop reset is asserted. The enabled checkstop event then generates an internal
hard reset sequence.
JTAG reset
When JTAG logic asserts the JTAG soft reset signal, an internal soft reset sequence is
generated.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
5-1
Reset
5.1.1
Reset Actions
The reset block has a reset control logic that determines the cause of reset, synchronizes it if necessary, and
resets the appropriate logic modules. The memory controller, system protection logic, interrupt controller,
and parallel I/O pins are initialized only on hard reset. Soft reset initializes the internal logic while
maintaining the system configuration. Because there is no soft nor hard reset in the 603e core, asserting
external SRESET generates a reset to the 603e core and a soft reset to the remainder of the device, The
impact on the given application is the reset to the core resets the MSR[IP] to the value in the HRCW[CIP],
Table 5-2 identifies reset actions for each reset source.
Table 5-2. Reset Actions for Each Reset Source
Reset Logic
and PLL
States
System
Configuratio
n
Clock
Module
Reset
Other
Internal
Logic Reset
HRESET
Driven
SRESET
Driven
Core
Reset
Reset Source
1
Reset
Sampled
Power-on reset
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
External hard reset
Software watchdog
Bus monitor
Checkstop
JTAG reset
No
No
No
No
Yes
Yes
Yes
External soft reset
1
Includes all other CPM and core logic not explicitly noted elsewhere in the table.
5.1.2
Power-On Reset Flow
Assertion of the PORESET external pin initiates the power-on reset flow. PORESET should be asserted
externally for at least 16 input clock cycles after external power to the chip reaches at least 2/3 Vcc. The
value driven on RSTCONF while PORESET changes from assertion to negation determines the chip
configuration. If RSTCONF is negated (driven high) while PORESET changes, the chip acts as a
configuration slave. If RSTCONF is asserted while PORESET changes, the chip acts as a configuration
‘configuration master’ and ‘configuration slave.’
Directly after the negation of PORESET and choice of the reset operation mode as configuration master
or configuration slave, the PowerQUICC II starts the configuration process. The PowerQUICC II asserts
HRESET and SRESET throughout the power-on reset process, including configuration. Configuration
takes 1,024 CLOCKIN cycles, after which MODCK[1–3] are sampled to determine the chips working
mode. Next the PowerQUICC II halts until the main PLL locks. As described in Section 10.2, “Clock
(MODCK[4–7]) taken from the reset configuration word. The main PLL lock can take up to 200 µs
depending on the specific chip. During this time HRESET and SRESET are asserted. When the main PLL
is locked, the clock block starts distributing clock signals in the chip. HRESET remains asserted for
another 512 clocks and is then released. The SRESET is released three clocks later.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
5-2
Freescale Semiconductor
Reset
Figure 5-4 shows the power-on reset flow.
External
pin is
asserted
for min 16
PORESET
Input
RSTCONF is sampled for
master determination
PORESET
Internal
MODCK[1–3] are
sampled. MODCK_HI
bits are ready for PLL
HRESET
Output
PLL is locked (no
external indication)
SRESET
Output
PLL locking period
HRESET /SRESET are
extended for 512/515
CLKIN (respectively), from
PLL lock time.
PORESET to internal logic is
extended for 1024 CLKIN.
Interval depends on
PLL locking time.
In reset configuration mode:
reset configuration
sequence occurs in this
period.
Figure 5-1. Power-on Reset Flow
5.1.3
HRESET Flow
The HRESET flow may be initiated externally by asserting HRESET or internally when the chip detects
a reason to assert HRESET. In both cases the chip continues asserting HRESET and SRESET throughout
the HRESET flow. The HRESET flow begins with the hard reset configuration sequence, which
configures the chip as explained in Section 5.4, “Reset Configuration.” After the chip asserts HRESET and
SRESET for 1,024 input clock cycles, it releases both signals and exits the HRESET flow. An external
pull-up resistor should negate the signals. After negation is detected, a 16-cycle period is taken before
testing the presence of an external (hard/soft) reset.
5.1.4
SRESET Flow
The SRESET flow may be initiated externally by asserting SRESET or internally when the chip detects a
cause to assert SRESET. In both cases the chip asserts SRESET for 512 input clock cycles, after which the
chip releases SRESET and exits the SRESET flow. An external pull-up resistor should negate SRESET;
after negation is detected, a 16-cycle period is taken before testing the presence of an external (hard/soft)
reset. While SRESET is asserted, internal hardware is reset but hard reset configuration does not change.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
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5-3
Reset
5.2
Reset Status Register (RSR)
register map.
0
15
Field
R/W
—
R/W
Reset
Addr
0000_0000_0000_0000
16
25
26
27
28
29
30
31
Field
R/W
—
JTRS CSRS SWRS BMRS ESRS EHRS
R/W
Reset
Addr
0000_0000_0000_0011
0x10C92
Figure 5-2. Reset Status Register (RSR)
Table 5-3 describes RSR fields.
Table 5-3. RSR Field Descriptions
Function
Bits
Name
0–25
26
—
Reserved, should be cleared.
JTRS JTAG reset status. When the JTAG reset request is set, JTRS is set and remains set until software
clears it. JTRS is cleared by writing a 1 to it (writing zero has no effect).
0 No JTAG reset event occurred
1 A JTAG reset event occurred
27
28
29
CSRS Check stop reset status. When the core enters a checkstop state and the checkstop reset is enabled
by the RMR[CSRE], CSRS is set and it remains set until software clears it. CSRS is cleared by
writing a 1 to it (writing zero has no effect).
0 No enabled checkstopreset event occurred
1 An enabled checkstopreset event occurred
SWRS Software watchdog reset status. When a software watchdog expire event (which causes a reset) is
detected, the SWRS bit is set and remains that way until the software clears it. SWRS is cleared by
writing a 1 to it (writing zero has no effect).
0 No software watchdog reset event occurred
1 A software watchdog reset event has occurred
BMRS Bus monitor reset status. When a bus monitor expire event (which causes a reset) is detected,
BMRS is set and remains set until the software clears it. BMRS can be cleared by writing a 1 to it
(writing zero has no effect).
0 No bus monitor reset event has occurred
1 A bus monitor reset event has occurred
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Reset
Table 5-3. RSR Field Descriptions (continued)
Function
Bits
Name
30
ESRS External soft reset status. When an external soft reset event is detected, ESRS is set and it remains
that way until software clears it. ESRS is cleared by writing a 1 to it (writing zero has no effect).
0 No external soft reset event has occurred
1 An external soft reset event has occurred
31
EHRS External hard reset status. When an external hard reset event is detected, EHRS is set and it
remains set until software clears it. EHRS is cleared by writing a 1 (writing zero has no effect).
0 No external hard reset event has occurred
1 An external hard reset event has occurred
NOTE
The Reset Status Register accumulates reset events. For example, because
software watchdog expiration results in a hard reset, which in turn results in
a soft reset, RSR[SWRS], RSR[ESRS] and RSR[EHRS] are all set after a
software watchdog reset.
5.3
Reset Mode Register (RMR)
0
15
Field
R/W
—
R/W
Reset
Addr
0000_0000_0000_0000
16
30
31
Field
R/W
—
CSRE
R/W
0000_0000_0000_0000
Reset
Addr
0x10C96
Figure 5-3. Reset Mode Register (RMR)
Table 5-4 describes RMR fields.
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5-5
Reset
Table 5-4. RMR Field Descriptions
Function
Bits Name
0–30
31
—
Reserved, should be cleared.
CSRE Checkstop reset enable. The core can enter checkstop mode as the result of several exception
conditions. Setting CSRE configures the chip to perform a hard reset sequence whenever the core
enters checkstop state.
0 Reset not generated when core enters checkstop state.
1 Reset generated when core enters checkstop state.
Note: When the core is disabled, CSRE must be cleared.
5.4
Reset Configuration
Various features may be configured during hard reset or power-on reset. For example, one configurable
features is core disable, which can be used to configure a system that uses two PowerQUICC IIs, one a
slave device and the other a the host with an active core. Most configurable features are reconfigured
whenever HRESET is asserted. However, the clock mode is configured only when PORESET is asserted.
The 32-bit hard reset configuration word is described in Section 5.4.1, “Hard Reset Configuration Word.”
The reset configuration sequence is designed to support a system that uses up to eight PowerQUICC II
chips, each configured differently. It needs no additional glue logic for reset configuration.
The description below explains the operation of this sequence with regard to a multiple-PowerQUICC II
system. This and other simpler systems are described in Section 5.4.2, “Hard Reset Configuration
configuration master while all other PowerQUICC IIs should act as configuration slaves. The
configuration master in the system typically reads the various configuration words from EPROM in the
system and uses them to configure itself as well as the configuration slaves. How the PowerQUICC II acts
during reset configuration is determined by the value of the RSTCONF input while PORESET changes
from assertion to negation. If RSTCONF is asserted while PORESET changes, PowerQUICC II is a
configuration master; otherwise, it is a slave.
In a typical multiple-PowerQUICC II system, RSTCONF input of the configuration master should be hard
wired to ground, while RSTCONF inputs of other chips should be connected to the high-order address bits
Table 5-5. RSTCONF Connections in Multiple-PowerQUICC II Systems
Configured Device
Configuration master
RSTCONF Connection
GND
A0
First configuration slave
Second configuration slave
Third configuration slave
Fourth configuration slave
Fifth configuration slave
A1
A2
A3
A4
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Reset
Table 5-5. RSTCONF Connections in Multiple-PowerQUICC II Systems (continued)
Configured Device
RSTCONF Connection
Sixth configuration slave
A5
A6
Seventh configuration slave
The configuration words for all PowerQUICC IIs are assumed to reside in an EPROM connected to CS0
of the configuration master. Because the port size of this EPROM is not known to the configuration master,
before reading the configuration words, the configuration master reads all configuration words
byte-by-byte only from locations that are independent of port size.
Table 5-6. shows addresses that should be used to configure the various PowerQUICC IIs. Byte addresses
that do not appear in this table have no effect on the configuration of the PowerQUICC II chips. The values
.
Table 5-6. Configuration EPROM Addresses
Configured Device
Configuration master
Byte 0 Address
Byte 1 Address
Byte 2 Address
Byte 3 Address
0x00
0x20
0x40
0x60
0x80
0xA0
0xC0
0xE0
0x08
0x28
0x48
0x68
0x88
0xA8
0xC8
0xE8
0x10
0x30
0x50
0x70
0x90
0xB0
0xD0
0xF0
0x18
0x38
0x58
0x78
0x98
0xB8
0xD8
0xF8
First configuration slave
Second configuration slave
Third configuration slave
Fourth configuration slave
Fifth configuration slave
Sixth configuration slave
Seventh configuration slave
The configuration master first reads a value from address 0x00 then reads a value from addresses 0x08,
0x10, and 0x18. These four bytes are used to form the configuration word of the configuration master,
which then proceeds reading the bytes that form the configuration word of the first slave device. The
configuration master drives the whole configuration word on D[0–31] and toggles its A0 address line.
Each configuration slave uses its RSTCONF input as a strobe for latching the configuration word during
HRESET assertion time. Thus, the first configuration slave whose RSTCONF input is connected to
configuration master’s A0 output latches the word driven on D[0–31] as its configuration word. In this way
the configuration master continues to configure all PowerQUICC II chips in the system. The configuration
master always reads eight configuration words regardless of the number of PowerQUICC II parts in the
system. In a simple system that uses one stand-alone PowerQUICC II, it is possible to use the default hard
reset configuration word (all zeros). This is done by tying RSTCONF input to VCC. Another scenario may
be a system which has no boot EPROM. In this case the user can configure the PowerQUICC II as a
configuration slave by driving RSTCONF to 1 during PORESET assertion and then applying a negative
pulse on RSTCONF and an appropriate configuration word on D[0–31]. In such a system, asserting
HRESET in the middle of operation causes the PowerQUICC II to return to the configuration programmed
after PORESET assertion (not the default configuration represented by configuration word of all zeros).
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5-7
Reset
5.4.1
Hard Reset Configuration Word
0
1
2
3
4
5
6
7
8
9
10
11
12
13
15
31
Field EARB EXMC CDIS EBM
Reset
BPS
CIP ISPS
L2CPC
DPPC
—
ISB
0000_0000_0000_0000
16
17
18
19
20
21
22
23
24
25
26
27
28
1
Field BMS
BBD
MMR
LBPC
APPC
CS10PC ALD_EN
—
MODCK_H
Reset
0000_0000_0000_0000
1
MPC8250, MPC8265, and MPC8266 only. Reserved on all other devices.
Figure 5-4. Hard Reset Configuration Word
Table 5-7 describes hard reset configuration word fields.
Table 5-7. Hard Reset Configuration Word Field Descriptions
Bits
Name
Description
1
0
EARB
External arbitration. Defines the initial value for ACR[EARB]. If EARB = 1, external arbitration is
1
2
EXMC
External MEMC. Defines the initial value of BR0[EMEMC]. If EXMC = 1, an external memory
1
CDIS
Core disable. Defines the initial value for the SIUMCR[CDIS].
1 The core is disabled. In this mode the PowerQUICC II functions as a slave.
1
3
EBM
External bus mode. Defines the initial value of BCR[EBM]. See Section 4.3.2.1, “Bus
4–5
BPS
Boot port size. Defines the initial value of BR0[PS], the port size for memory controller bank 0.
00 64-bit port size
01 8-bit port size
10 16-bit port size
11 32-bit port size
1
6
7
CIP
Core initial prefix. Defines the initial value of MSR[IP]. Exception prefix. The setting of this bit
specifies whether an exception vector offset is prepended with Fs or 0s. In the following
description, nnnnn is the offset of the exception vector.
0 MSR[IP] = 1 (default). Exceptions are vectored to the physical address 0xFFFn_nnnn
1 MSR[IP] = 0 Exceptions are vectored to the physical address 0x000n_nnnn.
1
ISPS
Internal space port size. Defines the initial value of BCR[ISPS]. Setting ISPS configures the
PowerQUICC II to respond to accesses from a 32-bit external master to its internal space. See
1
8–9
10–11
12
L2CPC
L2 cache pins configuration. Defines the initial value of SIUMCR[L2CPC]. See Section 4.3.2.6,
1
DPPC
—
Data parity pin configuration. Defines the initial value of SIUMCR[DPPC]. For more details refer
Reserved, should be cleared.
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Reset
Table 5-7. Hard Reset Configuration Word Field Descriptions (continued)
Bits
Name
Description
13–15
ISB
Initial internal space base select. Defines the initial value of IMMR[0–14] and determines the
base address of the internal memory space.
000 0x0000_0000
001 0x00F0_0000
010 0x0F00_0000
011 0x0FF0_0000
100 0xF000_0000
101 0xF0F0_0000
110 0xFF00_0000
111 0xFFF0_0000
16
BMS
Boot memory space. Defines the initial value for BR0[BA]. There are two possible boot memory
regions: HIMEM and LOMEM.
0 0xFE00_0000—0xFFFF_FFFF
1 0x0000_0000—0x01FF_FFFF
1
17
BBD
Bus busy disable. Defines the initial value of SIUMCR[BBD]. See Section 4.3.2.6, “SIU Module
18–19
20–21
MMR
Mask masters requests. Defines the initial value of SIUMCR[MMR]. See Section 4.3.2.6, “SIU
1
LBPC
Local bus pin configuration. Defines the value of SIUMCR[LBPC]. See Section 4.3.2.6, “SIU
00 Local bus pins function as local bus
01 Local bus pins function as PCI bus (MPC8250, MPC8265, and MPC8266 only)
10 Local bus pins function as core pins
11 Reserved
1
22–23
APPC
Address parity pin configuration. Defines the initial value of SIUMCR[APPC]. See
1
24–25 CS10PC
CS10 pin configuration. Defines the initial value of SIUMCR[CS10PC]. See Section 4.3.2.6,
Note: During the reset configuration sequence, the BCTL1/CS10 pin toggles like POE of the 60x
bus GPCM, regardless of the configuration of the reset configuration word. After the reset
configuration sequence, the BCTL1/CS10 pin behaves according to the configuration of
SIUMCR[CS10PC].
26
27
—
Reserved, should be cleared.
ALD_EN
MPC8250, MPC8265, and MPC8266 only: CP auto load enable. Allows the CP to automatically
load the essential PCI configuration registers from the EEPROM during reset.
0 CP auto load is disabled.
1 CP auto load is enabled.
—
Reserved, should be cleared.
28–31 MODCK_H High-order bits of the MODCK bus, which determine the clock reset configuration. See
Note: MPC8250, MPC8265, and MPC8266 only: If the device is configured to PCI mode
(PCI_MODE is driven low), this field has no effect and the value for MODCK_H is loaded
directly from the MODCK_H pins. Note that the value of the MODCK_H bits are derived
from the dedicated PCI_MODCK_H[0:3] pins when operating in PCI mode.
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5-9
Reset
1
The user should exercise caution when changing this bit. This bit has an immediate effect on the external bus and
may result in unstable system operation.
5.4.2
Hard Reset Configuration Examples
This section presents some examples of hard reset configurations in different systems.
5.4.2.1 Single PowerQUICC II with Default Configuration
This is the simplest configuration scenario. It can be used if the default values achieved by clearing the
hard reset configuration word are desired. This is applicable only for systems using single-PowerQUICC
II bus mode (as opposed to 60x bus mode). To enter this mode, tie RSTCONF to V as shown in
CC
Figure 5-5. The PowerQUICC II does not access the boot EPROM; it is assumed that the default
configuration is used upon exiting hard reset.
PORESET
Vcc
Configuration
Slave Chip
HRESET
A[0–31]
D[0–31]
Vcc
PORESET
RSTCONF
Figure 5-5. Single Chip with Default Configuration
5.4.2.2
Single PowerQUICC II Configured from Boot EPROM
For a configuration that differs from the default, the PowerQUICC II can be used as a configuration master
It is assumed the configuration is as defined there upon exiting hard reset.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
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Reset
PORESET
VCC
EPROM Control Signals
Boot EPROM
Configuration Master Chip
A[0–31]
A[..]
D[0–7]
HRESET
D[0–31]
PORESET
RSTCONF
Figure 5-6. Configuring a Single Chip from EPROM
5.4.2.3
Multiple PowerQUICC IIs Configured from Boot EPROM
For a complex system with multiple PowerQUICC II devices that may each be configured differently,
configuration is done by assigning one configuration master and multiple configuration slaves. The
PowerQUICC II that controls the boot EPROM should be the configuration master—RSTCONF tied to
GND. The RSTCONF inputs of the other PowerQUICC II devices are tied to the address bus lines, thus
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
5-11
Reset
PORESET
VCC
EPROM Control Signals
Boot EPROM
Configuration Master Chip
A[0–31]
A[..]
D[0–7]
HRESET
D[0–31]
PORESET
RSTCONF
Configuration Slave Chip 1
HRESET
D[0–31]
PORESET
RSTCONF
A0
Configuration Slave Chip 2
HRESET
D[0–31]
PORESET
RSTCONF
A1
Configuration Slave Chip 7
HRESET
PORESET
D[0–31]
RSTCONF
A6
Figure 5-7. Configuring Multiple Chips
In this system, the configuration master initially reads its own configuration word. It then reads other
configuration words and drives them to the configuration slaves by asserting RSTCONF. As Figure 5-7
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
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Reset
shows, this complex configuration is done without additional glue logic. The configuration master controls
the whole process by asserting the EPROM control signals and the system’s address signals as needed.
5.4.2.4
Multiple PowerQUICC IIs in a System with No EPROM
In some cases, the configuration master capabilities of the PowerQUICC II cannot be used. This can
happen for example if there is no boot EPROM in the system or the boot EPROM is not controlled by an
PowerQUICC II.
If this occurs, the user must do one of the following:
•
•
Accept the default configuration,
Emulate the configuration master actions in external logic (where the PowerQUICC II is a
configuration slave).
•
The external hardware should be connected to all RSTCONF pins of the different devices and to
the upper 32 bits of the data bus. During PORESET, the rising edge the external hardware should
negate all RSTCONF inputs to put all of the devices in their configuration slave mode. For 1,024
clocks after PORESET negation, the external hardware can configure the different devices by
driving appropriate configuration words on the data bus and asserting RSTCONF for each device
to strobe the data being received.
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Reset
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
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Part III
The Hardware Interface
Intended Audience
Part III is intended for system designers who need to understand how each PowerQUICC II signal works
and how those signals interact.
Contents
Part III describes external signals, clocking, memory control, and power management of the
PowerQUICC II.
It contains the following chapters:
•
PowerQUICC II signals.
•
•
•
PowerQUICC II.
•
•
bridge PCI agents to a host processor that implements the PowerPC architecture and how it is
compliant with PCI Specification Revision 2.2.
of eight memory banks shared between a general-purpose chip-select machine (GPCM) and three
user-programmable machines (UPMs).
•
•
configuration of a level-2 cache.
port (TAP), which is fully compatible with the IEEE 1149.1 Standard Test Access Port and
Boundary Scan Architecture.
Suggested Reading
This section lists additional reading that provides background for the information in this manual as well as
general information about the PowerPC architecture.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
III-1
MPC82xx Documentation
Supporting documentation for the PowerQUICC II can be accessed through the world-wide web at
www.freescale.com. This documentation includes technical specifications, reference materials, and
detailed applications notes.
Conventions
This document uses the following notational conventions:
Bold entries in figures and tables showing registers and parameter RAM should
be initialized by the user.
Bold
mnemonics
Instruction mnemonics are shown in lowercase bold.
Italics indicate variable command parameters, for example, bcctrx.
Book titles in text are set in italics.
italics
0x0
Prefix to denote hexadecimal number
0b0
Prefix to denote binary number
REG[FIELD]
Abbreviations or acronyms for registers or buffer descriptors are shown in
uppercase text. Specific bits, fields, or numerical ranges appear in brackets. For
example, MSR[LE] refers to the little-endian mode enable bit in the machine state
register.
x
In certain contexts, such as in a signal encoding or a bit field, indicates a don’t
care.
n
¬
&
|
Indicates an undefined numerical value
NOT logical operator
AND logical operator
OR logical operator
Acronyms and Abbreviations
Table i contains acronyms and abbreviations used in this document. Note that the meanings for some
acronyms (such as SDR1 and DSISR) are historical, and the words for which an acronym stands may not
be intuitively obvious.
Table III-1. Acronyms and Abbreviated Terms
Term
Meaning
BD
Buffer descriptor
BIST
BRI
Built-in self test
Basic rate interface
Content-addressable memory
CAM
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Table III-1. Acronyms and Abbreviated Terms (continued)
Meaning
Term
CPM
Communications processor module
Cyclic redundancy check
CRC
DMA
Direct memory access
DPLL
DRAM
DSISR
EA
Digital phase-locked loop
Dynamic random access memory
Register used for determining the source of a DSI exception
Effective address
EEST
GCI
Enhanced Ethernet serial transceiver
General circuit interface
GPCM
HDLC
General-purpose chip-select machine
High-level data link control
Inter-integrated circuit
2
I C
IDL
Inter-chip digital link
IEEE
IrDA
ISDN
JTAG
LIFO
LRU
LSB
Institute of Electrical and Electronics Engineers
Infrared Data Association
Integrated services digital network
Joint Test Action Group
Last-in-first-out
Least recently used
Least-significant byte
lsb
Least-significant bit
LSU
MAC
MMU
MSB
msb
Load/store unit
Multiply accumulate
Memory management unit
Most-significant byte
Most-significant bit
MSR
NMSI
OSI
Machine state register
Nonmultiplexed serial interface
Open systems interconnection
Peripheral component interconnect
Personal Computer Memory Card International Association
PCI
PCMCIA
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III-3
Table III-1. Acronyms and Abbreviated Terms (continued)
Meaning
Term
PRI
Primary rate interface
Rx
Receive
SCC
SCP
SDLC
SDMA
SI
Serial communications controller
Serial control port
Synchronous data link control
Serial DMA
Serial interface
SIU
System interface unit
SMC
SNA
SPI
Serial management controller
Systems network architecture.
Serial peripheral interface
Special-purpose register
Static random access memory
Time-division multiplexed
Translation lookaside buffer
Time-slot assigner
SPR
SRAM
TDM
TLB
TSA
Tx
Transmit
UART
UISA
UPM
USART
Universal asynchronous receiver/transmitter
User instruction set architecture
User-programmable machine
Universal synchronous/asynchronous receiver/transmitter
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Chapter 6
External Signals
This chapter describes the external signals. A more detailed description of 60x bus signals is provided in
6.1
Functional Pinout
Figure 6-1 shows PowerQUICC II signals grouped by function. Note that many signals are multiplexed
and this figure does not indicate how these signals are multiplexed.
NOTE
A bar over a signal name indicates that the signal is active low—for
example, BB (bus busy). Active-low signals are referred to as asserted
(active) when they are low and negated when they are high. Signals that are
not active low, such as TSIZ[0–1] (transfer size signals) are referred to as
asserted when they are high and negated when they are low.
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6-1
External Signals
VCCSYN/GNDSYN/VCCSYN1//VDDH/
⎯⎯⎯>100
32 <⎯⎯> A[0–31]
VDD/VSS
PCI_PAR1/L_A14
<⎯⎯>
<⎯⎯>
<⎯⎯>
<⎯⎯>
<⎯⎯>
<⎯⎯>
<⎯⎯>
<⎯⎯>
<⎯⎯>
<⎯⎯>
<⎯⎯>
<⎯⎯>
<⎯⎯⎯
<⎯⎯>
<⎯⎯>
<⎯⎯>
<⎯⎯>
<⎯⎯>
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
5
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
<⎯⎯> TT[0–4]
<⎯⎯> TSIZ[0–3]
<⎯⎯> TBST
SMI/PCI_FRAME1/L_A15
PCI_TRDY1/L_A16
CKSTOP_OUT/PCI_IRDY1/L_A17
PCI_STOP1/L_A18
<⎯⎯> GBL/IRQ1
<⎯⎯> CI/BADDR29/IRQ2
<⎯⎯> WT/BADDR30/IRQ3
<⎯⎯⎯ L2_HIT/IRQ4
<⎯⎯> CPU_BG/BADDR31/IRQ5
⎯⎯⎯> CPU_DBG
⎯⎯⎯> CPU_BR
<⎯⎯> BR
<⎯⎯> BG
<⎯⎯> ABB/IRQ2
<⎯⎯> TS
<⎯⎯> AACK
PCI_DEVSEL1/L_A19
L
O
C
A
L
PCI_IDSEL1/L_A20
PCI_PERR1/L_A21
PCI_SERR/1L_A22
PCI_REQ01/L_A23
CPCI_HS_ES1/PCI_REQ11/L_A24
PCI_GNT01/L_A25
6
0
x
CPCI_HS_LED1/PCI_GNT11/L_A26
CPCI_HS_ENUM1/GNT21/L_A27
CORE_SRESET/PCI_RST1/L_A28
PCI_INTA1/L_A29
B
U
S
<⎯⎯> ARTRY
<⎯⎯> DBG
<⎯⎯> DBB/IRQ3
PCI_REQ21/L_A30
B
U
S
DLLOUT1/L_A31
PCI_AD[31-0]1/LCL_D[0–31]
PCI_C/BE[3-0]1/LCL_DP[0–3]
<⎯⎯> 32
64 <⎯⎯> D[0–63]
<⎯⎯>
4
1
1
1
<⎯⎯> NC/DP0/RSRV/EXT_BR2
<⎯⎯> IRQ1/DP1/EXT_BG2
<⎯⎯> IRQ2/DP2/TLBISYNC/EXT_DBG2
PCI_CFG[3–0]1/LBS[0–3]/
<⎯⎯⎯
4
1
<⎯⎯> IRQ3/DP3/CKSTP_OUT/EXT_BR3
LSDDQM[0–3]/LWE[0–3]
PCI_MODCK_H01/LGPL0/LSDA10
PCI_MODCK_H11/LGPL1/LSDWE
PCI_MODCK_H21/LGPL2/LSDRAS/LOE
PCI_MODCK_H31/LGPL3/LSDCAS
<⎯⎯⎯
<⎯⎯⎯
<⎯⎯⎯
<⎯⎯⎯
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
<⎯⎯> IRQ4/DP4/CORE_SRESET/EXT_BG3
<⎯⎯> IRQ5/DP5/TBEN/EXT_DBG3
<⎯⎯> IRQ6/DP6/CSE0
<⎯⎯> IRQ7/DP7/CSE1
<⎯⎯> PSDVAL
<⎯⎯> TA
<⎯⎯> TEA
<⎯⎯> IRQ0/NMI_OUT
<⎯⎯> IRQ7/INT_OUT/APE
M
E
M
C
LPBS/LGPL4/LUPMWAIT/LGTA <⎯⎯>
<⎯⎯>
LWR <⎯⎯>
PCI_MODCK1/LGPL5
PA[0–31] <⎯⎯> 32
PB[4–31] <⎯⎯> 28
PC[0–31] <⎯⎯> 32
PD[4–31] <⎯⎯> 28
P
I
O
10 ⎯⎯⎯> CS[0–9]
1
1
2
1
1
8
1
1
1
1
1
1
1
1
1
1
1
<⎯⎯> CS[10]/BCTL1
<⎯⎯> CS[11]/AP[0]
⎯⎯⎯> BADDR[27–28]
⎯⎯⎯> ALE
1
⎯⎯⎯> 1
PCI_RST /PORESET
M
E
M
C
RSTCONF⎯⎯⎯> 1
⎯⎯⎯> BCTL0
HRESET<⎯⎯>
1
1
⎯⎯⎯> PWE[0–7]/PSDDQM[0–7]/PBS[0–7]
⎯⎯⎯> PSDA10/PGPL0
⎯⎯⎯> PSDWE/PGPL1
⎯⎯⎯> POE/PSDRAS/PGPL2
⎯⎯⎯> PSDCAS/PGPL3
<⎯⎯> PGTA/PUPMWAIT/PGPL4/PPBS
⎯⎯⎯> PSDAMUX/PGPL5
<⎯⎯− TMS
R
S
T
SRESET<⎯⎯>
QREQ<⎯⎯⎯ 1
XFC⎯⎯⎯> 1
CLKIN1⎯⎯⎯> 1
TRIS⎯⎯⎯> 1
C
L
K
BNKSEL[0]/TC[0]/AP[1]/MODCK1<⎯⎯>
BNKSEL[1]/TC[1]/AP[2]/MODCK2<⎯⎯>
BNKSEL[2]/TC[2]/AP[3]/MODCK3<⎯⎯>
1
1
1
J
T
A
G
<⎯⎯⎯ TDI
<⎯⎯− TCK
<⎯⎯− TRST
−⎯⎯> TDO
PCI_MODE2
⎯⎯⎯> 1
⎯⎯⎯> 1
CLKIN22
NC ⎯⎯⎯> 2
1
2
MPC8250, MPC8265, and MPC8266 only.
MPC8250, MPC8265, and MPC8266 only. This is a spare pin on all other devices.
Figure 6-1. PowerQUICC II External Signals
6.2
Signal Descriptions
The PowerQUICC II system bus, shown in Table 6-1, consists of all the signals that interface with the
external bus. Many of these pins perform different functions, depending on how the user assigns them.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
6-2
Freescale Semiconductor
External Signals
Table 6-1. External Signals
Description
Signal
BR
60x bus request—This is an output when an external arbiter is used and an input when an internal
arbiter is used. As an output the PowerQUICC II asserts this pin to request ownership of the 60x
bus. As an input an external master should assert this pin to request 60x bus ownership from the
internal arbiter.
BG
60x bus grant—This is an output when an internal arbiter is used and an input when an external
arbiter is used. As an output the PowerQUICC II asserts this pin to grant 60x bus ownership to an
external bus master. As an input the external arbiter should assert this pin to grant 60x bus
ownership to the PowerQUICC II.
ABB
60x address bus busy—(Input/output) As an output the PowerQUICC II asserts this pin for the
duration of the address bus tenure. Following an AACK, which terminates the address bus tenure,
the PowerQUICC II negates ABB for a fraction of a bus cycle and than stops driving this pin. As
an input the PowerQUICC II will not assume 60x bus ownership as long as it senses this pin is
asserted by an external 60x bus master.
IRQ2
TS
Interrupt Request 2—This input is one of the eight external lines that can request (by means of
the internal interrupt controller) a service routine from the core.
60x bus transfer start—(Input/output) Assertion of this pin signals the beginning of a new address
bus tenure. The PowerQUICC II asserts this signal when one of its internal 60x bus masters (core,
DMA, PCI bridge) begins an address tenure. When the PowerQUICC II senses this pin being
asserted by an external 60x bus master, it will respond to the address bus tenure as required
(snoop if enabled, access internal PowerQUICC II resources, memory controller support).
A[0–31]
60x address bus—These are input/output pins. When the PowerQUICC II is in external master
bus mode, these pins function as the 60x address bus. The PowerQUICC II drives the address of
its internal 60x bus masters and respond to addresses generated by external 60x bus masters.
When the PowerQUICC II is in internal master bus mode, these pins are used as address lines
connected to memory devices and controlled by the PowerQUICC II’s memory controller.
TT[0–4]
TBST
60x bus transfer type—These are input/output pins. The 60x bus master drives these pins during
the address tenure to specify the type of the transaction.
60x bus transfer burst—(Input/output) The 60x bus master asserts this pin to indicate that the
current transaction is a burst transaction (transfers 4 double words).
TSIZ[0–3]
AACK
60x transfer size—These are input/output pins. The 60x bus master drives these pins with a value
indicating the amount of bytes transferred in the current transaction.
60x address acknowledge—This is an input/output signal. A 60x bus slave asserts this signal to
indicate that it identified the address tenure. Assertion of this signal terminates the address
tenure.
ARTRY
DBG
60x address retry—(Input/output) Assertion of this signal indicates that the bus transaction
should be retried by the 60x bus master. The PowerQUICC II asserts this signal to enforce data
coherency with its internal cache and to prevent deadlock situations.
60x data bus grant—This is an output when an internal arbiter is used and an input when an
external arbiter is used. As an output the PowerQUICC II asserts this pin to grant 60x data bus
ownership to an external bus master. As an input the external arbiter should assert this pin to
grant 60x data bus ownership to the PowerQUICC II.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
6-3
External Signals
Table 6-1. External Signals (continued)
Description
Signal
DBB
60x data bus busy—(Input/output) As an output the PowerQUICC II asserts this pin for the
duration of the data bus tenure. Following a TA, which terminates the data bus tenure, the
PowerQUICC II negates DBB for a fraction of a bus cycle and than stops driving this pin. As an
input, the PowerQUICC II does not assume 60x data bus ownership as long as it senses DBB
asserted by an external 60x bus master.
IRQ3
Interrupt request 3—This input is one of the eight external lines that can request (by means of the
internal interrupt controller) a service routine from the core.
D[0–63]
DP[0]
60x data bus—These are input/output pins. In write transactions the 60x bus master drives the
valid data on this bus. In read transactions the 60x slave drives the valid data on this bus.
60x data parity 0—(Input/output) The 60x agent that drives the data bus drives also the data parity
signals. The value driven on data parity 0 pin should give odd parity (odd number of 1’s) on the
group of signals that includes data parity 0 and D[0–7].
RSRV
Reservation—The value driven on this output pin represents the state of the coherency bit in the
reservation address register that is used by the lwarx and stwcx. instructions.
EXT_BR2
IRQ1
External bus request 2—(Input). An external master should assert this pin to request 60x bus
ownership from the internal arbiter.
Interrupt request 1—This input is one of the eight external lines that can request (by means of the
internal interrupt controller) a service routine from the core.
DP[1]
60x data parity 1—(Input/output) The 60x agent that drives the data bus drives also the data parity
signals. The value driven on data parity 1 pin should give odd parity (odd number of ‘1’s) on the
group of signals that includes data parity 1 and D[8–15].
EXT_BG2
IRQ2
External bus grant 2—(Output) The PowerQUICC II asserts this pin to grant 60x bus ownership
to an external bus master.
Interrupt request 2—This input is one of the eight external lines that can request (by means of the
internal interrupt controller) a service routine from the core.
DP[2]
60x data parity 2—(Input/output) The 60x agent that drives the data bus drives also the data parity
signals. The value driven on data parity 2 pin should give odd parity (odd number of ‘1’s) on the
group of signals that includes data parity 2 and S[16–23].
TLBISYNC
EXT_DBG2
TLB sync—This input pin can be used to synchronize 60x core instruction execution to hardware
indications. Asserting this pin will force the core to stop instruction execution following a tlbsync
instruction execution. The core resumes instructions execution once this pin is negated.
External data bus grant 2—(Output) The PowerQUICC II asserts this pin to grant 60x data bus
ownership to an external bus master.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
6-4
Freescale Semiconductor
External Signals
Table 6-1. External Signals (continued)
Description
Signal
IRQ3
DP[3]
Interrupt request 3—This input is one of the eight external lines that can request (by means of the
internal interrupt controller) a service routine from the core.
60x data parity 3—(Input/output) The 60x agent that drives the data bus drives also the data parity
signals. The value driven on data parity 3 pin should give odd parity (odd number of 1’s) on the
group of signals that includes data parity 3 and D[24–31].
CKSTP_OUT
EXT_BR3
Checkstop output—(Output) Assertion indicates that the core is in its checkstop mode.
External bus request 3—(Input) An external master should assert this pin to request 60x bus
ownership from the internal arbiter.
IRQ4
DP[4]
Interrupt request 4—This input is one of the eight external lines that can request (by means of the
internal interrupt controller) a service routine from the core.
60x data parity 4—(Input/output) The 60x agent that drives the data bus drives also the data parity
signals. The value driven on data parity 4 pin should give odd parity (odd number of ‘1’s) on the
group of signals that includes data parity 4 and D[32–39].
CORE_SRESET
EXT_BG3
Core system reset—(Input) Asserting this pin will force the core to branch to its reset vector.
External bus grant 3—(Output) The PowerQUICC II asserts this pin to grant 60x bus ownership
to an external bus master.
IRQ5
DP[5]
Interrupt request 5—This input is one of the eight external lines that can request (by means of the
internal interrupt controller) a service routine from the core.
60x data parity 5—(Input/output) The 60x agent that drives the data bus drives also the data parity
signals. The value driven on data parity 5 pin should give odd parity (odd number of ‘1’s) on the
group of signals that includes data parity 5 and D[40–47].
TBEN
Time base enable—This is a count enable input to the Time Base counter in the core.
EXT_DBG3
External data bus grant 3—(Output) The PowerQUICC II asserts this pin to grant 60x data bus
ownership to an external bus master.
IRQ6
DP[6]
Interrupt request 6—This input is one of the eight external lines that can request (by means of the
internal interrupt controller) a service routine from the core.
60x data parity 6—(Input/output) The 60x agent that drives the data bus drives also the data parity
signals. The value driven on data parity 6 pin should give odd parity (odd number of ‘1’s) on the
group of signals that includes data parity 6 and D[48–55].
CSE[0]
Cache set entry 0—The cache set entry outputs from the core represent the cache replacement
set element for the current core transaction reloading into or writing out of the cache.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
6-5
External Signals
Table 6-1. External Signals (continued)
Description
Signal
IRQ7
DP[7]
Interrupt request 7—This input is one of the eight external lines that can request (by means of the
internal interrupt controller) a service routine from the core.
60x data parity 7—(Input/output) The 60x master or slave that drives the data bus drives also the
data parity signals. The value driven on data parity 7 pin should give odd parity (odd number of
‘1’s) on the group of signals that includes data parity 7 and D[56–63].
CSE[1]
Cache set entry 1—The cache set entry outputs from the core represent the cache replacement
set element for the current core transaction reloading into or writing out of the cache.
PSDVAL
60x data valid—(Input/output) Assertion of the PSDVAL pin indicates that a data beat is valid on
the data bus. The difference between the TA pin and the PSDVAL pin is that the TA pin is asserted
to indicate 60x data transfer terminations while the PSDVAL signal is asserted with each data
beat movement. Thus always when TA is asserted, PSDVAL will be asserted but when PSDVAL
is asserted, TA is not necessarily asserted. For example when a double word (2x64 bits) transfer
is initiated by the SDMA to a memory device that has 32 bits port size, PSDVAL will be asserted
3 times without TA and finally both pins will be asserted to terminate the transfer.
TA
Transfer acknowledge—(Input/output) Indicates that a 60x data beat is valid on the data bus. For
60x single beat transfers, assertion of this pin indicates the termination of the transfer. For 60x
burst transfers TA is asserted four times to indicate the transfer of four data beats with the last
assertion indicating the termination of the burst transfer.
TEA
GBL
Transfer error acknowledge—(Input/output) Assertion of this pin indicates a bus error. 60x
masters within the PowerQUICC II monitor the state of this pin. PowerQUICC II’s internal bus
monitor may assert this pin in case it identified a 60x bus transfer that is hung.
Global—(Input/output) When a 60x master within the chip initiates a bus transaction it drives this
pin. When an external 60x master initiates a bus transaction it should drive this pin. Assertion of
this pin indicates that the transfer is global and it should be snooped by caches in the system. The
PowerQUICC II’s data cache monitors the state of this pin.
IRQ1
CI
Interrupt request 1—This input is one of the eight external lines that can request (by means of the
internal interrupt controller) a service routine from the core.
Cache inhibit—Output pin. Used for L2 cache control. For each PowerQUICC II 60x transaction
initiated in the core, the state of this pin indicates if this transaction should be cached or not.
Assertion of the CI pin indicates that the transaction should not be cached.
BADDR29
IRQ2
Burst address 29—There are five burst address output pins. These pins are outputs of the 60x
memory controller. These pins are used in external master configuration and are connected
directly to memory devices controlled by PowerQUICC II’s memory controller. For information on
Interrupt request 2—This input is one of the eight external lines that can request (by means of the
internal interrupt controller) a service routine from the core.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
6-6
Freescale Semiconductor
External Signals
Table 6-1. External Signals (continued)
Description
Signal
WT
Write through—Output used for L2 cache control. For each core-initiated PowerQUICC II 60x
transaction, the state of this pin indicates if the transaction should be cached using write-through
or copy-back mode. Assertion of WT indicates that the transaction should be cached using the
write-through mode.
BADDR30
Burst address 30—There are five burst address output pins. These pins are outputs of the 60x
memory controller. These pins are used in external master configuration and are connected
directly to memory devices controlled by PowerQUICC II’s memory controller. For information on
IRQ3
Interrupt request 3—This input is one of the eight external lines that can request (by means of the
internal interrupt controller) a service routine from the core.
L2_HIT
L2 cache hit—(Input) It is used for L2 cache control. Assertion of this pin indicates that the 60x
transaction will be handled by the L2 cache. In this case, the memory controller will not start an
access to the memory it controls.
IRQ4
Interrupt request 4—This input is one of the eight external lines that can request (by means of the
internal interrupt controller) a service routine from the core.
CPU_BG
CPU bus grant—(Output) The value of the 60x core bus grant is driven on this pin to be used by
an external MPC2605GA L2 cache. The driven bus grant is not qualified; that is, when using an
external arbiter, the user should qualify this signal with the bus grant input to the PowerQUICC II
before connecting it to the L2 cache.
BADDR31
Burst address 31—There are five burst address output of the 60x memory controller used in an
external master configuration and are connected directly to the memory devices controlled by
PowerQUICC II’s memory controller. For information on the use of this signal, see
IRQ5
Interrupt Request 5—This input is one of the eight external lines that can request (by means of
the internal interrupt controller) a service routine from the core.
CPU_DBG
CPU data bus grant—(Output) Valid only when using the internal arbiter (PPC_ACR[EARB] = 0).
The OR of all data bus grant signals for internal masters from the internal arbiter is driven on
CPU_DBG. CPU_DBG should be connected to the CPU DBG input of an external MPC2605GA
L2 cache. (If an external arbiter is used, the CPU DBG input of the external MPC2605GA L2
cache should be connected to the DBG driven from the external arbiter to this PowerQUICC II.)
CPU_BR
CS[0–9]
CS[10]
CPU bus request—(Output) The value of the 60x core bus request is driven on this pin for the use
of an external L2 cache.
Chip select—These are output pins that enable specific memory devices or peripherals
connected to PowerQUICC II buses.
Chip select—These are output pins that enable specific memory devices or peripherals
connected to PowerQUICC II buses.
BCTL1
Buffer control 1—Output signal whose function is controlling buffers on the 60x data bus. Usually
used with BCTL0. The exact function of this pin is defined by the value of SIUMCR[BCTLC]. See
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
6-7
External Signals
Table 6-1. External Signals (continued)
Description
Signal
CS[11]
Chip select—Output that enable specific memory devices or peripherals connected to
PowerQUICC II buses.
AP[0]
Address parity 0—(Input/output) The 60x master that drives the address bus, drives also the
address parity signals. The value driven on address parity 0 pin should give odd parity (odd
number of ‘1’s) on the group of signals that includes address parity 0 and A[0–7].
BADDR[27–28]
Burst address 27–28—There are five burst address output pins. These pins are outputs of the
60x memory controller. Used in external master configuration and connected directly to the
memory devices controlled by PowerQUICC II’s memory controller. For information on the use of
ALE
Address latch enable—This output pin controls the external address latch that should be used in
external master 60x bus configuration.
BCTL0
Buffer control 0—Output whose function is controlling buffers on the 60x data bus. Usually used
with BCTL1 that is multiplexed on CS10. The exact function of this pin is defined by the value of
details.
PWE[0–7]
60x bus write enable—Outputs of the 60x bus GPCM. These pins select byte lanes for write
operations.
PSDDQM[0–7]
PBS[0–7]
60x bus SDRAM DQM—The DQM pins are outputs of the SDRAM control machine. These pins
select specific byte lanes of SDRAM devices.
60x bus UPM byte select—The byte select pins are outputs of the UPM in the memory controller.
They are used to select specific byte lanes during memory operations. The timing of these pins
is programmed in the UPM. The actual driven value depends on the address and size of the
transaction and the port size of the accessed device.
PSDA10
60x bus SDRAM A10—(Output) from the 60x bus SDRAM controller. Part of the address when a
row address is driven and is part of the command when a column address is driven.
PGPL0
60x bus UPM general purpose line 0—One of six general purpose output lines from UPM. The
values and timing of this pin is programmed in the UPM.
PSDWE
60x bus SDRAM write enable—(Output) from the 60x bus SDRAM controller. Should be
connected to SDRAMs’ WE input.
PGPL1
POE
60x bus UPM general purpose line 1—One of six general purpose output lines from UPM. The
values and timing of this pin is programmed in the UPM.
60x bus output enable—The output enable pin is an output of the 60x bus GPCM. Controls the
output buffer of memory devices during read operations.
PSDRAS
PGPL2
60x bus SDRAM ras—Output from the 60x bus SDRAM controller. Should be connected to
SDRAMs’ RAS input.
60x bus UPM general purpose line 2—One of six general purpose output lines from UPM. The
values and timing of this pin is programmed in the UPM.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
6-8
Freescale Semiconductor
External Signals
Table 6-1. External Signals (continued)
Description
Signal
PSDCAS
60x bus SDRAM CAS—Output from the 60x bus SDRAM controller. Should be connected to
SDRAMs’ CAS input.
PGPL3
PGTA
60x bus UPM general purpose line 3—One of six general purpose output lines from UPM. The
values and timing of this pin is programmed in the UPM.
60x GPCM TA—This input pin is used for transaction termination during GPCM operation.
Requires external pull up resistor for proper operation.
PUPMWAIT
PGPL4
60x bus UPM wait—This is an input to the UPM. An external device may hold this pin high to force
the UPM to wait until the device is ready for the continuation of the operation.
60x bus UPM general purpose line 4—One of six general purpose output lines from UPM. The
values and timing of this pin is programmed in the UPM.
PPBS
60x bus parity byte select—In systems in which data parity is stored in a separate chip, this output
is used as the byte-select for that chip.
PSDAMUX
PGPL5
60x bus SDRAM address multiplexer—This output pin controls the 60x SDRAM address
multiplexer when the PowerQUICC II is in external master mode.
60x bus UPM general purpose line 5—One of six general purpose output lines from UPM. The
values and timing of this pin is programmed in the UPM.
LWE[0–3]
Local bus write enable—The write enable pins are outputs of the Local bus GPCM. These pins
select specific byte lanes for write operations.
LSDDQM[0–3]
LBS[0–3]
Local bus SDRAM DQM—The DQM pins are outputs of the SDRAM control machine. These pins
select specific byte lanes of SDRAM devices.
Local bus UPM byte select—The byte select pins are outputs of the UPM in the memory
controller. They are used to select specific byte lanes during memory operations. The timing of
these pins is programmed in the UPM. The actual driven value depends on the address and size
of the transaction and the port size of the accessed device.
1
PCI_CFG[0-3]
PCI Configuration—In PCI mode, PCI_CFG[0-3] configure the PCI bridge to Host or agent and
control the PCI arbiter operation:
• PCI_CFG[0] is PCI_HOST, when High enables the PCI bridge for Agent operation, when Low
enables the PCI as Host.
• PCI_CFG[1] is PCI_ARB_EN, when Low enables the PCI internal arbiter logic, when High
disables the internal arbiter logic (and an external arbiter should be used).
• PCI_CFG[2] is the DLL_Enable. In PCI mode, this pin should be pulled high externally in order
to use the DLL.
• PCI_CFG[3] is reserved and should be pulled high externally.
LSDA10
LGPL0
Local bus SDRAM A10—Output from the 60x bus SDRAM controller. Is part of the address when
a row address is driven and is part of the command when a column address is driven.
Local bus UPM general purpose line 0—This is one of six general purpose output lines from
UPM. The values and timing of this pin is programmed in the UPM.
1
PCI_MODCK_H0 PCI MODCK_H0—In PCI mode, defines the operating mode of internal clock circuits.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
6-9
External Signals
Table 6-1. External Signals (continued)
Description
Signal
LSDWE
Local bus SDRAM write enable—Output from the local bus SDRAM controller. Should be
connected to the WE inputs of the SDRAMs.
Local bus UPM general purpose line 1—This is one of six general purpose output lines from
UPM. The values and timing of this pin is programmed in the UPM.
LGPL1
1
PCI_MODCK_H1 PCI MODCK_H1—In PCI mode, defines the operating mode of internal clock circuits.
LOE
Local bus output enable—The output enable pin is an output of the Local bus GPCM. Controls
the output buffer of memory devices during read operations.
LSDRAS
LGPL2
Local bus SDRAM RAS—Output from the Local bus SDRAM controller. Should be connected to
the SDRAM RAS input.
Local bus UPM general purpose line 2—This is one of six general purpose output lines from
UPM. The values and timing of this pin is programmed in the UPM.
1
PCI_MODCK_H2 PCI MODCK_H2—In PCI mode, defines the operating mode of internal clock circuits.
LSDCAS
Local bus SDRAM CAS—Output from the Local bus SDRAM controller. Should be connected to
the CAS inputs of the SDRAMs.
LGPL3
Local bus UPM general purpose line 3—This is one of six general purpose output lines from
UPM. The values and timing of this pin is programmed in the UPM.
1
PCI_MODCK_H3 PCI MODCK_H3—In PCI mode, defines the operating mode of internal clock circuits.
LGTA
Local bus GPCM TA—This input pin is used for transaction termination during GPCM operation.
Requires external pull up resistor for proper operation.
LUPMWAIT
LGPL4
Local bus UPM wait—This is an input to the UPM. An external device may hold this pin high to
force the UPM to wait until the device is ready for the continuation of the operation.
Local bus UPM general purpose line 4—One of six general purpose output lines from UPM. The
values and timing of this pin is programmed in the UPM.
LPBS
Local bus parity byte select—In systems in which the data parity is stored in a separate chip, this
output is used as the byte select for that chip.
LGPL5
Local bus UPM general purpose line 5—This is one of six general purpose output lines from
UPM. The values and timing of this pin is programmed in the UPM.
1
PCI_MODCK
LWR
PCI MODCK—In PCI mode, defines additional operating modes of internal clock circuits.
Local write—The local write pin is an output from the local bus memory controller. It is used to
distinguish between read and write transactions.
L_A14
Local bus address 14—Local bus address bit 14 output pin. In the local address bus bit 14 is most
significant and bit 31 is least significant.
1
PCI_PAR
PCI parity—PCI parity input/output pin. Assertion of this pin indicates that odd parity is driven
across PCI_AD[31-0] and PCI_C/BE[3–0] during address and data phases. Negation of
PCI_PAR indicates that even parity is driven across the PCI_AD[31-0] and PCI_C/BE[3–0] during
address and data phases.
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Freescale Semiconductor
External Signals
Table 6-1. External Signals (continued)
Description
Signal
L_A15
Local bus address 15—Local bus address bit 15 output pin. In the local address bus bit 14 is most
significant and bit 31 is least significant.
SMI
System management interrupt—System management interrupt input to the core.
1
PCI_FRAME
PCI frame—PCI cycle frame input/output pin. Used by the current PCI master to indicate the
beginning and duration of an access. Driven by the PowerQUICC II when its PCI interface is the
master of the access. Otherwise, it is an input.
L_A16
Local bus address 16—Local bus address bit 16 output pin. In the local address bus bit 14 is most
significant and bit 31 is least significant.
1
PCI_TRDY
PCI target ready—PCI target ready input/output pin. This pin is driven by the PowerQUICC II
when its PCI interface is the target of a PCI transfer. Assertion of this pin indicates that the PCI
target is ready to send or accept a data beat.
L_A17
Local bus address 17—Local bus address bit 17 output pin. In the local address bus bit 14 is most
significant and bit 31 is least significant.
1
PCI_IRDY
PCI initiator ready—PCI initiator ready input/output pin. This pin is driven by the PowerQUICC II
when its PCI interface is the initiator of a PCI transfer. Assertion of this pin indicates that the PCI
initiator is ready to send or accept a data beat.
CKSTOP_OUT
L_A18
Checkstop output—(Output) Assertion of CKSTOP_OUT indicates the core is in checkstop
mode.
Local bus address 18—Local bus address bit 18 output pin. In the local address bus bit 14 is most
significant and bit 31 is least significant.
1
PCI_STOP
PCI stop—PCI stop input/output pin. This pin is driven by the PowerQUICC II when its PCI
interface is the target of a PCI transfer. Assertion of this pin indicates that the PCI target is
requesting the master to stop the current PCI transfer.
L_A19
Local bus address 19—Local bus address bit 19 output pin. In the local address bus bit 14 is most
significant and bit 31 is least significant.
1
PCI_DEVSEL
PCI device select—PCI device select input/output pin. This pin is driven by the PowerQUICC II
when its PCI interface has decoded its own address as the target of the current PCI transfer. As
an input, PCI_DEVSEL indicates whether any device on the PCI bus has been selected.
L_A20
Local bus address 20—Local bus address bit 20 output pin. In the local address bus bit 14 is most
significant and bit 31 is least significant.
1
PCI_IDSEL
PCI initialization device select—(Input) Used to select the PowerQUICC II’s PCI interface during
a PCI configuration cycle.
L_A21
Local bus address 21—Local bus address bit 21 output pin. In the local address bus bit 14 is most
significant and bit 31 is least significant.
1
PCI_PERR
PCI parity error—PCI data parity error input/output pin. Assertion of this pin indicates that a data
parity error was detected during a PCI transfer (except for a special cycle).
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Freescale Semiconductor
6-11
External Signals
Table 6-1. External Signals (continued)
Description
Signal
L_A22
Local bus address 22—Local bus address bit 22 output pin. In the local address bus bit 14 is most
significant and bit 31 is least significant.
1
PCI_SERR
PCI system error—PCI system error input/output pin. Assertion of this pin indicates that a PCI
system error was detected during a PCI transfer. The PCI system error is for reporting address
parity errors, data parity errors on a special cycle command, or other catastrophic system errors.
L_A23
Local bus address 23—Local bus address bit 23 output pin. In the local address bus bit 14 is most
significant and bit 31 is least significant.
1
PCI_REQ0
PCI arbiter request 0—PCI request 0 input/output pin. When the PowerQUICC II’s internal PCI
arbiter is used, this is an input pin. In this mode assertion of this pin indicates that an external PCI
device is requesting the PCI bus. When an external PCI arbiter is used, this is an output pin. In
this mode assertion of this pin indicates that the PowerQUICC II’s PCI interface is requesting the
PCI bus.
L_A24
Local bus address 24—Local bus address bit 24 output pin. In the local address bus bit 14 is most
significant and bit 31 is least significant.
1
PCI_REQ1
PCI arbiter request 1—PCI request 1 input pin. When the PowerQUICC II’s internal PCI arbiter is
used, assertion of this pin indicates that an external PCI device is requesting the PCI bus.
1
CPCI_HS_ES
CompactPCI Hot Swap Ejector Switch—Hot Swap Ejector Switch input pin. In a CompactPCI
system, when the PowerQUICC II’s internal PCI arbiter is not used, this pin is used for the Hot
Swap interface to connect to the ejector switch logic.
0 Switch is closed
1 Switch is open
Important note: When functioning as the CPCI_HS_ES input, this signal must be filtered
(debounced) by an external circuit. Do not connect this input directly to the ejector switch. The
input must be a monotonically rising/falling signal.
L_A25
Local bus address 25—Local bus address bit 25 output pin. In the local address bus bit 14 is most
significant and bit 31 is least significant.
1
PCI_GNT0
PCI arbiter grant 0—PCI grant 0 input/output pin. When the PowerQUICC II’s internal PCI arbiter
is used, this is an output pin. In this mode, assertion of PCI_GNT0 indicates that an the external
PCI device that requested the PCI bus with PCI_REQ0 is granted the bus. When an external PCI
arbiter is used, this is an input pin. In this mode, assertion of PCI_GNT0 indicates that the
PowerQUICC II’s PCI interface is granted the PCI bus.
L_A26
Local bus address 26—Local bus address bit 26 output pin. In the local address bus bit 14 is most
significant and bit 31 is least significant.
1
PCI_GNT1
PCI arbiter grant 1—PCI grant 1 output pin. When the PowerQUICC II’s internal PCI arbiter is
used, assertion of PCI_GNT1 indicates that the external PCI device that requested the PCI bus
with PCI_REQ1 pin is granted the bus.
1
CPCI_HS_LED
CompactPCI Hot Swap LED—Hot Swap LED output pin. In CompactPCI system, when the
PowerQUICC II’s internal PCI arbiter is not used, this pin is used for the Hot Swap interface to
connect to the Hot Swap LED. The Hot Swap pins are not available when the internal arbiter is
used.
0 LED is off
1 LED is on
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Freescale Semiconductor
External Signals
Table 6-1. External Signals (continued)
Description
Signal
L_A27
Local bus address 27—Local bus address bit 27 output pin. In the local address bus bit 14 is most
significant and bit 31 is least significant.
1
PCI_GNT2
PCI arbiter grant 2—PCI grant 2 output pin. When the PowerQUICC II’s internal PCI arbiter is
used, assertion of PCI_GNT2 indicates that the external PCI device that requested the PCI bus
with PCI_REQ2 pin is granted the bus.
1
CPCI_HS_ENUM CompactPCI Hot Swap Enumerator—Hot Swap ENUM output pin. In CompactPCI system, when
the PowerQUICC II’s internal PCI arbiter is not used, this pin is used for the Hot Swap interface
to connect to the host as the enumeration request.
L_A28
Local bus address 28—Local bus address bit 28 output pin. In the local address bus bit 14 is most
significant and bit 31 is least significant.
1
PCI_RST
PCI reset—PCI reset output pin. When the PowerQUICC II is the host in the PCI system,
PCI_RST is an output.
CORE_SRESET
L_A29
Core system reset—This is an input to the core. When this input pin is asserted the core branches
to its reset vector.
Local bus address 29—Local bus address bit 29 output pin. In the local address bus bit 14 is most
significant and bit 31 is least significant.
1
PCI_INTA
PCI INTA—(output) When the PowerQUICC II is an agent of the PCI system, this pin is an output
used by the PowerQUICC II to signal an interrupt to the PCI host. (When the PowerQUICC II is
the host in the PCI system, the general IRQ pins are used for delivering PCI interrupts to the host.)
L_A30
Local bus address 30—Local bus address bit 30 output pin. In the local address bus bit 14 is most
significant and bit 31 is least significant.
1
PCI_REQ2
PCI arbiter request 2—PCI request 2 input pin. When the PowerQUICC II’s internal PCI arbiter is
used, assertion of this pin indicates that an external PCI device is requesting the PCI bus.
L_A31
Local bus address 31—Local bus address bit 31 output pin. In the local address bus bit 14 is most
significant and bit 31 is least significant.
1
DLLOUT
LCL_D[0–31]
Local bus data—Local bus data input/output pins. In the local data bus bit 0 is most significant
and bit 31 is least significant.
1
PCI_AD[31-0]
PCI address/data—PCI bus address/data input/output pins. During an address phase
PCI_AD[31-0] contains a physical address, during a data phase PCI_AD[31-0] contains the data
bytes. In the PCI address/data bus, bit 31 is msb and bit 0 is lsb.
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Freescale Semiconductor
6-13
External Signals
Table 6-1. External Signals (continued)
Description
Signal
LCL_DP[0–3]
PCI_C/BE[3-0]
Local bus data parity—Local bus data parity input/output pins. In local bus write operations the
PowerQUICC II drives these pins. In local bus read operations the accessed device drives these
pins. LCL_DP[0] is driven with a value that gives odd parity with LCL_D[0–7]. LCL_DP[1] is driven
with a value that gives odd parity with LCL_D[8–15]. LCL_DP[2] is driven with a value that gives
odd parity with LCL_D[16–23]. LCL_DP[3] is driven with a value that gives odd parity with
LCL_D[24–31].
1
PCI command/byte enable—PCI command/byte enable input/output pins. The PowerQUICC II
drives these pins when it is the initiator of a PCI transfer. During an address phase the
PCI_C/BE[3-0] defines the command, during the data phase PCI_C/BE[3-0] defines the byte
enables. PCI_C/BE[3] is the msb and PCI_C/BE[0] is the lsb.
IRQ0
Interrupt request 0—This input is an external line that causes an MCP interrupt to the core.
NMI_OUT
Non-maskable interrupt output—This is an output driven from PowerQUICC II’s internal interrupt
controller. Assertion of this output indicates that a non-maskable interrupt is pending in
PowerQUICC II’s internal interrupt controller.
IRQ7
Interrupt request 7—This input is one of the eight external lines that can request (by means of the
internal interrupt controller) a service routine from the core.
INT_OUT
Interrupt output—This is an output driven from PowerQUICC II’s internal interrupt controller.
Assertion of this output indicates that an unmasked interrupt is pending in PowerQUICC II’s
internal interrupt controller.
APE
Address parity error—This output pin is asserted when the PowerQUICC II detects wrong parity
driven on its address parity pins by an external master.
TRST
Test reset (JTAG)— Input only. This is the reset input to PowerQUICC II’s JTAG/COP controller.
TCK
TMS
Test clock (JTAG)—Input only. Provides the clock input for PowerQUICC II’s JTAG/COP controller.
Test mode select (JTAG)—Input only. Controls the state of PowerQUICC II’s JTAG/COP
controller.
TDI
Test data in (JTAG)—Input only. Data input to PowerQUICC II’s JTAG/COP controller.
Test data out (JTAG)—Output only. Data output from PowerQUICC II’s JTAG/COP controller.
Three-state—Asserting TRIS forces all other PowerQUICC II’s pins to high impedance state.
TDO
TRIS
PORESET
Power-on reset—When asserted, this input line causes the PowerQUICC II to enter power-on
reset state.
1
PCI_RST
PCI reset—PCI reset input pin. When the PowerQUICC II is an agent in the PCI system,
PCI_RST is an input.
HRESET
SRESET
QREQ
Hard reset—This open drain line, when asserted causes the PowerQUICC II to enter hard reset
state.
Soft reset—This open drain line, when asserted causes the PowerQUICC II to enter the soft reset
state.
Quiescent request— Output only. Indicates that PowerQUICC II’s internal core is about to enter
its low power mode. In the PowerQUICC II this pin will be typically used for debug purposes.
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Freescale Semiconductor
External Signals
Table 6-1. External Signals (continued)
Description
Signal
RSTCONF
RSTCONF —Input used during reset configuration sequence of the chip. Find detailed
MODCK1
AP[1]
MODCK1—Clock mode input. Defines the operating mode of internal clock circuits.
Address parity 1—(Input/output) The 60x master that drives the address bus, drives also the
address parity signals. The value driven on address parity 1 pin should give odd parity (odd
number of 1s) on the group of signals that includes address parity 1 and A[8–15].
TC[0]
Transfer Code 0—The transfer code output pins supply information that can be useful for debug
purposes for each of the PowerQUICC II’s initiated bus transactions.
BNKSEL[0]
Bank Select 0—The bank select outputs are used for selecting SDRAM bank when the
PowerQUICC II is in 60x compatible bus mode. BNKSEL0 is msb of the three BNKSEL signals.
MODCK2
AP[2]
MODCK2—Clock mode input. Defines the operating mode of internal clock circuits.
Address parity 2—(Input/output) The 60x master that drives the address bus, drives also the
address parity signals. The value driven on address parity 2 pin should give odd parity (odd
number of 1s) on the group of signals that includes address parity 2 and A[16–23].
TC[1]
Transfer code 1—The transfer code output pins supply information that can be useful for debug
purposes for each of the PowerQUICC II’s initiated bus transactions.
BNKSEL[1]
Bank select 1—The bank select outputs are used for selecting SDRAM bank when the
PowerQUICC II is in 60x-compatible bus mode.
MODCK3
AP[3]
MODCK3—Clock mode input. Defines the operating mode of internal clock circuits.
Address parity 3—(Input/output) The 60x master that drives the address bus, drives also the
address parity signals. The value driven on address parity 3 pin should give odd parity (odd
number of 1s) on the group of signals that includes address parity 3 and A[24—31].
TC[2]
Transfer code 2—The transfer code output pins supply information that can be useful for debug
purposes for each of the PowerQUICC II’s initiated bus transactions.
BNKSEL[2]
Bank select 2—The bank select outputs are used for selecting SDRAM bank when the
PowerQUICC II is in 60x-compatible bus mode. BNKSEL2 is lsb of the three BNKSEL signals.
XFC
External filter capacitance—Input connection for an external capacitor filter for PLL circuitry.
1
CLKIN1
Clock In—Primary clock input to PowerQUICC II’s PLL. In a PCI system , where the
PowerQUICC II PCI interface is operated from the PCI bus clock, CLKIN should be connected to
1
CLKIN2
Clock In2—This is the clock input to the PowerQUICC II’s DLL, which is used for deskewing the
1
PCI_MODE
PCI mode pin—This pin enables the PCI bridge of the PowerQUICC II.
• When Low, the PCI bridge is enabled, PCI interface replaces the Local bus.
• When High, the PCI bridge is disabled, the PowerQUICC II operates with the Local bus.
This pin has an internal pull up resistor so it defaults to Local bus operation.
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6-15
External Signals
Table 6-1. External Signals (continued)
Description
Signal
PA[0–31]
General-purpose I/O port A bits 0–31—CPM port multiplexing is described in Chapter 40,
PB[4–31]
PC[0–31]
PD[4–31]
Power Supply
General-purpose I/O port B bits 4–31—CPM port multiplexing is described in Chapter 40,
General-purpose I/O port C bits 0–31—CPM port multiplexing is described in Chapter 40,
General-purpose I/O port D bits 4–31—CPM port multiplexing is described in Chapter 40,
VDD—This is the power supply of the internal logic.
VDDH—This is the power supply of the I/O Buffers.
VCCSYN—This is the power supply of the PLL circuitry.
GNDSYN—This is a special ground of the PLL circuitry.
VCCSYN1—This is the power supply of the core’s PLL circuitry.
1
MPC8250, MPC8265, and MPC8266 only. This is a spare pin in all other devices.
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Freescale Semiconductor
Chapter 7
60x Signals
This chapter describes the PowerQUICC II processor’s external signals. It contains a concise description
of individual signals, showing behavior when a signal is asserted and negated, when the signal is an input
and an output, and the differences in how signals work in external-master or internal-only configurations.
NOTE
A bar over a signal name indicates that the signal is active low– for example,
ARTRY (address retry) and TS (transfer start). Active-low signals are
referred to as asserted (active) when they are low and negated when they are
high. Signals that are not active-low, such as TSIZ[0–3] (transfer size
signals) and TT[0–4] (transfer type signals) are referred to as asserted when
they are high and negated when they are low.
The 60x bus signals used with PowerQUICC II are grouped as follows:
•
Address arbitration signals—In external arbiter mode, PowerQUICC II uses these signals to
arbitrate for address bus mastership. The PowerQUICC II arbiter uses these signals to enable an
external device to arbitrate for address bus mastership.
•
Address transfer start signals—These signals indicate that a bus master has begun a transaction on
the address bus.
•
•
Address transfer signals (address bus)—These signals are used to transfer the address.
Transfer attribute signals—These signals provide information about the type of transfer, such as
the transfer size and whether the transaction is single, single extended, bursted, write-through or
cache-inhibited.
•
•
Address transfer termination signals—These signals are used to acknowledge the end of the
address phase of the transaction. They also indicate whether a condition exists that requires the
address phase to be repeated.
Data arbitration signals—The PowerQUICC II, in external arbiter mode, uses these signals to
arbitrate for data bus mastership. The PowerQUICC II arbiter uses these signals to enable an
external device to arbitrate for data bus mastership.
•
•
Data transfer signals—These signals, which consist of the data bus, data parity, and data parity
error signals, transfer the data and ensure its integrity.
Data transfer termination signals—Data termination signals are required after each data beat in a
data transfer. In a single-beat transaction, the data termination signals also indicate the end of the
tenure. For burst accesses or extended port-size accesses, the data termination signals apply to
individual beats and indicate the end of the tenure only after the final data beat.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
7-1
60x Signals
7.1
Signal Configuration
Figure shows the grouping of the PowerQUICC II’s 60x bus signal configuration.
NOTE
The PowerQUICC II hardware specifications provides a pinout showing pin
Bus Request (BR)
Data Bus Grant (DBG)
Data Bus Busy (DBB)
1
1
1
1
1
Bus Grant (BG)
Address
Arbitration
Data
Arbitration
Address Bus Busy (ABB)
Transfer Start (TS)
Address
Start
1
Data (D[0–63])
64
8
Address (A[0–31])
Address Parity (AP[0–3])
Address Parity Error (APE)
Data
32
4
Data Parity (DP[0–7])
Transfer
Address
Bus
1
Partial Data Valid Indication (PSDVAL)
Transfer Acknowledge (TA)
1
1
Transfer Type (TT[0–4])
Transfer Code (TC[0–2])
Transfer Burst (TBST)
Transfer Size (TSIZ[0–3])
Global (GBL)
5
3
1
4
1
1
1
Data
Termination
Transfer Error Acknowledge (TEA)
1
Transfer
Attributes
Cache Inhibit (CI)
Write-Through (WT)
Address Acknowledge (AACK)
Address Retry (ARTRY)
Reservation
TLBI SYNC
1
1
1
1
Address
Termination
Processor
State
Figure 7-1. Signal Groupings
7.2
Signal Descriptions
This section describes individual PowerQUICC II 60x signals, grouped according to Figure 7-1. Note that
the following sections briefly summarize signal functions. Chapter 8, “The 60x Bus,” describes many of
these signals in greater detail, both in terms of their function and how groups of signals interact.
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Freescale Semiconductor
60x Signals
7.2.1
Address Bus Arbitration Signals
The address arbitration signals are a collection of input and output signals devices use to request address
bus mastership, recognize when the request is granted, and indicate to other devices when mastership is
granted. For a detailed description of how these signals interact, see Section 8.4.1, “Address Arbitration.”
Bus arbitration signals have no meaning in internal-only mode.
7.2.1.1
Bus Request (BR)—Output
The bus request (BR) signal is both an input and an output signal on the PowerQUICC II.
7.2.1.1.1
Address Bus Request (BR)—Output
Following are the state meaning and timing comments for the BR signal output.
State Meaning
Asserted—Indicates that PowerQUICC II is requesting mastership of the address
bus. Note that BR may be asserted for one or more cycles and then deasserted due
to an internal cancellation of the bus request (for example, due to a load hit in the
Negated—Indicates that the PowerQUICC II is not requesting the address bus.
The PowerQUICC II may have no bus operation pending, it may be parked, or the
ARTRY input was asserted on the previous bus clock cycle.
Timing Comments
Assertion—May occur on any cycle; does not occur if the PowerQUICC II is
parked and the address bus is idle (BG asserted and ABB input negated).
Negation—Occurs for at least one cycle following a qualified BG even if another
transaction is pending; also negated for at least one cycle following any qualified
ARTRY on the bus unless PowerQUICC II asserted ARTRY and requires a snoop
copyback; may also be negated if PowerQUICC II cancels the bus request
internally before receiving a qualified BG.
High Impedance—Occurs during a hard reset or checkstop condition
7.2.1.1.2
Address Bus Request (BR)—Input
Following are the state meaning and timing comments for the BR signal input.
State Meaning
Asserted—Indicates that the external master has a bus transaction to perform and
is waiting for a qualified BG to begin the address tenure. BR may be asserted even
if the two possible pipelined address tenures have already been granted.
Negated—Indicates that the external master has no bus transaction to perform, or
if the device is parked, that it is potentially ready to start a bus transaction on the
next clock cycle (with proper qualification, see BG).
Timing Comments
Assertion—May occur on any cycle; does not occur if the external master is
parked and the address bus is idle (BG asserted and ABB input negated).
Negation—Occurs for at least one cycle after a qualified BG even if another
transaction is pending; also negated for at least one cycle following any qualified
ARTRY on the bus unless this chip asserted the ARTRY and requires to perform
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Freescale Semiconductor
7-3
60x Signals
a snoop copyback; may also be negated if the external master cancels a bus request
internally before receiving a qualified BG.
High Impedance—Occurs during a hard reset or checkstop condition.
7.2.1.2
Bus Grant (BG)
The address bus grant (BG) signal is both an input and an output signal.
7.2.1.2.1
Bus Grant (BG)—Input
The following are the state meaning and timing comments for the BG signal input.
State Meaning
Asserted—Indicates that the PowerQUICC II may, with the proper qualification,
begin a bus transaction and assume ownership of the address bus. A qualified bus
grant is generally determined from the bus state as follows: QBG = BG • ¬ABB
• ¬ARTRY where ARTRY is asserted only during the cycle after AACK. Note that
the assertion of BR is not required for a qualified bus grant (for bus parking).
Negated—Indicates that the PowerQUICC II is not granted next address
ownership.
Timing Comments
Assertion—May occur on any cycle. Once the PowerQUICC II has assumed
address bus ownership, it does not begin checking for BG again until the cycle
after AACK.
Negation—May occur whenever the PowerQUICC II must be prevented from
using the address bus. The PowerQUICC II may still assume address bus
ownership on the cycle BG is negated if it was asserted the previous cycle with
other bus grant qualifications.
7.2.1.2.2
Bus Grant (BG)—Output
Following are the state meaning and timing comments for the BG signal output.
State Meaning
Asserted—Indicates that the external device may, with the proper qualification,
begin a bus transaction and assume ownership of the address bus. A qualified bus
grant is generally determined from the bus state as follows: QBG = BG • ¬ABB
• ¬ARTRY where ARTRY is asserted only during the cycle after AACK. Note that
the assertion of BR is not required for a qualified bus grant (for bus parking).
Negated—Indicates that the external device is not granted next address
ownership.
Timing Comments
Assertion—May occur on any cycle. Once the external device has assumed
address bus ownership, it does not begin checking for BG again until the cycle
after AACK.
Negation—May occur when an external device must be kept from using the
address bus. The external device may still assume address bus ownership on the
cycle that BG is negated if it was asserted the previous cycle with other bus grant
qualifications.
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Freescale Semiconductor
60x Signals
7.2.1.3
Address Bus Busy (ABB)
The address bus busy (ABB) signal is both an input and an output signal.
7.2.1.3.1
Address Bus Busy (ABB)—Output
Following are the state meaning and timing comments for the ABB output signal.
State Meaning
Asserted—Indicates that the PowerQUICC II is the current address bus master.
The PowerQUICC II may not assume address bus ownership in case a bus request
is internally cancelled by the cycle a qualified BG would have been recognized.
Negated—Indicates that PowerQUICC II is not the current address bus master.
Timing Comments
Assertion—Occurs the cycle after a qualified BG is accepted by PowerQUICC II
and remains asserted for the duration of the address tenure.
Turn-Off Sequencing—Negates for a fraction of a bus cycle (1/2 minimum,
depends on clock mode) starting the cycle following the assertion of AACK. It
then goes to the high impedance state.
7.2.1.3.2
Address Bus Busy (ABB)—Input
Following are the state meaning and timing comments for the ABB input signal.
State Meaning
Asserted—Indicates that external device is the address bus master.
Negated—Indicates that the address bus may be available for use by the
PowerQUICC II (see BG). The PowerQUICC II also tracks the state of ABB on
the bus from the TS and AACK inputs. (See section on address arbitration phase.)
Timing Comments
Assertion—May occur whenever the PowerQUICC II must be prevented from
using the address bus.
Negation—May occur whenever the PowerQUICC II may use the address bus.
7.2.2
Address Transfer Start Signal
In the internal only mode the address transfer start signal has no meaning.
Address transfer start signal are input and output signals that indicate that an address bus transfer has
begun.
7.2.2.1
Transfer Start (TS)
The TS signal is both an input and an output signal on the PowerQUICC II.
7.2.2.1.1
Transfer Start (TS)—Output
Following are the state meaning and timing comments for the TS output signal.
State Meaning
Asserted—Indicates that the PowerQUICC II has started a bus transaction and that
the address bus and transfer attribute signals are valid. It is also an implied data
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7-5
60x Signals
bus request if the transfer attributes TT[0–4] indicate that a data tenure is required
for the transaction.
Negated—Has no special meaning during a normal transaction.
Timing Comments
Assertion/Negation—Driven and asserted on the cycle after a qualified BG is
accepted by PowerQUICC II; remains asserted for one clock only. Negated for the
remainder of the address tenure. Assertion is coincident with the first clock that
ABB is asserted.
High Impedance—Occurs the cycle following the assertion of AACK (same cycle
as ABB negation).
7.2.2.2
Transfer Start (TS)—Input
Following are the state meaning and timing comments for the TS input signal.
State Meaning
Asserted—Indicates that another device has begun a bus transaction and that the
address bus and transfer attribute signals are valid for snooping.
Negated—Has no special meaning.
Timing Comments
Assertion/Negation—Must be asserted for one cycle only and then immediately
negated. Assertion may occur at any time during the assertion of ABB.
7.2.3
Address Transfer Signals
In internal only mode the memory controller uses these signals for glueless address transfers to memory
and I/O devices.
The address transfer signals are used to transmit the address.
7.2.3.1
Address Bus (A[0–31])
The address bus (A[0–31]) consists of 32 signals that are both input and output signals.
7.2.3.1.1
Address Bus (A[0–31])—Output
Following are the state meaning and timing comments for the A[0–31] output signals.
State Meaning
Content—Specifies the physical address of the bus transaction. For burst or
extended operations, the address is a double-word.
Timing Comments
Assertion/Negation—Driven valid on the same cycle that TS is driven/asserted;
remains driven/valid for the duration of the address tenure.
High Impedance— Occurs the cycle following the assertion of AACK; no
precharge action performed on release.
7.2.3.1.2
Address Bus (A[0–31])—Input
Following are the state meaning and timing comments for the A[0–31] input signals.
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State Meaning
Asserted—Indicates that another device has begun a bus transaction and that the
address bus and transfer attribute signals are valid for snooping and in slave mode.
Negated—Has no special meaning.
Timing Comments
Assertion/Negation—Must be valid on the same cycle that TS is asserted; sampled
by the processor only on this cycle.
7.2.4
Address Transfer Attribute Signals
In internal only mode the address transfer attribute signals have no meaning.
The transfer attribute signals are a set of signals that further characterize the transfer—such as the size of
the transfer, whether it is a read or write operation, and whether it is a burst or single-beat transfer. For a
detailed description of how these signals interact, see Section 7.2.4, “Address Transfer Attribute Signals.”
7.2.4.1
Transfer Type (TT[0–4])
The transfer type signals (TT[0–4]) consist of five input/output signals on the PowerQUICC II. For a
complete description of TT[0–4] signals and transfer type encoding, see Section 8.4.3.1, “Transfer Type
7.2.4.1.1
Transfer Type (TT[0–4])—Output
Following are the state meaning and timing comments for the TT[0–4] output signals on the PowerQUICC
II.
State Meaning
Asserted/Negated—Specifies the type of transfer in progress.
Assertion/Negation—Same as A[0–31].
Timing Comments
High Impedance—Same as A[0–31].
7.2.4.1.2
Transfer Type (TT[0–4])—Input
Following are the state meaning and timing comments for the TT[0–4] input signals on the PowerQUICC
II.
State Meaning
Asserted/Negated—Specifies the type of transfer in progress for snooping by the
PowerQUICC II.
Timing Comments
Assertion/Negation—Same as A[0–31].
7.2.4.2
Transfer Size (TSIZ[0–3])
The transfer size (TSIZ[0–3]) signals consist of four input/output signals on the PowerQUICC II,
following are the state meaning and timing comments for the TSIZ[0–3] signals on the PowerQUICC II.
State Meaning
Asserted/Negated—Specifies the data transfer size for the transaction (see
graphics transfer operations, these signals form part of the Resource ID (see
TBST).
Timing Comments
Assertion/Negation—Same as A[0–31].
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High Impedance—Same as A[0–31].
Transfer Burst (TBST)
7.2.4.3
The transfer burst (TBST) signal is an input/output signal on the PowerQUICC II. Following are the state
meaning and timing comments for the TBST output/input signal.
State Meaning
Asserted—Indicates that a burst transfer is in progress (see Section 8.4.3.3,
operations, this signal forms part of the Resource ID field from the EAR as
follows:
TBST || TSIZ[0–3] = EAR[28–31]. (See TBST.)
Negated—Indicates that a burst transfer is not in progress.
Assertion/Negation—Same as A[0–31].
Timing Comments
High Impedance—Same as A[0–31].
7.2.4.4
Global (GBL)
The global (GBL) signal is an input/output signal on the PowerQUICC II.
7.2.4.4.1
Global (GBL)—Output
Following are the state meaning and timing comments for the GBL output signal.
State Meaning
Asserted—Indicates that the transaction is global and should be snooped by other
devices. GBL reflects the M bit (WIM bits) from the MMU except during certain
transactions.
Negated—Indicates that the transaction is not global and should not be snooped
by other devices.
Timing Comments
Assertion/Negation—Same as A[0–31].
High Impedance—Same as A[0–31].
7.2.4.4.2
Global (GBL)—Input
Following are the state meaning and timing comments for the GBL input signal.
State Meaning
Asserted—Indicates that a transaction must be snooped by PowerQUICC II.
Negated—Indicates that a transaction should not be snooped by PowerQUICC II.
(In addition, certain non-global transactions are snooped for reservation
coherency.)
Timing Comments
Assertion/Negation—Same as A[0–31].
7.2.4.5
Caching-Inhibited (CI)—Output
The cache inhibit (CI) signal is an output signal on the PowerQUICC II. Following are the state meaning
and timing comments for CI.
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State Meaning
Asserted—Indicates that the transaction in progress should not be cached. CI
reflects the I bit (WIM bits) from the MMU except during certain transactions.
Negated—Indicates that the transaction should be cached.
Assertion/Negation—Same as A[0–31].
Timing Comments
High Impedance—Same as A[0–31].
7.2.4.6
Write-Through (WT)—Output
The write-through (WT) signal is an output signal on the PowerQUICC II. Following are the state meaning
and timing comments for WT.
State Meaning
Asserted—Indicates that the transaction should operate in write-through mode.
WT reflects the W bit (WIM bits) from the MMU except during certain
transactions. WT may be asserted during read transactions.
Negated—Indicates that the transaction should not operate in write-through mode.
Assertion/Negation—Same as A[0–31].
Timing Comments
High Impedance—Same as A[0–31].
7.2.5
Address Transfer Termination Signals
The address transfer termination signals are used to indicate either that the address phase of the transaction
has completed successfully or must be repeated, and when it should be terminated. For detailed
information about how these signals interact, see Section 7.2.5, “Address Transfer Termination Signals.”
The address transfer termination signals have no meaning in internal only mode.
7.2.5.1
Address Acknowledge (AACK)
The address acknowledge (AACK) signal is an input/output on the PowerQUICC II.
7.2.5.1.1
Address Acknowledge (AACK)—Output
.Following are the state meaning and timing comments for AACK as an output signal.
State Meaning
Asserted—Indicates that the address tenure of a transaction is terminated. On the
cycle following the assertion of AACK, the bus master releases the
address-tenure-related signals to the high-impedance state and samples ARTRY.
Negated—Indicates that the address bus and the transfer attributes must remain
driven, if negated during ABB.
Timing Comments
Assertion—Occurs a programmable number of clocks after TS or whenever
ARTRY conditions are resolved.
Negation—Occurs one clock after assertion.
7.2.5.1.2
Address Acknowledge (AACK)—Input
Following are the state meaning and timing comments for AACK as an input signal.
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State Meaning
Asserted—Indicates that a 60x bus slave is terminating the address tenure. On the
cycle following the assertion of AACK, the bus master releases the address tenure
related signals to the high-impedance state and samples ARTRY.
Negated—Indicates that the address tenure must remain active and the address
tenure related signals driven.
Timing Comments
Assertion—Occurs during the 60x bus slave access, at least two clocks after TS.
Negation—Occurs one clock after assertion.
7.2.5.2
Address Retry (ARTRY)
The address retry (ARTRY) signal is both an input and output signal on the PowerQUICC II.
7.2.5.2.1
Address Retry (ARTRY)—Output
Following are the state meaning and timing comments for ARTRY as an output signal.
State Meaning
Asserted—Indicates that the PowerQUICC II detects a condition in which an
address tenure must be retried. If the PowerQUICC II processor needs to update
memory as a result of snoop that caused the retry, the PowerQUICC II asserts BR
the second cycle after AACK if ARTRY is asserted.
High Impedance—Indicates that the PowerQUICC II does not need the address
tenure to be retried.
Timing Comments
Assertion—Asserted the third bus cycle following the assertion of TS if a retry is
required.
Negation—Occurs the second bus cycle after the assertion of AACK. Since this
signal may be simultaneously driven by multiple devices, it negates in a unique
fashion. First the buffer goes to high impedance for a minimum of one-half
processor cycle (dependent on the clock mode), then it is driven negated for one
bus cycle before returning to high impedance.
7.2.5.2.2
Address Retry (ARTRY)—Input
Following are the state meaning and timing comments for the ARTRY input.
State Meaning
Asserted—If the PowerQUICC II is the address bus master, ARTRY indicates that
the PowerQUICC II must retry the preceding address tenure and immediately
negate BR (if asserted). If the associated data tenure has started, the PowerQUICC
II also aborts the data tenure immediately even if the burst data has been received.
If the PowerQUICC II is not the address bus master, this input indicates that the
PowerQUICC II should negate BR for one bus clock cycle immediately after
external device asserts ARTRY to permit a copy-back operation to main memory.
Note that the subsequent address presented on the address bus may not be the one
that generated the assertion of ARTRY.
Negated/High Impedance—Indicates that the PowerQUICC II does not need to
retry the last address tenure.
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Timing Comments
Assertion—May occur as early as the second cycle following the assertion of TS
and must occur by the bus clock cycle immediately following the assertion of
AACK if an address retry is required.
Negation—Must occur during the second cycle after the assertion of AACK.
7.2.6
Data Bus Arbitration Signals
The data bus arbitration signals have no meaning in internal-only mode.
Like the address bus arbitration signals, data bus arbitration signals maintain an orderly process for
determining data bus mastership. Note that there is no data bus arbitration signal equivalent to the address
bus arbitration signal BR (bus request), because, except for address-only transactions, TS implies data bus
requests. For a detailed description on how these signals interact, see Section 8.5.1, “Data Bus
7.2.6.1
Data Bus Grant (DBG)
The data bus grant signal (DBG) is an output/input on the PowerQUICC II.
7.2.6.1.1
Data Bus Grant (DBG)—Input
DBG an input when PowerQUICC II is configured to an external arbiter. The following are the state
meaning and timing comments for DBG.
State Meaning
Asserted—Indicates that the PowerQUICC II may, with the proper qualification,
assume mastership of the data bus. The PowerQUICC II derives a qualified data
bus grant when DBG is asserted and DBB and ARTRY are negated; that is, the
data bus is not busy (DBB is negated), and there is no outstanding attempt to
perform an ARTRY of the associated address tenure.
Negated—Indicates that the PowerQUICC II must hold off its data tenures.
Timing Comments
Assertion—May occur any time to indicate the PowerQUICC II is free to take data
bus mastership. It is not sampled until TS is asserted.
Negation—May occur at any time to indicate the PowerQUICC II cannot assume
data bus mastership.
7.2.6.1.2
Data Bus Grant (DBG)—Output
DBG signal is output when the PowerQUICC II configured to use the internal arbiter. Following are the
state meaning and timing comments for the DBG signal.
State Meaning
Asserted—Indicates that the external device may, with the proper qualification,
assume mastership of the data bus. A qualified data bus grant is defined as the
assertion of DBG, negation of DBB, and negation of ARTRY. The requirement for
the ARTRY signal is only for the address bus tenure associated with the data bus
tenure about to be granted (that is, not for another address tenure available because
of address pipelining).
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Negated—Indicates that an external device is not granted mastership of the data
bus.
Timing Comments
Assertion—Occurs on the first clock in which the data bus is not busy and the
processor has the highest priority outstanding data transaction.
Negation—Occurs one clock after assertion.
7.2.6.2
Data Bus Busy (DBB)
The data bus busy (DBB) signal is both an input and output signal on the PowerQUICC II.
7.2.6.2.1
Data Bus Busy (DBB)—Output
Following are the state meaning and timing comments for the DBB output signal.
State Meaning
Asserted—Indicates that the PowerQUICC II is the data bus master. The
PowerQUICC II always assumes data bus mastership if it needs the data bus and
determines a qualified data bus grant (see DBG).
Negated—Indicates that the PowerQUICC II is not using the data bus.
Assertion—Occurs during the bus clock cycle following a qualified DBG.
Timing Comments
Negation—Occurs for a minimum of one-half bus clock cycle following the
assertion of the final TA following TEA or certain ARTRY cases.
High Impedance—Occurs after DBB is negated.
7.2.6.2.2
Data Bus Busy (DBB)—Input
Following are the state meaning and timing comments for the DBB input signal.
State Meaning
Asserted—Indicates that another device is bus master.
Negated—Indicates that the data bus is free (with proper qualification, see DBG)
for use by the PowerQUICC II.
Timing Comments
Assertion—Must occur when the PowerQUICC II must be prevented from using
the data bus.
Negation—May occur whenever the data bus is available.
7.2.7
Data Transfer Signals
Data transfer signals are used in the same way in both internal only and external master modes. Like the
address transfer signals, the data transfer signals are used to transmit data and to generate and monitor
parity for the data transfer. For a detailed description of how data transfer signals interact, see
7.2.7.1
Data Bus (D[0–63])
The data bus (D[0–63]) states have the same meanings in both internal only mode external master mode.
The data bus consists of 64 signals that are both inputs and outputs on the PowerQUICC II. Following are
the state meaning and timing comments for the data bus.
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State Meaning
Timing Comments
The number of times the data bus is driven depends on the transfer size, port size,
and whether the transfer is a single-beat or burst operation.
7.2.7.1.1
Data Bus (D[0–63])—Output
Following are the state meaning and timing comments for the D[0–63] output signals.
State Meaning
Asserted/Negated—Represents the state of data during a data write. Byte lanes not
selected for data transfer do not supply valid data. PowerQUICC II duplicates data
to enable valid data to be sent to different port sizes.
Timing Comments
Assertion/Negation—Initial beat coincides with DBB, for bursts, transitions on
the bus clock cycle following each assertion of TA and, for port size, transitions
on the bus clock cycle following each assertion of PSDVAL.
High Impedance—Occurs on the bus clock cycle after the final assertion of TA,
TEA, or certain ARTRY cases.
Table 7-1. Data Bus Lane Assignments
Data Bus Signals
Byte Lane
D0–D7
0
1
2
3
4
5
6
7
D8–D15
D16–D23
D24–D31
D32–D39
D40–D47
D48–D55
D56–D63
7.2.7.1.2
Data Bus (D[0–63])—Input
Following are the state meaning and timing comments for the D[0–63] input signals.
State Meaning
Asserted/Negated—Represents the state of data during a data read transaction.
Timing Comments
Assertion/Negation—Data must be valid on the same bus clock cycle that TA
and/or PSDVAL is asserted.
7.2.7.2
Data Bus Parity (DP[0–7])
The eight data bus parity (DP[0–7]) signals both output and input signals.
7.2.7.2.1
Data Bus Parity (DP[0–7])—Output
Following are the state meaning and timing comments for the DP[0–7] output signals.
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State Meaning
Asserted/Negated—Represents odd parity for each of 8 bytes of data write
transactions. Odd parity means that an odd number of bits, including the parity bit,
Table 7-2. DP[0–7] Signal Assignments
Signal Name
Data Bus Signal Assignments
DP0
DP1
DP2
DP3
DP4
DP5
DP6
DP7
D[0–7]
D[8–15
D[16–23]
D[24–31]
D[32–39]
D[40–47]
D[48–55]
D[56–63]
Timing Comments
Assertion/Negation—The same as the data bus.
High Impedance—The same as the data bus.
7.2.7.2.2
Data Bus Parity (DP[0–7])—Input
Following are the state meaning and timing comments for the DP input signals.
State Meaning
Asserted/Negated—Represents odd parity for each byte of read data. Parity is
checked on all data byte lanes, regardless of the size of the transfer. Detected even
parity causes a checkstop if data parity errors are enabled in the BCS[PAR_EN].
Timing Comments
Assertion/Negation—The same as D[0–63].
7.2.8
Data Transfer Termination Signals
Data termination signals are required after each data beat in a data transfer. Note that in a single-beat
transaction that is not a port-size transfer, the data termination signals also indicate the end of the tenure.
In burst or port size accesses, the data termination signals apply to individual beats and indicate the end of
the tenure only after the final data beat. For a detailed description of how these signals interact, see
7.2.8.1
Transfer Acknowledge (TA)
The transfer acknowledge (TA) signal is both input and output on the PowerQUICC II.
7.2.8.1.1
Transfer Acknowledge (TA)—Input
Following are the state meaning and timing comments for the TA input signal.
State Meaning
Asserted—Indicates that a single-beat data transfer completed successfully or that
a data beat in a burst transfer completed successfully. Note that TA must be
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asserted for each data beat in a burst transaction. For more information, see
Negated—(During assertion of DBB) indicates that, until TA is asserted, the
PowerQUICC II must continue to drive the data for the current write or must wait
to sample the data for reads.
Timing Comments
Assertion—Depends on whether or not the PCI controller can initiate 60x bus
global transactions when the address retry mechanism is in use:
PCI controller is not used or cannot initiate global transactions— Assertion must
occur at least one cycle following AACK for the current transaction;
otherwise, assertion may occur at any time during the assertion of DBB.
The system can withhold assertion of TA to indicate that the
PowerQUICC II should insert wait states to extend the duration of the data
beat.
PCI controller can initiate global transactions—Assertion must occur at least one
clock cycle following AACK for the current transaction and at least one
clock cycle after ARTRY can be asserted.
Negation—Must occur after the bus clock cycle of the final (or only) data beat of
the transfer. For a burst transfer, the system can assert TA for one bus clock cycle
and then negate it to advance the burst transfer to the next beat and insert wait
states during the next beat. (Note: when configured for 1:1 clock mode and is
performing a burst read into the data cache, the PowerQUICC II requires two wait
states between the assertion of TS and the first assertion of TA for that transaction,
or one wait state for 1.5:1 clock mode.)
7.2.8.1.2
Transfer Acknowledge (TA)—Output
Following are the state meaning and timing comments for TA as an output signal.
State Meaning
Asserted—Indicates that the data has been latched for a write operation, or that the
data is valid for a read operation, thus terminating the current data beat. If it is the
last or only data beat, this also terminates the data tenure.
Negated—Indicates that master must extend the current data beat (insert wait
states) until data can be provided or accepted by the PowerQUICC II.
Timing Comments
Assertion—Depends on whether or not the PCI controller can initiate 60x bus
global transactions when the address retry mechanism is in use:
PCI controller is not used or cannot initiate global transactions—Assertion must
occur at least one cycle following AACK for the current transaction;
occurs on the clock in which the current data transfer can be completed.
PCI controller can initiate global transactions—Assertion must occur at least one
clock cycle following AACK for the current transaction and at least one
clock cycle after ARTRY can be asserted.
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Negation—Occurs after the clock cycle of the final (or only) data beat of the
transfer. For a burst transfer, TA may be negated between beats to insert one or
more wait states before the completion of the next beat.
7.2.8.2
Transfer Error Acknowledge (TEA)
The transfer error acknowledge (TEA) signal is both input and output on the PowerQUICC II.
7.2.8.2.1
Transfer Error Acknowledge (TEA)—Input
Following are the state meaning and timing comments for the TEA input signal.
State Meaning
Asserted—Indicates that a bus error occurred. The assertion of TEA causes the
negation/high impedance of DBB in the next clock cycle. However, data entering
the PowerQUICC II internal memory resources such as GPRs or caches are not
invalidated.
Negated—Indicates that no bus error was detected.
Timing Comments
Assertion—May be asserted while DBB is asserted and for the cycle after is TA is
asserted during a read operation. TEA should be asserted for one cycle only.
Negation—TEA must be negated no later than the negation of DBB.
7.2.8.2.2
Transfer Error Acknowledge (TEA)—Output
Following are the state meaning and timing comments for the TEA output.
State Meaning
Asserted—Indicates that a bus error has occurred. Assertion of TEA terminates
the transaction in progress; that is, asserting TA is unnecessary because it is
ignored by the target device. An unsupported memory transaction, such as a
direct-store access or a graphics read or write, causes the assertion of TEA
(provided TEA is enabled and the address transfer matches the PowerQUICC II
memory map).
Negated—Indicates that no bus error was detected.
Assertion—Occurs on the first clock after the bus error is detected.
Negation—Occurs one clock after assertion.
Timing Comments
7.2.8.3
Partial Data Valid Indication (PSDVAL)
The partial data valid indication (PSDVAL) is both an input and output on the PowerQUICC II.
7.2.8.3.1
Partial Data Valid (PSDVAL)—Input
Following are the state meaning and timing comments for the PSDVAL input signal. Note that TA asserts
with PSDVAL to indicate the termination of the current transfer and for each complete data beat in burst
transactions.
State Meaning
Asserted—Indicates that a beat data transfer completed successfully. Note that
PSDVAL must be asserted for each data beat in a single beat, port size and burst
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transaction,. For more information, see Section 8.5.5, “Port Size Data Bus
Negated—(During DBB) indicates that, until PSDVAL is asserted, the
PowerQUICC II must continue to drive the data for the current write or must wait
to sample the data for reads.
Timing Comments
Assertion—Must not occur before AACK for the current transaction (if the
address retry mechanism is to be used to prevent invalid data from being used by
the PowerQUICC II); otherwise, assertion may occur at any time during the
assertion of DBB. The system can withhold assertion of PSDVAL to indicate that
the PowerQUICC II should insert wait states to extend the duration of the data
beat.
Negation—Must occur after the bus clock cycle of the final (or only) data beat of
the transfer. For a burst and/or port size transfer, the system can assert PSDVAL
for one bus clock cycle and then negate it to insert wait states during the next beat.
(Note: when the PowerQUICC II Processor is configured for 1:1 clock mode and
is performing a burst read into the data cache, the PowerQUICC II requires two
wait state between the assertion of TS and the first assertion of PSDVAL for that
transaction, or 1 wait state for 1.5:1 clock mode.)
7.2.8.3.2
Partial Data Valid (PSDVAL)—Output
Following are the state meaning and timing comments for PSDVAL as an output signal.
State Meaning
Asserted—Indicates that the data has been latched for a write operation, or that the
data is valid for a read operation, thus terminating the current data beat. If it is the
last or only data beat, this also terminates the data tenure.
Negated—Indicates that the master must extend the current data beat (insert wait
states) until data can be provided or accepted by the PowerQUICC II.
Timing Comments
Assertion—Occurs on the clock in which the current data transfer can be
completed.
Negation—Occurs after the clock cycle of the final (or only) data beat of the
transfer. For a burst transfer, PSDVAL may be negated between beats to insert one
or more wait states before the completion of the next beat.
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Chapter 8
The 60x Bus
The 60x bus, which is used by processors that implement the PowerPC architecture, provides flexible
support for the on-chip MPC603 processor as well as other internal and external bus devices. The 60x bus
supports 32-bit addressing, a 64-bit data bus, and burst operations that transfer as many as 256 bits of data
in a four-beat burst. The 60x data bus can be accessed in 8-, 16-, 32-, and 64-bit data ports. The 60x bus
supports accesses of 1, 2, 3, and 4 bytes, aligned or unaligned, on 4-byte (word) boundaries; it also supports
64-, 128-, 192-, and 256-bit accesses.
The address and data buses support synchronous, one-level pipeline transactions. The 60x bus interface
can be configured to support both external and internal masters or internal masters only.
8.1
Terminology
Table 8-1 defines terms used in this chapter.
Table 8-1. Terminology
Term
Atomic
Definition
A bus access that attempts to be part of a read-write operation to the same address uninterrupted
by any other access to that address. The PowerQUICC II initiates the read and write separately, but
signals the memory system that it is attempting an atomic operation. If the operation fails, status is
kept so that PowerQUICC II can try again.
Beat
A single state on the PowerQUICC II interface that may extend across multiple bus cycles. (An
PowerQUICC II transaction can be composed of multiple address or data beats.)
Burst
A multiple-beat data transfer whose total size is typically equal to a cache block size (in
PowerQUICC II: 32 bytes, or 4 data beats at 8 bytes per beat).
Cache block
Clean
Flush
Kill
The PowerPC architecture defines the basic unit of coherency as a cache block, which can be
considered the same thing as a cache line.
An operation that causes a cache block to be written to memory if modified, and then left in a valid,
unmodified state in the cache.
An operation that causes a cache block to be invalidated in the cache, and its data, if modified, to
be written back to main memory.
An operation that causes a cache block to be invalidated in the cache without writing any modified
data to memory.
Lane
A sub-grouping of signals within a bus. An 8-bit section of the address or data bus may be referred
to as a byte lane for that bus.
Master
The device that owns the address or data bus, the device that initiates or requests the transaction.
Identifies a cache block The M state in a MESI or MEI protocol.
Modified
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Table 8-1. Terminology (continued)
Definition
Term
Parking
Pipelining
Slave
Granting potential bus mastership without requiring a bus request from that device. This eliminates
the arbitration delay associated with the bus request.
Initiating a bus transaction before the current one finishes. This involves running an address tenure
for a new bus transaction before the data tenure for a current bus transaction completes.
The device addressed by the master. The slave is identified in the address tenure and is responsible
for sourcing or sinking the requested data for the master during the data tenure.
Snooping
Monitoring addresses driven by a bus master to detect the need for coherency actions.
Split-transaction A transaction with separate request and response tenures.
Tenure
The period of bus mastership. For PowerQUICC II, there can be separate address bus tenures and
data bus tenures.
Transaction
A complete exchange between two bus devices. A typical transaction is composed of an address
tenure and a data tenure, which may overlap or occur separately from the address tenure. A
transaction can minimally consist of an address tenure alone.
8.2
Bus Configuration
The 60x bus supports separate bus configurations for internal masters and external bus masters.
•
Single-PowerQUICC II bus mode connects external devices by using only the memory controller.
•
connections to other masters and 60x-bus slaves, such as an external L2 cache controller.
The figures in the following sections show how the PowerQUICC II can be connected in these two
configurations.
8.2.1
Single-PowerQUICC II Bus Mode
In single-PowerQUICC II bus mode, the PowerQUICC II is the only bus device in the system. The internal
memory controller controls all devices on the external pins. Figure 8-1 shows the signal connections for
single-PowerQUICC II bus mode.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
8-2
Freescale Semiconductor
The 60x Bus
PowerQUICC II
APE
TS
Latch &
A[0–31]
DRAM MUX
I/O
TT[0–4]
TSIZ[0–3]
TBST
CI
WT
MEM
GBL
AACK
ARTRY
DBG
D[0–63]
DP[0–7]
TA
TEA
Memory Control Signals
Figure 8-1. Single-PowerQUICC II Bus Mode
NOTE
In single-PowerQUICC II bus mode, the PowerQUICC II uses the address
bus as a memory address bus. Slaves cannot use the 60x bus signals because
the addresses have memory timing, not address tenure timing.
8.2.2
60x-Compatible Bus Mode
The 60x-compatible bus mode can include one or more potential external masters (for example, an L2
cache, an ASIC DMA, a high-end processor that implements the PowerPC architecture, or a second
PowerQUICC II). When operating in a multiprocessor configuration, the PowerQUICC II snoops bus
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
8-3
The 60x Bus
an external processor is attached to the PowerQUICC II.
PowerQUICC II
APE
TS
BR
BG
TS
A[0–31]
AP[0–3]
TT[0–4]
TSIZ[0–3]
TBST
CI
Latch
I/O
Latch &
WT
MEM
DRAM MUX
GBL
AACK
ARTRY
DBG
External Device
Memory Control Signals
D[0–63]
BR
BG
DP[0–7]
DBG
TA
TEA
Figure 8-2. 60x-Compatible Bus Mode
8.3
60x Bus Protocol Overview
Typically, 60x bus accesses consist of address and data tenures, which in turn each consist of three
phases—arbitration, transfer, and termination, as shown in Figure 8-3.. The independence of the tenures is
indicated by showing the data tenure overlap the next address tenure, which allows split-bus transactions
to be implemented at the system level in multiprocessor systems. Figure 8-3 shows a data transfer that
consists of a single-beat transfer of as many as 256 bits. Four-beat burst transfers of 32-byte cache blocks
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
8-4
Freescale Semiconductor
The 60x Bus
require data transfer termination signals for each beat of data. Note that the PowerQUICC II supports port
sizes of 8, 16, 32, and 64 bits and requires the additional bus signal, PSDVAL, which is not defined by the
60x bus specification. For more information, see Section 8.5.5, “Port Size Data Bus Transfers and
Data Tenure
Arbitration
1- or 4-Beat Transfer
Termination
Independent Address and Data Tenures
Next Address Tenure
Arbitration
Transfer
Termination
Figure 8-3. Basic Transfer Protocol
The basic functions of the address and data tenures are as follows:
•
Address tenure
— Arbitration: Address bus arbitration signals are used to request and grant address bus
mastership.
— Transfer: After a device is granted address bus mastership, it transfers the address. The address
signals and the transfer attribute signals control the address transfer.
— Termination: After the address transfer, the system acknowledges that the address tenure is
complete or that it must be repeated, signalled by the assertion of the address retry signal
(ARTRY).
•
Data tenure
— Arbitration: After the address tenure begins, the bus device arbitrates for data bus mastership.
— Transfer: After the device is granted data bus mastership, it samples the data bus for read
operations or drives the data bus for write operations.
— Termination: Acknowledgment of a successful data transfer is required after each beat in a data
transfer. In single-beat transactions, the data termination signals also indicate the end of the
tenure. In burst or port-size accesses, data termination signals indicate the completion of
individual beats and, after the final data beat, the end of the tenure.
8.3.1
Arbitration Phase
The external bus design permits one device (either the PowerQUICC II or a bus-attached external device)
to be granted bus mastership at a time. Bus arbitration can be handled either by an external central bus
arbiter or by the internal on-chip arbiter. In the latter case, the system is optimized for three external bus
masters besides the PowerQUICC II. The arbitration configuration (external or internal) is determined at
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
8-5
The 60x Bus
system reset by sampling configuration pins. See Section 4.3.2.2, “60x Bus Arbiter Configuration Register
The PowerQUICC II controls bus access through the bus request (BR) and bus grant (BG) signals. It
determines the state of the address and data bus busy signals by monitoring DBG, TS, AACK, and TA, and
it qualifies them with ABB and DBB.
The following signals are used for address bus arbitration:
•
•
BR (bus request)—A device asserts BR to request address bus mastership.
BG (bus grant)—Assertion indicates that a bus device may, with proper qualification, assume
mastership of the address bus. A qualified bus grant occurs when BG is asserted while ABB and
ARTRY are negated.
•
ABB (address bus busy)—A device asserts ABB to indicate it is the current address bus master.
Note that if all devices assert ABB with TS and would normally negate ABB after AACK is
asserted, the devices can ignore ABB because the PowerQUICC II can internally generate ABB.
The PowerQUICC II’s ABB, if enabled, must be tied to a pull-up resistor.
The following signals are used for data bus arbitration:
•
DBG (data bus grant)—Indicates that a bus device can, with the proper qualification, assume data
bus mastership. A qualified data bus grant occurs when DBG is asserted while DBB and ARTRY
are negated.
•
DBB (data bus busy)—Assertion by the device indicates that the device is the current data bus
master. The device master always assumes data bus mastership if it needs the data bus and is given
a qualified data bus grant (see DBG). Note that if all devices assert DBB in conjunction with
qualified data bus grant and would normally negate DBB after the last TA is asserted, the devices
can ignore DBB because the PowerQUICC II can generate DBB internally. The PowerQUICC II’s
DBB signal, if enabled, must be tied to a pull-up resistor.
The following is a summary of rules for arbitration:
•
Preference among devices is determined at the request level. The PowerQUICC II supports eight
levels of bus requests.
•
When no bus device is requesting the address bus, the PowerQUICC II parks the device selected
in the arbiter configuration register on the bus.
8.3.2
Address Pipelining and Split-Bus Transactions
The 60x bus protocol provides independent address and data bus capability to support pipelined and
split-bus transaction system organizations. Address pipelining allows the next address tenure to begin
before the current data tenure has finished. Although this ability does not inherently reduce memory
latency, support for address pipelining and split-bus transactions can greatly improve effective
bus/memory throughput. These benefits are most fully realized in shared-memory, multiple-master
implementations where bus bandwidth is critical to system performance.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
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Freescale Semiconductor
The 60x Bus
External arbitration (as provided by the PowerQUICC II) is required in systems in which multiple devices
share the system bus. The PowerQUICC II uses the address acknowledge (AACK) signal to control
pipelining. The PowerQUICC II supports both one- and zero-level bus pipelining. One-level pipelining is
achieved by asserting AACK to the current address bus master and granting mastership of the address bus
to the next requesting master before the current data bus tenure has completed. Two address tenures can
occur before the current data bus tenure completes. The PowerQUICC II also supports non-pipelined
accesses.
8.4
Address Tenure Operations
This section describes the three phases of the address tenure—address bus arbitration, address transfer, and
address termination.
8.4.1
Address Arbitration
Bus arbitration can be handled either by an external arbiter or by the internal on-chip arbiter. The
arbitration configuration (external or internal) is chosen at system reset. For internal arbitration, the
PowerQUICC II provides arbitration for the 60x address bus and the system is optimized for three external
bus masters besides the PowerQUICC II. The bus request (BR) for the external device is an external input
to the arbiter. The bus grant signal for the external device (BG) is output to the external device.The BG
signal asserted by PowerQUICC II’s on-chip arbiter is asserted one clock after the current master on the
bus has asserted AACK; therefore, it can be called a qualified BG. Assuming that all potential masters
negate ABB one clock after receiving AACK, the device receiving BG can start the address tenure (by
asserting TS) one clock after receiving BG. In addition to the external signals, there are internal request
and grant signals for the PowerQUICC II processor, communications processor, refresh controller, and the
PCI internal bridge. Bus accesses are prioritized, with programmable priority. When a PowerQUICC II’s
internal master needs the 60x bus, it asserts the internal bus request along with the request level. The arbiter
asserts the internal bus grant for the highest priority request.
The PowerQUICC II supports address bus parking through the use of the parked master bits in the arbiter
configuration register. The PowerQUICC II parks the address bus (asserts the address bus grant signal in
anticipation of an address bus request) to the external master or internal masters. When a device is parked,
the arbiter can hold BG asserted for a device even if that device has not requested the bus. Therefore, when
the parked device needs to perform a bus transaction, it skips the bus request delay and assumes address
bus mastership on the next cycle. For this case, BR is not asserted and the access latency seen by the device
is shortened by one cycle.
The PowerQUICC II and external device bus devices qualify BG by sampling ARTRY in the negated state
prior to taking address bus mastership. The negation of ARTRY during the address retry window (one
cycle after the assertion of AACK) indicates that no address retry is requested. If a device detects ARTRY
asserted, it cannot accept a address bus grant during the ARTRY cycle or the cycle following. A device
that asserts ARTRY due to a modified cache block hit, for example, asserts its bus request during the cycle
after the assertion of ARTRY and assumes bus mastership for the cache block push when it is given a bus
grant.
configured in 60x-compatible bus mode. In this example, PowerQUICC II is initially parked on the bus
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
8-7
The 60x Bus
with BG INT-asserted (note that BG INT is an internal signal not seen by the user at the pins), which lets
it start an address bus tenure by asserting TS. During the same clock cycle, the external master’s bus
request is asserted to request access to the 60x bus, thereby causing the negation of BG INT internally and
the assertion of BG at the pin. Following PowerQUICC II’s address tenure, the external master takes the
bus and initiates its address transaction. The on-chip arbiter samples BR during the clock cycle in which
AACK is asserted; if BR is not asserted (no pending request), it negates BG and asserts the parked bus
grant (BG_INT in this example).
The master can assert BR and receive a qualified bus grant without subsequently using the bus. It can
negate (cancel) BR before accepting a qualified bus grant. This can occur when a replacement copyback
transaction waiting to be run on the bus is killed by a snoop of another bus master. This can also occur
when the reservation set by a pending stwcx. transaction is cancelled by a snoop of another master. In both
cases, the pending transaction by the processor is cancelled and BR is negated.
CLKOUT
BR INT
PowerQUICC II
BG INT
BR
BG
ABB
PowerQUICC I
External
External
ADDR+
TS
AACK
ARTRY
Figure 8-4. Address Bus Arbitration with External Bus Master
8.4.2
Address Pipelining
The PowerQUICC II supports one-level address pipelining by asserting AACK to the current bus master
when its data tenure starts and by granting the address bus to the next requesting device before the current
data bus tenure completes. Address pipelining improves data throughput by allowing the memory-control
hardware to decode a new set of address and control signals while the current data transaction finishes.
The PowerQUICC II pipelines data bus operations in strict order with the associated address operations.
Figure 8-5 shows how address pipelining allows address tenures to overlap the associated data tenures.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
8-8
Freescale Semiconductor
The 60x Bus
CLKOUT
ADDR + ATTR
TS
AACK
DBG
TA
Address
Tenure
Address 1
Address 2
Data Tenure
Data 1
Figure 8-5. Address Pipelining
Data 2
8.4.3
Address Transfer Attribute Signals
During the address transfer, the address is placed on the address signals, A[0–31]. The bus master provides
other signals that characterize the address transfer—transfer type (TT[0–4]), transfer code (TC[0–2]),
transfer size (TSIZ[0–3]), and transfer burst (TBST) signals. These signals are discussed in the following
sections.
8.4.3.1
Transfer Type Signal (TT[0–4]) Encoding
The transfer type signals define the nature of the transfer requested. They indicate whether the operation
is an address-only transaction or whether both address and data are to be transferred. Table 8-2 describes
the PowerQUICC II’s action as master, slave, and snooper.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
8-9
The 60x Bus
Table 8-2. Transfer Type Encoding
PowerQUICC I
I as Snooper
PowerQUICC II
as Slave
2
60x Bus Specification
PowerQUICC II as Bus Master
1
TT[0–4]
Command Transaction Bus Trans.
Transaction Source Action on Hit Action on Slave Hit
00000 Clean block Address
only
Address only dcbst (if enabled)
(if enabled)
Not applicable AACK asserted;
PowerQUICC II takes
no further action.
00100 Flush block Address
only
Address only dcbf (if enabled)
(if enabled)
Not applicable AACK is asserted;
PowerQUICC II takes
no further action.
01000 sync
Address
only
Address only sync (if enabled)
(if enabled)
Not applicable Assert AACK. BG is
negated until
PowerQUICC II
buffers are flushed.
01100 Kill block
10000 eieio
Address
only
Address only dcbz or dcbi (if
Flush, cancel
reservation
AACK is asserted.
enabled)
Address
only
Address only eieio (if enabled)
(if enabled)
Not applicable Assert AACK. BG is
negated until
PowerQUICC II
buffers are flushed.
101 00 Graphics
write
Single-beat Single-beat
ecowx
Not applicable No action.
write
write
(non-GLB)
11000 TLB
invalidate
Address
only
Not applicable Not applicable
Not applicable AACK is asserted;
PowerQUICC II takes
no further action.
11100 Graphics
read
Single-beat Single-beat
eciwx
Not applicable PowerQUICC II takes
no action.
read
read
(non-GBL)
00001 lwarx
Address
Not applicable Not applicable
Not applicable Address-only
operation. AACK is
asserted;
reservation only
set
PowerQUICC II takes
no further action.
00101 Reserved
01001 tlbsync
—
Not applicable Not applicable
Not applicable Not applicable
Not applicable Illegal
Address
only
Not applicable Address-only
operation. AACK is
asserted;
PowerQUICC II takes
no further action.
01101 icbi
Address
only
Not applicable Not applicable
Not applicable Address-only
operation. AACK is
asserted;
PowerQUICC II takes
no further action.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
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Freescale Semiconductor
The 60x Bus
Table 8-2. Transfer Type Encoding (continued)
PowerQUICC I
I as Snooper
PowerQUICC II
as Slave
2
60x Bus Specification
PowerQUICC II as Bus Master
1
TT[0–4]
Command Transaction Bus Trans.
Transaction Source Action on Hit Action on Slave Hit
Not applicable Not applicable Not applicable Illegal
1XX01 Reserved
—
for
customer
00010 WR w/flush Single-beat Single-beat
CI, WT store, or
Flush, cancel
Write, assert AACK
write or
Burst
write
non-processormaster reservation
under
and TA.
00110 WR w/Kill
01010 Read
Burst
Burst
(non-GLB)
Castout, ca-op push, Kill, cancel
Write, assert AACK
and TA.
or snoop copyback
reservation
Single-beat Single-beat
read or burst read
CI load, CI I-fetch or Clean or flush Read, assert AACK
nonprocessor master
and TA.
01110 Read with Burst
Burst
Load miss, store
miss, or I-fetch
Flush
Read, assert AACK
and TA.
intent to
modify
10010 WR w/flush Single-beat Single-beat
stwcx
Flush, cancel
reservation
Write, assert AACK
and TA
atomic
write
write
10110 Reserved
Not
Not applicable Not applicable
Not applicable Illegal
applicable
11010 Read
atomic
Single-beat Single-beat
read or burst read
lwarx (CI load)
Clean or flush Read, assert AACK
and TA
11110 Read with Burst
Burst
lwarx (load miss)
Flush
Read, assert AACK
and TA
intent to
modify
atomic
00011 Reserved
00111 Reserved
—
—
Not applicable Not applicable
Not applicable Not applicable
Not applicable Illegal
Not applicable Illegal
01011 Read with Single-beat Not applicable Not applicable
Clean
Read, assert AACK
and TA
no intent to read or burst
cache
01111 Reserved
—
—
Not applicable Not applicable
Not applicable Not applicable
Not applicable Illegal
Not applicable Illegal
1XX11 Reserved
for
customer
1
2
TT1 can be interpreted as a read-versus-write indicator for the bus.
This column specifies the TT encoding for the general 60x protocol. The processor generates or snoops only a subset
of those encodings.
NOTE
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
8-11
The 60x Bus
•
•
For reads, the processor cleans or flushes during a snoop based on the
TBST input. The processor cleans for single-beat reads (TBST negated)
to emulate read-with-no-intent-to-cache operations.
Castouts and snoop copybacks are generally marked as non-global and
are not snooped (except for reservation monitoring). However, other
masters performing DMA write operations with the same TT encoding
and marked as a global WR operation (whether global or non-global)
will cancel an active reservation during a snoop hit in the reservation
register (independent of a snoop hit in the cache).
•
A non-processor read can cause the internal processor to invalidate the
corresponding cache line if it exists.
8.4.3.2
Transfer Code Signals TC[0–2]
The transfer code signals, TC[0–2], provide supplemental information about the corresponding address
(mainly regarding the source of the transaction). Note that TCx signals can be used with the TT[0–4] and
TBST to further define the current transaction.
Table 8-3. Transfer Code Encoding for 60x Bus
60x Bus
TC[0–2]
Read
Write
000
001
010
011
100
101
110
111
Core data transaction
Core touch load
Core instruction fetch
Reserved
Any write
—
—
—
Reserved
DMA function code 0
DMA function code 1
8.4.3.3
TBST and TSIZ[0–3] Signals and Size of Transfer
As shown in Table 8-4, the transfer size signals (TSIZ[0–3]) and the transfer burst signal (TBST) together
indicate the size of the requested data transfer. These signals can be used with address bits A[27–31] and
the device port size to determine which portion of the data bus contains valid data for a write transaction
or which portion of the bus should contain valid data for a read transaction.
The PowerQUICC II uses four double-word burst transactions for transferring cache blocks. For these
transactions, TSIZ[0–3] are encoded as 0b0010, and address bits A[27–28] determine which double-word
is sent first.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
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Freescale Semiconductor
The 60x Bus
The PowerQUICC II supports critical-word-first burst transactions (double-word-aligned) from the
processor. The PowerQUICC II transfers the critical double word of data first, followed by the double
words from increasing addresses, wrapping back to the beginning of the eight-word block as required.
Table 8-4. Transfer Size Signal Encoding
TBST
TSIZ[0–3]
Transfer Size
Comments
Source
Core and DMA
Negated
Negated
Negated
Negated
Negated
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
1 Byte
2 Bytes
3 Bytes
4 Bytes
5 Bytes
Byte
Half-word
—
Core and DMA
Core and DMA
Core and DMA
Word
Extended 5 bytes
Extended 6 bytes
Extended 7 bytes
SDMA (PowerQUICC II
only)
Negated
Negated
0 1 1 0
0 1 1 1
6 Bytes
7 Bytes
SDMA (PowerQUICC II
only)
SDMA (PowerQUICC II
only)
Negated
Negated
0 0 0 0
1 0 0 1
8 Bytes
Double-word (maximum data bus size)
Extended double double-word
Core and DMA
16 Bytes
SDMA (PowerQUICC II
only)
Negated
Asserted
1 0 1 0
0 0 1 0
24 Bytes
32 bytes
Extended triple double-word
SDMA (PowerQUICC II
only)
Quad double-word (4 maximum data
beats)
Core and DMA
NOTE
The basic coherency size of the bus is 32 bytes for the processor
(cache-block size). Data transfers that cross an aligned 32-byte boundary
must present a new address onto the bus at that boundary for proper snoop
operation, or must operate as non-coherent with respect to the
PowerQUICC II.
8.4.3.4
Burst Ordering During Data Transfers
During burst transfers, 32 bytes of data (one cache block) are transferred to or from the cache. Burst write
transfers are performed zero double-word-first. However, because burst reads are performed
critical-double-word-first, a burst-read transfer may not start with the first double word of the cache block
PowerQUICC II burst ordering.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
8-13
The 60x Bus
Table 8-5. Burst Ordering
Double-Word Starting Address:
Data Transfer
1
A[27–28] = 00
A[27–28] = 01
A[27–28] = 10
A[27–28] = 11
2
1st data beat
2nd data beat
3rd data beat
4th data beat
DW0
DW1
DW2
DW3
DW0
DW2
DW3
DW0
DW1
DW3
DW0
DW1
DW2
DW1
DW2
DW3
1
2
A[27–28] specifies the first double word of the 32-byte block being transferred; any subsequent double words must
wrap-around the block. A[29–31] are always 0b000 for burst transfers by the PowerQUICC II.
DWx represents the double word that would be addressed by A[27–28] = x if a nonburst transfer were performed.
Each data beat is terminated with an assertion of TA.
8.4.3.5 Effect of Alignment on Data Transfers
Table 8-6 lists the aligned transfers that can occur to and from the PowerQUICC II. These are transfers in
which the data is aligned to an address that is an integer multiple of the size of the data. For example,
Table 8-6 shows that 1-byte data is always aligned; however, a 4-byte word must reside at an address that
is a multiple of 4 to be aligned.
In Figure 8-6, Table 8-6, and Table 8-7, OP0 is the most-significant byte of a word operand and OP7 is the
least-significant byte.
Table 8-6. Aligned Data Transfers
Data Bus Byte Lanes
...D31 D32...
B4
Program Transfer
Size
TSIZ[0–3]
A[29–31]
D0...
B0
...D63
B7
B1
B2
B3
B5
B6
1
2
Byte
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 1 0
0 0 1 0
0 0 1 0
0 0 1 0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 0 0
0 1 0
1 0 0
1 1 0
OP0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
OP1
—
—
OP2
—
—
—
—
—
—
—
—
OP3
—
—
—
—
—
—
—
—
OP4
—
—
—
—
—
—
—
—
OP5
—
—
—
—
—
—
—
—
OP6
—
—
—
—
—
—
—
—
OP7
—
Half-Word
OP0
—
OP1
—
—
—
—
—
—
OP2
—
OP3
—
—
—
—
—
—
—
OP4
—
OP5
—
—
—
—
—
—
—
OP6
OP7
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
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Freescale Semiconductor
The 60x Bus
Table 8-6. Aligned Data Transfers (continued)
Data Bus Byte Lanes
...D31 D32...
B4
Program Transfer
Size
TSIZ[0–3]
A[29–31]
D0...
B0
...D63
B1
B2
B3
B5
B6
B7
Word
0 1 0 0
0 1 0 0
0 0 0 0
0 0 0
1 0 0
0 0 0
OP0
—
OP1
—
OP2
—
OP3
—
—
—
—
—
OP4
OP4
OP5
OP5
OP6
OP6
OP7
OP7
Double-Word
OP0
OP1
OP2
OP3
1
OPn: These lanes are read or written during that bus transaction. OP0 is the most-significant byte of a word operand
and OP7 is the least-significant byte.
2
—: These lanes are ignored during reads and driven with undefined data during writes.
The PowerQUICC II supports misaligned memory operations, although they may degrade performance
substantially. A misaligned memory address is one that is not aligned to the size of the data being
transferred (such as, a word read from an odd byte address). The PowerQUICC II’s processor bus interface
supports misaligned transfers within a word (32-bit aligned) boundary, as shown in Table 8-7. Note that
the 4-byte transfer in Table 8-7 is only one example of misalignment. As long as the attempted transfer
does not cross a word boundary, the PowerQUICC II can transfer the data to the misaligned address within
a single bus transfer (for example, a half-word read from an odd byte-aligned address). It takes two bus
transfers to access data that crosses a word boundary.
Due to the performance degradation, misaligned memory operations should be avoided. In addition to the
double-word straddle boundary condition, the processor’s address translation logic can generate
substantial exception overhead when the load/store multiple and load/store string instructions access
misaligned data. It is strongly recommended that software attempt to align code and data where possible.
Table 8-7. Unaligned Data Transfer Example (4-Byte Example)
Data Bus Byte Lanes
...D31 D32...
B3 B4
Program Size of
Word (4 bytes)
TSIZ[1–3]
A[29–31]
D0...
B0
...D63
B7
B1
B2
B5
B6
1
2
Aligned
1 0 0
0 1 1
0 0 1
0 1 0
0 1 0
0 0 1
0 1 1
1 0 0
0 1 1
0 0 1
0 0 0
0 0 1
1 0 0
0 1 0
1 0 0
0 1 1
1 0 0
1 0 0
1 0 1
0 0 0
A
A
A
A
A
—
—
—
—
—
A
—
—
—
—
—
—
A
—
—
—
—
—
—
—
A
Misaligned—1st access
2nd access
—
—
—
—
—
—
—
—
A
A
A
—
A
—
—
—
—
—
—
—
—
—
A
—
A
Misaligned—1st access
2nd access
—
A
—
—
—
—
—
—
—
A
Misaligned—1st access
2nd access
—
A
—
A
—
—
—
—
Aligned
A
A
A
Misaligned—1st access
2nd access
—
—
A
A
A
—
—
—
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
8-15
The 60x Bus
Table 8-7. Unaligned Data Transfer Example (4-Byte Example) (continued)
Data Bus Byte Lanes
Program Size of
Word (4 bytes)
TSIZ[1–3]
A[29–31]
D0...
B0
...D31
B3
D32...
B4
...D63
B7
B1
B2
B5
B6
Misaligned—1st access
2nd access
0 1 0
0 1 0
0 0 1
0 1 1
1 1 0
0 0 0
1 1 1
0 0 0
—
A
—
A
—
—
—
A
—
—
—
—
—
—
—
—
—
—
—
—
A
A
—
A
—
—
—
Misaligned—1st access
2nd access
—
A
—
A
—
1
A: Byte lane used
2
—: Byte lane not used
8.4.3.6
Effect of Port Size on Data Transfers
The PowerQUICC II can transfer operands through its 64-bit data port. If the transfer is controlled by the
internal memory controller, the PowerQUICC II can support 8-, 16-, 32-, and 64-bit data port sizes as
demonstrated in Figure 8-6. The bus requires that the portion of the data bus used for a transfer to or from
a particular port size be fixed. A 64-bit port must reside on data bus bits D[0–63], a 32-bit port must reside
on bits D[0–31], a 16-bit port must reside on bits D[0–15], and an 8-bit port must reside on bits D[0–7].
The PowerQUICC II always tries to transfer the maximum amount of data on all bus cycles: for a word
operation, it always assumes the port is 64 bits wide when beginning the bus cycle; for burst and extended
byte cycles, a 64-bit bus is assumed.
Figure 8-6. shows the device connections on the data bus. Table 8-8 lists the bytes required on the data bus
for read cycles.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
8-16
Freescale Semiconductor
The 60x Bus
Interface Output Register
OP5 OP6 OP7
D[40–47] D[48–55] D[56–63]
OP5 OP6 OP7
64-Bit Port Size
0
31
63
OP0
D[0–7]
OP1
D[8–15]
OP2
D[15–23]
OP3
D[24–31]
OP3
OP4
D[32–39]
OP4
OP0
OP1
OP2
OP0
OP4
OP1
OP5
OP2
OP6
OP3
OP7
32-Bit Port Size
OP0
OP2
OP4
OP6
OP1
OP3
OP5
OP7
16-Bit Port Size
OP0
OP7
8-Bit Port Size
Figure 8-6. Interface to Different Port Size Devices
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
8-17
The 60x Bus
Table 8-8. Data Bus: Read Cycle Requirements and Write Cycle Content
Port Size/Data Bus Assignments
Transfer Address
1
Size
State
64-Bit
32-Bit
16-Bit
8-Bit
TSIZ[0–3] A[29–31]
0–7
8–15 16–23 24–31 32–39 40–47 48–55 56–63 0–7 8–15 16–23 24–31 0–7 8–15 0–7
3
2
Byte
(0001)
000
001
010
011
100
101
110
111
000
001
010
100
101
110
000
001
100
101
000
100
000
OP0
—
OP1
—
—
—
—
—
—
—
—
—
—
—
—
—
OP0
—
—
OP1
—
—
—
—
—
OP0
—
—
OP0
OP1 OP1
OP2
OP3 OP3
OP4
OP5 OP5
OP6
OP7 OP7
—
—
—
—
—
—
—
OP2
—
—
—
—
—
—
—
OP2
—
—
OP2
—
—
—
OP3
—
—
—
—
—
—
—
OP3
—
—
—
OP4
—
—
—
—
OP4
—
—
—
OP4
—
—
—
—
—
OP5
—
—
—
OP5
—
—
—
—
—
—
—
OP6
—
—
—
OP6
—
—
OP6
—
—
—
—
—
—
—
OP7
—
—
—
OP7
—
Half Word
(0010)
OP0 OP1
—
—
—
—
—
OP0 OP1
—
OP0 OP1 OP0
OP1 OP1
—
—
—
—
—
OP1 OP2
—
—
—
—
—
—
—
OP1 OP2
—
—
—
—
—
—
OP2 OP3
—
—
—
—
—
OP2 OP3 OP2 OP3 OP2
—
—
—
—
—
—
—
OP4 OP5
—
—
OP4 OP5
—
—
—
OP4 OP5 OP4
OP5 OP5
—
—
—
—
OP5 OP6
—
—
—
OP5 OP6
—
—
—
—
OP6 OP7
—
OP6 OP7 OP6 OP7 OP6
OP0 OP1 OP0
OP1 OP1
OP4 OP5 OP4
OP5 OP5
OP0 OP1 OP2 OP3 OP0 OP1 OP0
Triple Byte
(0011)
OP0 OP1 OP2
—
—
—
—
—
OP0 OP1 OP2
OP1 OP2 OP3
OP4 OP5 OP6
OP5 OP6 OP7
—
—
—
—
OP1 OP2 OP3
—
—
—
—
—
—
—
—
OP4 OP5 OP6
—
—
—
OP5 OP6 OP7
—
—
Word
(0100)
OP0 OP1 OP2 OP3
—
—
—
—
—
—
—
OP4 OP5 OP6 OP7 OP4 OP5 OP6 OP7 OP4 OP5 OP4
Double
Word
OP0 OP1 OP2 OP3 OP4 OP5 OP6 OP7 OP0 OP1 OP2 OP3 OP0 OP1 OP0
(0000)
1
Address state is the calculated address for port size.
2
OPn: These lanes are read or written during that bus transaction. OP0 is the most-significant byte of a word operand
and OP7 is the least-significant byte.
3
— These lanes are ignored during read cycles and driven with undefined data during write cycles.
8.4.3.7
60x-Compatible Bus Mode—Size Calculation
To comply with the requirements listed in Table 8-6 and Table 8-7, the transfer size and a new address must
be calculated at the termination of each beat of a port-size transaction. In single-PowerQUICC II bus
mode, these calculations are internal and do not constrain the system. In 60x-compatible bus mode, the
external slave or master must determine the new address and size. Table 8-9 describes the address and size
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
8-18
Freescale Semiconductor
The 60x Bus
calculation state machine. Note that the address and size states are for internal use and are not transferred
on the address or TSIZ pins. Extended transactions (16- and 24-byte) are not described here but can be
determined by extending this table for 9-, 10-, 16-, 23-, and 24-byte transactions.
Table 8-9. Address and Size State Calculations
Size State
Address State [0–4]
Port Size
Next Size State
Next Address State [0–4]
Stop
Byte
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
1
x
x
0
0
1
1
0
0
1
1
x
x
x
x
0
0
0
0
0
0
0
0
x
x
0
0
0
x
0
0
0
0
0
0
0
0
x
0
0
x
1
1
1
0
0
0
0
0
x
0
1
1
1
0
0
1
0
1
0
1
0
1
x
x
2-Byte
Byte
Byte
Byte
Byte
Byte
x
x
x
x
x
x
0
1
x
x
1
1
1
1
0
0
0
x
x
Half
x
Stop
3-Byte
Byte
2-Byte
2-Byte
2-Byte
2-Byte
Byte
x
x
x
x
x
x
x
x
x
0
0
1
1
0
0
1
1
0
1
0
1
1
1
1
1
1
0
1
0
0
0
0
0
x
x
x
Half
x
2-Byte
Byte
x
x
2-Byte
x
Word
Byte
Half
Stop
4-Byte
0
0
x
3-Byte
2-Byte
x
x
x
x
x
0
1
1
0
x
Word
Byte
Byte
Half
Stop
5-Byte
6-Byte
1
0
0
1
0
0
0
0
4-Byte
5-Byte
4-Byte
6-Byte
7-Byte
6-Byte
4-Byte
x
x
x
x
x
x
x
x
1
0
1
0
0
0
1
0
1
0
1
0
1
0
0
1
0
0
1
0
0
x
x
7-Byte
8-Byte
Byte
Byte
Half
x
x
x
Word
Double
x
Stop
8.4.3.8
Extended Transfer Mode
The PowerQUICC II supports an extended transfer mode that improves bus performance. This should not
be confused with the extended bus protocol used to support direct-store operations supported in some
earlier processors that implement the PowerPC architecture. The PowerQUICC II can generate 5-, 6-, 7-,
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
8-19
The 60x Bus
16-, or 24-byte extended transfers. These transactions are compatible with the 60x bus, but some slaves or
masters do not support these features. Clear BCR[ETM] to disable this type of transaction. This places the
PowerQUICC II in strict 60x bus mode. The following tables are extensions to Table 8-7, Table 8-8, and
Table 8-10 lists the patterns of the extended data transfer for write cycles when PowerQUICC II initiates
an access. Note that 16- and 24-byte transfers are always eight-byte aligned and use a 64-bit or less port
size.
Table 8-10. Data Bus Contents for Extended Write Cycles
Transfer
Size
Address
State
External Data Bus Pattern
TSIZ[0–3])
A[29–31]
D[0–7] D[8–15] D[16–23] D[24–31] D[32–39] D[40–47] D[48–55] D[56–63]
5 Bytes
(0101)
000
011
000
010
000
001
OP0
OP3
OP0
OP2
OP0
OP1
OP1
OP3
OP1
OP3
OP1
OP1
OP2
—
OP3
OP3
OP3
OP3
OP3
OP3
OP4
OP4
OP4
OP4
OP4
OP4
—
—
—
OP7
—
OP5
OP5
OP5
OP5
OP5
OP6
—
6 Bytes
(0110)
OP2
OP2
OP2
OP2
OP6
OP6
OP6
OP7
—
7 Bytes
(0111)
OP7
Table 8-11 lists the bytes required on the data bus for extended read cycles. Note that 16- and 24-byte
transfers are always 8-byte aligned and use a maximum 64-bit port size.
Table 8-11. Data Bus Requirements for Extended Read Cycles
Port Size/Data Bus Assignments
Addres
Transfer
Size
TSIZ[0–3]
s State
A[29-31
]
64-Bit
32-Bit
16-Bit
8-Bit
0–7 8–15 16–2 24–3 32–3 40–4 48–5 56–6 0–7
8–15
16–2 24–3
0–7
8–15
0–7
3
1
9
7
5
3
3
1
5 Byte
(0101)
000
OP OP OP2 OP3 OP4
—
—
—
OP OP1 OP2 OP3 OP0 OP1 OP0
0
0
1
011
000
—
—
—
OP3 OP4 OP5 OP6 OP7
—
—
—
OP3
—
OP3 OP3
6 Byte
(0110)
OP OP OP2 OP3 OP4 OP5
0
—
—
OP OP1 OP2 OP3 OP0 OP1 OP0
0
1
010
000
—
—
OP2 OP3 OP4 OP5 OP6 OP7
—
—
OP2 OP3 OP2 OP3 OP2
7 Byte
(0111)
OP OP OP2 OP3 OP4 OP5 OP6
0
—
OP OP1 OP2 OP3 OP0 OP1 OP0
0
1
001
—
OP OP2 OP3 OP4 OP5 OP6 OP7
1
—
OP1 OP2 OP3
—
OP1 OP1
Table 8-12 includes added states to the transfer size calculation state machine. Only extended transfers use
these states.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
8-20
Freescale Semiconductor
The 60x Bus
Table 8-12. Address and Size State for Extended Transfers
Size State [0–3]
Address State[0–4]
Port Size
Next Size State [0–3]
Next Address State[0–4]
Half
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1
x
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
x
0
0
0
0
0
0
0
x
1
0
x
1
0
1
0
0
1
0
0
1
1
0
1
1
0
1
x
0
0
1
0
1
0
1
x
1
1
x
0
0
0
0
1
1
0
1
0
1
0
0
1
0
1
x
0
1
0
0
0
0
0
x
Byte
Byte
x
x
x
1
1
0
1
0
0
x
Half
Stop
3-Byte
Byte
Half
Byte
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
1
1
1
0
1
0
0
0
1
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
0
0
0
1
1
0
0
0
0
1
0
1
0
0
0
0
0
0
x
Half
Byte
Byte
x
x
Word
3-Byte
Word
x
x
5-Byte
x
x
x
x
Half
3-Byte
x
x
Word
Byte
x
Word
x
Word
x
Double
Byte
Stop
6-Byte
5-Byte
Word
x
x
x
x
x
x
x
x
0
0
0
0
1
1
1
0
1
1
1
0
0
0
1
0
1
0
0
0
0
x
x
Half
Word
x
x
x
Half
Word
x
Double
Stop
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
8-21
The 60x Bus
Table 8-12. Address and Size State for Extended Transfers (continued)
Size State [0–3]
7-Byte
Address State[0–4]
Port Size
Next Size State [0–3]
Next Address State[0–4]
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
0
0
0
0
0
x
0
0
0
0
0
0
x
0
1
0
1
0
1
x
Byte
6-Byte
x
x
x
x
x
x
x
0
0
0
0
1
1
0
1
1
1
0
0
1
0
0
0
0
0
x
Half
Word
5-Byte
6-Byte
3-Byte
4-Byte
x
x
x
x
Double
Stop
Extended transfer mode is enabled by setting the BCR[ETM].
8.4.4
Address Transfer Termination
Address transfer termination occurs with the assertion of the address acknowledge (AACK) signal, or
retried with the assertion of ARTRY. ARTRY must remain asserted until one clock after AACK; the bus
clock cycle after AACK is called the ARTRY window. The PowerQUICC II controls assertion of AACK
unless the cycle is claimed by an external slave, such as an external L2 cache controller. Following the
assertion of L2_HIT, the L2 cache controller is responsible for asserting AACK. When AACK is asserted
by the external slave, it should be asserted for one clock cycle and then negated for one clock cycle before
entering a high-impedance state. The PowerQUICC II holds AACK in a high-impedance state until it is
required to assert AACK to terminate the address cycle.
The PowerQUICC II uses AACK to enforce a pipeline depth of one to its internal slaves.
8.4.4.1
Address Retried with ARTRY
The address transfer can be terminated with the requirement to retry if ARTRY is asserted during the
address tenure and through the cycle following AACK. The assertion causes the entire transaction (address
and data tenure) to be rerun. As a snooping device, the PowerQUICC II processor asserts ARTRY for a
snooped transaction that hits modified data in the data cache that must be written back to memory, or if the
snooped transaction could not be serviced. As a bus master, the PowerQUICC II responds to an assertion
of ARTRY by aborting the bus transaction and requesting the bus again, as shown in Figure 8-7. Note that
after recognizing an assertion of ARTRY and aborting the current transaction, the PowerQUICC II may
not run the same transaction the next time it is granted the bus.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
8-22
Freescale Semiconductor
The 60x Bus
CLKOUT
BR INT
BG INT
BR
External
BG
ABB
ADDR + ATTR
TS
PowerQUICC II
External
PowerQUICC II
AACK
ARTRY
Figure 8-7. Retry Cycle
As a bus master, the PowerQUICC II recognizes either an early or qualified ARTRY and prevents the data
tenure associated with the retried address tenure. If the data tenure has begun, the PowerQUICC II
terminates the data tenure immediately even if the burst data has been received. If the assertion of ARTRY
is received up to or on the bus cycle as the first (or only) assertion of TA for the data tenure, the
PowerQUICC II ignores the first data beat. If it is a read operation, the PowerQUICC II does not forward
data internally to the cache, execution unit, or any other PowerQUICC II internal storage. This address
retry case succeeds because the data tenure is aborted in time, and the entire transaction is rerun. This retry
mechanism allows the memory system to begin operating in parallel with the bus snoopers, provided
external devices do not present data sooner than the bus cycle before all snoop responses can be determined
and asserted on the bus.
Note that the system must ensure that ARTRY is never asserted later than the cycle of the first or only
assertion of TA (if the PCI controller can initiate global transactions, the system must ensure that ARTRY
is never asserted on the same cycle or later then the first or only assertion of TA). This guarantees the
relationship between TA and ARTRY such that, in case of an address retry, the data may be cancelled in
the chip before it can be forwarded internally to the internal memory resources (registers or cache).
Generally, the memory system must also detect this event and abort any transfer in progress. If this
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
8-23
The 60x Bus
TA/ARTRY relationship is not met, the master may enter an undefined state. Users may use
PPC_ACR[DBGD] to ensure correct operation of the system.
During the clock of a qualified ARTRY, each device master determines whether it should negate BR and
ignore BG on the following cycle. The following cycle is referred to as the window-of-opportunity for the
snooping master. During this window, only the snooping master that asserted ARTRY and requires a snoop
copyback operation is allowed to assert BR. This guarantees the snooping master a window of opportunity
to request and be granted the bus before the just-retried master can restart its transaction. BG is also
blocked in the window-of-opportunity, so the arbiter has a chance to negate BG to an already granted
potential bus master to perform a new arbitration.
Note that in some systems, an external processor may be unable to perform a pending snoop copyback
when a new snoop operation is performed. In this case, the PowerQUICC II requests the window of
opportunity if it hits on the new snooped address. To clear its internal snoop queue, it performs the snoop
copyback operation for the earlier snooped address instead of the current snooped address.
8.4.4.2
Address Tenure Timing Configuration
During address tenures initiated by 60x-bus devices, the timing of the assertion of AACK by the
PowerQUICC II is determined by the BCR[APD] and the pipeline status of the 60x bus. Because the
PowerQUICC II can support one level of pipelining, it uses AACK to control the 60x-bus pipeline
condition. To maintain the one-level pipeline, AACK is not asserted for a pipelined address tenure until
the current data tenure ends. The PowerQUICC II also delays asserting AACK until no more address retry
conditions can occur. Note that the earliest the PowerQUICC II can assert AACK is the clock cycle when
the wait-state values set by BCR[APD] have expired.
BCR[APD] specifies the minimum number of address tenure wait states for address operations initiated
by 60x-bus devices. APD indicates how many cycles the PowerQUICC II should wait for ARTRY, but
because it is assumed that ARTRY can be asserted (by other masters) only on cacheable address spaces,
APD is considered only on transactions that hit a 60x-assigned memory controller bank and that have GBL
asserted during the address phase.
Extra wait states may occur because of other PowerQUICC II configuration parameters. Note that in a
system with an L2 cache, the number of wait states configured by BCR[APD] should be at least as large
as the value needed by the L2 controller to assert hit response. In systems with multiple potential masters,
the number of wait states configured by BCR[APD] should be at least as large as the value the slowest
master would need by to assert a snoop response. For example, additional wait states are required when
the internal processor is in 1:1 clock mode; this case requires at least one wait state to generate the ARTRY
response.
8.4.5
Pipeline Control
The PowerQUICC II supports the two following modes:
•
One-level pipeline mode—To maintain the one-level pipeline, AACK is not asserted for a
pipelined address tenure until the current data tenure ends. In 60x-compatible bus mode, a
two-level pipeline depth can occur (for example, when an external 60x-bus slave does not support
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
8-24
Freescale Semiconductor
The 60x Bus
one-level pipelining). When the internal arbiter counts a pipeline depth of two (two assertions of
AACK before the assertion of the current data tenure) it negates all address bus grant (BG) signals.
•
No-pipeline mode—The PowerQUICC II does not assert AACK until the corresponding data
tenure ends.
8.5
Data Tenure Operations
This section describes the operation of the PowerQUICC II during the data bus arbitration, transfer, and
termination phases of the data tenure.
NOTE: External Master Writes to DPRAM
DPRAM is clocked by the CPM clock and not by the 60x bus clock.
Therefore, data is not latched at the TA assertion cycle during writes to
DPRAM from the external master. Instead, the data is latched earlier. It is
necessary, then, that the external master drive the data bus immediately after
DBG and hold the data bus until after TA.
8.5.1
Data Bus Arbitration
The beginning of an address transfer, marked by the assertion of transfer start (TS), is also an implicit data
bus request provided that the transfer type signals (TT[0–4]) indicate that the transaction is not
address-only.
The PowerQUICC II arbiter supports one external master and uses DBG to grant the external master data
bus.The DBG signals are not asserted if the data bus, which is shared with memory, is busy with a
transaction.
A qualified data bus grant (QDBG) can be expressed as the assertion of DBG while DBB and ARTRY
(associated with the data bus operation) are negated.
Note that the PowerQUICC II arbiter should assert DBG only when it is certain that the first TA will be
asserted with or after the associated ARTRY. The PowerQUICC II DBG is asserted with TS if the data bus
is free and if the PPC_ACR[DBGD] = 0. If PPC_ACR[DBGD] = 1, DBG is asserted one cycle after TS
if the data bus is not busy. The DBG delay should be used to ensure that ARTRY is not asserted after the
first or only TA assertion. For the programming model, see Section 4.3.2.2, “60x Bus Arbiter
Note that DBB should not be asserted after the data tenure is finished. Assertion of DBB after the last TA
causes improper operation of the bus. (PowerQUICC II internal masters do not assert DBB after the last
TA.)
Note the following:
•
External bus arbiters must comply with the following restriction on assertion of DBG which is
connected to the PowerQUICC II. In case the data bus is not busy with the data of a previous
transaction on the bus, external arbiter must assert DBG in the same cycle in which TS is asserted
(by a master which was granted the bus) or in the following cycle. In case the external arbiter
asserts DBG on the cycle in which TS was asserted, PPC_ACR[DBGD] should be zero. Otherwise,
PPC_ACR[DBGD] should be set.
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8-25
The 60x Bus
•
External masters connected to the 60x bus must assert DBB only for the duration of its data tenure.
External masters should not use DBB to prevent other masters from using the data bus after their
data tenure has ended.
8.5.2
Data Streaming Mode
The PowerQUICC II supports a special data streaming mode that can improve bus performance in some
conditions. Generally, the bus protocol requires one idle cycle between any two data tenures. This idle
cycle is essential to prevent contention on the data bus when the driver of the data is changing. However,
when the driver on the data bus is the same for both data tenures, this idle cycle may be omitted.
In data streaming mode, the PowerQUICC II omits the idle cycle where possible. PowerQUICC II
applications often require data stream transfers of more than 4 x 64 bits. For example, the ATM cell’s
payload is 6 x 64 bits. All this data is driven from a single device on the bus, so data-streaming saves a
cycle for such a transfer. When data-streaming mode is enabled, transactions initiated by the core are not
affected, while transactions initiated by other bus masters within the chip omit the idle cycle if the data
driver is the same. Note that data streaming mode cannot be enabled when the PowerQUICC II is in
60x-compatible bus mode and a device that uses DBB is connected to the bus. This restriction is due to the
fact that a PowerQUICC II for which data streaming mode is enabled may leave DBB asserted after the
last TA of a transaction and this is a violation of the strict bus protocol. The data streaming mode is enabled
by setting BCR[ETM].
8.5.3
Data Bus Transfers and Normal Termination
The data transfer signals include D[0–63] and DP[0–7]. For memory accesses, the data signals form a
64-bit data path, D[0–63], for read and write operations.
The PowerQUICC II handles data transfers in either single-beat or burst operations. Single-beat operations
can transfer from 1 to 24 bytes of data at a time. Burst operations always transfer eight words in four
double-word beats. A burst transaction is indicated by the assertion of TBST by the bus master. A
transaction is terminated normally by asserting TA.
The three following signals are used to terminate the individual data beats of the data tenure and the data
tenure itself:
•
•
•
TA indicates normal termination of data transactions. It must always be asserted on the bus cycle
coincident with the data that it is qualifying. It may be withheld by the slave for any number of
clocks until valid data is ready to be supplied or accepted.
Asserting TEA indicates a nonrecoverable bus error event. Upon receiving a final (or only)
termination condition, the PowerQUICC II always negates DBB for one cycle, except when fast
data bus grant is performed.
Asserting ARTRY causes the data tenure to be terminated immediately if the ARTRY is for the
address tenure associated with the data tenure in operation (the data tenure may not be terminated
due to address pipelining). The earliest allowable assertion of TA depends directly on the latest
possible assertion of ARTRY.
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The 60x Bus
Figure 8-8 shows both a single-beat and burst data transfer. The PowerQUICC II asserts TA to mark the
cycle in which data is accepted. In a normal burst transfer, the fourth assertion of TA signals the end of a
transfer.
CLKOUT
ADDR + ATTR
TS
AACK
DBG
TA
PSDVAL
D[0–63]
D0
D1
D2
D3
Figure 8-8. Single-Beat and Burst Data Transfers
8.5.4
Effect of ARTRY Assertion on Data Transfer and Arbitration
The PowerQUICC II allows an address tenure to overlap its associated data tenure. The PowerQUICC II
internally guarantees that the first TA of the data tenure is delayed to be at the same time or after the
ARTRY window (the clock after the assertion of AACK).
8.5.5
Port Size Data Bus Transfers and PSDVAL Termination
The PowerQUICC II can transfer data via data ports of 8, 16, 32, and 64 bits, as shown in Section 8.4.3,
“Address Transfer Attribute Signals.” Single-beat transaction sizes can be 8, 16, 32, 64, 128, and 192 bits;
burst transactions are 256 bits. Single-beat and burst transactions are divided into to a number of
intermediate beats depending on the port size. The PowerQUICC II asserts PSDVAL to mark the cycle in
which data is accepted. Assertion of PSDVAL in conjunction with TA marks the end of the transfer in
single-beat mode. The fourth assertion of PSDVAL in conjunction with TA signals the end of a burst
transfer. Figure 8-9 shows an extended transaction of 4 words to a port size of 32 bits. The single-beat
transaction is translated to four port-sized beats.
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8-27
The 60x Bus
CLKOUT
ADDR + ATTR
TS
AACK
DBG
PSDVAL
TA
D[0–31]
D0
D1
D2
D3
Figure 8-9. 28-Bit Extended Transfer to 32-Bit Port Size
Figure 8-10 shows a burst transfer to a 32-bit port. Each double-word burst beat is divided into two
port-sized beats such that the four double words are transferred in eight beats.
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The 60x Bus
CLKOUT
ADDR + ATTR
TS
AACK
DBG
PSDVAL
TA
D[0–31]
D0
D1
D2
D3
D4
D5
D6
D7
Figure 8-10. Burst Transfer to 32-Bit Port Size
8.5.6
Data Bus Termination by Assertion of TEA
If a device initiates a transaction that is not supported by the PowerQUICC II, the PowerQUICC II signals
an error by asserting TEA. Because the assertion of TEA is sampled by the device only during the data
tenure of the bus transaction, the PowerQUICC II ensures that the device master receives a qualified data
bus grant by asserting DBG before asserting TEA. The data tenure is terminated by a single assertion of
TEA regardless of the port size or whether the data tenure is a single-beat or burst transaction. This
sequence is shown in Figure 8-11.. In Figure 8-11. the data bus is busy at the beginning of the transaction,
thus delaying the assertion of DBG. Note that data errors (parity and ECC) are reported not by assertion of
TEA but by assertion of MCP.
Because the assertion of TEA is sampled by the device only during the data tenure of the bus transaction,
the PowerQUICC II ensures that the device receives a qualified data bus grant by asserting DBG before
asserting TEA. The data tenure is terminated by a single assertion of TEA regardless of the port size or
whether the data tenure is a single-beat or burst transaction. This sequence is shown in Figure 8-11. In
Figure 8-11 the data bus is busy at the beginning of the transaction, thus delaying the assertion of DBG.
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8-29
The 60x Bus
CLKOUT
ADDR + ATTR
For Single
For Burst
TS
AACK
DBG
TA
TEA
Data
Figure 8-11. Data Tenure Terminated by Assertion of TEA
The PowerQUICC II interprets the following bus transactions as bus errors:
•
•
Direct-store transactions, as indicated by the assertion of XATS.
Bus errors asserted by slaves (internal or external).
8.6
Memory Coherency—MEI Protocol
The PowerQUICC II provides dedicated hardware to ensure memory coherency by snooping bus
transactions, by maintaining information about the status of data in a cache block, and by the address retry
capability. Each data cache block includes status bits that support the modified/exclusive/invalid, or MEI,
cache-coherency protocol.
Asserting the global (GBL) output signal indicates whether the current transaction must be snooped by
other snooping devices on the bus. Address bus masters assert GBL to indicate that the current transaction
is a global access (that is, an access to memory shared by more than one device). If GBL is not asserted
for the transaction, that transaction is not snooped. When other devices detect the GBL input asserted, they
must respond by snooping any addresses broadcast. Normally, GBL reflects the M bit value specified for
the memory reference in the corresponding translation descriptor. Care must be taken to minimize the
number of pages marked as global, because the retry protocol discussed in the previous section used to
enforce coherency can require significant bus bandwidth.
When the PowerQUICC II processor is not the address bus master, GBL is an input. The PowerQUICC II
processor snoops a transaction if TS and GBL are asserted together in the same bus clock cycle (a qualified
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The 60x Bus
snooping condition). No snoop update to the PowerQUICC II processor cache occurs if the transaction is
not marked global. This includes invalidation cycles.
When the PowerQUICC II processor detects a qualified snoop condition, the address associated with the
TS is compared against the data cache tags. Snooping completes if no hit is detected. However, if the
address hits in the cache, the PowerQUICC II processor reacts according to the MEI protocol shown in
Figure 8-12. This figure assumes that WIM = 0b001 (memory space is marked for write-back,
caching-allowed, and coherency-enforced modes).
Invalid
SH/CRW
SH/CRW
WM
RM
WH
Modified
Exclusive
SH
RH
RH
WH
SH/CIR
SH = Snoop hit
RH = Read hit
WH = Write hit
WM = Write miss
RM = Read miss
= Snoop push
= Cache line fill
SH/CRW = Snoop hit, cacheable read/write
SH/CIR = Snoop hit, cache-inhibited read
Figure 8-12. MEI Cache Coherency Protocol—State Diagram (WIM = 001)
8.7
Processor State Signals
This section describes the PowerQUICC II’s support for atomic update and memory through the use of the
lwarx/stwcx. instruction pair. It also describes the TLBISYNC input.
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The 60x Bus
8.7.1
Support for the lwarx/stwcx. Instruction Pair
The load word and reserve indexed (lwarx) and the store word conditional indexed (stwcx.) instructions
provide a way to update memory atomically by setting a reservation on the load and checking that the
reservation is still valid before the store is performed. In the PowerQUICC II, reservations are made on
behalf of aligned, 32-byte sections of the memory address space.
The reservation (RSRV) output signal is driven synchronously with the bus clock and reflects the status of
the reservation coherency bit in the reservation address register.
Note that each external master must do its own snooping; the PowerQUICC II does not provide external
reservation snooping.
8.7.2
TLBISYNC Input
The TLBISYNC input permits hardware synchronization of changes to MMU tables when the
PowerQUICC II and another DMA master share the MMU translation tables in system memory. A DMA
master asserts TLBISYNC when it uses shared addresses that the PowerQUICC II could change in the
MMU tables during the DMA master’s tenure.
When the TLBISYNC input is asserted, the PowerQUICC II cannot complete any instructions past a
tlbsync instruction. Generally, during the execution of an eciwx or ecowx instruction, the selected DMA
device should assert the PowerQUICC II’s TLBISYNC signal and hold it asserted during its DMA tenure
if it is using a shared translation address. Subsequent instructions by the PowerQUICC II processor should
include a sync and tlbsync instruction before any MMU table changes are performed. This prevents the
PowerQUICC II from making disruptive table changes during the DMA tenure.
8.8
Little-Endian Mode
The PowerQUICC II supports a little-endian mode in which low-order address bits are operated on
(munged) based on the size of the requested data transfer. This mode allows a little-endian program
running on the processor with a big-endian memory system to offset into a data structure and receive the
same results as it would if it were operating on a true little-endian processor and memory system. For
example, writing a word to memory as a word operation on the bus and then reading in the second byte of
that word as a byte operation on the bus.
NOTE
When the processor is selected for little-endian operation, the bus interface
is still operating in big-endian mode. That is, byte address 0 of a double
word (as selected by A[29–31] on the bus—after the internal address
munge) still selects the most significant (left most) byte of the double word
on D[0–7]. If the processor interfaces with a true little-endian environment,
the system may need to perform byte-lane swapping or other operations
external to the processor.
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Chapter 9
PCI Bridge
NOTE
The functionality described in this chapter is available only on the
MPC8250, the MPC8265, and the MPC8266.
The PCI bridge enables the PowerQUICC II to gluelessly bridge PCI devices to a processor that
implements the PowerPC architecture, to serve as a PCI interface for CompactPCI™ (CPCI) systems or
as a basis for passive PCI NIC implementations. In addition, multiple PowerQUICC II processors can
interface with each other over the PCI bus.
The key features of the PCI bridge are as follows:
•
•
•
•
•
PCI Specification Revision 2.2 compliant and supports frequencies up to 66 MHz
On-chip arbitration
Support for PCI-to-60x-memory and 60x-memory-to-PCI streaming
PCI host bridge or peripheral capabilities
Includes 4 DMA channels for the following transfers:
— PCI-to-60x to 60x-to-PCI
— 60x-to-PCI to PCI-to-60x
— PCI-to-60x to PCI-to-60x
— 60x-to-PCI to 60x-to-PCI
•
Includes all of the configuration registers required by the PCI standard as well as message and
doorbell registers
•
•
Supports the I O standard
2
Hot-Swap friendly (supports the Hot Swap Specification as defined by PICMG 2.1 R1.0 August 3,
1998)
•
•
•
Support for 66 MHz, 3.3 V specification
Uses a buffer pool for the 60x-PCI bus interface
Makes use of the local bus signals to avoid the need for additional pins
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9-1
PCI Bridge
PowerQUICC II
G2 Core
60x
Bus
PCI
Bridge
0
Mux
SDMA
PCI
Bus
Communications
Processor
1
60x-to-Local
Bridge
DPRAM
Module
PCI_MODE
Figure 9-1. PCI Bridge in the PowerQUICC II
PowerQUICC II 60x Bus/Local SDMA
PowerQUICC II
Internal PCI Bridge
60x Interface
I/O Sequencer
Buffer
Pool
Embedded
Utilities
DMA
PCI Interface
I O
2
Regs
PCI Bus
Figure 9-2. PCI Bridge Structure
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PCI Bridge
9.1
Signals
To avoid the need for additional pins, the PCI bridge is designed to make use of the local bus signals.
Therefore, many of these pins perform different functions, depending on how the user configures them.
9.2
Clocking
9.3
PCI Bridge Initialization
The PCI bridge uses fields from the hard reset configuration word (refer to Section 5.4.1, “Hard Reset
Configuration Word”) which are loaded during a hard reset (that is, assertion of the HRESET signal). This
section discusses PCI bridge initialization issues after reset.
The local bus pin configuration (LBPC) field of the hard reset configuration word should be programmed
to 0b01 so that the local bus operates as the PCI bus.
For PCI agent applications, the PCI_RST signal should be connected to the power-on reset (PORESET)
pin of the PowerQUICC II. If the core is disabled, in PCI agent mode, an EEPROM must be provided for
loading the PCI configuration data.
For core-disabled, PCI agent applications, the communications processor (CP) can perform the minimal
initialization of the internal PCI bridge configuration registers required before responding to configuration
cycles. When the auto-load enable (ALD_EN) bit is set in the hard reset configuration word, the CP
automatically loads the PCI configuration data from the EPROM immediately following hard reset. (In
addition to the hard reset configuration word, the PCI configuration register data should be programmed
within the EPROM according to the port size. Refer to configuration register loading in Section 9.11.2.28,
“Initializing the PCI Configuration Registers,” for further details.) To prevent premature accesses,
CFG_LOCK (see Section 9.11.2.22, “PCI Bus Function Register”) is automatically set during hard reset
so that all attempted PCI accesses are retried. The user must re-enable PCI accesses by clearing
CFG_LOCK at the end of the PCI bridge initialization procedure.
In addition to the configuration register programming, several configuration pins are available in PCI
9.4
SDMA Interface
As shown in Figure 9-1, the PCI bridge has an interface to the SDMA controller. The CP can direct the
SDMA controller to bring data from the PCI bus memory/IO space into the dual-port RAM, or vice versa.
The user can choose if the data buffers, buffer descriptors, or any other needed data will reside on the 60x
bus or on the PCI bus. Because the PCI is replacing the local bus interface when PCI_MODE is active, the
PCI path is automatically chosen whenever the choice between 60x and local bus was programmed to
local. When the PCI bridge is disabled (PCI_MODE is negated), the SDMA transfers data to local memory
through the local bus interface whenever the choice is programmed to local. No change occurs when the
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9-3
PCI Bridge
NOTE
Although the user can direct the SDMA to the 60x bus, transactions can be
redirected to the PCI bridge if they fall in one of the PCI windows of the 60x
bus memory map (PCIBR0 or PCIBR1; refer to Section 4.3.4.1, “PCI Base
is not optimal. However, if it is implemented, the user must set strict 60x bus
mode (BCR[ETM] = 0).
9.5
Interrupts from PCI Bridge
Each of the PCI bridge interrupt sources—the PCI error condition detector, the DMA unit, and the message
unit—can generate an interrupt to the SIU interrupt controller. PCI bridge interrupts are reflected in
PCI bridge interrupts can be masked in general with SIMR_H[PCI] (refer to Section 4.3.1.5, “SIU
independently by masking the relevant bits in the following registers—error mask register, DMA mode
register, inbound message interrupt mask register, and the outbound message interrupt mask register. Each
The interrupt service routine can determine the source of the interrupt by reading the status bits of the
following registers—the error status register, the DMA general status register, the inbound message
interrupt status register, and the outbound message interrupt status register.
For PCI interrupt vector calculation, refer to Section 4.2.4, “Interrupt Vector Generation and Calculation.”
For the priority of PCI interrupts, refer to Section 4.3.1.2, “SIU Interrupt Priority Register (SIPRR).”
9.6
60x Bus Arbitration Priority
To prevent 60x bus arbitration deadlock, the PCI bridge should be programmed to have a high arbitration
priority level within the 60x bus. The 60x bus arbitration-level register (PPC_ALRH) should be
programmed so that the PCI request level index (0b0011) has a priority higher than all other 60x bus
masters which address the PCI space through the 60x-PCI bridge (that is, the internal core or any external
masters). Masters which do not perform transactions in the PCI space (through the 60x-PCI bridge) can
have higher priority. Note that the default value of ALRH (0x0126_7893l) does not meet this requirement.
The same guidelines to prevent 60x bus arbitration deadlock apply to the programming of the parked
master. That is, program the parked master in the 60x bus arbiter configuration register
(PPC_ACR[PRKM]) to be the PCI bridge (0b0011); refer to Section 4.3.2.2, “60x Bus Arbiter
9.7
60x Bus Masters
The number of external 60x bus masters allowed access to the PCI bridge is limited by the number of
pending requests that the PCI bridge is able to service. This number depends on the processor type of the
master. For example, up to two second generation (G2) processors that implement the PowerPC
architecture or three third generation (G3) processors can be accommodated.
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PCI Bridge
9.8
CompactPCI Hot Swap Specification Support
CompactPCI is an open specification supported by the PCI Industrial Computer Manufacturers Group
(PICMG) and is intended for embedded applications using PCI. CompactPCI Hot Swap is an extension of
the CompactPCI specification and allows the insertion and extraction (or “hot swapping”) of boards
without adversely affecting system operation.
The Hot Swap specification defines three levels of support:
•
•
•
Hot Swap capable
Hot Swap friendly
Hot Swap ready
The PowerQUICC II is a Hot Swap friendly device, meaning that it supports the hardware and software
connection processes as defined in the Hot Swap specification. This level of support allows the board and
system designers to build full Hot Swap and high availability systems based on the PowerQUICC II device
as a PCI target device. The only compliance exception is that the device pins are not 5-volt tolerant.
Application boards should be used in 3.3V signaling back planes, or add 5-to-3.3 volt signaling voltage
converters, if needed, to be used in 5V back planes.
For more information regarding the Hot Swap process, refer to the Hot Swap Specification PICMG 2.1,
R1.0, August 3, 1998.
9.9
PCI Interface
The PCI bridge connects the processor and memory system to the I/O components via the PCI system bus.
This interface acts as both initiator (master) and target (slave) device. The PCI bridge uses a 32-bit
multiplexed, address/data bus that can run at frequencies up to 66 MHz. The interface provides address
and data parity with error checking and reporting. The interface provides for three physical address
spaces—32-bit address memory, 32-bit address I/O, and PCI configuration space.
The PCI bridge can function as either a host bridge or an agent device. Note that the PCI bridge can be
configured from the PCI bus while in agent mode. An address translation mechanism is provided to map
PCI memory windows between the host and agent.
The following are the major features supported by the PCI interface:
•
•
•
•
•
•
•
•
•
•
PCI Specification Revision 2.2 compliant
On-chip arbitration supports 3 external PCI bus masters (in addition to the PCI bridge itself)
Arbiter supports high-priority request and grant signal pairs
Supports accesses to all PCI address spaces
Supports PCI-to-60x-memory and 60x-memory-to-PCI streaming
Memory prefetching of PCI read accesses and support for delayed read transactions
Supports posting of processor to PCI and PCI to memory writes
Supports selectable snoop
PCI host bridge capabilities
PCI agent mode capabilities which include the ability to configure from a remote host
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PCI Bridge
•
Address translation units for address mapping between host and agent.
Efforts were made to keep the terminology in this chapter consistent with the PCI Specification, revision
documentation for processors that implement the PowerPC architecture (for example, architecture
specification or reference manuals).
Table 9-1. PCI Terminology
Term
Definition
LSB/Lower Order
MSB/High Order
Byte
Represents bit 0 or the bits closest to the LSB
Represents bit 31 or the bits closest to the MSB
Represents 8 bits of information
Word
Represents 16 bits or 2 bytes
Double-Word
Quad-Word
Beat
Represents 32 bits or 2 words or 4 bytes
Represents 64 bits or 2 double-words or 4 words or 8 bytes
Represents any valid data during a data transfer
Represents any 1 or more beat transfers
Burst
Edge/Clock Edge
Cycle/Clock Cycle
Asserted/Negated
Address Phase
Data Phase(s)
Represents the rising edge of the PCI clock
Represents the time period between clock edges
Represents the globally visible state of the signal on the clock edge
Represents the first clock cycle where FRAME is asserted
Represents the clock cycle(s) where IRDY and TRDY are asserted
NOTE: PCI Bridge Signal Naming
PCI bridge signals are defined in most cases with the prefix “PCI_” (for
is not used. For descriptions of PCI bridge signals, refer to Chapter 6,
9.9.1
PCI Interface Operation
The following sections discuss the operation of the PCI bus.
9.9.1.1 Bus Commands
PCI bus commands indicate the type of transaction occurring on the bus. These commands are encoded on
PCI_C/BE[3-0] during the address phase of the transaction. PCI bus commands are described in Table 9-2.
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PCI Bridge
Table 9-2. PCI Command Definitions
Supported as:
PCI_C/BE[3-0]
Command Type
Definition
Initiator Target
0b0000
Interrupt acknowledge
Special cycle
YES
NO
A read implicitly addressed to the system interrupt
controller. The size of the vector to be returned is
indicated on the byte enables after the address phase.
0b0001
YES
NO
Provides a simple message broadcast mechanism. See
0b0010
0b0011
0b010x
0b0110
I/O read
I/O write
—
YES
YES
—
NO
NO
—
Accesses agents mapped in I/O address space.
Accesses agents mapped in I/O address space.
Reserved. No response occurs.
Memory read
YES
YES
Accesses agents mapped in memory address space. A
read from prefetchable space, when seen as a target,
fetches a cache line of data (32 bytes) from the starting
address, even though all 32 bytes may not actually be
sent to the initiator.
0b0111
0b100x
0b1010
Memory write
—
YES
—
YES
—
Accesses agents mapped in memory address space.
Reserved. No response occurs.
Configuration read
YES
YES
Accesses the configuration space of each agent. An
agent is selected when its IDSEL signal is asserted. See
more detail of configuration accesses. As a target, a
configuration read is only accepted if the PCI bridge is
configured to be in agent mode.
0b1011
Configuration write
YES
YES
Accesses the configuration space of each agent. An
agent is selected when its IDSEL signal is asserted. See
a target, a configuration write is only accepted if the PCI
bridge is configured to be in agent mode.
0b1100
0b1101
0b1110
Memory read multiple
Dual address cycle
Memory read line
YES
NO
YES
NO
Causes a prefetch of the next cache line.
Transfers an 8 byte address to devices.
YES
YES
Indicates that the initiator intends to transfer an entire
cache line of data.
0b1111
Memory write and
invalidate
NO
YES
Indicates that the initiator will transfer an entire cache line
of data, and if PCI has any cacheable memory, this line
needs to be invalidated.
9.9.1.2
PCI Protocol Fundamentals
The bus transfer mechanism on the PCI bus is called a burst. A burst is comprised of an address phase and
one or more data phases.
All signals are sampled on the rising edge of the PCI clock. Each signal has a setup and hold window with
respect to the rising clock edge, in which transitions are not allowed. Outside this aperture, signal values
or transitions have no significance.
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PCI Bridge
9.9.1.2.1
Basic Transfer Control
PCI data transfers are controlled with three fundamental signals:
•
•
•
FRAME is driven by an initiator to indicate the beginning and end of a transaction.
IRDY (initiator ready) is driven by an initiator, allowing it to force wait cycles.
TRDY (target ready) is driven by a target, allowing it to force wait cycles.
The bus is idle when both FRAME and IRDY are negated. The first clock cycle in which FRAME is
asserted indicates the beginning of the address phase. The address and the bus command code are
transferred in that cycle. The next cycle ends the address phase and begins the data phase.
During the data phase, data is transferred in each cycle that both IRDY and TRDY are asserted. Once the
PCI bridge, as an initiator, has asserted IRDY it does not change IRDY or FRAME until the current data
phase completes, regardless of the state of TRDY. Once the PCI bridge, as a target, has asserted TRDY or
STOP it does not change DEVSEL, TRDY, or STOP until the current data phase completes.
When the PCI bridge (as a master) intends to complete only one more data transfer, FRAME is negated
and IRDY is asserted (or kept asserted) indicating the initiator is ready. After the target indicates it is ready
(TRDY asserted) the bus returns to the idle state.
9.9.1.2.2
Addressing
The PCI specification defines three physical address spaces—memory, I/O, and configuration. The
memory and I/O address spaces are standard for all systems. The configuration address space has been
defined specifically to support PCI hardware configuration. Each PCI device decodes the address for each
PCI transaction with each agent responsible for its own address decode.
The information contained in the two lower address bits (AD1 and AD0) depends on the address space. In
the I/O address space, all 32 address/data lines provide the full byte address. AD[1-0] are used for the
generation of DEVSEL and indicate the least significant valid byte involved in the transfer. Once a target
has claimed an I/O access, it first determines if it can complete the entire access as indicated by the byte
enable signals. If all the selected bytes are not in the address range, the entire access should not be
completed; that is, the target should not transfer any data and should terminate the transaction with a
In the configuration address space, accesses are decoded to a double-word address using AD[7-2]. An
agent determines if it is the target of the access when a configuration command is decoded, IDSEL is
asserted, and AD[1-0] are 0b00; otherwise, the agent ignores the current transaction. The PCI bridge
determines a configuration access is for a device on the PCI bus by decoding a configuration command.
When in agent mode, the PCI bridge responds to host-generated PCI configuration cycles when its IDSEL
is asserted during a configuration cycle.
For memory accesses, the double-word address is decoded using AD[31–2]; thereafter, the address is
incremented internally by one double-word (4 bytes) until the end of the burst transfer. Another initiator
in a memory access should drive 0b00 on AD[1-0] during the address phase to indicate a linear
incrementing burst order. The PCI bridge checks AD[1-0] during a memory command access and provides
the linear incrementing burst order. On reads, if AD[1-0] is 0b10, which represents a cache line wrap, the
PCI bridge linearly increments the burst order starting at the critical word, wraps at the end of the cache
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PCI Bridge
line, and disconnects after reading one cache line. If AD[1-0] is 0bx1 (a reserved encoding) and the
PCI_C/BE[3-0] signals indicate a memory transaction, it executes a target disconnect after the first data
phase is completed. Note that AD[1-0] are included in parity calculations.
9.9.1.2.3
Byte Enable Signals
The byte enable signals (BE[3-0]) indicate which byte lanes carry valid data. The byte enable signals may
enable different bytes for each of the data phases. The byte enable signals are valid on the edge of the clock
that starts each data phase and remain valid for the entire data phase.
If the PCI bridge, as a target, sees no byte enable signals asserted, it completes the current data phase with
no permanent change. This implies that on a read transaction, the PCI bridge expects the data not to be
changed, and on a write transaction, the data is not stored.
9.9.1.2.4
Bus Driving and Turnaround
The turnaround-cycle is one clock cycle and is required to avoid contention. This cycle occurs at different
times for different signals. IRDY, TRDY, and DEVSEL use the address phase as their turnaround-cycle.
FRAME, PCI_C/BE[3-0], and AD[31-0] use the idle cycle between transactions as their turnaround-cycle.
(An idle cycle in PCI is when both FRAME and IRDY are negated.)
Byte lanes not involved in the current data transfer are driven to a stable condition even though the data is
not valid.
9.9.1.3
Bus Transactions
The timing diagrams in this section show the relationship of significant signals involved in bus
transactions.
Note the following conventions:
•
•
•
•
•
When a signal is drawn as a solid line, it is actively being driven by the current initiator or target.
When a signal is drawn as a dashed line, no agent is actively driving it.
Three-stated signals with slashes between the two rails have indeterminate values.
The terms ‘edge’ and ‘clock edge’ refer to the rising edge of the clock.
The terms ‘asserted’ and ‘negated’ refer to the globally visible state of the signal on the clock edge,
and not to signal transitions.
•
The symbol
represents a turnaround-cycle.
9.9.1.3.1
Read and Write Transactions
Both read and write transactions begin with an address phase followed by a data phase. The address phase
occurs when FRAME is asserted for the first time, and the AD[31-0] signals contain a byte address and
the PCI_C/BE[3-0] signals contain a bus command. The data phase consists of the actual data transfer and
possible wait cycles; the byte enable signals remain actively driven from the first clock of the data phase
through the end of the transaction.
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PCI Bridge
A read transaction starts when FRAME is asserted for the first time and the PCI_C/BE[3-0] signals
PCI_CLK
AD[31:0]
PCI_C/BE[3:0]
FRAME
ADDR
CMD
DATA
BYTE ENABLES
IRDY
DEVSEL
TRDY
Figure 9-3. Single Beat Read Example
Figure 9-4 shows an example of a burst read transaction.
PCI_CLK
AD[31:0]
PCI_C/BE[3:0]
FRAME
ADDR
CMD
DATA1
DATA2
BYTE ENABLES 2
BYTE ENABLES 1
IRDY
DEVSEL
TRDY
Figure 9-4. Burst Read Example
During the turnaround-cycle following the address phase, the PCI_C/BE[3-0] signals indicate which byte
lanes are involved in the data phase. The turnaround-cycle must be enforced by the target with the TRDY
signal if using fast DEVSEL assertion. The earliest the target can provide valid data is one cycle after the
turnaround-cycle. The target must drive the AD[31-0] signals when DEVSEL is asserted.
The data phase completes when data is transferred, which occurs when both IRDY and TRDY are asserted
on the same clock edge. When either is negated a wait cycle is inserted and no data is transferred. To
indicate the last data phase IRDY must be asserted when FRAME is negated.
A write transaction starts when FRAME is asserted for the first time and the PCI_C/BE[3-0] signals
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PCI Bridge
PCI_CLK
AD[31:0]
ADDR
CMD
DATA
PCI_C/BE[3:0]
FRAME
BYTE ENABLES
IRDY
DEVSEL
TRDY
Figure 9-5. Single Beat Write Example
Figure 9-6 shows an example of a burst write transaction.
PCI_CLK
AD[31:0]
PCI_C/BE[3:0]
FRAME
ADDR
CMD
DATA1
BEs 1
DATA2
BEs 2
DATA3
BEs 3
DATA4
BEs 4
IRDY
DEVSEL
TRDY
Figure 9-6. Burst Write Example
A write transaction is similar to a read transaction except no turnaround cycle is needed following the
address phase because the initiator provides both address and data. Data phases are the same for both read
and write transactions.
9.9.1.3.2
Transaction Termination
The termination of a PCI transaction is orderly and systematic, regardless of the cause of the termination.
All transactions end when FRAME and IRDY are both negated, indicating the idle cycle.
The PCI bridge as an initiator terminates a transaction when FRAMEis negated and IRDY is asserted. This
indicates that the final data phase is in progress. The final data transfer occurs when both TRDY and IRDY
are asserted. A master-abort is an abnormal case of an initiated termination. If the PCI bridge detects that
DEVSEL has remained negated for more than four clocks after the assertion of FRAME, it negates
FRAME and then, on the next clock, negates IRDY. On aborted reads, the PCI bridge returns
0xFFFF_FFFF. The data is lost on aborted writes.
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PCI Bridge
When the PCI bridge as a target needs to suspend a transaction, it asserts STOP. Once asserted, STOP
remains asserted until FRAME is negated. Depending on the circumstances, data may or may not be
transferred during the request for termination. If TRDY and IRDY are asserted during the assertion of
STOP, data is transferred. This type of target-initiated termination is called a ‘disconnect B,’ shown in
Figure 9-7. If TRDY is asserted when STOP is asserted but IRDY is not, TRDY must remain asserted until
IRDY is asserted and the data is transferred. This is called a “disconnect A” target-initiated termination,
transferred, and the initiator therefore does not have to wait for a final data transfer (see the ‘retry’ diagram
PCI_CLK
FRAME
IRDY
DEVSEL
TRDY
STOP
Disconnect A
Disconnect B
PCI_CLK
Retry
PCI_CLK
FRAME
FRAME
IRDY
IRDY
DEVSEL
DEVSEL
TRDY
STOP
TRDY
STOP
Latency disconnect
Figure 9-7. Target-Initiated Terminations
Target abort
Note that when an initiator is terminated by STOP, it must negate its REQx signal for a minimum of two
PCI clocks (of which one clock is needed for the bus to return to the idle state). If the initiator intends to
complete the transaction, it should reassert its REQx immediately following the two clocks or potential
starvation may occur. If the initiator does not intend to complete the transaction, it can assert REQx
whenever it needs to use the PCI bus again.
The PCI bridge terminates a transaction in the following cases:
•
Eight PCI clock cycles have elapsed between data phases. This is a ‘latency disconnect’ (see
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PCI Bridge
•
•
AD[1-0] is 0bx1 (a reserved burst ordering encoding) during the address phase and one data phase
has completed.
The PCI command is a configuration command and one data phase has completed when a
streaming transaction crosses a 4K page boundary.
•
•
A streaming transaction runs out of I/O sequencer buffer entries.
A cache line wrap transaction has completed a cache line transfer.
Another target-initiated termination is the retry termination. Retry refers to termination requested because
the target is currently in a state where it is unable to process the transaction. This can occur because no
buffer entries are available in the I/O sequencer, or the sixteen clock latency timer has expired without
transfer of the first data. The target latency timer of the PCI bridge can be optionally disabled see
When the PCI bridge is in host mode it does not respond to any PCI configuration transactions. When the
PCI bridge is in agent mode and AGENT_CFG_LOCK is set (refer to Section 9.11.2.22, “PCI Bus
Function Register”) the PCI bridge will retry all configuration transactions. Note that all retried accesses
Note that because a target can determine whether or not data is transferred (when both IRDY and TRDY
are asserted), if it wants to do only one more data transfer and then stop, it may assert TRDY and STOP at
the same time.
Target-abort refers to the abnormal termination that is used when a fatal error has occurred, or when a
target will never be able to respond. Target-abort is indicated by the fact that STOP is asserted and
DEVSEL is negated. This indicates that the target requires the transaction to be terminated and does not
want the transaction tried again. Note that any transferred data may have been corrupted.
The PCI bridge terminates a transaction with target-abort in the case in which it is the intended target of a
read transaction from system memory and the data from memory is corrupt. If the PCI bridge is the
intended target of a transaction and an address parity error occurs, or a data parity error occurs on a write
transaction to system memory, it continues the transaction on the PCI bus but aborts internally. The PCI
bridge does not target-abort in this case.
If the PCI bridge is mastering a transaction and the transaction terminates with a target-abort, undefined
data will be returned on a read and write data will be lost. An example of a target-abort is shown in
An initiator may retry any target disconnect accesses, except target-abort, at a later time starting with the
address of the next non-transferred data. Retry is actually a special case of disconnect where no data
transfer occurs at all and the initiator must start the entire transaction over again.
9.9.1.4
Other Bus Operations
The following sections provide information on additional PCI bus operations.
9.9.1.4.1
Device Selection
As a target, the PCI bridge drives DEVSEL one clock following the address phase as indicated in the
configuration space status register; see Section 9.11.2.4, “PCI Bus Status Register.” The PCI bridge as a
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PCI Bridge
target qualifies the address/data lines with FRAME before asserting DEVSEL. DEVSEL is asserted at or
before the clock edge at which the PCI bridge enables its TRDY, STOP, or data (for a read). DEVSEL is
not negated until FRAME is negated, with IRDY asserted and either STOP or TRDY asserted. The
As an initiator, if the PCI bridge does not see the assertion of DEVSEL within 4 clocks of FRAME, it
terminates the transaction with a master-abort as described in Section 9.9.1.3.2, “Transaction
9.9.1.4.2
Fast Back-to-Back Transactions
In the two types of fast back-to-back transactions, the first type places the burden of avoiding contention
on the initiator while the second places the burden on all potential targets. The PCI bridge as a target
supports both types of fast back-to-back transactions but does not support them as an initiator. The PCI
bridge as a target has the fast back-to-back enable bit hardwired to one, or enabled; see Table 9-18.
For the first type (governed by the initiator), the initiator may only run a fast back-to-back transaction to
the same target. For the second type, when the PCI bridge detects a fast-back-to-back operation and did
not drive DEVSEL in the previous cycle, it delays the assertion of DEVSEL and TRDY for one cycle to
allow the other target to get off the bus.
9.9.1.4.3
Data Streaming
The PCI bridge provides data streaming for PCI transactions to and from prefetchable memory. In other
words, when the PCI bridge is a target for a PCI initiated transaction, it supplies or accepts multiple cache
lines of data without disconnecting. For PCI transactions to non-prefetchable space, the PCI bridge
disconnects after the first data phase so that no streaming can occur.
For PCI memory reads, streaming is achieved by performing speculative reads from memory in
prefetchable space. A block of memory can be marked as prefetchable by setting the prefetch bit in the
•
•
•
When reads do not alter the contents of memory (reads have no side effects)
When reads return all bytes regardless of the byte enable signals
When writes can be merged without causing errors
For a memory read command or a memory read line command, the PCI bridge reads one cache line from
memory. If the PCI read or read line transaction crosses a cache line boundary, the PCI bridge starts the
read of a new cache line. For a memory read multiple command, the PCI bridge reads two cache lines from
memory. When the PCI transaction finishes the read for the first cache line, the PCI bridge performs a
speculative read of a third cache line. The PCI bridge continues this prefetching until the end of the
transaction.
For PCI writes to memory, streaming is achieved by buffering the transaction in the space available within
the I/O sequencer. This allows PCI memory writes to execute with no wait states.
A disconnect occurs if the PCI bridge runs out of buffer space on writes, or the PCI bridge cannot supply
consecutive data beats for reads within eight PCI bus clocks of each other. A disconnect also occurs if the
transaction crosses a 4K page boundary.
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PCI Bridge
For core- or DMA-initiated transfers, the PCI bridge streams over cache line boundaries if the prefetch bit
in the corresponding outbound ATU is enabled and the address space identified by the outbound ATU is
marked as PCI memory space.
9.9.1.4.4
Host Mode Configuration Access
The PCI bridge provides two types of configuration accesses to support hierarchical bridges. To access
configuration space, a value is written to the CONFIG_ADDR register specifying which PCI bus, which
device, and which configuration register to be accessed.
When the PCI bridge sees an access that falls inside the double-word beginning at the CONFIG_DATA
address, it checks the enable bit, the device number and the bus number in the CONFIG_ADDR register.
If the enable bit is set and the device number is not equal to all ones, a configuration cycle translation is
performed. When the device number field is equal to all ones, it has a special meaning (see
the system. Bits 15 through 11 choose a specific device on the bus. Bits 10 through 8 choose a specific
function in the requested device. Bits 7 through 2 choose a DWORD in the device’s configuration space.
Bit 31 is an enable flag for determining when accesses to CONFIG_DATA should be translated to
configuration cycles.
31 30
24 23
16 15
11 10
8
7
2
1
0
Function
number
E
—
Bus number
Device number
Register number
0
0
31
11 10
2
1
0
Only one bit is set at a time (for IDSEL)
Function register
0
0
Figure 9-8. PCI Configuration Type 0 Translation
(Top = CONFIG_ADDR) (Bottom = PCI Address Lines)
There are two types of translations supported:
•
Type 0 translations—For when the device is on the PCI bus connected to the PCI bridge.
lines on the PCI bus.)
•
Type 1 translations—For when the device is on another bus somewhere behind the PCI bridge.
For Type 0 translations, the PCI bridge decodes the device number field to assert the appropriate IDSEL
line and perform a configuration cycle on the PCI bus with AD[1-0] as 0b00. All 21 IDSEL bits are
decoded, starting with bit AD[11]. That is, if the device number field contains 0b01011, AD[11] on the
PCI bus is set. The IDSEL lines are bit-wise associated with increasing values for the device number such
that AD[12] corresponds to 0b01100, and so on up to bit 30. AD[31] is selected with 0b01010. A device
number of 0b11111 indicates a special cycle. Device number 0b00000 is used for configuring the PCI
bridge itself. Bits 10 through 8 are copied to the PCI bus as an encoded value for components which
contain multiple functions. Bits 7 through 2 are also copied onto the PCI bus. The PCI bridge implements
address stepping on configuration cycles so that the target’s IDSEL, which is connected directly to one of
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PCI Bridge
the AD lines, reaches a stable value. This means that a valid address and command are driven on the AD
and PCI_C/BE lines one cycle before the assertion of FRAME.
For Type 1 translations, the PCI bridge copies the contents of the CONFIG_ADDR register directly onto
the PCI address/data lines during the address phase of a configuration cycle, with the exception that
AD[1-0] contains 0b01 (not 0b00 as in Type 0 translations).
NOTE
Due to design constraints, the software must write a value to the
CONFIG_ADDR register prior to each access to the CONFIG_DATA
register, even if the address was not changed.
When the PowerQUICC II is configured as a host device, it sometimes needs to perform configuration
reads from unpopulated PCI slots (as part of the system configuration). To avoid getting a machine check
interrupt, the following steps should be taken:
1. Mask the “PCI No response” bit in the error mask register (clear bit 3). Refer to Section 9.11.1.9,
2. Make the PCI configuration reads.
3. Clear bit 3 in the error status register (by writing 0x08).
4. Unmask (write'1') bit 3 in the error mask register. Refer to Section 9.11.1.10, “Error Mask Register
(EMR).”
9.9.1.4.5
Agent Mode Configuration Access
When the PCI bridge is configured as an agent device, it responds to remote host generated PCI
configuration accesses to the PCI interface. This is indicated by decoding the configuration command
along with the PCI bridge's IDSEL being asserted. A remote host can access the 256-byte PCI
configuration area (Figure 9-32) and the memory-mapped configuration registers within the PCI bridge.
9.9.1.4.6
Special Cycle Command
A special cycle command contains no explicit destination address but is broadcast to all PCI agents. Each
receiving agent must determine whether the message is applicable to itself. No assertion of DEVSEL in
response to a special cycle command is necessary.
A special cycle command is like any other bus command in that it has an address phase and a data phase.
The address phase starts like all other commands with the assertion of FRAME and completes when
FRAME and IRDY are negated. Special cycles terminate with a master-abort. (In the special cycle case,
the received-master-abort bit in the configuration status register is not set.)
The address phase contains no valid information other than the command field. Even though there is no
explicit address, the address/data lines are driven to a stable state and parity is generated. During the data
phase, the address/data lines contain the message type and an optional data field. The message is encoded
on the sixteen least-significant bits (AD[15-0]). The data field is encoded on AD[31-16]. When running a
special cycle, the PCI bridge can insert wait states, but because no specific target is addressed, the message
and data are valid on the first clock IRDY is asserted.
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PCI Bridge
When the CONFIG_ADDRESS register gets written with a value such that the bus number matches the
bridge’s bus, the device number is all ones, the function number is all ones and the register number is zero,
the next time the CONFIG_DATA register is accessed the PCI bridge does either a special cycle or an
interrupt acknowledge command. When the CONFIG_DATA register is written, the PCI bridge generates
a special cycle encoding on the command/byte enable lines during the address phase, and drives the data
from the CONFIG_DATA register onto the address/data lines during the first data phase.
If the bus number field of the CONFIG_ADDRESS does not match one of the PCI bridge’s bus numbers,
the PCI bridge passes the write to CONFIG_DATA on through to the PCI bus as a type 1 configuration
cycle like any other time the bus number field does not match.
9.9.1.4.7
Interrupt Acknowledge
When the CONFIG_ADDRESS register gets written with a value such that the bus number is 0x00, the
device number is all ones, the function number is all ones and the register number is zero, the next time
the CONFIG_DATA register is accessed the PCI bridge does either a special cycle command or an
interrupt acknowledge command. When the CONFIG_DATA register is read, the PCI bridge generates an
interrupt acknowledge command encoding on the command/byte enable lines during the address phase.
During the address phase, AD[31-0] do not contain a valid address but are driven with stable data and valid
parity (PAR). During the data phase, the byte enable signals determine which bytes are involved in the
transaction. The interrupt vector must be returned when TRDY is asserted.
An interrupt acknowledge transaction can also be issued on the PCI bus by reading from the
PCI_INT_ACK register.
9.9.1.5
Error Functions
This section discusses PCI bus errors.
9.9.1.5.1
Parity
During valid 32-bit address and data transfers, parity covers all 32 address/data lines and the 4
command/byte enable lines regardless of whether or not all lines carry meaningful information. Byte lanes
not actually transferring data are driven with stable (albeit meaningless) data and are included in the parity
calculation. During configuration, special cycle or interrupt acknowledge commands, some address lines
are not defined but are still driven to stable values and included in the parity calculation.
Even parity is calculated for all PCI operations: the value of PAR is generated such that the number of ones
on AD[31-0], PCI_C/BE[3-0] and PAR equals an even number. PAR is driven when the address/data lines
are driven and follow the corresponding address or data by one clock.
The PCI bridge checks the parity after all valid address phases (the assertion of FRAME) and for valid data
transfers (IRDY and TRDY asserted) involving the PCI bridge. When an address or data parity error is
detected, the detected-parity-error bit in the configuration space status register is set (see Section 9.11.2.4,
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PCI Bridge
9.9.1.5.2
Error Reporting
Except for setting the detected-parity-error bit, all parity error reporting and response is controlled by the
parity-error-response bit is cleared, the PCI bridge completes all transactions regardless of parity errors
(address or data). If the bit is set, the PCI bridge asserts PERR two clocks after the actual data transfer in
which a data parity error is detected, and keeps PERR asserted for one clock. The PCI bridge asserts PERR
when acting as an initiator during a read transaction or as a target involved in a write to system memory.
Figure 9-9 shows the possible assertion points for PERR if the PCI bridge detects a data parity error.
PCI_CLK
AD[31:0]
PCI_C/BE[3:0]
PAR
ADDR
CMD
DATA
BEs
ADDR
CMD
DATA
BEs
FRAME
IRDY
DEVSEL
TRDY
PERR
SERR
Figure 9-9. PCI Parity Operation
As an initiator, the PCI bridge attempts to complete the transaction on the PCI bus if a data parity error is
detected and sets the data-parity-reported bit in the configuration space status register. If a data parity error
occurs on a read transaction, the PCI bridge aborts the transaction internally. As a target, the PCI bridge
completes the transaction on the PCI bus even if a data parity error occurs. If parity error occurs during a
write to system memory, the transaction completes on the PCI bus but is aborted internally, insuring that
potentially corrupt data does not go to memory.
When the PCI bridge asserts SERR, it sets the signaled-system-error bit in the configuration space status
register. Additionally, if the error is an address parity error, the parity-error-detected bit is set; reporting an
address parity error on SERR is conditioned on the parity-error-response bit being enabled in the command
register. SERR is asserted when the PCI bridge detects an address parity error while acting as a target. The
system error is passed to the PCI bridge’s interrupt processing logic to assert MCP. Figure 9-9 shows where
the PCI bridge could detect an address parity error and assert SERR or where the PCI bridge, acting as an
initiator, checks for the assertion of SERR signaled by the target detecting an address parity error.
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PCI Bridge
As a target that asserts SERR on an address parity, the PCI bridge completes the transaction on the PCI
bus, aborting internally if the transaction is a write to system memory. If PERR is asserted during a PCI
bridge write to PCI, the PCI bridge attempts to continue the transfer, allowing the target to abort/disconnect
if desired. If the PCI bridge detects a parity error on a read from PCI, the PCI bridge aborts the transaction
internally and continues the transfer on the PCI bus, allowing the target to abort/disconnect if desired.
In all cases of parity errors on the PCI bus, regardless of the parity-error-response bit, information about
the transaction is logged in the PCI error control capture register, the PCI error address capture register and
the PCI error data capture register; MCP is also asserted to the core as an option.
9.9.2
PCI Bus Arbitration
The PCI bus arbitration approach is access-based. Bus masters must arbitrate for each access performed
on the bus. PCI uses a central arbitration scheme where each master has its own unique request (REQx)
output and grant (GNTx) input signal. A simple request-grant handshake is used to gain access to the bus.
Arbitration for the bus occurs during the previous access so that no PCI bus cycles are consumed waiting
for arbitration (except when the bus is idle).
The PCI bridge provides arbitration for three external PCI bus masters (besides the PCI bridge itself) by
using the REQ0, REQ1, and REQ2 signals and generating the GNT0, GNT1, and GNT2 signals.
During reset, the PCI bridge samples the PCI_CFG[1] pin (and programs the PCI_ARB_DIS bit
accordingly) to determine if the arbiter is enabled or disabled. The arbiter can also be enabled or disabled
by directly programming the PCI_ARB_DIS bit in the arbiter configuration register (see
If the arbiter is disabled, the PCI bridge uses REQ0 to issue requests to an external arbiter, and uses GNT0
to receive grants from the external arbiter.
The PCI bridge implements a two-level priority, round-robin arbitration algorithm. The priority level for
the different masters can be programmed in the arbiter configuration register (see Section 9.11.2.23, “PCI
9.9.2.1
Bus Parking
When no devices are requesting the bus, the bus is granted, or parked, for a specified device to prevent the
AD, PCI_C/BE and PAR signals from floating. The PCI bridge can be configured to either park on the PCI
bridge or park on the last master to use the bus by programming the parking-mode bit in the arbiter
9.9.2.2
Arbitration Algorithm
The arbitration algorithm implemented is round-robin with two priority levels. Each of the three external
PCI bus masters, plus the PCI bridge, are assigned either a high or a low priority level, as programmed in
the arbiter configuration register (see Section 9.11.2.23, “PCI Bus Arbiter Configuration Register”).
Within each priority group (high or low), the bus grant is given to the next requesting device in numerical
order, with the PCI bridge itself positioned before device 0. GNTx is asserted for device x as soon as the
previously granted device begins a transaction. Conceptually, the lowest priority device at any given time
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PCI Bridge
is the master that is currently using the bus, and the highest priority device is the next one to follow the
current master. This is considered to be a fair algorithm because a given device cannot prevent other
devices from having access to the bus—a given device automatically becomes the lowest priority device
as soon as it begins to use the bus. If a master is not requesting the bus, the transaction slot is given to the
next requesting device within the priority group.
The grant given to a particular device may be taken away and given to another, higher priority device
whenever the higher priority device asserts its request. If the bus is idle when a new device is to receive a
grant, no device receives a grant for one clock and then in the next clock, the new winner of the arbitration
receives a grant. This operation allows for a turnaround clock when a device is using address stepping or
when the bus is parked.
The low priority group collectively receives one bus transaction request slot in the high priority group.
Therefore, if there are N high-priority devices, each high-priority device is guaranteed to get at least one
of (N+1) bus transactions, and the M low priority devices are guaranteed to each get at least one of (N+1)
x M bus transactions, with one of the low-priority devices receiving the grant in one of (N+1) bus
transactions. If all devices are programmed to the same priority level or if there is only one device at the
low priority, the algorithm provides each device an equal number of bus grants in a round-robin sequence.
An arbitration example with three masters in the high priority group and two in the low priority group is
shown in Figure 9-10. Noting that one position in the high priority group is actually a placeholder for the
low priority group, it can be seen that each high priority initiator is guaranteed at least 1 out of 3 transaction
slots, and each low priority initiator is guaranteed at least 1 out of 6 slots. Assuming all devices are
requesting the bus, the grant sequence (with device 1 being the current master) is as follows: 0, 2, the PCI
bridge, 0, 2, 1, 0, 2, the PCI bridge, and so on. If, for example, device 2 is not requesting the bus, the grant
sequence becomes 0, the PCI bridge, 0, 1, 0, the PCI bridge, and so on. If device 2 now requests the bus
at a point in the sequence when device 0 is conducting a transaction and the PCI bridge is the next grant,
then the PCI bridge’s grant is removed, and the higher-priority device 2 is awarded the next grant.
e
High priority group
Low priority group
2
(1/3)
1
(1/6)
0
(1/3)
Low
(1/3)
PCI
bridge
(1/6)
Figure 9-10. PCI Arbitration Example
9.9.2.3
Master Latency Timer
The PCI bridge implements the master latency timer register (see Section 9.11.2.10, “PCI Bus Latency
Timer Register”) to prevent the itself from monopolizing the bus. When the master latency timer expires,
the PCI bridge checks the state of its GNT signals. If the GNT signal is not asserted, the PCI bridge
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PCI Bridge
completes one more data phase and relinquishes the bus. The master latency timer can be disabled if
9.10 Address Map
A transaction sent to the PCI bridge from any 60x bus master side falls into one of the following three
cases:
•
If the transaction address is within the internal register space of the PowerQUICC II, the
transaction is handled by the PCI bridge internal register logic. (The internal registers are described
in this chapter.)
•
•
If the transaction address is within one of the three outbound PCI translation windows (described
in this chapter), the transaction is sent to the PCI bus with address translation.
If the transaction address is not within the internal register space and not within a PCI translation
window, the transaction is sent to the PCI bus with no address translation as a PCI memory
transaction to non-prefetchable space.
An address decode flow chart for transactions from the 60x bus masters to the PCI bridge is shown in
60x bus mastered
transaction
Hit
IMMR
?
Hit
No
No
Yes
PCIBR0/PCIBR1
?
Yes
No
Hit
No
Outbound ATU
?
Hit PCI
internal registers
Yes
?
(1)
Yes
Translate the
address
Issue transaction
with un-translated
address to PCI
Execute register
access to
PCI interface
internal registers
No action
Issue transaction
with translated
address to PCI
(1): IMMR+0x10400 ≤ addr ≤ IMMR+0x10bff
Figure 9-11. Address Decode Flow Chart for 60x Bus Mastered Transactions
Transactions directed to the PowerQUICC II from a PCI bus master are handled as follows:
•
If the transaction address is within the internal register space of the PowerQUICC II, the
transaction is either handled by the PCI bridge internal register logic or forwarded to the core side
of the PCI bridge to be handled by the PowerQUICC II internal register logic as appropriate.
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9-21
PCI Bridge
•
If the transaction address is within one of the two inbound PCI translation windows, the transaction
is sent to the core side of the PCI bridge with address translation.
This window is provided for the PCI master to access the PowerQUICC II's
internal (dual port) registers/area. Its size is assumed to be fixed at 128K
bytes. It translates to MPC8256A's IMMR value for the upper bits of the
address. This way, the PCI master can access any of the PCI bridge registers
(DMA/MU, etc.) without wasting an inbound translation window. In effect,
it suggests that we have a total of three inbound windows, 2 with ATUs and
one with PIMMR.
An address decode flow chart for transactions from a PCI bus master to the PCI bridge is shown in
PCI mastered
transaction
Hit
Hit
PIMMR
?
No
No
Inbound ATU
?
Yes
Yes
No DEVSEL
Translate the
address
Hit
IMMR
?
No
No
Yes
Issue transaction
to 60x bus
Hit PCI
internal registers
?
(1)
Yes
(1): IMMR+0x10400 ≤ addr ≤ IMMR+0x10bff
Execute register
access to
PCI interface
internal registers
Figure 9-12. Address Decode Flow Chart for PCI Mastered Transactions
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PCI Bridge
NOTE
When a transaction is performed by a PCI master, the bridge checks the
address against inbound ATUs and if it does not hit, it then checks against
PIMMR; if it is a hit, the bridge translates it to a 60x cycle. Because PIMMR
does not have an associated translation register and window size definition,
the translation is performed as follows: a 128-Kbyte window is provided for
the PCI master to access the PowerQUICC II’s internal (dual port) registers.
It translates to the PowerQUICC II’s IMMR value for the upper bits of the
address. This allows the PCI master to access any of the PCI-bridge registers
without wasting an inbound translation window. In effect, there are a total
of three inbound windows, 2 with ATUs and 1 with PIMMR.
Transactions initiated by the DMA controller or message unit fall into one of the following cases:
•
If the transaction address is within one of the outbound PCI translation windows, the transaction is
sent to the PCI bus with address translation.
•
If the transaction address is not within a PCI translation window, the transaction is sent to the core
side of the PCI bridge with no address translation.
An address decode flow chart for transactions from the DMA controller or message unit to the PCI bridge
DMA/MU mastered
transaction
Hit
No
Outbound ATU
?
Yes
Issue transaction
with translated
address to PCI
Issue transaction
with un-translated
address to 60x bus
Figure 9-13. Address Decode Flow Chart for Embedded Utilities
(DMA, Message Unit) Mastered Transactions
Example address mappings of these different types of transactions are shown in Figure 9-14. Note that the
translation mechanism shown is an example only; the address translation, as well as the memory and I/O
destinations, can be programmed independently for each address translation window.
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PCI Bridge
60x bus master view
PCI master memory view
PCI master I/O view
0
0
0
Address translation
Address translation
PCI bridge
Address translation
PCI memory
Address translation
Address translation
Internal registers
Internal registers
4G
4G
Figure 9-14. Address Map Example
4G
9.10.1 Address Map Programming
The address map has a number of programmable ranges to determine the PCI bridge’s response to all
transactions. The following are the PCI bridge’s rules for programming each address range:
•
•
•
All address regions should not overlap but do not have to be contiguous.
All address ranges must be aligned on a multiple of the region size.
Inbound and outbound windows for the same bus should not overlap. This means that a situation
where an inbound window translation points back into an outbound window, or a situation where
an outbound translation window points back into an inbound window, are not allowed.
9.10.2 Address Translation
The address translation registers allow the remapping of inbound and outbound transactions. The reset
configuration for outbound transactions are that all outbound requests from the core side of the PCI bridge
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PCI Bridge
are routed to the PCI bus with address translation disabled. The reset configuration for inbound
transactions are that all inbound requests from the PCI bus are disabled.
9.10.2.1 PCI Inbound Translation
For inbound transactions (transactions generated by an external master on the PCI bus where the PCI
bridge responds as a slave device), the PCI bridge only responds to PCI addresses within the windows
mapped by the PCI inbound base address registers (PIBARs). If there is an address hit in one of the
PIBARs, the PCI address is translated from PCI space to local memory space through the associated PCI
inbound translation address registers (PITARs). This allows an external master to access local memory on
the 60x’s bus. Each PIBAR register is associated with a PITAR and PICMR (PCI inbound comparison
mask register) which are located in the PCI bridge’s PCI internal register space. Figure 9-15 shows an
example translation window for inbound memory accesses.
PCI memory view
60x bus view
0
0
PCI inbound
translation
address
Peripheral memory
window
System memory
PCI inbound
window size
Local memory
Inbound address
translation
PCI memory
PCI inbound
base
PCI memory
Local peripheral
memory
address
PCI inbound
window size
4G
4G
Figure 9-15. Inbound PCI Memory Address Translation
There are two sets of inbound translation registers, allowing two simultaneous translation windows.
Software can move the translation base addresses during run-time to access different portions of local
memory, but be sure that the PCI inbound translation windows do not overlap.
The reset configuration for the windows is disabled; that is, after reset, the PCI bridge does not
acknowledge externally mastered transactions on the PCI bus by asserting DEVSEL until the inbound
translation windows are enabled. The inbound translation is performed in the PCI interface.
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PCI Bridge
9.10.2.2 PCI Outbound Translation
Outbound address translation is provided to allow the outbound transactions to access any address over the
PCI memory or I/O space. Translation window’s base addresses are defined in the PCI outbound base
Transactions to these address ranges are issued on the PCI bus with a translated address. The translation
addresses are defined in the associated PCI outbound translation address registers (POTARs). Outbound
addresses that fall outside the outbound windows are forwarded to the PCI bus without modification.
Figure 9-16 shows an example translation window for outbound memory accesses.
PCI memory view
60x bus view
0
0
System memory
PCI outbound
translation
address
Local memory
System memory
window
Outbound
memory
window size
Outbound address
translation
PCI memory
PCI outbound
base
address
PCI memory
Outbound memory
window
Outbound
memory
window size
Transactions outside
the window forwarded
without modification
4G
4G
Figure 9-16. Outbound PCI Memory Address Translation
The three sets of outbound translation registers allow three simultaneous translation windows. Software
can move and adjust the host memory window translations and sizes during run-time. This allows software
to access host memory or to address alternate memory space on the fly, but be sure that the PCI outbound
translation windows do not overlap. Also note that the PCI outbound translation windows should not
overlap with the PCI bridge internal register space defined by the PIMMR.
9.10.3 SIU Registers
PCI utilizes fields in general SIU registers (SIUMCR, TESCR1, TESCR2, and L-TESCR1). There are also
two pairs of PCI-specific registers that detect accesses from the 60x bus side to the PCI bridge (other than
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PCI Bridge
9.11 Configuration Registers
There are two types of configuration registers in the PCI bridge: PCI-specified and memory-mapped. The
PCI-specified type, referred to as PCI configuration registers, are accessed through PCI configuration
memory map
configuration registers are placed in the internal
of the PowerQUICC II and are accessed like
Both the PCI configuration and memory-mapped internal registers of the PCI bridge are intrinsically
little-endian and are described using classic bit-numbering; that is, the lowest memory address contains
the least significant byte of the register and bit 0 is the least-significant bit of the register.
NOTE: Accessing Configuration Registers
For a PCI device to share little-endian (LE) data with the 603e core CPU,
software must byte-swap the data of the configuration register. Refer to
Also note that reserved bits in the configuration registers are not guaranteed to have predictable values.
Software must preserve the values of reserved bits when writing to a configuration register. Also, when
reading from a configuration register, software should not rely on the value of reserved bits remaining
constant.
NOTE: Accessing PCI Registers in Non-PCI Mode
In non-PCI mode, a 60x bus master should not attempt to access the PCI
memory mapped configuration registers. Doing so will cause the internal
memory space of the PowerQUICC II to be inaccessible. Any following
access to the internal memory space will not be terminated normally, and
can only be terminated by TEA if the 60x bus monitor is activated. The
system can recover only after a soft reset.
9.11.1 Memory-Mapped Configuration Registers
Table 9-3 describes the memory-mapped configuration registers provided by the PCI bridge. Note that
memory gaps not defined are reserved and should not be accessed.
Table 9-3. Internal Memory Map
Address
(offset)
Register Access
Reset
Section/Page
0x10430 Outbound interrupt status register (OMISR)
0x10434 Outbound interrupt mask register (OMIMR)
0x10440 Inbound FIFO queue port register (IFQPR)
0x10444 Outbound FIFO queue port register (OFQPR)
0x10450 Inbound message register 0 (IMR0)
R/W
R/W
undefined 9.12.1.1/9-66
undefined 9.12.1.1/9-66
0x10454 Inbound message register 1 (IMR1)
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PCI Bridge
Table 9-3. Internal Memory Map (continued)
Address
(offset)
Register
Access
Reset
Section/Page
0x10458 Outbound message register 0 (OMR0)
R/W
R/W
undefined 9.12.1.2/9-66
undefined 9.12.1.2/9-66
0x1045C Outbound message register 1 (OMR1)
0x10460 Outbound doorbell register (ODR)
0x10468 Inbound doorbell register (IDR)
0x10480 Inbound message interrupt status register (IMISR)
0x10484 Inbound message interrupt mask register (IMIMR)
0x104A0 Inbound free_FIFO head pointer register (IFHPR)
0x104A8 Inbound free_FIFO tail pointer register (IFTPR)
0x104B0 Inbound post_FIFO head pointer register (IPHPR)
0x104B8 Inbound post_FIFO tail pointer register (IPTPR)
0x104C0 Outbound free_FIFO head pointer register (OFHPR)
0x104C8 Outbound free_FIFO tail pointer register (OFTPR)
0x104D0 Outbound post_FIFO head pointer register (OPHPR)
0x104D8 Outbound post_FIFO tail pointer register (OPTPR)
0x104E4 Message unit control register (MUCR)
0x104F0 Queue base address register (QBAR)
0x10500 DMA 0 mode register (DMAMR0)
0x10504 DMA 0 status register (DMASR0)
0x10508 DMA 0 current descriptor address register (DMACDAR0)
0x10510 DMA 0 source address register (DMASAR0)
0x10518 DMA 0 destination address register (DMADAR0)
0x10520 DMA 0 byte count register (DMABCR0)
0x10524 DMA 0 next descriptor address register (DMANDAR0)
0x10580 DMA 1 mode register (DMAMR1)
0x10584 DMA 1 status register (DMASR1)
0x10588 DMA 1 current descriptor address register (DMACDAR1)
0x10590 DMA 1 source address register (DMASAR1)
0x10598 DMA 1 destination address register (DMADAR1)
0x105A0 DMA 1 byte count register (DMABCR1)
0x105A4 DMA 1 next descriptor address register (DMANDAR1)
0x10600 DMA 2 mode register (DMAMR2)
0x10604 DMA 2 status register (DMASR2)
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PCI Bridge
Table 9-3. Internal Memory Map (continued)
Register Access
Address
(offset)
Reset
Section/Page
0x10608 DMA 2 current descriptor address register (DMACDAR2)
0x10610 DMA 2 source address register (DMASAR2)
0x10618 DMA 2 destination address register (DAR2)
0x10620 DMA 2 byte count register (DMABCR2)
0x10624 DMA 2 next descriptor address register (DMANDAR2)
0x10680 DMA 3 mode register (DMAMR3)
0x10684 DMA 3 status register (DMASR3)
0x10688 DMA 3 current descriptor address register (DMACDAR3)
0x10690 DMA 3 source address register (DMASAR3)
0x10698 DMA 3 destination address register (DMADAR3)
0x106A0 DMA 3 byte count register (DMABCR3)
0x106A4 DMA 3 next descriptor address register (DMANDAR3)
0x10800 PCI outbound translation address register 0 (POTAR0)
0x10808 PCI outbound base address register 0 (POBAR0)
0x10810 PCI outbound comparison mask register 0 (POCMR0)
0x10818 PCI outbound translation address register 1 (POTAR1)
0x10820 PCI outbound base address register 1 (POBAR1)
0x10828 PCI outbound comparison mask register 1 (POCMR1)
0x10830 PCI outbound translation address register 2 (POTAR2)
0x10838 PCI outbound base address register 2 (POBAR2)
0x10840 PCI outbound comparison mask register 2 (POCMR2)
0x10878 Discard timer control register (PTCR)
0x1087C General purpose control register (GPCR)
0x10880 PCI general control register (PCI_GCR)
0x10884 Error status register (ESR)
0x10888 Error mask register (EMR)
0x1088C Error control register (ECR)
0x10890 PCI error address capture register (PCI_EACR)
0x10898 PCI error data capture register (PCI_EDCR)
0x108A0 PCI error control capture register (PCI_ECCR)
0x108D0 PCI inbound translation address register 1 (PITAR1)
0x108D8 PCI inbound base address register 1 (PIBAR1)
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PCI Bridge
Table 9-3. Internal Memory Map (continued)
Register Access
Address
(offset)
Reset
Section/Page
0x108E0 PCI inbound comparison mask register 1 (PICMR1)
0x108E8 PCI inbound translation address register 0 (PITAR0)
0x108F0 PCI inbound base address register 0 (PIBAR0)
0x108F8 PCI inbound comparison mask register 0 (PICMR0)
0x10900 PCI CFG_ADDR
R/W
undefined 9.9.1.4.4/9-15
0x10904 PCI CFG_DATA
0x10908 PCI INT_ACK
9.11.1.1 Message Unit (I2O) Registers
9.11.1.2 DMA Controller Registers
9.11.1.3 PCI Outbound Translation Address Registers (POTARx)
addresses in PCI address space for locally generated transactions that hit within the outbound translation
windows. The new translated address is created by concatenating the transaction offset to this translation
31
20
19
16
Field
Reset
R/W
—
TA
0000_0000_0000_0000
R/W
Addr
0x10802 (POTAR0); 0x1081A (POTAR1); 0x10832 (POTAR2)
15
0
Field
Reset
R/W
TA
0000_0000_0000_0000
R/W
Addr
0x10800 (POTAR0); 0x10818 (POTAR1); 0x10830 (POTAR2)
Figure 9-17. PCI Outbound Translation Address Registers (POTARx)
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PCI Bridge
Table 9-4. POTARx Field Descriptions
Description
Bits
Name
31–20
19–0
—
Reserved, should be cleared.
Translation Address
PCI address which indicates the starting point of the outbound translated
address. The translation address must be aligned based on the window’s size.
This corresponds to bits 31-12 of a 32-bit address
9.11.1.4 PCI Outbound Base Address Registers (POBARx)
The PCI outbound base address registers (POBARx), shown in Figure 9-18, select the base address for the
windows which are translated to the PCI address space for transactions generated by the 60x bus master
or other local devices such as the DMA controller.
31
20
19
16
Field
Reset
R/W
—
BA
0000_0000_0000_0000
R/W
Addr
0x1080A (POBAR0); 0x10822 (POBAR1); 0x1083A (POBAR2)
15
0
Field
Reset
R/W
BA
0000_0000_0000_0000
R/W
Addr
0x10808 (POBAR0); 0x10820 (POBAR1); 0x10838 (POBAR2)
Figure 9-18. PCI Outbound Base Address Registers (POBARx)
Table 9-5. POBARx Field Descriptions
Bits
Name
Description
31–20
19–0
—
Reserved, should be cleared.
Base Address
Local address which is the starting point for the outbound translation window.
This corresponds to bits 31-12 of a 32-bit address
Addresses for outbound transactions are compared to the POBARs and the IMMR register. If the
transaction does not fall within one of these two spaces, it is forwarded to the PCI bus without modification
9.11.1.5 PCI Outbound Comparison Mask Registers (POCMRx)
to translate.
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PCI Bridge
31
30
29
28
20
19
16
Field EN
Reset
I/O PRE
—
CM
0000_0000_0000_0000
R/W
R/W
Addr
0x10812 (POCMR0); 0x2082A (POCMR1); 0x10842 (POCMR2)
15
0
Field
CM
Reset
R/W
0000_0000_0000_0000
R/W
Addr
0x10810 (POCMR0); 0x20828 (POCMR1); 0x10840 (POCMR2)
Figure 9-19. PCI Outbound Comparison Mask Registers (POCMRx)
Table 9-6. POCMRx Field Descriptions
Bits
Name
Description
31
30
Enable
I/O
This bit enables this address translation
This bit indicates that the translation is to PCI memory or PCI I/O space
0 PCI memory
1 PCI I/O
29
Prefetchable
This bit indicates that the address space is prefetchable, so streaming can occur
0 not prefetchable
1 prefetchable
28–20
19–0
—
Reserved, should be cleared.
Comparison mask
Comparison mask indicates the size of the space to be translated. The value in the
register represents which of the most significant address bits to compare for a
window match. Non-contiguous comparison masks will exhibit unpredictable
behavior.
Examples:
POCMR = 0b0xxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx
Translation is disabled. All addresses received pass through unaltered.
POCMR = 0b1xxx_xxxx_xxxx_1111_1111_1111_1111_1111
20 bits (physical address bits 31-12) are comparison masked for a 4Kbyte window
size. This is the smallest window size allowed.
POCMR = 0b1xxx_xxxx_xxxx_1111_1111_1111_0000_0000
12 bits (physical address bits 31-20) for a 1Mbyte window size.
9.11.1.6 Discard Timer Control Register (PTCR)
The discard timer control register (PTCR), shown in Figure 9-20, configures the discard timer used to put
a time limit on delayed read transactions from non-prefetchable memory.
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PCI Bridge
31
30
24
23
16
Field EN
—
PTV
Reset
R/W
0000_0000_0000_0000
R/W
Addr
0x1087A
15
0
Field
PTV
0000_0000_0000_0000
R/W
Reset
R/W
Addr
0x10878
Figure 9-20. Discard Timer Control register (PTCR)
Table 9-7. describes PTCR fields.
Table 9-7. PTCR Field Descriptions
Description
Bits
Name
31
Enable
Discard timer enable.
0 Disable the discard timer
1 Enable the discard timer
30–24
23–0
—
Reserved
Preload timer value
Preload value for 24-bit discard timer. Delayed PCI read transactions to a
non-prefetchable address space remain valid within the PCI bridge a minimum of
24
(2 - Preload Timer Value) internal clock cycles. The discard timer is used to
discard delayed reads from non-prefetchable address space if the master has not
24
repeated the transaction in n internal clock cycles, where n = (2 - Preload Timer
Value). Valid Preload Timer Values are in the range 0x000000–0xFFFFFE.
Example: To discard a delayed completion if the PCI master has not repeated the
15
transaction in 2 PCI clocks and the internal frequency is 2 to 1 to the PCI bus. The
24
16
Preload Timer Value should equal 2 - 2 (0xFF0000).
9.11.1.7 General Purpose Control Register (GPCR)
The general purpose control register (GPCR), shown in Figure 9-21, contains control bits for rerouting
interrupts and adjusting the DMA controller’s 60x bandwidth.
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PCI Bridge
31
20
19
18
17
16
Field
—
DMABC
—
Reset
R/W
0000_0000_0000_0000
R/W
Addr
0x1087E
15
14
13
12
1
0
Field
Reset
R/W
—
INTPCI MCP2PCI
—
0000_0000_0000_0000
R/W
LE_MODE
Addr
0x1087C
Figure 9-21. General Purpose Control Register (GPCR)
Table 9-8. describes GPCR fields.
Table 9-8. GPCR Field Descriptions
Description
Bits
Name
31–20
19–18
—
Reserved, should be cleared.
DMABC
DMA 60x bandwidth control
00 DMA uses low 60x bandwidth.
01 DMA uses high 60x bandwidth.
10 DMA uses maximum 60x bus bandwidth.
11 DMA uses minimum 60x bandwidth.
Allows breaks to be inserted in the DMA controller operation. This control may
be needed to avoid starvation of other 60x masters because the PCI bridge can
have higher priorities than other masters. The breaks are inserted only if some
other 60x bus master requests the bus.
The user should find the optimum setting by testing, arriving at the best for each
specific implementation. For most systems the default value (low 60x bandwidth
for the dma) will be good. Note that if the dma is the only master that needs the
bus during the period of the
transfer, the bandwidth is not affected.
17–15
14
—
Reserved, should be cleared.
INT2PCI
Interrupt reroute to PCI.
0 Interrupts are not rerouted to the PCI. Sent to the core if it is enabled or output
on IRQ7 if the core is disabled.
1 All SIU pending interrupts are rerouted to PCI's INTA. Useful in agent mode.
13
MCP2PCI
Machine check reroute to PCI.
0 Machine check interrupts are not rerouted to the PCI. Sent to the core if it is
enabled or output on IRQ0 if the core is disabled
1 All machine check interrupts are rerouted to PICE’s INTA. Useful in agent
mode.
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PCI Bridge
Table 9-8. GPCR Field Descriptions (continued)
Bits
Name
Description
12–1
0
—
Reserved, should be cleared.
LE_MODE
Little endian mode. Controls the translation of 60x-PCI and PCI-60x. Refer to
Section 9.11.2.27.1, “Additional Information on Endianess” for more details.
0 Big endian mode.
1 Little endian mode.
9.11.1.8 PCI General Control Register (PCI_GCR)
The PCI general control register (PCI_GCR), shown in Figure 9-22, contains a bit for controlling the PCI
reset signal when in host mode.
31
16
Field
Reset
R/W
—
0000_0000_0000_0000
R/W
Addr
0x10882
15
1
0
Field
Reset
R/W
—
SPRST
0000_0000_0000_0000
R/W
Addr
0x10880
Figure 9-22. PCI General Control Register (PCI_GCR)
Table 9-9. describes PCI_GCR fields.
Table 9-9. PCI_GCR Field Descriptions
Bits
Name
Description
31–1
0
—
Reserved, should be cleared.
Soft PCI Reset
Only valid when in host mode. Allows PCI_RST to be controlled software.
Setting this bit drives the PCI reset signal high; clearing it drives the signal low.
9.11.1.9 Error Status Register (ESR)
The error status register (ESR), shown in Figure 9-23, contains status bits for various types of error
conditions captured by the PCI bridge. Each status bit is set when the corresponding error condition is
captured. Each bit is cleared by writing a one.
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9-35
PCI Bridge
31
16
Field
—
0000_0000_0000_0000
R/W
Reset
R/W
Addr
0x10886
15
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DATA_ DATA_
PAR_ PAR_
I2O_
DBMC
I2O_ I2O_ PERR_ PERR_ PCI_ TAR_ NO_
IPQO OFQO WR RD SERR ABT RSP
ADDR_
PAR
Field
—
NMI
IRA
RD
WR
Reset
R/W
0000_0000_0000_0000
R/W
Addr
0x10884
Figure 9-23. Error Status Register (ESR)
Table 9-10. describes ESR fields.
Table 9-10. ESR Field Descriptions
Bits
Name
Description
31–13
12
—
Reserved, should be cleared.
I2O_DBMC
I O DoorBell Machine Check. When a PCI-mastered write sets IDBR[31], a
2
machine check is sent to the local processor and the event is reported in
ESR[I2O_DBMC].
This bit is also set in the following cases:
• An overflow condition in the inbound posted I O queue
2
• An overflow condition in the outbound free I O queue.
2
These two interrupts can be masked in the I O unit.
2
11
NMI
General error/interrupt indication. In host mode, this bit is set when a 60x bus
write transaction initiated by the PCI bridge is terminated by the assertion of
TEA. In agent mode, this bit is set when the GPCR[MCP2PCI] bit is set and an
internal machine check interrupt (MCP) is issued by one of the PowerQUICC II’s
MCP sources.
Machine check and interrupt assertion is determined by ECR[11].
The reset value of ECR[11], logic zero, indicates that an interrupt will be asserted
if ESR[NMI] is set (and enabled per EMR[11]).
10
9
IRA
Illegal register access with incorrect size.
I2O inbound post queue overflow.
I2O outbound free queue overflow.
PCI parity error received on a write.
PCI parity error received on a read.
PCI SERR received.
I2O_IPQO
8
I2O_OFQO
7
PCI_PERR_WR
PCI_PERR_RD
PCI_SERR
6
5
4
PCI_TAR_ABT
PCI target abort
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PCI Bridge
Table 9-10. ESR Field Descriptions (continued)
Bits
Name
Description
3
2
1
0
PCI_NO_RSP
PCI no response (no DEVSEL; master abort).
PCI_DATA_PAR_RD PCI read data parity error.
PCI_DATA_PAR_WR PCI write data parity error.
PCI_ADDR_PAR
PCI address parity error (read or write).
9.11.1.10 Error Mask Register (EMR)
The error mask register (EMR) register, shown in Figure 9-24, enables the IOU to assert an interrupt or a
machine check for the various types of error conditions listed in Table 9-10. Each mask bit is active high.
That is, if a bit value is zero, an interrupt or machine check is not asserted for the corresponding error
condition.
31
16
Field
Reset
R/W
—
0000_0000_0000_0000
R/W
Addr
0x1088A
15
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DATA_ DATA_
PAR_ PAR_
I2O_
DBMC
I2O_ I2O_ PERR_ PERR_ PCI_ TAR_ NO_
IPQO OFQO WR RD SERR ABT RSP
ADDR_
PAR
Field
—
NMI
IRA
RD
WR
Reset
R/W
0000_1111_1111_1111
R/W
Addr
0x10888
Figure 9-24. Error Mask Register (EMR)
Table 9-11. describes EMR fields.
Table 9-11. EMR Field Descriptions
Bits
Name
Description
31–13
12
—
Reserved, should be cleared.
I2O_DBMC
I O doorbell machine check.
2
0 Machine check is not enabled
1 Machine check is enabled
11
10
9
NMI
IRA
General error/interrupt indication.
Illegal register access with incorrect size.
I2O inbound post queue overflow.
I2O outbound free queue overflow.
I2O_IPQO
I2O_OFQO
8
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PCI Bridge
Table 9-11. EMR Field Descriptions (continued)
Description
Bits
Name
7
6
PCI_PERR_WR
PCI parity error received on a write. The PowerQUICC II sinks PERR. This error
is only a function of data.
PCI_PERR_RD
PCI parity error received on a read. The PowerQUICC II sinks PERR. This error
is only a function of data.
5
4
3
2
PCI_SERR
PCI_TAR_ABT
PCI_NO_RSP
PCI SERR received.
PCI target abort
PCI no response (no DEVSEL; master abort).
PCI_DATA_PAR_RD PCI read data parity error. The PowerQUICC II sources PERR. This error is only
a function of data.
1
0
PCI_DATA_PAR_WR PCI write data parity error. The PowerQUICC II sources PERR. This error is only
a function of data.
PCI_ADDR_PAR
PCI address parity error (read or write).
9.11.1.11 Error Control Register (ECR)
The error control register (ECR) register, shown in Figure 9-25, determines whether the IOU asserts an
interrupt or a machine check for the error conditions listed in Table 9-10. The IOU asserts an interrupt or
machine check only if the mask bit for the error condition (refer to Table 9-11) is set. Each bit is defined
as follows:
•
•
Zero: The IOU issues an interrupt upon the error condition.
One: The IOU issues a machine check upon the error condition.
31
16
Field
Reset
R/W
—
0000_0000_0000_0000
R/W
Addr
0x1088E
15
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DATA_ DATA_
PAR_ PAR_
I2O_
DBMC
I2O_ I2O_ PERR_ PERR_
TAR_ NO_
ABT RSP
ADDR_
PAR
Field
—
NMI
IRA
SERR
IPQO OFQO WR
RD
RD
WR
Reset
R/W
0000_0000_1111_1111
R/W
Addr
0x1088C
Figure 9-25. Error Control Register (ECR)
Table 9-12 describes ECR fields.
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PCI Bridge
Table 9-12. ECR Field Descriptions
Description
Bits
Name
31–13
12
—
Reserved, should be cleared.
I O doorbell machine check
I2O_DBMC
2
0
ESR[I2O_DBMC] causes an interrupt.
1 ESR[I2O_DBMC] (if enabled) causes a machine check.
General error/interrupt indication.
Illegal register access with incorrect size.
I2O inbound post queue overflow.
I2O outbound free queue overflow.
PCI parity error received on a write.
PCI parity error received on a read.
PCI SERR received.
11
10
9
NMI
IRA
I2O_IPQO
8
I2O_OFQO
PCI_PERR_WR
PCI_PERR_RD
PCI_SERR
PCI_TAR_ABT
PCI_NO_RSP
7
6
5
4
PCI Target Abort
3
PCI no response (no DEVSEL; master abort).
2
PCI_DATA_PAR_RD PCI read data parity error.
PCI_DATA_PAR_WR PCI write data parity error.
1
0
PCI_ADDR_PAR
PCI address parity error (read or write).
9.11.1.12 PCI Error Address Capture Register (PCI_EACR)
The PCI error address capture register (PCI_EACR), shown in Figure 9-26, stores the address associated
with the first PCI error captured.
31
16
Field
Reset
R/W
PCI_EAR
0000_0000_0000_0000
R/W
Addr
0x10892
15
0
Field
Reset
R/W
PCI_EAR
0000_0000_0000_0000
R/W
Addr
0x10890
Figure 9-26. PCI Error Address Capture Register (PCI_EACR)
Table 9-13. describes PCI_EACR fields.
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PCI Bridge
Table 9-13. PCI_EACR Field Descriptions
Bits
31–0
Name
Description
PCI_EAR
The address associated with the first error captured.
9.11.1.13 PCI Error Data Capture Register (PCI_EDCR)
The PCI error data capture register (PCI_EDCR), shown in Figure 9-27, stores the data associated with the
first PCI error captured.
31
16
Field
Reset
R/W
PCI_EDR
0000_0000_0000_0000
R/W
Addr
0x1089A
15
0
Field
Reset
R/W
PCI_EDR
0000_0000_0000_0000
R/W
Addr
0x10898
Figure 9-27. PCI Error Data Capture Register (PCI_EDCR)
Table 9-14. describes PCI_EDCR fields.
Table 9-14. PCI_EDCR Field Description
Bits
Name
Description
31–0
PCI_EDR
The data associated with the first error captured.
9.11.1.14 PCI Error Control Capture Register (PCI_ECCR)
The PCI error control capture register (PCI_ECCR), shown in Figure 9-28, stores information associated
with the first PCI error captured.
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PCI Bridge
31
30
28
27
24
23
22
21
20
19
16
Field
Reset
R/W
—
FET
BN
—
TS
ES
0000_0000_0000_0000
R/W
Addr
0x108A2
15
12
11
8
7
4
3
2
1
0
Field
Reset
R/W
CMD
—
BE
—
PB
VI
0000_0000_0000_0000
R/W
Addr
0x108A0
Figure 9-28. PCI Error Control Capture Register (PCI_ECCR)
Table 9-15 describes PCI_ECCR fields.
Table 9-15. PCI_ECCR Field Descriptions
Bits
Name
Description
31
—
Reserved, should be cleared.
30–28
First error type
Type of first PCI error captured. This field is the bit index of the error type in
condition while a value of 0b010 indicates a PCI read data parity error.
27–24
Beat number
32-bit data beat number for data parity error (data parity error only)
0000 1
0001 2
…
0111 8
1000 overflow (transaction larger than one cache line)
23–22
21–20
—
Reserved, should be cleared.
Transaction size
This is the size of the transaction in doublewords (4 bytes) (the PCI bridge as
master only)
00 4 doublewords
01 1 doubleword
10 2 doublewords
11 3 doublewords
19–16
Error source
The source of the PCI transaction
0000 External master
0001 60x master
0101 DMA
All others are reserved.
15–12
11–8
7–4
Command
PCI command
—
Byte enables
—
Reserved, should be cleared.
PCI byte enables.
3–2
Reserved, should be cleared.
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PCI Bridge
Table 9-15. PCI_ECCR Field Descriptions (continued)
Name Description
Bits
1
0
Parity bit
Valid info
Parity bit for PCI bus data word.
When this bit is set, the PCI bus error capture registers (PCI_EACR, PCI_EDCR,
and PCI_ECCR) contain valid information.
Writing ‘0’ to this bit enables the capture of a new error in the PCI bus error
capture registers (PCI_EACR, PCI_EDCR, and PCI_ECCR).
9.11.1.15 PCI Inbound Translation Address Registers (PITARx)
The PCI inbound translation address registers (PITARx), shown in Figure 9-29, select the base addresses
in the 60x address space of the translation windows for transactions generated by the master on the PCI
bus. The new translated address is created by concatenating the transaction offset to this base address.
31
20
19
16
Field
Reset
R/W
—
TA
0000_0000_0000_0000
R/W
Addr
0x108EC (PITAR0); 0x108D2 (PITAR1)
15
0
Field
Reset
R/W
TA
0000_0000_0000_0000
R/W
Addr
0x108EA (PITAR0); 0x108D0 (PITAR1)
Figure 9-29. PCI Inbound Translation Address Registers (PITARx)
Table 9-16. PITARx Field Descriptions
Bits
Name
Description
31–20
19–0
—
Reserved, should be cleared.
Translation Address
60x address which indicates the starting point of the inbound translated address.
The translation address must be aligned based on the window’s size. This
corresponds to bits 31-12 of a 32-bit address
9.11.1.16 PCI Inbound Base Address Registers (PIBARx)
The PCI inbound base address registers (PIBARx), shown in Figure 9-30, select the starting addresses (in
PCI memory space) of the windows to be translated. These registers are tied to the GPLABARx registers;
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PCI Bridge
in a PIBARx register causes a change in the GPLABARx in the base address bits that are non-masked by
PICMRx, and vice versa.
The system host is responsible for the configuration of the base address by writing to GPLABARx;
therefore, in PCI agent mode, the PIBARx registers should be read-only. However, if the PCI bridge is
defined as the PCI host, it may be easier to configure its own inbound base address by writing directly to
the PIBARx registers.
31
20
19
16
Field
Reset
R/W
—
BA
0000_0000_0000_0000
R/W
Addr
0x108F2 (PITAR0); 0x108DA (PITAR0)
15
0
Field
Reset
R/W
BA
0000_0000_0000_0000
R/W
Addr
0x108F0 (PITAR0); 0x108D8 (PITAR0)
Figure 9-30. PCI Inbound Base Address Registers (PIBARx)
9.11.1.17 PCI Inbound Comparison Mask Registers (PICMRx)
Table 9-17. PIBARx Field Descriptions
Bits
Name
Description
31–20
19–0
—
Reserved, should be cleared.
Base Address
PCI address which is the starting point for the inbound translation window.This
corresponds to bits 31-12 of a 32-bit address
window’s size. In PCI agent mode, this register should be initialized (either by the core or by the CP’s
automatic EPROM load) before the AGENT_CFG_LOCK bit (see Section 9.11.2.22, “PCI Bus Function
Register”) can be cleared to enable the host to configure the device. Some of the fields of this registers are
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
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9-43
PCI Bridge
31
30
29
28
20
19
16
NO_
Field EN SNOOP_ PRE
EN
—
CM
Reset
R/W
0000_0000_0000_0000
R/W
Addr
0x108FA (PICMR0); 0x108E2 (PICMR1)
15
0
Field
CM
0000_0000_0000_0000
R/W
Reset
R/W
Addr
0x108F8 (PICMR0); 0x108E0 (PICMR1)
Figure 9-31. PCI Inbound Comparison Mask Registers (PICMRx)
Table 9-18. PICMRx Field Descriptions
Bits
Name
Description
31
30
Enable
Setting this bit enables address translation
NO_SNOOP_EN
Controls whether the PCI bridge generates snoop transactions on the 60x bus for
PCI-to-60x memory transactions which hit in this address translation window.
Disabling snooping is a performance enhancement for systems that do not need to
maintain coherency on system memory accesses by PCI.
0 Snooping is enabled.
1 Snooping is disabled.
29
Prefetchable
Indicates whether the address space is prefetchable so that streaming can occur.
0 not prefetchable
1 prefetchable
28–20
19–0
—
Reserved, should be cleared.
Comparison Mask
Indicates the size of the space to be translated. The value in the register represents
which of the most significant address bits to compare for a window match.
Non-contiguous comparison mask bits cause unpredictable behavior.
Examples:
PICMR = 0b0xxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx
Inbound window is disabled.
PICMR = 0b1xxx_xxxx_xxxx_1111_1111_1111_1111_1111
The mask is 20 bits (physical address bits 31-12) which corresponds to a 4Kbyte
window size. This is the smallest window size allowed.
PICMR = 0b1xxx_xxxx_xxxx_1111_1111_1111_0000_0000
The mask is 12 bits (physical address bits 31-20) which corresponds to a 1Mbyte
window size.
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PCI Bridge
9.11.2 PCI Bridge Configuration Registers
The PCI Local Bus Specification defines the configuration registers from 0x00 through 0x3F. Additionally,
the PCI bridge specifies these additional registers: the PCI function register (at offset 0x44), the PCI arbiter
control register (at offset 0x46), and the PCI Hot Swap register block (at offset 0x48). Table 9-19 and
Figure 9-32 shows the PCI configuration registers provided by the PCI bridge for the PCI bus.
Note the following sections that apply to all PCI configuration registers (they appear immediately after the
descriptions of individual registers):
•
•
•
Table 9-19. PCI Bridge PCI Configuration Registers
Address
(offset)
Register
Access
Reset
Section/Page
00
02
04
06
08
09
0A
0B
0C
0D
0E
0F
10
14
18
1C
2C
2E
30
34
35
3C
3D
Vendor ID
R
0x1057
0x18C0
Device ID
R
PCI command
PCI status
Revision ID
R/W
Mode-dependent 9.11.2.3/9-47
0x00B0 9.11.2.4/9-48
Read/bit-reset
R
R
Rev-dependent 9.11.2.5/9-49
Mode-dependent 9.11.2.6/9-50
Standard programming interface
Subclass code
R
0x00
Class code
R
Mode-dependent 9.11.2.8/9-51
Cache line size
R/W
R/W
R
0x00
0x00
0x00
0x00
Latency timer
Header type
BIST control
R
PIMMR base address register
GPL base address register 0
GPL base address register 1
Reserved
R/W
R/W
R/W
—
0x0000_0000 9.11.2.14/9-54
0x0000_0000 9.11.2.14/9-54
—
0x0000
0x0000
—
—
Sub system vendor ID
Sub system device ID
Reserved
R/W
R/W
—
—
Capabilities pointer
Reserved
R
0x48
—
—
—
Interrupt line
R/W
R
0x00
0x01
Interrupt pin
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9-45
PCI Bridge
Table 9-19. PCI Bridge PCI Configuration Registers (continued)
Address
(offset)
Register
Access
Reset
Section/Page
3E
3F
40
44
46
48
MIN GNT
MAX LAT
Reserved
PCI function
R
0x00
0x00
—
—
R
—
R/W
R/W
R/W
0x0000
PCI arbiter control register
Hot swap register block
Mode-dependent 9.11.2.23/9-59
0x00nn_0006 9.11.2.24/9-60
Address offset
(Hex)
00
04
08
0C
10
14
18
Device ID (0x18C0)
PCI status
Vendor ID (0x1057)
PCI command
Class code
BIST control
Subclass code
Header type
Standard programming
Latency timer
Revision ID
Cache line size
PIMMR base address register
GPLA base address register 0
GPLA base address register 1
•
•
—
•
•
2C
Subsystem ID
Subsystem vendor ID
•
•
•
•
—
34
38
3C
40
44
48
—
Capabilities pointer
Interrupt line
—
—
MAX LAT
MIN GNT
Interrupt pin
PCI arbiter control
Hot swap CSR
PCI function
Hot swap capability ID
Figure 9-32. PCI Bridge PCI Configuration Registers
The PCI configuration registers are accessible from the core through an indirect method discussed in
accessible from the PCI bus through the PCI configuration transaction when the PCI bridge is in agent
mode.
The following sections describe the individual PCI configuration registers.
9.11.2.1 Vendor ID Register
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PCI Bridge
15
0
Field
Reset
R/W
VID
0001_0000_0101_0111
R
Addr
0x00
Figure 9-33. Vendor ID Register
Table 9-20. Vendor ID Register Description
Bits
Name
Description
15–0
Vendor ID
Identifies the manufacturer of the device (0x1057 = Freescale)
9.11.2.2 Device ID Register
15
0
Field
Reset
R/W
DID
0001_1000_1100_0000
R
Addr
0x02
Figure 9-34. Device ID Register
Table 9-21. Device ID Register Description
Bits
Name
Description
15–0
Device ID
Identifies the particular device (0x18C0 = PowerQUICC II)
9.11.2.3 PCI Bus Command Register
Figure 9-35 and Table 9-22 describe the PCI bus command register that provides control over the ability
to generate and respond to PCI cycles.
15
10
9
8
7
6
5
4
3
2
1
0
Field
Reset
R/W
—
FB-B SERR
—
PERRR
—
MWI SC
BM MEM I/O
0000_0000_0000_0000
R/W
Addr
0x04
Figure 9-35. PCI Bus Command Register
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PCI Bridge
Bits
Table 9-22. PCI Bus Command Register Description
Name
Description
15–10
9
—
Reserved, should be cleared.
Fast back-to-back
Hardwired to 0, indicating that the PCI bridge as a master does not run fast
back-to-back transactions.
8
SERR
Controls the SERR driver of the PCI bridge. This bit (and bit 6) must be set to report
address parity errors.
0 Disables the SERR driver
1 Enables the SERR driver
7
6
—
Reserved, should be cleared.
Parity error response Controls whether the PCI bridge responds to parity errors on the PCI bus.
0 Parity errors are ignored and normal operation continues.
1 Action is taken on a parity error.
5
4
—
Reserved, should be cleared.
Memory-write-and-
invalidate
Hardwired to 0, indicating that the PCI bridge acting as a master does not generate
the memory-write-and-invalidate command. The PCI bridge generates a
memory-write command instead.
3
2
Special-cycles
Bus master
Hardwired to 0, indicating that the PCI bridge as a target ignores all special-cycle
commands.
Controls whether the PCI bridge can act as a master on the PCI bus. This bit is
cleared if the PCI bridge is powered-up as an agent device and is set if it is
powered-up as a host bridge device.
0 Disables the ability to generate PCI accesses. In host bridge mode, read
transactions return undefined data and write transactions lose data. In agent
mode, transactions are held until this bit is enabled.
1 Enables the PCI bridge to behave as a PCI bus master
1
0
Memory space
I/O space
Controls whether the PCI bridge as a target responds to memory accesses.
0 The PCI bridge does not respond to PCI memory space accesses.
1 The PCI bridge responds to PCI memory space accesses.
Hardwired to 0, indicating that the PCI bridge as a target does not respond to PCI
I/O space accesses.
9.11.2.4 PCI Bus Status Register
The PCI bus status register, shown in Figure 9-36, is used to record status information for PCI bus-related
events. Only 2-byte accesses to address offset 0x06 are allowed.
Reads to this register behave normally. Writes are slightly different in that bits can be cleared, but not set.
A bit is cleared whenever the register is written, and the data in the corresponding bit location is set. For
example, to clear bit 14 and not affect any other bits in the register, write the value
0b0100_0000_0000_0000 to the register.
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PCI Bridge
15
14
13
12
11
10
9
8
7
6
5
4
3
0
Field DPERR SSERR RM-A RT-A ST-A DEVSEL_T DPD FB-BC
—
66MHzC CL
—
Reset
R/W
0000_0000_1011_0000
R/W
R
R/W
Addr
0x06
Figure 9-36. PCI Bus Status Register
Table 9-23. describes the PCI bus status register fields.
Table 9-23. PCI Bus Status Register Description
Bits
Name
Description
15
Detected parity error Set whenever the PCI bridge detects a parity error on the PCI bus, even if parity
error handling is disabled (as controlled by bit 6 in the PCI bus command register).
14
13
Signaled system error Set whenever the PCI bridge asserts SERR on the PCI bus.
Received master-abort Set whenever the PCI bridge, acting as the PCI master on the PCI bus, terminates
a transaction (except for a special-cycle) using master-abort.
12
11
Received target-abort Set whenever a PCI bridge-initiated transaction on the PCI bus is terminated by
a target-abort.
Signaled target-abort Set whenever the PCI bridge, acting as the PCI target on the PCI bus, issues a
target-abort to a PCI master.
10–9
8
DEVSEL timing
Hardwired to 0b00, indicating that the PCI bridge uses fast device-select timing
on the PCI bus.
Data parity detected Set upon detecting a data parity error on the PCI bus. Three conditions must be
met for this bit to be set:
• The PCI bridge detects a parity error.
• The PCI bridge is acting as the bus master for the operation in which the error
occurred.
• Bit 6 in the PCI bus command register is set.
7
Fast back-to-back
capable
Hardwired to 1, indicating that the PCI bridge as a target is capable of accepting
fast back-to-back transactions.
6
5
—
Reserved, should be cleared.
66-MHz capable
This bit is read-only and indicates that the PCI bridge is capable of 66-MHz PCI
bus operation on the PCI bus.
4
Capabilities List
—
Hardwired to 1, indicating that the PCI bridge implements new capabilities on the
PCI bus.
3–0
Reserved, should be cleared.
9.11.2.5 Revision ID Register
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PCI Bridge
7
0
Field
Reset
R/W
RID
R
Addr
0x08
Figure 9-37. Revision ID Register
Table 9-24. Revision ID Register Description
Reset
Bits
Name
Description
Value
7–0
Revision ID
Revision Specifies a device-specific revision code for the PowerQUICC II
Dependent (assigned by Freescale). Revision ID = 0x11 for .25 micron revisions
A.0, B.1, and C.0
9.11.2.6 PCI Bus Programming Interface Register
7
0
Field
Reset
R/W
PI
R
Addr
0x09
Figure 9-38. PCI Bus Programming Interface Register
Table 9-25. PCI Bus Programming Interface Register Description
Bits
7–0
Name
Description
Programming interface 0x00 When the PCI bridge is configured as host bridge.
0x01 When the PCI bridge is configured as a peripheral device to indicate the
programming model supports the I O interface.
2
9.11.2.7 Subclass Code Register
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PCI Bridge
7
0
Field
Reset
R/W
SC
0000_0000
R
Addr
0x0A
Figure 9-39. Subclass Code Register
Table 9-26. Subclass Code Register Description
Description
Bits
Name
7–0
Subclass code
Identifies more specifically the function of the PCI bridge (0x00 = host bridge)
9.11.2.8 PCI Bus Base Class Code Register
7
0
Field
Reset
R/W
BCC
R
Addr
0x0B
Figure 9-40. PCI Bus Base Class Code Register
Table 9-27. PCI Bus Base Class Code Register Description
Bits
Name
Base class code
Description
7–0
0x06 When the PCI bridge is configured as a host bridge to indicate “Host Bridge”.
0x0E When the PCI bridge is configured as a target device to indicate the device
is an agent and is I O capable.
2
NOTE: I O Compliancy
2
When configured as a PCI agent device, the value of the Interface, Subclass
Code, and Base Class Code Registers are 0x01, 0x00, and 0x0E
respectively, indicating that the PowerQUICC II supports the I O protocol.
2
The user should note that the I O support is not fully standard compliant.
2
9.11.2.9 PCI Bus Cache Line Size Register
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PCI Bridge
7
0
Field
Reset
R/W
CLS
0000_0000
R/W
Addr
0x0C
Figure 9-41. PCI Bus Cache Line Size Register
Table 9-28. PCI Bus Cache Line Size Register Description
Bits
Name
Description
7–0
Cache line size
Represents the cache line size of the system in terms of 32-bit words (eight 32-bit
words = 32 bytes). This register is read-write; however, an attempt to program this
register to any value other than 8 results in it being cleared.
9.11.2.10 PCI Bus Latency Timer Register
7
3
2
0
Field
Reset
R/W
LT
LT
R
0000_0000
0x0D
R/W
Addr
Figure 9-42. PCI Bus Latency Timer Register
Table 9-29. PCI Bus Latency Timer Register Description
Bits
Name
Description
7–3
Latency timer
Represents the maximum number of PCI clocks that the device, when mastering
a transaction, holds the bus after PCI bus grant has been negated. The value is
in PCI clocks. Refer to the PCI 2.2 specification for the rules by which the PCI bus
interface unit completes transactions when the timer has expired.
2–0
Read-only least-significant bits of the latency timer. (The latency timer value is
programmed in multiples of eight.)
9.11.2.11 Header Type Register
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PCI Bridge
7
6
0
Field
Reset
R/W
MD
HT
0000_0000
R
Addr
0x0E
Figure 9-43. Header Type Register
Table 9-30. Header Type Register Description
Description
Bits
Name
7
Multifunction device
Header type
The PCI bridge is not a multifunction PCI device.
Identifies the layout of bytes 0x10–0x3F of the configuration address space.
6–0
9.11.2.12 BIST Control Register
7
0
Field
Reset
R/W
BIST_CTRL
0000_0000
R
Addr
0x0F
Figure 9-44. BIST Control Register
Table 9-31. BIST Control Register Description
Bits
7–0
Name
Description
BIST control
Optional register for control and status of built-in self test (BIST)
9.11.2.13 PCI Bus Internal Memory-Mapped Registers Base Address Register
(PIMMRBAR)
In agent mode, the PCI bridge provides one base address register called the PCI bus internal
memory-mapped registers base address register (PIMMRBAR) to allow a host processor access to the
PowerQUICC II’s internal memory-mapped registers. Transactions from PCI that “hit” the PIMMRBAR
are translated to the IMMR and sent to the logic that controls the internal memory-mapped registers.
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PCI Bridge
31
17
16
Field
BA
BA
Reset
R/W
0000_0000_0000_0000
R/W
Addr
0x12
15
4
3
2
1
0
Field
Reset
R/W
BA
PRE
T
MSI
0000_0000_0000_0000
R/W
Addr
0x10
Figure 9-45. PCI Bus Internal Memory-Mapped Registers Base Address Register (PIMMRBAR)
Table 9-32 describes PIMMRBAR fields.
Table 9-32. PIMMRBAR Field Descriptions
Bits
Name
Description
31–17
16–4
Base address
Base address
Indicates the base address for the inbound configuration window.
Hardwired to zeros, indicating that the PCI bridge requires a 128-KByte space for
the configuration registers.
3
Prefetchable
Type
Hardwired to 0 to indicate that this address region is not prefetchable.
2–1
Hardwired to 00 to indicate that the address can be located anywhere in 32-bit
address space.
0
Memory space indicator Address is mapped to memory space.
9.11.2.14 General Purpose Local Access Base Address Registers (GPLABARx)
Two general purpose local access base address registers (GPLABARx) are provided to allow access to
local memory space. These registers are closely tied to PIBARx and PICMRx (see Section 9.11.1.16, “PCI
the PICMRx mask. Similarly, a write to PIBARx causes a write to GPLABARx of the non-masked bits of
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PCI Bridge
31
16
Field
Reset
R/W
BA
0000_0000_0000_0000
R/W
Addr
0x16 (GPLABAR0); 0x1A (GPLABAR1)
15
12
11
4
3
2
1
0
Field
Reset
R/W
BA
BA
0000_0000_0000_0000
R/W
PRE
T
MSI
Addr
0x14 (GPLABAR0); 0x18 (GPLABAR1)
Figure 9-46. General Purpose Local Access Base Address Registers (GPLABARx)
Table 9-33. GPLABARx Field Descriptions
Bits
Name
Description
31–12
Base address
Represents the base address for the inbound GPLA memory window. The number
of upper bits that the PCI bridge allows to be writable is selected through the PICMR;
11–4
3
Hardwired to zeros. (The minimum window size allowed is 4K.)
Prefetchable
Type
Corresponds to the prefetchable bit in the PICMR; see Section 9.11.1.17, “PCI
2–1
0
Hardwired to 00 to indicate that the address can be located anywhere in 32-bit
address space.
Memory space indicator Address is mapped to memory space (hardwired to 0).
9.11.2.15 Subsystem Vendor ID Register
15
0
Field
Reset
R/W
SVID
0000_0000_0000_0000
R/W
Addr
0x2C
Figure 9-47. Subsystem Vendor ID Register
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PCI Bridge
Table 9-34. Subsystem Vendor ID Register Description
Description
Bits
Name
Vendor ID
15–0
Identifies the add-in board or subsystem where the PCI device resides.
9.11.2.16 Subsystem Device ID Register
15
0
Field
Reset
R/W
SDID
0000_0000_0000_0000
R/W
Addr
0x2E
Figure 9-48. Subsystem Device ID Register
Table 9-35. Subsystem Device ID Description Register
Bits
Name
Subsystem ID
Description
15–0
Identifies the add-in board or subsystem where the PCI device resides.
9.11.2.17 PCI Bus Capabilities Pointer Register
7
0
Field
Reset
R/W
CP
0100_1000
R
Addr
0x34
Figure 9-49. PCI Bus Capabilities Pointer Register
Table 9-36. PCI Bus Capabilities Pointer Register Description
Bits
7–0
Name
Capabilities pointer
Description
Specifies the byte offset in the configuration space containing the first item in the
capabilities list.
9.11.2.18 PCI Bus Interrupt Line Register
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PCI Bridge
7
0
Field
Reset
R/W
IL
0000_0000
R/W
Addr
0x3C
Figure 9-50. PCI Bus Interrupt Line Register
Table 9-37. PCI Bus Interrupt Line Register Description
Bits
7–0
Name
Description
Interrupt line
Contains the interrupt routing information. Software can use this register to hold
information regarding which input of the system interrupt controller the INTA
signal is attached to. Values in this register are specific to the system
architecture.
9.11.2.19 PCI Bus Interrupt Pin Register
7
0
Field
Reset
R/W
IP
0000_0001
R
Addr
0x3D
Figure 9-51. PCI Bus Interrupt Pin Register
Table 9-38. PCI Bus Interrupt Pin Register Description
Description
Bits
7–0
Name
Interrupt Pin
Indicates which interrupt pin the device (or function) uses (0x01 = INTA).
9.11.2.20 PCI Bus MIN GNT
7
0
Field
Reset
R/W
MIN GNT
0000_0000
R
Addr
0x3E
Figure 9-52. PCI Bus MIN GNT
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PCI Bridge
Table 9-39. PCI Bus MIN GNT Description
Description
Bits
7–0
Name
MIN GNT
Specifies the length of the device’s burst period. The value 0x00 indicates that
the PCI bridge has no major requirements for the settings of latency timers.
9.11.2.21 PCI Bus MAX LAT
7
0
Field
Reset
R/W
MAX LAT
0000_0000
R
Addr
0x3F
Figure 9-53. PCI Bus MAX LAT
Table 9-40. PCI Bus MAX LAT Description
Description
Bits
7–0
Name
MAX LAT
Specifies how often the device needs to gain access to the PCI bus. The value
0x00 indicates that the PCI bridge has no major requirements for the settings of
latency timers.
9.11.2.22 PCI Bus Function Register
The PCI bus function register, shown in Figure 9-54, is used to determine the configuration of the PCI bus
interface.
15
6
5
4
3
2
1
0
TRGT_
MSTR_
Field
—
CFG_LOCK
—
PCI_HA
LATENCY_DIS LATENCY_DIS
Reset
R/W
0000_0000_0010_0000
R/W
R
Addr
0x44
Figure 9-54. PCI Bus Function Register
Table 9-41. describes PCI bus function register fields.
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Table 9-41. PCI Bus Function Register Field Descriptions
Name Description
Bits
15–6
5
—
Reserved, should be cleared.
CFG_LOCK
Agent mode: Setting CFG_LOCK prevents an external PCI master from
accessing the configuration space while the 60x bus is doing internal
configuration. It is explicitly set and cleared by the 60x bus.
0 PCI bridge accepts accesses to the PCI configuration space or the internal
memory-mapped configuration space.
1 PCI bridge retries all accesses to the PCI configuration space or the internal
memory-mapped configuration space.
Host mode: the PCI configuration space is not accessible from the PCI side
when the device is in host mode; therefore, this bit applies only for the internal
memory-mapped configuration space.
0 PCI bridge accepts accesses to the internal memory-mapped configuration
space.
1 PCI bridge retries all accesses to the internal memory-mapped configuration
space.
4-3
2
—
Reserved, should be cleared.
TRGT_LATENCY_DIS Target latency time-out disable. Controls whether the PCI bridge as a target
time-outs when the first data phase of a transaction has not completed in 16 PCI
cycles.
0 Target latency time-out enabled.
1 Target latency time-out disabled.
1
0
MSTR_LATENCY_DIS Master latency timer disable. Controls whether the PCI bridge as a master ends
a transaction after the expiration of the master latency timer. See
0 Master latency timer enabled.
1 Master latency timer disabled.
PCI_HA
Set or cleared by a Power-On configuration bit on power-up and is read-only.
0 PCI interface is in host mode
1 PCI interface is in agent mode
9.11.2.23 PCI Bus Arbiter Configuration Register
The PCI bus arbiter configuration register, shown in Figure 9-55, is used to determine the configuration of
the PCI bus arbiter. Only 1-byte or 2-byte accesses to address offset 0x46 are allowed.
15
14
13
7
6
4
3
1
0
PCI_
ARB_DIS
PCI_
BRIDGE MP
Field
PM
—
PCI_BUSMP
—
1
Reset
R/W
0 000_0000_0000_0000
R/W
Addr
0x46
1
Figure 9-55. PCI Bus Arbiter Configuration Register
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PCI Bridge
Table 9-42. describes the PCI bus arbiter configuration register fields.
Table 9-42. PCI Bus Arbiter Configuration Register Field Description
Bit
Name
Description
15
PCI_ARB_DIS
Determines if the PCI bridge is the PCI arbiter on the PCI bus. Set or cleared by
(PCI_CFG[1] pin value) the PIC_CFG[1] pin value after hard reset.
0 PCI bridge is the PCI arbiter.
1 PCI bridge is not the PCI arbiter. The PCI bridge presents its request on REQ0
to the external arbiter and receives its grant on GNT0.
14
Parking Mode
Controls which device receives the bus grant when there are no outstanding bus
requests and the bus is idle.
0 The bus is parked with the last device to use the bus.
1 The bus is parked with the PCI bridge.
13–7
6-4
—
Reserved, should be cleared.
PCI Bus Master
Priorities
Determines the arbitration priority given to the different masters on the PCI bus.
Bit 6 corresponds to the priority of the master sourcing REQ0, bit 5 corresponds
to REQ1, and bit 4 corresponds to REQ2.
0
1
Master n has a low priority.
Master n has a high priority.
3–1
0
—
Reserved, should be cleared.
PCI Bridge Master
Priority
Determines the PCI bridge’s arbitration priority.
0 The PCI bridge has a low priority.
1 The PCI bridge has a high priority.
9.11.2.24 PCI Hot Swap Register Block
The PCI Hot Swap register block, shown in Figure 9-56, is a set of registers in a capability structure. It
contains the Hot Swap control status register itself, as well as other fields as required by the capabilities
list format.
31
24
23
16
HS_CSR (See Section 9.11.2.25, “PCI Hot Swap
Field
—
Reset
R/W
0000_0000_0000_0000
R/W
Addr
0x4A
15
8
7
0
Field
Reset
R/W
NXT_PTR
R/W
CAP_ID
R
0000_0000_0000_0110
0x48
Addr
Figure 9-56. Hot Swap Register Block
Table 9-43 describes the Hot Swap register block fields.
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Table 9-43. Hot Swap Register Block Field Descriptions
Name Description
Bits
31–24
23–16
—
Reserved. Should be cleared.
HS_CSR
Hot Swap control status register; see Section 9.11.2.25, “PCI Hot Swap Control
15–8
7–0
NXT_PTR
CAP_ID
Next pointer—an offset into the device’s PCI configuration space for the location
of the next item in the capabilities linked list. A value of 0x00 indicates that this is
the last item in the list.
CompactPCI ® Hot Swap capability ID (read only).
9.11.2.25 PCI Hot Swap Control Status Register
23
22
21
20
19
18
17
16
Field
Reset
R/W
INS
EXT
—
LOO
—
EIM
—
0000_0000
R/W
Addr
0x4A
Figure 9-57. Hot Swap Control Status Register
Table 9-44. Hot Swap Control Status Register Field Descriptions
Bit
Name
Description
23
INS
ENUM status: insertion. Write a ‘1’ to clear this bit.
0 ENUM is not asserted
1 ENUM is asserted
22
EXT
ENUM status: extraction. Write a ‘1’ to clear this bit.
0 ENUM is not asserted
1 ENUM is asserted
21–20
19
—
Reserved. Should be cleared.
LOO
LED on/off when the hardware is in state H2. Read/write-able.
0 LED off
1 LED on
18
17
—
Reserved. Should be cleared.
EIM
ENUM signal mask. Read/write-able.
0 Enable signal
1 Mask signal
16
—
Reserved. Should be cleared.
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9.11.2.26 PCI Configuration Register Access from the Core
The 60x bus master cannot directly access the PCI configuration registers because they are not in the
internal memory-mapped configuration register’s space. The 60x bus master must first load CFG_ADDR
(at offset 0x10900 in the memory-mapped configuration registers block) with a 32-bit register address in
the form ‘0x8000_0nnn,’ where nnn is the address offset of the desired PCI configuration register. The data
can then be accessed in CFG_DATA (at offset 0x10904 in the internal memory map). See
When accessing the PCI bridge’s PCI configuration registers with the 60x bus master, note the following:
•
•
The bus number and device number fields of the CFG_ADDR register should be cleared.
Accesses to CFG_ADDR or CFG_DATA which are greater than 4 bytes generate an illegal register
• Accesses to CFG_DATA without a valid offset in CFG_ADDR generates an I/O transaction
on the PCI bus.
9.11.2.27 PCI Configuration Register Access in Big-Endian Mode
Since the local CPU (internal core or external) is operating in big-endian mode, software must byte-swap
the data of the configuration register before performing an access. That is, the data appears in the core
register in ascending significance byte order (LSB to MSB). Software loads the configuration register
address and the configuration register data into the core register in ascending significance byte order (LSB
to MSB).
Note that in the following examples, the data in the configuration register (at 0x18) is shown in
little-endian order. This is because all the internal registers are intrinsically little-endian.
Example: configuration sequence, 2-byte data write to register at address offset 0x1A for PCI bus.
Initial values:
r0 contains 0x1800_0080
r1 contains IMMR+0x10900
r2 contains IMMR+0x10904
r3 contains 0xDDCC_BBAA
Register at 0x18 contains 0xFFFF_FFFF (1B to 18)
Code sequence:
stw
sth
r0,0(r1)
r3,2(r2)
Results: Address IMMR+0x10900 contains 0x8000_0018 (MSB to LSB)
Address IMMR+0x10904 contains 0xXXXX_AABB (MSB to LSB) where ‘XXXX’ is
the old value and is not affected the sth.
Note: the address of PCI_CFG_DATA must match the offset address 0x1A.
Register at 0x18 contains 0xAABB_FFFF (1B to 18)
This example shows an address of IMMR+0x10906 used to access the PCI_CFG_DATA. This was done
in order to align the data with the address 0x1A. The address used to access PCI_CFG_DATA can have a
value of IMMR+0x10904, IMMR+0x10905, IMMR+0x10906, or IMMR+0x10907. The two least
significant bits of the address used to access PCI_CFG_DATA should match the byte-wise offset of the
register being accessed. For instance, if 0x0D is the offset of the register being accessed, then the address
used to access PCI_CFG_DATA must be IMMR+0x10905.
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9.11.2.27.1 Additional Information on Endianess
The endianess of both the MPC826x's peripheral logic (GPCR[LE_MODE]—see the following section)
and the MPC826x's 603e CPU core (MSR[LE]) must be set to the same endianess configuration—that is
both must be set for little or big endian operation.
For applications where little endian (LE) devices, such as those commonly found on the PCI bus, share
memory with the MPC826x, it is recommended to leave the MPC826x's 603e core CPU and peripheral
logic in the big endian (BE) modes and then to use a region of the PowerQUICC II local memory for
LE-formatted data. When a little endian PCI device stores data to this memory region, the PowerQUICC
II internal peripheral logic (in big endian mode) stores the data into memory in LE format. Likewise, when
a little-endian PCI device reads data from this memory region, the MPC826x internal peripheral logic (in
BE mode) provides the data to the PCI device in LE format.
A little-endian PCI device can share this LE memory region with the PowerQUICC II local processor
(603e core CPU) running in big endian if, when the PowerQUICC II accesses that LE region, it uses the
lwbrx and stwbrx commands. The lwbrx command byte-swaps the LE data from that region so the 603e
CPU sees the data in BE format. Similarly, the stwbrx command byte-swaps the BE data from the 603e
processor being stored to that region of memory, so it is stored into the memory region in LE format.
For the MPC603e and the PowerQUICC II implementations, there is NO latency difference associated
with lwbrx and stwbrx commands compared to the other load and store commands.
9.11.2.27.2 Notes on GPCR[LE_MODE]
PowerQUICC II. The default value of GPCR[LE_MODE] (offset: 0x1087C) is 0. If LE_MODE is set
while a program is executing, care should be taken as to how subsequent accesses to the PCI
memory-mapped registers are made. Consider the following two examples (assume internal memory starts
at 0x04700000):
Example 1— Accessing PCI memory-mapped registers before GPCR[LE_MODE] is set. Assume that
one wants to use CPU software to set CTM of PCI DMA0 mode register
(DMAMR0[CTM]) located at 0x04710500. The value constructed from the bit field
description of the DMAMR0 is 0x00000004. However, the value written to this register is
0x04000000—the byte-swapped version of 0x00000004.
Example 2—Accessing PCI memory-mapped registers after GPCR[LE_MODE] is set. Assume that, after
GPCR[LE_MODE] is set, one wants to use CPU software to set DMAMR0[CTM].
Because of address munging, this register is now located at 0x04710504. This new address
is derived from the following:
1.The register is located at 0x04710500.
2.For a 4-byte access, address munging dictates that the XOR value is 0b100 (refer to
Chapter 4 of the Programming Environments Manual for 32-Bit Implementations of the
PowerPC Architecture).
3.The last three bits of 0x04710500 is 0b000.
4.XOR 0b000 with 0b100 (0b000 ⊕ 0b100 = 0b100).
5.Therefore, the munged address of this register would be 0x04710504.
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PCI Bridge
Therefore, to set CTM in PCI DMA0 mode register, 0x00000004 is written to 0x04710504.
9.11.2.28 Initializing the PCI Configuration Registers
The configuration registers are initialized to the reset values shown in the register descriptions. However,
they can also be initialized to user-defined values loaded directly from the EEPROM used to configure the
PowerQUICC II by setting the ALD_EN (auto-load enable) bit in the hard reset configuration word; refer
To initialize configuration registers from an EEPROM, the user builds a contiguous table of register
initialization data structures in a user-defined space within the EEPROM. Each data structure, shown in
Figure 9-58, contains the address of a specific register and its initialization data, as well as some control
information. The last data structure entry in the table is marked by setting its ‘Last’ bit.
Offset from the table
start address
0
28
29
30
31
0x00
Destination address
Destination data
0x04
—
Last
Size[1:0]
0x08
0x0C
•
•
•
Figure 9-58. Data Structure for Register Initialization
Table 9-45. describes the data structure fields.
Table 9-45. Bit Settings for Register Initialization Data Structure
Offset
Bits
Name
Description
0x00
0x04
0–31
0–28
29
Address
—
Contains the absolute destination address to which the data is written.
Reserved, should be cleared.
Last
Indicates that this is the last initialization transaction to be performed.
0
1
Not last transaction
Last transaction
30–31
0–31
SIZE
Data
Data size in bytes
00 4 bytes
01 1 byte
10 2 bytes
11 3 bytes
0x08
Contains the data to be written to the specified address. Data bytes are
written according to the value specified in the SIZE field and according
to big-endian byte ordering.
Note that the data structure description assumes the following:
•
•
Addresses refer to 60x bus addresses.
Address and data byte ordering are big-endian.
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•
Accesses to PCI configuration registers are indirect (through PCI CFG_ADDR and PCI
CFG_DATA).
A pointer located at address 0x4 of the EEPROM (right after the hard reset configuration word) defines
the beginning of the initialization table. The table should be placed beyond the reset configuration data to
avoid the EEPROM bytes dedicated to the eight possible hard reset configuration words (refer to
EEPROM start address + 0x00
Configuration byte
Init Table Pointer
0x04
0x08
Configuration byte
0x10
Configuration byte
Init Table Pointer + 0x00
+0x0C
Address, data, size
Address, data, size
Address, data, size
+0x1A
+0x28
Address, data, size,
LAST
Figure 9-59. PCI Configuration Data Structure for the EEPROM
After a hard reset, if the auto-load enable bit has been set in the hard reset configuration word, a special
internal CP routine checks the EEPROM contents and loads the configuration data into the specified
addresses. Note that the initialization data can be loaded into any memory location (not restricted to the
PCI configuration space) by this routine.
9.12 Message Unit (I O)
2
The embedded processor is often part of a larger system containing many processors and distributed
memory. These processors tend to work on tasks independent of the host processor(s) and other peripheral
processors in the system. Because of the independent nature of the tasks, it is necessary to provide a
communication mechanism between the peripheral processors and the rest of the system. One such method
is the use of messages. The PCI bridge provides a messaging unit to further facilitate communications
between host and peripheral. The PCI bridge’s message unit can operate with either generic messages and
door bell registers, or as an I O interface.
2
9.12.1 Message Registers
The PCI bridge contains two inbound message registers and two outbound message registers. The registers
are each 32 bits. The inbound registers allow a remote host or PCI master to write a 32-bit value which in
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turn causes an interrupt to the local processor that implements the PowerPC architecture because the
register indirectly drives an interrupt line to the local processor. The outbound register allows the local
processor to write an outbound message which, in turn, causes the outbound interrupt signal INTA to
assert.
The interrupt to the local processor is cleared by setting the appropriate bit in the inbound message
interrupt status register. The interrupt to PCI (INTA) is cleared by setting the appropriate bit in the
outbound interrupt status register.
9.12.1.1 Inbound Message Registers (IMRx)
The inbound message registers, described in Figure 9-60 and Figure 9-46, are accessible from the PCI bus
and the 60x bus in both host and agent modes.
31
16
Field
Reset
R/W
IMSGx
Undefined
R/W
Addr
0x10452 (IMR0); 0x10456 (IMR1)
15
0
Field
Reset
R/W
IMSGx
Undefined
R/W
Addr
0x10450 (IMR0); 0x10454 (IMR1)
Figure 9-60. Inbound Message Registers (IMRx)
Table 9-46. IMRx Field Descriptions
Description
Bits
Name
31–0
IMSGx
Inbound message x. Contains generic data to be passed between the local
processor and external hosts.
9.12.1.2 Outbound Message Registers (OMRx)
The outbound message registers, described in Figure 9-61 and Figure 9-47, are accessible from the PCI
bus and the 60x bus in both host and agent modes.
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31
16
Field
Reset
R/W
OMSGx
Undefined
R/W
Addr
0x1045A (OMR0); 0x1045E (OMR1)
15
0
Field
Reset
R/W
OMSGx
Undefined
R/W
Addr
0x10458 (OMR0); 0x1045C (OMR1)
Figure 9-61. Outbound Message Registers (OMRx)
Table 9-47. OMRx Field Descriptions
Description
Bits
Name
31–0
OMSGx
Outbound message x. Contains generic data to be passed between the local
processor and external hosts.
9.12.2 Door Bell Registers
The PCI bridge contains an inbound and an outbound door bell register. The registers are 32-bit. The
inbound door bell allows a remote processor to set a bit in the register from the PCI bus. This, in turn,
causes the PCI bridge to generate an interrupt to the local processor. The local processor can write to the
outbound register which causes the outbound interrupt signal INTA to assert thus interrupting the remote
processor on the PCI bus.
9.12.2.1 Outbound Doorbell Register (ODR)
ODR, described in Figure 9-62 and Table 9-48, is accessible from the PCI bus and the 60x bus in both host
and agent modes.
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31
29
28
16
Field
—
ODRx
0000_0000_0000_0000
0x10462
Reset
R/W
Addr
15
0
Field
Reset
R/W
ODRx
0000_0000_0000_0000
0x10460
Addr
Figure 9-62. Outbound Doorbell Register (ODR)
Table 9-48. ODR Field Descriptions
Bits
Name
Access
Description
Reserved, should be cleared.
31–29
28–0
—
R
ODRx Write 1 to set from local processor. Outbound door bell x, where x is each bit. Writing a bit in
Write 1 to clear from PCI.
this register from the local processor causes an interrupt
(INTA) to be generated.
9.12.2.2 Inbound Doorbell Register (IDR)
IDR, described in Figure 9-63 and Table 9-49, is accessible from the PCI bus and the 60x bus in both host
and agent modes.
31
30
16
Field IMC
IDRx
0000_0000_0000_0000
R/W
Reset
R/W
Addr
0x1046A
15
0
Field
IDRx
0000_0000_0000_0000
R/W
Reset
R/W
Addr
0x10468
Figure 9-63. Inbound Doorbell Register (IDR)
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Table 9-49. IDR Field Descriptions
Access
Bits
Name
Description
31
IMC
Write 1 to set from PCI.
Machine check. Writing to this bit will generate a machine
Write 1 to clear from local processor. check interrupt to the local processor.
30–0
IDRx
Write 1 to set from PCI.
Inbound door bell x, where x is each bit. Writing a bit in this
Write 1 to clear from local processor. register from the PCI bus causes an interrupt to be
generated through the PCI bridge to the local processor.
9.12.3 I2O Unit
The Intelligent Input Output specification (I O) was established in the industry to allow
2
architecture-independent I/O subsystems to communicate with an OS through an abstraction layer. The
specification is centered around a message passing scheme. An I O embedded peripheral (IOP) is
2
comprised of memory, processor, and input/output device(s). An IOP dedicates space in its local memory
to hold inbound (from the remote host) and outbound (to the remote host) messages. The space is managed
as memory-mapped FIFOs, with pointers to this memory maintained in hardware.
Messages are made up of frames which are a minimum of 64-bytes in length. The message frame address
(MFA) is the address which points to the first byte of the message frame. The messages are located in
local-system memory. Tracking of the status and location of these messages is done with four FIFOs (two
FIFOs for inbound and two for outbound messages) also located in local-system memory. Hardware
registers inside the PCI bridge’s core logic manage these FIFOs. One FIFO in each queue keeps track of
the free MFAs (Free_LIST FIFO). The other FIFO keeps track of the MFAs which have posted messages
order that these queues must follow.
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Local memory
Inbound free list FIFO
Message
frame
Message
frame
Message
frame
Message
frame
Message
frame
Message
frame
Message
frame
Message
frame
Message
frame
Message
frame
Message
frame
Message
frame
Message
frame
Head pointer
Local processor write
MFA
MFA
MFA
Tail pointer
PCI master read
PCI master write
Inbound
queue
port
Inbound post list FIFO
Head pointer
MFA
MFA
MFA
MFA
MFA
Tail pointer
Local processor read
Local processor read
Outbound free list FIFO
Head pointer
MFA
MFA
MFA
Tail pointer
PCI master write
PCI master read
Outbound
queue
port
Outbound post list FIFO
Head pointer
Message
frame
Message
frame
Message
frame
MFA
MFA
MFA
MFA
MFA
Tail pointer
Local processor write
Figure 9-64. I O Message Queue
2
I O defines extensions for the PCI bus hardware through which message queues are managed in hardware.
2
9.12.3.1 PCI Configuration Identification
A host identifies an IOP by its PCI class code. When I O is enabled, configuration information is provided
2
through the PCI configuration space to the host. Refer to the following:
•
•
•
9.12.3.2 Inbound FIFOs
The inbound FIFO allows external PCI masters to post messages to the local processor. I O defines two
2
inbound FIFOs—an inbound post FIFO and an inbound free FIFO.
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The following registers should be accessed only from the 60x bus and only in agent mode. Accesses while
in host mode or from the PCI bus have undefined results.
9.12.3.2.1
Inbound Free_FIFO Head Pointer Register (IFHPR) and
Inbound Free_FIFO Tail Pointer Register (IFTPR)
The inbound free list FIFO holds the list of empty inbound MFAs. The external PCI master reads IFQPR
pointed to by the inbound free list tail pointer register, (IFTPR+QBAR). The PCI bridge’s I O unit then
2
advances IFTPR.
If the inbound free list is empty (no free MFA entries), the unit returns 0xFFFF_FFFF.
Free MFAs from the local processor are posted to the inbound free list FIFO that is pointed to by the
inbound free_FIFO head pointer register, described in Figure 9-65 and Table 9-50. The local processor is
responsible for updating this register.
31
20
19
16
Field
Reset
R/W
QBA
0000_0000_0000_0000
IFHP
R/W
R
Addr
0x104A2
15
2
1
0
Field
Reset
R/W
IFHP
—
0000_0000_0000_0000
R/W
R
Addr
0x104A0
Figure 9-65. Inbound Free_FIFO Head Pointer Register (IFHPR)
Table 9-50. IFHPR Field Descriptions
Bits
Name
Description
31–20 QBA
Queue base address. When read returns the contents of QBAR bits 31-20.
19–2
IFHP
Inbound free_fifo head pointer. Local memory offset of the head pointer of the inbound free list
FIFO.
1–0
—
Reserved, should be cleared.
Free MFAs are picked up by the PCI masters that are pointed to by the inbound free_FIFO tail pointer,
described in Figure 9-66 and Table 9-51. The PCI read is performed at the inbound queue port. Hardware
automatically advances this register after every read.
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31
20
19
16
Field
QBA
0000_0000_0000_0000
IFTP
R/W
Reset
R/W
R
Addr
0x104AA
15
2
1
0
Field
Reset
R/W
IFTP
—
0000_0000_0000_0000
R/W
R
Addr
0x104A8
Figure 9-66. Inbound Free_FIFO Tail Pointer Register (IFTPR)
Table 9-51. IFTPR Field Descriptions
Bits
Name
Description
31–20 QBA
19–2 IFTP
Queue base address. When read returns the contents of QBAR bits 31-20.
Inbound free_FIFO tail pointer. Local memory offset of the tail pointer of the inbound free list FIFO.
Reserved, should be cleared.
1–0
—
9.12.3.2.2
Inbound Post_FIFO Head Pointer Register (IPHPR) and
Inbound Post_FIFO Tail Pointer Register (IPTPR)
The inbound post FIFO holds MFAs from external PCI masters which are posted to the local processor.
PCI masters, external to the PCI bridge, write to the head of the FIFO by writing the MFA to IFQPR (refer
to Section 9.12.3.4.1, “Inbound FIFO Queue Port Register (IFQPR)”). The I O unit transfers the MFA to
2
the location pointed to by the IPHPR. The local address is QBAR + IPHPR.
Once the MFA has been written to the queue in local memory, the PCI bridge’s I O unit advances the
2
IPHPR to set up for the next message. This causes an interrupt to be asserted to the local processor. The
inbound post queue interrupt bit in the inbound interrupt status register (IMISR[IPQI]) is set to indicate
this condition (refer to Table 9-62). The local processor acknowledges the message (i.e. MFA) by writing
a one to the appropriate status bit (IMISR[IPQI]) to clear it. The local processor fetches the MFA by
reading the contents of the IPTPR. After the local processor has read the message pointed to by the MFA,
the local processor must advance the IPTPR. Once the processor has completed use of the message, it must
return the message buffer (i.e. MFA) to the inbound free list FIFO.
PCI masters post MFAs to the inbound post list FIFO that is pointed to by the inbound post_FIFO head
pointer register, described in Figure 9-67 and Table 9-52. The PCI writes are addressed to the inbound
queue port. Hardware (in the I O module) automatically advances the IPHPR after every write.
2
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31
20
19
16
Field
Reset
R/W
QBA
0000_0000_0000_0000
IPHP
R/W
R
Addr
0x104B2
15
2
1
0
Field
Reset
R/W
IPHP
—
0000_0000_0000_0000
R/W
R
Addr
0x104B0
Figure 9-67. Inbound Post_FIFO Head Pointer Register (IPHPR)
Table 9-52. IPHPR Field Descriptions
Bits
Name
Description
31–20 QBA
Queue base address. When read returns the contents of QBAR bits 31-20.
19–2
IPHP
Inbound post_FIFO head pointer. Local memory offset of the head pointer of the inbound post list
FIFO.
1–0
—
Reserved, should be cleared.
MFAs posted by PCI hosts are picked up by the local processor via the inbound post_FIFO tail pointer
register, described in Figure 9-68 and Table 9-53. The local processor is responsible for updating this
register.
31
20
19
16
Field
Reset
R/W
QBA
0000_0000_0000_0000
IPTP
R/W
R
Addr
0x104BA
15
2
1
0
Field
Reset
R/W
IPTP
—
0000_0000_0000_0000
R/W
R
Addr
0x104B8
Figure 9-68. Inbound Post_FIFO Tail Pointer Register (IPTPR)
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Table 9-53. IPTPR Field Descriptions
Bits
Name
Description
31–20 QBA
Queue base address. When read returns the contents of QBAR bits 31-20.
19–2
1–0
IPTP
—
Inbound post_FIFO tail pointer. Local memory offset of the tail pointer of the inbound post list
FIFO.
Reserved, should be cleared.
9.12.3.3 Outbound FIFOs
The outbound queues are used to send messages from the local processor to a remote host processor. I O
2
defines two outbound FIFOs—an outbound post FIFO and an outbound free FIFO.
The following registers should be accessed only from the 60x bus and only in agent mode. Accesses while
in host mode or from the PCI bus have undefined results.
9.12.3.3.1
Outbound Free_FIFO Head Pointer Register (OFHPR) and
Outbound Free_FIFO Tail Pointer Register (OFTPR)
The outbound free list FIFO holds the MFAs of the empty outbound message locations in local memory.
When the local processor is ready to send an outbound message, it first fetches an empty MFA by reading
the OFTPR. It then writes the message into the MFA. The OFTPR is managed by the local processor.
When an external PCI master has completed use of a message that was posted in the outbound post FIFO
and wants to return the MFA to the free list, it writes to OFQPR (refer to Section 9.12.3.4.2, “Outbound
2
This, in turn, causes the outbound free head pointer to be advanced.
Free MFAs are returned by the PCI masters to the outbound free list FIFO that is pointed to by the
references the outbound queue port. The I O hardware automatically advances the address, (i.e. OFHPR)
2
after every write.
31
20
19
16
Field
Reset
R/W
QBA
0000_0000_0000_0000
OFHP
R/W
R
Addr
0x104C2
15
2
1
0
Field
Reset
R/W
OFHP
—
0000_0000_0000_0000
R/W
R
Addr
0x104C0
Figure 9-69. Outbound Free_FIFO Head Pointer Register (OFHPR)
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Table 9-54. OFHPR Field Descriptions
Bits
Name
Description
31–20 QBA
Queue base address. When read returns the contents of QBAR.
19–2
1–0
OFHP
—
Outbound free_FIFO head pointer. Local memory offset of the head pointer of the outbound free
list FIFO.
Reserved, should be cleared.
Free MFAs are picked up by the local processor pointed to by the outbound free_FIFO tail pointer register,
31
20
19
16
Field
Reset
R/W
QBA
0000_0000_0000_0000
OFTP
R/W
R
Addr
0x104CA
15
2
1
0
Field
Reset
R/W
OFTP
—
0000_0000_0000_0000
R/W
R
Addr
0x104C8
Figure 9-70. Outbound Free_FIFO Tail Pointer Register (OFTPR)
Table 9-55. OFTPR Field Descriptions
Bits
Name
Description
31–20 QBA
Queue base address. When read returns the contents of QBAR bits 31-20.
19–2
OFTP
Outbound free_FIFO tail pointer. Local memory offset of the tail pointer of the outbound free list
FIFO.
1–0
—
Reserved, should be cleared.
9.12.3.3.2
Outbound Post_FIFO Head Pointer Register (OPHPR) and
Outbound Post_FIFO Tail Pointer Register (OPTPR)
The outbound post FIFO holds MFAs which are posted from the local processor to external processors.
The local processor places messages in the outbound post FIFO by writing to the MFA to OPHPR +
QBAR. The local processor must then advance the OPHPR.
The PCI bridge’s PCI interrupt is generated (INTA) when the FIFO is not empty (head and tail pointers are
not equal). The outbound post queue interrupt bit is set in the outbound interrupt status register. The status
bit is cleared when the head and tail pointers are equal. The interrupt can be masked using the outbound
interrupt mask register.
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An external PCI master reads the outbound queue port register. This causes the PCI bridge’s I O unit to
2
read the MFA from local memory pointed to by the OPTPR+QBAR. The unit then advances the OPTPR.
When the FIFO is empty (head and tail pointers are equal), the unit returns 0xFFFF_FFFF.
The local processor posts MFAs to the outbound post list FIFO that is pointed to by the outbound
responsible for updating this register.
31
20
19
16
Field
Reset
R/W
QBA
0000_0000_0000_0000
OPHP
R/W
R
Addr
0x104D2
15
2
1
0
Field
Reset
R/W
OPHP
—
0000_0000_0000_0000
R/W
R
Addr
0x104D0
Figure 9-71. Outbound Post_FIFO Head Pointer Register (OPHPR)
Table 9-56. OPHPR Field Descriptions
Bits
Name
Description
31–20 QBA
Queue base address. When read returns the contents of QBAR bits 31-20.
19–2
OPHP
Outbound post_FIFO head pointer. Local memory offset of the head pointer of the outbound
post list FIFO.
1–0
—
Reserved, should be cleared.
Posted MFAs are picked up by PCI hosts that are pointed to by the outbound post_FIFO tail pointer
register, described in Figure 9-72 and Table 9-57. The PCI read is performed at the outbound queue port.
Hardware automatically advances this register after every read.
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31
20
19
16
Field
Reset
R/W
QBA
0000_0000_0000_0000
OPTP
R/W
R
Addr
0x104DA
15
2
1
0
Field
Reset
R/W
OPTP
—
0000_0000_0000_0000
R/W
R
Addr
0x104D8
Figure 9-72. Outbound Post_FIFO Tail Pointer Register (OPTPR)
Table 9-57. OPTPR Field Descriptions
Bits
Name
Description
31–20 QBA
Queue base address. When read returns the contents of QBAR bits 31-20.
19–2
OPTP
Outbound post_FIFO tail pointer. Local memory offset of the tail pointer of the outbound post
list FIFO.
1–0
—
Reserved, should be cleared.
9.12.3.4 I2O Registers
9.12.3.4.1
Inbound FIFO Queue Port Register (IFQPR)
IFQPR is used by PCI masters to access inbound messages in local memory. Local processor does not have
access to this port. IFQPR should be accessed only from the PCI bus. IFQPR is described in Figure 9-73
31
16
Field
Reset
R/W
IFQP
0000_0000_0000_0000
R/W
Addr
0x10442
15
0
Field
Reset
R/W
IFQP
0000_0000_0000_0000
R/W
Addr
0x10440
Figure 9-73. Inbound FIFO Queue Port Register (IFQPR)
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Table 9-58. IFQPR Field Descriptions
Description
Bits
Name
31–0
IFQP
Inbound FIFO queue port. Reading this register will return the MFA from inbound free
list FIFO. Writing to this register will post the MFA to the inbound post list FIFO.
9.12.3.4.2
Outbound FIFO Queue Port Register (OFQPR)
OFQPR is used by PCI masters to access outbound messages in local memory. Local processor does not
have access to this port. OFQPR should be accessed only from the PCI bus. OFQPR is described in
31
16
Field
Reset
R/W
OFQP
0000_0000_0000_0000
R/W
Addr
0x10446
15
0
Field
Reset
R/W
OFQP
0000_0000_0000_0000
R/W
Addr
0x10444
Figure 9-74. Outbound FIFO Queue Port Register (OFQPR)
Table 9-59. OFQPR Field Descriptions
Description
Bits
Name
31–0
OFQP
Outbound FIFO queue port. Reading this register will return the MFA from outbound
post list FIFO. Writing this register will post the MFA to the outbound free list FIFO.
9.12.3.4.3
Outbound Message Interrupt Status Register (OMISR)
OMISR contains the interrupt status of the I O, door bell, and outbound message registers. A PCI device
2
acknowledges the outbound message interrupt by writing a 1 to the appropriate status bit: OMISR[OM1I]
or OMISR[OM0I]. This clears both the interrupt and the corresponding status bit. The local processor
provokes an outbound message interrupt by writing to either of the two outbound message registers:
OMR0 or OMR1. OMISR should be accessed only from the PCI bus IFQPR should be accessed only from
the PCI bus.
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31
16
Field
Reset
R/W
—
0000_0000_0000_0000
0x10432
Addr
15
6
5
4
3
2
1
0
Field
Reset
R/W
—
OPQI
—
ODI
—
OM1I OM0I
0000_0000_0000_0000
0x10430
Addr
Figure 9-75. Outbound Message Interrupt Status Register (OMISR)
Table 9-60 describes OMISR fields.
Table 9-60. OMISR Field Descriptions
Bits
Name
R/W
Description
31–6
5
—
R
R
Reserved, should be cleared.
OPQI
Outbound post queue interrupt. When set indicates that a message or messages
are posted in the outbound queue. To clear the interrupt, software has to read all
MFAs in the outbound post FIFO. This bit is set regardless of the state of the
1
OPQIM mask bit.
4
3
—
R
R
Reserved, should be cleared.
ODI
Outbound doorbell interrupt. When set indicates that there is an outbound doorbell
interrupt.
2
1
—
R
Reserved, should be cleared.
OM1I
Read/ Outbound message 1 interrupt. When set indicates that there is an Outbound
Write 1 message 1 interrupt.
to clear
0
OM0I
Read/ Outbound message 0 interrupt. When set indicates that there is an Outbound
Write 1 message 0 interrupt
to clear
1
Note that when conditions for the Outbound Post Queue Interrupt assertion are valid, and OMIMR[OPQIM] is set,
OMISR[OPQI] is cleared. The application should always clear OMIMR[OPQIM] before referring to the content of
OMISR[OPQI].
9.12.3.4.4
Outbound Message Interrupt Mask Register (OMIMR)
OMIMR contains the interrupt mask of the I O, door bell, and message register events generated by the
2
local processor. OMIMR should be accessed only from the PCI bus.
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31
16
Field
—
Reset
R/W
0000_0000_0000_0000
0x10436
Addr
15
6
5
4
3
2
1
0
Field
Reset
R/W
—
OPQIM
0000_0000_0000_0000
—
ODIM
—
OM1IM OM0IM
0x10434
Addr
Figure 9-76. Outbound Message Interrupt Mask Register (OMIMR)
Table 9-61 describes OMIMR fields.
Table 9-61. OMIMR Field Descriptions
Bits
Name
R/W
Description
31–6
5
—
R
Reserved, should be cleared.
OPQIM
RW
Outbound post queue interrupt mask
0 Outbound post queue interrupt is allowed.
1 Outbound post queue interrupt is masked.
4
3
—
R
Reserved, should be cleared.
ODIM
RW
Outbound doorbell interrupt mask
0 Outbound doorbell interrupt is allowed.
1 Outbound doorbell interrupt is masked.
2
1
—
R
Reserved, should be cleared.
OM1IM
RW
Outbound message 1 interrupt mask
0 Outbound message 1 interrupt is allowed.
1 Outbound message 1 interrupt is masked.
0
OM0IM
RW
Outbound message 0 interrupt mask
0 Outbound message 0 interrupt is allowed.
1 Outbound message 0 interrupt is masked.
9.12.3.4.5
Inbound Message Interrupt Status Register (IMISR)
This register contains the interrupt status of the I O, door bell, and message register events. Writing a 1 to
2
the corresponding set bit will clear the bit. The events are generated by the PCI masters. IMISR should be
accessed only from the 60x bus and only in agent mode. Accesses while in host mode or from the PCI bus
have undefined results.
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31
16
Field
Reset
R/W
—
0000_0000_0000_0000
0x10482
Addr
15
9
8
7
6
5
4
3
2
1
0
Field
Reset
R/W
—
OFOI IPOI
—
IPQI MCI IDI
—
IM1I IM0I
0000_0000_0000_0000
0x10480
Addr
Figure 9-77. Inbound Message Interrupt Status Register (IMISR)
Table 9-62 describes IMISR fields.
Table 9-62. IMISR Field Descriptions
Bits
Name
Access
Description
31–9
8
—
R
Reserved, should be cleared.
OFOI
IPOI
R/Write 1 Outbound Free Overflow Interrupt. When set indicates that the Outbound
to clear
Free_FIFO Head pointer is equal to the Outbound Free_FIFO Tail pointer and
the queue is full. A machine check interrupt is generated.
7
R/Write 1 Inbound Post Overflow Interrupt. When set indicates that the Inbound
to clear
Post_FIFO Head pointer is equal to the Inbound Post_FIFO Tail pointer and the
queue is full. A machine check interrupt is generated.
6
5
—
R
Reserved, should be cleared.
IPQI
R/Write 1 Inbound Post Queue Interrupt. When set indicates that the PCI master has
to clear
posted an MFA to the Inbound Post queue.
4
3
MCI
IDI
R
Machine check interrupt. When set indicates that a machine check interrupt
condition has been generated by setting the Inbound doorbell register’s bit 31.
The interrupt is cleared by resetting the Inbound doorbell register’s bit 31.
R
R
Inbound doorbell interrupt. When set indicates that there is an Inbound
Doorbell interrupt.
2
1
—
Reserved, should be cleared.
IM1I
R/Write 1 Inbound message 1 interrupt. When set indicates that there is an Inbound
to clear message 1 interrupt.
0
IM0I
R/Write 1 Inbound message 0 interrupt. When set indicates that there is an Inbound
to clear message 0 interrupt.
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9.12.3.4.6
Inbound Message Interrupt Mask Register (IMIMR)
This register contains the interrupt mask of the I O, door bell, and message register events generated by
2
the PCI master. IMIMR should be accessed only from the 60x bus and only in agent mode. Accesses while
in host mode or from the PCI bus have undefined results.
31
16
Field
Reset
R/W
—
0000_0000_0000_0000
R/W
Addr
0x10486
15
9
8
7
6
5
4
3
2
1
0
Field
Reset
R/W
—
OFOIM IPOIM
—
IPQIM MCIM IDIM
—
IM1IM IM0IM
0000_0000_0000_0000
R/W
Addr
0x10484
Figure 9-78. Inbound Message Interrupt Mask Register (IMIMR)
Table 9-63 describes IMIMR fields.
Table 9-63. IMIMR Field Descriptions
Bits
Name
Description
31–9
8
—
Reserved, should be cleared.
OFOIM
IPOIM
Outbound free overflow interrupt mask
0 Outbound free overflow interrupt is allowed.
1 Outbound free overflow interrupt is masked.
7
Inbound post overflow interrupt mask
0 Inbound post overflow interrupt is allowed.
1 Inbound post overflow interrupt is masked.
6
5
—
Reserved, should be cleared.
IPQIM
Inbound post queue interrupt mask
0 Inbound post queue interrupt is allowed.
1 Inbound post queue interrupt is masked.
4
3
2
MCIM
IDIM
—
Machine check interrupt mask
0 Machine check interrupt from the inbound doorbell register is allowed.
1 Machine check interrupt is masked.
Inbound doorbell interrupt mask
0 Inbound doorbell interrupt is allowed.
1 Inbound doorbell interrupt is masked.
Reserved, should be cleared.
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Table 9-63. IMIMR Field Descriptions (continued)
Description
Bits
Name
1
IM1IM
IM0IM
Inbound message 1 interrupt mask
0 Inbound doorbell interrupt is allowed.
1 Inbound doorbell interrupt is masked.
0
Inbound message 0 interrupt mask
0 Inbound message 0 interrupt is allowed.
1 Inbound message 0 interrupt is masked.
9.12.3.4.7
Messaging Unit Control Register (MUCR)
This register allows software to enable and setup the size of the inbound and outbound FIFOs. MUCR
should be accessed only from the 60x bus and only in agent mode. Accesses while in host mode or from
the PCI bus have undefined results.
31
16
Field
Reset
R/W
—
0000_0000_0000_0002
R/W
Addr
0x104E6
15
6
5
1
0
Field
Reset
R/W
—
CQS
CQE
0000_0000_0000_0000
R/W
Addr
0x104E4
Figure 9-79. Messaging Unit Control Register (MUCR)
Table 9-64 describes MUCR fields.
Table 9-64. MUCR Field Descriptions
Bits
Name
Access
Description
31–6
—
R
Reserved, should be cleared.
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Table 9-64. MUCR Field Descriptions
Description
Bits
Name
CQS
Access
5–1
RW
Circular queue size. CQS refers to each individual queue, not the total size of all four
queues together.
00001 4K entries (16 Kbytes)
00010 8K entries (32 Kbytes)
00100 16K entries (64 Kbytes)
01000 32K entries (128 Kbytes)
10000 64K entries (256 Kbytes)
All others reserved.
0
CQE
RW
Circular queue enable. When set will allow PCI masters to access the inbound and
outbound queue ports. Writes are ignored and reads will return 0xFFFF_FFFF when
this bit is cleared. Normally, this bit is set only if software has initialized all pointers and
configuration registers.
9.12.3.4.8
Queue Base Address Register (QBAR)
This register specifies the beginning of the circular queue structure in local memory. The following QBAR
should be accessed only from the 60x bus and only in agent mode. Accesses while in host mode or from
the PCI bus have undefined results.
31
20
19
16
Field
Reset
R/W
QBA
0000_0000_0000_0000
—
R/W
Addr
0x104F2
15
0
Field
Reset
R/W
—
0000_0000_0000_0000
R/W
Addr
0x104F0
Figure 9-80. Queue Base Address Register (QBAR)
Table 9-65 describes QBAR fields.
Table 9-65. QBAR Field Descriptions
Bits
Name
Access
Description
31–20
QBA
RW
Queue base address. Base address of circular queue in local memory. It must be
aligned to a 1Mbyte boundary.
19–0
—
R
Reserved, should be cleared.
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9.13 DMA Controller
The PCI bridge’s DMA controller transfers blocks of data independent of the local core or PCI hosts. Data
movement occurs on the PCI and/or 60x bus. The PCI Bridge’s DMA module has four high-speed DMA
channels with an aggregate bandwidth conservatively estimated at 210 Mbytes per second, for 60x to PCI
transfer. The channels share 144 bytes of DMA-dedicated buffer space to facilitate the gathering and
sending of data. Both the local core and PCI masters can initiate a DMA transfer.
Features of the DMA controller include the following:
•
•
•
•
•
•
•
4 channels
Concurrent execution across multiple channels with programmable bandwidth control
All channels are accessible by local core and remote PCI masters.
Unaligned transfer capability
Data chaining and direct mode
Interrupt on completed segment, chain, and error
Supports all transfer combinations between 60x memory and PCI memory: 60x-to-60x,
PCI-to-PCI, 60x-to-PCI, and PCI-to-60x.
Figure 9-81 shows a block diagram of the DMA controller.
DMA0
DMA1
DMA2
DMA3
60x bus
Interface logic
I/O sequencer
PCI bus
Figure 9-81. DMA Controller Block Diagram
9.13.1 DMA Operation
The DMA controller operates in two modes—chaining and direct. In direct mode, the software is
responsible for initializing the source, destination and byte count registers. In chaining mode, the software
first must build a chain of descriptor segments in external memory, residing either on the 60x or PCI bus,
and then initialize the current descriptor address register to point to the first descriptor segment in the
chain. In both modes, setting the start bit in the DMA mode register begins the DMA transfer.
The DMA controller supports unaligned transfers for both the source and destination addresses. It gathers
data beginning at the source address and aligns the data accordingly before sending it to the destination
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address. The DMA controller assumes that the source and destination addresses are valid PCI or 60x
memory addresses.
All 60x memory read operations are cache line reads (32 bytes); the DMA controller selects the
appropriate/valid data bytes within the cache line when loading its internal queue. Writing to 60x memory
depends on the alignment of the destination address and the size of the transfer. The DMA controller writes
a full cache line whenever possible. Misaligned destination addresses result in sub-transfers of less than a
cache line on the initial and final beats of the transfer; intermediate beats transfer full cache lines.
Configuring a DMA channel for a transfer size of less than 8 bytes in address hold mode (DAHE or SAHE
is set; refer to Section 9.13.1.6.1, “DMA Mode Register [0–3] (DMAMRx)”) precludes cache line writes.
PCI memory read operations depend on the PRC (PCI read command) field in the mode register, the
alignment of the source address and the size of the transfer. The DMA controller attempts to read a full
cache line whenever possible. Writing to PCI memory depends on the alignment of the destination address
and the size of the transfer.
9.13.1.1 DMA Direct Mode
In direct mode, the DMA controller does not read a chain of descriptors from memory but instead uses the
current parameters in the DMA registers to start a DMA transfer. The DMA transfer finishes after all the
bytes specified in the byte count register have been transferred or an error condition has occurred. Below
are the initialization steps of a DMA transfer in direct mode.
•
Poll the CB (channel busy) bit in the status register to make sure the DMA channel is idle (refer to
•
Initialize the source, destination and byte count register (refer to Section 9.13.1.6.5, “DMA
•
•
Initialize the CTM (channel transfer mode) bit in the mode register (refer to Section 9.13.1.6.1,
the mode register can also be initialized here if necessary.
First clear then set the CS (channel start) bit in the mode register to start the DMA transfer.
9.13.1.2 DMA Chaining Mode
In chaining mode, the DMA controller loads descriptors from memory prior to a DMA transfer. The DMA
controller begins the transfer according to the descriptor information loaded for each segment. Once the
current segment is finished, the DMA controller reads the next descriptor from memory and begins another
DMA transfer. The process is finished if the current descriptor is the last one in the chain or an error
condition has occurred. Below are the initialization steps of a DMA transfer in chaining mode.
•
Build a chain of descriptor segments in memory. Refer to the Section 9.13.2, “DMA Segment
•
•
•
Poll the CB (channel busy) bit in the status register to make sure the DMA channel is idle.
Initialize the current descriptor address register to point to the first descriptor in the chain.
Initialize the CTM (channel transfer mode) bit in the mode register to indicate chaining mode.
Other control parameters in the mode register can also be initialized here if necessary.
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•
First clear then set the CS (channel start) bit in the mode register to start the DMA transfer.
9.13.1.3 DMA Coherency
The four DMA channels are allocated 4 cache lines (128 bytes) of buffer space in the I/O sequencer module
in addition to 16 bytes of local buffer space. Because no address snooping occurs in these internal queues,
data posted in these queues is not visible to the rest of the system while a DMA transfer is in progress. It
is the responsibility of application software to ensure the coherency of the region being transferred during
the DMA process.
Snooping of the core data cache is selectable during DMA transactions. A snoop bit is provided in the
current descriptor address register and the next descriptor address register which allows software to control
when the cache is snooped. These bits are described in Section 9.13.1.6.3, “DMA Current Descriptor
9.13.1.4 Halt and Error Conditions
DMA transfers are halted either by clearing the CS (channel start) bit in the mode register or when
encountering an error condition. In both cases the application software can one of the following:
•
•
•
Continue the DMA transfer
Reconfigure the DMA for a new transfer
Leave the channel in the halted state
When a DMA channel is halted, its programming model is completely accessible. If the DMA is halted
due to an error condition, the TE (transfer error) bit in the status register must be cleared before the transfer
can be resumed or a new transfer initiated. Note that the TE bit is not cleared automatically by hardware.
NOTE: DMA Operation After Bus Error
After any bus error which occurs in the PowerQUICC II (either 60x or PCI,
not necessarily due to DMA operation), the user must reset the system to
avoid DMA malfunction.
9.13.1.5 DMA Transfer Types
The DMA controller supports all transfers between 60x memory and PCI memory: 60x-to-60x,
PCI-to-PCI, 60x-to-PCI, and PCI-to-60x. All data is temporarily stored in a 144-byte queue prior to
transmission. There are four types of DMA transfers:
•
PCI-memory-to-PCI-memory transfers—The DMA controller begins by reading data from PCI
memory space and storing it in the DMA queue. Once sufficient data is stored in the queue, the
DMA controller begins writing data from the queue to PCI memory space beginning at the
destination address. The process is repeated until there is no more data to transfer or an error
condition has occurred on the PCI bus.
•
PCI-memory-to-60x-memory transfers—The DMA controller initiates reads on the PCI bus and
stores the data in the DMA queue. Once sufficient data is stored in the queue, a 60x memory write
is initiated. The DMA controller stops the transfer either for an error condition on the PCI bus or
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60x bus, or when no data is left to transfer. Reading from PCI memory and writing to 60x memory
can occur concurrently.
•
•
60x-memory-to-PCI-memory transfers—The DMA controller initially fetches data from 60x
memory into the DMA queue. As soon as the first data arrives into the queue, the DMA engine
initiates write transactions to PCI memory. The DMA controller stops the transfer either when
there is an error on the PCI bus or 60x bus, or there is no more data left to transfer. Reading from
60x memory and writing to PCI memory can occur concurrently.
60x-memory-to-60x-memory transfers—The DMA controller begins reading data from 60x
memory and storing it in the DMA queue. Once sufficient data is stored in the queue, the DMA
controller begins writing data to 60x memory space beginning at the destination address. The
process is repeated until there is no more data to transfer or an error condition has occurred while
accessing memory.
9.13.1.6 DMA Registers
Each DMA channel has a set of seven 32-bit registers (mode, status, current descriptor address, next
descriptor address, source address, destination address, and byte count) to support transactions. This
section describes the format of the DMA support registers.
9.13.1.6.1
DMA Mode Register [0–3] (DMAMRx)
The mode register allows software to start the DMA transfer and to control various DMA transfer
characteristics.
31
24
23
21
20
19
18
17
16
Field
Reset
R/W
—
BWC
DM_SEN IRQS
—
DAHTS
0000_0000_0000_0000
R/W
Addr
0x10502 (DMAMR0); 0x10582 (DMAMR1); 0x10602 (DMAMR2); 0x10682 (DMAMR3)
15
14
13
12
11
10
9
8
7
6
4
3
2
1
0
Field
Reset
R/W
SAHTS
DAHE SAHE
PRC
—
EOTIE
—
TEM CTM CC
CS
0000_0000_0000_0000
R/W
Addr
0x10500 (DMAMR0); 0x10580 (DMAMR1); 0x10600 (DMAMR2); 0x10680 (DMAMR3)
Figure 9-82. DMA Mode Register [0–3] (DMAMRx)
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Table 9-66. DMAMRx Field Descriptions
Bits
Name
Description
31–24
23–21
—
Reserved, should be cleared.
BWC
Bandwidth control. This field only applies when multiple channels are executing
transfers concurrently. The field determines how many cache lines a given Channel
is allowed to transfer after it is granted access to the IOS interface and before it
releases the interface to the next channel. This allows the user to prioritize DMA
Channels.
000 1 cache line
001 2 cache lines
010 4 cache lines
011 8 cache lines
100 16 cache lines
20
19
DM_SEN
IRQS
Direct mode snoop enable. When set allows snooping during direct mode DMA
transactions.
Interrupt steer. When set routes all DMA interrupts to PCI bus through INTA. When
clear routes all DMA interrupts to local core.
18
Reserved, should be cleared.
—
17–16
DAHTS
Destination address hold transfer size. Indicates the transfer size used for each
transaction when DAHE is enabled. The Byte Count Register must be in multiples of
the size, and the Destination Address Register must be aligned based on the size.
00 1 byte
01 2 bytes
10 4 bytes
11 8 bytes
15–14
SAHTS
Source address hold transfer size. Indicates the transfer size used for each
transaction when SAHE is enabled. The Byte Count Register must be in multiples of
the size, and the Source Address Register must be aligned based on the size.
00 1 byte
01 2 bytes
10 4 bytes
11 -8 bytes
13
DAHE
Destination address hold enable. When set will allow the DMA controller to hold the
destination address constant for every transfer. The size used for transfer is
indicated by DAHTS. Note that hardware supports only aligned transfers for this
feature.
12
SAHE
PRC
Source address hold enable. When set will allow the DMA controller to hold the
source address constant for every transfer. The size used for the transfer is indicated
by SAHTS. Note that hardware supports only aligned transfers for this feature.
11–10
PCI read command. Indicates the types of PCI read command to use.
00 PCI read
01 PCI read line
10 PCI read multiple
11 Reserved
9–8
—
Reserved, should be cleared.
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Table 9-66. DMAMRx Field Descriptions (continued)
Name Description
Bits
7
EOTIE
End-of-transfer interrupt enable. When set will generate an interrupt at the
completion of a DMA transfer. No EOT interrupt is generated if this bit is cleared. End
of transfer is defined as the end of a direct mode transfer or in chaining mode, as the
end of the transfer of the last segment of a chain.
6–4
3
—
Reserved, should be cleared.
TEM
Transfer error mask. This bit determines the DMA response in the event of a transfer
error. If this bit is set, the DMA will complete the transfer regardless of whether a
transfer error occurs (the TE bit is not set). If this bit is clear, the DMA will halt when
a transfer error occurs (TE bit is set).
2
1
0
CTM
CC
Channel transfer mode
0
Channel continue. When this bit is set, the DMA transfer will restart the transferring
process starting at the Current Descriptor Address. This bit applies only to chaining
mode and is cleared by hardware after every descriptor read.
CS
Channel start. A 0-to-1 transition occurring on this bit when the channel is not busy
(SR[CB] bit is 0) will start the DMA process. If the channel is busy and a 0 to 1
transition occurs, then DMA channel will restart from a previous halt condition. A
1-to-0 transition when the channel is busy (CB bit is 1) will halt the DMA process.
Nothing happens if the channel is not busy and a 1 to 0 transition occurs.
9.13.1.6.2
DMA Status Register [0–3] (DMASRx)
The status register reports various DMA conditions during and after the DMA transfer. Writing a 1 to a
specific set bit clears the bit.
31
16
Field
Reset
R/W
—
0000_0000_0000_0000
R/W
Addr
0x10506(DMASR0); 0x10586 (DMASR1); 0x10606 (DMASR2); 0x10686 (DMASR3)
15
8
7
6
3
2
1
0
Field
Reset
R/W
—
TE
—
CB EOSI EOCDI
0000_0000_0000_0000
R/W
Addr
0x10504 (DMASR0); 0x10584(DMASR1); 0x10604 (DMASR2); 0x10684 (DMASR3)
Figure 9-83. DMA Status Register [0–3] (DMASRx)
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Table 9-67. DMASRx Field Descriptions
Bits
Name
Access
Description
31–8
7
—
RW
Reserved, should be cleared.
TE
Read/ Transfer error. This bit is set when there is an error condition during the DMA transfer
Write 1 and the TEM bit is cleared.
to clear
6–3
2
—
R
Reserved, should be cleared.
CB
Read
Only
Channel busy. When set indicates that a DMA transfer is currently in progress. This
bit will be cleared as a result of any of the three following conditions: (1) an error, (2)
a halt, or (3) completion of the DMA transfer.
1
0
EOSI
Read/ End-of-segment interrupt. After transferring a segment of data, if the EOSIE bit in the
Write 1 current descriptor address register is set, then this bit will be set and an interrupt is
to clear generated. Otherwise, no interrupt is generated.
EOCDI
Read/ End-of-chain/direct Interrupt. When the last DMA transfer is finished, either in
Write 1 chaining or direct mode, if DMAMR[EOTIE] is set, this bit will be set and an interrupt
to clear is generated. Otherwise, no interrupt is generated.
9.13.1.6.3
DMA Current Descriptor Address Register [0–3] (DMACDARx)
The current descriptor address register contains the address of the current segment descriptor being
transferred. In chaining mode, software must initialize this register to point to the first descriptor in the
chain. After processing the first descriptor, the DMA controller moves the contents of the next descriptor
address register into DMACDAR, loads the next descriptor into DMANDAR, and executes the current
transfer. This process continues until encountering a descriptor whose EOTD (end-of-transfer descriptor)
bit is set, which will be the last descriptor to be executed.
31
16
Field
Reset
R/W
CDA
0000_0000_0000_0000
R/W
Addr
0x1050A(DMACDR0); 0x1058A (DMACDR1); 0x1060A (DMACDR2); 0x1068A (DMACDR3)
15
5
4
3
2
0
Field
Reset
R/W
CDA
SNEN EOSIE
—
0000_0000_0000_0000
R/W
Addr
0x10508 (DMACDR0); 0x10588 (DMACDR1); 0x10608 (DMACDR2); 0x10688 (DMACDR3)
Figure 9-84. DMA Current Descriptor Address Register [0–3] (DMACDARx)
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Table 9-68. DMACDARx Field Descriptions
Description
Bits
Name
31–5
CDA
Current descriptor address. Contains the current descriptor address of the segment
descriptor in memory. It must be aligned on an 8-word boundary.
4
3
SNEN
EOSIE
Snoop enable. When set will allow snooping on DMA transactions.
End-of-segment interrupt enable. When set will generate an interrupt if the current DMA
transfer for the current descriptor is finished.
2–0
—
Reserved, should be cleared.
9.13.1.6.4
DMA Source Address Register [0–3] (DMASARx)
The source address register, shown in Figure 9-85, indicates the address where the DMA controller will be
reading data from. This address can be in either PCI memory or 60x memory. The software has to ensure
that this is a valid memory address.
The choice between PCI or 60x is done according to the following rule: If the address hits one of the PCI
outbound windows, then the source data is read from the PCI memory. Otherwise, it is read from the 60x
31
16
Field
Reset
R/W
SA
0000_0000_0000_0000
R/W
Addr
0x10512(DMASAR0); 0x10592 (DMASAR1); 0x10612 (DMASAR2); 0x10692 (DMASAR3)
15
0
Field
Reset
R/W
SA
0000_0000_0000_0000
R/W
Addr
0x10510 (DMASAR0); 0x10590 (DMASAR1); 0x10610 (DMASAR2); 0x10690 (DMASAR3)
Figure 9-85. DMA Source Address Register [0–3] (DMASARx)
Table 9-69. DMASARx Field Descriptions
Description
Source address of DMA transfer. The content is updated after every DMA read operation.
Bit
Name
31–0
SA
9.13.1.6.5
DMA Destination Address Register [0–3] (DMADARx)
The destination address register, shown in Figure 9-86, indicates the address where the DMA controller
will be writing data to. This address can be in either PCI memory or 60x memory. The software has to
ensure that this is a valid memory address.
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The choice between PCI or 60x is done according to the following rule: If the address hits one of the PCI
outbound windows, then the destination data is written to the PCI memory. Otherwise, it is written to the
31
16
Field
Reset
R/W
DA
0000_0000_0000_0000
R/W
Addr
0x1051A (DMAADAR0); 0x1059A (DMAADAR1); 0x1061A (DMAADAR2); 0x1069A (DMAADAR3)
15
0
Field
Reset
R/W
DA
0000_0000_0000_0000
R/W
Addr
0x10518 (DMAADAR0); 0x10598 (DMAADAR1); 0x10618 (DMAADAR2); 0x10698 (DMAADAR3)
Figure 9-86. DMA Destination Address Register [0–3] (DMADARx)
Table 9-70. DMADARx Field Descriptions
Description
Destination address. The content is updated after every DMA write operation.
Bit
Name
31–0
DA
9.13.1.6.6
DMA Byte Count Register [0–3] (DMABCRx)
This register contains the number of bytes per transfer (maximum transfer size is 64 Mbytes).
31
26
25
16
Field
Reset
R/W
—
BC
0000_0000_0000_0000
R/W
Addr
0x10522 (DMABCR0); 0x105A2(DMABCR1); 0x10622 (DMABCR2); 0x106A2 (DMABCR3)
15
0
Field
Reset
R/W
BC
0000_0000_0000_0000
R/W
Addr
0x10520 (DMABCR0); 0x105A0 (DMABCR1); 0x10620 (DMABCR2); 0x106A0 (DMABCR3)
Figure 9-87. DMA Byte Count Register [0–3] (DMABCRx)
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Table 9-71. DMABCRx Field Descriptions
Bit
Name
Description
31–26
25–0
—
Reserved, should be cleared.
BC
Byte count. Contains the number of bytes to transfer. The value in this register is
decremented after each DMA read operation.
9.13.1.6.7
DMA Next Descriptor Address Register [0–3] (DMANDARx)
The next descriptor address register (NDAR) contains the address for the next segment descriptor in the
chain. In chaining mode, this register is loaded from the “next descriptor” field of the descriptor that the
31
16
Field
Reset
R/W
NDA
0000_0000_0000_0000
R/W
Addr
0x10526 (DMANDAR0); 0x105A6 (DMANDAR1); 0x10626 (DMANDAR2); 0x106A6 (DMANDAR3)
15
5
4
3
2
1
0
Field
NDA
NDSNE NDEOSIE
N
—
EOTD
Reset
R/W
0000_0000_0000_0000
R/W
Addr
0x10524 (DMANDAR0); 0x105A4 (DMANDAR1); 0x10624 (DMANDAR2); 0x106A4 (DMANDAR3)
Figure 9-88. DMA Next Descriptor Address Register [0–3] (DMANDARx)
Table 9-72. DMANDARx Field Descriptions
Bit
Name
Description
31–5
NDA
Next descriptor address. Contains the next descriptor address of the segment
descriptor in memory. It must be aligned on an 8-word (32-byte) boundary.
4
3
NDSNEN
NDEOSIE
Next descriptor snoop enable. When set will allow snooping on DMA
transactions.
Next descriptor end-of-segment interrupt enable. When set will generate an
interrupt at the end of this DMA transfer.
2–1
0
—
Reserved, should be cleared.
EOTD
End-of-transfer descriptor. When set indicates that this descriptor is the last one
to be executed.
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PCI Bridge
9.13.2 DMA Segment Descriptors
DMA segment descriptors contain the source and destination addresses of the data segment, the segment
byte count, and a link to the next descriptor. Segment descriptors are built on cache-line (32-byte)
boundaries in either 60x or PCI memory and are linked together into chains using the
next-descriptor-address field.
Table 9-73. DMA Segment Descriptor Fields
Descriptor Field
Description
Source address
Contains the source address of the DMA transfer. After the DMA controller reads the
descriptor from memory, this field will be loaded into the source address register. For the bit
Destination address
Contains the destination address of the DMA transfer. After the DMA controller reads the
descriptor from memory, this field will be loaded into the destination address register. For the
bit definition, refer to Section 9.13.1.6.5, “DMA Destination Address Register [0–3]
Next descriptor address Points to the next descriptor in memory. After the DMA controller reads the descriptor from
memory, this field will be loaded into the next descriptor address register. For the bit definition,
Byte count
Contains the number of bytes to transfer. After the DMA controller reads the descriptor from
memory, this field will be loaded into the byte count register. For the bit definition, refer to
Application software initializes the current descriptor address register (DMACDARx) to point to the first
descriptor in the chain. For each descriptor in the chain, the DMA controller starts a new DMA transfer
with the control parameters specified by the descriptor. The DMA controller traverses the descriptor chain
until reaching the last descriptor (with its EOTD bit set).
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PCI Bridge
Current descriptor address register
31
Local memory or PCI memory
Offset
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
0
Source address
Reserved
Destination address
Reserved
Descriptor 0
Next descriptor
Reserved
Byte count
Reserved
31
31
31
0
0
0
Next descriptor address register
31
Offset
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
0
Source address
Reserved
Destination address
Reserved
Descriptor 1
Next descriptor
Reserved
Byte count
Reserved
Offset
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
Source address
Reserved
Descriptor N
(last)
Destination address
Reserved
Next descriptor
Reserved
EOTD=1
Byte count
Reserved
Figure 9-89. DMA Chain of Segment Descriptors
9.13.2.1 Descriptor in Big Endian Mode
In big endian mode, the descriptor in 60x memory should be programmed such that data appears in
ascending significant-byte order. If segment descriptors are written to memory located in the 60x bus, they
should be treated like they are translated from big endian to little endian mode.
Example: Big Endian mode descriptor’s data structure. Note that the descriptor structure must be aligned
on an 8-word boundary.
struct {
double a;
double b;
double c;
double d;
/* 0x1122334455667788 double word
/* 0x55667788aabbccdd double word
/* 0x8765432101234567 double word */
/* 0x0123456789abcdef double word */
*/
*/
} Descriptor;
Results: Source Address = 0x44332211 <MSB..LSB>
Destination Address = 0x88776655 <MSB..LSB>
Next Descriptor Address = 0x21436587 <MSB..LSB>
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Byte Count = 0x67452301 <MSB..LSB>
9.13.2.2 Descriptor in Little Endian Mode
In little endian mode, the descriptor in PCI memory should be programmed such that data appears in
descending significant byte order. If segment descriptors are written to memory located in the PCI bus,
they are obeying the rules for little endian mode.
Example: Little Endian mode descriptor’s data structure. Note that the descriptor structure must be
aligned on an 8-word boundary.
struct {
double a;
double b;
double c;
double d;
/* 0x8877665544332211 double word
/* 0x1122334488776655 double word
/* 0x7654321012345678 double word */
/* 0x0123456776543210 double word */
*/
*/
} Descriptor;
Results: Source Address = 0x44332211 <MSB..LSB>
Destination Address = 0x88776655 <MSB..LSB>
Next Descriptor Address = 0x12345678 <MSB..LSB>
Byte Count = 0x76543210 <MSB..LSB>
9.14 Error Handling
The PCI bridge provides error detection and reporting. This section describes how the PCI bridge handles
different error (or interrupt) conditions.
Errors detected by the PCI bridge are reported by asserting internal error signals for each detected error.
The system error (SERR) and parity error (PERR) signals are used to report errors on the PCI bus.
The PCI command and status registers and the error handling registers enable or disable the reporting and
detection of specific errors. There are six registers which define capture and control functionality under
The PCI bridge detects illegal transfer sizes to its configuration registers, PCI master-abort cycles, PCI
received target-abort errors, PCI parity errors, and overflow/underflow errors in the message unit.The PCI
bridge latches the address and type of transaction that caused the error in the error registers to assist
diagnostic and error handling software.
9.14.1 Interrupt and Error Signals
Although Section 9.11, “Configuration Registers,” contains the definitions for the interrupt and error
signals, this section describes the interactions between system components when an interrupt or error
signal is asserted.
9.14.1.1 PCI Bus Error Signals
The PCI bridge uses two error signals to interact with the PCI bus, SERR and PERR.
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9.14.1.1.1
System Error (SERR)
The SERR signal is used to report PCI address parity errors. It is driven for a single PCI clock cycle by the
agent that is reporting the error. The agent responsible for driving AD[31–0] on a given PCI bus phase is
responsible for driving even parity one PCI clock later on the PAR signal. (That is, the number of 1’s on
AD[31–0], PCI_C/BE[3–0], and PAR equals an even number.) The target agent is not allowed to terminate
with retry or disconnect if SERR is activated due to an address parity error.
Bits 8 and 6 of the PCI command register controls whether the PCI bridge asserts SERR upon detecting
one of the error conditions.
9.14.1.1.2
Parity Error (PERR)
The PERR signal is used to report PCI data parity errors during all PCI transactions, except for a PCI
special-cycle command. The agent responsible for driving AD[31–0] on a given PCI bus phase is
responsible for driving even parity one PCI clock later on the PAR signal. That is, the number of 1’s on
AD[31–0], PCI_C/BE[3–0], and PAR equals an even number.
The PERR signal must be asserted by the agent receiving data two PCI clocks following the data phase for
which a data parity error was detected. Only the master may report a read data parity error and only the
selected target may report a write data parity error.
Bit 6 of the PCI command register controls whether the PCI bridge ignores PERR.
9.14.1.1.3
Error Reporting
The error signals generated by the PCI bridge indicate which specific error has been detected.
The error control and address registers and the data capture registers are used to provide additional
information about the detected error. When an error is detected, the associated information is latched inside
these registers until all the associated error flags are cleared. Subsequent errors will set the appropriate
error flags in the error detection registers, but will not latch additional information.
9.14.1.2 Illegal Register Access Error
An illegal register access error occurs when an access to a configuration register is not specified to be 1
beat. When this occurs, ESR[IRA] is set (refer to Section 9.11.1.9, “Error Status Register (ESR)”). If a read
transaction causes the illegal access error the PCI bridge returns 0xFF (all 1s) and a write transaction with
an illegal register access error will be dropped.
9.14.1.3 PCI Interface
The PCI bridge supports the error detection and reporting mechanism as specified in the PCI Local Bus
Specification, Revision 2.2. The PCI bridge detects master and target abort errors, address parity errors,
received SERR, and master and target PERR errors. In these cases, the appropriate bit is set in the ESR,
and the address, data and control information about the transaction is loaded in the PCI error address
capture register (PCI_EACR), the PCI data capture register (PCI_EDCR) and the PCI error control capture
register.
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9.14.1.3.1
Address Parity Error
If the PCI bridge is acting as a PCI master and the target detects and reports (by asserting SERR) a PCI
address parity error, the PCI bridge sets bit 5 of the ESR and sets the detected parity error bit (bit 15) in
the PCI status register. This setting of bit 15 is independent of the settings in the PCI command register.
If the PCI bridge is acting as a PCI target and detects a PCI address parity error, the PCI interface of the
PCI bridge sets the status bit in the PCI status register (bit 15) and bit 0 of the ESR. If bits 6 and 8 of the
PCI command register are set, the PCI bridge reports the address parity error by asserting SERR to the
master (two clocks after the address phase) and sets bit 14 of the PCI status register.
9.14.1.3.2
Data Parity Error
If the PCI bridge is acting as a PCI master and a write data parity error is signaled by the target asserting
PERR, the PCI bridge sets bit 8 of the PCI status register if the parity error response bit (bit 6) in the PCI
command Register is set. The PCI bridge sets bit 7 of the error status register (refer to Section 9.11.1.9,
“Error Status Register (ESR)”), regardless of the configuration of the PCI command register.
If the PCI bridge is acting as a PCI master and a read data parity error occurs, the PCI bridge sets bit 8 of
the PCI status register if the parity error response bit (bit 6) in the PCI command register is set. The PCI
bridge sets bit 2 of the error status register. If the PCI command register of the PCI bridge is programmed
to respond to parity errors (bit 6 of the PCI command register is set) the PCI bridge reports the error to the
PCI target by asserting PERR and tries to complete the command if possible. The PCI bridge also sets bit
15 of the PCI status register regardless of the value of the parity error response bit (bit 6) in the PCI
command register.
If the PCI bridge is acting as a PCI target when the write data parity error occurs, the PCI bridge sets bit
15 of the PCI status register and bit 1 of the error status register (ESR). The setting of these bits is
independent of the settings in the PCI command register. If bit 6 of the PCI command Register is set, the
PCI bridge asserts PERR. When the data has all been transferred, the PCI bridge completes the operation
but ignores the data.
If the PCI bridge is acting as a PCI target when the master asserts PERR, the PCI bridge sets bit 6 of ESR
(refer to Section 9.11.1.9, “Error Status Register (ESR)”), regardless of the configuration of the PCI
command register.
9.14.1.3.3
Master-Abort Transaction Termination
If the PCI bridge, acting as a master, initiates a PCI bus transaction (excluding special-cycle transactions)
but there is no response from any PCI agent (DEVSEL has not been asserted within five PCI bus clocks
from the start of the address phase), the PCI bridge terminates the transaction with a master-abort and sets
the master-abort flag (bit 13) in the PCI status register and bit 3 in the ESR.
In the case of no response for a PCI read configuration transaction, the PCI bridge terminates the
transaction with a master-abort, but will return data of all ones and will not assert a machine check. This
kind of termination enables the host CPU to perform a PCI device scan without having to know in advance
if a particular PCI slot is populated or empty. The software still needs to mask the PCI_NO_RSP bit in the
transaction that is terminated with a master-abort results in a machine check interrupt.
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PCI Bridge
9.14.1.3.4
Target-Abort Error
If a PCI transaction initiated by the PCI bridge is terminated by target-abort, the PCI bridge sets the
received target-abort flag (bit 12) of the PCI status register and bit 4 of the error status register (refer to
Section 9.11.1.9, “Error Status Register (ESR)”). Note that data transferred in a target-aborted transaction
may be corrupt.
9.14.1.3.5
NMI
This signal is captured in bit 11 of the ESR (refer to Section 9.11.1.9, “Error Status Register (ESR)”). It
indicates that an error has occurred on the 60x bus in a transaction that was originally initiated by the PCI
bridge.
9.14.1.4 Embedded Utilities
Embedded utilities errors are errors detected in the I O interface. Embedded utilities errors are limited to
2
queue overflows in the I O outbound free queue and the inbound post queue.
2
9.14.1.4.1
Outbound Free Queue Overflow
If the PCI bridge detects an I O outbound free queue overflow, it sets bit 8 of the error status register (refer
2
2
9.14.1.4.2
Inbound Post Queue Overflow
If the PCI bridge detects an I O inbound post queue overflow, it sets bit 9 of the error status register (refer
2
2
9.14.1.4.3
Inbound DoorBell Machine Check
If an external PCI master writes the inbound doorbell register such that the most significant bit is set, then
bit 12 of ESR (refer to Section 9.11.1.9, “Error Status Register (ESR)”) is set and a machine check is
asserted to the local processor.
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Chapter 10
Clocks and Power Control
The PowerQUICC II’s clocking architecture includes two PLLs—the main PLL and the core PLL.
The clock block, which contains the main PLL, provides the following:
•
•
•
Internal clocks for all blocks in the chip except core blocks
Internal 60x bus clock in the chip
PCI clock (MPC8250, MPC8265, and MPC8266 only)
The core input clock has the 60x bus frequency, which the core PLL multiplies by a configurable factor
and provides to all core blocks.
During the power-up reset, the configuration of bus, core, PCI, and CPM clock frequencies is determined
by seven bits—three hardware configuration pins (MODCK[1–3]) and four bits from hardware
configuration word[28–31] (MODCK_H). Both the PLLs and the dividers are set according to the selected
clock configuration.
The CLOCKIN signal is the main timing reference for the PowerQUICC II. The CLOCKIN frequency is
equal to the 60x and local bus frequencies. The main PLL can multiply the frequency of the input clock to
the final CPM frequency.
10.1 Clock Unit
The PowerQUICC II’s clock module consists of the input clock interface (OSCM), the PLL, the system
frequency dividers, the clock generator/driver blocks, the configuration control unit, and the clock control
block. The clock module and the configuration control unit are managed through the system clock mode
register (SCMR), the configuration bits MODCK[1–7], and reset block.
To improve noise immunity, the charge pump and the VCO of the main PLL have their own set of power
supply pins (VCCSYN and GNDSYN). All other circuits are powered by the normal supply pins, VDD
and VSS.
10.2 Clock Configuration
To configure the main PLL multiplication factor and the core, CPM, and 60x bus frequencies, the
MODCK[1–3] pins are sampled while HRESET is asserted. Refer to the relevant hardware specifications
document for a complete list of possible clock configurations.
10.3 External Clock Inputs
The input clock source to the PLL is an external clock oscillator at the bus frequency. The PLL skew
elimination between the CLOCKIN pin and the internal bus clock is guaranteed.
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Clocks and Power Control
10.4 Main PLL
The main PLL performs frequency multiplication and skew elimination. It allows the processor to operate
at a high internal clock frequency using a low-frequency clock input, which has two immediate benefits:
A lower clock input frequency reduces overall electromagnetic interference generated by the system, and
oscillating at different frequencies eliminates the need for another oscillator to the system.
10.4.1 PLL Block Diagram
Figure 10-1 shows how clocking is implemented and the interdependencies of the SCMR and SCCR
fields:
•
•
•
BUSDF—60x bus division factor
CPMDF—CPM division factor. This value is always 1.
PLLDF—PLL pre-divider factor. Ensures that PLLMF is an integer value regardless of whether
CPM_CLK/CLKIN is an integer.
•
•
PLLMF—PLL multiplication factor
DFBRG—Division factor for the BRGCLK
VCO_OUT
(2*CPM_CLK)
CLKIN
CPM_CLK
÷ (CPMDF + 1)
(÷2)
÷ (PLLDF + 1)
X 2(PLLMF + 1)
CPM_CLK_90°
PLLDF ensures that PLLMF is an integer,
according to the following formula:
BUS_CLK (= CLKIN)
BUS_CLK_90°
÷ (BUSDF + 1)
CPM_CLK
PLLMF =
× (PLLDF + 1) – 1
CLKIN
General-Purpose Divider
÷ 4
SCC_CLK
SCC_CLK_90°
22 (DFBRG + 1)
BRG_CLK
Figure 10-1. System PLL Block Diagram
The reference signal (CLKIN) goes to the phase comparator that controls the direction (up or down) that
the charge pump drives the voltage across the external filter capacitor (XFC). The direction selected
depends on whether the feedback signal phase lags or leads the reference signal. The output of the charge
pump drives the VCO whose output frequency is divided and fed back to the phase comparator for
comparison with the reference signal, CLKIN. Ranging between 1 and 4,096, the PLL multiplication
factor is held in the system clock mode register (SCMR[PLLMF]). Also, when the PLL is operating, its
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Clocks and Power Control
output frequency is twice the CPM frequency. This double frequency is required to generate the
On initial system power-up, power-on reset (PORESET) should be asserted by external logic for 16 input
clocks after a valid level is reached on the power supply. Whenever power-on reset is asserted,
SCMR[PLLMF, PLLDF] are programmed by the configuration pins. This value then drives the clock
block to generate the correct CPM and bus frequencies.
10.4.2 Skew Elimination
The PLL can tighten synchronous timings by eliminating skew between phases of the internal clock and
the external clock entering the chip (CLOCKIN). Skew elimination is always active when the PLL is
enabled. Disabling the PLL can greatly increase clock skew.
10.4.3 PCI Bridge Clocking
NOTE
This section applies only to the MPC8250, the MPC8265, and the
MPC8266.
The PCI bridge uses a PLL and a DLL for clocking. The PLL is used for generating a high speed clock
(from CLKIN1) for the chip’s logic blocks, and the DLL is used for de-skewing the output reference clock.
The PCI bridge can be run from a PCI clock input when operating as a PCI agent, or it can generate the
PCI clock when operating as a host.
Note that when the PowerQUICC II operates in PCI mode the MODCK_H bits take their values from four
dedicated pins—PCI_MODCK_H[0–3].
10.4.3.1 PCI Bridge as an Agent Operating from the PCI System Clock
If the PowerQUICC II is connected to a system which generates the PCI clock, the PCI clock should be
fed to the CLKIN1 pin. The PCI clock is internally multiplied by the PLL to generate the chip’s internal
high speed clock. This clock is used to generate the 60x bus clock. The 60x bus clock is then driven by a
DLL circuit to the DLLOUT pin, which has a feedback path from the board to the CLKIN2 pin. This
feedback clock signal is used by the DLL logic to minimize clock skew between the internal and external
clocks.
NOTE
All PCI timings are measured relative to CLKIN1; all 60x bus timings are
measured relative to CLKIN2.
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10-3
Clocks and Power Control
PowerQUICC II
cpm_clk
PCI Interface
pci_clk
%
Divider
%
bus_clk
PCI Circuit
dllout
60x Circuit
PLL
DLL
bus_clk
clkin2
clkin1
PCI Clock
Bus Clock
Figure 10-2. PCI Bridge as an Agent, Operating from the PCI System Clock
10.4.3.2 PCI Bridge as a Host and Generating the PCI System Clock
In a system where the PowerQUICC II is the host that generates the PCI clock, the 60x bus clock should
be driven to the CLKIN1 pin. The 60x bus clock is internally multiplied by the PLL to generate the CPM
high speed clock and then internally divided for generating the PCI bus clock. The PCI bus clock is then
driven by the DLL circuit to the DLLOUT pin, which has a feedback path from the board to the CLKIN2
pin. This feedback is used to control the clock skew in order to have the same internal and external clock
timing.
NOTE
All PCI timings are measured relative to CLKIN2, and all 60x bus timings
are measured relative to CLKIN1.
PowerQUICC II
cpm_clk
PCI Interface
pci_clk
%
Divider
%
bus_clk
60x Circuit
dllout
PCI Circuit
PLL
DLL
pci_clk
clkin2
clkin1
60x Bus Clock
PCI Clock
Figure 10-3. PCI Bridge as a Host, Generating the PCI System Clock
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Clocks and Power Control
NOTE
If a clock buffer is used in the feedback path from DLLOUT to CLKIN2,
designers should ensure that the clock buffer does not include an internal
PLL as this may cause an unacceptable jitter on the clock signals.
10.4.3.2.1
CPM CLOCK and PCI Frequency Equations
The relation between CPM CLOCK frequency and PCI frequency is as follows.
If the PowerQUICC II is configured as a PCI agent device, and PCIDF = 9:
CPM/PCI = (PCIDF + 1) / 2
Otherwise:
CPM/PCI = (PCI_MODCK + 1) x (PCIDF + 1) / 2
10.5 Clock Dividers
The PLL output is twice the maximum frequency needed for all the clocks. The PLL output is sent to
general-purpose dividers (CPMDF, BUSDF), either of which can divide the double clock by a
programmable number between 1 and 16. The delay is the same for all dividers independent on the
programmable number, so the clocks are synchronized.
The output of each divider has two phases, one shifted 90° from the other. Each phase has a 50% duty
cycle.
10.6 PowerQUICC II Internal Clock Signals
The internal logic of the PowerQUICC II uses the following internal clock lines:
•
•
•
•
•
CPM general system clocks (CPM_CLK, CPM_CLK_90)
60x bus, core bus (BUS_CLK, BUS_CLK_90)
SCC clocks (SCC_CLK, SCC_CLK_90)
Baud-rate generator clock (BRG_CLK)
PCI clock (PCI_CLK) (MPC8250, MPC8265, and MPC8266 only)
The PLL synchronizes these signals to each other (but does not synchronize to BRG_CLK).
10.6.1 General System Clocks
The general system clocks (CPM_CLK, CPM_CLK_90) are the basic clocks supplied to most modules
and sub-modules on the CPM. The following points should be kept in mind:
•
•
•
BUS_CLK and BUS_CLK_90 are supplied to the 60x bus and to the core.
Many modules use both clocks (SIU, serials)
The external clock, CLKIN, is the same as BUS_CLK
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Clocks and Power Control
10.7 PLL Pins
Table 10-1 shows dedicated PLL pins.
Table 10-1. Dedicated PLL Pins
Signal
Description
VCCSYN Drain voltage—Analog VDD dedicated to core analog PLL circuits. To ensure core clock stability, filter the
1
power to the VCCSYN1 input with a circuit similar to the one in Figure 10-4. To filter as much noise as
possible, place the circuit as close as possible to VCCSYN1. The 0.1-µF capacitor should be closest to
VCCSYN1, followed by the 10-µF capacitor, and finally the 10-Ω resistor to Vdd. These traces should be
kept short and direct.
VCCSYN Drain voltage—Analog VDD dedicated to analog main PLL circuits. To ensure internal clock stability, filter
the power to the VCCSYN input with a circuit similar to the one in Figure 10-4. To filter as much noise as
possible, place the circuit should as close as possible to VCCSYN. The 0.1-µF capacitor should be closest
to VCCSYN, followed by the 10-µF capacitor, and finally the 10-Ω resistor to Vdd. These traces should be
kept short and direct.
GNDSYN Source voltage—Analog VSS dedicated to analog main PLL circuits. Should be provided with an
extremely low impedance path to ground and should be bypassed to VCCSYN by a 0.1-µF capacitor
located as close as possible to the chip package. The user should also bypass GNDSYN to VCCSYN with
a 0.01-µF capacitor as close as possible to the chip package.
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Clocks and Power Control
Table 10-1. Dedicated PLL Pins (continued)
Description
Signal
XFC
External filter capacitor—Connects to the off-chip capacitor for the main PLL filter. One terminal of the
capacitor is connected to XFC while the other terminal is connected to VCCSYN. 30 MΩ is the minimum
parasitic resistance value that ensures proper PLL operation when connected in parallel with the XFC
capacitor. A multiplication factor (MF) based on CPM_CLK/CLKIN determines the XFC capacitor value
according to the following tables:
Definition of Multiplication Factor (MF)
If the ratio of CPM_CLK/CLKIN is an integer (A), MF = A. If CPM_CLK/CLKIN is A.5, MF = 2 x A.5. For
example, if CPM_CLK/CLKIN is 166.66 MHz/ 66.66 MHz = 2.5, then MF = 5. The relevant factors are as
follows:
CPM_CLK/CLKIN = 2
CPM_CLK/CLKIN = 2.5 MF = 5
CPM_CLK/CLKIN = 3 MF = 3
CPM_CLK/CLKIN = 3.5 MF = 7
MF = 2
CPM_CLK/CLKIN = 4
CPM_CLK/CLKIN = 5
CPM_CLK/CLKIN = 6
MF = 4
MF = 5
MF = 6
.29µm (HiP3) Silicon: Rev. A.1 and B.x
Multiplication Factor Maximum Allowed Capacitance Minimum Allowed Capacitance Unit
MF ≤ 4
MF x 840 - 90
MF x 1220
MF x 750 - 90
MF x 1100
pF
pF
MF > 4
.29µm (HiP3) Silicon: Rev. C.2 and Future Revisions
Maximum Allowed Capacitance Minimum Allowed Capacitance Unit
MF x 840 - 90 MF x 750 - 90 pF
.25µm (HiP4) Silicon
Maximum Allowed Capacitance Minimum Allowed Capacitance Unit
MF x 780 - 140 MF x 580 -100 pF
Recommended
Capacitance
MF x 680 - 120
VDD
VCCSYN
10 Ω
10 µF
0.1 µF
Figure 10-4. PLL Filtering Circuit
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Clocks and Power Control
10.8 System Clock Control Register (SCCR)
PowerQUICC II’s internal space.
0
15
Field
Reset
R/W
—
—
R/W
Addr
0x0x10C80
16
22
23
24
25
28
29
30
31
1
1
1
Field
—
—
CLPD
DFBRG
01
PCIDF
PCI_MODE PCI_MODCK
Reset
0
0
—
—
R/W
R/W
R
R/W
Addr
0x10C82
Figure 10-5. System Clock Control Register (SCCR)
MPC8250, MPC8265, and MPC8266 only.
1
Table 10-2 describes SCCR fields.
Table 10-2. SCCR Field Descriptions
Defaults
Bits
Name
Description
POR
Hard Reset
0–22
23
—
0
Unaffected
Unaffected
Reserved
1
PCI_MODE
PCI_Mode
PCI Mode
0 Disabled
1 Enabled
Reflects the inverted value of the PCI_Mode pin.
24
PCI_MODCK PCI_MODC Unaffected
Reflects the value of the PCI_MODCK pin.
1
K
1
25–28 PCIDF
Configuratio Unaffected
n pins
PCI division factor.
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Freescale Semiconductor
Clocks and Power Control
Table 10-2. SCCR Field Descriptions (continued)
Defaults
Bits
Name
Description
POR
Hard Reset
29
CLPD
0
Unaffected
CPM low power disable.
0 Default. CPM does not enter low power mode when the core
enters low power mode.
1 CPM and SIU enter low power mode when the core does. This
may be useful for debug tools that use the assertion of QREQ
as an indication of breakpoint in the core.
Note: When the core is disabled, CLPD must be cleared.
30–31 DFBRG
01
Unaffected
Division factor of BRG_CLK relative to VCO_OUT (which is twice
the CPM clock). Defines the BRG_CLK frequency as shown in
Figure 10-1. Changing the value does not result in a loss of lock
condition.
00 Divide by 4
01 Divide by 16 (normal operation)
10 Divide by 64
11 Divide by 256
1
MPC8250, MPC8265, and MPC8266 only.
10.9 System Clock Mode Register (SCMR)
The system clock mode register (SCMR), shown in Figure 10-6, holds the parameters which determine the
0
2
3
7
8
11
12
15
Field
—
CORECNF
BUSDF
CPMDF
Reset
R/W
R
Addr
0x10C88
16
18
19
20
31
Field
—
PLLDF
PLLMF
Reset
R/W
R
Addr
0x10C8A
Figure 10-6. System Clock Mode Register (SCMR)
Table 10-3 describes SCMR fields. Also, refer to Figure 10-1 to see these fields in the system PLL block
diagram.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
10-9
Clocks and Power Control
Table 10-3. SCMR Field Descriptions
Defaults
Bits
Name
Description
POR
Hard Reset
0–2
3–7
—
—
—
Reserved
CORECNF Config pins Unaffected Core configuration. PLL configuration of the core. These values are
8–11
12–15
16–18
19
BUSDF
CPMDF
—
Config pins Unaffected 60x bus division factor
Config pins Unaffected CPM division factor. This value is always 1.
—
—
Reserved
PLLDF
Config pins Unaffected PLL pre-divider factor. Ensures that PLLMF is an integer value
regardless of whether the ratio CPM_CLK/CLKIN is an integer.
0 CPM_CLK/CLKIN is an integer. (The PLL division factor is 1.)
1 CPM_CLK/CLKIN is not an integer. (The PLL division factor is 2.)
20–31
PLLMF
Config pins Unaffected PLL multiplication factor. (A PLLMF value of 0x000 corresponds to 1,
and 0xFFF to 4,096.) The VCO output is divided to generate the
feedback signal that goes to the phase comparator. PLLMF and
PLLDF bits control the value of the divider in the PLL feedback loop.
The phase comparator determines the phase shift between the
feedback signal and the reference clock. This difference causes an
increase or decrease in the VCO output frequency.
CPM_CLK
CLKIN
PLLMF =
BUSDF =
× (PLLDF + 1) – 1
(PLLMF + 1) × 2
– 1
(PLLDF + 1)
Figure 10-7. Relationships of SCMR Parameters
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Freescale Semiconductor
Clocks and Power Control
Table 10-4. 60x Bus-to-Core Frequency
SCMR[CORECNF]
Bus-to-Core Multiplier
VCO Divider
0x02
1x
8
4
8
4
4
2
4
2
4
2
2
2
2
2
2
2
2
2
2
2
0x01
1x
0x0C
1.5x
0x00
1.5x
0x05, 0x15
0x04
2x
2x
0x11
2.5x
0x06
2.5x
0x10
3x
0x08
3x
0x0E,0x1E
0x0A, 0x1A
0x07, 0x17
0x0B, 0x1B
0x09, 0x19
0x0D, 0x1D
0x12,
3.5x
4x
4.5x
5x
5.5x
6x
6.5x
0x14
7x
0x16
7.5x
8x
0x1C
0x03, 0x13
PLL off/bypassed
• PLL off
• SYSCLK clocks core directly
• 1x bus-to-core defaulted
0x0F, 0x1F
PLL off
• PLL off
• no core clocking occurs
10.10 Basic Power Structure
The I/O buffers, logic, and clock block are fed by a 3.3-V power supply that allows them to function in a
TTL-compatible voltage range. Internal logic can be fed by a lower voltage source; this considerably
reduces power consumption. The PLL is fed by a separate power supply (VCCSYN) to achieve a highly
stable output frequency. The VCCSYN value is equal to the internal supply. For more information, refer
to Section 1.2, “Electrical and Thermal Characteristics,” in the hardware specifications document
available at wwww.freescale.com.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
10-11
Clocks and Power Control
The PowerQUICC II supports the two following power modes:
•
•
Full mode—Both the chip PLL and core PLL work.
Stop mode—Main PLL is working, core PLL is stopped, and internal clocks are disabled.
— When stop mode is entered, software sets the sleep bit in the core (HID0[10] = 1) and the clock
block freezes all clocks to the chip (the core clock and all other clocks) the main PLL remains
active.
— When stop mode is exited, the SRESET input must be asserted to the chip, the clock block
resumes clocks to all blocks and then releases the reset to the whole chip.
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Freescale Semiconductor
Chapter 11
Memory Controller
The memory controller is responsible for controlling a maximum of twelve memory banks sharing a high
performance SDRAM machine, a general-purpose chip-select machine (GPCM), and three
user-programmable machines (UPMs). It supports a glueless interface to synchronous DRAM (SDRAM),
SRAM, EPROM, flash EPROM, burstable RAM, regular DRAM devices, extended data output DRAM
devices, and other peripherals. This flexible memory controller allows the implementation of memory
systems with very specific timing requirements.
•
The SDRAM machine provides an interface to synchronous DRAMs, using SDRAM pipelining,
bank interleaving, and back-to-back page mode to achieve the highest performance.
•
The GPCM provides interfacing for simpler, lower-performance memory resources and
memory-mapped devices. The GPCM has inherently lower performance because it does not
support bursting. For this reason, GPCM-controlled banks are used primarily for boot-loading and
access to low-performance memory-mapped peripherals.
•
The UPM supports address multiplexing of the external bus, refresh timers, and generation of
programmable control signals for row address and column address strobes to allow for a glueless
interface to DRAMs, burstable SRAMs, and almost any other kind of peripheral. The refresh
timers allow refresh cycles to be initiated. The UPM can be used to generate different timing
patterns for the control signals that govern a memory device. These patterns define how the
external control signals behave during a read, write, burst-read, or burst- write access request.
Refresh timers are also available to periodically generate user-defined refresh cycles.
Unless stated otherwise, this chapter describes the 60x bus memory controller. The local bus memory
controller provides the same functionality as the 60x bus memory controller except 64-bit port size, ECC,
and external master support.
The PowerQUICC II supports the following new features as compared to the MPC860 and MPC850.
•
The synchronous DRAM machine enables back-to-back memory read or write operations using
page mode, pipelined operation and bank interleaving for high-performance systems.
•
The memory controller supports the local bus and the 60x bus in parallel. The 60x bus and the local
bus share twelve memory banks as well as two SDRAM machines, three user-programmable
machines (UPMs) and GPCMs.
•
•
•
•
•
The memory controller supports atomic operation.
The memory controller supports read-modify-write (RMW) data parity check.
The memory controller supports ECC data check and correction.
Two data buffer controls (one for the local bus).
ECC/parity byte select pin, which enables a fast, glueless connection to ECC/RMW-parity devices.
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Freescale Semiconductor
11-1
Memory Controller
•
18-bit address and 32-bit local data bus memory controller. The local bus memory controller
supports the following:
— 8-, 16-, and 32-bit port sizes
— Parity checking and generation
— Ability to work in parallel with the 60x bus memory controller
•
•
Flexible chip-select assignment—The 60x bus and local bus share twelve chip-select lines
(controlled by a memory controller bank). The user can allocate the twelve banks as needed
between the 60x bus and the local bus.
Flexible UPM assignment—The user can assign any of the three UPMs to the 60x bus or the Local
bus
Figure 11-1 shows the dual-bus architecture.
PowerQUICC II
External
Master
CPM/PCI
Core
A[0–31]
D[0–63]
60x Address [0–31]
60x Data[0–63]
60x Address
Bus Interface
60x Data
Bus Interface
60x Memory
Control Signals
SDRAM
60x
60x
Memory
Devices
Memory
Controller
GPCM
60x
Slave
60x-to-Local
Transactions
3 UPM
Arrays
CS[0–11]
Local
Slave
Local
Memory
Controller
Local
Memory
Devices
GPCM
Local Memory
Control Signals
CPM/Local
Master
SDRAM
Local Address
Bus Interface
LA[14–31]
LD[0–31]
Local Address [0–31]
Local Data [0–63]
Local Data
Bus Interface
Figure 11-1. Dual-Bus Architecture
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Freescale Semiconductor
Memory Controller
11.1 Features
The memory controller’s main features are as follows:
•
Twelve memory banks
— 32-bit address decoding with mask
— Variable block sizes (32 Kbytes to 4 Gbytes)
— Three types of data errors check/correction:
– Normal odd/even parity
– Read-modify-write (RMW) odd/even parity for single accesses
– ECC
— Write-protection capability
— Control signal generation machine selection on a per-bank basis
— Flexible chip-select assignment between the 60x bus and the local bus
— Supports internal or external masters on the 60x bus
— Data buffer controls activated on a per-bank basis
— Atomic operation
— Extensive external memory-controller/bus-slave support
— ECC/parity byte-select
— Data pipeline to reduce data setup time for synchronous devices
Synchronous DRAM machine (60x or local bus)
•
•
— Provides the control functions and signals for glueless connection to JEDEC-compliant
SDRAM devices
— Back-to-back page mode for consecutive, back-to-back accesses
— Supports 2-, 4- and 8-way bank interleaving
— Supports SDRAM port size of 64-bit (60x only), 32-bit, 16-bit and 8-bit
— Supports external address and/or command lines buffering
General-purpose chip-select machine (GPCM)—60x or local bus
— Compatible with SRAM, EPROM, FEPROM, and peripherals
— Global (boot) chip-select available at system reset
— Boot chip-select support for 8-, 16-, 32-, and 64-bit devices
— Minimum two clock accesses to external device
— Eight byte write enable signals (WE)—four on the local bus
— Output enable signal (OE)
— External access termination signal (GTA)
•
Three UPMs
— Each machine can be assigned to the 60x or local bus.
— Programmable-array-based machine controls external signal timing with a granularity of up to
one quarter of an external bus clock period
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11-3
Memory Controller
— User-specified control-signal patterns run when an internal or external master requests a
single-beat or burst read or write access.
— UPM refresh timer runs a user-specified control signal pattern to support refresh
— User-specified control-signal patterns can be initiated by software
— Each UPM can be defined to support DRAM devices with depths of 64, 128, 256, and 512
Kbytes, and 1, 2, 4, 8, 16, 32, 64, 128, and 256 Mbytes
– Chip-select line
– Byte-select lines
– Six external general-purpose lines
— Supports 8-, 16-, 32-, and 64-bit memory port sizes, 8-, 16-, and 32-bit port sizes on the local
bus
— Page mode support for successive transfers within a burst
— Internal address multiplexing for all on-chip bus masters supporting 64-, 128-, 256-, and
512-Kbyte, and 1-, 2-, 4-, 8-, 16-, 32-, 64-, 128-, 256-Mbyte page banks
11.2 Basic Architecture
The memory controller consists of three basic machines:
•
•
•
Synchronous DRAM machine
General-purpose chip-select machine (GPCM)
Three UPMs
Addresses are decoded by comparing (A[0–16] bit-wise and ORx[AM]) with BRx[BA]. If an address
match occurs in multiple banks, the lowest numbered bank has priority. However, if a 60x bus access hits
a bank allocated to the local bus, the access is transferred to the local bus. Local bus access hits to 60x
assigned banks are ignored.
When a memory address matches BRx[BA], the corresponding machine takes ownership of the external
signals that control access and maintains control until the cycle ends.
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Freescale Semiconductor
Memory Controller
MxMR[BS]
Bank 0
Bank 1
Bank 2
Bank 3
MS
MS
MS
MS
60x
User-Programmable
Machine (A/B/C)
Local
60x
60x SDRAM
Machine
Local SDRAM
Machine
Local
60x
60x General-Purpose
Chip-Select Machine
Bank 10
Bank11
MS
MS
Local General-Purpose
Chip-Select Machine
Local
Figure 11-2. Memory Controller Machine Selection
Some features are common to all machines.
•
•
A 17-bit most-significant address decode on each memory bank
The block size of each memory bank can vary between 32 Kbytes (1 Mbyte for SDRAM) and 4
Gbytes (128 Mbytes for SDRAM).
•
•
Normal parity may be generated and checked for any memory bank.
Read-modify-write parity may be generated and checked for any memory bank with either 32- or
64-bit port size. Using RMW parity on 32-bit port size bank, requires the bus to be in strict 60x
•
•
•
ECC may be generated and checked for any memory bank with a 64-bit port size
Each memory bank can be selected for read-only or read/write operation.
Each memory bank can use data pipelining, which reduces the required data setup time for
synchronous devices.
•
Each memory bank can be controlled by an external memory controller or bus slave.
The memory controller functionality minimizes the need for glue logic in PowerQUICC II-based systems.
CS1 is used as the RAS signal for 64-bit DRAM with BR1[MS] configured to select UPMA. BS[0–7] are
used as CAS signals on the DRAM.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
11-5
Memory Controller
EPROM
Address
PowerQUICC II
Address
CS0
GPL2/OE
BS/WE[0–7]
Data
CE
GPCM
OE
WE
Data
DRAM
Address
RAS
CS1
UPMA
CAS[0–7]
W
GPLx
Data
Figure 11-3. Simple System Configuration
Implementation differences between the supported machines are described in the following:
•
The SDRAM machine provides a glueless interface to JEDEC-compliant SDRAM devices, and
using SDRAM pipelining, page mode, and bank interleaving delivers very high performance. To
allow fine tuning of system performance, the SDRAM machine provides two types of page modes
selectable per memory bank:
— Page mode for consecutive back-to-back accesses (normal operation)
— Page mode for intermittent accesses
SDRAM machines are available on the 60x and local buses; each memory bank can be assigned to
any SDRAM machine.
•
•
The GPCM provides a glueless interface to EPROM, SRAM, flash EPROM (FEPROM), and other
peripherals. The GPCM is available on both buses on CS[0–11]. CS0 also functions as the global
(boot) chip-select for accessing the boot EPROM or FLASH device. The chip-select allows 0 to 30
wait states.
The UPMs provide a flexible interface to many types of memory devices. Each UPM can control
the address multiplexing for accessing DRAM devices and the timings of BS[0–7] and GPL. Each
UPM can be assigned either to the 60x or to the local bus. Each memory bank can be assigned to
any UPM.
Each UPM is a programmable RAM-based machine. The UPM toggles the memory controller
external signals as programmed in RAM when an internal or external master initiates any external
read or write access. The UPM also controls address multiplexing, address increment, and transfer
acknowledge (TA) assertion for each memory access. The UPM specifies a set of signal patterns
for a user-specified number of clock cycles. The UPM RAM pattern run by the memory controller
is selected according to the type of external access transacted. At every clock cycle, the logical
value of the external signals specified in the RAM array is output on the corresponding UPM pins.
Figure 11-4 shows a basic configuration.
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Freescale Semiconductor
Memory Controller
Internal/External Memory Access Request Select
Address (A),
Address
Type (AT)
Address
Comparator
Bank Select
SDRAM Machine
UPMx
GPCM
Signals
Timing
Generator
MS/BS
Fields
MUX
External Signals
Figure 11-4. Basic Memory Controller Operation
The SDRAM mode registers (LSDMR and PSDMR) define the global parameters for the 60x and local
SDRAM devices. Machine A/B/C mode registers (MxMR) define most of the global features for each
UPM. GPCM parameters are defined in the option register (ORx). Some SDRAM and UPM parameters
are also defined in ORx.
11.2.1 Address and Address Space Checking
The defined base address is written to the BRx. The bank size is written to the ORx. Each time a bus cycle
access is requested on the 60x or local bus, addresses are compared with each bank. If a match is found on
a memory controller bank, the attributes defined in the BRx and ORx for that bank are used to control the
memory access. If a match is found in more than one bank, the lowest-numbered bank handles the memory
access (that is, bank 0 has priority over bank 1).
NOTE
Although 60x bus accesses that hit a bank allocated to the local bus are
transferred to the local bus, local bus access hits to banks allocated to the
60x bus are ignored. 60x-to-local bus transactions have priority over regular
memory bank hits.
11.2.2 Page Hit Checking
The SDRAM machine supports page-mode operation. Each time a page is activated on the SDRAM
device, the SDRAM machine stores its address in a page register. The page information, which the user
writes to the ORx register, is used along with the bank size to compare page bits of the address to the page
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Freescale Semiconductor
11-7
Memory Controller
register each time a bus-cycle access is requested. If a match is found together with bank match, the bus
cycle is defined as a page hit. An open page is automatically closed by the SDRAM machine if the bus
becomes idle, unless ORx[PMS] is set.
11.2.3 Error Checking and Correction (ECC)
ECC can be configured for any bank as long as it is assigned to the 60x bus and is connected to a 64-bit
port size memory. ECC is generated and checked on a 64-bit basis using DP[0–7] for the bank if
BRx[DECC] = 11. If ECC is used, single errors can be corrected and all double-bit errors can be detected.
11.2.4 Parity Generation and Checking
Parity can be configured for any bank, if it is preferred. Parity is generated and checked on a per-byte basis
using DP[0–7] or LDP[0–3] for the bank if BR[DECC] = 01 for normal parity and 10 for RMW parity.
SIUMCR[EPAR] determines the global type of parity (odd or even).
Note that RMW parity can be used only for 32- or 64-bit port size banks. Also, using RMW parity on a
32-bit port size bank requires that the bus is placed in strict 60x mode. This is done by setting BCR[ETM]
NOTE: RMW Parity and ECC Modes and Pipelined Addresses
The following applies only to .25µm (HiP4) silicon.
Due to design constraints, using RMW parity or ECC modes and pipelined
addresses (BCR[PLDP]=0) on the SDRAM interface, requires that the
PSDMR[CL] will be set to 10, choosing CAS latency of 2. If CAS latency
of 3 is needed, use BCR[PLDP] = 1 for a pipeline depth of zero.
When the PowerQUICC II is decoding a 60x read transaction into one of its internal memory-mapped
registers or dual-port RAM that was originated by an external 60x master, it will generate parity bits along
with the data bytes on DP[0–7]. The type of parity (odd or even) is determined by the SIUMCR[EPAR]
programming.
11.2.5 Transfer Error Acknowledge (TEA) Generation
The memory controller asserts the transfer error acknowledge signal (TEA) in the following cases:
•
An unaligned or burst access is attempted to internal PowerQUICC II space (registers or dual-port
RAM). Note that the dual-port RAM cannot be accessed via bursts.
•
•
The core or an external master attempts a burst access to the local bus address space
A bus monitor timeout
11.2.6 Machine Check Interrupt (MCP) Generation
The memory controller asserts machine check interrupt (MCP) in the following cases:
•
A parity error
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Freescale Semiconductor
Memory Controller
•
•
An ECC double-bit error
An ECC single bit error when the maximum number of ECC errors has been reached
11.2.7 Data Buffer Controls (BCTLx and LWR)
The memory controller provides two data buffer controls for the 60x bus (BCTL0 and BCTL1) and one
for the local bus (LWR). These controls are activated when a GPCM- or UPM-controlled bank is accessed
and can be disabled by setting ORx[BCTLD]. An access to an SDRAM-machine controlled bank does not
activate the BCTLx controls. The BCTL signals are asserted on the rising edge of CLKIN on the first cycle
of the memory controller operation. They are negated on the rising edge of CLKIN after the last assertion
of PSDVAL of the access is asserted. (See Section 11.2.13, “Partial Data Valid Indication (PSDVAL).”) If
back-to-back memory controller operations are pending, BCTLx is not negated.
The BCTL signals have a programmable polarity. See Section 4.3.2.6, “SIU Module Configuration
11.2.8 Atomic Bus Operation
The PowerQUICC II supports the following kinds of atomic bus operations BRx[ATOM]:
•
Read-after-write (RAWA). When a write access hits a memory bank in which ATOM = 01, the
PowerQUICC II locks the bus for the exclusive use of the accessing master (internal or external).
While the bus is locked, no other device can be granted the bus. The lock is released when the
master that created the lock accesses the same bank with a read transaction. If the master fails to
release the lock within 256 bus clock cycles, the lock is released and a special interrupt is
generated. This feature is intended for CAM operations.
•
Write-after-read (WARA). When a read access hits a memory bank in which ATOM = 10, the
PowerQUICC II locks the bus for the exclusive use of the accessing master (internal or external).
During the lock period, no other device can be granted bus mastership. The lock is released when
the device that created the lock access the same bank with a write transaction. If the device fails to
release the lock within 256 bus clock cycles, the lock is released and a special interrupt is
generated.
NOTE
This mechanism does not replace the PowerPC reservation mechanism.
11.2.9 Data Pipelining
Multiple-PowerQUICC II systems that use data checking, such as ECC or parity, face a timing problem
when synchronous memories, such as SDRAM, are used. Because these devices can output data every
cycle and because the data checking requires additional data setup time, the timing constraints are
extremely hard to meet. In such systems, the user should set the data pipelining bit, BRx[DR]. This creates
data pipelining of one stage within the memory controller in which the data check calculations are done,
thus eliminating the additional data setup time requirement.
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11-9
Memory Controller
Note that this feature cannot be used with L2 cacheable banks and that in systems that involve both
PowerQUICC II-type masters and 60x compatible master, this feature can still be used on the 60x bus
under the following restrictions:
1. The arbiter and the memory controller are in the same PowerQUICC II.
2. The register field BCR[NPQM] is setup correctly.
11.2.10 External Memory Controller Support
The PowerQUICC II has an option to allocate specific banks (address spaces) to be controlled by an
external memory controller or bus slave, while retaining all the bank properties: port size, data
check/correction, atomic operation, and data pipelining. This is done by programming BRx and ORx[AM]
and by setting the external memory controller bit, BRx[EMEMC]. This action automatically assigns the
bank to the 60x bus. For an access that hits the bank, all bus acknowledgment signals (such as AACK,
PSDVAL, and TA) and the memory-device control strobes are driven by an external memory controller or
slave. If the device that initiates the transaction is internal to the PowerQUICC II, the memory controller
handles the port size, data checking, atomic locking, and data pipelining as if the access were governed by
it.
This feature allows multiple PowerQUICC II systems to be connected in 60x-compatible mode without
losing functionality and performance. It also makes it easy to connect other 60x-compatible slaves on the
60x bus.
11.2.11 External Address Latch Enable Signal (ALE)
The memory controller provides control for an external address latch, needed on the 60x bus in 60x
compatible mode. ALE is asserted for one clock cycle on the first cycle of each memory-controller
transaction. In this section, whenever ALE is not on a timing diagram, assume that it is asserted on the first
cycle in which CS can be asserted.
NOTE
ALE is relevant only on the 60x bus and only in 60x-compatible mode.
11.2.12 ECC/Parity Byte Select (PBSE)
Systems that use ECC or read-modify-write parity, require an additional memory device that requires
byte-select like a normal data device. ANDing BS[0–7] through external logic to achieve the logical
function of this byte-select can affect the memory access timing because it adds a delay to the byte-select
path. The PowerQUICC II’s memory controller provides optional byte-select pins that are an internal
AND of the eight byte selects, allowing glueless, faster connection to ECC/RMW-parity devices.
This option is enabled by setting SIUMCR[PBSE], as described in Section 4.3.2.6, “SIU Module
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Memory Controller
11.2.13 Partial Data Valid Indication (PSDVAL)
The 60x and local buses have an internal 64-bit data bus. According to the 60x bus specification, TA is
asserted when up to a double word of data is transferred. Because the PowerQUICC II supports memories
with port sizes smaller than 64 bits, there is a need for partial data valid indication. The memory controller
uses PSDVAL to indicate that data is latched by the memory on write accesses or valid data is present on
read accesses. The quantity of the data depends on the memory port size and the transfer size. The memory
controller accumulates PSDVAL assertions, and when a double word (or the transfer size) is transferred,
the memory controller asserts TA to indicate that a 60x data beat was transferred. Table 11-1 shows the
number of PSDVAL assertions needed for one TA assertion under various circumstances.
Table 11-1. Number of PSDVAL Assertions Needed for TA Assertion
Port Size
Transfer Size
PSDVAL Assertions
TA Assertions
64
32
32
16
16
16
8
Any
1
2
1
4
2
1
8
4
2
1
1
1
1
1
1
1
1
1
1
1
Double word
Word/half word/byte (32-bit aligned)
Double Word
Word
Half/byte
Double word
Word
8
8
Half
8
Byte
Figure 11-5 shows a double-word transfer on 32-bit port size memory.
Clock
External
Data Bus
(32 msb)
Upper 4 bytes
Lower 4 bytes
PSDVAL
Internal
Data Bus
(32 msb)
Upper 4 bytes
Internal
Data Bus
(32 lsb)
Lower 4 bytes
TA
Figure 11-5. Partial Data Valid for 32-Bit Port Size Memory, Double-Word Transfer
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
11-11
Memory Controller
11.2.14 BADDR[27:31] Signal Connections
The memory controller uses BADDR[27:31] to interface memory and peripheral devices on the 60x bus
in 60x-compatible mode. Not all the BADDR line are necessarily used.
Table 11-2. BADDR Connections
Non-SDRAM
64-/72-BitPort
Size Device
Non-SDRAM
32-Bit Port
Size Device
Any 16-Bit
Port Size
Device
64/72-Bit Port
Size SDRAM
32-Bit Port
Size SDRAM
Any 8-Bit Port
Size Device
BADDR[x]
BADDR[27]
BADDR[28]
BADDR[29]
BADDR[30]
BADDR[31]
N.C.
N.C.
N.C.
N.C.
N.C.
Connected
Connected
N.C
N.C.
N.C.
N.C.
N.C.
N.C.
Connected
Connected
Connected
N.C
Connected
Connected
Connected
Connected
N.C.
Connected
Connected
Connected
Connected
Connected
N.C
N.C
N.C.
11.3 Register Descriptions
Table 11-3 lists registers used to control the 60x bus memory controller.
Table 11-3. 60x Bus Memory Controller Registers
Abbreviation
Name
Reference
BR0–BR11
OR0–OR11]
PSDMR
LSDMR
MAMR
Base register banks 0–11
Section 11.3.1
Section 11.3.2
Section 11.3.3
Option register banks 0–11
60x bus SDRAM machine mode register
UPMA mode register
Section 11.3.5
MBMR
UPMB mode register
MCMR
MDR
UPMC mode register
Memory data register
Section 11.3.6
Section 11.3.7
Section 11.3.12
Section 11.3.8
Section 11.3.10
Section 11.3.9
Section 11.3.11
Section 11.3.13
Section 11.3.14
MAR
Memory address register
MPTPR
PURT
Memory refresh timer prescaler register
60x bus assigned UPM refresh timer
60x bus assigned SDRAM refresh timer
Local bus assigned UPM refresh timer
Local bus assigned SDRAM refresh timer
60x bus error status and control registers
Local bus error status and control regs
PSRT
LURT
LSRT
TESCRx
LTESCRx
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
11-12
Freescale Semiconductor
Memory Controller
11.3.1 Base Registers (BRx)
The base registers (BR0–BR11) contain the base address and address types that the memory controller uses
to compare the address bus value with the current address accessed. Each register also includes a memory
format.
0
15
Field
Reset
R/W
BA
0000_0000_0000_0000
R/W
0x0x10158 (BR11)
16
17
18
19
20
21
22
23
24
26
27
28
29
30
31
1
1
1
Field BA
—
PS
see note
DECC
WP
MS
EMEMC
ATOM
000
DR
V
Reset
R/W
000
0000_000
R/W
see note
see note
Addr
0x10102 (BR0); 0x1010A (BR1); 0x10112 (BR2); 0x1011A (BR3); 0x10122 (BR4); 0x1012A (BR5);
0x10132 (BR6); 0x1013A (BR7); 0x10142 (BR8); 0x1014A (BR9); 0x10152 (BR10); 0x1015A (BR11)
1
For BR0 these fields depend on reset configuration sequence. See Section 5.4.1, “Hard Reset Configuration Word.”
For BR1–11, these fields are cleared at reset.
Figure 11-6. Base Registers (BRx)
Table 11-4. BRx Field Descriptions
Description
Bits
Name
0–16
BA
Base address. The upper 17 bits of each base address register are compared to the address on
the address bus to determine if the bus master is accessing a memory bank controlled by the
memory controller. Used with ORx[BSIZE].
17–18
19–20
—
Reserved, should be cleared.
PS
Port size. Specifies the port size of this memory region.
01 8-bit
10 16-bit
11 32-bit
00 64-bit (60x bus only)
21–22 DECC Data error correction and checking. Specifies the method for data error checking and correction.
00 Data errors checking disabled
01 Normal parity checking
10 Read-modify-write parity checking
11 ECC correction and checking
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
11-13
Memory Controller
Table 11-4. BRx Field Descriptions (continued)
Description
Bits
Name
23
WP
Write protect. Can restrict write accesses within the address range of a BR. An attempt to write to
this address range while WP = 1 can cause TEA to be asserted by the bus monitor logic (if
enabled) which terminates the cycle.
0 Read and write accesses are allowed.
1 Only read accesses are allowed. The memory controller does not assert CSx and PSDVAL on
write cycles to this memory bank. TESCR1[WP] or L_TESCR1[WP] (depending on which bus is
being used) is set if a write to this memory bank is attempted.
24–26
MS
Machine select. Specifies machine select for the memory operations handling and assigns the
bank to the 60x or local bus if GPCM or SDRAM are selected. If UPMx is selected, the bus
assignment is determined by MxMR[BSEL].
000 GPCM—60x bus (reset value)
001 GPCM—local bus
010 SDRAM—60x Bus
011 SDRAM—local bus
100 UPMA
101 UPMB
110 UPMC
111 Reserved
27
EMEMC External MEMC enable. Overrides MS and assigns the bank to the 60x bus. However, other BRx
0 Access are handled by the memory controller according to MS.
1 Access are handled by an external memory controller (or other slave) on the 60x bus. The
external memory controller is expected to assert AACK, TA, and PSDVAL.
00 The address space controlled by the memory controller bank is not used for atomic operations.
01 Read-after-write-atomic (RAWA).Writes to the address space handled by the memory controller
bank cause the PowerQUICC II to lock the bus for the exclusive use of the master. The lock is
released when the master performs a read operation from this address space. This feature is
intended for CAM operations.
10 Write-after-read-atomic (WARA). Reads from the address space handled by the memory
controller bank cause the PowerQUICC II to lock the bus for the exclusive use of the accessing
device. The lock is released when the device performs a write operation to this address space.
11 Reserved
Note: If the device fails to release the bus, the lock is released after 256 clock cycles.
30
31
DR
V
0 No data pipelining is done.
1 Data beats of accesses to the address space controlled by the memory controller bank are
delayed by one cycle. This feature is intended for memory regions that use ECC or parity checks
and need to improve data setup time.
Valid bit. Indicates that the contents of the BRx and ORx pair are valid. The CS signal does not
assert until V is set.
0 This bank is invalid.
1 This bank is valid
Note: An access to a region that has no V bit set may cause a bus monitor time-out. After a system
reset, BR0[V] is set.
Note: Note: If BRx has been selected as the SDRAM controller and BRx[31] has been set, the
SDRAM controller must be invalidated by doing the following:
1. Disable the SDRAM refresh service by clearing PSDMR/LSDMR[RFEN].
2. Wait at least 100 60x-bus clock cycles.
3. Clear BRx[V].
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
11-14
Freescale Semiconductor
Memory Controller
11.3.2 Option Registers (ORx)
The ORx registers define the sizes of memory banks and access attributes. The ORx attributes bits support
the following three modes of operation as defined by BR[MS].
•
•
•
SDRAM mode
GPCM mode
UPM mode
0
11
12
15
Field
Reset
R/W
SDAM
0000_0000_0000_0000
R/W
LSDAM...
1
0x0x1015C (OR11)
16
17
18
19
22
23
25
26
27
28
31
Field ...LSDAM
BPD
ROWST
NUMR
PMSEL IBID
—
1
Reset
R/W
0000_00000_0000_0000
R/W
Addr
0x10106 (OR0); 0x1010E (OR1); 0x10116 (OR2); 0x1011E (OR3); 0x10126 (OR4); 0x1012E (OR5);
0x10136 (OR6); 0x1013E (OR7); 0x10146 (OR8); 0x1014E (OR9); 0x10156 (OR10); 0x1015E (OR11)
1
Reset values are for OR0 only. OR1–11 undefined at reset.
Figure 11-7. Option Registers (ORx)—SDRAM Mode
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
11-15
Memory Controller
Table 11-5. ORx Field Descriptions (SDRAM Mode)
Description
Bits
Name
0–11
SDAM
SDRAM address mask. Provides masking for corresponding BRx bits. By masking address
bits independently, SDRAM devices of different size address ranges can be used. Clearing
bits masks the corresponding address bit. Setting bits causes the corresponding address
bit to be compared with the address pins. Address mask bits can be set or cleared in any
order, allowing a resource to reside in more than one area of the address map. SDAM can
be read or written at any time.
0000_0000_0000 4Gbytes
1000_0000_0000 2 Gbytes
1100_0000_0000 1 Gbyte
1110_0000_0000 512 Mbytes
1111_0000_0000 256 Mbytes
1111_1000_0000 128 Mbytes
1111_1100_0000 64 Mbytes
1111_1110_0000 32 Mbytes
1111_1111_0000 16 Mbytes
1111_1111_1000 8 Mbytes
1111_1111_1100 4 Mbytes
1111_1111_1110 2 Mbytes
1111_1111_1111 1 Mbyte
Note: If xSDMR[PBI] = 0, the maximum size of the memory bank should not exceed 128
Mbytes.
12–16
17–18
LSDAM
BPD
Lower SDRAM address mask. Clearing LSDAM implements a minimum size of 1 Mbyte.
SDRAM Page Information
Banks per device. Sets the number of internal banks per SDRAM device.
00 2 internal banks per device
01 4 internal banks per device
10 8 internal banks per device (not valid for 128-Mbyte SDRAMs)
11 Reserved
Note: For 128-Mbyte SDRAMs, BPD must be 00 or 01.
19–22
ROWST
Row start address bit. Sets the demultiplexed row start address bit. The value of ROWST
depends on SDMR[PBI].
For xSDMR[PBI] = 0:
0010 A7
For xSDMR[PBI] = 1:
0000 A0
0100 A8
0001 A1
0110 A9
...
1000 A10
1100 A12
1010 A11
1101–1111 Reserved
1100 A12
1110 A13
Other values are reserved
23–25
NUMR
Number of row address lines. Sets the number of row address lines in the SDRAM device.
000 9 row address lines
001 10 row address lines
010 11 row address lines
011 12 row address lines
100 13 row address lines
101 14 row address lines
110 15 row address lines
111 16 row address lines
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
11-16
Freescale Semiconductor
Memory Controller
Table 11-5. ORx Field Descriptions (SDRAM Mode) (continued)
Name Description
Bits
26
PMSEL
Page mode select. Selects page mode for the SDRAM connected to the memory controller
bank.
0 Back-to-back page mode (normal operation). Page is closed when the bus becomes
idle.
1 Page is kept open until a page miss or refresh occurs.
27
IBID
—
Internal bank interleaving within same device disable. Setting this bit disables bank
interleaving between internal banks of a SDRAM device connected to the chip-select line.
IBID should be set in 60x-compatible mode if the SDRAM device is not connected to the
BANKSEL pins.
28–31
Reserved, should be cleared.
Figure 11-8 shows ORx as it is formatted for GPCM mode.
0
15
Field
AM
1111_1110_0000_0000
R/W
1
1
Reset
R/W
0x0x1015C (OR11)
16
17
18
19
20
21
22
23
24
27
28
29
30
31
Field AM
—
BCTLD CSNT
ACS
11
—
SCY
1111
SETA TRLX EHTR
—
1
Reset
0
00
0
1
0
0
1
0
0
R/W
Addr
R/W
0x10106 (OR0); 0x1010E (OR1); 0x10116 (OR2); 0x1011E (OR3); 0x10126 (OR4); 0x1012E (OR5);
0x10136 (OR6); 0x1013E (OR7); 0x10146 (OR8); 0x1014E (OR9); 0x10156 (OR10); 0x1015E (OR11)
Reset values are for OR0 only. OR1–11 are undefined at reset.
Figure 11-8. ORx —GPCM Mode
1
Table 11-6 describes ORx fields in GPCM mode.
Table 11-6. ORx—GPCM Mode Field Descriptions
Bits
Name
Description
0–16
AM
Address mask. Masks corresponding BRx bits. Masking address bits independently allows external
devices of different size address ranges to be used.
0 Corresponding address bits are masked.
1 The corresponding address bits are used in the comparison with address pins. Address mask bits
can be set or cleared in any order in the field, allowing a resource to reside in more than one area
of the address map. AM can be read or written at any time.
Note: After system reset, OR0[AM] is 1111_1110_0000_0000_0.
17–18
—
Reserved, should be cleared.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
11-17
Memory Controller
Table 11-6. ORx—GPCM Mode Field Descriptions (continued)
Description
Bits
Name
19
BCTLD Data buffer control disable. Disables the assertion of BCTLx (60x bus) and LWR (local bus) during
an access to the current memory bank. See Section 11.2.7, “Data Buffer Controls (BCTLx and
0 BCTLx and LWR are asserted upon an access to the current memory bank.
1 BCTLx and LWR are not asserted upon an access to the current memory bank.
20
CSNT Chip-select negation time. Determines when CS/WE are negated during an external memory write
access handled by the GPCM. This helps meet address/data hold times for slow memories and
peripherals.
0 CS/WE are negated normally.
1 CS/WE are negated a quarter of a clock earlier. (default)
Note: After system reset OR0[CSNT] is set.
21–22
ACS Address to chip select setup. Can be used when the external memory access is handled by the
GPCM. It allows the delay of the CS assertion relative to the address change.
00 CS is output at the same time as the address lines
01 Reserved
10 CS is output a quarter of a clock after the address lines
11 CS is output half a clock after the address lines (default)
Note: After a system reset, OR0[ACS] = 11.
23
—
Reserved, should be cleared.
24–27
SCY Cycle length in clocks. Determines the number of wait states inserted in the cycle, when the GPCM.
handles the external memory access. Thus it is the main parameter for determining cycle length.
The total cycle length depends on other timing attribute settings.
The total memory access length is (2 + SCY) x Clocks.
If the user selects an external PSDVAL response for this memory bank (by setting the SETA bit),
write a non-zero values to SCY.
0000 = 0 clock cycle wait states...1111 = 15 clock cycles wait states
Note: After a system reset, OR0[SCY] = 1111.
Note: Refer to the note immediately following this table.
28
SETA External access termination (PSDVAL generation). Used to specify that when the GPCM is selected
to handle the memory access initiated to this memory region, the access is terminated externally by
asserting the GTA external pin. In this case, PSDVAL is asserted one or two clocks later, depending
0 PSDVAL is generated internally by the memory controller unless GTA is asserted earlier
externally.
1 PSDVAL is generated after external logic asserts GTA.
Note: After a system reset, the OR0[SETA] is cleared.
29
30
TRLX Timing relaxed. Works in conjunction with EHTR.
EHTR Extended hold time on read accesses. Indicates with TRLX how many cycles are inserted between
a read access from the current bank and the next write access to the same bank, or any type of
access to another bank. It does not affect subsequent read accesses to the same bank.
TRLX and EHTR work together and are interpreted as follows:
00 Normal timing is generated by the memory controller. No additional cycles are inserted.
01 One idle clock cycle is inserted.
10 Four idle clock cycles are inserted. (default)
11 Eight idle clock cycles are inserted.
31
—
Reserved, should be cleared.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
11-18
Freescale Semiconductor
Memory Controller
NOTE
GPCM produces a glitch on the BSx lines when the following memory
controller settings are used: SETA = 1, CSNT = 1, ACS = 01, TRLX = 1,
and SCY = 0000.
During a write operation, the BSx are asserted for 3/4 of a cycle, negated for
1/4 of a cycle, and asserted again until the end of the cycle. Therefore, when
the other conditions occur, it is necessary that SCY ≠ 0000.
Figure 11-9 shows ORx as it is formatted for UPM mode.
0
15
Field
Reset
R/W
AM...
0000_0000_0000_0000
R/W
1
0x0x1015C (OR11)
16
17
18
19
20
22
23
24
28
29
30
31
Field ...AM
—
BCTLD
—
BI
—
EHTR
—
1
Reset
R/W
0000_0000_0000_0000
R/W
Addr 0x10106 (OR0); 0x1010E (OR1); 0x10116 (OR2); 0x1011E (OR3); 0x10126 (OR4); 0x1012E (OR5); 0x10136
(OR6); 0x1013E (OR7); 0x10146 (OR8); 0x1014E (OR9); 0x10156 (OR10); 0x1015E (OR11)
1
Reset values are for OR0 only. OR1–11 are undefined at reset.
Figure 11-9. ORx—UPM Mode
Table 11-7. Option Register (ORx)—UPM Mode
Bits
Name
Description
0–16
AM
Address mask. Provides masking for corresponding BRx bits. By masking address bits
independently, external devices of different size address ranges can be used. Any clear bit masks
the corresponding address bit. Any set bit causes the corresponding address bit to be used in the
comparison with the address pins. Address mask bits can be set or cleared in any order in the field,
allowing a resource to reside in more than one area of the address map. AM can be read or written
at any time.
17–18
19
—
Reserved, should be cleared.
BCTLD Data buffer control disable. Disables the assertion of BCTLx (60x bus) and LWR (local bus) during
an access to the current memory bank. See Section 11.2.7, “Data Buffer Controls (BCTLx and
0 BCTLx and LWR are asserted upon an access to the current memory bank.
1 BCTLx and LWR are not asserted upon an access to the current memory bank.
20–22
—
Reserved, should be cleared.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
11-19
Memory Controller
Table 11-7. Option Register (ORx)—UPM Mode
Description
Bits
Name
23
BI
Burst inhibit. Indicates if this memory bank supports burst accesses.
0 The bank supports burst accesses
1 The bank does not support burst accesses. The UPMx executes burst accesses as series of
single accesses.
24–28
—
Reserved, should be cleared.
29–30 EHTR Extended hold time on read accesses. Indicates how many cycles are inserted between a read
access from the current bank and the next access.
00 Normal timing is generated by the memory controller. No additional cycles are inserted.
01 One idle clock cycle is inserted.
10 Four idle clock cycles are inserted.
11 Eight idle clock cycles are inserted.
31
—
Reserved, should be cleared.
11.3.3 60x SDRAM Mode Register (PSDMR)
pertaining to SDRAM.
0
1
2
4
5
7
8
11
13
14
15
Field PBI RFEN
OP
SDAM
BSMA
SDA10
RFRC
Reset
R/W
0000_0000_0000_0000
R/W
Addr
16
17
19
20
22
23
24
25
26
27
28
29
30
31
Field RFRC
PRETOACT
ACTTORW
BL LDOTOPRE
WRC
EAMUX BUFCMD
CL
Reset
R/W
0000_0000_0000_0000
R/W
Addr
0x10192 (PSDMR), 0x10196 (LSDMR)
Figure 11-10. 60x/Local SDRAM Mode Register (PSDMR/LSDMR)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
11-20
Freescale Semiconductor
Memory Controller
Table 11-8. PSDMR Field Descriptions
Description
Bits
Name
0
PBI
Page-based interleaving. Selects the address multiplexing method. PBI works in conjunction
0 Bank-based interleaving (default at reset)
1 Page-based interleaving (recommended operation)
1
RFEN
Refresh enable. Indicates that the SDRAM needs refresh services.
0 Refresh services are not required
1 Refresh services are required
Note: After system reset, RFEN is cleared.
(LSRT).”
2–4
OP
SDRAM operation. Determines which operation occurs when the SDRAM device is accessed.
000 Normal operation
001 CBR refresh, used in SDRAM initialization.
010 Self refresh (for debug purpose).
011 Mode Register write, used in SDRAM initialization.
Note that if 60x-compatible mode is in effect on the 60x bus or the SDRAM port size is 8/16 or
the SDRAM is connected to the BADDR lines (not needed for 64/32 port size), the bus master
must supply the mode register data on the low bits of the address during the access.
100 Precharge bank (for debug purpose).
101 Precharge all banks, used in SDRAM initialization.
110 Activate bank (for debug purpose).
111 Read/write (for debug purpose).
5–7
SDAM
BSMA
Address multiplex size. Determines how the address of the current memory cycle can be output
8–10
Bank select multiplexed address line. Selects the address pins to serve as bank-select address
for the 60x SDRAM. The bank select address can also be output on the BANKSEL pins
000 A12–A14
001 A13–A15
010 A14–A16
011 A15–A17
100 A16–A18
101 A17–A19
110 A18–A20
111 A19–A21
11–13
SDA10
“A10” control. With PSDMR[PBI], determines which address line can be output to SDA10 during
an ACTIVATE command, when SDRAM is selected, to control the memory access. See
For PBI = 0: For PBI = 1:
000 A12
001 A11
010 A10
011 A9
100 A8
101 A7
110 A6
111 A5
000 A10
001 A9
010 A8
011 A7
100 A6
101 A5
110 A4
111 A3
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
11-21
Memory Controller
Table 11-8. PSDMR Field Descriptions (continued)
Description
Bits
Name
SDRAM Device–Specific Parameters:
14–16
RFRC
Refresh recovery. Defines the earliest timing for an activate command after a REFRESH
command. Sets the refresh recovery interval in clock cycles. See Section 11.4.6.6, “Refresh
Recovery Interval (RFRC),” for how to set this field.
000 Reserved
001 3 clocks
010 4 clocks
011 5 clocks
100 6 clocks
101 7 clocks
110 8 clocks
111 16 clocks
17–19 PRETOACT Precharge to activate interval. Defines the earliest timing for ACTIVATE or REFRESH command
001 1 clock-cycle wait states
010 2 clock-cycle wait states
...
111 7 clock-cycle wait states
000 8 clock-cycle wait states
20–22 ACTTORW Activate to read/write interval. Defines the earliest timing for READ/WRITE command after an
001 1 clock cycle
010 2 clock cycles
...
111 7 clock cycles
000 8 clock cycles
23
BL
Burst length
0 SDRAM burst length is 4. Use this value if the device port size is 64 or 16
1 SDRAM burst length is 8. Use this value if the device port size is 32 or 8
24–25 LDOTOPRE Last data out to precharge. Defines the earliest timing for PRECHARGE command after the last
00 0 clock cycles
01 -1 clock cycle
10 -2 clock cycles
11 Reserved
Note: A value of 0b00 (0 clock cycles) gives the longest time while a value of 0b10 (-2 clock
cycles) gives the least.
26–27
WRC
Write recovery time. Defines the earliest timing for PRECHARGE command after the last data was
01 1 clock cycles
10 2 clock cycles
11 3 clock cycles
00 4 clock cycles
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
11-22
Freescale Semiconductor
Memory Controller
Table 11-8. PSDMR Field Descriptions (continued)
Description
Bits
Name
28
EAMUX
External address multiplexing enable/disable.
0 No external address multiplexing. Fastest timing.
1 The memory controller asserts SDAMUX for an extra cycle before issuing an ACTIVATE
command to the SDRAM. This is useful when external address multiplexing can cause a
delay on the address lines. Note that if this bit is set, ACTTORW should be a minimum of 2.
In 60x-compatible mode, external address multiplexing is placed on the address lines. If the
additional delay of the multiplexing endangers the device setup time, EAMUX should be set.
Setting this bit causes the memory controller to add another cycle for each address phase.
Note that EAMUX can also be set in any case of delays on the address lines, such as address
29
BUFCMD If external buffers are placed on the control lines going to both the SDRAM and address lines,
setting BUFCMD causes all SDRAM control lines except CS to be asserted for two cycles,
0 Normal timing for the control lines
1 All control lines except CS are asserted for two cycles
In 60x-compatible mode, external buffers may be placed on the command strobes, except CS,
as well as the address lines. If the additional delay of the buffers endangers the device setup
time, BUFCMD should be set, which causes the memory controller to add a cycle for each
SDRAM command.
30–31
CL
CAS latency. Defines the timing for first read data after SDRAM samples a column address. See
00 Reserved
01 1
10 2
11 3
11.3.4 Local Bus SDRAM Mode Register (LSDMR)
fields.
Table 11-9. LSDMR Field Descriptions
Bits
Name
Description
0
PBI
Page-based interleaving. Selects the address multiplexing method. PBI works in conjunction
0 Bank-based interleaving
1 Page-based interleaving (normal operation)
1
RFEN
Refresh enable. Indicates that the SDRAM requires refresh services.
0 Refresh services are not required
1 Refresh services are required
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Table 11-9. LSDMR Field Descriptions (continued)
Description
Bits
Name
2–4
OP
SDRAM operation. Selects the operation that occurs when the SDRAM device is accessed.
000 Normal operation
001 CBR refresh, used in SDRAM initialization.
010 Self refresh (for debug purpose).
011 Mode Register write, used in SDRAM initialization.
100 Precharge bank (for debug purpose).
101 Precharge all banks, used in SDRAM initialization.
110 Activate bank (for debug purpose).
111 Read/write (for debug purpose).
5–7
SDAM
BSMA
Address multiplex size. Determines how the address of the current memory cycle is output on
8–10
Bank select multiplexed address line. Selects which PowerQUICC II address pins serve as
bank-select address for the local bus SDRAM. See Section 11.4.5.2, “SDRAM Address
000 L_A14 (ORx[BPD] must be 00)
001 L_A–L_A15 (ORx[BPD] must be 00 or 01)
010 L_A14–L_A16
011 L_A15–L_A17
100 L_A16–L_A18
101 L_A17–L_A19
110 L_A18–L_A20
111 L_A19–L_A21
11–13
SDA10
“A10” control. When SDRAM is selected, with LSDMR[PBI], determines which address line is
output to SDA10 during an ACTIVATE command, to control the memory access. See
For PBI=0: For PBI=1:
000 A12
001 A11
010 A10
011 A9
100 A8
101 A7
110 A6
111 A5
000 A10
001 A9
010 A8
011 A7
100 A6
101 A5
110 A4
111 A3
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Table 11-9. LSDMR Field Descriptions (continued)
Description
Bits
Name
SDRAM Device–Specific Parameters:
14–16
RFRC
Refresh recovery. Defines the earliest timing for an activate command after a REFRESH
command. Sets the refresh recovery interval in clock cycles. See Section 11.4.6.6, “Refresh
Recovery Interval (RFRC),” for how to set this field.
000 Reserved
001 3 clocks
010 4 clocks
011 5 clocks
100 6 clocks
101 7 clocks
110 8 clocks
111 16 clocks
17–19 PRETOACT Precharge to activate interval. Defines the earliest timing for ACTIVATE or REFRESH command
001 1 clock-cycle wait states
010 2 clock-cycle wait states
...
111 7 clock-cycle wait states
000 8 clock-cycle wait states
20–22 ACTTORW Activate to read/write interval. Defines the earliest timing for READ/WRITE command after an
001 1 clock cycle
010 2 clock cycles
...
111 7 clock cycles
000 8 clock cycles
23
BL
Burst length
0 SDRAM burst length is 4. Use this value if the device port size is16
1 SDRAM burst length is 8. Use this value if the device port size is 32 or 8
24–25 LDOTOPRE Last data out to precharge. Defines the earliest timing for PRECHARGE command after the last
00 0 clock cycles
01 -1 clock cycle
10 -2 clock cycles
11 Reserved
26–27
WRC
Write recovery time. Defines the earliest timing for PRECHARGE command after the last data is
01 1 clock cycles
10 2 clock cycles
11 3 clock cycles
00 4 clock cycles
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Bits
Table 11-9. LSDMR Field Descriptions (continued)
Description
Name
EAMUX
28
External address multiplexing enable/disable.
0 No external address multiplexing. Fastest timing.
1 The memory controller asserts SDAMUX for an extra cycle before issuing an ACTIVATE
command to the SDRAM. This is useful when external address multiplexing can cause a
delay on the address lines. Note that if EAMUX is set, ACTTORW should be at least 2.
In local bus mode, external address multiplexing is placed on the address lines. If the additional
delay of the multiplexing endangers the device setup time, EAMUX should be set. Setting this
bit causes the memory controller to add another cycle for each address phase.
Note: EAMUX can also be set in case of address line delays, such as address buffers. See
29
BUFCMD If external buffers are placed on the control lines going to both the SDRAM and address lines,
setting BUFCMD causes all SDRAM control lines except CS to be asserted for two cycles,
0 Normal timing for the control lines
1 All control lines except CS are asserted for two cycles
In 60x-compatible mode, external buffers may be placed on the command strobes, except CS,
as well as the address lines. If the additional delay of the buffers is endangering the device
setup time, BUFCMD should be set to cause the memory controller to add another cycle for
each SDRAM command.
30–31
CL
CAS latency. Defines the timing for first read data after a column address is sampled by the
00 Reserved
01 1 clock cycle
10 2 clock cycles
11 3 clock cycles
11.3.5 Machine A/B/C Mode Registers (MxMR)
UPMs.
0
1
2
3
4
5
7
8
9
10
12
13
14
15
Field BSEL RFEN
OP
—
AMx
DSx
G0CLx
GPL_x4DIS
RLFx
00
Reset
R/W
0000_0000_0000_0
1
R/W
Addr
16
17
18
21
22
25
26
31
Field
Reset
R/W
RLFx
WLFx
TLFx
MAD
0000_0000_0000_0000
R/W
Addr
0x10172 (MAMR); 0x10176 (MBMR); 0x1017A (MCMR)
Figure 11-11. Machine x Mode Registers (MxMR)
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Table 11-10. Machine x Mode Registers (MxMR)
Description
Bits
Name
0
BSEL
Bus select. Assigns banks that select UPMx to the 60x or local bus.
0 Banks that select UPMx are assigned to the 60x bus.
1 Banks that select UPMx are assigned to the local bus.
Note: If refresh is required, the UPM’s should be assigned as follows:
UPMA: 60x bus (if 60x bus refresh needed)
UPMB: Local bus (if local bus refresh required)
UPMC: Any bus, as long as UPMA or UPMB is used on the relevant bus.
1
RFEN
Refresh enable. Indicates that the UPM needs refresh services.
0 Refresh services are not required
1 Refresh services are required
2–3
OP
Command opcode. Determines the command executed by the UPMx when a memory access
hit a UPM assigned bank.
00 Normal operation.
01 Write to array. On the next memory access that hits a UPM assigned bank, write the
contents of the MDR into the RAM location pointed by MAD. After the access, the MAD field
is automatically incremented.
10 Read from array. On the next memory access that hits a UPM assigned bank, read the
contents of the RAM location pointed by MAD into the MDR. After the access, the MAD field
is automatically incremented
11 Run pattern. On the next memory access that hits a UPM assigned bank, run the pattern
written in the RAM array. The pattern run starts at the location pointed by MAD and
continues until the LAST bit is set in the RAM.
Note: RLF determines the number of times a loop is executed during a pattern run.
4
—
Reserved, should be cleared.
5–7
AMx
Address multiplex size. Determines how the address of the current memory cycle can be output
on the address pins. The address output on the pins controlled by the contents of the UPMx
RAM array. This field is useful when connecting the PowerQUICC II to DRAM devices requiring
row and column addresses multiplexed on the same pins.
8–9
DSx
Disable timer period. Guarantees a minimum time between accesses to the same memory
bank if it is controlled by the UPMx. The disable timer is turned on by the TODT in the RAM
array, and when expired, the UPMx allows the machine access to handle a memory pattern to
the same memory region. Accesses to a different memory region by the same UPMx will be
allowed.
00 1-cycle disable period
01 2-cycle disable period
10 3-cycle disable period
11 4-cycle disable period
Note: To avoid conflicts between successive accesses to different memory regions, the
minimum pattern in the RAM array for a request serviced should not be shorter than the
period established by DSx.
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Table 11-10. Machine x Mode Registers (MxMR) (continued)
Description
Bits
Name
G0CLx
10–12
General line 0 control. Determines which address line can be output to the GPL0 pin when the
UPMx is selected to control the memory access.
000 A12
001 A11
010 A10
011 A9
100 A8
101 A7
110 A6
111 A5
13
GPL_x4DIS GPL_A4 output line disable. Determines if the UPMWAIT/GTA/GPL_4 pin behaves as an output
line controlled by the corresponding bits in the UPMx array (GPL4x).
0 UPMWAIT/GTA/GPL_x4 behaves as GPL_4.
UPMx[G4T4/DLT3] is interpreted as G4T4.
The UPMx[G4T3/WAEN] is interpreted as G4T3.
1 UPMWAIT/GTA/GPL_x4 behaves as UPMWAIT.
UPMx[G4T4/DLT3] is interpreted as DLT3.
UPMx[G4T3/WAEN] is interpreted as WAEN.
Note: After a system reset, GPL_x4DIS = 1.
14–17
18–21
22–25
26–31
RLFx
WLFx
TLFx
MAD
Read loop field. Determines the number of times a loop defined in the UPMx will be executed
for a burst- or single-beat read pattern or when MxMR[OP] = 11 (RUN command)
0001 The loop is executed 1 time
0010 The loop is executed 2 times
...
1111 The loop is executed 15 times
0000 The loop is executed 16 times
Write loop field. Determines the number of times a loop defined in the UPMx will be executed
for a burst- or single-beat write pattern.
0001 The loop is executed 1 time
0010 The loop is executed 2 times
...
1111 The loop is executed 15 times
0000 The loop is executed 16 times
Refresh loop field. Determines the number of times a loop defined in the UPMx will be executed
for a refresh service pattern.
0001 The loop is executed 1 time
0010 The loop is executed 2 times
...
1111 The loop is executed 15 times
0000 The loop is executed 16 times
Machine address. RAM address pointer for the command executed. This field is incremented
by 1, each time the UPM is accessed and the OP field is set to WRITE or READ.
11.3.6 Memory Data Register (MDR)
The memory data register (MDR), shown in Figure 11-12, contains data written to or read from the RAM
array for UPM READ or WRITE commands. MDR must be set up before issuing a write command to the
UPM.
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Memory Controller
0
15
Field
Reset
R/W
MD
xxxx_xxxx_xxxx_xxxx
R/W
1
Addr
16
31
Field
Reset
R/W
MD
xxxx_xxxx_xxxx_xxxx
R/W
1
Addr
0x1018A
1
Undefined at reset.
Figure 11-12. Memory Data Register (MDR)
Table 11-11 describes MDR fields.
Table 11-11. MDR Field Descriptions
Bits Name
Description
0–31
MD Memory data. The data to be read or written into the RAM array when a WRITE or READ command is
supplied to the UPM.
11.3.7 Memory Address Register (MAR)
0
15
Field
Reset
R/W
A
xxxx_xxxx_xxxx_xxxx
R/W
1
Addr
16
31
Field
Reset
R/W
A
xxxx_xxxx_xxxx_xxxx
R/W
1
Addr
0x10116A
1
Undefined at reset.
Figure 11-13. Memory Address Register (MAR)
Table 11-12 describes MAR fields.
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Memory Controller
Table 11-12. MAR Field Description
Description
Bits
Name
0–31
A
Memory address. The memory address register can be output to the address lines under control of
the AMX bits in the UPM
11.3.8 60x Bus-Assigned UPM Refresh Timer (PURT)
0
7
Field
Reset
R/W
PURT
0000_0000
R/W
Addr
Figure 11-14. 60x Bus-Assigned UPM Refresh Timer (PURT)
Table 11-13 describes PURT fields.
Table 11-13. 60x Bus-Assigned UPM Refresh Timer (PURT)
Description
PURT Refresh timer period. Determines the timer period according to the following equation:
Bits
Name
0–7
(PURT + 1) × (MPTPR[PTP] + 1)
⎛
⎝
⎞
⎠
----------------------------------------------------------------------------------------
TimerPeriod =
Bus Frequency
This timer generates a refresh request for all valid banks that selected a UPM machine assigned to
the 60x bus (MxMR[BSEL] = 0) and is refresh-enabled (MxMR[RFEN] = 1). Each time the timer
expires, a qualified bank generates a refresh request using the selected UPM. The qualified banks
are rotating their requests.
Example: For a 25-MHz system clock and a required service rate of 15.6 µs, given
MPTPR[PTP] = 31, the PURT value should be 11decimal. (12*32)/25 MHz = 15.36 µs, which is less
than the required service period of 15.6 µs.
11.3.9 Local Bus-Assigned UPM Refresh Timer (LURT)
0
7
Field
Reset
R/W
LURT
0000_0000
R/W
Addr
Figure 11-15. Local Bus-Assigned UPM Refresh Timer (LURT)
Table 11-14 describes LURT fields.
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Memory Controller
Table 11-14. Local Bus-Assigned UPM Refresh Timer (LURT)
Description
Bits
Name
0–7
LURT Refresh timer period. Determines the timer period according to the following equation:
(LURT + 1) × (MPTPR[PTP] + 1)
⎛
⎝
⎞
⎠
----------------------------------------------------------------------------------------
TimerPeriod =
Bus Frequency
This timer generates a refresh request for all valid banks that selected a UPM machine assigned to
the local bus (MxMR[BSEL] =1) and is refresh-enabled (MxMR[RFEN] =1). Each time the timer
expires, a qualified bank generates a refresh request using the selected UPM. The qualified banks
are rotating their requests.
Example: For a 25-MHz system clock and a required service rate of 15.6 µs, given
MPTPR[PTP] = 31, the LURT value should be 11 decimal. (12*32)/25 MHz = 15.36 µs, which is less
than the required service period of 15.6 µs.
11.3.10 60x Bus-Assigned SDRAM Refresh Timer (PSRT)
0
7
Field
Reset
R/W
PSRT
0000_0000
R/W
Addr
Figure 11-16. 60x Bus-Assigned SDRAM Refresh Timer (PSRT)
Table 11-15 describes PSRT fields.
Table 11-15. 60x Bus-Assigned SDRAM Refresh Timer (PSRT)
Description
PSRT Refresh timer period. Determines the timer period according to the following equation:
Bits
Name
0–7
(PSRT + 1) × (MPTPR[PTP] + 1)
⎛
⎝
⎞
⎠
---------------------------------------------------------------------------------------
TimerPeriod =
Bus Frequency
This timer generates refresh requests for all valid banks that selected a SDRAM machine assigned
to the 60x bus and is refresh-enabled (PSDMR[RFEN] = 1). Each time the timer expires, all banks
that qualify generate a bank staggering auto refresh request using the SDRAM machine. See
Example: For a 25-MHz system clock and a required service rate of 15.6 µs, given
MPTPR[PTP] = 31, the PSRT value should be 11decimal. (12*32)/25 MHz = 15.36 µs, which is less
than the required service period of 15.6 µs.
11.3.11 Local Bus-Assigned SDRAM Refresh Timer (LSRT)
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0
7
Field
Reset
R/W
LSRT
0000_0000
R/W
Addr
Figure 11-17. Local Bus-Assigned SDRAM Refresh Timer (LSRT)
Table 11-16 describes LSRT fields.
Table 11-16. LSRT Field Descriptions
Description
Bits
Name
0–7
LSRT Refresh timer period. Determines the timer period according to the following equation:
(LSRT + 1) × (MPTPR[PTP] + 1)
⎛
⎝
⎞
⎠
---------------------------------------------------------------------------------------
TimerPeriod =
Bus Frequency
This timer generates refresh requests for all valid banks that selected a SDRAM machine assigned
to the local bus and is refresh enabled (LSDMR[RFEN] = 1). Each time the timer expires, all banks
that qualify generate a bank staggering auto refresh request using the SDRAM machine. See
Example: For a 25-MHz system clock and a required service rate of 15.6 µs, given
MPTPR[PTP] = 31, the LSRTvalue should be 11decimal. (12*32)/25 MHz = 15.36 µs, which is less
than the required service period of 15.6 µs.
11.3.12 Memory Refresh Timer Prescaler Register (MPTPR)
Figure 11-18 shows the memory refresh timer prescaler register (MPTPR).
0
7
8
15
Field
Reset
R/W
PTP
—
undefined
R/W
Addr
Figure 11-18. Memory Refresh Timer Prescaler Register (MPTPR)
Table 11-17 describes MPTPR fields.
Table 11-17. MPTPR Field Descriptions
Bits
Name
Description
0–7
PTP Refresh timers prescaler. Determines the period of the memory refresh timers input clock. It divides
the bus clock. Prescaler clock frequency = Bus frequency / (PTP + 1).
8–15
—
Reserved, should be cleared
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11.3.13 60x Bus Error Status and Control Registers (TESCRx)
These registers indicate the source of an error that caused TEA or MCP to be asserted on the 60x bus. See
Section 4.3.2.10, “60x Bus Transfer Error Status and Control Register 1 (TESCR1),” and Section 4.3.2.11,
11.3.14 Local Bus Error Status and Control Registers (L_TESCRx)
These registers indicate the source of an error that causes TEA or MCP to be asserted on the local bus. See
11.4 SDRAM Machine
The PowerQUICC II provides one SDRAM interface (machine) for the 60x bus and one for the local bus.
The machines provide the necessary control functions and signals for JEDEC-compliant SDRAM devices.
interface signals controlled by the memory controller.
Table 11-18. SDRAM Interface Signals
60x Bus
Local Bus
Comments
CS[0–11]
Device select
RAS
PSDRAS
SDCAS
SDWE
LSDRAS
LSDCAS
LSDWE
CAS
WEN
SDA10
LSDA10
“A10” control
Byte select
DQM[0–7]
LDQM[0–3]
Additional controls are available in 60x-compatible mode (60x bus only):
•
•
ALE—External address latch enable
PSDAMUX—External address multiplexing control (asserted = row, negated = column)
Throughout this section, whenever a signal is named, the reference is to the 60x or local bus signal,
according to the accessed bank’s machine-select.
Figure 11-19. shows an eight-bank, 128-Mbyte system. Each bank consists of eight 2 x 1-Mbit x 8
SDRAMs. Note that the SDRAM memory clock must operate at the same frequency as, and be
phase-aligned with, the system clock.
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Memory Controller
y
PowerQUICC II
PSDDQM[0–7]
A[17]
PSDA10
A[19–28]
12-bit
D[0–63]
CS[0–7]
PSDRAS
PSDWE
PSDCAS
CAS
CS
RAS
WE
CKE
CLK
CAS
CS
RAS
WE
CKE
CLK
CS7
CS7
x8
2x1M x8
SDRAM
2x1M x8
SDRAM
FM CLK SOURCE
DQM
DQM
ADDR[0–11]
ADDR[0–11]
DQ[0–7]
DQ[0–7]
DATA[0–7]
DATA[56–63]
x8
x8
CAS
CAS
CS0
x8
CS
RAS
WE
CKE
CLK
CS
RAS
WE
CKE
CLK
CS0
2x1M x8
SDRAM
2x1M x8
SDRAM
DQM
DQM
ADDR[0–11]
ADDR[0–11]
DQ[0–7]
DQ[0–7]
DATA[0–7]
DATA[56–63]
Figure 11-19. 128-Mbyte SDRAM (Eight-Bank Configuration, Banks 1 and 8 Shown)
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11.4.1 Supported SDRAM Configurations
The PowerQUICC II memory controller supports any SDRAM configuration under the restrictions that all
SDRAM devices that reside on the same bus (60x or local) should have the same port size and timing
parameters. For more information, refer to Application Note 2165, “MPC8260 SDRAM Support” (order
number AN2165/D).
11.4.2 SDRAM Power-On Initialization
At system reset, initialization software must set up the programmable parameters in the memory controller
banks registers (ORx, BRx, P/LSDMR). After all memory parameters are configured, system software
should execute the following initialization sequence for each SDRAM device.
1. Issue a PRECHARGE-ALL-BANKS command
2. Issue eight CBR REFRESH commands
NOTE
If the SDRAM does not require eight CBR REFRESH COMMANDS, then the
SDRAM requirement should be followed.
3. Issue a MODE-SET command to initialize the mode register
The initial commands are executed by setting P/LSDMR[OP] and accessing the SDRAM with a
single-byte transaction. See Figure 11-10 on page 11-20.
Note that software should ensure that no memory operations begin until this process completes.
11.4.3 JEDEC-Standard SDRAM Interface Commands
The PowerQUICC II performs all accesses to SDRAM by using JEDEC-standard SDRAM interface
commands. The SDRAM device samples the command and data inputs on the rising edge of the
PowerQUICC II bus clock. Data at the output of the SDRAM device must be sampled on the rising edge
of the PowerQUICC II bus clock.
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Table 11-19. SDRAM Interface Commands
Description
Command
BANK-ACTIVATE
Latches the row address and initiates a memory read of that row. Row data is latched in SDRAM
sense amplifiers and must be restored with a PRECHARGE command before another BANK-ACTIVATE
is issued.
MODE-SET
Allows setting of SDRAM options—CAS latency, burst type, and burst length. CAS latency depends
on the SDRAM device used (some SDRAMs provide CAS latency of 1, 2, or 3; some provide a
latency of 1, 2, 3, or 4, etc.). Burst type must be chosen according to the 60x cache wrap
(sequential). Although some SDRAMs provide burst lengths of 1, 2, 4, 8, or a page, PowerQUICC II
supports only a 4-beat burst for 64-bit port size and an 8-beat burst for 32-bit port size.
PowerQUICC II does not support burst lengths of 1, 2, and a page for SDRAMs. The mode register
data (CAS latency, burst length, and burst type) is programmed into the P/LSDMR register by
initialization software at reset. After the P/LSDMR is set, the PowerQUICC II transfers the
PRECHARGE
(SINGLE
Restores data from the sense amplifiers to the appropriate row. Also initializes the sense amplifiers
to prepare for reading another row in the SDRAM array. A PRECHARGE command must be issued
BANK/ALL BANKS) after a read or write if the row address changes on the next access. Note that the PowerQUICC II
uses the SDA10 pin to distinguish the PRECHARGE-ALL-BANKS command. The SDRAMs must be
compatible with this format.
READ
Latches the column address and transfers data from the selected sense amplifier to the output buffer
as determined by the column address. During each successive clock, additional data is output
without additional READ commands. The amount of data transferred is determined by the burst size.
At the end of the burst, the page remains open.
REFRESH
WRITE
Causes a row to be read in both memory banks (JEDEC SDRAM) as determined by the refresh row
address counter (similar to CBR). The refresh row address counter is internal to the SDRAM device.
After being read, a row is automatically rewritten into the memory array. Both banks must be in a
precharged state before executing REFRESH.
Latches the column address and transfers data from the data signals to the selected sense amplifier
as determined by the column address. During each successive clock, additional data is transferred
to the sense amplifiers from the data signals without additional WRITE commands. The amount of
data transferred is determined by the burst size. At the end of the burst, the page remains open.
11.4.4 Page-Mode Support and Pipeline Accesses
The SDRAM interface supports back-to-back page mode. A page remains open as long as back-to-back
accesses that hit the page are generated on the bus. The page is closed once the bus becomes idle unless
ORx[PMSEL] is set.
The use of SDRAM pipelining allows data phases to occur on with zero bubbles for CPM accesses and
with one bubble for core accesses, as required by the 60x bus specification.
If ETM/LETM = 1, the use of SDRAM pipelining also allows for back-to-back data phases to occur with
zero clocks of separation for CPM accesses and with one clock of separation for core accesses, as required
by the 60x bus specification.
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11.4.5 Bank Interleaving
The SDRAM interface supports bank interleaving. This means that if a missed page is in a different
SDRAM bank than the currently open page, the SDRAM machine first issues an ACTIVATE command to
the new page and later issues a DEACTIVATE command to the old page, thus eliminating the DEACTIVATE
time overhead.
This procedure can be done if both pages reside on different SDRAM devices or on different internal
SDRAM banks. The second option can be disabled by setting ORx[IBID]. The user should set this bit if
the BNKSEL pins are not used in 60x-compatible mode.
The following two methods are used for internal bank interleaving:
•
Page-based interleaving—Page-based interleaving yields the best performance and is the preferred
interleaving method. This method uses low address bits as the Bank-Select for the SDRAM, thus
allowing interleaving on every page boundary. It is activated by setting xSDMR[PBI]=1. See
•
Bank-based interleaving —This method uses the most-significant address bits as the bank-select
for the SDRAM, thus allowing interleaving only on bank boundaries. It is activated by clearing
11.4.5.1 Using BNKSEL Signals in Single-PowerQUICC II Bus Mode
The BNKSEL signals provide the following functionality in single-PowerQUICC II bus mode
•
If bank-based interleaving is used, BNKSEL signals facilitate compatibility with SDRAMs that
have different numbers of row or column address lines. The address lines of the PowerQUICC II
bus and the BNKSEL lines can be routed independently to the address lines and BA lines of the
DIMM. Note that all SDRAMs populated on an PowerQUICC II bus must still have the same
organization. This flexibility merely allows the SDRAMs to be populated as a group with larger or
smaller devices as appropriate.
If BNKSEL lines were not used, the number of row and column address lines of the SDRAMs
would affect which PowerQUICC II address bus lines on which the bank select signals would be
driven, and would thus require that the BA signals of the SDRAMs be routed to those address lines,
thus limiting flexibility.
•
If BCR[EAV] is programmed, BNKSEL signals facilitate logic analysis of the system. Otherwise,
the logic analyzer equipment must understand the address multiplexing scheme of the board and
intelligently reconstruct the address of bus transactions.
11.4.5.2 SDRAM Address Multiplexing (SDAM and BSMA)
In single PowerQUICC II mode, the lower bits of the address bus are connected to the device’s address
port, and the memory controller multiplex the row/column and the internal banks select lines, according
to the PL/SDMR[SDAM] and PL/SDMR[BSMA].
Table 11-20. shows how P/LSDMR[SDAM] settings affect address multiplexing. For the effect of
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
11-37
Memory Controller
Note that in 60x-compatible mode, the 60x address must be latched and multiplexed by glue logic that is
controlled by ALE and SDAMUX, however, the user still has to configure PSDMR[SDAM].
multiplexing for A0–A15.
Table 11-20. SDRAM Address Multiplexing (A0–A15)
ExternalBus
SDAM
Address
Pins
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15
000
001
010
011
100
101
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
A5 A6 A7
Signal
driven on
externalpins
when
address
multiplexing
is enabled
—
—
—
—
—
A5 A6
—
—
—
—
A5
—
—
—
Table 11-21 shows SDRAM address multiplexing for A16–A31.
Table 11-21. SDRAM Address Multiplexing (A16–A31)
ExternalBus
Address
Pins
SDAM
A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31
000
001
010
011
100
101
A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23
A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22
A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21
A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20
A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19
Signal
driven on
externalpins
when
address
multiplexing
is enabled
—
—
A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18
11.4.6 SDRAM Device-Specific Parameters
The software is responsible for setting correct values to some device-specific parameter that can be
extracted from the data sheet. The values are stored in the ORx and P/LSDMR registers. These parameters
include the following:
•
•
•
Precharge to activate interval (P/LSDMR[PRETOACT]). See Section 11.4.6.1,
Activate to read/write interval (P/LSDMR[ACTTORW]). See Section 11.4.6.2, “Activate to
CAS latency, column address to first data out (P/LSDMR[CL]). See Section 11.4.6.3, “Column
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
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Freescale Semiconductor
Memory Controller
•
•
•
•
•
Last data out to precharge (P/LSDMR[LDOTOPRE]). Section 11.4.6.4, “Last Data Out to
Write recovery, last data in to precharge (P/LSDMR[WRC]). See Section 11.4.6.5, “Last Data In
Refresh recovery interval (P/LSDMR[RFRC]). See Section 11.4.6.6, “Refresh Recovery Interval
(RFRC).”
External address multiplexing present (P/LSDMR[EAMUX]). See Section 11.4.6.7, “External
External buffers on the control lines present (P/LSDMR[BUFCMD]). See Section 11.4.6.8,
The following sections describe the SDRAM parameters that are programmed in the P/LSDMR register.
11.4.6.1 Precharge-to-Activate Interval
earliest timing for activate or refresh command after a precharge command.
CLK
ALE
CS
SDRAS
SDCAS
MA11
RAy
RAy
MA10
MA[0–9]
WE
DQM
PRETOACT
= 2
PRECHARGE
Command
Bank A
ACTIVATE
Command
Bank A
Figure 11-20. PRETOACT = 2 (2 Clock Cycles)
11.4.6.2 Activate to Read/Write Interval
As represented in Figure 11-21, this parameter, controlled by P/LSDMR[ACTTORW], defines the earliest
timing for READ/WRITE command after an ACTIVATE command.
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Freescale Semiconductor
11-39
Memory Controller
CLK
ALE
CS
SDRAS
SDCAS
MA[0–11]
WE
Cbz
D0
Rbz
DQM
DATA
D1
D2
D3
ACTTORW = 2
ACTIVATE
Command
WRITE
Command
Figure 11-21. ACTTORW = 2 (2 Clock Cycles)
11.4.6.3 Column Address to First Data Out—CAS Latency
As seen in Figure 11-22, this parameter, controlled by P/LSDMR[CL], defines the timing for first read data
after a column address is sampled by the SDRAM.
Activate
Read
First data out
CLK
ALE
CL = 2
CSn
SDRAS
SDCAS
WE
Row
Column
MA[0–11]
DQMn
Data
D0
D2
D1
D3
Figure 11-22. CL = 2 (2 Clock Cycles)
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Memory Controller
11.4.6.4 Last Data Out to Precharge
timing for the PRECHARGE command after the last data was read from the SDRAM. It is always related to
the CL parameter.
Activate
Read
Deactivate
Last Data Out
CLK
ALE
LDOTOPRE = 2
CS
SDRAS
SDCAS
WE
Column
MA[0–11]
Row
DQM
Data
D0
D2
D1
D3
Figure 11-23. LDOTOPRE = 2 (-2 Clock Cycles)
11.4.6.5 Last Data In to Precharge—Write Recovery
timing for PRECHARGE command after the last data was written to the SDRAM.
Activate
WRITE
Last data in
Deactivate
CLK
ALE
WRC = 2
CS
SDRAS
SDCAS
WE
Column
MA[0–11]
DQM
Row
D0
D2
D1
D3
Data
Figure 11-24. WRC = 2 (2 Clock Cycles)
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Freescale Semiconductor
11-41
Memory Controller
11.4.6.6 Refresh Recovery Interval (RFRC)
timing for an ACTIVATE command after a REFRESH command.
CLK
ALE
CS
SDRAS
SDCAS
A8 = 1
MA[0–11]
RAx
WE
DQM
PRETOACT
= 3
RFRC = 4 (6 clocks)
Precharge
if needed
Activate command
Bank A
Auto refresh
Figure 11-25. RFRC = 4 (6 Clock Cycles)
11.4.6.7 External Address Multiplexing Signal
In 60x-compatible mode, external address multiplexing is placed on the address lines. If the additional
delay of multiplexing endangers the device setup time, P/LSDMR[EAMUX] should be set. Setting this bit
causes the memory controller to add another cycle for each address phase. Figure 11-26 demonstrates the
timing when EAMUX equals 1.
Note that EAMUX can also be set in any case of delays on the address lines, such as address buffers.
CLK
ALE
SDAMUX
CMD
NOP
Act
NOP
Column
Read
NOP
MA[0–11]
Row
Address setup cycle
Figure 11-26. EAMUX = 1
11.4.6.8 External Address and Command Buffers (BUFCMD)
In 60x-compatible mode, external buffers may be placed on the command strobes, except CS, as well as
the address lines. If the additional delay of the buffers is endangering the device setup time,
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Memory Controller
P/LSDMR[BUFCMD] should be set. Setting this bit causes the memory controller to add one cycle for
CLK
ALE
SDAMUX
CMD strobes
(without cs)
Activate
NOP
Read
NOP
MA[0–11]
CS
Row
Column
Command setup cycle
Command setup cycle
Figure 11-27. BUFCMD = 1
11.4.7 SDRAM Interface Timing
CLK
ALE
CS
SDRAS
SDCAS
Row
Column
MA[0–11]
WE
DQM
Data
D0
Figure 11-28. SDRAM Single-Beat Read, Page Closed, CL = 3
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Freescale Semiconductor
11-43
Memory Controller
CLK
ALE
CS
SDRAS
SDCAS
MA[0–11]
WE
Column
Z
DQM
D0
Data
Figure 11-29. SDRAM Single-Beat Read, Page Hit, CL = 3
CLK
ALE
CS
SDRAS
SDCAS
MA[0–11]
WE
Row
Column
DQM
Data
D1
D0
Figure 11-30. SDRAM Two-Beat Burst Read, Page Closed, CL = 3
Deactivate
Activate
CLK
ALE
CS
SDRAS
SDCAS
MA[0–11]
WE
BS
*
A10 = 1
Row
Col
Z
DQM
D0
D2
D1
D4
Data
* BS—Bank select according to SDRAM organization. A10 = 1 means all banks are precharged.
CAS Latency = 3
Figure 11-31. SDRAM Four-Beat Burst Read, Page Miss, CL = 3
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Freescale Semiconductor
Memory Controller
CLK
ALE
CS
SDRAS
SDCAS
MA[0–11]
WE
Column
DQM
D0
Data
Figure 11-32. SDRAM Single-Beat Write, Page Hit
CLK
ALE
CS
SDRAS
SDCAS
MA[0–11]
WE
Row
Column
DQM
Data
D0
D1
D2
Figure 11-33. SDRAM Three-Beat Burst Write, Page Closed
CLK
ALE
CS
SDRAS
SDCAS
MA[0–11]
WE
Z
Column1
Column2
DQM
D0
D1
D0
D1
Data
DQM latency (affects negation only) = 2
Figure 11-34. SDRAM Read-after-Read Pipeline, Page Hit, CL = 3
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Freescale Semiconductor
11-45
Memory Controller
CLK
ALE
CS
SDRAS
SDCAS
MA[0–11]
WE
Column1
Column2
D2
DQM
D1
D3
D0
D1
D3
D0
D2
Data
Figure 11-35. SDRAM Write-after-Write Pipelined, Page Hit
CLK
ALE
CS
SDRAS
SDCAS
MA[0–11]
WE
Column1
D1
Z
Column2
DQM
D1
D2
D3
D0
D2
D3
D0
Data
Figure 11-36. SDRAM Read-after-Write Pipelined, Page Hit
11.4.8 SDRAM Read/Write Transactions
The SDRAM interface supports the following read/write transactions:
•
•
Single-beat reads/writes up to double word size
Bursts of two, three, or four double words
SDRAM devices perform bursts for each transaction, the burst length depends on the port size. For 64-bit
port size, it is a burst of 4. For 32-bit port size, it is a burst of 8. For reads that require less than the full
burst length, extraneous data in the burst is ignored. For writes that require less than the full burst length,
the PowerQUICC II protects non-targeted addresses by driving DQMn high on the irrelevant cycles of the
burst. However, system performance is not compromised since, if a new transaction is pending, the
PowerQUICC II begins executing it immediately, effectively terminating the burst early.
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Memory Controller
11.4.9 SDRAM MODE-SET Command Timing
The PowerQUICC II transfers mode register data (CAS latency, burst length, burst type) stored in
MODE-SET command.
Mode Set
Page Activate
Write (Burst)
CLK
ALE
CS
SDRAS
SDCAS
MA[0–11]
WE
*Mode Data
Row
Column
D2
DQM
D3
Z
Z
D0
D1
Data
*The mode data is the address value during a mode-set cycle. It is driven by the memory controller, in single
PowerQUICC II mode, according to P/LSDMR[CL] register. In 60x-compatible mode, software must drive the
Figure 11-37. SDRAM MODE-SET Command Timing
Figure 11-38 shows mode data bit settings.
Bit number
0
1
2
3
4
5
6
7
8
0
9
10 11
BL
lsb
CL
burst length:
4(010) for 16- and 64-bit port sizes
8(011) for 8- and 32-bit port sizes
latency mode—can be 1(001), 2(010), or 3(011).
Figure 11-38. Mode Data Bit Settings
11.4.10 SDRAM Refresh
The memory controller supplies auto (CBR) refreshes to SDRAM according to the interval specified in
PSRT or LSRT. This represents the time period required between refreshes. The value of P/LSRT depends
on the specific SDRAM devices used and the operating frequency of the PowerQUICC II’s bus. This value
should allow for a potential collision between memory accesses and refresh cycles. The period of the
refresh interval must be greater than the access time to ensure that read and write operations complete
successfully.
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Freescale Semiconductor
11-47
Memory Controller
There are two levels of refresh request priority—low and high. The low priority request is generated as
soon as the refresh timer expires, this request is granted only if no other requests to the memory controller
are pending. If the request is not granted (memory controller is busy) and the refresh timer expires two
more times, the request becomes high priority and is served when the current memory controller operation
finishes.
NOTE
There are two SDRAM refresh timers, one for 60x SDRAM machines and
one for local bus SDRAM machines.
11.4.11 SDRAM Refresh Timing
The memory controller implements bank staggering for the auto refresh function. This reduces
instantaneous current consumption for memory refresh operations.
Once a refresh request is granted the memory controller begins issuing auto-refresh command to each
device associated with the refresh timer, in one clock intervals. After the last REFRESH command is issued,
the memory controller waits for the number of clocks written in the SDRAM machine’s mode register
(RFRC in P/LSDMR). The timing is shown in Figure 11-39.
Activate
CBR
CBR
CBR
CBR
RFRC
CLK
CS0
CS1
CS2
CS3
SDRAS
SDCAS
WE
MA[0–11]
DQM
Z
Data
Figure 11-39. SDRAM Bank-Staggered CBR Refresh Timing
11.4.12 SDRAM Configuration Examples
The following sections provide SDRAM configuration examples for page- and bank-based interleaving.
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Memory Controller
11.4.12.1 SDRAM Configuration Example (Page-Based Interleaving)
Consider the following SDRAM organization:
•
•
64-bit port size, organized as eight 64-Mbit devices, each organized as 8M x 8bits.
Each device has 4 internal banks, 12 rows, and 9 columns
Table 11-22. 60x Address Bus Partition
A[0–5]
A[6–17]
Row
A[18–19]
A[20–28]
Column
A[29–31]
lsb
msb of start address
Bank select
The following parameters can be extracted:
•
•
•
•
PSDMR[PBI] = 1—Page-based interleaving
ORx[BPD] = 01—Four internal banks
ORx[ROWST] = 0110—Row starts at A[6]
ORx[NUMR] = 011—Twelve row lines
Now, from the SDRAM device point of view, during an ACTIVATE command, its address port should look
Table 11-23. SDRAM Device Address Port during ACTIVATE Command
“A[0–14]”
—
A[15–16]
A[17–28]
A[29–31]
n.c.
Internal bank select (A[18–19])
Row (A[6–17])
Table 11-20 on page 11-38 indicates that to multiplex A[6–17] over A[17–28], PSDMR[SDAM] must be
011 and, because the internal bank selects are multiplexed over A[15–16], PSDMR[BSMA] must be 010
(only the lower two bank select lines are used).
When using bank-based interleaving, the internal bank-select signals that are multiplexed over the address
lines should be adjacent to the row address during the ACTIVATE command (refer to Table 11-23). So, the
value of PSDMR[BSMA] is selected according to the combination of PSDMR[SDAM], ORx[ROWST],
and ORx[NUMR]. Otherwise, the output of the BNKSEL pins could be incorrect even if the device is
connected to the BNKSEL pins. To ensure proper connection, note that BNKSEL0 is msb and BNKSEL2
is lsb as stated in Table 6-1.
When using page-based interleaving, the internal bank-select signals that are mutilplexed over the address
lines are determined only by PSDMR[BSMA] during the ACTIVATE command. The output of the BNKSEL
pins are not affected by the PSDMR[BSMA] value.
Table 11-24. SDRAM Device Address Port during READ/WRITE Command
“A[0–14]”
—
A[15–16]
A[17]
A[18]
AP
A[19]
A[20–28]
Column
A[29–31]
n.c.
Internal bank select
Don’t care
Don’t care
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Freescale Semiconductor
11-49
Memory Controller
Because AP alternates with A[7] of the row lines, set PSDMR[SDA10] = 011. This outputs A[7] on the
SDA10 line during the ACTIVATE command and AP during READ/WRITE and CBR commands.
Table 11-25 shows the register configuration. Not shown are PSRT and MPTPR, which should be
programmed according to the device refresh requirements:
Table 11-25. Register Settings (Page-Based Interleaving)
Register
Settings
EMEMC0
BRx
BA Base address
PS00 = 64-bit port size
DECC00
ATOM00
DR0
WP0
V 1
MS010 = SDRAM-60x bus
ORx
AM1111_1100_0000
LSDAM00000
BPD01
NUMR011
PMSEL0
IBID0
ROWST0110
PSDMR
PBI1
RFEN1
ACTTOROW from device data sheet
BL0
OP000
SDAM011
BSMA010
LDOTOPRE from device data sheet
WRC from device data sheet
EAMUX0
SDA10011
BUFCMD0
RFRC from device data sheet
PRETOACT from device data sheet
CL from device data sheet
11.4.13 SDRAM Configuration Example (Bank-Based Interleaving)
Consider the following SDRAM organization:
•
•
Eight 64 Mbit devices, each organized as 8M x 8bits
Each device has four internal banks, 12 rows, and 9 columns
For bank-based Interleaving, this means that the address bus should be partitioned as shown in
Table 11-26. 60x Address Bus Partition
A[0–5]
A[6–7]
A[8–19]
Row
A[20–28]
Column
A[29–31]
lsb
msb of start address Internal bank select
The following parameters can be extracted:
•
•
•
•
PSDMR[PBI] = 0
ORx[BPD] = 01—4 internal banks
ORx[ROWST] = 0100—row starts at A[8]
ORx[NUMR] = 011—there are 12 row lines
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Memory Controller
Now, from the SDRAM device point of view, during an ACTIVATE command, its address port should look
Table 11-27. SDRAM Device Address Port during ACTIVATE Command
“A[0–14]”
—
A[15–16]
A[17–28]
A[29–31]
n.c.
Internal bank select (A[6–7])
Row (A[8–19])
Table 11-20. indicates that in order to multiplex A[6–19] over A[15–28] PSDMR[SDAM] must be 001
and, because the internal bank selects are multiplexed over A[15–16] PSDMR[BSMA] must be 010 (only
the lower two bank select lines are used).
Table 11-28. SDRAM Device Address Port during READ/WRITE Command
“A[0–14]”
—
A[15–16]
A[17]
A[18]
AP
A[19]
A[20–28]
Column
A[29–31]
n.c.
Internal bank select
Don’t care
Don’t care
Because AP alternates with A[9] of the row lines, set PSDMR[SDA10] = 011. This outputs A[9] on the
SDA10 line during the ACTIVATE command and AP during READ/WRITE and CBR commands.
Table 11-29. shows the register configuration. Not shown are PSRT and MPTPR, which should be
programmed according to the device refresh requirements.
Table 11-29. Register Settings (Bank-Based Interleaving)
Register
Settings
EMEMC0
BRx
BA Base address
PS00 = 64-bit port size
DECC00
ATOM00
DR0
WP0
V 1
MS010 = SDRAM-60x bus
ORx
SDAM1111_1100_0000
LSDAM00000
BPD01
NUMR011
PMSEL0
IBID0
ROWST010
PSDMR
PBI0
RFEN1
ACTTOROWfrom device data sheet
BL0
OP000
SDAM001
BSMA010
LDOTOPREfrom device data sheet
WRC from device data sheet
EAMUX0
SDA10011
BUFCMD0
RFRC from device data sheet
PRETOACT from device data sheet
CL from device data sheet
11.5 General-Purpose Chip-Select Machine (GPCM)
Users familiar with the MPC8xx memory controller should read Section 11.5.4, “Differences between
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11-51
Memory Controller
The GPCM allows a glueless and flexible interface between the PowerQUICC II, SRAM, EPROM,
FEPROM, ROM devices, and external peripherals. The GPCM contains two basic configuration register
groups—BRx and ORx.
Although GPCM does not support bursting, the internal logic will split a burst into individual beats that
the GPCM can support. Therefore, the flash can be cached. Note that if the PowerQUICC II is in 60x-bus
compatible mode, baddr[27–31] should be used instead of a[27–31].
Table 11-30 lists the GPCM interface signals on the 60x and local bus
Table 11-30. GPCM Interfaces Signals
60x Bus
Local Bus
Comments
CS[0–11]
Device select
PWE[0–7]
POE
LWE[0–3]
LOE
Write enables for write cycles
Output enable for read cycles
GPCM-controlled devices can use BCTLx as read/write indicators. The BCTLx signals appears as R/W in
Additional control is available in 60x-compatible mode (60x bus only)—ALE–external address latch
enable
In this section, the output-enable and write-enable signals are generically labeled OE and WE. When using
the 60x bus they refer to POE and PWE, and for the local bus they refer to LOE and LWE.
Figure 11-40 shows a simple connection between a 32-bit port size SRAM device and the
PowerQUICC II.
32-Bit Wide SRAM
PowerQUI
CSx
CE
128K
WE[0–3]
GPL_x1/OE
A[15–29]
WE[0–3]
OE
Address
Data
D[0–31]
Figure 11-40. GPCM-to-SRAM Configuration
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Memory Controller
11.5.1 Timing Configuration
If BRx[MS] selects the GPCM, the attributes for the memory cycle are taken from ORx. These attributes
behavior and system response.
Table 11-31. GPCM Strobe Signal Behavior
Option Register Attributes
TRLX Access ACS CSNT
Signal Behavior
Address to CS
Asserted
CS Negated to
WE Negated to
Total Cycles
Address Change
Address/Data Invalid
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
Read
Read
Read
Write
Write
Write
Write
Write
Write
Read
Read
Read
Write
Write
Write
Write
Write
Write
00
10
11
00
10
11
00
10
11
00
10
11
00
10
11
00
10
11
x
x
x
0
0
0
1
1
1
x
x
x
0
0
0
1
1
1
0
0
x
2+SCY
1/4*Clock
1/2*Clock
0
0
x
2+SCY
2+SCY
0
x
0
0
2+SCY
1/4*Clock
1/2*Clock
0
0
0
2+SCY
0
0
2+SCY
0
-1/4*Clock
2+SCY
1/4*Clock
1/2*Clock
0
-1/4*Clock
-1/4*Clock
2+SCY
-1/4*Clock
-1/4*Clock
2+SCY
0
x
2+2*SCY
3+2*SCY
3+2*SCY
2+2*SCY
3+2*SCY
3+2*SCY
3+2*SCY
4+2*SCY
4+2*SCY
(1+1/4)*Clock
(1+1/2)*Clock
0
0
x
0
x
0
0
(1+1/4)*Clock
(1+1/2)*Clock
0
0
0
0
0
0
-1-1/4*Clock
-1-1/4*Clock
-1-1/4*Clock
(1+1/4)*Clock
(1+1/2)*Clock
-1-1/4*Clock
-1-1/4*Clock
1
SCY is the number of wait cycles from the option register.
11.5.1.1 Chip-Select Assertion Timing
From 0 to 30 wait states can be programmed for PSDVAL generation. Byte-write enable signals (WE) are
available for each byte written to memory. Also, the output enable signal (OE) is provided to eliminate
external glue logic. The memory banks selected to work with the GPCM have unique features. On system
reset, a global (boot) chip-select is available that provides a boot ROM chip-select prior to the system
being fully configured. The banks selected to work with the GPCM support an option to output the CS line
at different timings with respect to the external address bus. CS can be output in any of three
configurations:
•
Simultaneous with the external address
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•
•
One quarter of a clock cycle later
One half of a clock cycle later
Note the GPCM does not negate CS in back-to-back reads to the same device when in single
PowerQUICC II bus mode or in 60x-compatible bus mode with extended transfers enabled. When in strict
60x bus mode, however, the GPCM does negate CS in back-to-back reads. See Section 4.3.2.1, “Bus
Figure 11-41 shows a basic connection between the PowerQUICC II and an external peripheral device.
Here, CS (the strobe output for the memory access) is connected directly to CE of the memory device and
BCTL0 is connected to the respective R/W in the peripheral device.
PowerQUI
Peripheral
Address
Address
CS
BCTL0
Data
CE
R/W
Data
Figure 11-41. GPCM Peripheral Device Interface
Figure 11-42 shows CS as defined by the setup time required between the address lines and CE. The user
can configure ORx[ACS] to specify CS to meet this requirement.
Clock
Address
PSDVAL
ACS = 11
ACS = 10
CS
R/W(BCTL0)
Data
Figure 11-42. GPCM Peripheral Device Basic Timing (ACS = 1x and TRLX = 0)
11.5.1.2 Chip-Select and Write Enable Deassertion Timing
Figure 11-43 shows a basic connection between the PowerQUICC II and a static memory device. Here,
CS is connected directly to CE of the memory device. The WE signals are connected to the respective W
signal in the memory device where each WE corresponds to a different data byte.
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MEMORY
Address
PowerQUICC II
Address
CS
CE
OE
W
OE
WE
Data
Data
Figure 11-43. GPCM Memory Device Interface
transaction are supplied by OE or WE, depending on the transaction direction (read or write). ORx[CSNT]
controls the timing for the appropriate strobe negation in write cycles. When this attribute is asserted, the
strobe is negated one quarter of a clock before the normal case. For example, when ACS = 00 and CSNT
Clock
Address
PSDVAL
CS
CSNT = 1
WE
OE
Data
Figure 11-44. GPCM Memory Device Basic Timing (ACS = 00, CSNT = 1, TRLX = 0)
When ACS ≠ 00 and CSNT = 1, WE and CS are negated one quarter of a clock earlier, as shown in
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Clock
Address
PSDVAL
ACS = 11
ACS = 10
CS
WE
CSNT = 1
Data
Figure 11-45. GPCM Memory Device Basic Timing (ACS ≠ 00, CSNT = 1, TRLX = 0)
11.5.1.3 Relaxed Timing
ORx[TRLX] is provided for memory systems that require more relaxed timing between signals. When
TRLX = 1 and ACS ≠ 00, an additional cycle between the address and strobes is inserted by the
Clock
Address
PSDVAL
CS
ACS = 10
ACS = 11
BCTLx
WE
OE
Data
Figure 11-46. GPCM Relaxed Timing Read (ACS = 1x, SCY = 1, CSNT = 0, TRLX = 1)
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Clock
Address
PSDVAL
CS
ACS = 10
ACS = 11
BCTLx
WE
OE
Data
Figure 11-47. GPCM Relaxed-Timing Write (ACS = 1x, SCY = 0, CSNT = 0,TRLX = 1)
When TRLX and CSNT are set in a write-memory access, the strobe lines, WE[0–7] are negated one clock
earlier than in the normal case. If ACS ≠ 0, CS is also negated one clock earlier, as shown in Figure 11-48
TRLX = 1), the memory controller does not support external devices that provide PSDVAL to complete
the transfer with zero wait states. The minimum access duration in this case is three clock cycles.
Clock
Address
CSNT = 1
PSDVAL
CS
ACS = 10
BCTLx
WE
OE
Data
Figure 11-48. GPCM Relaxed-Timing Write (ACS = 10, SCY = 0, CSNT = 1, TRLX = 1)
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Clock
Address
PSDVAL
CS
BCTLx
WE
OE
Data
Figure 11-49. GPCM Relaxed-Timing Write (ACS = 00, SCY = 0, CSNT = 1, TRLX = 1)
11.5.1.4 Output Enable (OE) Timing
The timing of the OE is affected only by TRLX. It always asserts and negates on the rising edge of the
external bus clock. OE always asserts on the rising clock edge after CS is asserted, and therefore its
assertion can be delayed (along with the assertion of CS) by programming TRLX = 1. OE deasserts on the
rising clock edge coinciding with or immediately after CS deassertion.
11.5.1.5 Programmable Wait State Configuration
The GPCM supports internal PSDVAL generation. It allows fast accesses to external memory through an
internal bus master or a maximum 17-clock access by programming ORx[SCY]. The internal PSDVAL
generation mode is enabled if ORx[SETA] = 0. If GTA is asserted externally at least two clock cycles
before the wait state counter has expired, the current memory cycle is terminated. When TRLX = 1, the
number of wait states inserted by the memory controller is defined by 2 x SCY or a maximum of 30 wait
states.
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11.5.1.6 Extended Hold Time on Read Accesses
Slow memory devices that take a long time to turn off their data bus drivers on read accesses should choose
some combination of ORx[29–30] (TRLX and EHTR). Any access following a read access to the slower
Table 11-32. TRLX and EHTR Combinations
ORx[TRLX] ORx[EHTR] Number of Hold Time Clock Cycles
0
0
1
1
0
1
0
1
0
1
4
8
Clock
Address
PSDVAL
CSx
CSy
BCTLx
OE
Data
Figure 11-50. GPCM Read Followed by Read (ORx[29–30] = 00, Fastest Timing)
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Clock
Address
PSDVAL
CSx
CSy
BCTLx
OE
Data
Hold Time
1-cycle hold time allowed
Figure 11-51. GPCM Read Followed by Read (ORx[29–30] = 01)
Clock
Address
PSDVAL
CSx
CSy
BCTLx
OE
Data
Hold Time
Long hold time allowed
Figure 11-52. GPCM Read Followed by Write (ORx[29–30] = 01)
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Clock
Address
PSDVAL
CSx
CSy
BCTLx
OE
Data
Hold Time
Figure 11-53. GPCM Read Followed by Write (ORx[29–30] = 10)
11.5.2 External Access Termination
External access termination is supported by the GPCM using GTA, which is synchronized and sampled
internally by the PowerQUICC II. If, during a GPCM data phase (second cycle or later), the sampled signal
is asserted, it is converted to PSDVAL, which terminates the current GPCM access. GTA should be
asserted for one cycle. Note that because GTA is synchronized, bus termination may occur three cycles
after GTA assertion, so in case of read cycle, the device still must output data as long as OE is asserted.
The user selects whether PSDVAL is generated internally or externally (by means of GTA assertion) by
resetting/setting ORx[SETA].
access even if ORx[SETA] = 0 (internal PSDVAL generation).
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Clock
Address
BCTLx
CS
OE
D
GTA
PSDVAL
Figure 11-54. External Termination of GPCM Access
11.5.3 Boot Chip-Select Operation
Boot chip-select operation allows address decoding for a boot ROM before system initialization. The CS0
signal is the boot chip-select output; its operation differs from the other external chip-select outputs on
system reset. When the PowerQUICC II internal core begins accessing memory at system reset, CS0 is
asserted for every address in the boot address range, unless an internal register is accessed. The address
range is configured during reset.
The boot chip-select also provides a programmable port size during system reset by using the
configuration mechanism described in Section 5.4, “Reset Configuration.” The boot chip-select does not
provide write protection. CS0 operates this way until the first write to OR0 and it can be used as any other
chip-select register once the preferred address range is loaded into BR0. After the first write to OR0, the
boot chip-select can be restarted only on hardware reset. Table 11-33 describes the initial values of the boot
bank in the memory controller.
Table 11-33. . Boot Bank Field Values after Reset
Register
Setting
BR0
DECC0
WP0
MS000
V 1
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Table 11-33. . Boot Bank Field Values after Reset (continued)
Setting
Register
OR0
AM1111_1110_0000_0000_0 (32 MByte)
BCTLD0
CSNT1
ACS11
SCY1111
SETA0
TRLX1
EHTR0
11.5.4 Differences between MPC8xx’s GPCM and MPC82xx’s GPCM
Users familiar with the MPC8xx GPCM should read this section first:
•
External termination—In the MPC8xx the external termination connects to the external bus TA and
so must be asserted in sync with the system clock. In the PowerQUICC II, this signal is separated
from the bus and named GTA. The signal is synchronized internally and sampled. The sampled
signal is used to generate TA, which terminates the bus transaction.
•
Extended hold time for reads can be up to 8 clock cycles (instead of 1 in the MPC8xx).
11.6 User-Programmable Machines (UPMs)
Users familiar with MPC8xx memory controller should first read Section 11.6.6, “Differences between
Table 11-34. UPM Interfaces Signals
60x Bus
Local Bus
Comments
CS[0–11]
Device select
Byte Select
PBS[0–7]
PGPL_0
PGPL_1
PGPL_2
PGPL_3
LBS[0–3]
LGPL_0
General-purpose line 0
General-purpose line 1
General-purpose line 2
General-purpose line 3
General-purpose line 4/UPM wait
General-purpose line 5
LGPL_1
LGPL_2
LGPL_3
PGPL_4/UPMWAIT
PGPL_5
LGPL_4/UPMWAIT
LGPL_5
Additional control is available in 60x-compatible mode (60x bus only) using the external address latch
enable (ALE). However, ALE is not a UPM-controlled signal; it toggles with chip select signals.
Note that in this section, when a signal is named, the reference is to the 60x or local bus signal, according
to the bank being accessed.
The three user-programmable machines (UPMs) are flexible interfaces that connect to a wide range of
memory devices. At the heart of each UPM is an internal-memory RAM array that specifies the logical
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value driven on the external memory controller pins for a given clock cycle. Each word in the RAM array
provides bits that allow a memory access to be controlled with a resolution of up to one quarter of the
external bus clock period on the byte-select and chip-select lines. Figure 11-55 shows the basic operation
of each UPM. The following events initiate a UPM cycle:
•
Any internal or external device requests an external memory access to an address space mapped to
a chip-select serviced by the UPM
•
•
A UPM refresh timer expires and requests a transaction, such as a DRAM refresh
A transfer error or reset generates an exception request
Internal/external
memory access request
UPM refresh
timer request
Array
Index
Generator
Index
RAM Array
RUN command
(issued in software)
Exception request
Increment
Index
(LAST = 0)
Wait
Request
Logic
Internal
Signals
Latch
Signals
Timing
Generator
Hold
UPMWAIT
WAEN Bit
GPLx, BS_x, CSx
Internal Controls
Figure 11-55. User-Programmable Machine Block Diagram
The RAM array contains 64 32-bit RAM words. The signal timing generator loads the RAM word from
the RAM array to drive the general-purpose lines, byte-selects, and chip-selects. If the UPM reads a RAM
word with WAEN set, the external UPMWAIT signal is sampled and synchronized by the memory
controller and the current request is frozen.
When a new access to external memory is requested by any device on the 60x or local bus, the addresses
of the transfer are compared to each one of the valid banks defined in the memory controller. When an
address match is found in one of the memory banks, BRx[MS] selects the UPM to handle this memory
access. MxMR[BSEL] assigns the UPM to the 60x or the local bus.
Note that 60x bus accesses that hit a bank allocated to the local bus are transferred to the local bus.
However, local bus accesses that hit a bank allocated to the 60x bus are ignored.
11.6.1 Requests
An internal or external device’s request for a memory access initiates one of the following patterns
(MxMR[OP] = 00):
•
Read single-beat pattern (RSS)
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•
•
•
Read burst cycle pattern (RBS)
Write single-beat pattern (WSS)
Write burst cycle pattern (WBS)
A UPM refresh timer request pattern initiates a refresh timer pattern (PTS), as described in
An exception (caused by a soft reset or the assertion of TEA) occurring while another UPM pattern is
running initiates an exception condition pattern (EXS).
A special pattern in the RAM array is associated with each of these cycle type. Figure 11-56 shows the
start addresses of these patterns in the UPM RAM, according to cycle type. RUN commands (MxMR[OP]
= 11), however, can initiate patterns starting at any of the 64 UPM RAM words.
Array Index
Generator
RSS
Read Single-Beat Request
RBS
Read Burst Request
WSS
Write Single-Beat Request
Write Burst Request
64 RAM
Words
RAM Array
WBS
PTS
EXS
Refresh Timer Request
Exception Condition Request
Figure 11-56. RAM Array Indexing
Table 11-35 show the start address of each pattern.
Table 11-35. UPM Routines Start Addresses
UPM Routine Routine Start Address
Read single-beat (RSS)
0x00
0x08
0x18
0x20
0x30
0x3C
Read burst (RBS)
Write single-beat (WSS)
Write burst (WBS)
Refresh timer (PTS)
Exception condition (EXS)
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11.6.1.1 Memory Access Requests
When an internal device requests a new access to external memory, the address of transfer is compared to
each valid bank defined in BRx. The value in BRx[MS] selects the UPM to handle the memory access. The
user must ensure that the UPM is appropriately initialized before a request.
The UPM supports two types of memory reads and writes:
•
A single-beat transfer transfers one operand consisting of up to double word. A single-beat cycle
starts with one transfer start and ends with one transfer acknowledge.
•
A burst transfer transfers four double words. For 64-bit accesses, the burst cycle starts with one
transfer start but ends after four transfer acknowledges. A 32-bit device requires 8 data
The PowerQUICC II defines two additional transfer sizes: bursts of two and three doublewords. These
accesses are treated by the UPM as back-to-back, single-beat transfers.
11.6.1.2 UPM Refresh Timer Requests
Each UPM contains a refresh timer that can be programmed to generate refresh service requests of a
timer request generation. PURT defines the period for the timers associated with UPMx on the 60x bus and
PTP Prescaling
60x bus assigned UPM
refresh timer request
Bus
Clock
Divide by PURT
Divide by LURT
Local bus assigned UPM
refresh timer request
Figure 11-57. Memory Refresh Timer Request Block Diagram
All 60x bus refreshes are done using the refresh pattern of UPMA. This means that if refresh is required
on the 60x bus, UPMA must be assigned to the 60x bus and MAMR[RFEN] must be set. It also means that
only one refresh routine should be programmed for the 60x bus and be placed in UPMA, which serves as
the 60x bus refresh executor. If refresh is not required on the 60x bus, UPMA can be assigned to any bus.
All local bus refreshes are done using the refresh pattern of UPMB. This means that if refresh is required
on the local bus, UPMB must be assigned to the local bus and MBMR[RFEN] must be set. It also means
that only one refresh routine should be programmed for the local bus, and be placed in UPMB, which
serves as the local bus refresh executor. If refresh is not required on the local bus, UPMB can be assigned
to any bus.
UPMC can be assigned to any bus; there is no need to program its refresh routine because it will use the
one in UPMA or UPMB, according to the bus to which it is assigned.
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11.6.1.3 Software Requests—RUN Command
Software can start a request to the UPM by issuing a RUN command to the UPM. Some memory devices
have their own signal handshaking protocol to put them into special modes, such as self-refresh mode.
Other memory devices require special commands to be issued on their control signals, such as for SDRAM
initialization.
For these special cycles, the user creates a special RAM pattern that can be stored in any unused areas in
the UPM RAM. Then the RUN command is used to run the cycle. The UPM runs the pattern beginning at
the specified RAM location until it encounters a RAM word with its LAST bit set. The RUN command is
issued by setting MxMR[OP] = 11 and accessing the UPMx memory region with a single-byte transaction.
Note that the pattern must contain exactly one assertion of PSDVAL (UTA bit in the RAM word, described
11.6.1.4 Exception Requests
When the PowerQUICC II under UPM control initiates an access to a memory device, the external device
may assert TEA or SRESET. The UPM provides a mechanism by which memory control signals can meet
the timing requirements of the device without losing data. The mechanism is the exception pattern that
defines how the UPM deasserts its signals in a controlled manner.
11.6.2 Programming the UPMs
The UPM is a microsequencer that requires microinstructions or RAM words to generate signal timings
for different memory cycles. Follow these steps to program the UPMs:
1. Set up BRx and ORx.
2. Write patterns into the RAM array.
3. Program MPTPR and L/PURT if refresh is required.
4. Program the machine mode register (MxMR).
Patterns are written to the RAM array by setting MxMR[OP] = 01 and accessing the UPM with a single
11.6.3 Clock Timing
Fields in the RAM word specify the value of the various external signals at each clock edge. The signal
timing generator causes external signals to behave according to the timing specified in the current RAM
integer and non-integer clock ratios. The clock phases shown reflect timing windows during which
generated signals can change state. If specified in the RAM, the value of the external signals can be
changed after any of the positive edges of T[1–4], plus a circuit delay time as specified in the Hardware
Specifications.
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NOTE
For integer clock ratios, the widths of T1/2/3/4 are equal, for a 1:2.5 clock
ratio, T1 = 4/3*T2 and T3 = 4/3*T4, and for a 1:3.5 clock ratio, the ticks
widths are T1 = 3/2*T2 and T3 = 3/2*T4.
CLKIN
T1
T2
T3
T4
Figure 11-58. Memory Controller UPM Clock Scheme for Integer Clock Ratios
CLKIN
T1
T2
T3
T4
Figure 11-59. Memory Controller UPM Clock Scheme for Non-Integer (2.5:1/3.5:1) Clock Ratios
The state of the external signals may change (if specified in the RAM array) at any positive edge of T1,
T2, T3, or T4 (there is a propagation delay specified in the Hardware Specifications). Note however that
only the CS signal corresponding to the currently accessed bank is manipulated by the UPM pattern when
it runs. The BS signal assertion and negation timing is also specified for each cycle in the RAM word;
which of the four BS signals are manipulated depends on the port size of the specified bank, the external
address accessed, and the value of TSIZn. The GPL lines toggle as programmed for any access that
initiates a particular pattern, but resolution of control is limited to T1 and T3.
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Figure 11-60 shows how CSx, GPL1, and GPL2 can be controlled. A word is read from the RAM that
specifies on every clock cycle the logical bits CST1, CST2, CST3, CST4, G1T1, G1T3, G2T1, and G2T3.
These bits indicate the electrical value for the corresponding output pins at the appropriate timing.
CLKIN
T1
T2
T3
T4
CSx
GPL1
GPL2
CST1 CST2 CST3 CST4
CST1 CST2 CST3 CST4
G1T1
G2T1
G1T3
G2T3
G1T1
G2T1
G1T3
G2T3
Word 1
Word 2
Figure 11-60. UPM Signals Timing Example
11.6.4 The RAM Array
The RAM array for each UPM is 64 locations deep and 32 bits wide, as shown in Figure 11-61. The signals
at the bottom of Figure 11-61. are UPM outputs. The selected CS is for the bank that matches the current
address. The selected BS is for the byte lanes read or written by the access.
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32 Bits
RAM Array
64
T1, T2, T3, T4
Current Bank
External Signals Timing Generator (60x or Local)
TSIZ, PS, A[30,31]
CS Line
Selector
Byte Select
Packaging
CS[0–11]
BS
GPL0 GPL1 GPL2 GPL3 GPL4 GPL5
Figure 11-61. RAM Array and Signal Generation
11.6.4.1 RAM Words
The RAM word, shown in Figure 11-62, is a 32-bit microinstruction stored in one of 64 locations in the
RAM array. It specifies timing for external signals controlled by the UPM.
0
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
Field CST1 CST2 CST3 CST4 BST1 BST2 BST3 BST4
G0L
G0H G1T1 G1T3 G2T1 G2T3
Reset
R/W
—
R/W
Addr
(MCR[MAD] indirect addressing of 1 of 64 entries
16
17
18
19
20
21
22
23
24
25
26 27
28
29
30
31
Field G3T1 G3T3 G4T1/ G4T3/ G5T1 G5T3
DLT3 WAEN
REDO
LOOP EXEN AMX
NA UTA TODT LAST
Reset
R/W
—
R/W
Addr
(All 32 bits of the RAM word are addressed as shown in the address row above.)
Figure 11-62. The RAM Word
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Table 11-36 describes RAM word fields.
Table 11-36. RAM Word Bit Settings
Bit
Name
Description
0
CST1 Chip-select timing 1. Defines the state of CS during clock phase 1.
0 The value of the CS line at the rising edge of T1 will be 0
1 The value of the CS line at the rising edge of T1 will be 1
1
2
3
4
CST2 Chip-select timing 2. Defines the state of CS during clock phase 2.
0 The value of the CS line at the rising edge of T2 will be 0
1 The value of the CS line at the rising edge of T2 will be 1
CST3 Chip-select timing 3. Defines the state of CS during clock phase 3.
0 The value of the CS line at the rising edge of T3 will be 0
1 The value of the CS line at the rising edge of T3 will be 1
CST4 Chip-select timing4. Defines the state of CS during clock phase 4.
0 The value of the CS line at the rising edge of T4 will be 0
1 The value of the CS line at the rising edge of T4 will be 1
BST1 Byte-select timing 1. Defines the state of BS during clock phase 1.
0 The value of the BS lines at the rising edge of T2 will be 0
1 The value of the BS lines at the rising edge of T2 will be 1
The final value of the BS lines depends on the values of BRx[PS], the TSIZ lines, and A[30–31] for
5
6
BST2 Byte-select timing 2. Defines the state of BS during clock phase 2.
0 The value of the BS lines at the rising edge of T2 will be 0
1 The value of the BS lines at the rising edge of T2 will be 1
The final value of the BS lines depends on the values of BRx[PS], TSIZx, and A[30–31] for the
access.
BST3 Byte-select timing 3. Defines the state of BS during clock phase 3.
0 The value of the BS lines at the rising edge of T3 will be 0
1 The value of the BS lines at the rising edge of T3 will be 1
The final value of the BS lines depends on the values of BRx[PS], TSIZx, and A[30–31] for the
access.
7
BST4 Byte-select timing 4. Defines the state of BS during clock phase 4.
0 The value of the BS lines at the rising edge of T4 will be 0
1 The value of the BS lines at the rising edge of T4 will be 1
The final value of the BS lines depends on the values of BRx[PS], TSIZx, and A[30–31] for the
access.
8–9
10–11
G0L General-purpose line 0 lower. Defines the state of GPL0 during phases 1–2.
00 The value of GPL0 at the rising edge of T1 is as defined in MxMR[G0CL]
10 The value of the GPL0 line at the rising edge of T1 will be 0
11 The value of the GPL0 line at the rising edge of T1 will be 1
G0H General-purpose line 0 higher. Defines the state of GPL0 during phase 3–4.
00 The value of GPL0 at the rising edge of T3 is as defined in MxMR[G0CL]
10 The value of the GPL0 line at the rising edge of T3 will be 0
11 The value of the GPL0 line at the rising edge of T3 will be 1
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Table 11-36. RAM Word Bit Settings (continued)
Description
Bit
Name
12
G1T1 General-purpose line 1 timing 1. Defines the state of GPL1 during phase 1–2.
0 The value of the GPL1 line at the rising edge of T1 will be 0
1 The value of the GPL1 line at the rising edge of T1 will be 1
13
14
15
16
17
18
G1T3 General-purpose line 1 timing 3. Defines the state of GPL1 during phase 3–4.
0 The value of the GPL1 line at the rising edge of T3 will be 0
1 The value of the GPL1 line at the rising edge of T3 will be 1
G2T1 General-purpose line 2 timing 1. Defines the state of GPL2 during phase 1–2.
0 The value of the GPL2 line at the rising edge of T1 will be 0
1 The value of the GPL2 line at the rising edge of T1 will be 1
G2T3 General-purpose line 2 timing 3. Defines the state of GPL2 during phase 3–4.
0 The value of the GPL2 line at the rising edge of T3 will be 0
1 The value of the GPL2 line at the rising edge of T3 will be 1
G3T1 General-purpose line 3 timing 1. Defines the state of GPL3 during phase 1–2.
0 The value of the GPL3 line at the rising edge of T1 will be 0
1 The value of the GPL3 line at the rising edge of T1 will be 1
G3T3 General-purpose line 3 timing 3. Defines the state of GPL3 during phase 3–4.
0 The value of the GPL3 line at the rising edge of T3 will be 0
1 The value of the GPL3 line at the rising edge of T3 will be 1
G4T/
DLT2
General-purpose line 4 timing 1/delay time 2. The function is determined by MxMR[GPLx4DIS].
G4T1 If MxMR defines UPMWAITx/GPL_x4 as an output (GPL_x4), this bit functions as G4T1:
0 The value of the GPL4 line at the rising edge of T1 will be 0
1 The value of the GPL4 line at the rising edge of T1 will be 1
DLT3 If MxMR[GPLx4DIS] = 1, UPMWAITx is chosen and this bit functions as DLT3.
0 In the current word, indicates that the data bus should be sampled at the rising edge of T1 (if a
read burst or a single read service is executed).
1 In the current word, indicates that the data bus should be sampled at the rising edge of T3 (if a
read burst or a single read service is executed).
19
G4T3/ General-purpose line 4 timing 3/wait enable. Function depends on the value of MxMR[GPLx4DIS].
AEN
W
G4T3 If MxMR[GPLx4DIS] = 0, G4T3 is selected.
0 The value of the GPL4 line at the rising edge of T3 will be 0
1 The value of the GPL4 line at the rising edge of T3 will be 1
0 The UPMWAITx function is disabled.
1 A freeze in the external signal’s logical value occurs if the external wait signal is detected
asserted. This condition lasts until UPMWAITx is negated.
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Table 11-36. RAM Word Bit Settings (continued)
Description
Bit
Name
20
G5T1 General-purpose line 5 timing 1. Defines the state of GPL5 during phase 1–2.
0 The value of the GPL5 line at the rising edge of T1 will be 0
1 The value of the GPL5 line at the rising edge of T1 will be 1
21
G5T3 General-purpose line 5 timing 3. Defines the state of GPL5 during phase 3–4.
0 The value of the GPL5 line at the rising edge of T3 will be 0
1 The value of the GPL5 line at the rising edge of T3 will be 1
(REDO).”
00 Normal operation
01 The current RAM word is executed twice.
10 The current RAM word is executed tree times.
11 The current RAM word is executed four times.
Note: For Rev A.1 and forward: for any value other than 00, do not use REDO on two consecutive
CPM RAM words. The second word will not execute.
24
25
LOOP Loop. The first RAM word in the RAM array where LOOP is 1 is recognized as the loop start word.
The next RAM word where LOOP is 1 is the loop end word. RAM words between the start and end
are defined as the loop. The number of times the UPM executes this loop is defined in the
corresponding loop field of the MxMR.
0 The current RAM word is not the loop start word or loop end word.
1 The current RAM word is the start or end of a loop.
EXEN Exception enable. If an external device asserts TEA or RESET, EXEN allows branching to an
exception pattern at the exception start address (EXS) at a fixed address in the RAM array.
When the PowerQUICC II under UPM control begins accessing a memory device, the external
device may assert TEA or SRESET. An exception occurs when one of these signals is asserted by
an external device and the PowerQUICC II begins closing the memory cycle transfer. When one of
these exceptions is recognized and EXEN in the RAM word is set, the UPM branches to the special
exception start address (EXS) and begins operating as the pattern defined there specifies. See
Table 11-35.. The user should provide an exception pattern to deassert signals controlled by the
UPM in a controlled fashion. For DRAM control, a handler should negate RAS and CAS to prevent
data corruption. If EXEN = 0, exceptions are deferred and execution continues. After the UPM
branches to the exception start address, it continues reading until the LAST bit is set in the RAM
word.
0 The UPM continues executing the remaining RAM words.
1 The current RAM word allows a branch to the exception pattern after the current cycle if an
exception condition is detected. The exception condition can be an external device asserting TEA
or SRESET.
26–27
AMX Address multiplexing. Determines the source of A[0–31] at the rising edge of t1
00 A[0–31] is the non-multiplexed address. For example, column address.
01 Reserved.
10 A[0–31] is the address requested by the internal master multiplexed according to MxMR[AMx].
For example, row address.
11 A[0–31] is the contents of MAR. Used for example, during SDRAM mode initialization.
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Table 11-36. RAM Word Bit Settings (continued)
Description
Bit
Name
NA
28
Next address. Determines when the address is incremented during a burst access.
0 The address increment function is disabled
1 The address is incremented in the next cycle. In conjunction with the BRx[PS], the increment
value of A[27–31] and/or BADDR[27–31] at the rising edge of T1 is as follows
If the accessed bank has a 64-bit port size, the value is incremented by 8.
If the accessed bank has a 32-bit port size, the value is incremented by 4.
If the accessed bank has a 16-bit port size, the value is incremented by 2.
If the accessed bank has an 8-bit port size, the value is incremented by 1.
Note: The value of NA is relevant only when the UPM serves a burst-read or burst-write request. NA
is reserved under other patterns.
29
30
UTA UPM transfer acknowledge. Indicates assertion of PSDVAL, sampled by the bus interface in the
current cycle.
0 PSDVAL is not asserted in the current cycle.
1 PSDVAL is asserted in the current cycle.
TODT Turn-on disable timer. The disable timer associated with each UPM allows a minimum time to be
guaranteed between two successive accesses to the same memory bank. This feature is critical
when DRAM requires a RAS precharge time. TODT, turns the timer on to prevent another UPM
access to the same bank until the timer expires.The disable timer period is determined in
MxMR[DSx]. The disable timer does not affect memory accesses to different banks.
0 The disable timer is turned off.
1 The disable timer for the current bank is activated preventing a new access to the same bank
(when controlled by the UPMs) until the disable timer expires. For example, precharge time.
Note: TODT must be set together with LAST. Otherwise it is ignored.
31
LAST Last. If this bit is set, it is the last RAM word in the program. When the LAST bit is read in a RAM
word, the current UPM pattern terminates and the highest priority pending UPM request (if any) is
serviced immediately in the external memory transactions. If the disable timer is activated and the
next access is top the same bank, the execution of the next UPM pattern is held off for the number
of clock cycles specified in MxMR[DSx].
0 The UPM continues executing RAM words.
1 The service to the UPM request is done.
Additional information about some of the RAM word fields is provided in the following sections.
11.6.4.1.1 Chip-Select Signals (CxTx)
If BRx[MS] of the accessed bank selects a UPM on the currently requested cycle the UPM manipulates
the CS signal for that bank with timing as specified in the UPM RAM word. The selected UPM affects
only assertion and negation of the appropriate CS signal. The state of the selected CSx signal of the
corresponding bank depends on the value of each CSTn bit.
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Bank Selected
CS0
CS1
CS2
CS3
CS4
CS5
CS6
CS7
CS8
CS9
CS10
CS11
Switch
UPMA/B/C
SDRAM
GPCM
BRx[MS]
MUX
Figure 11-63. CS Signal Selection
11.6.4.1.2
Byte-Select Signals (BxTx)
BRx[MS] of the accessed memory bank selects a UPM on the currently requested cycle. The selected UPM
affects only the assertion and negation of the appropriate BS signal; its timing as specified in the RAM
word. The BS signals are controlled by the port size of the accessed bank, the transfer size of the
Bank Selected
A[29–31]
TSIZ
MS/BS
MUX
BRx[PS]
BS0
BS1
BS2
BS3
BS4
BS5
BS6
BS7
UPMA
UPMB
UPMC
Byte-Select
Logic
Figure 11-64. BS Signal Selection
The uppermost byte select (BS0) indicates that D[0–7] contains valid data during a cycle. Likewise, BS1
indicates that D[8–15] contains valid data, BS2 indicates that D[16–23] contains valid data, and BS3
indicates that D[24–31] contains valid data during a cycle, and so forth. Note that for a refresh timer
request, all the BS signals are asserted/negated by the UPM.
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11.6.4.1.3
General-Purpose Signals (GxTx, GOx)
The general-purpose signals (GPL[1–5]) each have two bits in the RAM word that define the logical value
of the signal to be changed at the rising edge of T1 and/or at the rising edge of T3. GPL0 offer
enhancements beyond the other GPLx lines.
GPL0 can be controlled by an address line specified in MxMR[G0CLx]. To use this feature, set G0H and
G0L in the RAM word. For example, for a SIMM with multiple banks, this address line can be used to
switch between banks.
11.6.4.1.4
Loop Control
The LOOP bit in the RAM word (bit 24) specifies the beginning and end of a set of UPM RAM words that
are to be repeated. The first time LOOP = 1, the memory controller recognizes it as a loop start word and
loads the memory loop counter with the corresponding contents of the loop field shown in Table 11-37..
The next RAM word for which LOOP = 1 is recognized as a loop end word. When it is reached, the loop
counter is decremented by one.
Continued loop execution depends on the loop counter. If the counter is not zero, the next RAM word
executed is the loop start word. Otherwise, the next RAM word executed is the one after the loop end word.
Loops can be executed sequentially but cannot be nested.
Table 11-37. MxMR Loop Field Usage
Request Serviced
Loop Field
Read single-beat cycle
Read burst cycle
RLFx
RLFx
WLFx
WLFx
TLFx
RLFx
Write single-beat cycle
Write burst cycle
Refresh timer expired
RUN command
11.6.4.1.5
Repeat Execution of Current RAM Word (REDO)
The REDO function is useful for wait-state insertion in a long UPM routine that would otherwise need too
many RAM words. Setting the REDO bits of the RAM word to a nonzero value to cause the UPM to
Special care must be taken in the following cases:
•
When UTA and REDO are set together, PSDVAL is asserted the number of times specified by the
REDO function.
•
When LOOP and REDO are set together, the loop mechanism works as usual and the line is
repeated according to the REDO function.
•
•
LAST and REDO should not be set together.
REDO should not be used within the exception routine.
Figure 11-79 shows an example of REDO use.
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11.6.4.2 Address Multiplexing
The address lines can be controlled by the pattern the user provides in the UPM. The address multiplex
bits can choose between outputting an address requested by the internal master as is and outputting it
according to the multiplexing specified by the MxMR[AMx]. The last option is to output the contents of
the MAR on the address pins.
Note that in 60x-compatible mode, MAR cannot be output on the 60x bus external address line.
Note that on the local bus, only the lower 18 bits of the MAR are output.
Also, note that for the UPM address multiplexing to work, if the UPM is on the 60x bus, PSDMR[PBI]
needs to be zero. If the UPM is on the local bus, LSDMR[PBI] needs to be zero. This means that UPM
address multiplexing does not work when the SDRAM controller is on the same bus and PBI is set to one.
Table 11-38. UPM Address Multiplexing
External Bus
Address Pin
AMx
A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31
000
001
010
011
100
101
A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23
A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22
A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21
A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20
Signal Driven
on External
Pin when
Address
Multiplexing
—
—
A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19
A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18
is Enabled
—
11.6.4.3 Data Valid and Data Sample Control
When a read access is handled by the UPM and the UTA bit is 1, the value of the DLT3 bit in the same
RAM word indicates when the data input is sampled by the internal bus master, assuming that
MxMR[GPLx4DIS] = 1.
•
If G4T4/DLT3 functions as DLT3 and DLT3 = 1 in the RAM word, data is latched on the falling
edge of CLKIN instead of the rising edge. The data is sampled by the internal master on the next
rising edge as is required by the PowerQUICC II bus operation spec. This feature lets the user
speed up the memory interface by latching data 1/2 clock early, which can be useful during burst
reads. This feature should be used only in systems without external synchronous bus devices.
•
If G4T4/DLT3 functions as G4T4, data is latched on the rising edge of CLKIN, as is normal in
PowerQUICC II bus operation.
Figure 11-65 shows data sampling that is controlled by the UPM.
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M
U
L
T
I
To internal
data bus
P
L
E
X
E
R
Data Bus
CLKIN
UPMx selected to handle the transfer
AND
(GPL4xDIS = 1) and RD/WR and DLT2x
Figure 11-65. UPM Read Access Data Sampling
11.6.4.4 Signals Negation
When the LAST bit is read in a RAM word, the current UPM pattern terminates. On the next cycle all the
UPM signals are negated unconditionally (driven to logic ‘1’).
This negation will not occur only if there is a back-to-back UPM request pending. In this case the signals
value on the cycle following the LAST bit, will be taken from the first line of the pending UPM routine.
11.6.4.5 The Wait Mechanism
mechanism in selected UPM RAM words. Note that the WAEN bit needs to be set in two consecutive UPM
words to get the desired operation.
If the UPM reads a RAM word with the WAEN bit set, the external UPMWAIT signal is sampled by the
memory controller in the following cycle and the request is frozen. The UPMWAIT signal is sampled at
the rising edge of CLKIN. If UPMWAIT is asserted and WAEN = 1 in the previous UPM word, the UPM
is frozen until UPMWAIT is negated. The value of the external pins driven by the UPM remains as
indicated in the previous word read by the UPM. When UPMWAIT is negated, the UPM continues its
normal functions. Note that during the wait cycles, the UPM negates PSDVAL.
to hold the UPM in a particular state until UPMWAIT is negated. As the example in Figure 11-66 shows,
the CSx and GPL1 states (C12 and F) and the WAEN value (C) are frozen until UPMWAIT is recognized
as deasserted. WAEN is typically set before the line that contain UTA = 1.
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CLKIN
T1
T2
T3
T4
CSx
GPL1
c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11
c12
c13 c14
D
A
B
C
PSDVAL
WAEN
UPMWAIT
Word n
Word n+1
Word n+2
Wait
Wait
Word n+3
Figure 11-66. Wait Mechanism Timing for Internal and External Synchronous Masters
11.6.4.6 Extended Hold Time on Read Accesses
Slow memory devices that take a long time to turn off their data bus drivers on read accesses should chose
some combination of ORx[EHTR]. Accesses after a read access to the slower memory bank is delayed by
the number of clock cycles specified by Table 11-32. The information in Section 11.5.1.6, “Extended Hold
11.6.5 UPM DRAM Configuration Example
Consider the following DRAM organization:
•
•
Eight 64Mbit devices, each organized as 8M x 8bits
Each device has 12 row lines and 9 column lines.
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Table 11-39. 60x Address Bus Partition
A[0–7]
A[8–19]
Row
A[20–28]
Column
A[29–31]
lsb
msb of start address
Table 11-40. DRAM Device Address Port during an ACTIVATE command
“A[0–16]”
—
A[17–28]
A[29–31]
n.c.
Row (A[8–19])
Table 11-41 shows the register configuration. Not shown are PURT and MPTPR, which should be
programmed according to the device refresh requirements.
Table 11-41. Register Settings
Register
Settings
BRx
BA msb of base address
PS 00 = 64-bit port size
DECC00
EMEMC0
ATOM00
DR 0
WP0
V
1
MS100 = UPMA
ORx
AM1111_1111_0000_0000_0 = 16 Mbyte
BI 0
EHTR0
MxMR
BSEL0 = 60x bus
RFEN1
OP 00
AM001
DSAAs needed
G0CLAN/A
GPL_A4DIS0
RLFAAs needed
WLFAAs needed
TLFAAs needed
MADN/A
11.6.6 Differences between MPC8xx UPM and MPC82xx UPM
Users familiar with the MPC8xx UPM should read this section first.
Below is a list of the major differences between the MPC8xx devices and the MPC82xx:
•
•
•
First cycle timing transferred to the UPM array—In the MPC8xx’s UPM, the first cycle value of
some of the signals is determined from ORx[SAM,G5LA,G5LS]. This is eliminated in the
PowerQUICC II. All signals are controlled only by the pattern written to the array.
Timing of GPL[0–5]—In the MPC8xx’s UPM, the GPL lines could change on the positive edge of
T2 or T3. In the PowerQUICC II these signals can change in the positive edge of T1 or T3 to allow
connection to high-speed synchronous devices such as burst SRAM.
UPM controlled signals negated at end of an access—In the MPC8xx’s UPM, if the user did not
negate the UPM signals at end of an access, those signals kept their previous value. In the
PowerQUICC II, all UPM signals are negated (CS,BS,GPL[0:4] driven to logic 1 and GPL5 driven
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to logic 0) at the end of that cycle, unless there is a back-to-back UPM cycle pending. In many cases
this allows the UPM routine to finish one cycle earlier because it is now possible and desired to
assert both UTA and LAST.
•
MCR is eliminated—In the PowerQUICC II, MCR is eliminated. The function of RAM read/write
and RUN is done via the MxMR.
•
•
UTA polarity is reversed—In the PowerQUICC II, UTA is active-high.
The disable timer control (TODT) and LAST bit in the RAM array word must be set together,
otherwise TODT is ignored.
•
Refresh timer value is in a separate register—In the PowerQUICC II, the refresh timer value has
moved to two registers, PURT and LURT, which can serve multiple UPMs.
•
•
•
•
Refresh on the 60x bus must be done in UPMA; on the local bus, it must be done in UPMB.
New feature: Repeated execution of the current RAM word (REDO).
Extended hold time on reads can be up to 8 clock cycles instead of 1 in the MPC8xx.
Each UPM on the MPC8xx has a wait signal. On the PowerQUICC II, the three UPMs share two
wait signals (PUPMWAIT and LUPMWAIT).
11.7 Memory System Interface Example Using UPM
Connecting the PowerQUICC II to a DRAM device requires a detailed examination of the timing diagrams
representing the possible memory cycles that must be performed when accessing this device. This section
provides timing diagrams for various UPM configurations.
PowerQUICC II
BS[0–7]
1M x 16
1M x 16
RAS
CS1
RAS
CAS[0–1]
W
CAS[0–1]
W
BCTL0
A[0–9]
A[0–9]
A[19–28]
D[0–15]
D[0–15
16
16
16
16
D[0–63]
D[0–15]
D[0–15]
RAS
RAS
CAS[0–1]
W
CAS[0–1]
W
A[0–9]
A[0–9]
1M x 16
1M x 16
Figure 11-67. DRAM Interface Connection to the 60x Bus (64-Bit Port Size)
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After timings are created, programming the UPM continues with translating these timings into tables
representing the RAM array contents for each possible cycle. When a table is completed, the global
parameters of the UPM must be defined for handling the disable timer (precharge) and the refresh timer
Table 11-42. UPMs Attributes Example
Explanation
Field
Value
Machine select UPMA
Port size 64-bit
BRx[MS]
BRx[PS]
0b100
0b00
0b0
No write protect (R/W)
BRx[WP]
Refresh timer value (1024 refresh cycles)
Refresh timer enable
PURT[PURT]
MxMR[RFEN]
MxMR[AMx]
MxMR[DSx]
0x0C
0b1
Address multiplex size
0b010
0b01
0b0
Disable timer period
Select between GPL4 and UPMWAIT = GPL4 data sample at clock rising edge MxMR[GPL_x4DIS]
Burst inhibit device ORx[BI]
0b0
The OR and BR of the specific bank must be initialized according to the address mapping of the DRAM
device used. The MS field should indicate the specific UPM selected to handle the cycle. The RAM array
of the UPM can than be written through use of the MxMR[OP] = 11. Figure 11-56 shows the first locations
addressed by the UPM, according to the different services required by the DRAM.
CLKIN
A
Row
Column 1
RD/WR
D
PSDVAL
CS1
(RAS)
BS
(CAS)
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cst1
cst2
cst3
cst4
bst1
bst2
bst3
bst4
g0l0
g0l1
g0h0
g0h1
g1t1
g1t3
g2t1
g2t3
g3t1
g3t3
g4t1
g4t3
g5t1
g5t3
redo[0]
redo[1]
loop
exen
amx0
amx1
na
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
Bit 16
Bit 17
Bit 18
Bit 19
Bit 20
Bit 21
Bit 22
Bit 23
Bit 24
Bit 25
Bit 26
Bit 27
Bit 28
Bit 29
Bit 30
Bit 31
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
uta
todt
last
RSS
RSS+1 RSS+2
Figure 11-68. Single-Beat Read Access to FPM DRAM
CLKIN
A
Row
Column 1
RD/WR
D
PSDVAL
CS1
(RAS)
BS
(CAS)
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cst1
cst2
cst3
cst4
bst1
bst2
bst3
bst4
g0l0
g0l1
g0h0
g0h1
g1t1
g1t3
g2t1
g2t3
g3t1
g3t3
g4t1
g4t3
g5t1
g5t3
redo[0]
redo[1]
loop
exen
amx0
amx1
na
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
0
0
0
1
0
0
0
1
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
Bit 16
Bit 17
Bit 18
Bit 19
Bit 20
Bit 21
Bit 22
Bit 23
Bit 24
Bit 25
Bit 26
Bit 27
Bit 28
Bit 29
Bit 30
Bit 31
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
uta
todt
last
WSS
WSS+1 WSS+2
Figure 11-69. Single-Beat Write Access to FPM DRAM
CLKIN
A
Row
Column 1
Column 2
Column 3
Column 4
RD/WR
D
PSDVAL
CS1
(RAS)
BS
(CAS)
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cst1
cst2
cst3
cst4
bst1
bst2
bst3
bst4
g0l0
g0l1
g0h0
g0h1
g1t1
g1t3
g2t1
g2t3
g3t1
g3t3
g4t1
g4t3
g5t1
g5t3
redo[0]
redo[1]
loop
exen
amx0
amx1
na
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
0
0
0
0
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
Bit 16
Bit 17
Bit 18
Bit 19
Bit 20
Bit 21
Bit 22
Bit 23
Bit 24
Bit 25
Bit 26
Bit 27
Bit 28
Bit 29
Bit 30
Bit 31
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
uta
todt
last
RBS
RBS+1 RBS+2 RBS+3 RBS+4 RBS+5 RBS+6 RBS+7 RBS+8
Figure 11-70. Burst Read Access to FPM DRAM (No LOOP)
CLKIN
A
Row
Column 1
Column 2
Column 3
Column 4
RD/WR
D
PSDVAL
CS1
(RAS)
BS
(CAS)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
11-85
Memory Controller
cst1
cst2
cst3
cst4
bst1
bst2
bst3
bst4
g0l0
g0l1
g0h0
g0h1
g1t1
g1t3
g2t1
g2t3
g3t1
g3t3
g4t1
g4t3
g5t1
g5t3
redo[0]
redo[1]
loop
exen
amx0
amx1
na
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
Bit 16
Bit 17
Bit 18
Bit 19
Bit 20
Bit 21
Bit 22
Bit 23
Bit 24
Bit 25
Bit 26
Bit 27
Bit 28
Bit 29
Bit 30
Bit 31
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
0
0
1
1
1
1
uta
todt
last
RBS
RBS+1 RBS+2 RBS+3 RBS+4
Figure 11-71. Burst Read Access to FPM DRAM (LOOP)
CLKIN
A
Row
Column 1
Column 2
Column 3
Column 4
RD/WR
D
PSDVAL
CS1
(RAS)
BS
(CAS)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
11-86
Freescale Semiconductor
Memory Controller
cst1
cst2
cst3
cst4
bst1
bst2
bst3
bst4
g0l0
g0l1
g0h0
g0h1
g1t1
g1t3
g2t1
g2t3
g3t1
g3t3
g4t1
g4t3
g5t1
g5t3
redo[0]
redo[1]
loop
exen
amx0
amx1
na
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
0
0
0
0
1
0
0
1
1
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
Bit 16
Bit 17
Bit 18
Bit 19
Bit 20
Bit 21
Bit 22
Bit 23
Bit 24
Bit 25
Bit 26
Bit 27
Bit 28
Bit 29
Bit 30
Bit 31
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
uta
todt
last
WBS
WBS+1 WBS+2 WBS+3 WBS+4 WBS+5 WBS+6 WBS+7 WBS+8
Figure 11-72. Burst Write Access to FPM DRAM (No LOOP)
CLKIN
MA
RD/WR
D
PSDVAL
CS1
(RAS)
BS
(CAS)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
11-87
Memory Controller
cst1
cst2
cst3
cst4
bst1
bst2
bst3
bst4
g0l0
g0l1
g0h0
g0h1
g1t1
g1t3
g2t1
g2t3
g3t1
g3t3
g4t1
g4t3
g5t1
g5t3
redo[0]
redo[1]
loop
exen
amx0
amx1
na
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
Bit 16
Bit 17
Bit 18
Bit 19
Bit 20
Bit 21
Bit 22
Bit 23
Bit 24
Bit 25
Bit 26
Bit 27
Bit 28
Bit 29
Bit 30
Bit 31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
uta
todt
last
PTS
PTS+1 PTS+2
Figure 11-73. Refresh Cycle (CBR) to FPM DRAM
CLKIN
MA
RD/WR
D
PSDVAL
CS1
(RAS)
BS
(CAS)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
11-88
Freescale Semiconductor
Memory Controller
cst1
cst2
cst3
cst4
bst1
bst2
bst3
bst4
g0l0
g0l1
g0h0
g0h1
g1t1
g1t3
g2t1
g2t3
g3t1
g3t3
g4t1
g4t3
g5t1
g5t3
redo[0]
redo[1]
loop
exen
amx0
amx1
na
1
1
1
1
1
1
1
1
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
Bit 16
Bit 17
Bit 18
Bit 19
Bit 20
Bit 21
Bit 22
Bit 23
Bit 24
Bit 25
Bit 26
Bit 27
Bit 28
Bit 29
Bit 30
Bit 31
0
0
0
0
0
0
1
1
uta
todt
last
EXS
Figure 11-74. Exception Cycle
•
If GPL_4 is not used as an output, the performance for a page read access can be improved by
setting MxMR[GPL_x4DIS]. The following example shows how the burst read access to FPM
DRAM (no LOOP) can be modified using this feature. In this case the configuration registers are
defined in the following way.
Table 11-43. UPMs Attributes Example
Explanation
Field
Value
Machine select UPMA
BRx[MS]
BRx[PS]
0b100
0b00
0b0
Port size 64-bit
No write protect (R/W)
BRx[WP]
Refresh timer value (1024 refresh cycles)
Refresh timer enable
PURT[PURT]
MxMR[RFEN]
MxMR[AMx]
MxMR[DSx]
MxMR[GPL_x4DIS]
0x0C
0b1
Address multiplex size
0b010
0b01
0b1
Disable timer period
Select between GPL4 and UPMWAIT = UPMWAIT, data sampled at clock
negative edge
Burst inhibit device
ORx[BI]
0b0
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
11-89
Memory Controller
reduced.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
11-90
Freescale Semiconductor
Memory Controller
CLKIN
A
row
col 1
col 2
col 3
col 4
RD/WR
D
D1
D2
D3
D4
PSDVAL
CS1
(RAS)
BS
(CAS)
cst1
cst2
cst3
cst4
bst1
bst2
bst3
bst4
g0l0
g0l1
g0h0
g0h1
g1t1
g1t3
g2t1
g2t3
g3t1
g3t3
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
Bit 16
Bit 17
Bit 18
Bit 19
Bit 20
Bit 21
Bit 22
Bit 23
Bit 24
Bit 25
Bit 26
Bit 27
Bit 28
Bit 29
Bit 30
Bit 31
g4t1 -> DLT3
g4t3
g5t1
g5t3
redo[0]
redo[1]
loop
1
0
1
0
1
0
1
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
1
1
exen
amx0
amx1
na
uta
todt
last
RBS
RBS+1 RBS+2 RBS+3 RBS+4 RBS+5
Figure 11-75. FPM DRAM Burst Read Access (Data Sampling on Falling Edge of CLKIN)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
11-91
Memory Controller
11.7.0.1 EDO Interface Example
Figure 11-76 shows a memory connection to extended data-out type devices. For this connection, GPL1
is connected to the memory device’s OE pins.
PowerQUICC II
BS[0–7]
CS1
RAS
RAS
CASl/h
CASl/h
1M x 16
1M x 16
OE
W
OE
W
MCM516165
MCM516165
R/W
A[0–9]
A[0–9]
A[19–28]
D[0–15]
16
D[0–15]
16
D[0–63]
16
16
RAS
CASl/h
OE
RAS
CASl/h
OE
D[0–15]
1M x 16
D[0–15]
1M x 16
GPL1
MCM516165
MCM516165
W
W
A[0–9]
A[0–9]
Figure 11-76. PowerQUICC II/EDO Interface Connection to the 60x Bus
Table 11-44 shows the programming of the register field for supporting the configuration shown in
Figure 11-76. The example assumes a CLKIN frequency of 66 MHz and that the device needs a
1,024-cycle refresh every 10 µs.
Table 11-44. EDO Connection Field Value Example
Explanation
Machine select UPMA
Field
Value
BRx[MS]
BRx[PS]
0b100
0b00
0b0
Port size 64-bit
No write protect (R/W)
Refresh timer prescaler
Refresh timer value (1024 refresh cycles)
Refresh timer enable
BRx[WP]
MPTPR
0x04
0x07
0b1
PURT[PURT]
MxMR[RFEN]
MxMR[AMx]
Address multiplex size
0b001
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
11-92
Freescale Semiconductor
Memory Controller
Table 11-44. EDO Connection Field Value Example (continued)
Explanation
Field
Value
Disable timer period
Burst inhibit device
MxMR[DSx]
ORx[BI]
0b10
0b0
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
11-93
Memory Controller
CLKIN
A
Row
Column 1
RD/WR
D
PSDVAL
CS1
(RAS)
BS
(CAS)
GPL1
(OE)
cst1
cst2
cst3
cst4
bst1
bst2
bst3
bst4
g0l0
g0l1
g0h0
g0h1
g1t1
g1t3
g2t1
g2t3
g3t1
g3t3
g4t1
g4t3
g5t1
g5t3
redo[0]
redo[1]
loop
exen
amx0
amx1
na
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
Bit 0
0
0
0
1
1
1
1
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
Bit 16
Bit 17
Bit 18
Bit 19
Bit 20
Bit 21
Bit 22
Bit 23
Bit 24
Bit 25
Bit 26
Bit 27
Bit 28
Bit 29
Bit 30
Bit 31
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
uta
todt
last
RSS
RSS+1 RSS+2 RSS+3 RSS+4
Figure 11-77. Single-Beat Read Access to EDO DRAM
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
11-94
Freescale Semiconductor
Memory Controller
CLKIN
A
RD/WR
D
Row
Column 1
PSDVAL
CS1
(RAS)
BS
(CAS)
GPL1
(OE)
cst1
cst2
cst3
cst4
bst1
bst2
bst3
bst4
g0l0
g0l1
g0h0
g0h1
g1t1
g1t3
g2t1
g2t3
g3t1
g3t3
g4t1
g4t3
g5t1
g5t3
0
0
0
0
0
1
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
1
Bit 0
0
0
0
1
1
1
1
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
Bit 16
Bit 17
Bit 18
Bit 19
Bit 20
Bit 21
Bit 22
Bit 23
Bit 24
Bit 25
Bit 26
Bit 27
Bit 28
Bit 29
Bit 30
Bit 31
1
1
1
1
1
1
1
1
redo[0]
redo[1]
loop
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
exen
amx0
amx1
na
uta
todt
last
WSS
WSS+1 WSS+2 WSS+3
Figure 11-78. Single-Beat Write Access to EDO DRAM
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
11-95
Memory Controller
CLKIN
A
RD/WR
D
Row
Column 1
PSDVAL
CS1
(RAS)
BS
(CAS)
GPL1
(OE)
cst1
cst2
cst3
cst4
bst1
bst2
bst3
bst4
g0l0
g0l1
g0h0
g0h1
g1t1
g1t3
g2t1
g2t3
g3t1
g3t3
g4t1
g4t3
g5t1
g5t3
redo[0]
redo[1]
loop
exen
amx0
amx1
na
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
Bit 0
0
0
0
1
1
1
1
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
Bit 16
Bit 17
Bit 18
Bit 19
Bit 20
Bit 21
Bit 22
Bit 23
Bit 24
Bit 25
Bit 26
Bit 27
Bit 28
Bit 29
Bit 30
Bit 31
1
1
1
1
1
1
1
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
uta
todt
last
WSS
WSS+1 WSS+2 REDO1 REDO2 REDO3 WSS+3
Figure 11-79. Single-Beat Write Access to EDO DRAM Using REDO to Insert Three Wait States
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
11-96
Freescale Semiconductor
Memory Controller
CLKIN
A
RD/WR
D
Row
Column 1
Column 2
Column 3
Column 4
PSDVAL
CS1
(RAS)
BS
(CAS)
GPL1
(OE)
cst1
cst2
cst3
cst4
bst1
bst2
bst3
bst4
g0l0
g0l1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
g0h0
g0h1
g1t1
g1t3
g2t1
g2t3
g3t1
g3t3
g4t1
g4t3
g5t1
g5t3
redo[0]
redo[1]
loop
exen
amx0
amx1
na
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
Bit 16
Bit 17
Bit 18
Bit 19
Bit 20
Bit 21
Bit 22
Bit 23
Bit 24
Bit 25
Bit 26
Bit 27
Bit 28
Bit 29
Bit 30
Bit 31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
uta
todt
last
RBS+10
RBS
RBS+1 RBS+2 RBS+3 RBS+4 RBS+5 RBS+6 RBS+7 RBS+8 RBS+9
Figure 11-80. Burst Read Access to EDO DRAM
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
11-97
Memory Controller
CLKIN
A
RD/WR
D
Row
Column 1
Column 2
Column 3
Column 4
PSDVAL
CS1
(RAS)
BS
(CAS)
GPL1
(OE)
cst1
cst2
cst3
cst4
bst1
bst2
bst3
bst4
g0l0
g0l1
g0h0
g0h1
g1t1
g1t3
g2t1
g2t3
g3t1
g3t3
g4t1
g4t3
g5t1
g5t3
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
0
0
0
0
0
0
1
0
1
1
1
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
Bit 16
Bit 17
Bit 18
Bit 19
Bit 20
Bit 21
Bit 22
Bit 23
Bit 24
Bit 25
Bit 26
Bit 27
Bit 28
Bit 29
Bit 30
Bit 31
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
redo[0]
redo[1]
loop
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
exen
amx0
amx1
na
uta
todt
last
WBS
WBS+1 WBS+2 WBS+3 WBS+4 WBS+5 WBS+6 WBS+7 WBS+8 WBS+9
Figure 11-81. Burst Write Access to EDO DRAM
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Memory Controller
CLKIN
A
RD/WR
D
PSDVAL
CS1
(RAS)
BS
(CAS)
GPL1
(OE)
cst1
cst2
cst3
cst4
bst1
bst2
bst3
bst4
g0l0
g0l1
g0h0
g0h1
g1t1
g1t3
g2t1
g2t3
g3t1
g3t3
g4t1
g4t3
g5t1
g5t3
redo[0]
redo[1]
loop
exen
amx0
amx1
na
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
Bit 16
Bit 17
Bit 18
Bit 19
Bit 20
Bit 21
Bit 22
Bit 23
Bit 24
Bit 25
Bit 26
Bit 27
Bit 28
Bit 29
Bit 30
Bit 31
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
uta
todt
last
PTS
PTS+1 PTS+2 PTS+3 PTS+4
Figure 11-82. Refresh Cycle (CBR) to EDO DRAM
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11-99
Memory Controller
CLKIN
A
RD/WR
D
PSDVAL
CS1
(RAS)
BS
(CAS)
GPL1
(OE)
cst1
cst2
cst3
cst4
bst1
bst2
bst3
bst4
g0l0
g0l1
g0h0
g0h1
g1t1
g1t3
g2t1
g2t3
g3t1
g3t3
g4t1
g4t3
g5t1
g5t3
redo[0]
redo[1]
loop
exen
amx0
amx1
na
1
1
1
1
1
1
1
1
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
Bit 16
Bit 17
Bit 18
Bit 19
Bit 20
Bit 21
Bit 22
Bit 23
Bit 24
Bit 25
Bit 26
Bit 27
Bit 28
Bit 29
Bit 30
Bit 31
1
1
0
0
0
0
0
0
1
1
uta
todt
last
EXS
Figure 11-83. Exception Cycle For EDO DRAM
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Memory Controller
11.8 Handling Devices with Slow or Variable Access Times
The memory controller provides two ways to interface with slave devices that are very slow (access time
is greater than the maximum allowed by the user programming model) or cannot guarantee a predefined
access time (for example some FIFO, hierarchical bus interface, or dual-port memory devices). These
mechanisms are as follows:
•
The wait mechanism—Used only in accesses controlled by the UPM. Setting MxMR[GPLx4DIS]
enables this mechanism.
•
The external termination (GTA) mechanism is used only in accesses controlled by the GPCM.
ORx[SETA] specifies whether the access is terminated internally or externally.
The following examples show how the two mechanisms work.
11.8.1 Hierarchical Bus Interface Example
Assume that the core initiates a local-bus read cycle that addresses main memory connected to the system
bus. The hierarchical bus interface accepts local bus requests and generates a read cycle on the system bus.
The programmer cannot predict when valid data can be latched by the core because a DMA device may
be occupying the system bus.
•
The wait solution (UPM)—The external module asserts UPMWAIT to the memory controller to
indicate that data is not ready. The memory controller synchronized this signal because the wait
signal is asynchronous. As a result of the wait signal being asserted, the UPM enters a freeze mode
at the rising edge of CLKIN upon encountering the WAEN bit being set in the UPM word. The
UPM stays in that state until UPMWAIT is negated. After UPMWAIT is negated, the UPM
continues executing from the next entry to the end of the pattern (LAST bit is set).
•
The external termination solution (GPCM)—The bus interface module asserts GTA to the memory
controller when it can sample data. Note that GTA is also synchronized.
11.8.2 Slow Devices Example
Assume that the core initiates a read cycle from a device whose access time exceeds the maximum allowed
by the user programming model.
•
The wait solution (UPM)—The core generates a read access from the slow device. The device in
turn asserts the wait signal until the data is ready. The core samples data only after the wait signal
is negated.
•
The external termination solution (GPCM)—The core generates a read access from the slow
device, which must generate the asynchronous GTA when it is ready.
11.9 External Master Support (60x-Compatible Mode)
The memory controller supports internal and external bus masters. Accesses from the core or the CPM are
considered internal; accesses from an external bus master are external.
External bus master support is available only if the PowerQUICC II is placed in 60x-compatible mode by
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11-101
Memory Controller
There are two types of external bus masters:
•
Any 60x-compatible device with a 64-bit data bus, such as an MPC603e, MPC604e, MPC750, or
an MPC2605 (L2 cache) in copy-back mode
•
PowerQUICC II
Both of these external bus master types can access a slave PowerQUICC II’s internal registers and
dual-port RAM. They can also use the slave’s memory controller to access memory devices on the 60x
bus. An external master has access to the slave’s local bus via the slave’s 60x-to-local bus bridge.
11.9.1 60x-Compatible External Masters (non-PowerQUICC II)
A non-PowerQUICC II external master can perform only 64-bit port accesses when using a slave
PowerQUICC II’s memory controller for memory devices assigned to the 60x bus. Also, ECC or
RMW-parity are not supported.
For 60x bus compatibility, the following connections should be observed:
•
•
•
PowerQUICC II’s TSIZ[1–3] should be connected to the external master’s TSIZ[0–2]
PowerQUICC II’s TSIZ[0] should be pulled down
PowerQUICC II’s PSDVAL should be pulled up
11.9.2 PowerQUICC II External Masters
An PowerQUICC II external master is a 60x-compatible master with additional functionality. As described
in the following, it has fewer the restrictions than other 60x-compatible masters:
•
•
Any port size is allowed
ECC and RMW-parity are supported
11.9.3 Extended Controls in 60x-Compatible Mode
In 60x-compatible mode, the memory controller provided extended controls for the glue logic. The
extended control consists of the following:
•
•
Memory address latch (ALE) to latch the 60x address for memory use
The address multiplex pin (GPL5/SDAMUX), which controls external multiplexing for DRAM
and SDRAM devices
•
•
LSB address pins (BADDR[27–31]) for incrementing memory addresses
PSDVAL as a termination to a partial transaction (such as port-size beat access).
11.9.4 Address Incrementing for External Bursting Masters
BADDR[27–31] should be used to generate addresses to memory devices for burst accesses. In
60x-compatible mode, when a master initiates an external bus transaction, it reflects the value of A[27–31]
on the first clock cycle of the memory access. These signals are latched by the memory controller and on
subsequent clock cycles, BADDR[27–31] increments as programmed in the UPM or after each data beat
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Memory Controller
is sampled in the GPCM or after each READ/WRITE command in the SDRAM machine (the SDRAM
machine uses BADDR only for port sizes of 16 or 8 bits).
11.9.5 External Masters Timing
External and internal masters have similar memory access timings. However, because it takes more time
to decode the addresses of external masters, memory accesses by external masters start one cycle later than
those of internal masters.
As soon as the external master asserts TS, the memory controller compares the address with each of its
defined valid banks. If a match is found, the memory controller asserts the address latch enable (ALE) and
control signals to the memory devices. The memory controller asserts PSDVAL for each data beat to
indicate data beat termination on write transactions and data valid on read transactions.
The 60x bus is pipelined. The ALE pins control the external latch that latches the address from the 60x bus
and keeps the address stable for the memory access. The memory controller asserts ALE only on the start
of new memory controller access.
Figure 11-84 shows the pipelined bus operation in 60x-compatible mode.
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Freescale Semiconductor
11-103
Memory Controller
CLKIN
ADDR + ATTR
TS
AACK
DBG
PSDVAL
TA
D
ALE
MA
CS
WE
OE
BADDR[27–28]
02
03
00
01
Figure 11-84. Pipelined Bus Operation and Memory Access in 60x-Compatible Mode
Figure 11-85 shows the 1-cycle delay for external master access. For systems that use the 60x bus with low
frequency (33 MHz), the 1-cycle delay for external masters can be eliminated by setting BCR[EXDD].
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Memory Controller
CLKIN
A[0–28]
A[27–31]
TT
TBST
TSIZ
TS
TA
CS
WE
OE
Data
Address
Match and
Compare
Memory
Device
Access
Figure 11-85. External Master Access (GPCM)
11.9.5.1 Example of External Master Using the SDRAM Machine
Figure 11-86 shows an interconnection in which a 60x-compatible external master and the
PowerQUICC II can share access to a SDRAM bank. Note that the address multiplexer is controlled by
SDAMUX, while the address latch is controlled by ALE. Also note that because this is a 64-bit port size
SDRAM, BADDR is not needed.
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11-105
Memory Controller
BNKSEL,SDWE,SDRAS,SDCAS
CS1
SDRAM
64-Bit Port Size
DQM[0–7]
SDAMUX
Multiplexer
MA
Latch
ALE
PowerQUICC II
External Master
A[0–31]
D[0–63]
TT[0–4]
TS
TBST
TA
TSIZ[1–3]
TSIZ[0]
TSIZ[0–2]
(pull down)
PSDVAL
(pull up)
Arbitration signals
Figure 11-86. External Master Configuration with SDRAM Device
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Chapter 12
Secondary (L2) Cache Support
The PowerQUICC II has features to support an externally controlled secondary (L2) cache such as the
Freescale MPC2605 integrated secondary cache for microprocessors that implement the PowerPC
architecture. This chapter describes the PowerQUICC II’s L2 cache interface—configurations, operation,
programmable parameters, system requirements, and timing.
12.1 L2 Cache Configurations
The PowerQUICC II supports three L2 cache configurations—copy-back mode, write-through mode, and
ECC/parity mode. The following sections describe the L2 cache modes.
12.1.1 Copy-Back Mode
The use of a copy-back L2 cache offers several advantages over direct access to the memory system. In
copy-back mode, cacheable write operations are performed to the L2 cache without updating main
memory. Since every cacheable write operation does not go to main memory but to the L2 cache which
can be accessed more quickly, write operation latency is reduced along with contention for the memory
system. In copy-back mode, cacheable read operations that hit in the L2 cache are serviced from the L2
cache without requiring a memory transaction and its associated latency. Copy-back mode offers the
greatest performance of all the L2 cache modes.
Copy-back L2 cache blocks implement a dirty bit in their tag RAM, which indicates whether the contents
of the L2 cache block have been modified from that in main memory. During L2 cache line replacement,
L2 cache blocks that have been modified (dirty) are written back to memory; unmodified (not dirty) L2
cache blocks are invalidated and overwritten without being written back to memory.
Copy-back mode requires that the L2 cache is able to initiate copy-backs to main memory. To do this, the
L2 cache must act as a bus master and implement the bus arbitration signals BR, BG, and DBG. The
PowerQUICC II can also support additional bus masters (60x or PowerQUICC II type) in copy-back
mode.
Figure 12-1. shows a PowerQUICC II connected to a MPC2605 integrated L2 cache in copy-back mode.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
12-1
Secondary (L2) Cache Support
(pull up)
PowerQUICC II
MPC2605
BR
BG
L2BR
L2BG
L2DBG
DBG
CPU_BR, CPU_BG, CPU_DBG
TS, TT[0–4], TBST, TSIZ[1–3]
CI, WT, GBL, TA, DBB, TEA
AACK, ARTRY
CPU_BR,CPU_BG,CPU_DBG
TS, TT[0–4], TBST, TSIZ[0–2]]
CI, WT, GBL, TA, DBB, TEA
AACK, ARTRY
TSIZ[0]
(pull down)
L2_HIT
L2_CLAIM
A[0–31]
D[0–63]
A[0–31]
D[0–63]
Latch
MUX
Memory Controller
SDRAM Main Memory
I/O Devices
Figure 12-1. L2 Cache in Copy-Back Mode
12.1.2 Write-Through Mode
In write-through mode, cacheable write operations are performed to both the L2 cache and to main
memory. Since every cacheable write operation goes to the L2 cache and to main memory, write operation
latency is the same as an ordinary memory write transaction. In write-through mode, cacheable read
operations that hit in the L2 cache are serviced from the L2 cache without requiring a memory transaction
and its associated latency. Thus, reads are serviced just as they are for copy-back mode. Write-through
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
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Freescale Semiconductor
Secondary (L2) Cache Support
mode sacrifices some of the write performance of copy-back mode, but guarantees L2 cache coherency
with main memory.
Since write-through mode keeps memory coherent with the contents of the L2 cache, there is never any
need to perform an L2 copy-back. This removes the need for the L2 cache to maintain a dirty bit in the tag
RAM (all cache blocks are unmodified) and it also removes the need for bus arbitration signals.
The L2 cache is configured for write-through mode by pulling down it’s WT signal. There are no
configuration changes to the PowerQUICC II required in write-through mode. The PowerQUICC II can
also support additional bus masters (60x or PowerQUICC II type) in write-through mode.
Figure 12-2. shows a PowerQUICC II connected to a MPC2605 integrated L2 cache in write-through
mode.
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Freescale Semiconductor
12-3
Secondary (L2) Cache Support
PowerQUICC II
MPC2605
(pull up)
(pull up)
BR
BG
L2BR
L2BG
L2DBG
DBG
CPU_BR, CPU_BG, CPU_DBG
TS, TT[0:4], TBST, TSIZ[1–3]
CI, GBL, TA, DBB, TEA
AACK, ARTRY
CPU_BR,CPU_BG,CPU_DBG
TS, TT[0–4], TBST, TSIZ[0–2]
CI, GBL, TA, DBB, TEA
AACK, ARTRY
TSIZ[0]
WT
(pull down)
(pull down)
L2_HIT
L2_CLAIM
A[0–31]
D[0–63]
A[0–31]
D[0–63]
Latch
Memory Controller
MUX
SDRAM Main Memory
I/O Devices
Figure 12-2. External L2 Cache in Write-Through Mode
12.1.3 ECC/Parity Mode
ECC/parity mode is a subset of write-through mode with some connection changes that allow the L2 cache
to support ECC or Parity. The connection changes are:
•
•
•
The PowerQUICC II’s DP[0:7] signals are connected to the L2 cache’s DP[0:7] signals.
The L2’s TSIZ[0:2] signals are pulled down to always indicate 8-byte transaction size.
The L2’s A[29:31] signals are pulled down.
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Freescale Semiconductor
Secondary (L2) Cache Support
In ECC/parity mode the L2 cache can support memory regions with ECC/Parity under the following
restrictions:
•
All non-write-protected (BRx[WP] = 0) memory banks marked caching-allowed must use either
ECC (BRx[DECC] = 0b11) or read-modify-write parity (BRx[DECC] = 0b10). See
register parameters.
•
Only PowerQUICC II-type masters are supported in systems that use ECC/parity L2 cache mode.
external master types.
Figure 12-3. shows a PowerQUICC II connected to an MPC2605 integrated L2 cache in ECC/Parity
mode.
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Freescale Semiconductor
12-5
Secondary (L2) Cache Support
PowerQUICC II
MPC2605
(pull up)
(pull up)
BR
BG
L2BR
L2BG
L2DBG
DBG
CPU_BR, CPU_BG, CPU_DBG
TS, TT[0–4], TBST
CPU_BR,CPU_BG,CPU_DBG
TS, TT[0–4], TBST
TSIZ[0–2]
(pull downs)
CI, GBL, TA, DBB, TEA
AACK, ARTRY
TSIZE[0]
CI, GBL, TA, DBB, TEA
AACK, ARTRY
WT
(pull down)
(pull down)
L2_HIT
L2_CLAIM
A[29–31]
(pull downs)
A[0–31]
A[0–28]
D[0–63],DP[0–7]
D[0–63], DP[0–7]
Latch
MUX
Memory Controller
SDRAM Main Memory
I/O Devices
Figure 12-3. External L2 Cache in ECC/Parity Mode
12.2 L2 Cache Interface Parameters
The L2 cache interface parameters in the bus configuration register (BCR) control the configuration and
operation of the PowerQUICC II’s L2 interface. The parameters should be configured as follows:
•
•
BCR[EBM] = 1—PowerQUICC II in 60x-compatible mode.
BCR[L2C] = 1—L2 cache is present.
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Freescale Semiconductor
Secondary (L2) Cache Support
•
•
BCR[L2D] = 0—L2 response time. In this case, the L2 will claim a bus transaction one clock cycle
after TS assertion.
BCR[APD] = 1: This parameter is not L2 specific, but should consider the L2 ARTRY assertion
timing.
12.3 System Requirements When Using the L2 Cache Interface
The following requirements apply to PowerQUICC II-based systems that implement an external L2 cache:
•
For systems that use copy-back mode, all cachable memory regions must be marked as global in
the CPU’s MMU and the CPM. This causes the assertion of the GBL signal on every cachable
transaction. Systems that use write-through mode (or ECC/Parity mode) have no such restriction.
•
•
•
All cachable memory regions must have a 64-bit port size.
All cachable memory regions must not set the BRx[DR] bit.
All cachable memory regions must not use ECC or parity unless the external L2 is connected as
•
All non-cachable memory regions must be marked as caching-inhibited in the CPU’s MMU. This
causes the assertion of the CI signal on every non-cachable transaction. Note that the
PowerQUICC II’s internal space (IMMR) and any memory banks assigned to the local bus are
always considered non-cachable.
12.4 L2 Cache Operation
When configured for an L2 cache (BCR[L2C] = 1), the PowerQUICC II samples the L2_HIT input signal
when the delay time programmed in BCR[L2D] expires. For 60x bus cycles, if L2_HIT is asserted, the
external L2 cache drives AACK and TA to complete the transaction without the PowerQUICC II initiating
a system memory transfer.
The external L2 cache can assert ARTRY to retry 60x bus cycles, and can request the bus by asserting BR
to perform L2 cast-out operations. The arbiter grants the address and data bus to the external L2 cache by
asserting BG and DBG, respectively. If the external L2 cache asserts ARTRY, it should not assert L2_HIT.
For more information about the timing and behavior of the MPC2605 integrated L2 cache, refer to the
MPC2605 data sheet.
12.5 Timing Example
Figure 12-4. shows a read access performed by the PowerQUICC II with an externally controlled L2
cache. For the first transaction (A0), the PowerQUICC II grants the bus and asserts TS with the address
and address transfer attributes. In this example, BCR[L2D] = 0, which means that L2_HIT is valid one
clock cycle after the assertion of TS. The PowerQUICC II samples L2_HIT when L2D expires. In the
second transaction (A1), the access misses in the L2 cache and the memory controller starts the transaction
a minimum of three cycles after the assertion of TS.
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12-7
Chapter 13
IEEE 1149.1 Test Access Port
The PowerQUICC II provides a dedicated user-accessible test access port (TAP) that is fully compatible
with the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture. Problems associated
with testing high-density circuit boards have led to development of this proposed standard under the
sponsorship of the Test Technology Committee of IEEE and the Joint Test Action Group (JTAG). The
PowerQUICC II’s implementation supports circuit-board test strategies based on this standard.
The TAP consists of five dedicated signal pins—a 16-state TAP controller and two test data registers. A
boundary scan register links all device signal pins into a single shift register. The test logic, which is
implemented using static logic design, is independent of the device system logic. The PowerQUICC II’s
implementation provides the capability to do the following:
•
•
Perform boundary scan operations to check circuit-board electrical continuity.
Bypass the PowerQUICC II for a given circuit-board test by effectively reducing the boundary
scan register to a single cell.
•
•
Sample the PowerQUICC II system pins during operation and transparently shift out the result in
the boundary-scan register.
Disable the output drive to pins during circuit-board testing.
NOTE
Precautions must be observed to ensure that the IEEE 1149.1-like test logic
does not interfere with nontest operation.
13.1 Overview
The PowerQUICC II’s implementation includes a TAP controller, a 4-bit instruction register, and two test
registers (a 1-bit bypass register and a 475-bit boundary scan register). Figure 13-1 shows an overview of
the PowerQUICC II’s scan chain implementation.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
13-1
IEEE 1149.1 Test Access Port
Boundary Scan Register
M
U
X
TDI
Bypass
Instruction Apply & Decode Register
8
0
M
U
X
TDO
8–Bit Instruction Register
TRST
TMS
TAP Controller
Figure 13-1. Test Logic Block Diagram
TCK
The TAP consists of the signals in Table 13-1.
.
Table 13-1. TAP Signals
Signal
Description
TCK A test clock input to synchronize the test logic.
TMS A test mode select input (with an internal pull-up resistor) that is sampled on the rising edge of TCK to
sequence the TAP controller’s state machine.
TDI
A test data input (with an internal pull-up resistor) that is sampled on the rising edge of TCK.
TDO A data output that can be three-stated and actively driven in the shift-IR and shift-DR controller states. TDO
changes on the falling edge of TCK.
TRST An asynchronous reset with an internal pull-up resistor that provides initialization of the TAP controller and
other logic required by the standard.
13.2 TAP Controller
The TAP controller is responsible for interpreting the sequence of logical values on the TMS signal. It is
a synchronous state machine that controls the operation of the JTAG logic. The value shown adjacent to
each bubble represents the value of the TMS signal sampled on the rising edge of the TCK signal.
Figure 13-2 shows the state machine.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
13-2
Freescale Semiconductor
IEEE 1149.1 Test Access Port
Test Logic
Reset
1
0
0
1
1
1
Run—Test/Idle
Select—DR_SCAN
Select—IR_SCAN
0
0
Capture—DR
Capture—IR
0
0
Shift—DR
Shift—IR
1
1
Exit1—DR
Exit1—IR
0
0
Pause—DR
Pause—IR
1
Exit2—DR
1
1
Exit2—IR
1
Update—DR
0
Update—IR
0
1
1
Figure 13-2. TAP Controller State Machine
13.3 Boundary Scan Register
The PowerQUICC II’s scan chain implementation has a 878-bit boundary scan register that contains bits
for all device signal, clock pins, and associated control signals. The PORESET_B and XFC pins are
associated with analog signals and are not included in the boundary scan register. An
IEEE-1149.1-compliant boundary-scan register has been included on the PowerQUICC II that can be
connected between TDI and TDO when EXTEST or SAMPLE/PRELOAD instructions are selected. It is
used for capturing signal pin data on the input pins, forcing fixed values on the output signal pins, and
selecting the direction and drive characteristics (a logic value or high impedance) of the bidirectional and
three-state signal pins. Figure 13-3, Figure 13-4, Figure 13-5, and Figure 13-6 show various cell types.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
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13-3
IEEE 1149.1 Test Access Port
Shift DR
To Next Cell
1 — EXTEST | Clamp
0 — Otherwise
G1
Data from
System
Logic
1
1
To Output
Buffer
MUX
G1
1
1
D
C
MUX
D
C
Clock DR
Figure 13-3. Output Pin Cell (O.Pin)
From Last Cell
Update DR
To Next Cell
Data to
System
Logic
Input
Pin
G1
D
C
1
1
MUX
Shift DR
From Last Cell
Figure 13-4. Observe-Only Input Pin Cell (I.Obs)
Clock DR
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13-4
Freescale Semiconductor
IEEE 1149.1 Test Access Port
Shift DR
To Next Cell
1 — EXTEST | Clamp
0 — Otherwise
G1
Output Control
from System
1
1
To Output
Buffer
Logic
MUX
G1
1
1
D
C
MUX
D
C
Clock DR
From Last Cell
Update DR
Figure 13-5. Output Control Cell (IO.CTL)
From Last Cell
Output Enable
from System Logic
I/O.CTL
I/O
Pin
EN
Output Data
O.PIN
Input Data
I.OBS
To Next Pin Pair
To Next Cell
Figure 13-6. General Arrangement of Bidirectional Pin Cells
The control bit value controls the output function of the bidirectional pin. One or more bidirectional data
cells can be serially connected to a control cell. Bidirectional pins include two scan cell for data (IO.Cell)
13.4 Instruction Register
The PowerQUICC II JTAG implementation includes the public instructions (EXTEST,
SAMPLE/PRELOAD, and BYPASS) and also supports the CLAMP instruction. One additional public
instruction (HI-Z) can be used to disable all device output drivers. The PowerQUICC II includes an 8-bit
instruction register (no parity) that consists of a shift register with four parallel outputs. Data is transferred
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13-5
IEEE 1149.1 Test Access Port
from the shift register to the parallel outputs during the update-IR controller state. The four bits are used
Table 13-2. Instruction Decoding
1
Code
Instruction
Description
B7 B6 B5 B4 B3 B2 B1 B0
0
0
0
0
0
0
0
0
EXTEST
External test. Selects the 475-bit boundary scan register.
EXTEST also asserts an internal reset for the PowerQUICC II’s
system logic to force a known beginning internal state while
performing external boundary scan operations. By using the
TAP, the register is capable of scanning user-defined values
into the output buffers, capturing values presented to input
pins, sampling this data into the boundary scan register (device
revision B.3 and later), and controlling the output drive of
three-state output or bi-directional pins. For more details on the
function and use of EXTEST, refer to the IEEE 1149.1
standard.
1
1
0
0
0
0
0
0
SAMPLE/
Initializes the boundary scan register output cells before the
PRELOAD selection of EXTEST. This initialization ensures that known
data appears on the outputs when entering an EXTEST
instruction. SAMPLE/PRELOAD also provides a chance to
obtain a snapshot of system data and control signals.
NOTE: Since there is no internal synchronization between the
TCK and CLKOUT, the user must provide some form of
external synchronization between the JTAG operation at TCK
frequency and the system operation CLKOUT frequency to
achieve meaningful results.
1
1
1
1
1
1
1
1
BYPASS
The BYPASS instruction creates a shift register path from TDI
to the bypass register and, finally, to TDO, circumventing the
475-bit boundary scan register. This instruction is used to
enhance test efficiency when a component other than the
PowerQUICC II becomes the device under test. It selects the
single-bit bypass register as shown below.
Shift DR
G1
0
1
1
D
MUX
To TDO
C
From TDI
Clock DR
When the bypass register is selected by the current instruction,
the shift register stage is cleared on the rising edge of TCK in
the capture-DR controller state. Thus, the first bit to be shifted
out after selecting the bypass register is always a logic zero.
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Freescale Semiconductor
IEEE 1149.1 Test Access Port
Table 13-2. Instruction Decoding (continued)
1
Code
B7 B6 B5 B4 B3 B2 B1 B0
Instruction
Description
1
1
1
1
0
0
0
0
0
1
HI–Z
Provided as a manufacturer’s optional public instruction to
avoid back driving the output pins during circuit-board testing.
When HI-Z is invoked all output drivers, including the two-state
drivers, are turned off (high impedance). The instruction
selects the bypass register.
1
1
1
1
0
0
CLAMP and CLAMP selects the single-bit bypass register as shown in the
BYPASS
BYPASS instruction figure above, and the state of all signals
driven from the system output pins is completely defined by the
data previously shifted into the boundary scan register. For
example, using the SAMPLE/PRELOAD instruction.
1
B0 (lsb) is shifted first.
The parallel output of the instruction register is set to all ones in the test-logic-reset controller state. Notice
that this preset state is equivalent to the BYPASS instruction. During the capture-IR controller state, the
parallel inputs to the instruction shift register are loaded with the CLAMP command code.
13.5 PowerQUICC II Restrictions
The control afforded by the output enable signals using the boundary-scan register and the EXTEST
instruction requires a compatible circuit-board test environment to avoid device-destructive
configurations. The user must avoid situations in which the PowerQUICC II’s output drivers are enabled
into actively driven networks.
13.6 Nonscan Chain Operation
In nonscan chain operation, the TCK input does not include an internal pull-up resistor and should be tied
high or low to preclude mid-level inputs.
To ensure that the scan chain test logic is kept transparent to the system logic, the TAP controller is forced
into the test-logic-reset state. This is done inside the chip by connecting TRST to PORESET
TMS should remain logic high, so that the TAP controller does not leave the test-logic-reset state.
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IEEE 1149.1 Test Access Port
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Part IV
Communications Processor Module
Intended Audience
Part IV is intended for system designers who need to implement various communications protocols on the
PowerQUICC II. It assumes a basic understanding of the PowerPC exception model, the PowerQUICC II
interrupt structure, as well as a working knowledge of the communications protocols to be used. A
complete discussion of these protocols is beyond the scope of this book.
Contents
Part IV describes behavior of the PowerQUICC II communications processor module (CPM) and the
RISC communications processor (CP) that it contains (note that this is separate from the embedded
processor that implements the PowerPC architecture).
It contains the following chapters:
•
•
•
•
•
•
•
PowerQUICC II CPM.
start-up, initialization and operation, protection, as well as the external system bus.
the physical layer—UTOPIA, MII, modem lines,
generators (BRGs) that can be used with the FCCs, SCCs, and SMCs.
configured as four identical 16-bit or two 32-bit general-purpose timers.
(SDMA) channels on the PowerQUICC II.
communications controllers (SCC), which can be configured independently to implement different
protocols for bridging functions, routers, and gateways, and to interface with a wide variety of
standard WANs, LANs, and proprietary networks.
•
•
asynchronous receiver transmitter (UART) protocol that is used for sending low-speed data
between devices.
protocol.
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IV-1
•
•
byte-oriented BISYNC protocol developed by IBM for use in networking products.
transparent mode (also called totally transparent mode), which provides a clear channel on which
the SCC can send or receive serial data without bit-level manipulation.
•
protocol.
•
•
controllers, full-duplex ports that can be configured independently to support one of three
protocols—UART, transparent, or general-circuit interface (GCI).
•
•
controller (MCC), which handles up to 128 serial, full-duplex data channels.
communications controllers (FCCs), which are SCCs optimized for synchronous high-rate
protocols.
•
controller, which provides the ATM and AAL layers of the ATM protocol. The ATM controller
performs segmentation and reassembly (SAR) functions of AAL5, AAL1, and AAL0, and most of
the common parts convergence sublayer (CP-CS) of these protocols.
•
•
•
•
emulation service (CES) using ATM adaptation layer type 1 (AAL1) on the PowerQUICC II.
type 2 (AAL2) CPS, CPS switching, and SSSAR.
multiplexing for ATM (IMA) microcode.
support applications which receive ATM traffic over the standard serial protocols like E1, T1, and
xDSL via its serial interface (SIx TDMx and NMSI) ports because of its internally implemented
TC-layer functionality.
•
Ethernet IEEE 802.3 protocol.
•
•
protocol.
•
allows the PowerQUICC II to exchange data between other PowerQUICC II chips, the MC68360,
the MC68302, the M68HC11, and M68HC05 microcontroller families, and peripheral devices
such as EEPROMs, real-time clocks, A/D converters, and ISDN devices.
•
circuit (I2C®) controller, which allows data to be exchanged with other I2C devices, such as
microcontrollers, EEPROMs, real-time clock devices, and A/D converters.
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Freescale Semiconductor
•
the I/O ports can be configured as a general-purpose I/O signal or as a signal dedicated to
supporting communications devices, such as SMCs, SCCs. MCCs, and FCCs.
Suggested Reading
This section lists additional reading that provides background for the information in this manual as well as
general information about the PowerPC architecture.
MPC82xx Documentation
Supporting documentation for the PowerQUICC II can be accessed through the world-wide web at
www.freescale.com. This documentation includes technical specifications, reference materials, and
detailed applications notes.
Architecture Documentation
Documentation is available in the following document:
•
Programming environments manuals—These books provide information about resources defined
by the PowerPC architecture that are common to processors that implement the PowerPC
architecture. There are two versions, one that describes the functionality of the combined 32- and
64-bit architecture models and one that describes only the 32-bit model.
— Programming Environments for 32-Bit Implementations of the PowerPC Architecture, REV
3(Freescale order #: MPCFPE32B/AD)
For a current list of documentation, refer to http://www.freescale.com.
Conventions
This document uses the following notational conventions:
Bold entries in figures and tables showing registers and parameter RAM should
Bold
be initialized by the user.
mnemonics
Instruction mnemonics are shown in lowercase bold.
Italics indicate variable command parameters, for example, bcctrx.
Book titles in text are set in italics.
italics
0x0
Prefix to denote hexadecimal number
0b0
Prefix to denote binary number
rA, rB
rD
Instruction syntax used to identify a source GPR
Instruction syntax used to identify a destination GPR
REG[FIELD]
Abbreviations or acronyms for registers or buffer descriptors are shown in
uppercase text. Specific bits, fields, or numerical ranges appear in brackets. For
example, MSR[LE] refers to the little-endian mode enable bit in the machine state
register.
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Freescale Semiconductor
IV-3
x
In certain contexts, such as in a signal encoding or a bit field, indicates a don’t
care.
n
¬
&
|
Indicates an undefined numerical value
NOT logical operator
AND logical operator
OR logical operator
Acronyms and Abbreviations
Table i contains acronyms and abbreviations used in this document. Note that the meanings for some
acronyms (such as SDR1 and DSISR) are historical, and the words for which an acronym stands may not
be intuitively obvious.
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Table IV-1. Acronyms and Abbreviated Terms
Meaning
Term
AAL
ATM adaptation layer
ABR
ACR
ALU
APC
ATM
BD
Availabe bit rate
Allowed cell rate
Arithmetic logic unit
ATM pace control
Asynchronous transfer mode
Buffer descriptor
Built-in self test
BIST
BT
Burst tolerance
CBR
CEPT
Constant bit rate
Conference des administrations Europeanes des Postes et Telecommunications (European
Conference of Postal and Telecommunications Administrations).
C/I
Condition/indication channel used in the GCI protocol
Cell loss priority
CLP
CP
Communications processor
CP-CS
CPM
CPS
Common part convergence sublayer
Communications processor module
Cells per slot
CSMA
CSMA/CD
DMA
DPLL
DPR
Carrier sense multiple access
Carrier sense multiple access with collision detection
Direct memory access
Digital phase-locked loop
Dual-port RAM
DRAM
DSISR
EA
Dynamic random access memory
Register used for determining the source of a DSI exception
Effective address
EEST
EPROM
FBP
Enhanced Ethernet serial transceiver
Erasable programmable read-only memory
Free buffer pool
FIFO
GCI
First-in-first-out (buffer)
General circuit interface
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IV-5
Table IV-1. Acronyms and Abbreviated Terms (continued)
Meaning
Term
GCRA
Generic cell rate algorithm (leaky bucket)
General-purpose chip-select machine
Graphical user interface
High-level data link control
Inter-integrated circuit
GPCM
GUI
HDLC
2
I C
IDL
Inter-chip digital link
IEEE
IrDA
ISDN
JTAG
JTAG
LAN
LIFO
LRU
LSB
lsb
Institute of Electrical and Electronics Engineers
Infrared Data Association
Integrated services digital network
Joint Test Action Group
Joint Test Action Group
Local area network
Last-in-first-out
Least recently used
Least-significant byte
Least-significant bit
MAC
MBS
MII
Multiply accumulate or media access control
Maximum burst size
Media-independent interface
Most-significant byte
MSB
msb
MSR
NaN
NIC
Most-significant bit
Machine state register
Not a number
Network interface card
NIU
Network interface unit
NMSI
NRT
OSI
Nonmultiplexed serial interface
Non-real time
Open systems interconnection
Peripheral component interconnect
Protocol data unit
PCI
PDU
PCR
Peak cell rate
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Table IV-1. Acronyms and Abbreviated Terms (continued)
Meaning
Term
PHY
Physical layer
PPM
RM
Pulse-position modulation
Resource management
RT
Real-time
RTOS
Rx
Real-time operating system
Receive
SAR
SCC
SCP
SCR
SDLC
SDMA
SI
Segmentation and reassembly
Serial communications controller
Serial control port
Sustained cell rate
Synchronous Data Link Control
Serial DMA
Serial interface
SIU
System interface unit
SMC
SNA
SPI
Serial management controller
Systems network architecture
Serial peripheral interface
Static random access memory
Synchronous residual time stamp
Time-division multiplexed
Terminal endpoint of an ISDN connection
Translation lookaside buffer
Time-slot assigner
SRAM
SRTS
TDM
TE
TLB
TSA
Tx
Transmit
UBR
UBR+
UART
UPM
USART
WAN
Unspecified bit rate
Unspecified bit rate with minimum cell rate guarantee
Universal asynchronous receiver/transmitter
User-programmable machine
Universal synchronous/asynchronous receiver/transmitter
Wide area network
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Chapter 14
Communications Processor Module Overview
The PowerQUICC II’s communications processor module (CPM) is a superset of the MPC860
PowerQUICC CPM, with enhancements in performance. The support for multiple HDLC channels is
enhanced to support up to 256 HDLC channels.
14.1 Features
The CPM includes various blocks to provide the system with an efficient way to handle data
communication tasks. The following is a list of the CPM’s important features.
•
Communications processor (CP)
— One instruction per clock
— Executes code from internal ROM or dual-port RAM
— 32-bit RISC architecture
— Tuned for communication environments: instruction set supports CRC computation and bit
manipulation.
— Internal timer
— Interfaces with the embedded G2core processor through a dual-port RAM and virtual DMA
channels for each peripheral controller. (Dual-port RAM size is device-specific: 24 Kbyte on
0.29µm (HiP3) devices and 32 Kbyte on 0.25µm (HiP4) devices.)
— Handles serial protocols and virtual DMA.
•
Three full-duplex fast serial communications controllers (FCCs) (two on the MPC8255) support
the following protocols:
— ATM protocol through UTOPIA interface (FCC1 and FCC2 only) (Not on MPC8250)
— IEEE802.3/Fast Ethernet
— HDLC
— Totally transparent operation
•
•
Two multi-channel controllers (MCCs) (only MCC2 on the MPC8250 and the MPC8255) that
together can handle up to 256 HDLC/transparent channels at 64 Kbps each, multiplexed on up to
eight TDM interfaces
Four full-duplex serial communications controllers (SCCs) support the following protocols:
— IEEE 802.3/Ethernet
— High level/synchronous data link control (HDLC/SDLC)
— LocalTalk (HDLC-based local area network protocol)
— Universal asynchronous receiver transmitter (UART)
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14-1
Communications Processor Module Overview
— Synchronous UART (1x clock mode)
— Binary synchronous communication (BISYNC)
— Totally transparent operation
•
Two full-duplex serial management controllers (SMCs) support the following protocols:
— GCI (ISDN interface) monitor and C/I channels
— UART
— Transparent operation
•
•
•
Serial peripheral interface (SPI) support for master or slave
2
I C bus controller
Time-slot assigner supports multiplexing of data from any of the SCCs, FCCs, SMCs, and MCCs
onto eight time-division multiplexed (TDM) interfaces. The time-slot assigner supports the
following TDM formats:
— T1/CEPT lines
— T3/E3
— Pulse code modulation (PCM) highway interface
— ISDN primary rate
— Freescale interchip digital link (IDL)
— General circuit interface (GCI)
— User-defined interfaces
•
•
•
•
Eight TC layers between the TDMs and FCC2 (MPC8264 and MPC8266 only)
Eight independent baud rate generators (BRGs)
Four general-purpose 16-bit timers or two 32-bit timers
General-purpose parallel ports—sixteen parallel I/O lines with interrupt capability
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Communications Processor Module Overview
Figure 14-1 shows the PowerQUICC II’s CPM block diagram.
Local Bus
60x Bus
To SIU
Interrupt
Bus Interface
SDMA
Controller
Internal Bus
4 Timers
Communications
Processor
Dual-Port
RAM
Parallel I/O Ports
Baud Rate Generators
ROM
Peripheral Bus
1
2
2 MCCs
3 FCCs
4 SCCs
2 SMCs
SPI
I C
2
3
Serial Interface (SI), TC layer , and Time-Slot Assigner (TSA)
Note
1
One MCC on the MPC8250 and MPC8255
Two FCCs on the MPC8255
MPC8264 and MPC8266 only
2
3
Figure 14-1. PowerQUICC II CPM Block Diagram
14.2 PowerQUICC II Serial Configurations
The PowerQUICC II offers a flexible set of communications capabilities. A subset of the possible
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14-3
Communications Processor Module Overview
Table 14-1. Possible PowerQUICC II Applications
FCC3
1
Application
MCC1 MCC2
FCC1
FCC2
SCC1 SCC2 SCC3 SCC4 SMC1 SMC2
2
ISDN router
ATM switch
ATM access
4 E1 4 E1 FEnet or ATM FEnet
UART UART UART UART
UART
ATM
ATM
FEnet
FEnet FEnet
E3 or E3 or ATM
UART
E1’s
E1’s
GSM mobile
switching center
E1’s
FEnet or ATM
Backbone
10 M 10 M
HDLC HDLC
1
Not on the MPC8250 and the MPC8255.
Not on the MPC8255.
2
14.3 Communications Processor (CP)
The communications processor (CP), also called the RISC microcontroller, is a 32-bit controller for the
CPM that resides on a separate bus from the core and, therefore, can perform tasks independent of the G2
core. The CP handles lower-layer communications tasks and DMA control, freeing the core to handle
higher-layer activities. The CP works with the peripheral controllers and parallel port to implement
user-programmable protocols and manage the serial DMA (SDMA) channels that transfer data between
the I/O channels and memory. It also manages the IDMA (independent DMA) channels and contains an
internal timer used to implement up to 16 additional software timers.
The CP’s architecture and instruction set are optimized for data communications and data processing
required by many wire-line and wireless communications standards.
14.3.1 CPM Performance Evaluation
Because the CP is a single shared resource used by all of the CPM’s communications peripherals, the
combined service requests from all of the communications peripherals must not exceed the CP’s capacity.
The amount of processing required by a particular communications peripheral depends on the mode in
which the peripheral is configured and the maximum rate at which the channel requests service. To
determine if CPM performance and bus bandwidth consumption of a given configuration is valid, users
should consult the “MPC8260 CPM Performance Evaluator,” which is located under “Application
Software” on a device’s product page at www.freescale.com.
14.3.2 Features
The following is a list of the CP’s important features.
•
•
•
•
One system clock cycle per instruction
32-bit instruction object code
Executes code from internal ROM or RAM
32-bit ALU data path
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Communications Processor Module Overview
•
•
•
64-bit dual-port RAM access
Optimized for communications processing
Performs DMA bursting of serial data from/to dual-port RAM to/from external memory. Note that
IDMA cannot burst to dual-port RAM.
14.3.3 CP Block Diagram
The CP contains the following functional units:
•
•
•
•
•
•
•
Scheduler and sequencer
Instruction decoder
Execution unit
Load/store unit (LSU)
Block transfer module (BTM)—moves data between serial FIFO and RAM
Eight general purpose registers (GPRs)
Special registers, CRC machine, HDLC framer
The CP also gives SDMA commands to the SDMA. The CP interfaces with the dual-port RAM for loading
and storing data and for fetching instructions while running microcode from dual-port RAM.
Figure 14-2 shows the CP block diagram.
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14-5
Communications Processor Module Overview
Communications Processor (CP)
Timer
Data
General-
Purpose
Registers
Special
Registers
Execution
Unit
Source Buses
Destination Bus
Block Transfer
Module
Data
Load/Store
Unit
(BTM)
Instruction
Scheduler
Sequencer
Decoder
To all units
Microcode
ROM
Address
Data
DMA
Dual-Port RAM
Address
Data
Bus
Interface
60x Bus
Local Bus
Figure 14-2. Communications Processor (CP) Block Diagram
14.3.4 G2 Core Interface
The CP communicates with the G2 core in several ways:
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Communications Processor Module Overview
•
•
Many parameters are exchanged through the dual-port RAM.
The CP can execute special commands issued by the core. These commands should only be issued
in special situations like exceptions or error recovery.
•
•
The CP generates interrupts through the SIU interrupt controller.
The G2 core can read the CPM status/event registers at any time.
14.3.5 Peripheral Interface
The CP uses the peripheral bus to communicate with all of its peripherals. Each FCC and each SCC has a
separate receive and transmit FIFOs. The FCC FIFOs are 192 bytes. The SCC FIFOs are 32 bytes. The
SMCs, SPI, and I2C are all double-buffered, creating effective FIFO sizes of two characters.
Table 14-2 shows the order in which the CP handles requests from peripherals from highest to lowest
priority.
NOTE: Emergency Prioritization
Elevation to emergency status (priority 4) is determined on per peripheral
basis and may depend on a peripheral’s mode of operation. Emergency
prioritization among peripherals maintains relative normal prioritization.
For example, simultaneous emergency requests from FCC1 transmit and
MCC2 transmit would be handled in the same order as normal requests
(FCC1 transmit).
Table 14-2. Peripheral Prioritization
Priority
Request
Reset in the CPCR or SRESET
1
2
SDMA bus error
3
Commands issued to the CPCR
IDMA[1–4] emulation (default—option 1)
1
4
5
Emergency (from FCCs, MCCs, and SCCs)
1
6
IDMA[1–4] emulation (option 2)
7
FCC1 receive
FCC1 transmit
8
2
9
MCC1 receive
10
11
12
13
14
15
MCC2 receive
2
MCC1 transmit
MCC2 transmit
FCC2 receive
FCC2 transmit
FCC3 receive
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Communications Processor Module Overview
Table 14-2. Peripheral Prioritization (continued)
Priority
Request
3
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
FCC3 transmit
SCC1 receive
SCC1 transmit
SCC2 receive
SCC2 transmit
SCC3 receive
SCC3 transmit
SCC4 receive
SCC4 transmit
SMC1 receive
SMC1 transmit
SMC2 receive
SMC2 transmit
SPI receive
SPI transmit
2
I C receive
2
I C transmit
RISC timer table
1
IDMA[1–4] emulation (option 3)
1
The priority of each IDMA channel is programmed independently. See the
2
Not on MPC8250 and MPC8255.
3
Not on MPC8255.
14.3.6 Execution from RAM
The CP has an option to execute microcode from a portion of user RAM located in the dual-port RAM. In
this mode, the CP fetches instructions from both the dual-port RAM and its own private ROM. This mode
allows Freescale to add new protocols or enhancements to the PowerQUICC II in the form of RAM
microcode packages. If preferred, the user can obtain binary microcode from Freescale and load it into the
dual-port RAM.
14.3.7 RISC Controller Configuration Register (RCCR)
The RISC controller configuration register (RCCR), as shown in Figure 14-3, configures the CP to run
microcode from ROM or RAM and controls the CP’s internal timer.
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Communications Processor Module Overview
0
1
2
7
8
9
10
11
12
13
14
15
1
2
Field TIME MCCPR
TIMEP
DR1M DR2M DR1QP
EIE
SCD
DR2QP
Reset
R/W
0000_0000_0000_0000
R/W
Addr
16
19
20
21
22
23
24
25
26
27
28
29
30
31
3
Field
Reset
R/W
ERAM
EDM1 EDM2 EDM3 EDM4 DR3M DR4M DR3QP DEM12 DEM34 DR4QP
0000_0000_0000_0000
R/W
Addr
0X119C6
1
2
3
Figure 14-3. RISC Controller Configuration Register (RCCR
.
Table 14-3. RISC Controller Configuration Register Field Descriptions
Bits
Name
Description
0
TIME
Timer enable. Enables the CP internal timer that generates a tick to the CP based on the value
programmed into the TIMEP field. TIME can be modified at any time to start or stop the scanning
of the RISC timer tables.
1
—
.29µm (HiP3) Rev A.1 and B.3 devices: Reserved, should be cleared.
MCCPR .29µm (HiP3) Rev. C.2 and .25µm (HiP4) devices: MCC request priority. Controls the priority of the
MCCs in relation to the other communication peripherals. See Table13-2. “Peripheral
Prioritization,” for more information.
0 Original CPM priority scheme. MCCx priority behaves according to Table 13-2.
1 MCC priority remains at emergency level, priority level 4.
2–7
TIMEP Timer period controls the CP timer tick. The RISC timer tables are scanned on each timer tick and
the input to the timer tick generator is the general system clock (133/166MHZ) divided by 1,024.
The formula is (TIMEP + 1) × 1,024 = (general system clock period). Thus, a value of 0 stored in
these bits gives a timer tick of 1 × (1,024) = 1,024 general system clocks and a value of 63
(decimal) gives a timer tick of 64 × (1,024) = 65,536 general system clocks.
8, 9,
24, 25
DRxM IDMAx request mode. Controls the IDMA request x (DREQx) sensitivity mode. DREQx is used to
0 DREQx is edge sensitive (according to EDMx).
1 DREQx is level sensitive.
10–11, DRxQP IDMAx request priority. Controls the priority of DREQx relative to the communications controllers.
14–15,
26–27,
30–31
00 DREQx has more priority than the communications controllers (default).
01 DREQx has less priority than the communications controllers (option 2).
10 DREQx has the lowest priority (option 3).
11 Reserved
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Communications Processor Module Overview
Table 14-3. RISC Controller Configuration Register Field Descriptions (continued)
Bits
Name
Description
12
EIE
External interrupt enable. When EIE is set, DREQ1 acts as an external interrupt to the CP.
Configure as instructed in the download process of a Freescale-supplied RAM microcode
package.
0 DREQ1 cannot interrupt the CP.
1 DREQ1 will interrupt the CP.
13
—
.29µm (HiP3) devices: Reserved
SCD
.25µm (HiP4) devices: Scheduler configuration. Configure as instructed in the download process
of a Freescale-supplied RAM microcode package.
0 Normal operation
1 Alternate configuration of the scheduler, according to bit 19 (in the ERAM field):
If RCCR[19] = 0, the jump table starts at dual-port RAM address 0x0000.
If RCCR[19] = 1, the jump table starts at dual-port RAM address 0x4000.
16–18
ERAM .29µm (HiP3) devices: Enable RAM microcode. Configure as instructed in the download process
of a Freescale-supplied RAM microcode package. (For .25µm (HiP4) devices RCCR[ERAM] =
16–19. See the following row for settings.)
000 Disable microcode program execution from the dual-port RAM.
001 Microcode uses the first 2 Kbytes of the dual-port RAM.
010 Microcode uses the first 4 Kbytes of the dual-port RAM.
011 Microcode uses the first 6 Kbytes of the dual-port RAM.
100 Microcode uses the first 8 Kbytes of the dual-port RAM.
101 Microcode uses the first 10 Kbytes of the dual-port RAM.
110 Microcode uses the first 12 Kbytes of the dual-port RAM.
111 Reserved
19
—
.29µm (HiP3) devices: Reserved
ERAM .25µm (HiP4) devices: ERAM[16-19] .Enable RAM microcode. Configure as instructed in the
download process of a Freescale-supplied RAM microcode package.
0000 Disable microcode program execution from the dual-port RAM. (That is, microcode
execution starts at ROM address 0x0000 after reset.)
In the following configurations, RAM microcode execution starts at address 0x0000 after reset:
0010 Microcode uses the first 2 Kbytes of the dual-port RAM + 8 Kbytes starting from 0x4000.
0100 Microcode uses the first 4 Kbytes of the dual-port RAM + 8 Kbytes starting from 0x4000.
0110 Microcode uses the first 6 Kbytes of the dual-port RAM + 8 Kbytes starting from 0x4000.
1000 Microcode uses the first 8 Kbytes of the dual-port RAM + 8 Kbytes starting from 0x4000.
1010 Microcode uses the first 10 Kbytes of the dual-port RAM + 8 Kbytes starting from 0x4000.
1100 Microcode uses the first 12 Kbytes of the dual-port RAM + 8 Kbytes starting from 0x4000.
In the following configurations, microcode execution starts at RAM address 0x4000 after reset:
0011 Microcode uses 2 Kbytes starting from dual-port RAM address 0x4000.
0101 Microcode uses 4 Kbytes starting from dual-port RAM address 0x4000.
0111 Microcode uses 6 Kbytes starting from dual-port RAM address 0x4000.
1001 Microcode uses 8 Kbytes starting from dual-port RAM address 0x4000.
Note: All other configurations not listed are reserved.
20, 21,
22, 23
EDMx Edge detect mode. DREQx asserts as follows:
0 Low-to-high change
1 High-to-low change
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Communications Processor Module Overview
Table 14-3. RISC Controller Configuration Register Field Descriptions (continued)
Name Description
Bits
28
asserts as follows:
0 High-to-low change
1 Low-to-high change
29
asserts as follows:
0 High-to-low change
1 Low-to-high change
14.3.8 RISC Time-Stamp Control Register (RTSCR)
timer (RTSR). The time-stamp timer is used by the ATM and the HDLC controllers. For application
(FPSMR).”
0
4
5
6
15
Field
Reset
R/W
—
RTE
RTPS (Timer Prescale)
0000_0000_0000_0000
R/W
Addr
Figure 14-4. RISC Time-Stamp Control Register (RTSCR)
Table 14-4 describes RTSCR fields.
Table 14-4. RTSCR Field Descriptions
Bits
Name
Description
0–4
5
—
Reserved
RTE Time stamp enable.
0 Disable time-stamp timer.
1 Enable time-stamp timer.
6–15
RTPS Time-stamp timer pre-scale. Must be programmed to generate a 1-µs period input clock to the
time-stamp timer. (Time-stamp frequency = (CPM frequency)/(RTPS+2)
14.3.9 RISC Time-Stamp Register (RTSR)
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Communications Processor Module Overview
0
15
Field
Time Stamp
Reset
R/W
—
R
Addr
16
31
Field
Time Stamp
Reset
R/W
—
R
Addr
0X119E2
Figure 14-5. RISC Time-Stamp Register (RTSR)
After reset, setting RTSCR[RTE] causes the time stamp to start counting microseconds from zero.
14.3.10 RISC Microcode Revision Number
Associated with each version of CPM microcode, is a number (REV_NUM) that uniquely identifies that
specific microcode. This number is hard-coded into the microcode which is stored in the CPM's internal
ROM. At power-up, the Communication Processor (CP) reads this number, and proceeds to store it into
the miscellaneous parameter RAM portion of the CPM's internal dual-port Ram (DPR). The user can then
access this location in DPR to determine which version of CPM microcode is contained in that device.
Table 14-5 describes which microcode version numbers are associated with each silicon revision.
Table 14-5. RISC Microcode Revision Number
Address
Name
Width
Description
RAM Base + 0x8AF0 REV_NUM Hword
Microcode revision number. If working with newer silicon than what is
shown below, consult the product page on the web.
For .29µm (HiP3) devices:
Rev A.1—0x0001
Rev B.2—0x003B
Rev C.2—0x007B
For .25µm (HiP4) devices: Rev A.0—0x000D
Rev B.1—0x002D
Rev C.0—0x002D
RAM Base + 0x8AF2
—
Hword
Reserved
14.4 Command Set
The core issues commands to the CP by writing to the CP command register (CPCR). The CPCR rarely
needs to be accessed. For example, to terminate the transmission of an SCC’s frame without waiting until
the end, a STOP TX command must be issued through the CP command register (CPCR).
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Communications Processor Module Overview
14.4.1 CP Command Register (CPCR)
after completing the command, thus indicating to the core that it is ready for the next command.
Subsequent commands to the CPCR can be given only after FLG is clear. However, the software reset
command issued by setting RST does not depend on the state of FLG, but the core should still set FLG
when setting RST.
0
1
5
6
10
11
15
Field RST
PAGE
Sub-block code (SBC)
—
FLG
Reset
R/W
0000_0000_0000_0000
R/W
Addr
16
17
18
25
26
27
28
31
Field
—
MCC channel number (MCN)
0000_0000_0000_0000
—
OPCODE
Reset
R/W
R/W
Addr
0x119C2
Figure 14-6. CP Command Register (CPCR)
Table 14-6 describes CPCR fields.
Table 14-6. CP Command Register Field Descriptions
Bit
Name
Description
0
RST
Software reset command. Set by the core and cleared by the CP. When this command is executed,
RST and FLG bit are cleared within two general system clocks. The CPM reset routine is
approximately 60 clocks long, but the user can begin initialization of the CPM immediately after
this command is issued.
RST is useful when the core wants to reset the registers and parameters for all the channels
2
(FCCs, SCCs, SMCs, SPI, I C, MCC) as well as the CP and RISC timer tables. However, this
command does not affect the serial interface (SIx) or parallel I/O registers.
1–5
PAGE
Indicates the parameter RAM page number associated with the sub-block being served. See the
SBC description for page numbers.
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Communications Processor Module Overview
Table 14-6. CP Command Register Field Descriptions (continued)
Bit
Name
Description
6–10
SBC
Sub-block code. Set by the core to specify the sub-block on which the command is to operate. Set
according to OPCODE[28-31]. Refer to Table 13-7.
Sub-block
Code
Page
Sub-block
Code
Page
1
FCC1
01110: ATM transmit
(OPCODE = 1010)
00100 SPI
01010
01001
10000: all other commands
1
2
FCC2
01110: ATM transmit
(OPCODE = 1010)
00101 I C
01011
01010
10001: all other commands
FCC3
SCC1
SCC2
SCC3
SCC4
SMC1
SMC2
RAND
10010
00100
00101
00110
00111
01000
01001
01110
00110 Timer
00000 MCC1
00001 MCC2
01111
11100
11101
10100
10101
10110
10111
01010
00111
01000
00111
01000
01001
01010
2
00010 IDMA1
00011 IDMA2
00111 IDMA3
01000 IDMA4
01010
11–14
15
—
Reserved
FLG
Command semaphore flag. Set by the core and cleared by the CP.
0 The CP is ready to receive a new command.
1 The CPCR contains a command that the CP is currently processing. The CP clears this bit at
the end of command execution or after reset.
16–17
18–25
—
Reserved
MCN
MCC channel number. Specifies the channel number in the case of an MCC command.
In FCC protocols, this field contains the protocol code as follows:
0x00 HDLC/transparent
3
0x0A ATM
0x0C Ethernet
Reserved
26-27
—
1
Set according to OPCODE[28-31]. If OPCODE is 1010, SBC must be 01110. Refer to Table 14-7. ATM functionality
not available on the MPC8250.
2
3
Not available on the MPC8250 and the MPC8255.
Not available on the MPC8250.
14.4.1.1 CP Commands
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Communications Processor Module Overview
Table 14-7. CP Command Opcodes
Channel
SMC
(UART/
Transparent
)
Opcode
SMC
(GCI)
2
FCC
SCC
SPI
I C
IDMA
MCC
Timer Special
0000
INIT RX
AND
INIT RX
AND
INIT RX AND
TX PARAMS
INIT RX
AND TX
INIT RX
AND TX
INIT RX
AND TX
—
INIT RX AND
TX PARAMS
—
—
TX
TX
PARAMS PARAMS PARAMS
PARAMS
PARAMS
0001
0010
0011
INIT RX
INIT RX
INIT RX
—
—
—
INIT RX
INIT RX
—
—
—
INIT RX
—
—
—
—
—
—
PARAMS
PARAMS
PARAMS
PARAMS PARAMS
PARAMS
INIT TX
INIT TX
INIT TX
INIT TX
INIT TX
INIT TX
PARAMS
PARAMS
PARAMS
PARAMS PARAMS
PARAMS
ENTER
HUNT
MODE
ENTER
HUNT
MODE
ENTER HUNT
MODE
—
—
INIT MCC RX
AND TX
PARAMS
(one
channel)1
0100
0101
STOP TX
STOP TX
STOP TX
—
—
—
—
—
—
—
—
MCC STOP TX
—
—
—
—
GRACEFUL GRACEFUL
—
INIT MCC TX
PARAMS
(one
STOP TX
STOP TX
channel)1
0110
RESTART
TX
RESTART RESTART TX
TX
—
—
—
—
INIT MCC RX
PARAMS
(one
—
—
—
channel)1
MCC RESET1
—
0111
1000
—
CLOSE
RX BD
CLOSE
RX BD
—
—
CLOSE
RX BD
CLOSE
RX BD
—
—
—
—
SET
SET
—
—
—
SET
GROUP
ADDRESS
GROUP
ADDRESS
TIMER
1001
1010
—
—
—
—
GCI
—
—
—
—
START MCC STOP RX
IDMA
—
—
—
—
TIMEOUT
ATM
RESET BCS
GCI
ABORT
REQUES
T
—
—
TRANSMIT
COMMAND
2
1011
1100
11XX
—
—
—
—
—
—
—
—
—
—
—
—
STOP
IDMA
—
—
—
—
—
—
RANDOM
NUMBER
Undefined. Reserved for use by Freescale-supplied RAM microcodes.
1
Not available on .29µm (HiP3) Rev A.1 devices.
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Communications Processor Module Overview
2
See FCC1 and FCC2 in SBC[6-10] in Table 13-6. Not available on the MPC8250.
NOTE
If a reserved command is issued, the CPM enters an unknown state that
requires an external reset to recover.
Table 14-8. Command Descriptions
Command
Description
INIT TX AND RX
PARAMS
Initialize transmit and receive parameters. Initializes the transmit and receive parameters in the
parameter RAM to the values that they had after the last reset of the CP. This command is especially
useful when switching protocols on a given peripheral controller.
INIT MCC RX AND Initialize receive and transmit parameters. Initializes the receive and transmit parameters of the
TX PARAMS —
ONE CHANNEL
peripheral controller. Differs from INIT RX AND TX PARAMS in that, for the MCCs, issuing INIT RX
AND TX PARAMS initializes 32 consecutive channels beginning with the channel number specified
in CPCR[MCN], but issuing INIT MCC RX AND TX—ONE CHANNEL initializes only the channel in
1
INIT RX PARAMS
Initialize receive parameters. Initializes the receive parameters of the peripheral controller. Note that
for the MCCs, issuing this command initializes only 32 channels at a time; see Section 28.7, “MCC
INIT MCC RX
PARAMS—
Initialize MCC receive parameters for only a single channel according to MCC channel number field.
1
ONE CHANNEL
INIT TX PARAMS
Initialize transmit parameters. Initializes the transmit parameters of the peripheral controller. Note
that for the MCCs, issuing this command initializes only 32 channels at a time; see Section 28.7,
INIT TX PARAMS— Initialize MCC transmit parameters for only a single channel according to MCC channel number
1
ONE CHANNEL
ENTER HUNT
MODE
Enter hunt mode. Causes the receiver to stop receiving and begin looking for a new frame. The exact
operation of this command may vary depending on the protocol used.
STOP TX
Stop transmission. Aborts the transmission from this channel as soon as the transmit FIFO has been
emptied. It should be used in cases where transmission needs to be stopped as quickly as possible.
Transmission proceeds when the RESTART command is issued.
GRACEFUL STOP Graceful stop transmission. Stops the transmission from this channel as soon as the current frame
TX
has been fully transmitted from the transmit FIFO. Transmission proceeds when the RESTART
command is issued and the R-bit is set in the next TxBD.
RESTART TX
CLOSE RXBD
Restart transmission. Once the STOP TX command has been issued, this command is used to
restart transmission at the current BD.
Close RxBD. Causes the receiver to close the current RxBD, making the receive buffer immediately
available for manipulation by the user. Reception continues using the next available BD. Can be
used to access the buffer without waiting until the buffer is completely filled by the SCC.
START IDMA
STOP IDMA
SET TIMER
Set timer. Activates, deactivates, or reconfigures one of the 16 timers in the RISC timer table.
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Communications Processor Module Overview
Table 14-8. Command Descriptions (continued)
Command
Description
SET GROUP
Set group address. Sets a bit in the hash table for the Ethernet logical group address recognition
function.
ADDRESS
GCI ABORT
REQUEST
GCI abort request. The GCI receiver sends an abort request on the E-bit.
GCI TIMEOUT
RESET BCS
GCI time-out. The GCI performs the timeout function.
Reset block check sequence. Used in BISYNC mode to reset the block check sequence calculation.
MCC STOP
TRANSMIT
MCC STOP
RECEIVE
1
MCC RESET
this command, software should execute the following sequence:
1 Disable the TDM by clearing the appropriate enable bit in SIxGMR[4-7] (See Table 14-4,
“SIxGMR Field Descriptions.”).
2
3
4
5
Issue the MCC RSET command.
Issue the INIT RX AND TX command.
Reprogram the specific MCC channel, global parameters, and any BDs that need to be updated.
Set the appropriate enable bit in SIxGMR[4-7]. (See Table 14-4, “SIxGMR Field Descriptions.”).
2
ATM TRANSMIT
1
Not available on .29µm (HiP3) Rev A.1 devices.
Not available on the MPC8250.
2
14.4.2 Command Register Example
To perform a complete reset of the CP, the value 0x8001_0000 should be written to the CPCR. Following
this command, the CPCR returns the value 0x0000_0000 after two clocks.
14.4.3 Command Execution Latency
The worst-case command execution latency is 200 clocks and the typical command execution latency is
about 40 clocks.
14.5 Dual-Port RAM
The CPM static RAM (24 Kbyte on 0.29µm (HiP3) devices and 32 Kbyte on 0.25µm (HiP4) devices) is
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Communications Processor Module Overview
Slave Address
CP Instruction Address
CP Data Address
Slave Data
CP Instruction
CP Data
Dual-Port RAM
24 KBytes (HiP3)
32 KBytes (HiP4)
(BDs, Buffers
and Microcode)
DMA (60x) Address
DMA (Local) Address
BTM Address
DMA (60x) Data
DMA (Local) Data
BTM Data
Figure 14-7. Dual-Port RAM Block Diagram
The dual-port RAM can be accessed by the following:
•
•
•
•
•
•
CP load/store unit
CP block transfer module (BTM)
CP instruction fetcher (when executing microcode from RAM)
G2 60x slave
SDMA 60x bus
SDMA local bus
Note that the dual-port RAM should not be cached.
Figure 14-8 shows the memory map of the dual-port RAM.
NOTE
Starting at address 0x4000 on .25µm (HiP4) devices, an extra 8 Kbytes is
available for microcode execution only and cannot be used for data buffers
or BDs. However, when not used for microcode, the extra 8 Kbytes can be
accessed from the 60x bus for general purpose internal storage. On .29µm
(HiP3) revisions of the PowerQUICC II, this space is reserved.
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Communications Processor Module Overview
0x0000
0x0800
0x1000
0x1800
0x2000
0x2800
0x3000
0x3800
0x4000
0x4800
0x5000
0x5800
0x6000
0x8000
Bank #1
BD/Data/µCode
2 KBytes
Bank #13
Microcode
Bank #9
Parameter RAM
2 KBytes
1
2 KBytes
0x8800
0x9000
Bank #10
Parameter RAM
2 KBytes
Bank #2
BD/Data/µCode
2 KBytes
Bank #14
Microcode
1
2 KBytes
(Partially Reserved)
Bank #3
BD/Data/µCode
2 KBytes
Bank #15
Microcode
1
2 KBytes
Bank #4
BD/Data/µCode
2 KBytes
Bank #16
Microcode
1
2 KBytes
Reserved
Bank #5
BD/Data/µCode
2 KBytes
Bank #6
BD/Data/µCode
2 KBytes
Reserved
0xB000
0xB800
Bank #7
BD/Data
2 KBytes
Bank #11
FCC Data
2 KBytes
Bank #8
BD/Data
2 KBytes
Bank #12
FCC Data
2 KBytes
1
Reserved on .29µm (HiP3) devices.
Figure 14-8. Dual-Port RAM Memory Map
The dual-port RAM data bus is 64-bits wide. The RAM is used for the following tasks:
•
To store parameters associated with the FCCs, SCCs, MCCs, SMCs, SPI, I2C, and IDMAs in the
parameter RAM.
•
•
•
To store buffer descriptors (BDs).
To hold data buffers (optional because data can also be stored in external memory).
For temporary storage of FCC data moving to/from an FCC FIFO (using the BTM) from/to
external memory (using SDMA).
•
•
To store RAM microcode for the CP. This feature allows Freescale to add protocols in the future.
For additional scratch-pad RAM space for user software.
The RAM is designed to serve multiple requests at the same cycle, as long as they are not in the same bank.
Only the parameters in the parameter RAM and the microcode RAM option require fixed addresses to be
used. The BDs, buffer data, and scratchpad RAM can be located in the dual-port system RAM or in any
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Communications Processor Module Overview
unused parameter RAM, such as, in the area made available when a peripheral controller or sub-block is
not being used.
Microcode can be executed from the first 12 Kbytes. To ensure an uninterrupted instruction stream (one
per cycle), no other agent is allowed to use a RAM bank used by the microcode. Since the first 12 Kbytes
are divided to six 2-Kbyte banks, RAM microcode occupies 2, 4, 6, 8, 10, or 12 Kbytes of RAM,
14.5.1 Buffer Descriptors (BDs)
The peripheral controllers (FCCs, SCCs, SMCs, MCCs, SPI, and I2C) always use BDs for controlling
Table 14-9. Buffer Descriptor Format
Address
Descriptor
Offset + 0
Offset + 2
Offset + 4
Offset + 6
Status and control
Data length
High-order buffer pointer
Low-order buffer pointer
If the IDMA is used in the buffer chaining or auto-buffer mode, the IDMA channel also uses BDs. They
NOTE
The CPM accesses BDs by initiating a DMA cycle on either the 60x or local
bus. If BDs are located in DPRAM, the CPM initiates a cycle on the 60x bus
because DPRAM is a slave device on the 60x bus. Therefore, a system
design should not plan to access the 60x bus simultaneously with DPRAM
BD fetches.
14.5.2 Parameter RAM
The CPM maintains a section of RAM called the parameter RAM, which contains many parameters for
the operation of the FCCs, SCCs, SMCs, SPI, I2C, and IDMA channels. An overview of the parameter
The exact definition of the parameter RAM is contained in each protocol subsection describing a device
that uses a parameter RAM. For example, the Ethernet parameter RAM is defined differently in some
locations from the HDLC-specific parameter RAM.
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Communications Processor Module Overview
Table 14-10. Parameter RAM
Size
(Bytes)
1
Page
Address
0x8000
Peripheral
SCC1
1
2
3
4
5
6
7
8
256
256
256
256
256
256
256
128
124
2
0x8100
0x8200
0x8300
0x8400
0x8500
0x8600
0x8700
0x8780
0x87FC
0x87FE
0x8800
0x8880
0x88FC
0x88FE
0x8900
0x89FC
0x89FE
0x8A00
0x8AE0
0x8AF0
0x8AF2
0x8AF4
0x8AF8
0x8AFC
0x8AFE
0x8B00
SCC2
SCC3
SCC4
FCC1
FCC2
2
FCC3
MCC1
3
Reserved
SMC1_BASE
IDMA1_BASE
MCC2
2
9
128
124
2
Reserved
SMC2_BASE
IDMA2_BASE
Reserved
2
10
11
252
2
SPI_BASE
IDMA3_BASE
Reserved
2
224
16
2
RISC Timers
4
REV_NUM
Reserved
Reserved
RAND
2
4
4
2
I C_BASE
2
IDMA4_BASE
Reserved
2
12-16
1280
1
2
3
4
Offset from RAM_BASE
Reserved on the MPC8255.
Reserved on the MPC8250 and the MPC8255.
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14-21
Communications Processor Module Overview
14.6 RISC Timer Tables
The CP can control up to 16 software timers that are separate from the four general-purpose timers and the
BRGs in the CPM. These timers are best used in protocols that do not require extreme precision, but in
which it is preferable to free the core from scanning the software’s timer tables. These timers are clocked
from an internal timer that only the CP uses. The following is a list of the RISC timer tables important
features.
•
•
•
•
•
•
Supports up to 16 timers.
Two timer modes: one-shot and restart.
Maskable interrupt on timer expiration.
Programmable timer resolution as fine as 7.7 µs at 133 MHz (6.17 µs at 166 MHz).
Maximum timeout period of 31.8 seconds at 133 MHz (25.5 seconds at 166 MHz).
Continuously updated reference counter.
All operations on the RISC timer tables are based on a fundamental tick of the CP’s internal timer that is
programmed in the RCCR. The tick is a multiple of 1,024 general system clocks; see Section 14.3.7,
The RISC timer tables have the lowest priority of all CP operations. Therefore, if the CP is so busy with
other tasks that it does not have time to service the timer during a tick interval, one or more timer may not
be updated accurately. This behavior can be used to estimate the worst-case loading of the CP; see
The timer table is configured using the RCCR, the timer table parameter RAM, and the RISC controller
timer event/mask registers (RTER/RTMR), and by issuing SET TIMER to the CPCR.
14.6.1 RISC Timer Table Parameter RAM
•
•
The RISC timer table parameter RAM
The RISC timer table entries
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Freescale Semiconductor
Communications Processor Module Overview
16 RISC
Timer Table
Entries
(Up to 64 Bytes)
Timer Table Base Pointer
0x8AE0
TM_BASE
RISC
Timer Table
Parameter RAM
Figure 14-9. RISC Timer Table RAM Usage
The RISC timer table parameter RAM area begins at the RISC timer base address and is used for the
Table 14-11. RISC Timer Table Parameter RAM
1
Offset
Name
Description
0x00
TM_BASE RISC timer table base address. The actual timers are a small block of memory in the dual-port
RAM. TM_BASE is the offset from the beginning of the dual-port RAM where that block resides.
Four bytes must be reserved at the TM_BASE for each timer used, (64 bytes if all 16 timers are
used). If fewer than 16 timers are used, timers should be allocated in ascending order to save
space. For example, only 8 bytes are required if two timers are needed and RISC timers 0 and
1 are enabled. TM_BASE should be word-aligned.
0x02
0x04
TM_PTR RISC timer table pointer. This value is used exclusively by the CP to point to the next timer
accessed in the timer table. It should not be modified by the user.
R_TMR
RISC timer mode register. This value is used exclusively by the CP to store the mode of the
timer—one-shot (bit is 0) or restart (bit is 1). R_TMR should not be modified by the user. The
SET TIMER command should be used instead.
0x06
0x08
0x0C
R_TMV
RISC timer valid register. Used exclusively by the CP to determine if a timer is currently
enabled. If the corresponding timer is enabled, a bit is 1. R_TMV should not be modified by the
user. The SET TIMER command should be used instead.
TM_CMD RISC timer command register. Used as a parameter location when the SET TIMER command is
issued. The user should write this location before issuing the SET TIMER command. This register
TM_CNT RISC timer internal count. A tick counter that the CP updates after each tick. The update occurs
after the CP complete scanning the timer table.All 16 timers are scanned every tick interval
regardless of whether any of them is enabled.It is updated if the CP’s internal timer is enabled,
regardless of whether any of the 16 timers are enabled and it can be used to track the number
of ticks the CP receives and responds to.TM_CNT is updated only after the last timer (timer 15)
has been serviced. If the CP is so busy with other tasks that it does not have time to service all
the timers during a tick interval, and timer 15 has not been serviced, then TM_CNT would not
be updated in that tick interval.
1
Offset from timer base address (0x8AE0)
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14-23
Communications Processor Module Overview
14.6.2 RISC Timer Command Register (TM_CMD)
Figure 14-10 shows the RISC timer command register (TM_CMD).
0
1
2
11
12
15
31
Field
Field
V
R
—
TN
16
TIMER PERIOD (TP)
Figure 14-10. RISC Timer Command Register (TM_CMD)
Table 14-12. TM_CMD Field Descriptions
Bits
Name
Description
0
V
R
Valid. This bit should be set to enable the timer and cleared to disable it.
1
Restart. Should be set for an automatic restart or cleared for a one-shot operation of the timer.
Reserved. These bits should be written with zeros.
2–11
12–15
16–31
—
TN
TP
Timer number. A value from 0–15 signifying which timer to use—an offset into the timer table entries.
Timer period. The 16-bit timeout value of the timer is zero-based. The minimum value is 1 and is
programmed by writing 0x0000 to the timer period.The maximum value of the timer is 65,536 and is
programmed by writing 0xFFFF.
14.6.3 RISC Timer Table Entries
The 16 timers are located in the block of memory following the TM_BASE location; each timer occupies
4 bytes. The first half-word forms the initial value of the timer written during the execution of the SET
TIMER command and the next half-word is the current value of the timer that is decremented until it reaches
zero. These locations should not be modified by the user. They are documented only as a debugging aid
for user code. Use the SET TIMER command to initialize table values.
14.6.4 RISC Timer Event Register (RTER)/Mask Register (RTMR)
The RTER is used to report events recognized by the 16 timers and to generate interrupts. RTER can be
read at any time. Bits are cleared by writing ones; writing zeros does not affect bit values.
The RISC timer mask register (RTMR) is used to enable interrupts that can be generated in the RTER.
Setting an RTMR bit enables the corresponding interrupt in the RTER; clearing a bit masks the
corresponding interrupt. An interrupt is generated only if the RISC timer table bit is set in the SIU interrupt
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Communications Processor Module Overview
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Field TMR TMR TMR TMR TMR TMR TMR TMR TMR TMR TMR TMR TMR TMR TMR TMR
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Reset
R/W
0000_0000_0000_0000
R/W
Addr
Figure 14-11. RISC Timer Event Register (RTER)/Mask Register (RTMR)
14.6.5 SET TIMER Command
The SET TIMER command is used to enable, disable, and configure the 16 timers in the RISC timer table
and is issued to the CPCR. This means the value 0x29E1008 should be written to CPCR. However, before
writing this value, the user should program the TM_CMD fields. See Section 14.6.2, “RISC Timer
14.6.6 RISC Timer Initialization Sequence
The following sequence initializes the RISC timers:
1. Configure RCCR to determine the preferred tick interval for the entire timer table. The TIME bit
is normally set at this time but can be set later if all RISC timers need to be synchronized.
2. Determine the maximum number of timers to be located in the timer table. Configure the
TM_BASE in the RISC timer table parameter RAM to point to a location in the dual-port RAM
with 4 × n bytes available, where n is the number of timers. If n is less than 16, use timer 0 through
timer n–1 to save space.
3. Clear the TM_CNT field in the RISC timer table parameter RAM to show how many ticks elapsed
since the RISC internal timer was enabled. This step is optional.
4. Clear RTER, if it is not already cleared. Write ones to clear this register.
5. Configure RTMR to enable the timers that should generate interrupts. Ones enable interrupts.
6. Set the RISC timer table bit in the SIU interrupt mask register (SIMR_L[RTT]) to generate
interrupts to the system. The SIU interrupt controller may require other initialization not mentioned
here.
7. Configure the TM_CMD field of the RISC timer table parameter RAM. At this point, determine
whether a timer is to be enabled or disabled, one-shot or restart, and what its timeout period should
be. If the timer is being disabled, the parameters (other than the timer number) are ignored.
8. Issue the SET TIMER command by writing 0x29E1_0008 to the CPCR.
9. Repeat the preceding two steps for each timer to be enabled or disabled.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
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14-25
Communications Processor Module Overview
14.6.7 RISC Timer Initialization Example
The following sequence initializes RISC timer 0 to generate an interrupt approximately every second using
a 133-MHz general system clock:
1. Write 111111 to RCCR[TIMEP] to generate the slowest clock. This value generates a tick every
65,536 clocks, which is every 485 µs at 133 MHz.
2. Configure the TM_BASE in the RISC timer table parameter RAM to point to a location in the
dual-port RAM with 4 bytes available. Assuming the beginning of dual-port RAM is available,
write 0x0000 to TM_BASE.
3. (Optional) Write 0x0000 to the TM_CNT field in the RISC timer table parameter RAM to see how
many ticks elapsed since the RISC internal timer was enabled.
4. Write 0xFFFF to the RTER to clear any previous events.
5. Write 0x0001 to the RTMR to enable RISC timer 0 to generate an interrupt.
6. Write 0x0002_0000 to the SIU interrupt mask register (SIMR_L) to allow the RISC timers to
generate a system interrupt. Initialize the SIU interrupt configuration register.
7. Write 0xC000_080D to the TM_CMD field of the RISC timer table parameter RAM. This enables
RISC timer 0 to timeout after 2,061(decimal) ticks of the timer. The timer automatically restarts
after it times out.
8. Write 0x29E1_0008 to the CPCR to issue the SET TIMER command.
9. Set RCCR[TIME] to enable the RISC timer to begin operation.
14.6.8 RISC Timer Interrupt Handling
The following sequence describes what normally would occur within an interrupt handler for the RISC
timer tables:
1. Once an interrupt occurs, read RTER to see which timers have caused interrupts. The RISC timer
event bits are usually cleared by this time.
2. Issue additional SET TIMER commands at this time or later, as preferred. Nothing needs to be done
if the timer is being automatically restarted for a repetitive interrupt.
3. Clear the RTT bit in the SIU interrupt pending register (SIPNR_L).
4. Execute the RTE instruction.
14.6.9 RISC Timer Table Scan Algorithm
The CP scans the timer table once every tick. It handles each of the 16 timers at its turn and checks for
other requests with higher priority to service, before handling the next one. For each valid timer in the
table, the CP decrements the count and checks for a timeout. If none occurs, the CP moves to the next timer.
If a timeout occurs, the CP sets the corresponding event bit in RTER. Then the CP checks to see if the timer
is to be restarted and if it is, the CP leaves the timer’s valid bit set in the R_TMV location and resets the
current count to the initial count. Otherwise, it clears R_TMV. Once the timer table scanning has
completed, the CP updates the TM_CNT value in the RISC timer table parameter RAM and stops working
on the timer tables until the next tick.
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Communications Processor Module Overview
If a SET TIMER command is issued, the CP makes the appropriate modifications to the timer table and
parameter RAM, but does not scan the timer table until the next tick of the internal timer. It is important
to use the SET TIMER command to properly synchronize timer table modifications to the execution of the
CP.
14.6.10 Using the RISC Timers to Track CP Loading
The RISC timers can be used to track CP loading. The following sequence provides a way to use the 16
RISC timers to determine if the CP ever exceeds the 96% utilization level during any tick interval.
Removing the timers adds a 4% margin to the CP utilization level, but the aggressive user can use this
technique to push CP performance to its limit. The user should use the standard initialization sequence and
incorporate the following differences:
1. Program the tick of the RISC timers to be every 1,024 x 16 = 16,384 system clocks.
2. Disable RISC timer interrupts, if preferred.
3. Using the SET TIMER command, initialize all 16 RISC timers to have a timer period of 0xFFFF,
which equates to 65,536.
4. Program one of the four general-purpose timers to increment once every tick. The general-purpose
timer should be free-running and should have a timeout of 65,536.
5. After a few hours of operation, compare the general-purpose timer to the current count of RISC
timer 15. If it is more than two ticks different from the general-purpose timer, the CP has, during
some tick interval, exceeded the 96% utilization level.
NOTE
General-purpose timers are up counters, but RISC timers are down counters.
The user should take this under consideration when comparing timer counts.
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14-27
Communications Processor Module Overview
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
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Freescale Semiconductor
Chapter 15
Serial Interface with Time-Slot Assigner
Figure 15-1 shows a block diagram of the time-slot assigner (TSA). Two SI blocks in the PowerQUICC II
(SI1 and SI2), can be programmed to handle eight TDM lines concurrently with the same flexibility
described in this manual. TDM channels on SI1 are referred to as TDMa1, TDMb1, TDMc1, TDMd1;
TDM channels on SI2 are TDMa2, TDMb2, TDMc2, TDMd2.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
15-1
Serial Interface with Time-Slot Assigner
Tx/Rx
RAM
Control
Route
Shadow
Address
Register
Mode
Command
Register
Status
SI RAM
Register
Register
Peripheral Bus
CPM Mux
Channel #
Clock
Route
Multi-Channel
Controllers
(MCCs)
RAM
To: SMC1 SMC2 SCC1 SCC2 SCC3 SCC4 FCC1 FCC2 FCC3
MUX MUX MUX MUX MUX MUX MUX MUX MUX
Time-Slot
Assigner (TSA)
SMC1 SMC2 SCC1
SCC2 SCC3 SCC4
MII2/ MII3
MII1/
UTOPIA
UTOPIA
1
1
8
16
Nonmultiplexed Serial Interface (NMSI) Pins
TDM A, B, C, D
Strobes
TDM A, B, C, D
Pins
Notes
The CPM mux and the MCCs are not part of the SI. (See their chapters for details.)
1
Not available on the MPC8250.
Figure 15-1. SI Block Diagram
If the TSA is not used as intended, it can be used to generate complex wave forms on dedicated output
pins. For instance, it can program these pins to implement stepper motor control or variable-duty cycle and
period control on-the-fly.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
15-2
Freescale Semiconductor
Serial Interface with Time-Slot Assigner
15.1 Features
Each SI has the following features:
•
Can connect to four independent TDM channels. Each TDM can be one of the following:
— T1 or E1 line
— Integrated services digital network primary rate (PRI)
— An ISDN basic rate–interchip digital link (IDL) channel in up to four TDM channels—each
IDL channel requires support from a separate SCC
— ISDN basic rate–general circuit interface (GCI) in up to two TDM channels—each GCI
channel requires support from a separate SMC
— E3 or DS3 clear channel on TDMa only (parallel-nibble interface)
— User-defined interfaces
•
•
•
•
•
•
•
•
•
•
•
•
Independent, programmable transmit and receive routing paths
Independent transmit and receive frame syncs allowed
Independent transmit and receive clocks allowed
Selection of rising/falling clock edges for the frame sync and data bits
Supports 1× and 2× input clocks (1 or 2 clocks per data bit)
Selectable delay (0–3 bits) between frame sync and frame start
Four programmable strobe outputs and four (2×) clock output pins
1- or 8-bit resolution in routing, masking, and strobe selection
Supports frames up to 16,384 bits long
Internal routing and strobe selection can be dynamically programmed
Supports automatic echo and loopback mode for each TDM
Maximum TDM frequency is serial-dependent:
CPM Clock
for MCCs
—
7
CPM Clock
—
—
for FCCs transparent
for FCCs HDLC
4
CPM Clock
— for FCCs HDLC nibble mode
for all other serials
6
CPM Clock
3
—
For the MCC route, the SI performs the following features:
•
•
•
Up to 128 independent communication channels (64-Kbps per channel)
Arbitrary mapping of any TDM time slots
Can connect up to four independent TDM channels. Each TDM channel can support up to 128
channels (all four channels can support up to 128 channels together).
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
15-3
Serial Interface with Time-Slot Assigner
•
•
•
Independent mapping for receive/transmit
Individual channel echo or loop mode
Global echo or loop mode through the SI
15.2 Overview
The TSA implements both internal route selection and time-division multiplexing (TDM) for multiplexed
serial channels. The TSA supports the serial bus rate and format for most standard TDM buses, including
T1 and E1 highways, pulse-code modulation (PCM) highway, and the ISDN buses in both basic and
primary rates. The two popular ISDN basic rate buses (interchip digital link (IDL) and general-circuit
interface (GCI), also known as IOM-2) are supported.
Because each SI supports four TDMs, it is possible to simultaneously support a combination of up to eight
T1 or E1 lines, and basic rate or primary rate ISDN channels.
The TDMa channel can support E3 or DS-3 rates as a clear channel in a parallel-nibble interface (FCC in
HDLC mode, clock ratio 1/6) or serial interface (clock ratio 1/4).
TSA programming is independent of the protocol used. The serial controllers can be programmed for any
synchronous protocol without affecting TSA programming. The TSA simply routes programmed portions
of the received data frame from the TDM pins to the target controller, while the target controller handles
the received data in the actual protocol.
In its simplest mode, the TSA identifies the frame using one sync pulse and one clock signal provided
externally by the user. This can be enhanced to allow independent routing of the receive and transmit data
on the TDM. Additionally, the definition of a time-slot need not be limited to 8 bits or even to a single
contiguous position within the frame. Finally, the user can provide separate receive and transmit syncs as
complex.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
15-4
Freescale Semiconductor
Serial Interface with Time-Slot Assigner
1 TDM Sync
1 TDM Clock
SCC2
SCC2
SMC1
TDM
TSA
Slot
Slot
3
3
Slot
Slot
N
N
TDM Tx
TDM Rx
SMC1
PowerQUICC II
More complex TDM example—unique routing
1 TDM Sync
1 TDM Clock
SCC2
SMC1
TSA
TDM
Slot 1 Slot
2
TDM Tx
TDM Rx
Slot
3
Slot
N
SMC1
SCC2
Even more complex TDM example—multiple time slot per
channel with varying sizes of time slots
PowerQUICC II
1 TDM Sync
1 TDM Clock
SMC1
SCC2
SCC2
TSA
TDM
TDM Tx
TDM Rx
SCC2
SMC1 SCC2
NOTE: The two shaded areas off SCC2 Rx are received as one high-speed data stream by SCC2 Rx
stored together in the same data buffers
Most complex TDM example —Totally independent Rx and Tx
PowerQUICC II
1 TDM Sync
1 TDM Clock
SCC2 SMC1
SCC2
TSA
TDM
TDM Tx
1 TDM Sync
1 TDM Clock
TDM Rx
Figure 15-2. Various Configurations of a Single TDM Channel
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
15-5
Serial Interface with Time-Slot Assigner
At its most flexible, the TSA can provide four separate TDM channels, each with independent receive and
transmit routing assignments and independent sync pulse and clock inputs. Thus, the TSA can support
eight, independent, half-duplex TDM sources, four in reception and four in transmission, using eight sync
TDMa Tx SYNC
TDMa Tx CLOCK
SCC2 SMC1
SCC2
TDMa Rx
TDMa Rx Sync
TDMa Rx Clock
TDMa Rx
TDMa
TDMb
SMC1
SCC3
TSA
TDMb Tx Sync
TDMb Tx Clock
SCC3
SCC4
TDMa Tx
TDMb Rx Sync
TDMb Rx Clock
TDMb Rx
SCC2
SMC1
Note:
SCCs can receive on one TDM and transmit on another (SCC2 and SCC3).
Figure 15-3. Dual TDM Channel Example
In addition to channel programming, the TSA supports up to four strobe outputs that may be asserted on a
bit or byte basis. These strobes are completely independent from the channel routing used by the SCCs and
SMCs. The strobe outputs are useful for interfacing to other devices that do not support the multiplexed
interface or for enabling/disabling three-state I/O buffers in a multiple-transmitter architecture. Notice that
open-drain programming on the TXDx pins that supports a multiple-transmitter architecture occurs in the
parallel I/O block. These strobes can also be used for generating output wave forms to support such
applications as stepper-motor control.
Most TSA programming is done in the two 256- × 16-bit SIx RAMs. These SIx RAMs are directly
accessible by the core in the internal register section of the PowerQUICC II and are not associated with
the dual-port RAM. One SIx RAM is always used to program the transmit routing; the other is always used
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
15-6
Freescale Semiconductor
Serial Interface with Time-Slot Assigner
to program the receive routing. SIx RAMs can be used to define the number of bits/bytes to be routed to
the MCC, FCC, SCC, or SMC and determine when external strobes are to be asserted and negated.
The size of the SIx RAM available for time-slot programming depends on the user’s configuration. The
user defines how many of the 256 entries are related to each TDM. The resolution of the division is by
fractions of 32. If on-the-fly changes are allowed, the SIx RAM entries are reduced according to the user’s
programming. The maximum frame length that can be supported in any configuration is 16,384 bits.
The maximum external serial clock that may be an input to the TSA is CPM CLK/3.
The SI supports two testing modes—echo and loopback.
•
The echo mode provides a return signal from the physical interface by retransmitting the signal it
has received. The physical interface echo mode differs from the individual FCC or SCC echo mode
in that it can operate on the entire TDM signal rather than just on a particular serial channel.
•
Loopback mode causes the physical interface to receive the same signal it is sending. The SI
loopback mode checks more than the individual serial loopback; it checks both the SI and the
internal channel routes.
NOTE
The flexibility described in the preceding section can be applied to each of
the four TDM channels and to all serial interfaces independently.
15.3 Enabling Connections to TSA
Each serial interface can be independently enabled to connect to one of the following: TSA, UTOPIA, MII,
or dedicated external pins. Note the following:
•
Each FCC can be connected to a dedicated MII or one of four TDMs. FCC1 can also be connected
to a 8-/16-bit UTOPIA level-2 interface; FCC2 can also be connected to an 8-bit UTOPIA level-2
interface.
•
•
Each SCC or SMC can be connected to one of four TDMs or to its own set of pins.
The MCC can be connected to one of the four TDMs with different numbers of channels.
The four TDMs are connected to four independent TDM interfaces. Figure 15-4 illustrates the connection
between the TSA and the serial interfaces. The connection is made by programming the CPM mux. See
Chapter 16, “CPM Multiplexing.” Once the connections are made, the exact routing decisions are made in
the SIx RAM.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
15-7
Serial Interface with Time-Slot Assigner
TDM a channels
TDM b channels
TDM c channels
TDM d channels
MCCx
TDM a,b,c,d Enable = 1
En
En
En
En
TDM a Pins
TDM b Pins
TDM c Pins
TDM d Pins
Time-Slot
Assigner
SIx RAM
FC1 = 0
MII1/UTOPIA 16
FCC1
FCC2
FCC3
SCC1
SCC2
FC2 = 00
FC3 = 0
SC1 = 0
SC2 = 0
SC3 = 0
MII2/UTOPIA 8
MII3
SCC1 pins
SCC2 pins
SCC3 pins
SCC3
SC4 = 0
SCC4 pins
SMC1 pins
SMC2 pins
SCC4
SMC1
SMC2
SMC1 = 0
SMC2 = 0
In the CPM mux
Figure 15-4. Enabling Connections to the TSA
15.4 Serial Interface RAM
Each SI has a transmit RAM and a receive RAM, each with four banks of 64 halfword entries that enable
it to control TDM channel routing to all serial devices, including the MCCs. The SIx RAMs are
uninitialized after power-on reset; unwanted results can occur if the user does not program them before
enabling the multiplexed channels.
Each 16-bit SI RAM entry defines the routing of 1–8 bits or bytes at a time. In addition to the routing, up
to four strobe pins (logic OR of four strobes in the transmit RAM and four in receive RAM) can be asserted
according to the programming of the RAMs. The four SIx RAM banks can be configured in many different
ways to support various TDM channels. The user can define the size of each SIx RAM that is related to a
certain TDM channel by programming the starting bank of that TDM. Programming the starting shadow
whether this RAM has a shadow for changing SIx RAM entries while the TDM channel is active. This
reduces the number of available SIx RAM entries for that TDM.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
15-8
Freescale Semiconductor
Serial Interface with Time-Slot Assigner
15.4.1 One Multiplexed Channel with Static Frames
The example in Figure 15-5. shows one of many possible settings. With this configuration, the SIx RAM
has 256 entries for transmit data and strobe routing and 256 entries for receive data and strobe routing. This
configuration should be chosen only when one TDM is required and the routing on that TDM does not
need to be dynamically changed. The number of entries available in the SIx RAM is determined by the
user.
Framing Signals
SIx RAM address:
0
L1TCLKax
L1TSYNCax
(each entry is16 bits wide)
256 Entries
TXa
Route
511
1024
L1RCLKax
L1RSYNCax
256 Entries
RXa
Route
1535
Figure 15-5. One TDM Channel with Static Frames and Independent Rx and Tx Routes
15.4.2 One Multiplexed Channel with Dynamic Frames
In the configuration shown in Figure 15-6., one multiplexed channel has 256 entries for transmit data and
strobe routing and 256 entries for receive data and strobe routing. Each RAM has two sections, the
current-route RAM and a shadow RAM for changing serial routing dynamically.
After programming the shadow RAM, the user sets SIxCMDR[CSRxn] for the associated channel. When
the next frame sync arrives, the SI automatically exchanges the current-route RAM for the shadow RAM.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
15-9
Serial Interface with Time-Slot Assigner
Framing Signals
256
SIx RAM Address:
0
(each entry is 16 Bits Wide)
L1TCLKax
L1TSYNCax
128 Entries
TXa
Route
255
511
1024
1280
L1RCLKax
L1RSYNCax
128 Entries
RXa
Route
1279
1535
Figure 15-6. One TDM Channel with Shadow RAM for Dynamic Route Change
This configuration should be chosen when only one TDM is needed, but dynamic rerouting may be needed
on that TDM. Similarly, for two TDM channels, the number of SIx RAM entries are reduced for every
TDM channel programmed for shadow mode.
15.4.3 Programming SIx RAM Entries
The programming of each entry in the SIx RAM determines the routing of the serial bits (or bit groups)
and the assertion of strobe outputs. If MCC is set, the entry refers to the corresponding MCC; otherwise,
The use of MCC slots is restricted for slots with lengths up to a single byte. For channels, that require more
than a single byte, superchannel or slot splitting is mandatory.
0
1
2
3
4
5
6
7
10 11
13
14
15
Field MCC = 0
SWTR
SSEL1 SSEL2 SSEL3 SSEL4
0
CSEL
CNT
CNT
BYT LST
BYT LST
MCC = 1 LOOP/ECHO SUPER
MCSEL
R/W
Figure 15-7. SIx RAM Entry Fields
R/W
Addr
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
15-10
Freescale Semiconductor
Serial Interface with Time-Slot Assigner
Table 15-1. SIx RAM Entry (MCC = 0)
Description
Bits
Name
0
MCC The entry controls the functionality of the other bits in the SIx RAM entry.
0 The entry refers to other serial controllers (FCCs, SCCs, SMC, according to the CSEL field).
1 The entry refers to the MCC.
1
SWTR Switch Tx and Rx. Valid only in the receive route RAM and ignored in the transmit route RAM. SWTR
affects the operation of both L1RXD and L1TXD. SWTR is set only in special situations where the
user prefers to receive data from a transmit pin and transmit data on a receive pin. For instance,
where devices A and B are connected to the same TDM, each with different time-slots. Normally,
there is no opportunity for stations A and B to communicate with each other directly over the TDM,
because they both receive the same TDM receive data and transmit on the same TDM transmit
signal.
0 Normal operation of L1TXD and L1RXD.
1 Data for this entry is sent on L1RXD and received from L1TXD.
2–5
SSELx Strobe select. There are four strobes available that can be assigned to the receive RAM and
asserted/negated with the received clock of this TDM channel (L1RCLKx). They can also be
assigned to the transmit RAM and asserted/negated with the transmit clock of this TDM channel
(L1TCLKx). Each bit corresponds to the value the strobe should have during this bit/byte group.
There are four strobe pins for all eight strobe bits in the SIx RAM entries, so the value on a strobe
pin is the logical OR of the Rx and Tx RAM entry strobe bits. Multiple strobes can be asserted
simultaneously. A strobe configured to be asserted in consecutive SIx RAM entries remains
continuously asserted for both entries. A strobe asserted on the last entry in a table is negated after
the last entry is processed.
Note: Each strobe is changed with the corresponding RAM clock and is output only if the
corresponding parallel I/O is configured as a dedicated pin. If a strobe is programmed to be
asserted in more than one set of entries (the SI route entries for more then one TDM channel
select the same strobe), the assertion of the strobe corresponds to the logical OR of all
possible sources. This use of strobes is not useful for most applications. A given strobe should
be selected in only one set of SIx RAM entries.
6
—
Reserved, should be cleared.
7–10
CSEL Channel select. In some MCC cases, when SI frame length is shorter than the gap between sync
signals, an underrun condition may appear even though the aggregate serial rate is low. To avoid
these cases, add entries with unsupported bits (CSEL = 0000 in SI entry) in the end of the SI frame.
Thus SI frame length should match the gap between syncs.
0000 The bit/byte group is not supported by the PowerQUICC II. The transmit data pin is
three-stated and the receive data pin is ignored.
0001 The bit/byte group is routed to SCC1.
0010 The bit/byte group is routed to SCC2.
0011 The bit/byte group is routed to SCC3.
0100 The bit/byte group is routed to SCC4.
0101 The bit/byte group is routed to SMC1.
0110 The bit/byte group is routed to SMC2.
0111 The bit/byte group is not supported by the PowerQUICC II. This code is also used in SCIT
1000 Reserved.
1001 The bit/byte group is routed to FCC1.
1010 The bit/byte group is routed to FCC2.
1011 The bit/byte group is routed to FCC3.
11xx Reserved.
11–13
CNT Count. Indicates the number of bits/bytes (according to the BYT bit) that the routing and strobe
select of this entry controls. 000 = 1 bit/byte; 111= 8 bits/bytes.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
15-11
Serial Interface with Time-Slot Assigner
Table 15-1. SIx RAM Entry (MCC = 0) (continued)
Description
Bits
Name
14
BYT Byte resolution
0 Bit resolution. The CNT value indicates the number of bits in this group.
1 Byte resolution. The CNT value indicates the number of bytes in this group.
15
LST Last entry in the RAM. Whenever SIx RAM is used, LST must be set in one of the Tx or Rx entries
of each group. Even if all entries of a group are used, this bit must still be set in the last entry.
0 Not the last entry in this section of the route RAM.
1 Last entry in this RAM. After this entry, the SI waits for the sync signal to start the next frame.
Note: There must be only an even number of entries in an SIx RAM frame, because LST is active
only in odd-numbered entries (assuming the entry count starts with 0). Therefore, to obtain
an even number of entries, an entry may need to be split into two entries.
Also note that, to avoid errors in switching to and from shadow SI RAM, the last entry in SI RAM
should not be programmed to 1-bit resolution (i.e. CNT = 000 and BYT = 0).
Figure 15-8 shows how SWTR can be used.
L1RXD
L1TXD
L1RXD
L1TXD
Rx
Tx
Rx
Tx
Rx
Tx
Tx
Rx
Station A
Station B
Station A
Station B
Tx and Rx SIx RAMn[SWTR] = 0
Tx and Rx SIx RAMn[SWTR] = 1
Figure 15-8. Using the SWTR Feature
The SWTR option lets station B listen to transmissions from station A and send data to station A. To do
this, station B would set SWTR in its receive route RAM. For this entry, receive data is taken from the
L1TXD pin and data is sent on the L1RXD pin. If the user wants to listen only to station A transmissions
and not send data on L1RXD, the CSEL bits in the corresponding transmit route RAM entry should be
cleared to prevent transmission on the L1RXD pin.
Station B can transmit data to station A by setting the SWTR bit of the entry in its receive route RAM.
Data is sent on L1RXD rather than L1TXD, according to the transmit route RAM. Note that this
configuration could cause collisions with other data on L1RXD unless an available (quiet) time slot is
used. To transmit on L1RXD and not receive data on L1TXD, clear the CSEL bits in the receive route
RAM.
NOTE
If the transmit and receive sections of the TDM do not use a common clock
source, the SWTR feature can cause erratic behavior. Also note, this feature
does not work with nibble operation.
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15-12
Freescale Semiconductor
Serial Interface with Time-Slot Assigner
Table 15-2. SIx RAM Entry (MCC = 1)
Description
Bits
Name
0
1
MCC If MCC =1, the other SIx RAM entries in this table are valid:
LOOP/ Channel loopback or echo.
ECHO 0 Normal mode of operation.
1 Operation depends on the following configurations:
In the receive SIx RAM, this bit selects loopback mode for this MCC channel. The channel’s
transmit data is sent to both the receiver’s input and to the data output line.
In the transmit SIx RAM, this bit selects echo mode for this MCC channel. The channel’s receive
data is sent both to the transmitter’s line and to the receiver’s input.
To use the loop/echo modes, program the receive and transmit SIx RAMs identically, except that the
LOOP/ECHO bit should be set in only one of the entry pairs; that is, select only one of the modes
(echo or loopback, not both) per MCC slot. Also, the receive and transmit clocks must be identical.
2
0 The current entry refers to a regular channel.
1 The current entry refers to a super channel.
3–10 MCSEL MCC channel select. Indicates the MCC channel the bit/byte group is routed to.
• 0000_0000 selects channel 0
• 1000_000 selects channel 128 (MPC8250 and MPC8255 have only MCC2)
• 1111_1111, selects channel 255
For SI1 use values 0–127 and for SI2 use values 128–255.
Note: SI2 always reads the leftmost bit as set, even if the user has not set this bit. This ensures SI2
operates with MCC2 channel numbers.
11–13
CNT Count.
If SUPER = 0 (normal mode), CNT indicates the number of bits/bytes (according to the BYT bit) that
the routing select of this entry controls. 000 = 1 bit/byte; 111 = 8 bits/bytes.
If SUPER = 1 (MCC super channel), CNT and BYT together indicate whether the current entry is
the first byte of the MCC super channel.
CNT= 000 and BYT = 1—The current entry is the first byte of this MCC super channel.
CNT= 111 and BYT = 0—The current entry is not the first byte of this MCC super channel.
Note: Because all SIx RAM entries relating to super channels must be 1-byte in resolution, only the
above two combinations of CNT and BYT are allowed when SUPER = 1.
14
15
BYT Byte resolution
0 Bit resolution. The CNT value indicates the number of bits in this group.
1 Byte resolution. The CNT value indicates the number of bytes in this group.
LST
Last entry in the RAM. Whenever the SIx RAM is used, LST must be set in one of the Tx or Rx
entries of each group. Even if all entries of a group are used, LST must still be set in the last entry.
0 Not the last entry in this section of the route RAM.
1
Last entry in this RAM. After this entry, the SI waits for the sync signal to start the next frame.
Note: There must be only an even number of entries in an SIx RAM frame, because LST is active
only in odd-numbered entries (assuming the entry count starts with 0). Therefore, to obtain
an even number of entries, an entry may need to be split into two entries.
Also note that, to avoid errors in switching to and from shadow SI RAM, the last entry in SI RAM
should not be programmed to 1-bit resolution (i.e. CNT = 000 and BYT = 0).
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
15-13
Serial Interface with Time-Slot Assigner
15.4.4 SIx RAM Programming Example
10-bit IDL bus format. In this example, the TSA supports the B1 channel with SCC2, the D channel with
SCC1, the first 4 bits of the B2 channel with an external device (using a strobe to enable the external
device), and the last 4 bits of B2 with SMC1. Additionally, the TSA marks the D channel with another
strobe signal.
First, divide the frame from the start (the sync) to the end of the frame according to the support that is
required:
•
•
•
•
•
•
8 bits (B1)—SCC2
1 bit (D)—SCC1 + strobe 1
1 bit—no support
4 bits (B2)—strobe 2
4 bits (B2)—SMC1
1 bit (D)—SCC1 + strobe 1
Each of these six divisions can be supported by a single SIx RAM entry. Thus, six SIx RAM entries are
Table 15-3. SIx RAM Entry Descriptions
SIx RAM Entry
Entry
Number
MCC
SWTR
SSEL
CSEL
CNT
BYT
LST
Description
0
1
2
3
4
5
0
0
0
0
0
0
0
0
0
0
0
0
0000
1000
0000
0100
0000
1000
0010
0001
0000
0000
0101
0001
000
000
000
011
011
000
1
0
0
0
0
0
0
0
0
0
0
1
8-bit SCC2
1-bit SCC1 strobe1
1-bit no support
4-bit strobe2
4-bit SMC1
1-bit SCC1 strobe1
NOTE
IDL requires the same routing for both receive and transmit., Therefore, an
exact duplicate of the above entries should be written to both the receive and
transmit sections of the SIx RAM. Then SIxMR[CRTx] can be used to
instruct the SIx RAM to use the same clock and sync to simultaneously
control both sets of SIx RAM entries.
15.4.5 Static and Dynamic Routing
The SIx RAM has two operating modes for the TDMs:
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
15-14
Freescale Semiconductor
Serial Interface with Time-Slot Assigner
•
•
Static routing. The number of SIx RAM entries is determined by the banks the user relates to the
corresponding TDM and is divided into two parts (Rx and Tx). The following sequence must be
followed to program the routing entries.
— All serial devices connected to the TDM must be disabled.
— SI routing can be modified.
— All appropriate serial devices connected to the TDM must be reenabled.
Dynamic routing. A TDM’s routing definition can be modified while FCCs, MCCs, SCCs, or
SMCs are connected to the TDM. The number of SIx RAM entries is determined by the banks the
user relates to the corresponding TDM channel and is divided into four parts (Rx, Rx shadow, Tx,
and Tx shadow).
Dynamic changes divide portions of the SIx RAM into current-route and shadow RAM. Once the
current-route RAM is programmed, the TSA and SI channels are enabled, and TSA operation begins.
When a change in routing is required, the shadow RAM must be programmed with the new route and
SIxCMDR[CSRxn] must be set. As a result, as soon as the corresponding sync arrives the SI exchanges
the shadow RAM with the current-route RAM and resets CSRxn to indicate that the operation is complete.
At this time, the user may change the routing again. Notice that the original current-route RAM is now the
two TDM channels both with half of the RAM as a shadow.
If for instance one TDM with dynamic changes is programmed to own all four banks, and the shadow is
programmed to the last two banks, the initial current-route RAM addresses in the SIx RAM are as follows.
•
•
0–255: TXa route
1024–1279: RXa route
The initial shadow RAMs are at addresses:
•
•
256–511: TXa route
1280–1535: RXa route
The user can read any RAM at any time, but for proper SI operation the user must not attempt to write the
current-route RAM. The SIx status register (SIxSTR) can be read to find out which part of the RAM is the
current-route RAM. The user can also externally connect one of the strobes to an interrupt pin to generate
an interrupt on a particular SIx RAM entry starting or ending execution by the TSA.
NOTE
The current-route and shadow SI RAMs of a given TDMx should be
contiguous; that is, the current-route and shadow SI RAMs of differing
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
15-15
Serial Interface with Time-Slot Assigner
Initial State
RAM Address:
0
127 128
64 TXa
Shadow
255 256
383 384
511
1)
64 TXb
Route
64 TXb
Shadow
64 TXa
Route
The TSA uses the first part of
the RAM, and the shadow is
the second part of the RAM.
CSRxn = 0
L1TCLKa
L1TSYNCa
L1TCLKb
L1TSYNCb
Framing Signals:
CSRRa=0
CSRTa=0
CSRRb=0
CSRTb=0
1024
1151 1152
12791280
1407 1408
1535
RAM Address:
64 RXb
Route
64 RXb
Shadow
64 RXa
Route
64 RXa
Shadow
L1RCLKa
L1RCLKb
Framing Signals:
RAM Address:
L1RSYNCa
L1RSYNCb
0
127 128
255 256
383 384
511
Programming
2)
64 TXb
Route
64 TXb
Shadow
64 TXa
Route
64 TXa
Shadow
The user programs the
shadow RAM for the new
Rx and Tx route and sets
CSRxn.
L1TCLKa
L1TSYNCa
L1TCLKb
L1TSYNCb
Framing Signals:
CSRRa=1
CSRTa=1
CSRRb=1
CSRTb=1
1024
1151 1152
12791280
1407 1408
1535
RAM Address:
64 RXb
Route
64 RXb
Shadow
64 RXa
Route
64 RXa
Shadow
L1RCLKa
L1RCLKb
Framing Signals:
RAM Address:
L1RSYNCa
L1RSYNCb
0
127 128
255 256
383 384
511
Swap
3)
64 TXb
Route
64 TXb
Shadow
64 TXa
Shadow
64 TXa
Route
The SI swaps between
the shadow and the
current-route RAMs
and resets CSRxn.
L1TCLKa
L1TSYNCa
L1TCLKb
L1TSYNCb
Framing Signals:
RAM Address:
1024
64 RXa
Shadow
1151 1152
12791280
1407 1408
1535
CSRRa=0
CSRTa=0
CSRRb=0
CSRTb=0
64 RXb
Route
64 RXb
Shadow
64 RXa
Route
L1RCLKa
L1RSYNCa
L1RCLKb
L1RSYNCb
Framing Signals:
Figure 15-9. Example: SIx RAM Dynamic Changes, TDMa and b, Same SIx RAM Size
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
15-16
Freescale Semiconductor
Serial Interface with Time-Slot Assigner
15.5 Serial Interface Registers
The serial interface registers are described in the following sections. The MCC configuration registers,
NOTE
The programming of SI registers and SIx RAM must be coherent with the
MCCF programming.
15.5.1 SI Global Mode Registers (SIxGMR)
The SI global mode registers (SIxGMR), shown in Figure 15-10., defines the activation state of the TDM
channels for each SI.
0
1
2
3
4
5
6
7
Field
Reset
R/W
STZD
STZC
STZB
STZA
END
ENC
ENB
ENA
0000_0000
R/W
Figure 15-10. SI Global Mode Registers (SIxGMR)
Addr
Table 15-4. SIxGMR Field Descriptions
Description
Bit
Name
0–3
STZx Program L1TXDx to zero for TDM a, b, c or d
0 Normal operation
1 L1TXDx = 0 until serial clocks are available, which is useful for GCI activation. See
4–7
ENx Enable TDMx. Note that enabling a TDM is the last step in initialization.
0 TDM channel x is disabled. The SIx RAMs and routing for TDMx are in a state of reset, but all
other SI functions still operate.
1 All TDMx functions are enabled.
15.5.2 SI Mode Registers (SIxMR)
There are eight SI mode registers (SIxMR), shown in Figure 15-11., one for each TDM channel (SIxAMR,
SIxBMR, SIxCMR, and SIxDMR). They are used to define SI operation modes and allow the user (with
SIx RAM) to support any or all of the ISDN channels independently when in IDL or GCI mode. Any extra
serial channel can then be used for other purposes.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
15-17
Serial Interface with Time-Slot Assigner
0
1
3
4
5
6
7
8
9
10
11
12
13
14
15
Field
Reset
R/W
—
SADx
SDMx
RFSDx
DSCx CRTx SLx CEx FEx GMx
TFSDx
0000_0000_0000_0000
R/W
Addr
Figure 15-11. SI Mode Registers (SIxMR)
Table 15-5. SIxMR Field Descriptions
Bits
Name
Description
0
—
Reserved. Should be cleared.
1–3
SADx Starting bank address for the RAM of TDM a, b, c or d. These three bits define the starting bank
address of the SIx RAM section that belongs to TDMx channel.
Note: As noted previously, the SIx RAM contains four banks of 64 entries for receive and four banks
of 64 entries for transmit. The starting bank address of each TDM can be programmed with a
granularity of 32 entries. The user can put the shadow RAM section of the same TDM on the
same bank, but the user cannot put two different TDMs on the same bank.
The last entry of a certain TDM is determined by the LST bit in the SIx RAM entry. The user must set
LST within the entries of SIx RAM blocks for every TDM used, that is, before the starting address of
the next TDM.
000 First bank, first 32 entries
001 First bank, second 32 entries
010 Second bank, first 32entries
011 Second bank, second 32 entries
100 Third bank, first 32 entries
101 Third bank, second 32 entries
110 Fourth bank, first 32 entries
111 Fourth bank, second 32 entries
4–5
SDMx SI Diagnostic Mode for TDM a, b, c or d
00 Normal operation.
01 Automatic echo. In this mode, the TDM transmitter automatically retransmits the TDM received
data on a bit-by-bit basis. The receive section operates normally, but the transmit section can only
retransmit received data. In this mode, the L1GRx line is ignored.
10 Internal loopback. In this mode, the TDM transmitter output is internally connected to the TDM
receiver input (L1TXDx is connected to L1RXDx). The receiver and transmitter operate normally.
The data appears on the L1TXDx pin and in this mode, L1RQx is asserted normally. The L1GRx
line is ignored.
11 Loopback control. In this mode, the TDM transmitter output is internally connected to the TDM
receiver input (L1TXDx is connected to L1RXDx). The transmitter output (L1TXDx) and L1RQx
are inactive. This mode is used to accomplish loopback testing of the entire TDM without affecting
the external serial lines.
Note: In modes 01, 10, and 11, the receive and transmit clocks should be identical.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
15-18
Freescale Semiconductor
Serial Interface with Time-Slot Assigner
Table 15-5. SIxMR Field Descriptions (continued)
Description
Bits
Name
6–7 RFSDx Receive frame sync delay for TDM a, b, c, or d. Determines the number of clock delays between the
receive sync and the first bit of the receive frame. Even if CRTx is set, these bits do not control the
delay for the transmit frame.
00 No bit delay. The first bit of the frame is transmitted/received on the same clock as the sync; use
for GCI. If frame sync delay is not used and if a frame sync is issued early during the last bit of
the previous frame, data corruption could occur on all subsequent frames. To avoid this problem,
program a 1, 2, or 3-bit sync delay.
01 1-bit delay. Use for IDL
10 2-bit delay
11 3-bit delay
8
9
DSCx Double speed clock for TDM a, b, c or d. Some TDMs, such as GCI, define the input clock to be twice
as fast as the data rate and this bit controls this option.
0 The channel clock (L1RCLKx and/or L1TCLKx) is equal to the data clock. Use for IDL and most
TDM formats.
1 The channel clock rate is twice the data rate. Use for GCI.
Note: When an SI is in 2X mode (DSC=1), the SI does not ignore sync signals asserted in the last
phase of the last clock cycle of the frame.
CRTx Common receive and transmit pins for TDM a, b, c or d. Useful when the transmit and receive
sections of a given TDM use the same clock and sync signals. In this mode, L1TCLKx and
L1TSYNCx can be used for their alternate functions.
0 Separate pins. The receive section of this TDM uses L1RCLKx and L1RSYNCx pins for framing
and the transmit section uses L1TCLKx and L1TSYNCx for framing.
1 Common pins. The receive and transmit sections of this TDM use L1RCLKx as clock pin of
channel x and L1RSYNCx as the receive and transmit sync pin. Use for IDL and GCI. RFSD and
TFSD are independent of one another in this mode.
10
11
SLx Sync level for TDM a, b, c, or d.
0 The L1RSYNCx and L1TSYNCx signals are active on logic “1”.
1 The L1RSYNCx and L1TSYNCx signals are active on logic “0”.
CEx Clock edge for TDM a, b, c or d. The function depends on DSCx.
When DSCx = 0:
0 The data is sent on the rising edge of the clock and received on the falling edge (use for IDL).
1 The data is sent on the falling edge of the clock and received on the rising edge.
When DSCx = 1:
0 The data is sent on the rising edge of the clock and received on the rising edge.
1 The data is sent on the falling edge of the clock and received on the falling edge (use for GCI).
12
FEx Frame sync edge for TDM a, b, c or d. Determines whether L1RSYNCx and L1TSYNCx pulses are
0 Falling edge. Use for IDL and GCI.
1 Rising edge.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
15-19
Serial Interface with Time-Slot Assigner
Table 15-5. SIxMR Field Descriptions (continued)
Description
Bits
Name
13
GMx Grant mode for TDM a, b, c, or d
0 GCI/SCIT mode. The GCI/SCIT D channel grant mechanism for transmission is internally
supported. The grant is one bit from the receive channel. This bit is marked by programming the
channel select bits of the SIx RAM with 0111 to assert an internal strobe on it. See
1 IDL mode. A grant mechanism is supported if the corresponding CMXSCR[GRx] bit is set. The
grant is a sample of L1GRx while L1RSYNCx is asserted. This grant mechanism implies the IDL
access controls for transmission on the D channel. See Section 15.6.2, “IDL Interface
14–15 TFSDx Transmit frame sync delay for TDM a, b, c or d. Determines the number of clock delays between the
00 No bit delay. The first bit of the frame is transmitted/received on the same clock as the sync. If
frame sync delay is not used and if a frame sync is issued early during the last bit of the
previous frame, data corruption could occur on all subsequent frames. To avoid this problem,
program a 1, 2, or 3-bit sync delay.
01 1-bit delay
10 2-bit delay
11 3-bit delay
L1CLK
(CE=0)
End of Frame
L1SYNC
(FE=1)
Data
Bit-0
Bit-1
Bit-2
Bit-3
Bit-4
Bit-5
Bit-0
One-Clock Delay from Sync Latch to First Bit of Frame
Figure 15-12. One-Clock Delay from Sync to Data (xFSD = 01)
Figure 15-13 shows the elimination of the single-clock delay shown in Figure 15-12 by clearing xFSD.
L1CLK
(CE=0)
L1SYNC
(FE=1)
Data
Bit-0
Bit-1
Bit-2
Bit-3
Bit-4
Bit-0
Bit-1
Bit-2
No Delay from Sync Latch to First Bit of Frame
Figure 15-13. No Delay from Sync to Data (xFSD = 00)
Figure 15-14 shows the effects of changing FE when CE = 1 with a 1-bit frame sync delay.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
15-20
Freescale Semiconductor
Serial Interface with Time-Slot Assigner
CE=1
xFSD=01
L1CLK
L1SYNC
L1SYNC
(FE=0)
(FE=1)
L1TxD
(Bit-0)
L1ST
(On Bit-0)
L1ST Driven from Clock High for Both FE Settings
Rx Sampled Here
Figure 15-14. Falling Edge (FE) Effect When CE = 1 and xFSD = 01
Figure 15-15 shows the effects of changing FE when CE = 0 with a 1-bit frame sync delay.
CE=0
xFSD=01
L1CLK
L1SYNC
L1SYNC
(FE=0)
(FE=1)
L1TXD
(Bit-0)
L1ST is Driven from Clock Low
in Both the FE Settings
L1ST
(On Bit-0)
Rx Sampled Here
Figure 15-15. Falling Edge (FE) Effect When CE = 0 and xFSD = 01
Figure 15-16 shows the effects of changing FE when CE = 1 with no frame sync delay.
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15-21
Serial Interface with Time-Slot Assigner
CE=1
xFSD=00
(FE=0)
L1CLK
L1SYNC
L1TXD
(Bit-0)
The L1ST is Driven from Sync.
Data is Driven from Clock Low.
L1ST
(On Bit-0)
Rx Sampled Here
L1SYNC
(FE=0)
L1TXD
(Bit-0)
L1ST is Driven from Clock High.
L1ST
(On Bit-0)
L1SYNC
(FE=1)
L1TXD
(Bit-0)
Both Data Bit-0 and L1ST are
Driven from Sync.
L1ST
(On Bit-0)
Rx Sampled Here
L1SYNC
(FE=1)
L1TXD
(Bit-0)
L1ST and Data Bit-0 is Driven
from Clock Low.
L1ST
(On Bit-0)
Figure 15-16. Falling Edge (FE) Effect When CE = 1 and xFSD = 00
Figure 15-17 shows the effects of changing FE when CE = 0 with no frame sync delay.
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Freescale Semiconductor
Serial Interface with Time-Slot Assigner
CE=0
xFSD=00
L1CLK
L1SYNC
(FE=1)
L1TXD
(Bit-0)
The L1ST is Driven from Sync.
Data is Driven From Clock High.
L1ST
(On Bit-0)
Rx Sampled Here
L1SYNC
(FE=1)
L1TXD
(Bit-0)
L1ST is Driven from Clock Low.
L1ST
(On Bit-0)
L1SYNC
(FE=0)
L1TXD
(Bit-0)
Both the Data and L1ST from Sync
when Asserted during Clock High.
L1ST
(On Bit-0)
L1SYNC
(FE=0)
L1TXD
(Bit-0)
Both the Data and L1ST from the Clock
when Asserted during Clock Low.
L1ST
(On Bit-0)
Figure 15-17. Falling Edge (FE) Effect When CE = 0 and xFSD = 00
15.5.3 SIx RAM Shadow Address Registers (SIxRSR)
The SIx RAM shadow address registers (SIxRSR), shown in Figure 15-18, define the starting addresses of
the shadow section in the SIx RAM for each of the TDM channels.
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15-23
Serial Interface with Time-Slot Assigner
0
1
3
4
5
7
8
9
11
12
13
15
Field
Reset
R/W
—
SSADA
—
SSADB
—
SSADC
—
SSADD
0000_0000_0000_0000
R/W
Addr
Figure 15-18. SIx RAM Shadow Address Registers (SIxRSR)
Table 15-6. SIxRSR Field Descriptions
Bits
Name
Description
0, 4, 8,
12
—
Reserved. Should be cleared.
1–3, SSADx Starting bank address for the shadow RAM of TDM a, b, c, or d. Defines the starting bank address
5–7,
9–11,
13–15
of the shadow SIx RAM section that belongs to the corresponding TDM channel.
Note: As noted before, the SIx RAM contain four banks of 64 entries for receive and four banks of
64 entries for transmit.
In spite of the above, the starting bank address of each TDM can be programmed by the user in a
granularity of 32 entries, but the user cannot put two different TDMs on the same bank.
The user can put the shadow RAM section of the same TDM on the same bank.
The last entry of a certain TDM frame is determined by the LST bit in the SIx RAM entry. The user
must set this bit within the entries of SIx RAM shadow blocks for every TDM used. That means
before the starting address of the next TDM.
15.5.4 SI Command Register (SIxCMDR)
The SI command registers (SIxCMDR), shown in Figure 15-19, allow the user to dynamically program the
SIx RAM. When the user sets bits in the SIxCMDR, the SIx switches to the shadow SIx RAM at the end
of the current-route RAM programming frame. For more information about dynamic programming, see
0
1
2
3
4
5
6
7
Field CSRRA
CSRTA
CSRRB
CSRTB
CSRRC
CSRTC
CSRRD
CSRTD
Reset
R/W
0000_0000
R/W
Figure 15-19. SI Command Register (SIxCMDR)
Addr
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Freescale Semiconductor
Serial Interface with Time-Slot Assigner
Table 15-7. SIxCMDR Field Description
Description
Bits
Name
0, 2, 4, CSRRx Change shadow RAM for TDM a, b, c, or d receiver. Set CSRRx causes the SI receiver to replace
6
the current route RAM with the shadow RAM. Set by the user and cleared by the SI.
0 The receiver shadow RAM is not valid. The user can write into the shadow RAM to program a
new routing.
1 The receiver shadow RAM is valid. The SI exchanges between the RAMs and take the new
receive routing from the receiver shadow RAM. Cleared as soon as the switch has completed.
1, 3, 5, CSRTx Change shadow RAM for TDM a, b, c, or d transmitter. Set CSRTx causes the SI transmitter to
7
replace the current route RAM with the shadow RAM. Set by the user and cleared by the SI.
0 The transmitter shadow RAM is not valid. The user can write into the shadow RAM to program a
new routing.
1 The transmitter shadow RAM is valid. The SI exchanges between the RAMs and take the new
transmitter routing from the receiver shadow RAM. Cleared as soon as the switch has completed.
15.5.5 SI Status Registers (SIxSTR)
The SI status register (SIxSTR), shown in Figure 15-20, identifies the current-route RAM. SIxSTR values
are valid only when the corresponding SIxCMDR bit = 0.
0
1
2
3
4
5
6
7
Field CRORA
CROTA
CRORB
CROTB
CRORC
CROTC
CRORD
CROTD
Reset
R/W
0000_0000
R
Addr
Figure 15-20. SI Status Registers (SIxSTR)
Table 15-8. SIxSTR Field Descriptions
Description
0, 2, 4, CROR Current-route original receiver. Determines whether the current-route receiver RAM is the original
Bits
Name
6
x
or the shadow.
0 The current-route receiver RAM is the lower address area.
1 The current-route receiver RAM is the upper address area.
1, 3, 5, CROTx Current-route original transmitter. Determines whether the current-route transmitter RAM is the
7
original or the shadow.
0 The current-route transmitter RAM is the lower address area.
1 The current-route transmitter RAM is the upper address area.
15.6 Serial Interface IDL Interface Support
The IDL interface is a full-duplex ISDN interface used to connect a physical layer device to the
PowerQUICC II. The PowerQUICC II supports both the basic and primary rate of the IDL bus. In the basic
rate of IDL, data on three channels (B1, B2, and D) is transferred in a 20-bit frame, providing a full-duplex
bandwidth of 160 Kbps. The PowerQUICC II is an IDL slave device that is clocked by the IDL bus master
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15-25
Serial Interface with Time-Slot Assigner
(physical layer device) and has separate receive and transmit sections. Although the PowerQUICC II has
eight TDMs, it can support only four independent IDL buses (limited by the number of serials that support
ISDN TE
NT
IDL1
IDL2
S/T
S/T
S/T
S/T
U
U
U
S/T
PowerQUICC II
Interfaces
Interfaces
Figure 15-21. Dual IDL Bus Application Example
15.6.1 IDL Interface Example
application, the IDL interface is used to connect the 2B+D channels between the PowerQUICC II,
CODEC, and S/T transceiver. One of the PowerQUICC II’s SCCs is configured to HDLC mode to handle
the D channel; another PowerQUICC II’s SCC is used to rate adapt the terminal data stream over the first
B channel. That SCC is configured for HDLC mode if V.120 rate adaptation is required. The second B
channel is then routed to the CODEC as a digital voice channel, if preferred. The SPI is used to send
initialization commands and periodically check status from the S/T transceiver. The SMC connected to the
terminal is configured for UART.
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Serial Interface with Time-Slot Assigner
System Bus (ROM and RAM)
PCM
CODEC/Filter
Monocircuit
POTS
B1
ASYNC
SMC1
SCC1
SPI
PowerQUICC II
IDL
SMC2
SCC2
SCC3
(Data)
TSA
B2+D
ICL
(Control)
S/T
Transceiver
4 wire
Ethernet
B1+B2+D
Ethernet
PHY
LAN
Figure 15-22. IDL Terminal Adaptor
The PowerQUICC II can identify and support each IDL channel or can output strobe lines for interfacing
devices that do not support the IDL bus. The IDL signals for each transmit and receive channel are
Table 15-9. IDL Signal Descriptions
Signal
Description
L1RCLKx
IDL clock; input to the PowerQUICC II.
L1RSYNCx IDL sync signal; input to the PowerQUICC II. This signal indicates that the clock periods following
the pulse designate the IDL frame.
L1RXDx
L1TXDx
L1RQx
L1GRx
IDL receive data; input to the PowerQUICC II. Valid only for the bits supported by the IDL; ignored
for any other signals present.
IDL transmit data; output from the PowerQUICC II. Valid only for the bits that are supported by the
IDL; otherwise, three-stated.
IDL request permission to transmit on the D channel; output from the PowerQUICC II on the L1RQx
pin.
IDL grant permission to transmit on the D Channel; input to the PowerQUICC II on the L1TSYNCx
pin.
Note: x = a, b, c, and d for TDMa, TDMb, TDMc, and TDMd (for SI1 and SI2).
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Serial Interface with Time-Slot Assigner
The basic rate IDL bus has the three following channels:
•
•
•
B1 is a 64-Kbps bearer channel
B2 is a 64-Kbps bearer channel
D is a 16-Kbps signaling channel
There are two definitions of the IDL bus frame structure—8 and 10 bits. The only difference between them
L1CLK
L1SYNC
10-Bit IDL
L1RXD
L1TXD
B1
B1
D1
B2
B2
D2
D2
D1
8-Bit IDL
L1RXD
L1TXD
B1
B1
B2
B2
D1 D2
D1 D2
Notes:
1. Clocks are not to scale.
2. L1RQx and L1GRx are not shown.
Figure 15-23. IDL Bus Signals
NOTE
Previous versions of Freescale IDL-defined bit functions called auxiliary
(A) and maintenance (M) were removed from the IDL definition when it
was concluded that the IDL control channel would be out-of-band. These
functions were defined as a subset of the Freescale SPI format called serial
control port (SCP). To implement the A and M bits as originally defined,
program the TSA to access these bits and route them transparently to an
SCC or SMC. Use the SPI to perform out-of-band signaling.
The PowerQUICC II supports all channels of the IDL bus in the basic rate. Each bit in the IDL frame can
be routed to any SCC and SMC or can assert a strobe output for supporting an external device. The
PowerQUICC II supports the request-grant method for contention detection on the D channel of the IDL
basic rate and when the PowerQUICC II has data to transmit on the D channel, it asserts L1RQx. The
physical layer device monitors the physical layer bus for activity on the D channel and indicates that the
channel is free by asserting L1GRx. The PowerQUICC II samples the L1GRx signal when the IDL sync
signal (L1RSYNCx) is asserted. If L1GRx is asserted, the PowerQUICC II sends the first zero of the
opening flag in the first bit of the D channel. If a collision is detected on the D channel, the physical layer
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Serial Interface with Time-Slot Assigner
device negates L1GRx. The PowerQUICC II then stops sending and retransmits the frame when L1GRx
is reasserted. This procedure is handled automatically for the first two buffers of a frame.
For the primary rate IDL, the PowerQUICC II supports up to four 8-bit channels in the frame, determined
by the SIx RAM programming. To support more channels, the user can route more than one channel to
each SCC and the SCC treats it as one high-speed stream and store it in the same data buffers (appropriate
only for transparent data). Additionally, the PowerQUICC II can be used to assert strobes for support of
additional external IDL channels.
The IDL interface supports the CCITT I.460 recommendation for data-rate adaptation since it separately
accesses each bit of the IDL bus. The current-route RAM specifies which bits are supported by the IDL
interface and by which serial controller. The receiver only receives bits that are enabled by the receiver
route RAM. Otherwise, the transmitter sends only bits that are enabled by the transmitter route RAM and
three-states L1TXDx.
15.6.2 IDL Interface Programming
To program an IDL interface, first program SIxMR[GMx] to the IDL grant mode for that channel. If the
receive and transmit sections interface to the same IDL bus, set SIxMR[CRTx] to internally connect the
Rx clock and sync signals to the transmit section. Then, program the SIx RAM used for the IDL channels
Define the IDL frame structure by programming SIxMR[xFSDx] to have a 1-bit delay from frame sync to
data, SIxMR[FEx] to sample on the falling edge, and SIxMR[CEx] to transmit on the rising edge of the
clock. Program the parallel I/O open-drain register so that L1TXDx is three-stated when inactive; see
definitions of IDL, 8 or 10 bits, are implemented by simply modifying the SIx RAM programming. In both
cases, L1GRx is sampled while L1TSYNCx is asserted and transferred to the D-channel SCC as a grant
indication.
implement an IDL bus using SCC1, SCC2, and SMC1 connected to TDMa1 as follows:
Table 15-10. SIx RAM Entries for an IDL Interface
SIx RAM Entry
Entry
Number
MCC
SWTR
SSEL
CSEL
CNT
BYT
LST
Description
0
1
2
0
0
0
0
0
0
0000
0000
0000
0010
0001
0000
000
000
000
1
0
0
0
0
0
8-bit SCC2
1-bit SCC1
1-bit no
support
3
0
0
0000
0101
011
0
0
4-bit SMC1
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Serial Interface with Time-Slot Assigner
Table 15-10. SIx RAM Entries for an IDL Interface (continued)
SIx RAM Entry
Entry
Number
MCC
SWTR
SSEL
CSEL
CNT
BYT
LST
Description
4
5
0
0
0
0
0000
1000
0101
0001
011
000
0
0
0
1
4-bit SMC1
1-bit SCC1
strobe1
2. CMXSI1CR = 0x00. TDMA receive clock is CLK1.
3. CMXSMR = 0x80. SMC1 is connected to the TSA.
4. CMXSCR = 0xC040_0000. SCC1 and SCC2 are connected to the TSA. SCC1 supports the grant
mechanism because it handles the D channel.
5. SI1AMR = 0x0145. TDMA grant mode is used with 1-bit frame sync delay in Tx and Rx and
common receive-transmit mode.
6. Set PPARA[6–9]. Configures L1TXDa[0], L1RXDa[0], L1TSYNCa, and L1RSYNCa.
7. Set PSORA[6–9]. Configures L1TXDa[0], L1RXDa[0], L1TSYNCa, and L1RSYNCa.
8. Set PDIRA[9]. Configures L1TXDa[0].
9. Set PODRA[9]. Configures L1TXDa[0] to an open-drain output.
10. Set PPARC[30,31]. Configures L1TCLKa and L1RCLKa.
11. Clear PDIRC[30,31] Configures L1TCLKa and L1RCLKa.
12. Clear PSORC[30,31]. Configures L1TCLKa and L1RCLKa.
13. Set PPARB[17]. Configures L1RQa.
14. Clear PSORB[17]. Configures L1RQa.
15. Set PDIRB[17]. Configures L1RQa.
16. Set PPARD[13]. Configures L1ST1.
17. Clear PSORD[13]. Configures L1ST1.
18. Set PDIRD[13]. Configures L1ST1.
19. SI1CMDR is not used.
20. SI1STR does not need to be read.
21. Configure the SCC1 for HDLC operation (to handle the LAPD protocol of the D channel), and
configure SCC2 and SMC1 as preferred.
22. SI1GMR = 0x01. Enable TDM A (one static TDM).
23. Enable SCC1, SCC2 and SMC1.
15.7 Serial Interface GCI Support
The PowerQUICC II fully supports the normal mode of the GCI, also known as the ISDN-oriented
modular revision 2.2 (IOM-2), and the SCIT. The PowerQUICC II also supports the D-channel access
control in S/T interface terminals using the command/indication (C/I) channel
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Serial Interface with Time-Slot Assigner
The GCI bus consists of four lines—two data lines, a clock, and a frame synchronization line. Usually, an
8-kHz frame structure defines the various channels within the 256-kbps data rate. The PowerQUICC II
supports two (limited by the number of SMCs) independent GCI buses, each with independent receive and
transmit sections. The interface can also be used in a multiplexed frame structure on which up to eight
physical layer devices multiplex their GCI channels. In this mode, the data rate would be 2,048 kbps.
In the GCI bus, the clock rate is twice the data rate. The SI divides the input clock by two to produce the
data clock. The PowerQUICC II also has data strobe lines and the 1× data rate clock L1CLKOx output
pins. These signals are used for interfacing devices to GCI that do not support the GCI bus. Table 15-11
describes GCI signals for each transmit and receive channel.
Table 15-11. GCI Signals
Signal
Description
L1RSYNCx
Used as a GCI sync signal; input to the PowerQUICC II. This signal indicates that the clock periods
following the pulse designate the GCI frame.
L1RCLKx
Used as a GCI clock; input to the PowerQUICC II. The L1RCLKx signal frequency is twice the data
clock.
L1RXDx
L1TXDx
Used as a GCI receive data; input to the PowerQUICC II.
Used as a GCI transmit data; open-drain output. Valid only for the bits that are supported by the IDL;
otherwise, three-stated.
L1CLKOx
Optional signal; output from the PowerQUICC II. This 1× clock output is used to clock devices that do
not interface directly to the GCI. If the double-speed clock is used, (DSCx bit is set in the SIxMR), this
output is the L1RCLKx divided by 2; otherwise, it is simply a 1× output of the L1RCLKx signal.
Note: x = a, b, c, and d for TDMa, TDMb, TDMc, and TDMd (for SI1 and SI2).
L1CLK
(2X the data rate)
L1SYNC
L1RXD
L1TXD
B1
B1
B2
B2
M (Monitor)
M (Monitor)
D1 D2
D1 D2
C/I
C/I
A E
A E
Notes: Clock is not to scale.
L1CLKO is not shown.
Figure 15-24. GCI Bus Signals
In addition to the 144-Kbps ISDN 2B+D channels, the GCI provides five channels for maintenance and
control functions:
•
•
B1 is a 64-Kbps bearer channel
B2 is a 64-Kbps bearer channel
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Serial Interface with Time-Slot Assigner
•
•
•
M is a 64-Kbps monitor channel
D is a 16-Kbps signaling channel
C/I is a 48-Kbps C/I channel (includes A and E bits)
The M channel is used to transfer data between layer 1 devices and the control unit (the CPU); the C/I
channel is used to control activation/deactivation procedures or to switch test loops by the control unit. The
M and C/I channels of the GCI bus should be routed to SMC1 or SMC2, which have modes to support the
channel protocols. The PowerQUICC II can support any channel of the GCI bus in the primary rate by
modifying SIx RAM programming.
The GCI supports the CCITT I.460 recommendation as a method for data rate adaptation since it can
access each bit of the GCI separately. The current-route RAM specifies which bits are supported by the
interface and which serial controller support them. The receiver only receives the bits that are enabled by
the SIx RAM and the transmitter only transmits the bits that are enabled by the SIx RAM and does not
drive L1TXDx. Otherwise, L1TXDx is an open-drain output and should be pulled high externally.
The PowerQUICC II supports contention detection on the D channel of the SCIT bus. When the
PowerQUICC II has data to transmit on the D channel, it checks a SCIT bus bit that is marked with a
special route code (usually, bit 4 of C/I channel 2). The physical layer device monitors the physical layer
bus for activity on the D channel and indicates on this bit that the channel is free. If a collision is detected
on the D channel, the physical layer device sets bit 4 of C/I channel 2 to logic high. The PowerQUICC II
then aborts its transmission and retransmits the frame when this bit is set again. This procedure is
automatically handled for the first two buffers of a frame.
15.7.1 SI GCI Activation/Deactivation Procedure
In the deactivated state, the clock pulse is disabled and the data line is at a logic one. The layer 1 device
activates the PowerQUICC II by enabling the clock pulses and by an indication in the channel 0 C/I
channel. The PowerQUICC II reports to the core (via a maskable interrupt) that a valid indication is in the
SMC RxBD.
When the core activates the line, the data output of L1TXDn is programmed to zero by setting
SIxGMR[STZx]. Code 0 (command timing TIM) is transmitted on channel 0 C/I channel to the layer 1
device until STZx is reset. The physical layer device resumes the clock pulses and gives an indication in
the channel 0 C/I channel. The core should reset STZx to enable data output.
15.7.2 Serial Interface GCI Programming
The following sections describe serial interface GCI programming.
15.7.2.1 Normal Mode GCI Programming
The user can program and configure the channels used for the GCI bus interface. First, the SIxMR register
to the GCI/SCIT mode for that channel must be programmed, using the DSCx, FEx, CEx, and RFSDx bits.
This mode defines the sync pulse to GCI sync for framing and data clock as one-half the input clock rate.
The user can program more than one channel to interface to the GCI bus. Also, if the receive and transmit
section are used for interfacing the same GCI bus, the user internally connects the receive clock and sync
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Serial Interface with Time-Slot Assigner
signals to the SIx RAM transmit section, using the CRTx bits. The user should then define the GCI frame
routing and strobe select using the SIx RAM.
When the receive and transmit section uses the same clock and sync signals, these sections should be
programmed to the same configuration. Also, the L1TXDx pin in the I/O register should be programmed
to be an open-drain output. To support the monitor and the C/I channels in GCI, those channels should be
routed to one of the SMCs. To support the D channel when there is no possibility of collision, the user
should clear the SIxMR[GRx] bit corresponding to the SCC that supports the D channel.
15.7.2.2 SCIT Programming
For interfacing the GCI/SCIT bus, SIxMR must be programmed to the GCI/SCIT mode. The SIx RAM is
programmed to support a 96-bit frame length and the frame sync is programmed to the GCI sync pulse.
Generally, the SCIT bus supports the D channel access collision mechanism. For this purpose, the user
should program the CRTx bits so the receive and transmit sections use the same clock and sync signals and
program the GRx bits to transfer the D channel grant to the SCC that supports this channel. The received
(grant) bit should be marked by programming the channel select bits of the SIx RAM to 0b0111 for an
internal assertion of a strobe on this bit. This bit is sampled by the SI and transferred to the D-channel SCC
as the grant. The bit is generally bit 4 of the C/I in channel 2 of the GCI, but any other bit can be selected
using the SIx RAM.
For example, assuming that SCC1 is connected to the D channel, SCC2 to the B1 channel, and SMC2 to
the B2 channel, SMC1 is used to handle the C/I channels, and the D-channel grant is on bit 4 of the C/I on
SCIT channel 2, the initialization sequence is as follows:
and 1024, respectively.
Table 15-12. SIx RAM Entries for a GCI Interface (SCIT Mode)
SIx RAM Entry
Entry
Number
MCC
SWTR
SSEL
CSEL
CNT
BYT
LST
Description
0
1
2
3
4
5
6
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0000
0000
0000
0000
0000
0000
0000
0000
0010
0110
0101
0001
0101
0000
0000
0111
000
000
000
001
101
110
001
000
1
1
1
0
0
1
0
0
0
0
0
0
0
0
0
1
8 Bits SCC2
8 Bits SMC2
8 Bits SMC1
2 Bits SCC1
6 Bits SMC1
Skip 7 bytes
Skip 2 bits
D grant bit
2. SI1AMR = 0x00c0. TDMa is used in double speed clock and common Rx/Tx modes. SCIT mode
is used in this example.
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15-33
Serial Interface with Time-Slot Assigner
NOTE
If SCIT mode is not used, delete the last three entries of the SIx RAM, divide
one entry into two and set the LST bit in the new last entry.
3. CMXSMR = 0x88. SMC1 and SMC2 are connected to the TSA.
4. CMXSCR = 0xC040_0000. SCC2 and SCC1 are connected to the TSA. SCC1 supports the grant
mechanism since it is on the D channel.
5. CMXSI1CR = 0x00. TDMa uses CLK1.
6. Set PPARA[6–9]. Configures L1TXDa[0], L1RXDa[0], L1TSYNCa and L1RSYNCa.
7. Set PSORA[6–9]. Configures L1TXDa[0], L1RXDa[0], L1TSYNCa and L1RSYNCa.
8. Set PDIRA[9]. Configures L1TXDa[0].
9. Set PODRA[9]. Configures L1TXDa[0] to an open-drain output.
10. Set PPARC[30,31]. Configures L1TCLKa and L1RCLKa.
11. Clear PDIRC[30,31]. Configures L1TCLKa and L1RCLKa.
12. Clear PSORC[30,31]. Configures L1TCLKa and L1RCLKa.
13. Set PPARB[17]. Configures L1CLKO and L1RQa.
14. Clear PSORB[17]. Configures L1CLKO and L1RQa.
15. Set PDIRB[17]. Configures L1CLKO and L1RQa.
16. If the 1x GCI data clock is required, set PBPAR bit 16 and PBDIR bit 16 and clear PSORB 16,
which configures L1CLKOa as an output.
17. Configure SCC1 for HDLC operation (to handle the LAPD protocol of the D channel). Configure
SMC1 for SCIT operation and configure SCC2 and SMC2 as preferred.
18. SI1GMR = 0x11. Enable TDMa (one static TDM), STZ for TDMa.
19. SI1CMDR is not used.
20. SI1STR does not need to be read.
21. Enable the SCC1, SCC2, SMC1 and SMC2.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
15-34
Freescale Semiconductor
Chapter 16
CPM Multiplexing
The CPM multiplexing logic (CMX) connects the physical layer—UTOPIA, MII, modem lines, TDM
lines and proprietary serial lines to the FCCs, SCCs and SMCs. The CMX features the following two
modes:
•
•
In NMSI mode, the CMX allows all serial devices to be connected to their own set of individual
pins. Each serial device that connects to the external world in this way is said to connect to a
nonmultiplexed serial interface (NMSI). In the NMSI configuration, the CMX provides a flexible
clocking assignment for each FCC, SCC and SMC from a bank of external clock pins and/or
internal BRGs.
In TDM mode, the CMX performs the connection of the serial devices to the SIs for using the
time-slot assigner (TSA). This allows any combination of MCCs, FCCs, SCCs, and SMCs to
multiplex data on any of the eight TDM channels. The CMX connects the serial device only to the
TSA in the SIx. The actual multiplexing of the TDM is made by programming the SIx RAM. In
TDM mode, all other pins used in NMSI mode are available for other purposes. See Chapter 15,
The CMX also allows the user to route the multiple-PHY address to FCC1 or to FCC2 in various
combinations, allowing the use of both FCCs in multiple-PHY mode.
NOTE
The CMX serves both SI1 and SI2. When the user programs the CMX to
connect a serial device to the SI, the CMX connects that serial device to both
SIs. Programming both SIs to use one serial device in the same time slot
causes erratic behavior.
Figure 16-1 shows a block diagram of the CMX.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
16-1
CPM Multiplexing
Register Bus
CPM MUX
SIx
UTOPIA
SMC
Clock
Register
(CMXSMR)
SCC
Clock
Register
(CMXSCR)
FCC
Clock
Register
(CMXFCR)
Clock
Address
Register
2
Registers
(CMXSIxCR)
(CMXUAR)
BRGs
MCCs
To Serials:
SMC1 SMC2 SCC1 SCC2 SCC3 SCC4 FCC1 FCC2 FCC3
MUX MUX MUX MUX MUX MUX MUX MUX MUX
MUX
Time-Slot Assigner
SIx
1
TC Layer (Option for FCC2 Only)
SMC1 SMC2 SCC1 SCC2 SCC3 SCC4 MII1/
8/16
MII2/ MII3
UTOPIA UTOPIA
2
2
8
Clocks
Nonmultiplexed Serial Interface (NMSI) Pins
Note:
TDM Ax, Bx, Cx, Dx TDM Ax, Bx, Cx, Dx
1
MPC8264 and MPC8266 only.
Not on MPC8250.
Pins
Strobes
2
Figure 16-1. CPM Multiplexing Logic (CMX) Block Diagram
16.1 Features
The NMSI mode supports the following:
•
Each FCC, SCC, and SMC can be programmed independently to work with a serial device’s own
set of pins in a non-multiplexed manner.
•
•
Each FCC can be connected to its own MII (media-independent interface).
FCC1 can also be connected to an 8- or 16-bit ATM UTOPIA level-2 interface (not on the
MPC8250).
•
•
FCC2 can also be connected also to an 8-bit ATM UTOPIA level-2 interface (not on the
MPC8250).
FCC2 can also be connected also to the TC layer (MPC8264 and MPC8266 only).
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
16-2
Freescale Semiconductor
CPM Multiplexing
•
•
•
Each SCC can have its own set of modem control pins.
Each SMC can have its own set of four pins.
Each FCC, SCC, and SMC can be driven from a bank of twenty clock pins or a bank of eight BRGs.
The multiple-PHY addressing selection supports the following options for FCC1 and FCC2:
•
In master mode:
— FCC1 connect up to 31 PHYs and FCC2 connect up to 7 PHYs.
— FCC1 connect up to 15 PHYs and FCC2 connect up to 15 PHYs.
— FCC1 connect up to 7 PHYs and FCC2 connect up to 31 PHYs.
In slave mode:
•
— FCC1 connect up to 31 PHYs and FCC2 connect to 0 PHYs.
— FCC1 connect up to 15 PHYs and FCC2 connect up to 1 PHYs.
— FCC1 connect up to 7 PHYs and FCC2 connect up to 3 PHYs.
— FCC1 connect up to 3 PHYs and FCC2 connect up to 7 PHYs.
— FCC1 connect up to 1 PHYs and FCC2 connect up to 15 PHYs.
— FCC1 connect to 0 PHYs and FCC2 connect up to 31 PHYs.
16.2 Enabling Connections to TSA or NMSI
Each serial device can be independently enabled to connect to the TSA or to dedicated external pins, as
also be connected to an 8- or 16-bit UTOPIA level-2 interface. FCC2 can also be connected to an 8-bit
UTOPIA level-2 interface. Each SCC or SMC can be connected to the eight TDMs or to its own set of
pins. Once connections are made to the TSA, the exact routing decisions are made in the SIx RAMs.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
16-3
CPM Multiplexing
TDM a channels
TDM b channels
TDM c channels
TDM d channels
MCCs
TDM a,b,c,d Enable = 1
En
En
En
En
TDM a Pins
TDM b Pins
TDM c Pins
TDM d Pins
Time-Slot
Assigners
SI RAMs
FC1 = 0
MII1/UTOPIA 8/16/M-phy
FCC1
FC2 = 00
FC3 = 0
SC1 = 0
SC2 = 0
SC3 = 0
MII2/UTOPIA 8/M-phy
MII3
FCC2
FCC3
SCC1
SCC2
SCC1 Pins
SCC2 Pins
SCC3 Pins
SCC3
SC4 = 0
SCC4 Pins
SMC1 Pins
SMC2 Pins
SCC4
SMC1
SMC2
SMC1 = 0
SMC2 = 0
Figure 16-2. Enabling Connections to the TSA
16.3 NMSI Configuration
The CMX supports an NMSI mode for each of the FCCs, SCCs, and SMCs. Each serial device is
connected independently either to the NMSI or to the TSA using the clock route registers. The user should
note, however, that NMSI pins are multiplexed with other functions at the parallel I/O lines. Therefore, if
a combination of TDM and NMSI channels are used, consult the PowerQUICC II’s pinout to determine
which FCC, SCC, and SMC to connect and where to connect them.
The clocks provided to the FCCs, SCCs, and SMCs are derived from a bank of 8 internal BRGs and 20
external CLK pins; see Figure 16-3. There are two main advantages to the bank-of-clocks approach. First,
a serial device is not forced to choose a serial device clock from a predefined pin or BRG; this allows a
flexible pinout-mapping strategy. Second, a group of serial receivers and transmitters that needs the same
clock rate can share the same pin. This configuration leaves additional pins for other functions and
minimizes potential skew between multiple clock sources.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
16-4
Freescale Semiconductor
CPM Multiplexing
BRG5
BRG6
BRG7
BRG8
BRGO5
BRGO6
BRGO7
BRGO8
BRG1
BRG2
BRG3
BRG4
Rx
Tx
FCC1
FCC2
FCC3
SCC1
SCC2
SCC3
SCC4
BRGO1
BRGO2
BRGO3
BRGO4
Rx
Tx
Rx
Tx
CLK1
CLK2
CLK3
CLK4
Rx
Tx
CLK5
CLK6
CLK7
CLK8
CLK9
CLK10
Rx
Tx
Bank of Clocks
Selection Logic
Rx
Tx
CLK11
CLK12
(Partially filled cross-switch logic
programmed in the CMX registers.)
CLK13
CLK14
Rx
Tx
CLK15
CLK16
CLK17
SMC1
SMC2
CLK18
CLK19
CLK20
Rx Tx Rx Tx Rx Tx Rx Tx Rx Tx Rx Tx Rx Tx Rx Tx
TDMA1 TDMB1 TDMC1 TDMD1 TDMA2 TDMB2 TDMC2 TDMD2
Figure 16-3. Bank of Clocks
The eight BRGs also make their clocks available to external logic, regardless of whether the BRGs are
being used by a serial device. Notice that the BRG outputs are multiplexed with other functions; thus, all
multiplexing.
There are two restrictions in the bank-of-clocks mapping:
•
•
Only four of the twenty sources can be connected to any given FCC or SCC receiver or transmitter.
The SMC transmitter and receiver share the same clock source when connected to the NMSI.
Table 16-1 shows the clock source options for the serial controllers and TDM channels.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
16-5
CPM Multiplexing
Clock
Table 16-1. Clock Source Options
CLK
BRG
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
SCC1 Rx
SCC1 Tx
SCC2 Rx
SCC2 Tx
SCC3 Rx
SCC3 Tx
SCC4 Rx
SCC4 Tx
FCC1 Rx
FCC1 Tx
FCC2 Rx
FCC2 Tx
FCC3 Rx
FCC3 Tx
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
TDMA1
Rx
V
V
TDMA1 Tx
V
V
TDMB1
Rx
V
V
TDMB1 Tx
V
V
TDMC1
Rx
V
V
V
V
TDMC1 Tx
V
V
V
V
TDMD1
Rx
V
V
V
TDMD1 Tx
V
V
V
TDMA2
Rx
TDMA2 Tx
TDMB2
Rx
V
V
TDMB2 Tx
V
V
TDMC2
Rx
V
TDMC2 Tx
V
TDMD2
Rx
V
V
TDMD2 Tx
SMC1 Rx
SMC1 Tx
SMC2 Rx
SMC2 Tx
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
16-6
Freescale Semiconductor
CPM Multiplexing
NOTE
After a clock source is selected, the clock is given an internal name. For the
FCCs and SCCs, the names are RCLKx and TCLKx; for SMCs, the name is
simply SMCLKx. These internal names are used only in NMSI mode to
specify the clocks sent to the FCCs, SCCs or SMCs. These names do not
correspond to any PowerQUICC II pins.
16.4 CMX Registers
The following sections describe the CMX registers.
16.4.1 CMX UTOPIA Address Register (CMXUAR)
NOTE
This section does not apply to the MPC8250.
and FCC2 UTOPIA multiple-PHY addresses to the twenty UTOPIA address pins of the PowerQUICC II;
it also defines the connection of a BRG to the FCCs when an internal rate feature is used. This enables the
user to implement a multiple-PHY UTOPIA master or slave on both FCC1 and FCC2 using only twenty
pins. The user chooses how many PHYs to use with each interface and how many address lines are needed
for each FCC.
0
1
2
3
4
5
6
7
8
9
10
11
12
15
Field SAD0 SAD1 SAD2 SAD3 SAD4
—
MAD4 MAD3
F1IRB
F2IRB
—
Reset
R/W
0000_0000_0000_0000
R/W
Addr
Figure 16-4. CMX UTOPIA Address Register (CMXUAR)
Table 16-2 describes CMXUAR fields.
Table 16-2. CMXUAR Field Descriptions
Bits
Name
Description
0–4
SADx Slave address input pin x connection. Note that the address indexes are relative to FCC1; see
0 This address input pin is used by FCC2 in slave mode.
1 This address input pin is used by FCC1 in slave mode.
5
—
Reserved, should be cleared.
6–7
MADx Master address output pin x connection. Note that the address indexes are relative to FCC1; see
0 This address output pin is used by FCC2 in master mode.
1 This address output pin is used by FCC1 in master mode.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
16-7
CPM Multiplexing
Table 16-2. CMXUAR Field Descriptions (continued)
Description
Bits
Name
8–9
F1IRB FCC1 internal rate BRG selection. Selects the BRG to be connected to FCC 1 for internal rate
00 FCC1 internal rate clock is BRG5.
01 FCC1 internal rate clock is BRG6.
10 FCC1 internal rate clock is BRG7.
11 FCC1 internal rate clock is BRG8.
10–11 F12IRB FCC2 internal rate BRG selection. Selects the BRG to be connected to FCC 2 for internal rate
00 FCC2 internal rate clock is BRG5.
01 FCC2 internal rate clock is BRG6.
10 FCC2 internal rate clock is BRG7.
11 FCC2 internal rate clock is BRG8.
12–15
—
Reserved, should be cleared.
NOTE
Each SADx and MADx corresponds to a pair of separate receive and
transmit address pins.
The PowerQUICC II has 16 output address pins and 10 input address pins dedicated for the UTOPIA
interface. However, it has two FCCs with two parts each—receiver and transmitter that can be ether master
or slave concurrently. The PowerQUICC II allows both FCC1 and FCC2 to connect to the address lines
without putting limitations on being a master or slave, as described in the following:
•
For master mode: The user has two groups of eight address pins each. Three pins from each group
are always connected to FCC1 and three are always connected to FCC2. The user decides which
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
16-8
Freescale Semiconductor
CPM Multiplexing
Pins
FCC1
5
5
M
These three bits always relate
to an FCC1 master.
8
5
S
5
5
M
S
0
1
2
These two address bits relate to the
master of FCC1 or FCC2 according
to the programming. Bit 4 is the msb.
4 3
4
3
2
1
0
FCC2
5
5
M
S
These three bits always relate
to FCC2 master
8
5
5
5
M
S
Figure 16-5. Connection of the Master Address
•
For slave mode—The user has two groups of five address pins each. The user decides
which FCC uses each pin by programming CMXUAR[SADx]. Connect any UTOPIA pins
Pins
FCC1
5
5
M
8
5
S
5
5
M
S
0
1
2
3
4
4
3
2
1
0
These 5 address bits relate to the
slave of FCC1 or FCC2 according to
the programming. Bit 4 is the msb.
FCC2
5
5
M
S
8
5
5
5
NOTE: To use FCC2 as shown, connect the FCC2 address bits reversed with
respect to the pinout address indexes. PHY address pins with no pin
connection should be connected to GND.
M
S
Figure 16-6. Connection of the Slave Address
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
16-9
CPM Multiplexing
NOTE
The user must program the addresses of the PHYs to be consecutive for each
FCC; that is, the address lines connected to each FCC must be consecutive.
Figure 16-7 describes the interconnection between the receive external multi-PHY bus and the internal
FCC1 and FCC2 receive multi-PHY addresses. The same diagram applies to the transmit multi-PHY bus
using different dedicated parallel I/O pins.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
16-10
Freescale Semiconductor
CPM Multiplexing
FCC1 Rx
Master Address
MAD4
MAD3
msb
1
0
FCC1-RxAddr[4]
PIO
PIO
PIO
PIO
PIO
FCC2-RxAddr[3] (master)
FCC2-RxAddr[0] (slave)
1
0
FCC1-RxAddr[3]
FCC2-RxAddr[4] (master)
FCC2-RxAddr[1] (slave)
lsb
FCC1-RxAddr[2]
FCC2-RxAddr[2] (slave)
FCC1 Rx
Slave Address
1
0
GND
msb
FCC1-RxAddr[1]
FCC2-RxAddr[3] (slave)
SAD4
1
0
GND
FCC1-RxAddr[0]
FCC2-RxAddr[4] (slave)
SAD3
lsb
1
0
GND
FCC1
SAD2
1
0
GND
SAD1
PIO
PIO
PIO
1
0
FCC2-RxAddr[2]
(master)
GND
SAD0
FCC2-RxAddr[1]
(master)
FCC2 Rx
Master Address
1
0
msb
GND
FCC2-RxAddr[0]
(master)
¬SAD0
1
0
GND
lsb
¬SAD1
1
0
FCC2 Rx
Slave Address
GND
msb
¬SAD2
1
0
GND
¬SAD3
1
0
lsb
GND
FCC2
¬SAD4
Figure 16-7. Multi-PHY Receive Address Multiplexing
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
16-11
CPM Multiplexing
16.4.2 CMX SI1 Clock Route Register (CMXSI1CR)
The CMX SI1 clock route register (CMXSI1CR), displayed in Figure 16-8, defines the connection of SI1
to the clock sources that can be input from the bank of clocks.
0
1
2
3
4
5
6
7
Field RTA1CS
RTB1CS
RTC1CS
RTD1CS
TTA1CS
TTB1CS
TTC1CS
TTD1CS
Reset
R/W
0000_0000
R/W
Addr
Figure 16-8. CMX SI1 Clock Route Register (CMXSI1CR)
Table 16-3 describes CMXSI1CR fields.
Table 16-3. CMXSI1CR Field Descriptions
Bits
Name
Description
0
RTA1CS Receive TDM A1 clock source
0 TDM A1 receive clock is CLK1.
1 TDM A1 receive clock is CLK19.
1
2
3
4
5
6
7
RTB1CS Receive TDM B1 clock source
0 TDM B1 receive clock is CLK3.
1 TDM B1 receive clock is CLK9.
RTC1CS Receive TDM C1 clock source
0 TDM C1 receive clock is CLK5.
1 TDM C1 receive clock is CLK13.
RTD1CS Receive TDM D1 clock source
0 TDM D1 receive clock is CLK7.
1 TDM D1 receive clock is CLK15.
TTA1CS Transmit TDM A1 clock source
0 TDM A1 transmit clock is CLK2.
1 TDM A1 transmit clock is CLK20.
TTB1CS Transmit TDM B1 clock source
0 TDM B1 transmit clock is CLK4.
1 TDM B1 transmit clock is CLK10.
TTC1CS Transmit TDM C1 clock source
0 TDM C1 transmit clock is CLK6.
1 TDM C1 transmit clock is CLK14.
TTD1CS Transmit TDM D1 clock source
0 TDM D1 transmit clock is CLK8.
1 TDM D1 transmit clock is CLK16.
16.4.3 CMX SI2 Clock Route Register (CMXSI2CR)
The CMX SI2 clock route register (CMXSI2CR), seen in Figure 16-9, defines the connection of SI2 to the
clock sources that can be input from the bank of clocks.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
16-12
Freescale Semiconductor
CPM Multiplexing
0
1
2
3
4
5
6
7
Field RTA2CS
RTB2CS
RTC2CS
RTD2CS
TTA2CS
TTB2CS
TTC2CS
TTD2CS
Reset
R/W
0000_0000
R/W
Addr
Figure 16-9. CMX SI2 Clock Route Register (CMXSI2CR)
Table 16-4 describes CMXSI2CR fields.
Table 16-4. CMXSI2CR Field Descriptions
Bits
Name
Description
0
RTA2CS Receive TDM A2 clock source
0 TDM A2 receive clock is CLK13.
1 TDM A2 receive clock is CLK5.
1
2
3
4
5
6
7
RTB2CS Receive TDM B2 clock source
0 TDM B2 receive clock is CLK15.
1 TDM B2 receive clock is CLK17.
RTC2CS Receive TDM C2 clock source
0 TDM C2 receive clock is CLK3.
1 TDM C2 receive clock is CLK17.
RTD2CS Receive TDM D2 clock source
0 TDM D2 receive clock is CLK1.
1 TDM D2 receive clock is CLK19.
TTA2CS Transmit TDM A2 clock source
0 TDM A2 transmit clock is CLK14.
1 TDM A2 transmit clock is CLK6.
TTB2CS Transmit TDM B2 clock source
0 TDM B2 transmit clock is CLK16.
1 TDM B2 transmit clock is CLK18.
TTC2CS Transmit TDM C2 clock source
0 TDM C2 transmit clock is CLK4.
1 TDM C2 transmit clock is CLK18.
TTD2CS Transmit TDM D2 clock source
0 TDM D2 transmit clock is CLK2.
1 TDM D2 transmit clock is CLK20.
16.4.4 CMX FCC Clock Route Register (CMXFCR)
FCCs to the TSA and to the clock sources from the bank of clocks.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
16-13
CPM Multiplexing
0
1
2
4
5
7
8
9
10
12
13
15
Field
Reset
R/W
—
FC1
RF1CS
RF3CS
TF1CS
FC2
RF2CS
TF2CS
0000_0000_0000_0000
R/W
Addr
16
17
18
20
21
23
24
31
Field
Reset
R/W
—
FC3
TF3CS
—
0000_0000_0000_0000
R/W
Addr
0x11B06
Figure 16-10. CMX FCC Clock Route Register (CMXFCR)
Table 16-5 describes CMXFCR fields.
Table 16-5. CMXFCR Field Descriptions
Bits
Name
Description
0
1
—
Reserved, should be cleared
Defines the FCC1 connection
FC1
0 FCC1 is not connected to the TSA and is either connected directly to the NMSIx pins or is not
used. The choice of general-purpose I/O port pins versus FCCn pins is made in the parallel I/O
control register.
1 FCC1 is connected to the TSA of the SIs. The NMSIx pins are available for other purposes.
2–4
RF1CS Receive FCC1 clock source (NMSI mode). Ignored if FCC1 is connected to the TSA (FC1 = 1).
000 FCC1 receive clock is BRG5.
001 FCC1 receive clock is BRG6.
010 FCC1 receive clock is BRG7.
011 FCC1 receive clock is BRG8.
100 FCC1 receive clock is CLK9.
101 FCC1 receive clock is CLK10.
110 FCC1 receive clock is CLK11.
111 FCC1 receive clock is CLK12.
5–7
TF1CS Transmit FCC1 clock source (NMSI mode). Ignored if FCC1 is connected to the TSA (FC1 = 1).
000 FCC1 transmit clock is BRG5.
001 FCC1 transmit clock is BRG6.
010 FCC1 transmit clock is BRG7.
011 FCC1 transmit clock is BRG8.
100 FCC1 transmit clock is CLK9.
101 FCC1 transmit clock is CLK10.
110 FCC1 transmit clock is CLK11.
111 FCC1 transmit clock is CLK12.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
16-14
Freescale Semiconductor
CPM Multiplexing
Table 16-5. CMXFCR Field Descriptions (continued)
Description
Bits
8-9
Name
FC2
Defines the FCC2 connection.
00 FCC2 is not connected to the TSA and is either connected directly to the NMSIx pins or is not
used. The choice of general-purpose I/O port pins versus FCCn pins is made in the parallel I/O
control register.
01 FCC2 is connected to the TSA of the SIs. The NMSIx pins are available for other purposes.
10 FCC2 is connected to the TC layer (MPC8264 and MPC8266 only). The NMSIx pins are
available for other purposes.
11 Reserved
10–12 RF2CS Receive FCC2 clock source (NMSI mode). Ignored if FCC2 is connected to the TSA (FC2 = 01).
000 FCC2 receive clock is BRG5.
001 FCC2 receive clock is BRG6.
010 FCC2 receive clock is BRG7.
011 FCC2 receive clock is BRG8.
100 FCC2 receive clock is CLK13.
101 FCC2 receive clock is CLK14.
110 FCC2 receive clock is CLK15.
111 FCC2 receive clock is CLK16.
13–15 TF2CS Transmit FCC2 clock source (NMSI mode). Ignored if FCC2 is connected to the TSA (FC2 = 01).
000 FCC2 transmit clock is BRG5.
001 FCC2 transmit clock is BRG6.
010 FCC2 transmit clock is BRG7.
011 FCC2 transmit clock is BRG8.
100 FCC2 transmit clock is CLK13.
101 FCC2 transmit clock is CLK14.
110 FCC2 transmit clock is CLK15.
111 FCC2 transmit clock is CLK16.
16
17
—
Reserved, should be cleared
FC3
Defines the FCC3 connection
0 FCC3 is not connected to the TSA and is either connected directly to the NMSIx pins or is not
used. The choice of general-purpose I/O port pins versus FCCn pins is made in the parallel I/O
control register.
1 FCC3 is connected to the TSA of the SIs. The NMSIx pins are available for other purposes.
18–20 RF3CS Receive FCC3 clock source (NMSI mode). Ignored if FCC3 is connected to the TSA (FC3 = 1).
000 FCC3 receive clock is BRG5.
001 FCC3 receive clock is BRG6.
010 FCC3 receive clock is BRG7.
011 FCC3 receive clock is BRG8.
100 FCC3 receive clock is CLK13.
101 FCC3 receive clock is CLK14.
110 FCC3 receive clock is CLK15.
111 FCC3 receive clock is CLK16.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
16-15
CPM Multiplexing
Table 16-5. CMXFCR Field Descriptions (continued)
Description
Bits
Name
21–23 TF3CS Transmit FCC3 clock source (NMSI mode). Ignored if FCC3 is connected to the TSA (FC3 = 1).
000 FCC3 transmit clock is BRG5.
001 FCC3 transmit clock is BRG6.
010 FCC3 transmit clock is BRG7.
011 FCC3 transmit clock is BRG8.
100 FCC3 transmit clock is CLK13.
101 FCC3 transmit clock is CLK14.
110 FCC3 transmit clock is CLK15.
111 FCC3 transmit clock is CLK16.
24–31
—
Reserved, should be cleared
16.4.5 CMX SCC Clock Route Register (CMXSCR)
to the TSA and to the clock sources from the bank of clocks. This register also enables the use of the
external grant pin.
0
1
2
4
5
7
8
9
10
12
13
15
Field GR1 SC1
RS1CS
RS3CS
TS1CS
GR2 SC2
RS2CS
TS2CS
Reset
R/W
0000_0000_0000_0000
R/W
Addr
16
17
18
20
21
23
24
25
26
28
29
31
Field GR3 SC3
TS3CS
GR4 SC4
RS4CS
TS4CS
Reset
R/W
0000_0000_0000_0000
R/W
Addr
0x11B0A
Figure 16-11. CMX SCC Clock Route Register (CMXSCR)
Table 16-6 describes CMXSCR fields.
Table 16-6. CMXSCR Field Descriptions
Bits
Name
Description
0
GR1
Grant support of SCC1
0 SCC1 transmitter does not support the grant mechanism. The grant is always asserted internally.
1 SCC1 transmitter supports the grant mechanism as determined by the GMx bit of a serial device
channel.
1
SC1
SCC1 connection
0 SCC1 is not connected to the TSA and is either connected directly to the NMSIx pins or is not
used. The choice of general-purpose I/O port pins versus SCCn pins is made in the parallel I/O
control register.
1 SCC1 is connected to TSA of the SIs. The NMSIx pins are available for other purposes.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
16-16
Freescale Semiconductor
CPM Multiplexing
Table 16-6. CMXSCR Field Descriptions (continued)
Description
Bits
Name
2–4
RS1CS Receive SCC1 clock source (NMSI mode). Ignored if SCC1 is connected to the TSA (SC1 = 1).
000 SCC1 receive clock is BRG1.
001 SCC1 receive clock is BRG2.
010 SCC1 receive clock is BRG3.
011 SCC1 receive clock is BRG4.
100 SCC1 receive clock is CLK11.
101 SCC1 receive clock is CLK12.
110 SCC1 receive clock is CLK3.
111 SCC1 receive clock is CLK4.
5–7
TS1CS Transmit SCC1 clock source (NMSI mode). Ignored if SCC1 is connected to the TSA (SC1 = 1).
000 SCC1 transmit clock is BRG1.
001 SCC1 transmit clock is BRG2.
010 SCC1 transmit clock is BRG3.
011 SCC1 transmit clock is BRG4.
100 SCC1 transmit clock is CLK11.
101 SCC1 transmit clock is CLK12.
110 SCC1 transmit clock is CLK3.
111 SCC1 transmit clock is CLK4.
8
9
GR2
SC2
Grant support of SCC2
0 SCC2 transmitter does not support the grant mechanism. The grant is always asserted internally.
1 SCC2 transmitter supports the grant mechanism as determined by the GMx bit of a serial device
channel.
SCC2 connection
0 SCC2 is not connected to the TSA and is either connected directly to the NMSIx pins or is not
used. The choice of general-purpose I/O port pins versus SCCn pins is made in the parallel I/O
control register.
1 SCC2 is connected to TSA of the SIs. The NMSIx pins are available for other purposes.
10–12 RS2CS Receive SCC2 clock source (NMSI mode). Ignored if SCC2 is connected to the TSA (SC2 = 1).
000 SCC2 receive clock is BRG1.
001 SCC2 receive clock is BRG2.
010 SCC2 receive clock is BRG3.
011 SCC2 receive clock is BRG4.
100 SCC2 receive clock is CLK11.
101 SCC2 receive clock is CLK12.
110 SCC2 receive clock is CLK3.
111 SCC2 receive clock is CLK4.
13–15 TS2CS Transmit SCC2 clock source (NMSI mode). Ignored if SCC2 is connected to the TSA (SC2 = 1).
000 SCC2 transmit clock is BRG1.
001 SCC2 transmit clock is BRG2.
010 SCC2 transmit clock is BRG3.
011 SCC2 transmit clock is BRG4.
100 SCC2 transmit clock is CLK11.
101 SCC2 transmit clock is CLK12.
110 SCC2 transmit clock is CLK3.
111 SCC2 transmit clock is CLK4.
16
GR3
Grant support of SCC3
0 SCC3 transmitter does not support the grant mechanism. The grant is always asserted internally.
1 SCC3 transmitter supports the grant mechanism as determined by the GMx bit of a serial device
channel.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
16-17
CPM Multiplexing
Table 16-6. CMXSCR Field Descriptions (continued)
Description
Bits
Name
SC3
17
SCC3 connection
0 SCC3 is not connected to the TSA and is either connected directly to the NMSIx pins or is not
used. The choice of general-purpose I/O port pins versus SCCn pins is made in the parallel I/O
control register.
1 SCC3 is connected to TSA of the SIs. The NMSIx pins are available for other purposes.
18–20 RS3CS Receive SCC3 clock source (NMSI mode). Ignored if SCC3 is connected to the TSA (SC3 = 1).
000 SCC3 receive clock is BRG1.
001 SCC3 receive clock is BRG2.
010 SCC3 receive clock is BRG3.
011 SCC3 receive clock is BRG4.
100 SCC3 receive clock is CLK5.
101 SCC3 receive clock is CLK6.
110 SCC3 receive clock is CLK7.
111 SCC3 receive clock is CLK8.
21–23 TS3CS Transmit SCC3 clock source (NMSI mode). Ignored if SCC3 is connected to the TSA (SC3 = 1).
000 SCC3 transmit clock is BRG1.
001 SCC3 transmit clock is BRG2.
010 SCC3 transmit clock is BRG3.
011 SCC3 transmit clock is BRG4.
100 SCC3 transmit clock is CLK5.
101 SCC3 transmit clock is CLK6.
110 SCC3 transmit clock is CLK7.
111 SCC3 transmit clock is CLK8.
24
25
GR4
SC4
Grant support of SCC4
0 SCC4 transmitter does not support the grant mechanism. The grant is always asserted internally.
1 SCC4 transmitter supports the grant mechanism as determined by the GMx bit of a serial device
channel.
SCC4 connection
0 SCC4 is not connected to the TSA and is either connected directly to the NMSIx pins or is not
used. The choice of general-purpose I/O port pins versus SCCn pins is made in the parallel I/O
control register.
1 SCC4 is connected to TSA of the SIs. The NMSIx pins are available for other purposes.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
16-18
Freescale Semiconductor
CPM Multiplexing
Table 16-6. CMXSCR Field Descriptions (continued)
Description
Bits
Name
26–28 RS4CS Receive SCC4 clock source (NMSI mode). Ignored if SCC4 is connected to the TSA (SC4 = 1).
000 SCC4 receive clock is BRG1.
001 SCC4 receive clock is BRG2.
010 SCC4 receive clock is BRG3.
011 SCC4 receive clock is BRG4.
100 SCC4 receive clock is CLK5.
101 SCC4 receive clock is CLK6.
110 SCC4 receive clock is CLK7.
111 SCC4 receive clock is CLK8
29–31 TS4CS Transmit SCC4 clock source (NMSI mode). Ignored if SCC4 is connected to the TSA (SC4 = 1).
000 SCC4 transmit clock is BRG1.
001 SCC4 transmit clock is BRG2.
010 SCC4 transmit clock is BRG3.
011 SCC4 transmit clock is BRG4.
100 SCC4 transmit clock is CLK5.
101 SCC4 transmit clock is CLK6.
110 SCC4 transmit clock is CLK7.
111 SCC4 transmit clock is CLK8
16.4.6 CMX SMC Clock Route Register (CMXSMR)
SMCs to the TSA and to the clock sources from the bank of clocks.
0
1
2
3
4
5
6
7
Field
Reset
R/W
SMC1
—
SMC1CS
SMC2
—
SMC2CS
0000_0000
R/W
Addr
Figure 16-12. CMX SMC Clock Route Register (CMXSMR)
Table 16-7 describes CMXSMR fields.
Table 16-7. CMXSMR Field Descriptions
Bit s
Name
SMC1
Description
0
SMC1 connection
0 SMC1 is not connected to the TSA and is either connected directly to the NMSIx pins or is not
used. The choice of general-purpose I/O port pins versus SMCn pins is made in the parallel I/O
control register.
1 SMC1 is connected to the TSA of the SIs. The NMSIx pins are available for other purposes.
1
—
Reserved, should be cleared
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
16-19
CPM Multiplexing
Table 16-7. CMXSMR Field Descriptions
Description
Bit s
Name
2–3
SMC1CS SMC1 clock source (NMSI mode). SMC1 can take its clocks from one of the two BRGs or one of
two pins from the bank of clocks. However, the SMC1 transmit and receive clocks must be the same
when it is connected to the NMSI.
00 SMC1 transmit and receive clocks are BRG1.
01 SMC1 transmit and receive clocks are BRG7.
10 SMC1 transmit and receive clocks are CLK7.
11 SMC1 transmit and receive clocks are CLK9.
4
SMC2
SMC2 connection
0 SMC2 is not connected to the TSA and is either connected directly to the NMSIx pins or is not
used. The choice of general-purpose I/O port pins versus SMCn pins is made in the parallel I/O
control register.
1 SMC2 is connected to the TSA of the SIs. The NMSIx pins are available for other purposes.
5
—
Reserved, should be cleared
6–7
SMC2CS SMC2 clock source (NMSI mode). SMC2 can take its clocks from one of the eight BRGs or one of
eight pins from the bank of clocks. However, the SMC2 transmit and receive clocks must be the
same when it is connected to the NMSI.
00 SMC2 transmit and receive clocks are BRG2.
01 SMC2 transmit and receive clocks are BRG8.
10 SMC2 transmit and receive clocks are CLK19.
11 SMC2 transmit and receive clocks are CLK20.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
16-20
Freescale Semiconductor
Chapter 17
Baud-Rate Generators (BRGs)
The CPM contains eight independent, identical baud-rate generators (BRGs) that can be used with the
FCCs, SCCs, and SMCs. The clocks produced by the BRGs are sent to the bank-of-clocks selection logic,
where they can be routed to the controllers. In addition, the output of a BRG can be routed to a pin to be
used externally. The following is a list of BRGs’ main features:
•
•
•
•
•
•
Eight independent and identical BRGs
On-the-fly changes allowed
Each BRG can be routed to one or more FCCs, SCCs, or SMCs
A 16x divider option allows slow baud rates at high system frequencies
Each BRG contains an autobaud support option
Each BRG output can be routed to a pin (BRGOn)
EXTC
DIV 16
CD[0–11]
CLK Pin x
Clock
Prescaler
12-Bit Counter
1–4,096
BRGOn Clock
Divide by
1 or 16
To Pin and/or
Bank of Clocks
CLK Pin y
Source
MUX
BRGCLK
ATB
Autobaud
Control
RXDn
BRGn
Figure 17-1. Baud-Rate Generator (BRG) Block Diagram
Each BRG clock source can be BRGCLK, or a choice of two external clocks (selected in BRGCx[EXTC]).
The BRGCLK is an internal signal generated in the PowerQUICC II clock synthesizer specifically for the
2
BRGs, the SPI, and the I C internal BRG. Alternatively, external clock pins can be configured as clock
sources. The external source option allows flexible baud-rate frequency generation, independent of the
system frequency. Additionally, the external source option allows a single external frequency to be the
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
17-1
Baud-Rate Generators (BRGs)
source for multiple BRGs. The external source signals are not synchronized internally before being used
by the BRG.
The BRG provides a divide-by-16 option (BRGCx[DIV16]) and a 12-bit prescaler (BRGCx[CD]) to divide
the source clock frequency. The combined source-clock divide factor can be changed on-the-fly; however,
two changes should not occur within two source clock periods.
The prescaler output is sent internally to the bank of clocks and can also be output externally on BRGOn
through the parallel I/O ports. If the BRG divides the clock by an even value, the transitions of BRGOn
always occur on the falling edge of the source clock. If the divide factor is odd, the transitions alternate
between the falling and rising edges of the source clock. Additionally, the output of the BRG can be sent
to the autobaud control block.
17.1 BRG Configuration Registers 1–8 (BRGCx)
The BRG configuration registers (BRGCx) are shown in Figure 17-2. A reset disables the BRG and drives
the BRGO output clock high. The BRGC can be written at any time with no need to disable the SCCs or
external devices that are connected to BRGO. Configuration changes occur at the end of the next BRG
clock cycle (no spikes occur on the BRGO output clock). BRGC can be changed on-the-fly; however, two
changes should not occur within a time equal to two source clock periods.
0
13
14
15
Field
Reset
R/W
—
RST EN
0000_0000_0000_0000
R/W
Addr
16
17
18
19
30
31
Field
Reset
R/W
EXTC
ATB
CD
0000_0000_0000_0000
R/W
DIV16
Addr
0x119F22 (BRGC1), 0x119F6 (BRGC2), 0x119FA (BRGC3), 0x119FE (BRGC4),
0x115F2 (BRGC5), 0x115F6 (BRGC6), 0x115FA (BRGC7), 0x115FE (BRGC8)
Figure 17-2. Baud-Rate Generator Configuration Registers (BRGCx)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
17-2
Freescale Semiconductor
Baud-Rate Generators (BRGs)
Table 17-1. BRGCx Field Descriptions
Description
Bits
Name
0–13
14
—
Reserved, should be cleared.
RST Reset BRG. Performs a software reset of the BRG identical to that of an external reset. A reset
disables the BRG and drives BRGO high. This is externally visible only if BRGO is connected to the
corresponding parallel I/O pin.
0 Enable the BRG.
1 Reset the BRG (software reset).
15
EN
Enable BRG count. Used to dynamically stop the BRG from counting—useful for low-power modes.
0 Stop all clocks to the BRG.
1 Enable clocks to the BRG.
00 The BRG input clock comes from the BRGCLK (internal clock generated from the CPM clock);
01 If BRG1, 2, 5, 6: The BRG input clock comes from the CLK3 pin.
If BRG3, 4, 7, 8: The BRG input clock comes from the CLK9 pin
10 If BRG1, 2, 5, 6: The BRG input clock comes from the CLK5 pin.
If BRG3, 4, 7, 8: The BRG input clock comes from the CLK15 pin
11 Reserved.
18
ATB Autobaud. Selects autobaud operation of the BRG on the corresponding RXD. ATB must remain
zero until the SCC receives the three Rx clocks. Then the user must set ATB to obtain the correct
baud rate. After the baud rate is obtained and locked, it is indicated by setting AB in the UART event
register.
0 Normal operation of the BRG.
1 When RXD goes low, the BRG determines the length of the start bit and synchronizes the BRG
to the actual baud rate.
19–30
CD
Clock divider. CD presets an internal 12-bit counter that is decremented at the DIV16 output rate.
When the counter reaches zero, it is reloaded with CD. CD = 0xFFF produces the minimum clock
rate for BGRO (divide by 4,096); CD = 0x000 produces the maximum rate (divide by 1). When
dividing by an odd number, the counter ensures a 50% duty cycle by asserting the terminal count
once on clock low and next on clock high. The terminal count signals counter expiration and toggles
31
DIV16 Divide-by-16. Selects a divide-by-1 or divide-by-16 prescaler before reaching the clock divider. See
0 Divide by 1.
1 Divide by 16.
Table 17-2 shows the possible external clock sources for the BRGs.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
17-3
Baud-Rate Generators (BRGs)
Table 17-2. BRG External Clock Source Options
CLK
BRG
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
1
2
3
4
5
6
7
8
9
BRG1
BRG2
BRG3
BRG4
BRG5
BRG6
BRG7
BRG8
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
17.2 Autobaud Operation on a UART
During the autobaud process, a UART deduces the baud rate of its received character stream by examining
the received pattern and its timing. A built-in autobaud control function automatically measures the length
of a start bit and modifies the baud rate accordingly.
If the autobaud bit BRGCx[ATB] is set, the autobaud control function starts searching for a low level on
the corresponding RXDn input, which it assumes marks the beginning of a start bit, and begins counting
the start bit length. During this time, the BRG output clock toggles for 16 BRG clock cycles at the BRG
source clock rate and then stops with BRGOn in the low state.
When RXDn goes high again, the autobaud control block rewrites BRGCx[CD, DIV16] to the divide ratio
found, which at high baud rates may not be exactly the final rate desired (for example, 56,600 may result
rather than 57,600). An interrupt can be enabled in the UART SCC event register to report that the
autobaud controller rewrote BRGCx. The interrupt handler can then adjust BRGCx[CD, DIV16] (see
Table 17-3.) for accuracy before the first character is fully received, ensuring that the UART recognizes
all characters.
After a full character is received, the software can verify that the character matches a predefined value
(such as ‘a’ or ‘A’). Software should then check for other characters (such as ‘t’ or ‘T’) and program the
preferred parity mode in the UART’s protocol-specific mode register (PSMR).
Note that the SCC associated with this BRG must be programmed to UART mode and select the 16×
option for TDCR and RDCR in the general SCC mode register low. Input frequencies such as 1.8432, 3.68,
7.36, and 14.72 MHz should be used. The SCC performing the autobaud function must be connected to
that SCC’s BRG; that is, SCC2 must be clocked by BRG2, and so on.
Also, to detect an autobaud lock and generate an interrupt, the SCC must receive three full Rx clocks from
the BRG before the autobaud process begins. To do this, first clear BRGCx[ATB] and enable the BRG Rx
clock to the highest frequency. Then, immediately before the autobaud process starts (after device
initialization), set BRGCx[ATB].
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
17-4
Freescale Semiconductor
Baud-Rate Generators (BRGs)
17.3 UART Baud Rate Examples
For synchronous communication using the internal BRG, the BRGO must not exceed the BRG input clock
divided by 2. Therefore, with a BRG input clock of 66MHz (generated using an external clock source: refer
to BRGCx[EXTC]), the maximum BRGO rate is 33MHz. Program the UART to 16× oversampling when
using the SCC as a UART. Rates of 8× and 32× are also available. Assuming 16× oversampling is chosen
in the UART, the maximum data rate is 66 MHz ÷ 16 = 4.125 Mbps. Keeping the above in mind, use the
following formula to calculate the bit rate based on a particular BRG configuration for a UART:
BRGCLK or External Clock Source
(Prescale Divider) • (Clock Divider + 1) • (Sampling Rate)
------------------------------------------------------------------------------------------------------------------------------------------------
Async Baud Rate =
BRGCx[EXTC]
(BRGCx[DIV16]) • (BRGCx[CD] + 1) • (GSMRx_L[xDCR])
--------------------------------------------------------------------------------------------------------------------------------------------------------
=
Table 17-3 lists typical bit rates of asynchronous communication. Note that here the internal clock rate is
assumed to be 16× the baud rate; that is, GSMRx_L[TDCR] = GSMRx_L[RDCR] = 0b10.
Table 17-3. Typical Baud Rates for Asynchronous Communication
Using a 66-MHz BRG Input Clock
Baud Rate
BRGCx[DIV16]
BRGCx[CD]
Actual Frequency (Hz)
75
150
1
1
1
1
0
0
0
0
0
0
0
0
0
3436
1718
858
429
3436
1718
858
429
214
106
71
75.01
149.98
300.13
599.56
1200.2
2399.7
4802.1
9593.0
19,186
38,551
57,292
114,583
458,333
300
600
1200
2400
4800
9600
19,200
38,400
57,600
115,200
460,000
35
8
For synchronous communication, the internal clock is identical to the baud-rate output. To get the preferred
rate, select the system clock according to the following:
BRGCLK or External Clock Source
(Prescale Divider) • (Clock Divider + 1)
--------------------------------------------------------------------------------------------------
Sync Baud Rate =
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
17-5
Baud-Rate Generators (BRGs)
BRGCx[EXTC]
(BRGCx[DIV16]) • (BRGCx[CD] + 1)
-----------------------------------------------------------------------------------------------
=
For example, to get a rate of 64 kbps, the system clock can be 24.96 MHz, BRGCx[DIV16] = 0, and
BRGCx[CD] = 389.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
17-6
Freescale Semiconductor
Chapter 18
Timers
The CPM includes four identical 16-bit general-purpose timers or two 32-bit timers. Each general-purpose
timer consists of a timer mode register (TMR), a timer capture register (TCR), a timer counter (TCN), a
timer reference register (TRR), a timer event register (TER), and a timer global configuration register
(TGCR). The TMRs contain the prescaler values programmed by the user.
Figure 18-1 shows the timer block diagram.
Bus
Clock
TGCR
Global Configuration Register
TGATE1
TGATE2
TER1
TMR1
Timer Event Register
Mode Register
Timer
Clock
Generator
TIN1
TIN2
Prescaler
Mode Bits
TIN3
TIN4
Clock
Divider
TCN1
TRR1
TCR1
Timer Counter (TCN)
Capture
Detection
Reference Register
Capture Register
TOUT1
TOUT2
TOUT3
TOUT4
Timer1
Timer2
Timer3
Timer4
Figure 18-1. Timer Block Diagram
18.1 Features
The key features of the timer include the following:
•
•
The maximum input clock is the bus clock
Maximum period of 4 seconds (at 66 MHz)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
18-1
Timers
•
•
•
•
•
•
•
16-nanosecond resolution (at 66 MHz)
Programmable sources for the clock input
Input capture capability
Output compare with programmable mode for the output pin
Two timers cascade internally or externally to form a 32-bit timer
Free run and restart modes
Functional compatibility with timers on the MC68360 and MPC860
18.2 General-Purpose Timer Units
The clock input to the prescaler can be selected from three sources:
•
•
•
The bus clock (CLKIN)
The bus clock divided by 16 (CLKIN/16)
The corresponding TINx, programmed in the parallel port registers
The bus clock is generated in the clock synthesizer and defaults to the bus frequency. However, the bus
clock has the option to be divided before it leaves the clock synthesizer. This mode, called slow go, is used
to save power. Whatever the resulting frequency of the bus clock, the user can either choose that frequency
or the frequency divided by 16 as the input to the prescaler of each timer. Alternatively, the user may prefer
TINx to be the clock source. TINx is internally synchronized to the internal clock. If the user has chosen
to internally cascade two 16-bit timers to a 32-bit timer, then a timer can use the clock generated by the
output of another timer.
The clock input source is selected by the corresponding TMR[ICLK] bits. The prescaler is programmed
to divide the clock input by values from 1 to 256 and the output of the prescaler is used as an input to the
16-bit counter. The best resolution of the timer is one clock cycle (16 ns at 66 MHz). The maximum period
(when the reference value is all ones) is 268,435,456 cycles (4 seconds at 66 MHz).
Each timer can be configured to count until a reference is reached and then either begin a new time count
immediately or continue to run. The FRR bit of the corresponding TMR selects each mode. Upon reaching
the reference value, the corresponding TER bit is set and an interrupt is issued if TMR[ORI] = 1. The
timers can output a signal on the timer outputs (TOUT1–TOUT4) when the reference value is reached
(selected by the corresponding TMR[OM]). This signal can be an active-low pulse or a toggle of the
current output. The output can also be connected internally to the input of another timer, resulting in a
32-bit timer.
In addition, each timer has a 16-bit TCR used to latch the value of the counter when a defined transition
of TIN1, TIN2, TIN3, or TIN4 is sensed by the corresponding input capture edge detector. The type of
transition triggering the capture is selected by the corresponding TMR[CE] bits. Upon a capture or
reference event, the corresponding TER bit is set and a maskable interrupt request is issued to the interrupt
controller. The timers may be gated/restarted by an external gate signal. There are two gate
signals—TGATE1 controls timer 1 and/or 2 and TGATE2 controls timer 3 and/or 4. Normal gate mode
enables the count on a falling edge of TGATEx and disables the count on the rising edge of TGATEx. This
mode allows the timer to count conditionally, based on the state of TGATEx.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
18-2
Freescale Semiconductor
Timers
The restart gate mode performs the same function as normal mode, except it also resets the counter on the
falling edge of TGATEx. This mode has applications in pulse interval measurement and bus monitoring as
follows:
•
Pulse measurement—The restart gate mode can measure a low TGATEx. The rising edge of
TGATEx completes the measurement and if TGATEx is connected externally to TINx, it causes the
timer to capture the count value and generate a rising-edge interrupt.
•
Bus monitoring—The restart gate mode can detect a signal that is abnormally stuck low. The bus
signal should be connected to TGATEx. The timer count is reset on the falling edge of the bus
signal and if the bus signal does not go high again within the number of user-defined clocks, an
interrupt can be generated.
The gate function is enabled in the TMR; the gate operating mode is selected in the TGCR.
NOTE
TGATEx is internally synchronized to the system clock. If TGATEx meets
the asynchronous input setup time, the counter begins counting after one
system clock when working with the internal clock.
18.2.1 Cascaded Mode
In this mode, two 16-bit timers can be internally cascaded to form a 32-bit counter. Timer 1 may be
internally cascaded to timer 2, and timer 3 can be internally cascaded to timer 4. Because the decision to
cascade timers is made independently, the user can select two 16-bit timers or one 32-bit timer. TGCR is
Timer1
Timer2
Clock
TRR, TCR, TCN connected to D[0–15]
TRR, TCR, TCN connected to D[16–31]
Capture
Timer3
Clock
Timer4
TRR, TCR, TCN connected to D[0–15]
TRR, TCR, TCN connected to D[16–31]
Capture
Figure 18-2. Timer Cascaded Mode Block Diagram
If TGCR[CAS] = 1, the two timers function as a 32-bit timer with a 32-bit TRR, TCR, and TCN. In this
case, TMR1 and/or TMR3 are ignored, and the modes are defined using TMR2 and/or TMR4. The capture
is controlled from TIN2 or TIN4 and the interrupts are generated from TER2 or TER4. In cascaded mode,
the combined TRR, TCR, and TCN must be referenced with 32-bit bus cycles.
18.2.2 Timer Global Configuration Registers (TGCR1 and TGCR2)
contain configuration parameters used by the timers. These registers allow simultaneous starting and
stopping of a pair of timers (1 and 2 or 3 and 4) if one bus cycle is used.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
18-3
Timers
0
1
2
3
4
5
6
7
Field
Reset
R/W
CAS2
—
STP2
RST2
GM1
—
STP1
RST1
0000_0000
R/W
Addr
Figure 18-3. Timer Global Configuration Register 1 (TGCR1)
Table 18-1 describes TGCR1 fields.
Table 18-1. TGCR1 Field Descriptions
Bits
Name
Description
0
CAS2 Cascade timers.
0 Normal operation.
1 Timers 1 and 2 cascade to form a 32-bit timer.
Reserved, should be cleared.
STP 2 Stop timer.
1
2
—
0 Normal operation.
1 Reduce power consumption of the timer. This bit stops all clocks to the timer, except the clock
from the internal bus interface, which allows the user to read and write timer registers. The clocks
to the timer remain stopped until the user clears this bit or a hardware reset occurs.
3
4
RST2 Reset timer.
0 Reset the corresponding timer (a software reset is identical to an external reset).
1 Enable the corresponding timer if the STP bit is cleared.
GM1 Gate mode for TGATE1. This bit is valid only if the gate function is enabled in TMR1 or TMR2.
0 Restart gate mode. TGATE1 is used to enable/disable count. A falling TGATE1 enables and
restarts the count and a rising edge of TGATE1 disables the count.
1 Normal gate mode. This mode is the same as 0, except the falling edge of TGATE1 does not
restart the count value in TCN.
5
6
—
Reserved, should be cleared.
STP1 Stop timer.
0 Normal operation.
1 Reduce power consumption of the timer. This bit stops all clocks to the timer, except the clock
from the internal bus interface, which allows the user to read and write timer registers. The clocks
to the timer remain stopped until the user clears this bit or a hardware reset occurs.
7
RST1 Reset timer.
0 Reset the corresponding timer (a software reset is identical to an external reset).
1 Enable the corresponding timer if STP = 0.
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Freescale Semiconductor
Timers
0
1
2
3
4
5
6
7
Field
Reset
R/W
CAS4
—
STP4
RST4
GM2
—
STP3
RST3
0000_0000
R/W
Addr
Figure 18-4. Timer Global Configuration Register 2 (TGCR2)
Table 18-2 describes TGCR2 fields.
Table 18-2. TGCR2 Field Descriptions
Bit
Name
Description
0
CAS4 Cascade timers.
0 Normal operation.
1 Timers 3 and 4 cascades to form a 32-bit timer.
Reserved, should be cleared.
STP 4 Stop timer.
1
2
—
0 Normal operation.
1 Reduce power consumption of the timer. This bit stops all clocks to the timer, except the clock
from the internal bus interface, which allows the user to read and write timer registers. The clocks
to the timer remain stopped until the user clears this bit or a hardware reset occurs.
3
4
RST4 Reset timer.
0 Reset the corresponding timer (a software reset is identical to an external reset).
1 Enable the corresponding timer if the STP bit is cleared.
GM2 Gate mode for TGATE2. This bit is valid only if the gate function is enabled in TMR3 or TMR4.
0 Restart gate mode. TGATE2 is used to enable/disable the count. The falling edge of TGATE2
enables and restarts the count and the rising edge of TGATE2 disables the count.
1 Normal gate mode. This mode is the same as 0, except the falling edge of TGATE2 does not
restart the count value in TCN.
5
6
—
Reserved, should be cleared.
STP3 Stop timer.
0 Normal operation.
1 Reduce power consumption of the timer. This bit stops all clocks to the timer, however it is
possible to read the values while the clock is stopped. The clocks to the timer remain stopped
until the user clears this bit or a hardware reset occurs.
7
RST3 Reset timer.
0 Reset the corresponding timer (a software reset is identical to an external reset).
1 Enable the corresponding timer if STP = 0.
18.2.3 Timer Mode Registers (TMR1–TMR4)
Erratic behavior may occur if TGCR1 and TGCR2 are not initialized before the TMRs. Only TGCR[RST]
can be modified at any time.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
18-5
Timers
0
7
8
9
10
11
12
13
14
15
Field
Reset
R/W
PS
CE
OM ORI FRR
ICLK
GE
0000_0000_0000_0000
R/W
Addr
Figure 18-5. Timer Mode Registers (TMR1–TMR4)
Table 18-3 describes TMR1–TMR4 register fields.
Table 18-3. TMR1–TMR4 Field Descriptions
Bits
Name
PS
Description
0–7
Prescaler value. The prescaler is programmed to divide the clock input by values from 1 to 256. The
value 00000000 divides the clock by 1 and 11111111 divides the clock by 256.
8–9
10
CE
Capture edge and enable interrupt.
00 Disable interrupt on capture event; capture function is disabled.
01 Capture on rising TINx edge only and enable interrupt on capture event.
10 Capture on falling TINx edge only and enable interrupt on capture event.
11 Capture on any TINx edge and enable interrupt on capture event.
OM
Output mode
0 Active-low pulse on TOUTx for one timer input clock cycle as defined by the ICLK bits. Thus,
TOUTx may be low for one bus clock period, one bus clock/16 period, or one TINx clock cycle
period. TOUTx changes occur on the rising edge of the system clock.
1 Toggle TOUTx. TOUTx changes occur on the rising edge of the system clock.
11
12
ORI Output reference interrupt enable.
0 Disable interrupt for reference reached (does not affect interrupt on capture function).
1 Enable interrupt upon reaching the reference value.
FRR Free run/restart.
0 Free run. The timer count continues to increment after the reference value is reached.
1 Restart. The timer count is reset immediately after the reference value is reached.
13–14 ICLK Input clock source for the timer.
00 Internally cascaded input. For TMR1, the timer 1 input is the output of timer 2. For TMR3, the
timer 3 input is the output of timer 4. For TMR2 and TMR4, this selection means no input clock
is provided to the timer.
01 Internal bus clock.
10 Internal bus clock divided by 16.
11 Corresponding TINx: TIN1, TIN2, TIN3, or TIN4 (falling edge).
15
GE
Gate enable.
0 TGATEx is ignored.
1 TGATEx is used to control the timer.
18.2.4 Timer Reference Registers (TRR1–TRR4)
value. The reference value is not reached until TCNx increments to equal the timeout reference value.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
18-6
Freescale Semiconductor
Timers
0
15
Field
Reset
R/W
Timeout reference value
0xFFFF
R/W
Addr
Figure 18-6. Timer Reference Registers (TRR1–TRR4)
18.2.5 Timer Capture Registers (TCR1–TCR4)
Each timer capture register (TCR1–TCR4), shown in Figure 18-7, is used to latch the value of the counter
according to TMRx[CE].
0
15
Field
Reset
R/W
Latched counter value
0x0000
R/W
Addr
Figure 18-7. Timer Capture Registers (TCR1–TCR4)
18.2.6 Timer Counters (TCN1–TCN4)
Each timer counter register (TCN1–TCN4), shown in Figure 18-8, is an up-counter. A read cycle to TCNx
yields the current value of the timer but does not affect the counting operation. A write cycle to TCNx sets
the register to the written value, thus causing its corresponding prescaler, TMRx[PS], to be reset.
0
15
Field
Reset
R/W
Up counter
0x0000
R/W
Addr
Figure 18-8. Timer Counter Registers (TCN1–TCN4)
Note that the counter registers may not be updated correctly if a write is made while the timer is not
running. Use TRRx to define the preferred count value.
18.2.7 Timer Event Registers (TER1–TER4)
Each timer event register (TERx), shown in Figure 18-9, reports events recognized by the timers. When
an output reference event is recognized, the timer sets TERx[REF] regardless of the corresponding
TMRx[ORI]. The capture event is set only if it is enabled by TMRx[CE]. TER1–TER4 can be read at any
time.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
18-7
Timers
Writing ones clears event bits; writing zeros has no effect. Both event bits must be cleared before the timer
negates the interrupt.
0
13
14
15
Field
Reset
Addr
—
REF CAP
0x0000
Figure 18-9. Timer Event Registers (TER1–TER4)
Table 18-4 describes TER fields.
Table 18-4. TER Field Descriptions
Description
Bits
Name
0–13
14
–
Reserved, should be cleared.
REF Output reference event. The counter has reached the TRR value. TMR[ORI] is used to enable the
interrupt request caused by this event.
15
CAP Capture event. The counter value has been latched into the TCR. TMR[CE] is used to enable
generation of this event.
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Freescale Semiconductor
Chapter 19
SDMA Channels and IDMA Emulation
The PowerQUICC II has two physical serial DMA (SDMA) channels. The CP implements two dedicated
virtual SDMA channels for each FCC, MCC, SCC, SMC, SPI, and I2C—one for each transmitter and
receiver. An additional four virtual SDMA channels are assigned to the programmable independent DMA
(IDMA) channels.
Figure 19-1 shows data flow paths. Data from the peripheral controllers can be routed to external RAM
using the 60x bus (path 1) or the local bus (path 2).
External
RAM
1
60x
Internal 60x Bus
Core
Dual-Port
RAM
External
ROM
SDMA
CP
2
Local
External
RAM
2
2 MCCs
3 FCCs
4 SCCs
2 SMCs
SPI
I C
Figure 19-1. SDMA Data Paths
On a path 1 access, the SDMA channel must acquire the external system bus. On a path 2 access, the local
bus is acquired and the access is not seen on the external system bus. Thus, the local bus transfer occurs at
the same time as other operations on the external 60x system bus.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
19-1
SDMA Channels and IDMA Emulation
The SDMA channel can be assigned big-endian (Freescale) or little-endian format for accessing buffer
data. These features are programmed in the receive and transmit registers associated with the FCCs,
MCCs, SCCs, SMCs, SPI, and I2C.
If a 60x or local bus error occurs on a CP-related access by the SDMA, the CP generates a unique interrupt
in the SDMA status register (SDSR). The interrupt service routine then reads the appropriate DMA
transfer error address register (PDTEA for the 60x bus or LDTEA for the local bus) to determine the
address the bus error occurred on. The channel that caused the bus error is determined by reading the
channel number from PDTEM or LDTEM. If an SDMA bus error occurs on a CP-related transaction, all
CPM activity stops and the entire CPM must be reset in the CP command register (CPCR). See
19.1 SDMA Bus Arbitration and Bus Transfers
On the PowerQUICC II, the core, PCI bridge, and SDMA can become external bus masters. (The relative
priority of these masters is programmed by the user; see Section 4.3.2, “System Configuration and
Protection Registers,” for programming bus arbitration.)Therefore, any SDMA channel can arbitrate for
the bus against the other internal devices and any external devices present. Once an SDMA channel
becomes system bus master, it remains bus master for one transaction (which can be a byte, half-word,
word, burst, or extended special burst) before releasing the bus. This feature, in combination with the
zero-clock arbitration overhead provided by the 60x bus, increases bus efficiency and lowers bus latency.
To minimize the latency associated with slower, character-oriented protocols, an SDMA writes each
character to memory as it arrives without waiting for the next character, and always reads using 16-bit
half-word transfers.
The SDMA can access the 60x bus either at the regular 60x transactions (single-beat accesses, four-beat
bursts) or special two- and three-beat burst accesses. For a further description of this feature see
A transfer may take multiple bus transactions if the memory provides a less than 64-bit 60x port size or
less than 32-bit local bus port size. An SDMA uses back-to-back bus transactions for the entire
transfer—4-word bursts, 64-bit reads, and 8-, 16-, 32-, or 64-bit writes—before relinquishing the bus. For
example, a 64-bit word 60x-bus read from a 32-bit memory takes two consecutive SDMA bus transactions.
An SDMA can steal transactions with no arbitration overhead when the PowerQUICC II is bus master.
Figure 19-2 shows an SDMA stealing a transaction from an internal bus master.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
19-2
Freescale Semiconductor
SDMA Channels and IDMA Emulation
Other Transaction
SDMA Transaction
Other Transaction
CLK
TS
TA
SDMA Internally
Requests the Bus
Figure 19-2. SDMA Bus Arbitration (Transaction Steal)
19.2 SDMA Registers
The only user-accessible registers associated with the SDMA are the SDMA address registers, read-only
register used for diagnostics in case of an SDMA bus error, the SDMA status register and the SDMA mask
register.
19.2.1 SDMA Status Register (SDSR)
The SDMA status register (SDSR), seen in Figure 19-3, reports bus error events recognized by the SDMA
controller for all 26 SDMA channels and 4 IDMA channels. On recognition of a bus error on the local or
60x buses, the SDMA sets its corresponding SDSR bit. The SDSR is a memory-mapped register that can
be read at any time. Bits are cleared by writing ones to them; writing zeros has no effect.
0
5
6
7
Field
Reset
Addr
—
SBER_L
SBER_P
0000_0000
Figure 19-3. SDMA Status Register (SDSR)
Table 19-1 describes SDSR fields.
Table 19-1. SDSR Field Descriptions
Description
Bits
Name
0–5
6
—
Reserved, should be cleared.
SBER_L SDMA channel local bus error. Indicates that the SDMA channel on the local bus had terminated
with an error during a read or write transaction. This bit is cleared writing a 1; writing a zero has no
effect. The SDMA transfer error address can be read from LDTEA, and the channel number from
LDTEM. Assertion of SBER_L causes the value inside LDTEA to stop updating. See Section 18.2.3,
“SDMA Transfer Error Address Registers (PDTEA and LDTEA).
7
SBER_P SDMA channel 60x bus error. Indicates that the SDMA channel on the 60x bus had terminated with
an error during a read or write transaction. This bit is cleared writing a 1; writing a zero has no effect.
The SDMA transfer error address is read from PDTEA. The channel number is read from PDTEM.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
19-3
SDMA Channels and IDMA Emulation
19.2.2 SDMA Mask Register (SDMR)
The SDMA mask register (SDMR) is an 8-bit read/write register with the same bit format as the SDMA
status register. If an SDMR bit is 1, the corresponding interrupt in SDSR is enabled. If the bit is zero, the
corresponding interrupt in the status register is masked. SDMR is cleared at reset. SDMR can be accessed
19.2.3 SDMA Transfer Error Address Registers (PDTEA and LDTEA)
There are two 32-bit, read-only SDMA address registers. The PDTEA holds the system address accessed
during an SDMA transfer error on the 60x bus. The LDTEA holds the system address accessed during an
SDMA transfer error on the local/PCI bus. LDTEA is constantly updated with memory address of the local
bus access regardless of whether SDMA error on the local bus has occurred. The address value inside
LDTEA stops updating when SDSR[SBRE_L] is asserted. Both registers are undefined at reset. PDTEA
19.2.4 SDMA Transfer Error MSNUM Registers (PDTEM and LDTEM)
There are two SDMA transfer error MSNUM registers (PDTEM and LDTEM). MSNUM[0–4] contains
the sub-block code (SBC) used to identify the current peripheral controller accessing the bus. MSNUM[5]
identifies which half of the controller is transferring (transmitter or receiver). The MSNUM of each
transaction is held in these registers until the transaction is complete.
PDTEM is for SDMA transfer errors on the 60x bus, and LDTEM is for errors on the local/PCI bus. Both
0
1
2
7
1
Field
Reset
R/W
—
MSNUM
—
R
Addr
1
On .29µm (HiP3) , Rev A.1 devices, MSNUM = [0–5]. For .25µm (HiP4) and all other .29µm devices, MSNUM = [2–6].
Figure 19-4. SDMA Transfer Error MSNUM Registers (PDTEM/LDTEM)
Table 19-2 describes PDTEM and LDTEM fields.
Table 19-2. PDTEM and LDTEM Field Descriptions
1
Bits
Name
Description
2
0–1
—
Reserved, should be cleared.
3
3
2–6 MSNUM[2–6] Bits 2–6 of MSNUM is the sub-block code of the current peripheral controller accessing the
bus. See the SBC field description of the CPCR in Section 14.4.1, “CP Command Register
(CPCR).”
4
4
7
MSNUM[7]
Bit 7 of MSNUM indicates which section of the peripheral controller is accessing the bus.
0 Transmit section
1 Receive section
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Freescale Semiconductor
SDMA Channels and IDMA Emulation
1
Bit ranges are for .29µm (HiP3) Rev B.3, C.2 and .25µm (HiP4) devices. For .29µm Rev A.1 devices, refer to notes
2–4.
2
3
4
On .29µm Rev A.1 devices, [6–7].
On .29µm Rev A.1 devices, MSNUM[0–4].
On .29µm Rev A.1 devices, MSNUM[5].
19.3 IDMA Emulation
The CPM can be configured to provide general-purpose DMA functionality through the SDMA channel.
Four general-purpose independent DMA (IDMA) channels are supported. In this special emulation mode,
the user can specify any memory-to-memory or peripheral-to/from-memory transfers as if using dedicated
DMA hardware.
The general-purpose IDMA channels can operate in different user-programmable data transfer modes. The
IDMA can transfer data between any combination of memory and I/O. In addition, data may be transferred
in either byte, half-word, word, double-word or burst quantities (note that IDMA cannot burst to or from
the dual-port RAM) and the source and destination addresses may be odd or even. The most efficient
packing algorithms are used in the IDMA transfers; however, anytime the IDMA has 0x10 or more bytes
to transfer, it will burst. The single-address mode (fly-by mode) gives the highest performance, allowing
data to be transferred between memory and a peripheral in a single bus transaction. The chip-select and
wait-state generation logic on the PowerQUICC II can be used with the IDMA.
The bus bandwidth occupied by the IDMA can be programmed in the IDMA parameter RAM to achieve
maximum system performance.
The IDMA supports two buffer handling modes—auto buffer and buffer chaining. The auto buffer mode
allows blocks of data to be repeatedly moved from one location to another without user intervention. The
buffer chaining mode allows a chain of blocks to be moved. The user specifies the data movement using
BD tables like those used by other peripheral controllers. The BD tables reside in the dual-port RAM.
Each IDMA has three signals (DREQx, DACKx and DONEx) for peripheral handshaking.
19.4 IDMA Features
The main IDMA features are as follows:
•
•
•
•
•
•
•
Four independent, fully programmable DMA channels
Dual- or single-address transfers with 32-bit address and 64-bit data capability
Memory-to-memory, memory-to-peripheral, and peripheral-to-memory modes
4-Gbyte maximum block length for each buffer
32-bit address pointers that can be optionally incremented
Two buffer handling modes—auto buffer and buffer chaining
Interrupts are optionally generated for BD transfer completion, external DONE assertion, and
STOP_IDMA command completion.
•
Any channel is independently configurable for data transfer from any 60x, local bus, or PCI source
to any 60x, local bus, or PCI destination
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Freescale Semiconductor
19-5
SDMA Channels and IDMA Emulation
•
•
Programmable byte-order conversion is supported independently for each DMA channel
Supports programmable 60x-bus bandwidth usage for system performance optimization
Peripheral to/from memory features include the following:
•
External DREQ, DACK, and DONE signals for each channel simplifies the peripheral interface for
memory-to/from-peripheral transfers
•
•
Supports 1-, 2-, 4-, and 8-byte peripheral port sizes
Supports standard 60x burst accesses (four consecutive 64-bit data phases) to/from peripherals
19.5 IDMA Transfers
The IDMA channel transfers data from a source to a destination using an intermediate transfer buffer (of
programmable size) in the dual-port RAM (note that the IDMA cannot burst to or from the dual-port
RAM). An efficient data-packing algorithm bursts data through the IDMA transfer buffer to minimize the
bus cycles needed for the transfer; however, the IDMA will burst when it has 0x10 or more bytes to
transfer. In single-address peripheral transfers, however, data is transferred directly between memory and
a peripheral device without using the IDMA transfer buffer.
Unaligned data is transferred in single accesses until alignment is achieved. Then, burst transactions are
used (if allowed by the user) to transfer the bulk of the data buffer. Single accesses are used again for any
remaining non-burstable data at the end of the transfer.
19.5.1 Memory-to-Memory Transfers
For memory-to-memory transfers, the IDMA first fills the IDMA transfer buffer in the dual-port RAM by
initiating read accesses on the source bus. It then empties the data from the internal transfer buffer to the
destination bus by initiating write accesses. The transfer sizes for the source and destination buses are
programmed in the IDMA parameter RAM.
For the DMA to generate bursts on the 60x bus, the address boundaries of each burst transfer must be
32-byte aligned. If the transfer does not start on a burst boundary, the IDMA controller transfers the
end-of-burst (EOB) data (1–31 bytes) in non-burst transactions on the source bus and on the destination
bus until reaching the next boundary. When alignment is achieved, subsequent data is bursted until the
remainder of the data in the buffer is less than a burst size (32 bytes). The remaining data is transferred
using non-burst transactions.
Table 19-3. IDMA Transfer Parameters
Parameter
Description
DMA_WRAP Determines the size of the dedicated IDMA transfer buffer in dual-port RAM. The buffer size is a
multiple of a 60x burst size (k*32 bytes).
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Freescale Semiconductor
SDMA Channels and IDMA Emulation
Table 19-3. IDMA Transfer Parameters (continued)
Description
Parameter
SS_MAX
Initialized to (IDMA_transfer_buffer_size - 32) bytes, which is the steady-state maximum transfer size
of IDMA transfer. This condition ensures that the transfer buffer is either filled by one SS_MAX bytes
transfer and emptied in one or several transfers, or filled by one or several transfers to be emptied in
one SS_MAX bytes transfer. In terms of bursts, if the transfer buffer contains k bursts (each is 32 bytes
long), then SS_MAX equals to k-1 bursts which is (k-1)*32 bytes.
STS/DTS
Source/destination transfer size. These parameters determine the access sizes in which the
source/destination is accessed in steady state of work. At least one of these values (DTS/STS) must
be initialized to the value of SS_MAX.
Figure 19-5 shows the IDMA transfer buffer.
DMA_WRAP determines IDMA transfer buffer size
(32 * k) bytes
EOB[0–31]
SS_MAX
(k-1)*32
128
96
64
32
Base Address (aligned to buffer size)
0
Figure 19-5. IDMA Transfer Buffer in the Dual-Port RAM
Each buffer’s contents are transferred in three phases:
•
First phase. The internal transfer buffer is filled with [EOB(alignment to source address) + SS_MAX]
bytes, read from the source bus. Then, if EOB(alignment to destination address) ≤ EOB(alignment to source
address), [EOB(destination) + SS_MAX] bytes are written from the transfer buffer to the destination
bus; or if EOB(destination) > EOB(source), [EOB(destination) + (k-2)*32] bytes are written bytes are
written. This write transfer size leaves a remainder of 0–31 bytes in the transfer buffer after the last
write burst of the steady-state phase. After the first phase, burst alignment is ensured.
•
•
Steady-state phase. The transfer buffer is filled with SS_MAX bytes (k-1 bursts), read from the
source bus in STS units. Then, SS_MAX bytes are written to the destination bus, in DTS units,
from the transfer buffer. Because alignment is ensured from first phase, all bus transfers are bursts.
This sequence is repeated until there are no more than SS_MAX bytes to be transferred. A
remainder of 0–31 bytes is left in the transfer buffer after the last burst write.
Last phase. The remaining data is read into the transfer buffer in bursts, with the last 1–31 bytes
read in single accesses. All data in the transfer buffer is written to the destination bus in bursts, with
the last 1–31 bytes written in single accesses. The last transfers, read/write or both can be
accompanied with DONE assertion, if programmed.
Figure 19-6 shows an example of the three IDMA transfer stages.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
19-7
SDMA Channels and IDMA Emulation
First Phase
128
EOB (source)
EOB (destination)
96
Read size = EOB(source) + SS_MAX
64
32
0
Write size = EOB(destination) + SS_MAX
Note: After phase 1, less than 32 bytes (a burst) will
remain in the internal buffer.
after first read
after first write
Steady-State Phase (2 transfers in this case)
Read size = SS_MAX
Write size = SS_MAX
Read size = SS_MAX
Write size = SS_MAX
after second read
Last Phase
after second write
after third read
after third write
Read size = remainder data of BD
Write size = all data left
after last read
after last write
Figure 19-6. Example IDMA Transfer Buffer States for a Memory-to-Memory Transfer (Size = 128 Bytes)
19.5.1.1 External Request Mode
Memory-to-memory transfers can be configured to operate in external request mode (DCM[ERM] = 1).
In external request mode, every read transfer is triggered by the assertion of DREQ. When the transfer
buffer is full, the first write transfer is done automatically. Additional write transfers, if needed, are
triggered by DREQ assertions. Because at least one of the transfer sizes (STS or DTS) equals SS_MAX,
every DREQ assertion causes one transfer to the smaller (in STS/DTS terms) bus. If STS = DTS, asserting
DREQ triggers one read transfer automatically followed by one write transfer.
NOTE
External request mode does not support external DONE signaling from a
device and DACK signaling from an IDMA channel.
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19.5.1.2 Normal Mode
When external request mode is not selected (DCM[ERM] = 0), the IDMA channel operates automatically,
ignoring DREQ.
19.5.1.3 Working with a PCI Bus
NOTE
This section applies to the MPC8250, the MPC8265, and the MPC8266
only.
When working to/from the PCI bus (multiplexed with the local bus), the data usually comes on the bus in
one long burst. The alignment policy described above to support 60x/local bus bursts does not affect its
efficiency.
19.5.2 Memory to/from Peripheral Transfers
Working with peripheral devices requires the external signals DONE, DREQ, DACK to control the data
transfer using the following rules:
•
The peripheral sets a request for data to be read-from/write-to by asserting DREQ as configured,
falling or rising edge sensitive.
•
•
•
The peripheral transfers/samples the data when DACK is asserted.
The peripheral asserts DONE to stop the current transfer.
The peripheral terminates the current transfer when DONE is asserted, combined with DACK, by
the IDMA.
Peripherals are usually accessed with fixed port-size transfers. The transfer sizes (STS/DTS) related to the
peripheral must be programmed to its port size; thus, every access to a peripheral yields a single bus
transaction. The maximum peripheral port size is (bus_width - 8) bytes and also should evenly divide the
buffer length, BD[Data Length].
A peripheral can also be configured to accept a burst per DREQ assertion. In this case, the transfer size
A peripheral can be accessed at a fixed address location or at incremental addresses. Setting DCM[SINC,
DINC] in the DMA channel mode register causes the address to be incremented before the next transfer;
same way it does peripherals.
DCM[S/D] determines whether the peripheral is the source or destination.
Data can be transferred between a peripheral and memory in single- or dual-address accesses:
•
For dual-address accesses, the data is read from the source, temporarily stored in the IDMA
transfer buffer in the dual-port RAM, and then written to the destination.
•
For single-address accesses (fly-by mode), the data is transferred directly between memory and the
peripheral. Memory responds to the address phase, while the peripheral ignores it and responds to
DACK assertions.
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Any IDMA access to a peripheral uses the highest arbitration priority allowed for the DMA, providing
faster bus access by bypassing other pending DMA requests.
19.5.2.1 Dual-Address Transfers
The following sections discuss various dual-address transfers.
19.5.2.1.1
Peripheral to Memory
Dual-address peripheral-to-memory data transfers are similar to memory-to-memory transfers using the
DREQ, data is loaded from the peripheral in port-size units to the internal transfer buffer. When the transfer
buffer reaches the steady-state level, it is automatically written to the memory destination in one transfer.
The source transfer size (STS) is initialized to the peripheral port size, and the destination transfer size
(DTS) is initialized to SS_MAX.
External requests must be enabled (DCM[ERM] = 1) for dual-address peripheral-to-memory transfers. If
DONE is asserted externally by the peripheral or if a STOP_IDMA command is issued, the current transfer
stops. All data in the internal transfer buffer is written to memory in one transfer before its BD is closed,
and the IDSR[EDN] or IDSR[SC] event bits are set; see Section 19.8.4, “IDMA Event Register (IDSR)
When the peripheral controls a transfer of unknown length, initialize a large enough buffer so that the
peripheral will most likely assert DONE before overflowing the buffer. When DONE is asserted, the BD
is closed and interrupts are generated (if enabled). The next DREQ assertion opens the next BD if
19.5.2.1.2
Memory to Peripheral
Dual-address memory-to-peripheral data transfers are similar to memory-to-memory transfers using the
SS_MAX and DTS is initialized to the peripheral port size. The first DREQ peripheral assertion triggers
a read of SS_MAX (or more in the first phase) bytes from the memory into the internal transfer buffer,
automatically followed by a write of DTS bytes to the peripheral. Subsequent DREQ assertions trigger
writes to the peripheral. When the transfer buffer has fewer than DTS bytes left, the next DREQ assertion
triggers a read of SS_MAX bytes from memory, automatically followed by a write to the peripheral, and
the sequence begins again.
External requests must be enabled (DCM[ERM] = 1) for dual-address peripheral-to-memory transfers. If
DONE is asserted externally by the peripheral or if a STOP_IDMA command is issued, the current transfer
is stopped, its BD is closed, and the IDSR[EDN] or IDSR[SC] event bits are set; see Section 19.8.4,
19.5.2.2 Single Address (Fly-By) Transfers
When DCM[FB] = 1, both peripheral-to-memory and memory-to-peripheral transfers occur in fly-by
mode; see Section 19.8.2.1, “DMA Channel Mode (DCM).” In fly-by mode, an internal transfer buffer is
not needed because the data is transferred directly between memory and the peripheral. Also, parameters
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related to the dual-port RAM bus are not relevant in fly-by mode. Each DREQ assertion triggers a transfer
the size of the peripheral port. All transfers are made in single memory accesses accompanied by DACK
assertion. When DONE is asserted externally or a STOP_IDMA command is issued, the current transfer is
stopped, its BD is closed, and the IDSR[EDN] or IDSR[SC] event bits are set; see Section 19.8.4, “IDMA
In fly-by mode, a peripheral can be configured to handle a burst per DREQ assertion if STS is programmed
to 32. The first phase of the transfer aligns the data to the burst boundary so that subsequent accesses can
be performed in bursts.
19.5.2.2.1
Peripheral-to-Memory Fly-By Transfers
During peripheral-to-memory fly-by transfers, the IDMA controller writes to memory while
simultaneously asserting DACK. The constant assertion of DACK enables the controller to write to
memory as soon as the peripheral outputs data to the bus. Thus, data is transferred from a peripheral to
memory in one data phase instead of two, increasing throughput.
For proper operation, STS must equal the peripheral port size.
19.5.2.2.2
Memory-to-Peripheral Fly-By Transfers
During memory-to-peripheral fly-by transfers, the IDMA controller reads from memory while
simultaneously asserting DACK.
The constant assertion of DACK enables the controller to read from memory as soon as the peripheral
samples the data bus. Thus, data is transferred from memory to a peripheral in one data phase instead of
two, increasing throughput.
For proper operation, DTS must equal the peripheral port size.
19.5.3 Controlling 60x Bus Bandwidth
STS, DTS, and SS_MAX can be used to control the 60x bus bandwidth occupied by the IDMA channel.
In every mode except fly-by mode, at least one transfer size parameter (STS/DTS) must be initialized to
the SS_MAX value. For memory-to-memory transfers, the other transfer size parameter can be initialized
to a smaller value used to control the 60x bus bandwidth. For example, if the transfer size is N*32 bytes,
each time the DMA controller wins arbitration, it transfers N bursts before releasing the bus. When
SS_MAX bytes have been transferred, the controller reverts to single transactions (double-word, word,
half-word, or byte).
Memory-to-memory transfer sizes must evenly divide into SS_MAX and also be a multiple of 32 (for
The size of the IDMA transfer buffer in the dual-port RAM should be determined by the largest transfer
(usually SS_MAX + 32 bytes) needed by one of the buses, while the other transfer size can be programmed
to control the bandwidth of the other bus.
Summarizing the above, a larger DMA transfer size provides for greater microcode efficiency and lower
DMA bus latency, because the DMA controller does not release the 60x bus until the transfer is completed.
If the DMA priority on the 60x bus is high, however, other 60x masters may experience a high bus latency.
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Conversely, if the transfer size is small, the DMA requests the 60x bus more often, DMA latency increases
and microcode efficiency decreases.
Example:
A channel is configured for data transfer from PCI memory to 60x memory. The PCI bus is not overloaded
and can stand large bursts. Thus, the dual-port RAM buffer size is set as follows:
•
64*32 = 2048 bytes (DCM[DMA_WRAP] = 101), allowing maximum of 2016 (STS = 63*32 =
2016) bytes long bursts at the source (PCI) bus.
•
•
The 60x bus is loaded. Small bursts are preferred. Setting DTS to 1*32 is best for minimizing the
contribution to the bus load. The dual-port RAM buffer is emptied in 63 DMA write transfers, of
one burst long each, before the next long DMA read. Setting DTS to 7*32 is better for the channel
performance, but is worse for the Bus since the dual-port RAM buffer is emptied in 9 DMA write
transfers, of 7 bursts each, before the next long PCI DMA read.
The 60x bus traffic is relatively low. Large bursts are preferred as long as they do not overload the
bus. Setting DTS to 63*32 (SS_MAX) might be enough, but are too large for most of the systems
because the dual-port RAM buffer would be written in one transfer to the 60x bus. On the other
hand, setting DTS to 9*32 is the solution for moderately loaded bus as the dual-port RAM buffer
is emptied in 7 DMA write transfers of nine bursts each before the next long PCI DMA read.
The IDMA transfer size parameters give high flexibility, but it is recommended to check overall system
performance with different IDMA parameter settings for maximum throughput.
Note that the memory priority parameter DCM[LP] should be considered when dealing with bus
bandwidth usage.
19.5.4 PCI Burst Length and Latency Control
NOTE
This section applies to the MPC8250, the MPC8265, and the MPC8266
only.
In general, PCI burst length is larger than the 60x burst length, it is variable in length and is limited by
system parameters such as latency timers. When the PCI bus is used, long bursts are preferred. The
dual-port RAM buffer size, combined with the transfer size parameter (STS/DTS) of the PCI bus, are used
to control its burst size. Long bursts are assigned by defining a big DPR buffer and setting the transfer size
of the PCI to be equal to SS_MAX. See the example in Section 19.5.3, “Controlling 60x Bus Bandwidth.”
The PCI bus, by nature, also has a long latency that should also be considered, especially when working
with peripherals, which usually require low latencies. A definition of a large dual-port RAM buffer may
end in a high latency, because it takes a long time, from the DREQ assertion until the buffer is filled and
data is provided.
The IDMA transfer size parameters give high flexibility to the user but it recommended to check the
overall performance of the system with different IDMA parameters setting for maximum throughput.
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19.6 IDMA Priorities
Each IDMA channel can be programmed to have a higher or lower priority relative to the serial controllers
or to have the lowest overall priority when requesting service from the CP. The IDMA priorities are
Take care to avoid overrun or underrun errors in the serial controllers when selecting high priorities for
IDMA.
Additional priority over all serial controllers can be selected by setting DCM[LP]; see Section 19.8.2.1,
19.7 IDMA Interface Signals
Each IDMA has three dedicated handshake control signals for transfers involving an external peripheral
device: DMA request (DREQ[1–4]), DMA acknowledge (DACK[1–4]) and DMA done (DONE[1–4]).
DREQx may also be used to control the transfer pace of memory-to-memory transfers.
•
•
•
DREQx is the external DMA request signal.
DACKx is the DMA acknowledge.
DONEx marks the end of an IDMA transfer.
The IDMA signals are multiplexed with other internal controller signals at the parallel I/O ports. To enable
the IDMA signals, the corresponding bits in the parallel I/O registers should be set. See Chapter 40,
19.7.1 DREQx and DACKx
When the peripheral requires IDMA service, it asserts DREQx and the PowerQUICC II begins the IDMA
process. When the IDMA service is in progress, DACKx is asserted during accesses to the peripheral. A
peripheral must validate the transfer by asserting TA or signal an error by asserting TEA.
If the user programs the memory controller for the peripheral, the PowerQUICC II asserts TA so that the
peripheral terminates DACKx. Without TA assertion, DACKx could be asserted for only one cycle, and
no data transfer occurs. To avoid peripherals mistaking this as a valid data transfer, DACKx should be
qualified with TA.
NOTE
Programming the parallel ports DREQ pins generates a transition on the
internal DREQ signals. This might cause an IDMA transaction, and, if the
IDMA is not initialized at that time, the IDMA transaction may lock the
CPM. Therefore, do one of the following:
•
Program the parallel ports to be DREQ after initializing the IDMA
registers and parameter RAM.
•
Pull down (pull-up does not help) the DREQ inputs before programming
the parallel port DREQ pins and until after setting the IDMA registers,
or program the IDMA registers for a dummy transaction before
programming the parallel port DREQ pins.
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DREQx may be configured as either edge- or level-sensitive by programming the RCCR[DRxM]. When
DREQx is configured as edge-sensitive, RCCR[EDMx] controls whether the request is generated on the
DREQx is sampled at each rising edge of the clock to determine when a valid request is asserted by the
device.
19.7.1.1 Level-Sensitive Mode
For external devices requiring very high data transfer rates, level-sensitive mode allows the IDMA to use
a maximum bandwidth to service the device. The device requests service by asserting DREQx and leaving
it asserted as long as it needs service. This mode is selected by setting the corresponding RCCR[DRxM].
The IDMA asserts DACK each time it issues a bus transaction to either read or write the peripheral. The
peripheral must use TA and TEA for data validation. DACK is the acknowledgment of the original burst
request given on DREQx. DREQx should be negated during the DACK active period to ensure that no
further transactions are performed.
When an IDMA is in external request mode and its DREQ is set to level-sensitive mode, the IDMA
requests service by the CPM whenever its DREQ signal is active. This is true regardless of whether or not
an IDMA is in progress. Therefore, whenever the IDMA's DREQ is active, all CPM peripherals with a
priority lower than the IDMA do not receive service. The IDMA priority can be configured via
RCCR[DRxQP] and, because DREQ may be active for long periods, systems that configure DREQ to be
level-sensitive must select priority option 3 for DRxQP to avoid starving other CPM peripherals (see Table
14-2 and Table 14-3). If more than one IDMA is given the same priority, the lower numbered IDMA has
priority over a higher numbered IDMA. For example, if both IDMA3 and IDMA4 are given priority
option 3, then IDMA3 will have priority over IDMA4.
In addition to the issue described in the previous paragraph, there is another issue to consider when an
IDMA is in external request mode and its DREQ is set to level-sensitive mode. When these are true and
the external peripheral device is controlled by one of the memory controllers of PowerQUICC II, such as
UPM or GPCM controller, DREQ must be negated before ‘tmax’ to prevent DREQ negation from
triggering an extra IDMA transfer cycle. Refer to the Figure 19-7. Note that T = 2 x CPM_CLK. In the
example shown, CPM_CLK = 133MHz, with an approximate clock cycle of 7.5ns. Therefore, T = 15ns
and DREQ must be negated no later than 15ns after the first rising edge of the bus clock after CS negation
for the peripheral.
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The first rising edge
of the bus clock after
the negation of the CS
for the peripheral.
Tmax
T = 2 x (CPM clock cycle)
Figure 19-7. Timing Requirement for DREQ Negation when IMDA Read from a Peripheral
19.7.1.2 Edge-Sensitive Mode
For external devices that generate a pulsed signal for each operand to be transferred, edge-sensitive mode
should be used. In edge-sensitive mode, the IDMA controller moves one operand for each falling/rising
(as configured by RCCR[EDMx]) edge of DREQx. This mode is selected by clearing the corresponding
RCCR[DRxM] and programming the corresponding RCCR[EDMx] to the proper edge.
When the IDMA controller detects a valid edge on DREQx, a request becomes pending and remains
pending until it is serviced by the IDMA. Subsequent changes on DREQx are ignored until the request
begins to be serviced. The servicing of the request results in one operand being transferred. Each time the
IDMA issues a bus transaction to either read or write the device, the IDMA asserts DACK. The device
must use TA and TEA for data validation. Thus, DACK is the acknowledgment of the original transaction
request given on DREQx.
19.7.2 DONEx
This bidirectional open-drain signal is used to indicate the last IDMA transfer. DONE can be an output of
the IDMA in the source or destination bus transaction if the transfer count is exhausted. This function is
controlled by BD[SDN, DDN].
DONE can also operate as an input. When operating in external request modes, DONE may be used as an
input to the IDMA controller to indicate that the device being serviced requires no more transfers. In that
case, the transfer is terminated, the current BD is closed, and an interrupt is generated (if enabled).
NOTE
DONE is ignored if it is asserted externally during internal request mode
(DCM[ERM] = 0).
DONE must not be asserted externally during memory-to-memory transfers
if external request mode is enabled (DCM[ERM] = 1).
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NOTE
When DREQ is level-sensitive and DONE is an input to the PowerQUICC
II, the system design must ensure that DONE is not asserted while DREQ is
also asserted. In other words, the system must not request IDMA service
and termination at the same time.
19.8 IDMA Operation
Every IDMA operation involves the following steps—IDMA channel initialization, data transfer, and
block termination.
•
During initialization, the core initializes the IDMA_BASE register in the internal parameter RAM
to point to the IDMA-specific table in RAM. This table contains control information for the IDMA
operation. In addition the core initializes the parallel I/O registers to enable IDMA external signals,
if needed, and other registers related to the channel priority and operation modes; see
point to the data for the transfer and/or a free space for data to be transferred to, and starts the
transfer by issuing the START_IDMA command.
•
•
During data transfer, the IDMA accepts requests for data transfers and provides addressing and bus
control for the transfers.
Termination occurs when the IDMA operation completes or the peripheral asserts DONE
externally. The core can initiate termination by using the STOP_IDMA command. The IDMA can
interrupt the core if interrupts are enabled to signal for operation termination and other events
related to the data transfer.
The IDMA uses a data structure, which, as with serial controller BDs, allows flexible data allocation and
eliminates the need for core intervention between transfers. BDs contain information describing the data
block and special control options for the DMA operation while transferring the data block.
19.8.1 Auto Buffer and Buffer Chaining
The core processor should initialize the IDMA BD table with the appropriate buffer handling mode, source
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IDMAx BD Base
Address (IBASE)
BD 0
BD 1
BD 2
Source Device or
Buffer 0
Destination Device or
Buffer 0
Source Device or
Buffer 1
Destination Device or
Buffer 1
•
•
•
Source Device or
Buffer 2
Destination Device or
Buffer 2
•
•
•
•
•
•
BD n
Source Device or
Destination Device or
Buffer n
Buffer n
Figure 19-8. IDMAx Channel’s BD Table
Data associated with each IDMA channel is stored in buffers and each buffer is referenced by a BD that
uses a circular table structure in the dual-port RAM. Control options such as interrupt and DONE assertion
are also programmed on a per-buffer basis in each BD.
Data may be transferred in the two following modes:
•
Auto buffer mode. The IDMA continuously transfers data to/from the location programmed in the
BD until a STOP_IDMA command is issued or DONE is asserted externally.
•
Buffer chaining mode. Data is transferred according to the first BD parameters, then the second BD
and so forth. The first BD is reused (if ready) until the BD with the last bit set is reached. IDMA
transfers stop and restarts when the BD table is reinitialized and a START_IDMA command is issued.
19.8.2 IDMAx Parameter RAM
When an IDMAx channel is configured to auto buffer or buffer chaining mode, the PowerQUICC II uses
the IDMAx parameters listed in the Table 19-4. Parameters should be modified only while the channel is
disabled, that is, before the first START_IDMA command or when the event register’s stop-completed bit
(IDSR[SC]) is set following a STOP_IDMA command.
Each IDMAx channel parameter table can be placed at any 64-byte aligned address in the dual-port RAM’s
general-purpose area (banks 1–8, 11 and 12). The CP accesses each IDMAx channel parameter table using
“Parameter RAM.” For example, if the IDMA1 channel parameter table is to be placed at address offset
0x2000 in the dual-port RAM, write 0x2000 to IDMA1_BASE.
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Table 19-4. IDMAx Parameter RAM
Width Description
1
Offset
Name
0x00
IBASE
Hword IDMA BD table base address. Defines the starting location in the dual-port RAM
for the set of IDMA BDs. It is an offset from the beginning of the dual-port RAM.
The user must initialize IBASE before enabling the IDMA channel and should not
overlap BD tables of two enabled serial controllers or IDMA channels or erratic
operation results. IBASE should be 16-byte aligned.
0x02
0x04
DCM
IBDPTR
Hword IDMA BD pointer. Points to the current BD during transfer processing. Points to
the next BD to be processed when an idle channel is restarted. Initialize to
IBASE before the first START_IDMA command. If BD[W] = 1, the CP initializes
IBPTR to IBASE When the end of an IDMA BD table is reached. After a
STOP_IDMA command is issued, IBDPTR points to the next BD to be processed.
It can be modified after SC interrupt is set and before a START_IDMA command
is reissued.
0x06
DPR_BUF
Hword IDMA transfer buffer base address. The base address should be aligned
according to the buffer size determined by DCM[DMA_WRAP]. The transfer
buffer size should be consistent with DCM[DMA_WRAP]; that is, DPR_BUF =
DMA_WRAP
(64 X 2
0x08
0x0A
BUF_INV
SS_MAX
Hword Internal buffer inventory. Indicates the quantity of data inside the internal buffer.
Hword Steady-state maximum transfer size in bytes. User-defined parameter to
increase microcode efficiency. Initialize to internal_buffer_size - 32, that is,
DMA_WRAP
SS_MAX = (64 X 2
) - 32. If possible, SS_MAX is used as the transfer
size on transfers to/from memory in memory-to-peripheral mode or in
peripheral-to-memory mode. For memory-to-memory mode, SS_MAX is used
as the transfer size for at least one of the devices. SS_MAX should be consistent
0x0C
0x0E
DPR_IN_PTR Hword Write pointer inside the internal buffer.
STS Hword Source transfer size in bytes. All transfers from the source (except the start
alignment and the end) are written to the bus using this parameter.
In memory-to-peripheral mode, STS should be initialized to SS_MAX.
In peripheral-to-memory mode, STS should be initialized to the peripheral port
for valid STS values for peripherals.
In fly-by mode, STS is initialized to the peripheral port size.
In memory-to-memory mode:
• STS should be initialized to SS_MAX.
• DTS value should be initialized to SS_MAX. STS can be initialized to values
other than SS_MAX in the following conditions:
– STS must divide SS_MAX.
– STS must be divided by 32 to enable bursts during the steady-state phase.
0x10
0x12
0x14
DPR_OUT_PTR Hword Read pointer inside the internal buffer.
SEOB
DEOB
Hword Source end of burst. Used for alignment of the first read burst.
Hword Destination end of burst. Used for alignment of the first write burst.
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Table 19-4. IDMAx Parameter RAM (continued)
Width Description
1
Offset
Name
0x16
DTS
Hword Destination transfer size in bytes. All transfers to destination (except the start
alignment and the tail) are written to the bus using this parameter.
In peripheral-to-memory mode, DTS should equal SS_MAX.
In memory-to-peripheral modes, initialize DTS to the peripheral port size if
transfer’s destination is a peripheral. Valid sizes for peripheral destination is 1,
2, 4, and 8 bytes, or peripheral transfer size (if the peripheral accepts bursts).
In fly-by mode, DTS is initialized to the peripheral port size.
• In memory-to-memory mode:
• DTS value is initialized to SS_MAX.
• STS value is initialized to SS_MAX. DTS can be initialized to values other
than SS_MAX in the following conditions:
– DTS must divide SS_MAX.
– DTS must be divided by 32, to enable bursts in steady-state phase.
0x18
0x1A
0x1C
0x20
0x24
0x28
RET_ADD
—
Hword Used to save return address when working in ERM = 1 mode.
Hword Reserved, should be cleared.
BD_CNT
S_PTR
D_PTR
ISTATE
Word Internal byte count.
Word Source internal data pointer.
Word Destination internal data pointer.
Word Internal. Should be cleared before every START_IDMA command.
1
From the pointer value programmed in IDMAx_BASE: IDMA1_BASE at 0x87FE, IDMA2_BASE at 0x88FE,
19.8.2.1 DMA Channel Mode (DCM)
RAM, that controls the operation modes of the IDMA channel. As are all other IDMA parameters, the
DCM is undefined at reset.
0
1
2
4
5
6
7
9
10
11
12
13
14
15
Field FB
LP
—
TC2
—
DMA_WRAP
SINC DINC ERM DT
S/D
Reset
R/W
—
R/W
Figure 19-9. DCM Parameters
Table 19-5 describes DCM bits.
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Table 19-5. DCM Field Descriptions
Description
Bits
Name
0
FB
0 Dual-address mode.
1 Fly-by (single-address) mode. The internal IDMA transfer buffer is not used. Valid only in
peripheral-to-memory (S/D=10) or memory-to-peripheral (S/D=01) modes.
1
LP
0 The IDMA transaction to memory is in middle CPM request priority.
1 The IDMA transaction to memory is in low CPM request priority.
Note that IDMA single-address (fly-by) transfers with external peripherals are always high
priority, ignoring this bit and bypassing other pending SDMA requests.
2–4
5
—
Reserved, should be cleared.
TC2
Driven on TC[2] during IDMA transactions. The TC[0–1] signals are always driven to 0b11
during IDMA transactions.
6
—
Reserved, should be cleared.
7–9
DMA_WRA DMA wrap. Defines the size of the IDMA transfer buffer. The IDMA pointer wraps to the
P
beginning of the buffer whenever DMA_WRAP bytes have been transferred to/from the buffer.
000 64 byte
001 128 byte
010 256 byte
011 512 byte
100 1024 byte
101 2048 byte
11x Reserved
SS_MAX, STS, DTD and DCM[S/D] parameters.
The IDMA transfer buffer (DPR_BUF) size should be consistent with DCM[DMA_WRAP]; that is
(DMA_WRAP)
DPR_BUF = 64 X 2
.
10
11
SINC
DINC
Source increment address.
0 Source address pointer (S_PTR) is not incremented in the source read transaction. Should
be cleared for peripheral-to-memory transfers if the peripheral has a fixed address.
1 CP increments the source address pointer (S_PTR) with the number of bytes transferred in
the source read transaction. Used for memory-to-memory and memory-to-peripheral
transfers.
In fly-by mode, SINC controls the memory address increment and should equal DINC.
Destination increment address.
0 Destination address pointer (D_PTR) is not changed in the destination write transaction.
Used for memory-to-peripheral transfers if the peripheral has a fixed address.
1 CP increments the destination pointer (D_PTR) with the number of bytes transferred in the
destination write transaction. Used for memory-to-memory and memory-to-peripheral
transfers.
In fly-by mode, DINC should equal SINC.
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SDMA Channels and IDMA Emulation
Table 19-5. DCM Field Descriptions (continued)
Description
Bits
Name
12
ERM
External request mode.
0 The CP transfers continuously, as if an external level request is asserted, regardless of the
DREQ signal assertion. The CP stops the transfer when there are no more valid BDs or after
a STOP_IDMA command is issued. DONE assertion by a external device is ignored.
1 The CP responds to DREQ as configured (edge/level) by performing single- or dual-address
transfers. The CP also responds to DONE assertions.
Note: Memory-to-memory transfers (S/D=00) with external request (ERM=1) is allowed, but
DONE assertion is not supported in this mode (DONE should be disabled).
13
DT
DONE treatment:
0 After external DONE assertion, the IDMA ignores further DREQ assertions. The CP closes
the current BD and IDMA stops. START_IDMA command should be issued before assertion of
another DREQ.
1 After external DONE assertion, the CP closes the current BD. The IDMA continues to the
next BD when DREQ is asserted.
14–1
5
S/D
00 Read from memory, write to memory.
10 Read from peripheral, write to memory.
01 Read from memory, write to peripheral.
11 Reserved
When a device is a peripheral:
• DACK is asserted during transfers to/from it.
• It may assert DONE to terminate all accesses to/from it.
• It can be operated in fly-by mode—respond to DACK ignoring the address.
• It gets highest DMA priority on the bus arbiter and the lowest DMA latency available.
19.8.2.2 Data Transfer Types as Programmed in DCM
Table 19-6 summarizes the types of data transfers according to the DCM programming.
Table 19-6. IDMA Channel Data Transfer Operation
S/D FB
Read From
Memory
Write To
Peripheral
Description (Steady-State Operation)
01
10
0
0
Read from memory: Filling internal buffer in one DMA transfer.
(STS = SS_MAX) (DTS = port size On the bus: one burst or more, depends on STS
or 32)
Write to peripheral: In smaller transfers until internal buffer empties.
On the bus: singles or burst, depends on DTS
Peripheral
(STS = port size or (DTS =
Memory
Read from peripheral: Filling internal buffer in several DMA
transfers.
32)
SS_MAX)
On the bus: singles or burst, depends on STS
Write to memory: in one DMA transfer, internal buffer empties.
On the bus: one burst or more, depends on DTS
00
0
Memory
Memory
Read from memory: Filling internal buffer in one DMA transfer.
On the bus: one burst or more, depends on STS
(STS = SS_MAX) (DTS =
SS_MAX or
less)
Write to memory: in one transfer or more until internal buffer
empties.
On the bus: singles or bursts, depends on DTS
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Table 19-6. IDMA Channel Data Transfer Operation (continued)
S/D FB
Read From
Memory
(STS = SS_MAX
or less)
Write To
Memory
(DTS =
SS_MAX)
Description (Steady-State Operation)
00
0
Read from memory: Filling internal buffer in one or more DMA
transfers.
On the bus: singles or bursts, depends on STS
Write to memory: in one DMA transfer, internal buffer empties.
On the bus: one burst or more, depends on DTS
01
10
1
1
Memory to
peripheral
(DTS = port size or
32)
—
Read transaction from memory while asserting DACK to
peripheral. Peripheral samples the data read from memory.
On the bus: singles or bursts, depends on DTS
—
Peripheral to
memory
Write transaction to memory while asserting DACK to peripheral.
Peripheral provides the data that is written to the memory.
(STS = port size On the bus: singles or bursts, depends on STS
or 32)
19.8.2.3 Programming DTS and STS
The options for setting STS and DTS depend on (DCM[DMA_WRAP]) and are described in the following
tables for memory/memory and memory/peripheral transfers.
Table 19-7 describes valid STS/DTS values for memory-to-memory operations.
Table 19-7. Valid Memory-to-Memory STS/DTS Values
Number of Transfers to Fill
Internal
Internal Buffer
DMA_WRAP Buffer SS_MAX
STS (in Bytes)
DTS (in Bytes)
Size
STS Size
DTS Size
1 * 32
32
32
1 * 32
1
1
000
001
010
011
100
64
128
256
512
1024
1 * 32
3 * 32
1
1
3 * 32
3 * 32, 32
3 * 32
1
1, 3
3 * 32, 32
7 * 32
1, 3
1
7 * 32, 32
7 * 32
1
1, 7
7 * 32
7 * 32, 32
15 * 32
1, 7
1
15 * 32, 3 * 32, 5 * 32, 32
15 * 32
1
1, 5, 3, 15
1
1, 5, 3, 15
15 * 32
31 * 32
15 * 32, 3 * 32, 5 * 32, 32
31 * 32
1
1, 31
1
31 * 32, 32
31 * 32
31 * 32, 32
1, 31
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SDMA Channels and IDMA Emulation
Table 19-7. Valid Memory-to-Memory STS/DTS Values
Number of Transfers to Fill
Internal Buffer
Internal
DMA_WRAP Buffer SS_MAX
Size
STS (in Bytes)
DTS (in Bytes)
STS Size
1
DTS Size
1, 7, 9, 63
1
63 * 32
63 * 32, 9 * 32, 7 * 32, 32
63 * 32
101
2048
63 * 32
63 * 32, 9 * 32, 7 * 32, 32
1, 7, 9, 63
Table 19-8 describes valid STS/DTS values for memory/peripheral operations.
Table 19-8. Valid STS/DTS Values for Peripherals
DMA_WRAP Internal Buffer Size SS_MAX
S/D Mode
STS (in Bytes)
DTS (in Bytes)
1
000
001
010
011
100
101
64
1 * 32
3 * 32
01
1 * 32
1, 2, 4, 8 (single) ; 32
2
(burst)
10
01
10
01
10
01
10
01
10
01
10
1, 2, 4, 8 (single); 32
(burst)
1 * 32
128
3 * 32
1, 2, 4, 8 (single); 32
(burst)
1, 2, 4, 8 (single); 32
(burst)
3 * 32
256
7 * 32
7 * 32
1, 2, 4, 8 (single); 32
(burst)
1, 2, 4, 8 (single); 32
(burst)
7 * 32
512
15 * 32
31 * 32
63 * 32
15 * 32
1, 2, 4, 8 (single); 32
(burst)
1, 2, 4, 8 (single); 32
(burst)
15 * 32
1024
2048
31 * 32
1, 2, 4, 8 (single); 32
(burst)
1, 2, 4, 8 (single); 32
(burst)
31 * 32
63 * 32
1, 2, 4, 8 (single); 32
(burst)
1, 2, 4, 8 (single); 32
(burst)
63 * 32
1
2
These values come out as a single transaction on the bus.
Peripherals that can accept bursts of 32 bytes are supported.
19.8.3 IDMA Performance
The transfer parameters STS, DTS, SS_MAX, and DMA_WRAP determine the amount of data transferred
for each START_IDMA command issued. Using large internal IDMA transfer buffers and the maximum
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SDMA Channels and IDMA Emulation
transfer sizes allows longer transfers to memory devices, optimizes bus usage and thus reduces the overall
load on the CP.
For example, 2,016 bytes can be transferred by issuing one START_IDMA command using a 2-Kbyte
internal transfer buffer, or by issuing 63 START_IDMA commands using a 64-byte buffer. The load on the
CP in the second case is about 63 times more than the first.
19.8.4 IDMA Event Register (IDSR) and Mask Register (IDMR)
The IDMA event (status) register (IDSR) is used to report events recognized by the IDMA controller. On
recognition of an event, the controller sets the corresponding IDSR bit. Each IDMA event bit can generate
a maskable interrupt to the core. Even bits are cleared by writing ones; writing zeros has no effect.
The IDMA mask register (IDMR) has the same format as IDSR. Setting IDMR bits enables, and clearing
IDMR bits disables, the corresponding interrupts in the event register.
Figure 19-10 shows the bit format for IDSR and IDMR.
0
3
4
5
6
7
Field
Reset
R/W
—
SC
OB
EDN
BC
0000_0000
R
R/W
Addr
Figure 19-10. IDMA Event/Mask Registers (IDSR/IDMR)
Table 19-9 describes IDSR/IDMR fields.
Table 19-9. IDSR/IDMR Field Descriptions
Bits
Name
Description
0–3
4
—
Reserved, should be cleared.
SC
Stop completed. Set after the IDMA channel completes processing the STOP_IDMA command. Do
not change channel parameters until SC is set.
5
6
OB
Out of buffers. Set to indicate that the IDMA channel encountered no valid BDs for the transfer.
EDN External DONE was asserted by device. Set to indicate that the IDMA channel terminated a transfer
because DONE was asserted by an external device, on the former SDMA transaction.
7
BC
BD completed. Set only after all data of a BD whose I (interrupt) bit is set has completed transfer to
the destination.
19.8.5 IDMA BDs
Source addresses, destination addresses, and byte counts are presented to the CP using the special IDMA
BDs. The CP reads the BDs, programs the SDMA channel, and notifies the core about the completion of
a buffer transfer using the IDMA BDs. This concept is similar to the one used for the serial controllers on
the PowerQUICC II except that the BD is larger because it contains additional information.
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SDMA Channels and IDMA Emulation
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Offset + 0
Offset + 2
Offset + 4
Offset + 6
Offset + 8
Offset + A
Offset + C
Offset + E
V
—
W
I
L
—
CM
—
SDN DDN DGBL
DBO
—
DDTB
—
SGBL
SBO
—
SDTB
—
Data Length
Source Data Buffer Pointer
Destination Data Buffer Pointer
Figure 19-11. IDMA BD Structure
Table 19-10 describes IDMA BD fields.
Table 19-10. IDMA BD Field Descriptions
Offset Bits
Name
V
Description
0x00
0
Valid
0 This BD does not contain valid data for transfer.
1 This BD contain valid data for transfer.
The CP checks this bit before starting a BD service. If this bit is cleared when the CP
accesses the BD, an interrupt IDSR[OB] is issued to the core, the IDMA channel is
stopped until a START_IDMA command is issued. After the BD is serviced this bit is
cleared by CP unless CM = 1.
1
2
—
Reserved, should be cleared.
W
Wrap (final BD in table)
0 This is not the last BD in the BD table.
1 Last BD in the table. After the associated buffer has been used, the CP transfers data
from the first BD in the table, which is pointed by IBASE. The number of BDs in this
table is programmable and determined by W bit and the overall space constraints of
the dual-port RAM.
3
4
I
Interrupt
0 No interrupt is generated after this buffer is serviced.
1 When the CP services all the buffer’s data, IDSR[BC] is set, which generates a
maskable interrupt.
L
Last
0 Not the last buffer of a chain to be transferred in buffer chaining mode. The I bit can
be used to generate an interrupt when this buffer service is complete.
1 Last buffer of a chain to be transferred in buffer chaining mode. When this BD service
is complete the channel is stopped by CP until START_IDMA command is issued.
This bit should be set only in buffer chaining mode (CM bit 6 = 0).
5
—
Reserved, should be cleared.
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Table 19-10. IDMA BD Field Descriptions (continued)
Description
Offset Bits
Name
CM
6
Continuous mode
0 Buffer chaining mode. The CP clears V after this BD is serviced. Buffer chaining
mode is used to transfer large quantities of data into non-contiguous buffer areas.
The user can initialize BDs ahead of time, if needed. The CP automatically loads the
IDMA registers from the next BD values when the transfer is terminated.
1 Auto buffer mode (continuous mode). The CP does not clear V after this BD is
serviced. This is the only difference between auto buffer mode and buffer chaining
mode. Auto buffer mode transfers multiple groups of data to/from a buffer table and
does not require BD reprogramming. The CP automatically reloads the IDMA
registers from the next BD values when the transfer is terminated. Either a single BD
or multiple BDs can be used to create an infinite loop of repeated data moves.
Note: The I bit can still be used to generate an interrupt in this mode.
7-8
9
—
Reserved, should be cleared.
SDN
Source done
0 DONE is inactive during this BD.
1 The IDMA asserts DONE at the last read data phase of the BD.
In fly-by mode (DCM[FB] = 1), SDN should be same as DDN.
10
11
DDN
DGBL
DBO
Destination done
0 DONE is inactive during this BD.
1 The IDMA asserts DONE at the last write data phase of the BD.
In fly-by mode (DCM[FB] = 1), DDN should be same as SDN.
Destination global
0 Snooping is not activated.
1 Snooping is activated for write transactions to the destination.
In fly-by mode, should be the same as SGBL.
12-13
Destination byte ordering:
01 Munged little Endian.
1x Big endian (Freescale).
00 Reserved
In fly-by mode, should be the same as SBO.
14
15
—
Reserved, should be cleared.
DDTB
Destination data bus.
0 The destination address lies within the 60x bus.
1 The destination address lies within the local bus.
In fly-by mode, should be the same as SDTB.
0x02
0-1
2
—
Reserved, should be cleared.
SGBL
Source global
0 Snooping is not activated.
1 Snooping is activated for read transactions from the source.
In fly-by mode, should be the same as DGBL.
3-4
SBO
Source byte ordering:
01 Munged little endian
1x Big endian (Freescale)
00 Reserved
In fly-by mode, should be the same as DBO.
5
—
Reserved, should be cleared.
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SDMA Channels and IDMA Emulation
Table 19-10. IDMA BD Field Descriptions (continued)
Description
Offset Bits
Name
SDTB
6
Source data bus.
0 The source address lies within the 60x bus.
1 The source address lies within the local or PCI buses.
In fly-by mode, should be the same as DDTB.
7-15
—
Reserved, should be cleared.
0x04 0–31
Data
Length
Number of bytes the IDMA transfers. Should be programmed to a value greater than
zero.
Note: When operating with a peripheral that accepts only single bus transactions
(transfer size < 32), data length should be a multiple of the peripheral transfer size
(STS for S/D = 10, or DTS for S/D = 01). Also, there is no error notification if the
data length does not match the buffer sizes.
0x08 0–31
Source
Buffer
Pointer
Holds the address of the associated buffer. Buffers may reside in internal or external
memory. Note that if the source/destination is a device, the pointer should contain the
device address.
In fly-by mode, the pointers should contain the memory address.
0x0C 0–31 Destination
Buffer
Pointer
19.9 IDMA Commands
The user has two commands to control each IDMA channel. These commands are executed through the
19.9.1 START_IDMA Command
The START_IDMA command is used to start a transfer on an IDMA channel. The user must initialize all
parameters relevant for the correct operation of the channel (IDMAx_BASE and IDMA channel parameter
table) before issuing this command.
To restart the channel operation, the START_IDMA command can be reissued after every pause in channel
activity. The user must ensure that parameters are correct for the channel to continue operation correctly.
The parameter ISTATE of the IDMA parameter RAM should be cleared before every issue of a
START_IDMA command.
An IDMA pause may occur for one of the following reasons:
•
The channel is out of buffers—IDSR[OB] event is set and an interrupt is generated to the core, if
enabled.
•
and an interrupt is generated to the core, if enabled.
•
•
STOP_IDMA command was issued.
The channel has finished a transfer of a BD with the last bit (L) set.
If the START_IDMA command is reissued and channel has more buffers to transfer, it restarts transferring
data according to the next BD in the buffer table.
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SDMA Channels and IDMA Emulation
In external request mode (ERM=1), the START_IDMA command initializes the channel, but the first data
transfer is performed after external DREQx assertion.
In internal request mode (ERM=0), the START_IDMA command starts the data transfer almost immediately,
with a delay which depends on the CP load.
19.9.2 STOP_IDMA Command
The STOP_IDMA command is issued to stop the transfer of an IDMA channel.
When a STOP_IDMA command is issued, the CP terminates current IDMA transfers and the current BD is
closed (if it was open). If memory is the destination, all data in the IDMA internal buffer is transferred to
memory before termination.
At the end of the stop process, the stop-completed event (SC) is set and a maskable interrupt is generated
to the core. The user should not modify channel parameters until SC = 1. When the channel is stopped, it
does not respond to external requests. If a START_IDMA command is reissued, the next BD in the BD table
is processed (if it is valid).
In external request mode (ERM = 1), STOP_IDMA command processing has priority over a peripheral
asserting DONE.
Note: In memory-to-peripheral, peripheral-to-memory, and fly-by modes, if a STOP_IDMA command is
issued with no data in the internal buffer, the BD is immediately closed and the channel is stopped. In this
case, a peripheral expecting DONE to be asserted is not notified because the last transfer of the buffer (with
BD[DDN or SDN] set) is not performed.
19.10 IDMA Bus Exceptions
Bus exceptions can occur while the IDMA has the bus and is transferring operands. In any computer
system, a hardware failure can cause an error during a bus transaction due to random noise or an illegal
access. When a synchronous bus structure (like those supported by the PowerQUICC II) is used, it is easy
to make provisions for a bus master to detect and respond to errors during a bus transaction. The IDMA
recognizes the same bus exceptions as the core, reset and transfer error, as described in Table 19-11.
Table 19-11. IDMA Bus Exceptions
Exception
Description
Reset
On an external reset, the IDMA immediately aborts the channel operation, returns to the idle state, and
clears IDSR. If reset is detected when a bus transaction is in progress, the transaction is terminated, the
control and address/data pins are three-stated, and bus mastership is released.
Transfer
Error
When a fatal error occurs during a bus transaction, a bus error exception is used to abort the transaction
and systematically terminate channel operation. The IDMA terminates the current bus transaction,
signals an error in the SDSR, and signals an interrupt if the corresponding bit in the SDMR is set. The
CPM must be reset before IDMA operation is restarted. Any data previously read from the source into the
internal storage is lost, however, issuing a START_IDMA command transfers the last BD again.
Note: Any source or destination device for an operand under IDMA handshake control for single-address
transfers may need to monitor TEA to detect a bus exception for the current bus transaction. TEA
terminates the transaction immediately and negates DACK, which is used to control the transfer to/from
the device.
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SDMA Channels and IDMA Emulation
19.10.1 Externally Recognizing IDMA Operand Transfers
The following ways can be used determine externally that the IDMA is executing a bus transaction:
•
The TC[2] signal (programmed in DCM[TC2]) or SDMA channels can be programmed to a unique
code that identifies an IDMA transfer.
•
The DACK signal shows accesses to the peripheral device. DACK activates on either the source
or destination bus transactions, depending on DCM[S/D].
19.11 Programming the Parallel I/O Registers
The parallel I/O registers control the use of the external pins of the chip. Each pin can be used for different
purposes. See Table 19-12, Table 19-13 and Table 19-14 (optional) for the proper parallel I/O register
programming dedicating the proper external ports to the four IDMA channels’ external I/O signals.
Each port is controlled by five I/O registers: PPAR, PSOR, PDIR, PODR, and PDAT. Each bit in these
registers controls the external pin of the same location.
•
•
•
•
•
PPARC selects the pins general purpose(0)/dedicated(1) mode for port C.
PDIRC select the pins input or inout (0)/output(1) mode for port C.
PODRC selects the open drain pins for port C.
PSORC selects the pins dedicated1(0)/dedicated2(1) mode for port C.
PPARA, PDIRA, PODRA, and PSORA control port A in the same way.
• PPARD, PDIRD, PODRD, and PSORD control port D in the same way.
•
The default is the value that is seen by the IDMA channel on the pin (input or inout mode
only—PDIR[PN] = 0) if a PSORx register bit is set to the complement value of the value in
Table 19-12. Parallel I/O Register Programming—Port C
Channel
Signal
Pin
PPARC
PDIRC
PODRC
PSORC
Default
IDMA1
IDMA2
DREQ1 (I)
DACK1 (O)
DONE1 (I/O)
DREQ2 (I)
PC[0]
PC[23]
PC[22]
PC[1]
PC[3]
PC[2]
1
1
1
1
1
1
0
1
0
0
1
0
0
0
1
0
0
1
0
1
1
0
1
1
GND
—
VDD
GND
—
DACK2 (O)
DONE2 (I/O)
VDD
Table 19-13 describes parallel I/O register programming for port A.
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SDMA Channels and IDMA Emulation
Table 19-13. Parallel I/O Register Programming—Port A
Channel
Signal
Pin
PPARA
PDIRA
PODRA
PSORA
Default
IDMA3
DREQ3 (I)
DACK3 (O)
DONE3 (I/O)
DREQ4 (I)
PA[0]
PA[2]
PA[1]
PA[5]
PA[3]
PA[4]
1
1
1
1
1
1
0
1
0
0
1
0
0
0
1
0
0
1
1
1
1
1
1
1
GND
—
VDD
GND
—
IDMA4
DACK4 (O)
DONE4 (I/O)
VDD
Table 19-14 describes parallel I/O register programming for port D (optional).
Table 19-14. Parallel I/O Register Programming—Port D
Channel
Signal
Pin
PPARD
PDIRD
PODRD
PSORD
Default
IDMA1
DACK1 (O)
PD[6]
PD[5]
1
1
1
0
0
1
1
1
—
DONE1 (I/O)
VDD
19.12 IDMA Programming Examples
These programming examples demonstrate the use of most of the different modes and configurations of
the IDMA channels.
19.12.1 Peripheral-to-Memory Mode (60x Bus to Local Bus)—IDMA2
In the example in Table 19-15, the IDMA2 channel reads 8 bytes per DREQ assertion from a fixed address
peripheral located on the 60x bus into the internal buffer. When there is enough data in the internal buffer,
it writes one burst to the memory located on the local bus. The internal buffer size is set to 64 bytes to
handle maximum transfer of a single burst. The IDMA2 channel asserts DONE on the last read transfer of
the last BD to notify the peripheral that there is no data left to transfer.
Table 19-15. Example: Peripheral-to-Memory Mode—IDMA2
Important Init Values
Description
DCM(FB) = 0
DCM(LP) = 0
Not in fly-by mode.
Transfers to memory have middle CPM request priority. The destination bus is not
overloaded.
DCM(DMA_WRAP) =
000
The internal buffer is 64 bytes long to support 32-byte transfers to memory on the
destination bus (one 60x burst) on steady-state of work.
DCM(ERM) = 1
DCM(DT) = 0
Transfers from peripheral are initiated by DREQ. DONE assertion is supported.
Assertion of DONE by the peripheral causes the transfer to be terminated, after writing all
the data in the internal buffer to memory, interrupt EDN is set to the core, IDMA channel is
stopped. additional DREQ assertions are ignored, until START_IDMA command is issued.
DCM(S/D) = 10
Peripheral-to-memory mode. DONE DREQ and DACK are connected to the peripheral.
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Table 19-15. Example: Peripheral-to-Memory Mode—IDMA2 (continued)
Important Init Values
Description
DCM(SINC) = 0
The peripheral address are not incremented after transfers, fixed location.
The memory address is incremented after every transfer.
DCM(DINC) = 1
DPR_BUF = 0x0DC0
Initiated to address aligned to 64 (bit[5–0]= 00000).
IBASE = IBDPTR =
0x0030
The current BD pointer is set to the BD table base address (aligned 16 -bits[3–0] = 0).
STS = 8 (0x0008)
Transfers from peripheral are always single 8-byte accesses.
Transfers to memory are 32 bytes long (60x bursts) on steady-state of work.
Peripheral is on the 60x bus.
DTS = 32 (0x0020)
Every BD(SDTB) = 0
Every BD(DDTB) = 1
Last BD(SDN) = 1
Memory is on the local bus.
DONE is asserted on the last transfer from peripheral.
DONE is not asserted on the last transfer to memory.
Data length must be STS modular (divided by STS without residue).
IDMA2 Mask register is programmed to enable EDN and BC interrupts only.
Last BD(DDN) = 0
Every BD(DL) = k*STS
IDMR2 = 0x0300_0000
SIMR_L = 0x0000_0200 Interrupt controller is programmed to enable interrupts from IDMA2.
PDIRC = 0x1000_0000 Parallel I/O registers are programmed to enable:PC[1] = DREQ2; PC[3] = DACK2; PC[2] =
PPARC = 0x7000_0000 DONE2.
PSORC = 0x3000_0000 The peripheral signals are to be connected to these lines accordingly.
PODRC = 0x2000_0000
RCCR = 0x0000_0000
IDMA2 configuration: DREQ is edge low-to-high. DONE is high-to-low. Request priority is
higher than the SCCs.
88FE = 0x0300
IDMA2_BASE points to 0x0300 where the parameter table base address is located for
IDMA2.
CPCR = 0x22A1_0009
START_IDMA command. IDMA2 page-01000 SBC-10101 op-1001 FLG=1.This write starts
the channel operation.
DMA operation description:
START_IDMA: Initialize all parameter RAM values, wait for DREQ to open the first BD. The four first DREQs trigger
single, 8-byte read transactions from the peripheral until data in the internal buffer is 32 bytes long. Then, a write
transaction to memory is done with the size needed for alignment.
Steady state: Every DREQ assertion triggers a read transaction of 8 bytes from the peripheral. If the data in the internal
buffer is more than 31 bytes a write transaction to memory of 32 bytes (one local burst) follows immediately. Memory
address is incremented constantly. Last read transaction of the last BD from the peripheral is combined with DONE
assertion.
STOP_IDMA: After all data in internal buffer is written to memory in one transfer, SC bit is set in IDSR (SC interrupt to
the core is not enabled) and BD is closed. Channel is stopped until START_IDMA command is reissued.
DONE assertion by the peripheral: All data in internal buffer is written to memory in one transfer. At the end of the
transfer, EDN interrupt is set to host. Additional DREQ assertions are ignored. IDMA2 channel is stopped until
START_IDMA command is issued.
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19-31
SDMA Channels and IDMA Emulation
19.12.2 Memory-to-Peripheral Fly-By Mode—IDMA3
In the example in Table 19-16, IDMA3 transfers data from a memory device to a 4-byte wide peripheral,
both on the 60x bus. The transfers are made by issuing 4-byte read transactions to the memory and
asserting DACK so the peripheral samples the data from the bus directly. No address is dedicated for the
peripheral, and no internal buffer is defined in this mode. The IDMA3 channel asserts DONE on the last
read transfer of the last BD to notify the peripheral that there is no data left to transfer.
Table 19-16. Example: Memory-to-Peripheral Fly-By Mode
(on 60x)–IDMA3
Important Init Values
Description
DCM[FB] = 1
DCM[LP] = x
Fly-by mode.
Don’t care. Transfer from memory to peripheral on the 60x bus is high priority.
DCM[DMA_WRAP] = DC Don’t care. No internal buffer is used.
DCM[ERM] = 1
DCM[DT] = 1
Transfers from peripheral are initiated by DREQ.
Assertion of DONE by the peripheral terminates the transfer, interrupt EDN is set to the
core, Current BD is closed and the next BD if valid is opened. Additional DREQ assertions
cause the new BD to be transferred.
DCM[S/D] = 01
DCM[SINC] = 1.
DCM[DINC] = 1
DPR_BUF
Memory-to-peripheral mode. DONE, DREQ, and DACK are connected to the peripheral.
The memory address is incremented after every transfer.
The memory address is incremented after every transfer.
The IDMA transfer buffer is not used.
IBASE = IBDPTR =
0x0030
The current BD pointer is set to the BD table base address (aligned 16 -bits[3–0]=0000).
STS = 0x0004
Transfers from memory to peripheral are always 4 bytes long (60x singles).
Transfers from memory to peripheral are always 4 bytes long (60x singles).
Memory and peripheral are on the 60x bus.
DTS = 0x0004
Every BD[SDTB] = 0
Every BD[DDTB] = 0
Last BD[SDN] = 1
Last BD[DDN] = 1
IDMR3 = 0x0400_0000
Memory and peripheral are on the 60x bus.
DONE is asserted on the last transfer.
DONE is asserted on the last transfer.
The IDMA3 mask register is programmed to enable the IDSR[OB] interrupt only.
SIMR_L = 0x0000_0100 The interrupt controller is programmed to enable interrupts from IDMA3.
PDIRA = 0x2000_0000 Parallel I/O registers are programmed to enable:PA[0] = DREQ3; PA[2] = DACK3; PA[1] =
PPARA = 0xE000_0000 DONE3.
PSORA = 0xE000_0000 The peripheral signals are to be connected to these lines accordingly.
PODRA = 0x4000_0000
RCCR = 0x0000_0080
IDMA3 configuration: DREQ is level high. DONE is high to low. request priority is higher
than the SCCs.
89FE = 0x0300
IDMA3_BASE points to 0x0300 where the parameter table base address is located for
IDMA3.
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SDMA Channels and IDMA Emulation
Table 19-16. Example: Memory-to-Peripheral Fly-By Mode
(on 60x)–IDMA3 (continued)
Important Init Values
Description
CPCR = 0x26C1_0009
START_IDMA command. IDMA3 page-01001 SBC-10110 op-1001 FLG=1.This write starts
the channel operation.
DMA operation:
START_IDMA: Initialize all parameter RAM values, wait for DREQ to open the first BD.
Steady state: Every DREQ triggers a 4-byte transfer in single address transaction. DMA performs a memory read
transaction combined with DACK assertion. Memory address is incremented constantly. Last transaction of the last
BD is combined with DONE assertion.Another DREQ assertion after last BD complete will issue IDSR[OB] interrupt
to the core.
STOP_IDMA: BD is closed. SC bit is set in IDSR (SC interrupt to the core is not enabled).Channel is stopped until
START_IDMA command is issued.
DONE assertion by the peripheral: current BD is closed. IDSR[EDN] is set (but the interrupt to the core is not
enabled).The next BD is open with the next DREQ assertion (or IDSR[OB] interrupt is set to the core if there is no other
valid BDs).
19.12.3 Memory-to-Memory (PCI Bus to 60x Bus)—IDMA1
NOTE
This section applies to the MPC8250, the MPC8265, and the MPC8266
only.
to one on the 60x bus. IDMA1 channel reads from the PCI bus into the internal buffer in one transfer and
writes to the 60x bus in nine consequent transfers of seven bursts each. It does this operation constantly by
using the internal request mode. The internal buffer is set to 2 Kbytes to maximize use of the PCI bus,
which is not too loaded.
The transfers to memory on the 60x bus are shorter, arbitration priority is low, and the internal request
priority of IDMA1 is lowest to prevent other device starvation on the 60x bus, which is loaded.
Table 19-17. Programming Example: Memory-to-Memory
(PCI-to-60x)—IDMA1
Important Init Values
Description
DCM[FB] = 0
DCM[LP] = 1
Not in fly-by mode.
Transfers to 60x have low priority; the destination bus is loaded by higher priority devices.
DCM[DMA_WRAP] = 101 The internal buffer is 2,048 bytes long. Transfers from memory on the source bus (PCI) can
be as long as possible (PCI has high arbitration latency and long bursts). Transfers on the
destination side are shorter, as defined in DTS.
DCM[ERM] = 0
IDMA transfers data continuously until a IDMA_STOP command is issued or until the
transfer complete.s DREQ, DONE, and DACK are not connected externally.
DCM[DT] = DC.
DCM[S/D] = 00
DCM[SINC] = 1
Do not care. DONE assertion is not defined in memory-to-memory mode.
Memory-to-memory mode.
The source memory address is incremented after transfers.
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19-33
SDMA Channels and IDMA Emulation
Table 19-17. Programming Example: Memory-to-Memory
(PCI-to-60x)—IDMA1 (continued)
Important Init Values
Description
DCM[DINC] = 1
The destination memory address is incremented after every transfer.
IBASE=IBDPTR= 0x0030 The current BD pointer is set to the BD ring Base address (aligned 16 -bits[3–0]=0000).
DPR_BUF = 0x0800 Initiated to address aligned to 2048 (bits[10–0] = 000_0000_0000).
SS_MAX = 2016(0x07e0) Initiated to (internal buffer size - 32) equal to STS in this mode.
STS = 2016(0x07e0)
DTS = 7*32 (0x00e0)
Transfers from memory on PCI are 2016 bytes long on steady state of work.
Transfers to memory on 60x are 224 bytes long (7 60x bursts) for steady-state operations.
We have low arbitration priority on the bus (LP = 1) but once we get it we would like to use
it for more that one burst.
every BD[SDTB] = 1
every BD[DDTB] = 0
last BD[SDN] = 0
last BD[DDN] = 0
last BD[L] = 1
Source memory is on the PCI (multiplexed with local) bus.
Destination memory is on the 60x bus.
DONE is not asserted on the last transfer from memory on PCI.
DONE is not asserted on the last transfer to memory on the 60x bus.
IDMA1 is stopped after last BD complete untill START_IDMA command is reissued.
IDMA1 set BC interrupt to the core after last BD complete.
IDMA1 Mask register is programmed to enable all interrupts.
Interrupt controller is programmed to enable interrupts from IDMA1.
IDMA1 configuration: Internal request priority is the lowest.
last BD[I]] = 0
IDMR1=0x0f000000
SIMR_L=0x00000800
RCCR=0x00200000
87FE=0x0100
IDMA1_BASE points to 0x0100 where the parameter table base address is located for
IDMA1.
CPCR=0x1e810009
DMA operation:
IDMA_start command. IDMA1 page-00111 SBC-10100 op-1001 FLG=1. This write starts
the channel operation.
START_IDMA: Initialize all parameter RAM values, start transferring data immediately from the first BD. Data is read from
PCI bus in single burst of (32 aligment + 2016) bytes long, to fill internal buffer.The first write transfer to the 60x bus is
(32 aligment + 6 or 7 burst) bytes long. The rest 8 write transfers are 7 burst long each.
Steady state: Internal buffer is filled in large burst from PCI (STS long). Data is transferred to the 60x bus in 9 transfers
of 7 burst long (DTS) each. Addresses are incremented constantly. Operation continues until the last BD is completed
or STOP_IDMA command is issued. When the last valid BD is complete BC interrupt is set to the core, and IDMA1
channel is stopped, until START_IDMA command is issued.
STOP_IDMA: after all data in internal buffer is written to the 60x bus, BD is closed and SC interrupt is set. Channel is
stopped until START_IDMA command is issued.
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Freescale Semiconductor
Chapter 20
Serial Communications Controllers (SCCs)
The PowerQUICC II has four serial communications controllers (SCCs), which can be configured
independently to implement different protocols for bridging functions, routers, and gateways, and to
interface with a wide variety of standard WANs, LANs, and proprietary networks. An SCC has many
physical interface options such as interfacing to TDM buses, ISDN buses, and standard modem interfaces.
The SCCs are independent from the physical interface, but SCC logic formats and manipulates data from
the physical interface. Furthermore, the choice of protocol is independent from the choice of interface. An
SCC is described in terms of the protocol it runs. When an SCC is programmed to a certain protocol or
mode, it implements functionality that corresponds to parts of the protocol’s link layer (layer 2 of the OSI
reference model). Many SCC functions are common to protocols of the following controllers:
•
•
•
•
•
•
Although the selected protocol usually applies both to the SCC transmitter and receiver, one half of an SCC
can run transparent operations while the other runs a standard protocol (except Ethernet).
Each Rx and Tx internal clock can be programmed with either an external or internal source. Internal
clocks originate from one of eight baud rate generators (BRGs) or an external clock pin; see Section 16.3,
“NMSI Configuration,” for each SCC’s available clock sources. These clocks can be as fast as a 1:4 ratio
of the system clock. (For example, an SCC internal clock can run at 12.5 MHz in a 50-MHz system.)
However, an SCC’s ability to support a sustained bit stream depends on the protocol as well as other
factors.
Associated with each SCC is a digital phase-locked loop (DPLL) for external clock recovery, which
supports NRZ, NRZI, FM0, FM1, Manchester, and Differential Manchester. If the clock recovery function
is not required (that is, synchronous communication), then the DPLL can be disabled, in which case only
NRZ and NRZI are supported.
An SCC can be connected to its own set of pins on the PowerQUICC II. This configuration is called the
non-multiplexed serial interface (NMSI) and is described in Chapter 15, “Serial Interface with Time-Slot
required, software and additional parallel I/O lines can be used to support additional handshake signals.
Figure 20-1 shows the SCC block diagram.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
20-1
Serial Communications Controllers (SCCs)
60x Bus
DPLL
and Clock
Recovery
TCLK
RCLK
Control
Registers
Clock
Generator
Peripheral Bus
Internal Clocks
Rx
Data
FIFO
Tx
Data
FIFO
Rx
Control
Unit
Tx
Control
Unit
Modem Lines
Decoder
Modem Lines
Encoder
RXD
Delimiter
Shifter
Shifter
Delimiter
TXD
Figure 20-1. SCC Block Diagram
20.1 Features
The following is a list of the main SCC features. (Performance figures assume a 25-MHz system clock.)
•
Implements HDLC/SDLC, HDLC bus, synchronous start/stop, asynchronous start/stop (UART),
AppleTalk/LocalTalk, and totally transparent protocols
•
•
Supports 10-Mbps Ethernet/IEEE 802.3 (half- or full-duplex) on all SCCs
Additional protocols may be available through the use of RAM-based microcodes. Please contact
your Freescale sales office.
•
DPLL circuitry for clock recovery with NRZ, NRZI, FM0, FM1, Manchester, and Differential
Manchester (also known as Differential Bi-phase-L)
•
•
•
•
Clocks can be derived from a baud rate generator, an external pin, or DPLL
Data rate for asynchronous communication can be as high as 16.62 Mbps at 133 MHz
Supports automatic control of the RTS, CTS, and CD modem signals
Multi-buffer data structure for receive and send (the number of buffer descriptors (BDs) is limited
only by the size of the internal dual-port RAM—8 bytes per BD)
•
•
•
Deep FIFOs (SCC transmit and receive FIFOs are 32 bytes each.)
Transmit-on-demand feature decreases time to frame transmission (transmit latency)
Low FIFO latency option for send and receive in character-oriented and totally transparent
protocols
•
•
Frame preamble options
Full-duplex operation
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Freescale Semiconductor
Serial Communications Controllers (SCCs)
•
•
Fully transparent option for one half of an SCC (Rx/Tx) while another protocol executes on the
other half (Tx/Rx)
Echo and local loopback modes for testing
20.1.1 The General SCC Mode Registers (GSMR1–GSMR4)
Each SCC contains a general SCC mode register (GSMR) that defines options common to most of the
high-order 32 bits. Some GSMR operations are described in later sections.
0
14
15
Field
Reset
R/W
—
0000_0000_0000_0000
R/W
Addr
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Field TCRC
Reset
REVD TRX TTX CDP CTSP CDS CTSS TFL RFW TXSY
SYNL
RTSM RSYN
0000_0000_0000_0000
R/W
R/W
Addr
0x11A06 (GSMR1); 0x11A26 (GSMR2); 0x11A46 (GSMR3); 0x11A66 (GSMR4)
Figure 20-2. GSMR_H—General SCC Mode Register (High Order)
Table 20-1 describes GSMR_H fields.
Table 20-1. GSMR_H Field Descriptions
Bit
Name
Description
0–15
—
Reserved, should be cleared.
16–17 TCRC Transparent CRC (valid for totally transparent channel only). Selects the frame checking provided
on transparent channels of the SCC (either the receiver, transmitter, or both, as defined by TTX and
TRX). Although this configuration selects a frame check type, the decision to send the frame check
is made in the TxBD. Thus, frame checks are not needed in transparent mode and frame check
errors generated on the receiver can be ignored.
00 16-bit CCITT CRC (HDLC). (X16 + X12 + X5 + 1).
01 CRC16 (BISYNC). (X16 + X15 + X2 + 1).
10 32-bit CCITT CRC (Ethernet and HDLC).
(X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X1 + 1).
11 Reserved.
18
REVD Reverse data (valid for a totally transparent channel only)
0 Normal operation.
1 Reverses the bit order for totally transparent channels on this SCC (either the receiver,
transmitter, or both) and sends the msb of each byte first. Section 23.11, “BISYNC Mode Register
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20-3
Serial Communications Controllers (SCCs)
Table 20-1. GSMR_H Field Descriptions (continued)
Description
Bit
Name
19–20 TRX, Transparent receiver/transmitter. The receiver, transmitter, or both can use totally transparent
TTX operation, regardless of GSMR_L[MODE]. For example, to configure the transmitter as a UART and
the receiver for totally transparent operations, set MODE = 0b0100 (UART), TTX = 0, and TRX = 1.
0 Normal operation.
1 The channel uses totally transparent mode, regardless of the protocol chosen in
GSMR_L[MODE].
For full-duplex totally transparent operation, set both TTX and TRX.
Note: An SCC cannot operate with half in Ethernet mode and half in transparent mode. That is, if
MODE = 0b1100 (Ethernet), erratic operation occurs unless TTX = TRX.
21, 22
CDP, CD/CTS pulse. If this SCC is used in the TSA and is programmed in transparent mode, set CTSP
0 Normal operation (envelope mode). CD/CTS should envelope the frame. Negating CD/CTS
during reception causes a CD/CTS lost error.
1 Pulse mode. Synchronization occurs when CD/CTS is asserted; further CD/CTS transitions do
not affect reception.
23, 24 CDS, CD/CTS sampling. Determine synchronization characteristics of CD and CTS. If the SCC is in
CTSS transparent mode and is used in the TSA, CDS and CTSS must be set. Also, CDS and CTSS must
be set for loopback testing in transparent mode.
0 CD/CTS is assumed to be asynchronous with data. It is internally synchronized by the SCC, then
data is received (CD) or sent (CTS) after several clock delays.
1 CD/CTS is assumed to be synchronous with data, which speeds up operation. CD or CTS must
transition while the Rx/Tx clock is low, at which time, the transfer begins. Useful for connecting
PowerQUICC II in transparent mode since the RTS of one PowerQUICC II can connect directly
to the CD/CTS of another.
25
26
TFL Transmit FIFO length.
0 Normal operation. The transmit FIFO is 32 bytes.
1 The Tx FIFO is 1 byte. This option is used with character-oriented protocols, such as UART, to
ensure a minimum FIFO latency at the expense of performance.
RFW Rx FIFO width.
0 Receive FIFO is 32 bits wide for maximum performance; the Rx FIFO is 32 bytes. Data is not
normally written to receive buffers until at least 32 bits are received. This configuration is required
for HDLC-type protocols and Ethernet and is recommended for high-performance transparent
protocols.
1 Low-latency operation. The receive FIFO is 8 bits wide, reducing the Rx FIFO to a quarter its
normal size. This allows data to be written to the buffer as soon as a character is received, instead
of waiting to receive 32 bits. This configuration must be chosen for character-oriented protocols,
such as UART. It can also be used for low-performance, low-latency, transparent operation.
However, it must not be used with HDLC, HDLC Bus, AppleTalk, or Ethernet because it causes
erratic behavior.
27
TXSY Transmitter synchronized to the receiver. Intended for X.21 applications where the transmitted data
must begin an exact multiple of 8-bit periods after the received data arrives.
0 No synchronization between receiver and transmitter (default).
1 The transmit bit stream is synchronized to the receiver. Additionally, if RSYN = 1, transmission in
totally transparent mode does not occur until the receiver synchronizes with the bit stream and
CTS is asserted to the SCC. Assuming CTS is asserted, transmission begins 8 clocks after the
receiver starts receiving data.
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Serial Communications Controllers (SCCs)
Table 20-1. GSMR_H Field Descriptions (continued)
Description
Bit
Name
28–29 SYNL Sync length (BISYNC and transparent mode only). See the data synchronization register (DSR)
Section 24.4.1.1, “In-Line Synchronization Pattern,” (transparent).
00 An external sync (CD) is used instead of the sync pattern in the DSR.
01 4-bit sync. The receiver synchronizes on a 4-bit sync pattern stored in the DSR. This sync and
additional syncs can be stripped by programming the SCC’s parameter RAM for character
recognition.
10 8-bit sync. Should be chosen along with the BISYNC protocol to implement mono-sync. The
receiver synchronizes on an 8-bit sync pattern in the DSR.
11 16-bit sync. Also called BISYNC. The receiver synchronizes on a 16-bit sync pattern stored in
the DSR.
30
31
RTSM RTS mode. Determines whether flags or idles are to be sent. Can be changed on-the-fly.
0 Send idles between frames as defined by the protocol and the TEND bit. RTS is negated between
frames (default).
1 Send flags/syncs between frames according to the protocol. RTS is always asserted whenever
the SCC is enabled.
RSYN Receive synchronization timing (totally transparent mode only).
0 Normal operation.
1 If CDS = 1, CD should be asserted on the second bit of the Rx frame rather than on the first.
Figure 20-3 shows GSMR_L.
0
1
2
3
4
5
6
7
8
10
11
12
13
14
15
Field
Reset
R/W
—
EDGE
TCI
TSNC
RINV TINV
TPL
TPP
TEND
TDCR
0000_0000_0000_0000
R/W
Addr
16
17
18
20
21
23
24
25
26
27
28
31
Field
Reset
R/W
RDCR
RENC
TENC
DIAG
ENR ENT
MODE
0000_0000_0000_0000
R/W
Addr
0x11A02 (SCC1); 0x11A22 (SCC2); 0x11A42 (SCC3); 0x11A62 (SCC4)
Figure 20-3. GSMR_L—General SCC Mode Register (Low Order)
Table 20-2 describes GSMR_L fields.
Table 20-2. GSMR_L Field Descriptions
Bit
Name
Description
0
—
Reserved, should be cleared.
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20-5
Serial Communications Controllers (SCCs)
Table 20-2. GSMR_L Field Descriptions (continued)
Description
Bit
Name
1–2
EDGE Clock edge. Determines the clock edge the DPLL uses to adjust the receive sample point due to
jitter in the received signal. Ignored in UART protocol or if the 1x clock mode is selected in RDCR.
00 Both the positive and negative edges are used for changing the sample point (default).
01 Positive edge. Only the positive edge of the received signal is used to change the sample point.
10 Negative edge. Only the negative edge of the received signal is used to change the sample
point.
11 No adjustment is made to the sample point.
3
TCI
Transmit clock invert.
0 Normal operation.
1 Before it is used, the internal Tx clock (TCLK) is inverted by the SCC so it can clock data out
one-half clock earlier (on the rising rather than the falling edge). In this case, the SCC offers a
minimum and maximum rising clock edge-to-data specification. Data output by the SCC after the
rising edge of an external Tx clock can be latched by the external receiver one clock cycle later
on the next rising edge of the same Tx clock. The edge on which the SCC outputs the data
depends on the mode of operation:
• In HDLC and Transparent mode, when TCI=0, data is sent on the falling edge; when TCI=1, on
the rising edge.
• In Ethernet mode, when TCI=0, data is sent on the rising edge; when TCI=1, on the falling edge.
Note: Recommended for Ethernet, HDLC, and transparent operation when clock rates exceed 8
MHz to improve data setup time for the external transceiver.
4–5
TSNC Transmit sense. Determines the amount of time the internal carrier sense signal stays active after
the last transition on RXD, indicating that the line is free. For instance, AppleTalk can use TSNC to
avoid a spurious CS-changed (SCCE[DCC]) interrupt that would otherwise occur during the frame
sync sequence before the opening flags. If RDCR is configured to 1× clock mode, the delay is the
greater of the two numbers listed. If RDCR is configured to 8×, 16×, or 32× mode, the delay is the
smaller number.
00 Infinite. Carrier sense is always active (default).
01 14- or 6.5-bit times as determined by RDCR.
10 4- or 1.5-bit times as determined by RDCR (normally for AppleTalk).
11 3- or 1-bit times as determined by RDCR.
6
7
RINV DPLL Rx input invert data. Must be zero in HDLC bus mode or asynchronous UART mode.
0 Do not invert.
1 Invert data before sending it to the DPLL for reception. Used to produce FM1 from FM0 and NRZI
space from NRZI mark or to invert the data stream in regular NRZ mode.
TINV DPLL Tx input invert data. Must be zero in HDLC bus mode.
0 Do not invert.
1 Invert data before sending it to the DPLL for transmission. Used to produce FM1 from FM0 and
NRZI space from NRZI mark and to invert the data stream in regular NRZ mode. In T1
applications, setting TINV and TEND creates a continuously inverted HDLC data stream.
8–10
TPL Tx preamble length. Determines the length of the preamble configured by the TPP bits.
000 No preamble (default).
001 8 bits (1 byte).
010 16 bits (2 bytes).
011 32 bits (4 bytes).
100 48 bits (6 bytes). Select this setting for Ethernet operation.
101 64 bits (8 bytes).
110 128 bits (16 bytes).
111 Reserved.
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Serial Communications Controllers (SCCs)
Table 20-2. GSMR_L Field Descriptions (continued)
Description
Bit
Name
11–12
TPP Tx preamble pattern. Determines what, if any, bit pattern should precede each Tx frame. The
preamble pattern is sent before the first flag/sync of the frame. TPP is ignored in UART mode. The
preamble length is programmed in TPL; the preamble pattern is typically sent to a receiving station
that uses a DPLL for clock recovery. The receiving DPLL uses the regular preamble pattern to help
it lock onto the received signal in a short, predictable time period.
00 All zeros.
01 Repetitive 10s. Select this setting for Ethernet operation.
10 Repetitive 01s.
11 All ones. Select this setting for LocalTalk operation.
13
TEND Transmitter frame ending. Intended for NRZI transmitter encoding of the DPLL. TEND determines
whether TXD should idle in a high state or in an encoded ones state (high or low). It can, however,
be used with other encodings besides NRZI.
0 Default operation. TXD is encoded only when data is sent, including the preamble and opening
and closing flags/syncs. When no data is available to send, the signal is driven high.
1 TXD is always encoded, even when idles are sent.
14–15 TDCR Transmitter/receiver DPLL clock rate. If the DPLL is not used, choose 1× mode except in
asynchronous UART mode where 8×, 16×, or 32× must be chosen. TDCR should match RDCR in
most applications to allow the transmitter and receiver to use the same clock source. If an
16–17 RDCR
application uses the DPLL, the selection of TDCR/RDCR depends on the encoding/decoding. If
communication is synchronous, select 1×. FM0/FM1, Manchester, and Differential Manchester
require 8×, 16×, or 32×. If NRZ- or NRZI-encoded communication is asynchronous (that is, clock
recovery required), select 8×, 16×, or 32×. The 8× option allows highest speed, whereas the 32×
option provides the greatest resolution.
00 1× clock mode. Only NRZ or NRZI encodings/decodings are allowed.
01 8× clock mode.
10 16× clock mode. Normally chosen for UART and AppleTalk.
11 32× clock mode.
18–20 RENC Receiver decoding/transmitter encoding method. Select NRZ if DPLL is not used. RENC should
equal TENC in most applications. However, do not use this internal DPLL for Ethernet.
21–23 TENC
000 NRZ (default setting if DPLL is not used). Required for UART (synchronous or asynchronous).
001 NRZI Mark (set RINV/TINV also for NRZI space).
010 FM0 (set RINV/TINV also for FM1).
011 Reserved.
100 Manchester.
101 Reserved.
110 Differential Manchester (Differential Bi-phase-L).
111 Reserved.
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Serial Communications Controllers (SCCs)
Table 20-2. GSMR_L Field Descriptions (continued)
Description
Bit
Name
24–25 DIAG Diagnostic mode.
00 Normal operation, CTS and CD are under automatic control. Data is received through RXD and
transmitted through TXD. The SCC uses modem signals to enable or disable transmission and
reception. These timings are shown in Section 20.3.5, “Controlling SCC Timing with RTS, CTS,
and CD.”
01 Local loopback mode. Transmitter output is connected internally to the receiver input, while the
receiver and the transmitter operate normally. The value on RXD is ignored. If enabled, data
appears on TXD, or the parallel I/O registers can be programmed to make TXD high. RTS can
also be programmed to be disabled in the appropriate parallel I/O register. The transmitter and
receiver must share the same clock source, but separate CLKx pins can be used if connected
to the same external clock source.
If external loopback is preferred, program DIAG for normal operation and externally connect TXD
and RXD. Then, physically connect the control signals (RTS connected to CD, and CTS
grounded) or set the parallel I/O registers so CD and CTS are permanently asserted to the SCC
by configuring the associated CTS and CD pins as general-purpose I/O.
10 Automatic echo mode. The transmitter automatically resends received data bit-by-bit using the
Rx clock provided. The receiver operates normally and receives data if CD is asserted. CTS is
ignored.
11 Loopback and echo mode. Loopback and echo operation occur simultaneously. CD and CTS are
ignored. See the loopback bit description above for clocking requirements.
26
ENR Enable receive. Enables the receiver hardware state machine for this SCC.
0 The receiver is disabled and data in the Rx FIFO is lost. If ENR is cleared during reception, the
receiver aborts the current character.
1 The receiver is enabled.
ENR can be set or cleared, regardless of whether serial clocks are present. Section 20.3.7,
“Reconfiguring the SCCs,” describes how to disable/enable an SCC. Note that other tools, including
the ENTER HUNT MODE and CLOSE RXBD commands and the E bit of the Rx BD, data provide the
capability to control the receiver.
27
ENT Enable transmit. Enables the transmitter hardware state machine for this SCC.
0 The transmitter is disabled. If ENT is cleared during transmission, the current character is aborted
and TXD returns to the idle state. Data already in the Tx shift register is not sent.
1 The transmitter is enabled.
ENT can be set or cleared, regardless of whether serial clocks are present. Section 20.3.7,
the STOP TRANSMIT, GRACEFUL STOP TRANSMIT, and RESTART TRANSMIT commands, the freeze option
and CTS flow control option in UART mode, and the R bit of the TxBD, also provide the capability to
control the transmitter.
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Serial Communications Controllers (SCCs)
Table 20-2. GSMR_L Field Descriptions (continued)
Description
Bit
Name
28–31 MODE Channel protocol mode. See also GSMR_H[TTX, TRX].
0000 HDLC
0001 Reserved
0010 AppleTalk/LocalTalk
0011 SS7—reserved for RAM microcode
0100 UART
0101 Profibus—reserved for RAM microcode
0110 Reserved
0111 Reserved
1000 BISYNC
1001 Reserved
101x Reserved
1100 Ethernet
11xx Reserved
20.1.2 Protocol-Specific Mode Register (PSMR)
The protocol implemented by an SCC is selected by its GSMR_L[MODE]. Each SCC has an additional
protocol-specific mode register (PSMR) that configures it specifically for the chosen protocol. The PSMR
fields are described in the specific chapters that describe each protocol. PSMRs are cleared at reset.
20.1.3 Data Synchronization Register (DSR)
Each SCC has a data synchronization register (DSR) that specifies the pattern used for frame
synchronization. The programmed value for DSR depends on the protocol:
•
•
•
•
UART—DSR is used to configure fractional stop bit transmission.
BISYNC and transparent—DSR should be programmed with the sync pattern.
Ethernet—DSR should be programmed with 0xD555.
HDLC—At reset, DSR defaults to 0x7E7E (two HDLC flags), so it does not need to be written.
Figure 20-4 shows the sync fields.
0
7
8
15
Field
Reset
R/W
SYN2
0111_1110
SYN1
0111_1110
R/W
Addr
Figure 20-4. Data Synchronization Register (DSR)
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20-9
Serial Communications Controllers (SCCs)
20.1.4 Transmit-on-Demand Register (TODR)
In normal operation, if no frame is being sent by an SCC, the CP periodically polls the R bit of the next
TxBD to see if a new frame/buffer is requested. Depending on the SCC configuration, this polling occurs
every 8–32 serial Tx clocks. The transmit-on-demand option, selected in the transmit-on-demand register
protocols where maximum inter-frame gap times are limited by the protocol specification.
0
15
Field TOD
—
Reset
R/W
0000_0000_0000_0000
W
Addr
Figure 20-5. Transmit-on-Demand Register (TODR)
The CP can be configured to begin processing a new frame/buffer without waiting the normal polling time
by setting TODR[TOD] after TxBD[R] is set. Because this feature favors the specified TxBD, it may affect
servicing of other SCC FIFOs. Therefore, transmitting on demand should only be used when a
high-priority TxBD has been prepared and enough time has passed since the last transmission. Table 20-3
describes TODR fields.
Table 20-3. TODR Field Descriptions
Bits
Name
Description
0
TOD Transmit on demand.
0 Normal operation.
1 The CP gives high priority to the current TxBD and begins sending the frame without waiting the
normal polling time to check the TxBD’s R bit. TOD is cleared automatically after one serial clock,
but transmitting on demand continues until an unprepared (R = 0) BD is reached. TOD does not
need to be set again if new TxBDs are added to the BD table as long as older TxBDs are still
being processed. New TxBDs are processed in order. The first bit of the frame is typically clocked
out 5-6 bit times after TOD is set.
1–15
—
Reserved, should be cleared.
20.2 SCC Buffer Descriptors (BDs)
Data associated with each SCC channel is stored in buffers and each buffer is referenced by a buffer
descriptor (BD) that can reside anywhere in dual-port RAM. The total number of 8-byte BDs is limited
only by the size of the dual-port RAM (128 BDs/1 Kbyte). These BDs are shared among all serial
controllers—SCCs, SMCs, SPI, and I2C. The user defines how the BDs are allocated among the
controllers.
Each 64-bit BD has the following structure:
•
The half word at offset + 0x0 contains status and control bits that control and report on the data
transfer. These bits vary from protocol to protocol. The CPM updates the status bits after the buffer
is sent or received.
•
The half word at offset + 0x2 (data length) holds the number of bytes sent or received.
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Serial Communications Controllers (SCCs)
— For an RxBD, this is the number of bytes the controller writes into the buffer. The CPM writes
the length after received data is placed into the associated buffer and the buffer closed. In
frame-based protocols (but not including SCC transparent operation), this field contains the
total frame length, including CRC bytes. Also, if a received frame’s length, including CRC, is
an exact multiple of MRBLR, the last BD holds no actual data but does contain the total frame
length.
— For a TxBD, this is the number of bytes the controller should send from its buffer. Normally,
this value should be greater than zero. The CPM never modifies this field.
•
The word at offset + 0x4 (buffer pointer) points to the beginning of the buffer in memory (internal
or external).
— For an RxBD, the value must be a multiple of four. (word-aligned)
— For a TxBD, this pointer can be even or odd.
control bits differ for each protocol.
0
15
Offset + 0
Offset + 2
Offset + 4
Offset + 6
Status and Control
Data Length
High-Order Buffer Pointer
Low-Order Buffer Pointer
Figure 20-6. SCC Buffer Descriptors (BDs)
For frame-oriented protocols, a message can reside in as many buffers as necessary. Each buffer has a
maximum length of 65,535 bytes. The CPM does not assume that all buffers of a single frame are currently
linked to the BD table. The CPM does assume, however, that the unlinked buffers are provided by the core
in time to be sent or received; otherwise, an error condition is reported—an underrun error when sending
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20-11
Serial Communications Controllers (SCCs)
Dual-Port RAM
External Memory
Tx Buffer Descriptors
Status and Control
Buffer Length
Buffer Pointer
SCCx TxBD
Table
Tx Buffer
Rx Buffer Descriptors
SCCx RxBD
Table
Status and Control
Buffer Length
SCCx RxBD
Table Pointer
Buffer Pointer
SCCx TxBD
Table Pointer
Rx Buffer
Figure 20-7. SCC BD and Buffer Memory Structure
In all protocols, BDs can point to buffers in the internal dual-port RAM. However, because dual-port RAM
is used for descriptors, buffers are usually put in external RAM, especially if they are large.
The CPM processes TxBDs straightforwardly; when the transmit side of an SCC is enabled, the CPM
starts with the first BD in that SCC TxBD table. Once the CPM detects that the R bit is set in the TxBD,
it starts processing the buffer. The CPM detects that the BD is ready when it polls the R bit or when the
user writes to the TODR. After data from the BD is put in the Tx FIFO, if necessary the CPM waits for the
next descriptor’s R bit to be set before proceeding. Thus, the CPM does no look-ahead descriptor
processing and does not skip BDs that are not ready. When the CPM sees a BD’s W bit (wrap) set, it returns
to the start of the BD table after this last BD of the table is processed. The CPM clears R (not ready) after
using a TxBD, which keeps it from being retransmitted before it is confirmed by the core. However, some
protocols support a continuous mode (CM), for which R is not cleared (always ready).
The CPM uses RxBDs similarly. When data arrives, the CPM performs required processing on the data
and moves resultant data to the buffer pointed to by the first BD; it continues until the buffer is full or an
event, such as an error or end-of-frame detection, occurs. The buffer is then closed; subsequent data uses
the next BD. If E = 0, the current buffer is not empty and it reports a busy error. The CPM does not move
from the current BD until E is set by the core (the buffer is empty). After using a descriptor, the CPM clears
E (not empty) and does not reuse a BD until it has been processed by the core. However, in continuous
mode (CM), E remains set. When the CPM discovers a descriptor’s W bit set (indicating it is the last BD
in the circular BD table), it returns to the beginning of the table when it is time to move to the next buffer.
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Serial Communications Controllers (SCCs)
20.3 SCC Parameter RAM
Each SCC parameter RAM area begins at the same offset from each SCC base area. Section 20.3.1, “SCC
parameter RAM are discussed in the specific protocol descriptions and the part that is common to all SCC
Some parameter RAM values must be initialized before the SCC can be enabled. Other values are
initialized or written by the CPM. Once initialized, most parameter RAM values do not need to be accessed
because most activity centers around the descriptors rather than the parameter RAM. However, if the
parameter RAM is accessed, note the following:
•
•
Parameter RAM can be read at any time.
Tx parameter RAM can be written only when the transmitter is disabled—after a STOP TRANSMIT
command and before a RESTART TRANSMIT command or after the buffer/frame finishes
transmitting after a GRACEFUL STOP TRANSMIT command and before a RESTART TRANSMIT
command.
•
•
Rx parameter RAM can be written only when the receiver is disabled. Note the CLOSE RXBD
command does not stop reception, but it does allow the user to extract data from a partially full Rx
buffer.
Table 20-4 shows the parameter RAM map for all SCC protocols. Boldfaced entries must be initialized by
the user.
Table 20-4. SCC Parameter RAM Map for All Protocols
1
Offset
Name
Width
Description
0x00
0x02
RBASE Hword Rx/TxBD table base address—offset from the beginning of dual-port RAM. The BD
tables can be placed in any unused portion of the dual-port RAM. The CPM starts BD
TBASE Hword
processing at the top of the table. (The user defines the end of the BD table by setting
the W bit in the last BD to be processed.) Initialize these entries before enabling the
corresponding channel. Erratic operations occur if BD tables of active SCCs overlap.
Values in RBASE and TBASE should be multiples of eight.
0x04
0x05
0x06
RFCR
TFCR
Byte
Byte
MRBLR Hword Maximum receive buffer length. Defines the maximum number of bytes the
PowerQUICC II writes to a receive buffer before it goes to the next buffer. The
PowerQUICC II can write fewer bytes than MRBLR if a condition such as an error or
end-of-frame occurs. It never writes more bytes than the MRBLR value. Therefore,
user-supplied buffers should be no smaller than MRBLR. MRBLR should be greater than
zero for all modes. It should be a multiple of 4 for Ethernet and HDLC modes, and in
totally transparent mode unless the Rx FIFO is 8-bits wide (GSMR_H[RFW] = 1).
Note: Although MRBLR is not intended to be changed while the SCC is operating, it can
be changed dynamically in a single-cycle, 16-bit move (not two 8-bit cycles).
Changing MRBLR has no immediate effect. To guarantee the exact Rx BD on
which the change occurs, change MRBLR only while the receiver is disabled.
Transmit buffer length is programmed in TxBD[Data Length] and is not affected by
MRBLR.
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Serial Communications Controllers (SCCs)
Table 20-4. SCC Parameter RAM Map for All Protocols (continued)
Width Description
RSTATE Word Rx internal state
1
Offset
Name
3
0x08
0x0C
2
Word Rx internal buffer pointer . The Rx and Tx internal buffer pointers are updated by the
SDMA channels to show the next address in the buffer to be accessed.
0x10
RBPTR Hword Current RxBD pointer. Points to the current BD being processed or to the next BD the
receiver uses when it is idling. After reset or when the end of the BD table is reached,
the CPM initializes RBPTR to the value in the RBASE. Although most applications do
not need to write RBPTR, it can be modified when the receiver is disabled or when no
Rx buffer is in use.
2
0x12
Hword Rx internal byte count . The Rx internal byte count is a down-count value initialized with
MRBLR and decremented with each byte written by the supporting SDMA channel.
3
0x14
0x18
0x1C
Word Rx temp
3
TSTATE Word Tx internal state
2
Word Tx internal buffer pointer . The Rx and Tx internal buffer pointers are updated by the
SDMA channels to show the next address in the buffer to be accessed.
0x20
TBPTR
Hword Current TxBD pointer. Points to the current BD being processed or to the next BD the
transmitter uses when it is idling. After reset or when the end of the BD table is reached,
the CPM initializes TBPTR to the value in the TBASE. Although most applications do not
need to write TBPTR, it can be modified when the transmitter is disabled or when no Tx
buffer is in use (after a STOP TRANSMIT or GRACEFUL STOP TRANSMIT command is issued
and the frame completes its transmission).
2
0x22
Hword Tx internal byte count . A down-count value initialized with TxBD[Data Length] and
decremented with each byte read by the supporting SDMA channel.
3
0x24
0x28
0x2C
0x30
Word Tx temp
2
RCRC
TCRC
Word Temp receive CRC
2
Word Temp transmit CRC
Protocol-specific area. (The size of this area depends on the protocol chosen.)
1
2
3
These parameters need not be accessed for normal operation but may be helpful for debugging.
For CP use only
20.3.1 SCC Base Addresses
The CPM maintains a section of RAM called the parameter RAM, which contains many parameters for
the operation of the FCCs, SCCs, SMCs, SPI, I2C, and IDMA channels. SCC base addresses are described
The exact definition of the parameter RAM is contained in each protocol subsection describing a device
that uses a parameter RAM. For example, the Ethernet parameter RAM is defined differently in some
locations from the HDLC-specific parameter RAM.
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Serial Communications Controllers (SCCs)
Table 20-5. Parameter RAM—SCC Base Addresses
1
Page
Address
Peripheral
Size (Bytes)
1
0x8000
0x8100
0x8200
0x8300
SCC1
SCC2
SCC3
SCC4
256
256
256
256
2
3
4
1
Offset from RAM_Base
20.3.2 Function Code Registers (RFCR and TFCR)
There are eight separate function code registers for the four SCC channels, four for Rx buffers
(RFCR1–RFCR4) and four for Tx buffers (TFCR1–TFCR4). The function code registers contain the
transaction specification associated with SDMA channel accesses to external memory. Figure 20-8 shows
the register format.
0
1
2
3
4
5
6
7
Field
Reset
R/W
—
GBL
BO
TC2
DTB
—
0000_0000_0000_0000
R/W
Addr
SCCx base + 0x04 (RFCRx); SCCx base + 0x05 (TFCRx)
Figure 20-8. Function Code Registers (RFCR and TFCR)
Table 20-6. RFCRx /TFCRx Field Descriptions
Bits
Name
Description
0–1
2
—
Reserved, should be cleared.
GBL Global
0 Snooping disabled.
1 Snooping enabled.
3–4
BO
Byte ordering. Set BO to select the required byte ordering for the buffer. If BO is changed on-the-fly,
it takes effect at the beginning of the next frame (Ethernet, HDLC, and transparent) or at the
beginning of the next BD.
00 Reserved
01 Munged little-endian.
1x Big-endian or true little-endian.
5
6
TC2 Transfer code. Contains the transfer code value of TC[2], used during this SDMA channel memory
access. TC[0–1] is driven with a 0b11 to identify this SDMA channel access as a DMA-type access.
DTB Data bus indicator
0 Use 60x bus for SDMA operation
1 Use local bus for SDMA operation
7
—
Reserved, should be cleared.
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Serial Communications Controllers (SCCs)
20.3.3 Handling SCC Interrupts
To allow interrupt handling for SCC-specific events, event, mask, and status registers are provided within
each SCC’s internal memory map area; see Table 20-7. Because interrupt events are protocol-dependent,
event descriptions are found in the specific protocol chapters.
Table 20-7. SCCx Event, Mask, and Status Registers
Register &
Description
IMMR Offset
SCCEx
SCC event register. This 16-bit register reports events recognized by any of the SCCs. When an
event is recognized, the SCC sets its corresponding bit in SCCE, regardless of the
corresponding mask bit. When the corresponding event occurs, an interrupt is signaled to the
SIVEC register. Bits are cleared by writing ones (writing zeros has no effect). SCCE is cleared
at reset and can be read at any time.
(SCCE1);
(SCCE2);
(SCCE3);
(SCCE4)
SCCMx
SCC mask register. The 16-bit, read/write register allows interrupts to be enabled or disabled
using the CPM for specific events in each SCC channel. An interrupt is generated only if SCC
interrupts in this channel are enabled in the SIU interrupt mask register (SIMR). If an SCCM bit
is zero, the CPM does not proceed with interrupt handling when that event occurs. The SCCM
and SCCE bit positions are identical.
(SCCM1);
(SCCM2);
(SCCM3);
(SCCM4)
SCCSx
SCC status register. This 8-bit, read-only register allows monitoring of the real-time status of
RXD.
(SCCS1);
(SCCS2);
(SCCS3);
(SCCS4)
Follow these steps to handle an SCC interrupt:
1. When an interrupt occurs, read SCCE to determine the interrupt sources and clear those SCCE bits
(in most cases).
2. Process the TxBDs to reuse them if SCCE[TX] or SCCE[TXE] = 1. If the transmit speed is fast or
the interrupt delay is long, the SCC may have sent more than one Tx buffer. Thus, it is important
to check more than one TxBD during interrupt handling. A common practice is to process all
TxBDs in the handler until one is found with its R bit set.
3. Extract data from the RxBD if SCCE[RX], SCCE[RXB], or SCCE[RXF] is set. As with transmit
buffers, if the receive speed is fast or the interrupt delay is long, the SCC may have received more
than one buffer and the handler should check more than one RxBD. A common practice is to
process all RxBDs in the interrupt handler until one is found with RxBD[E] set.
4. Execute the rfi instruction.
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Serial Communications Controllers (SCCs)
Additional information about interrupt handling can be found in Section 4.2, “Interrupt Controller.”
20.3.4 Initializing the SCCs
The SCCs require that a number of registers and parameters be configured after a power-on reset.
Regardless of the protocol used, follow these steps to initialize SCCs:
1. Write the parallel I/O ports to configure and connect the I/O pins to the SCCs.
2. Configure the parallel I/O registers to enable RTS, CTS, and CD if these signals are required.
3. If the time-slot assigner (TSA) is used, the serial interface (SIx) must be configured. If the SCC is
used in NMSI mode, CMXSCR must still be initialized.
4. Write all GSMR bits except ENT or ENR.
5. Write the PSMR.
6. Write the DSR.
7. Initialize the required values for this SCC’s parameter RAM.
8. Initialize the transmit/receive parameters via the CP command register (CPCR).
9. Clear out any current events in SCCE (optional).
10. Write ones to SCCM register to enable interrupts.
11. Set GSMR_L[ENT] and GSMR_L[ENR].
Descriptors can have their R or E bits set at any time. Notice that the CPCR does not need to be accessed
after a hardwarereset. An SCC should be disabled and reenabled after any dynamic change to its parallel
I/O ports or serial channel physical interface configuration. A full reset can also be implemented using
CPCR[RST].
20.3.5 Controlling SCC Timing with RTS, CTS, and CD
When GSMR_L[DIAG] is programmed to normal operation, CD and CTS are controlled by the SCC. In
the following subsections, it is assumed that GSMR_L[TCI] is zero, implying normal transmit clock
operation.
20.3.5.1 Synchronous Protocols
RTS is asserted when the SCC data is loaded into the Tx FIFO and a falling Tx clock occurs. At this point,
the SCC starts sending data once appropriate conditions occur on CTS. In all cases, the first data bit is the
start of the opening flag, sync pattern, or preamble.
Figure 20-9 shows that the delay between RTS and data is 0 bit times, regardless of GSMR_H[CTSS]. This
operation assumes that CTS is already asserted to the SCC or that CTS is reprogrammed to be a parallel
I/O line, in which case CTS to the SCC is always asserted. RTS is negated one clock after the last bit in
the frame.
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Serial Communications Controllers (SCCs)
TCLK
TXD
(Output)
First Bit of Frame DataLast Bit of Frame Data
RTS
(Output)
CTS
(Input)
NOTE:
1. A frame includes opening and closing flags and syncs, if present in the protocol.
Figure 20-9. Output Delay from RTS Asserted for Synchronous Protocols
When RTS is asserted, if CTS is not already asserted, delays to the first data bit depend on when CTS is
asserted. Figure 20-10 shows that the delay between CTS and the data can be approximately 0.5 to 1 bit
times or no delay, depending on GSMR_H[CTSS].
TCLK
TXD
(Output)
First Bit of Frame DataLast Bit of Frame Data
RTS
(Output)
CTS
(Input)
CTS Sampled Low Here
NOTE:
1. GSMR_H[CTSS] = 0. CTSP is a don’t care.
TCLK
TXD
(Output)
First Bit of Frame DatLaast Bit of Frame Data
RTS
(Output)
CTS
(Input)
NOTE:
1. GSMR_H[CTSS] = 1. CTSP is a don’t care.
Figure 20-10. Output Delay from CTS Asserted for Synchronous Protocols
If CTS is programmed to envelope data, negating it during frame transmission causes a CTS lost error.
Negating CTS forces RTS high and Tx data to become idle. If GSMR_H[CTSS] is zero, the SCC must
sample CTS before a CTS lost is recognized; otherwise, the negation of CTS immediately causes the CTS
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Serial Communications Controllers (SCCs)
TCLK
TXD
(Output)
Data Forced High
RTS Forced High
First Bit of Frame Data
RTS
(Output)
CTS
(Input)
CTS Sampled Low Here CTS Sampled High Here
CTS Lost Signaled in Frame B
NOTE:
1. GSMR_H[CTSS] = 0. CTSP=0 or no CTS lost can occur.
TCLK
TXD
(Output)
Data Forced High
RTS Forced High
First Bit of Frame Data
RTS
(Output)
CTS
(Input)
CTS Lost Signaled in Frame B
NOTE:
1. GSMR_H[CTSS] = 1. CTSP=0 or no CTS lost can occur.
Figure 20-11. CTS Lost in Synchronous Protocols
Note that if GSMR_H[CTSS] = 1, CTS transitions must occur while the Tx clock is low.
sampled on the rising Rx clock edge before data is received. If GSMR_H[CDS] is 1, CD transitions cause
data to be immediately gated into the receiver.
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Serial Communications Controllers (SCCs)
RCLK
RXD
(Input)
First Bit of Frame DaLtaast Bit of Frame Data
CD
(Input)
CD Sampled Low Here
CD Sampled High Here
NOTE:
1. GSMR_H[CDS] = 0. CDP=0.
2. If CD is negated prior to the last bit of the receive frame, CD lost is signaled in the frame BD.
3. If CDP=1, CD lost cannot occur and CD negation has no effect on reception.
RCLK
RXD
(Input)
First Bit of Frame DatLaast Bit of Frame Data
CD
(Input)
CD Assertion Immediately
Gates Reception
CD Negation Immediately
Halts Reception
NOTE:
1. GSMR_H[CDS] = 1. CDP=0.
2. If CD is negated prior to the last bit of the receive frame, CD lost is signaled in the frame BD.
3. If CDP=1, CD lost cannot occur and CD negation has no effect on reception.
Figure 20-12. Using CD to Control Synchronous Protocol Reception
If CD is programmed to envelope the data, it must remain asserted during frame transmission or a CD lost
error occurs. Negation of CD terminates reception. If GSMR_H[CDS] is zero, CD must be sampled by the
SCC before a CD lost error is recognized; otherwise, the negation of CD immediately causes the CD lost
condition.
If GSMR_H[CDS] is set, all CD transitions must occur while the Rx clock is low.
20.3.5.2 Asynchronous Protocols
In asynchronous protocols, RTS is asserted when SCC data is loaded into the Tx FIFO and a falling Tx
clock occurs. CD and CTS can be used to control reception and transmission in the same manner as the
synchronous protocols. The first bit sent in an asynchronous protocol is the start bit of the first character.
In addition, the UART protocol has an option for CTS flow control as described in Chapter 21, “SCC
•
•
If CTS is already asserted when RTS is asserted, transmission begins in two additional bit times.
If CTS is not already asserted when RTS is asserted and GSMR_H[CTSS] = 0, transmission begins
in three additional bit times.
• If CTSis not already asserted when RTS is asserted and GSMR_H[CTSS] = 1, transmission
begins in two additional bit times.
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Serial Communications Controllers (SCCs)
20.3.6 Digital Phase-Locked Loop (DPLL) Operation
Each SCC channel includes a digital phase-locked loop (DPLL) for recovering clock information from a
received data stream. For applications that provide a direct clock source to the SCC, the DPLL can be
bypassed by selecting 1x mode for GSMR_L[RDCR, TDCR]. If the DPLL is bypassed, only NRZ or
NRZI encodings are available. The DPLL must not be used when an SCC is programmed to Ethernet and
transmitter block diagram.
RENC
RDCR
Recovered Clock
HSRCLK
0
1
RCLK
Carrier SNC
EDGE
TSNC
DPLL
Receiver
S
Noise
Hunting
RINV
1x Mode
Decoded Data
RXD
HSRCLK
RINV
0
1
SCCR Data
RXD
S
RENC = NRZI
1x Mode
D
Q
HSRCLK
CLK
Figure 20-13. DPLL Receiver Block Diagram
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20-21
Serial Communications Controllers (SCCs)
TENC
TDCR
TEND
Divided Clock
HSTCLK
0
1
TCLK
TXEN
DPLL
Transmitter
S
HSTCLK
1x Mode
D
Q
HSTCLK
CLK
Encoded
SCCT Data
TINV
0
TXD
1
0
1
D
Q
S
HSTCLK
CLK
S
1x Mode
TENC = NRZI
Figure 20-14. DPLL Transmitter Block Diagram
The DPLL can be driven by one of the baud rate generator outputs or an external clock, CLKx. In the block
diagrams, this clock is labeled HSRCLK/HSTCLK. The HSRCLK/HSTCLK should be approximately 8x,
16x, or 32x the data rate, depending on the coding chosen. The DPLL uses this clock, along with the data
stream, to construct a data clock that can be used as the SCC Rx and/or Tx clock. In all modes, the DPLL
uses the input clock to determine the nominal bit time. If the DPLL is bypassed, HSRCLK/HSTCLK is
used directly as RCLK/TCLK.
At the beginning of operation, the DPLL is in search mode, whereas the first transition resets the internal
DPLL counter and begins DPLL operation. While the counter is counting, the DPLL watches the incoming
data stream for transitions; when one is detected, the DPLL adjusts the count to produce an output clock
that tracks incoming bits.
The DPLL has a carrier-sense signal that indicates when data transfers are on RXD. The carrier-sense
signal asserts as soon as a transition is detected on RXD; it negates after the programmed number of clocks
in GSMR_L[TSNC] when no transitions are detected.
To prevent itself from locking on the wrong edges and to provide fast synchronization, the DPLL should
receive a preamble pattern before it receives the data. In some protocols, the preceding flags or syncs can
function as a preamble; others use the patterns in Table 20-8. When transmission occurs, the SCC can
generate preamble patterns, as programmed in GSMR_L[TPP, TPL].
Table 20-8. Preamble Requirements
Decoding Method
NRZI Mark
Preamble Pattern
Minimum Preamble Length Required
All zeros
All ones
All ones
8-bit
8-bit
8-bit
NRZI Space
FM0
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Serial Communications Controllers (SCCs)
Table 20-8. Preamble Requirements (continued)
Decoding Method
FM1
Preamble Pattern
Minimum Preamble Length Required
All zeros
101010...10
All ones
8-bit
8-bit
8-bit
Manchester
Differential Manchester
The DPLL can also be used to invert the data stream of a transfer. This feature is available in all encodings,
including standard NRZ format. Also, when the transmitter is idling, the DPLL can either force TXD high
or continue encoding the data supplied to it.
The DPLL is used for UART encoding/decoding, which gives the option of selecting the divide ratio in
the UART decoding process (8×, 16×, or 32×). Typically, 16× is used.
Note the 1:4 system clock/serial clock ratio does not apply when the DPLL is used to recover the clock in
the 8×, 16×, or 32× modes. Synchronization occurs internally after the DPLL generates the Rx clock.
Therefore, even the fastest DPLL clock generation (the 8× option) easily meets the required 1:4 ratio
clocking limit.
20.3.6.1 Encoding Data with a DPLL
Each SCC contains a DPLL unit that can be programmed to encode and decode the SCC data as NRZ,
different encoding methods.
Data
NRZ
0
1
1
0
0
1
NRZI Mark
NRZI Space
FM0
FM1
Manchester
Differential
Manchester
Figure 20-15. DPLL Encoding Examples
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Serial Communications Controllers (SCCs)
If the DPLL is not needed, NRZ or NRZI codings can be selected in GSMR_L[RENC, TENC]. Coding
Table 20-9. DPLL Codings
Coding
NRZ
Description
A one is represented by a high level for the duration of the bit and a zero is represented by a low level.
NRZI Mark A one is represented by no transition at all. A zero is represented by a transition at the beginning of the
bit (the level present in the preceding bit is reversed).
NRZI
Space
A one is represented by a transition at the beginning of the bit (the level present in the preceding bit is
reversed). A zero is represented by no transition at all.
FM0
A one is represented by a transition only at the beginning of the bit. A zero is represented by a transition
at the beginning of the bit and another transition at the center of the bit.
FM1
A one is represented by a transition at the beginning of the bit and another transition at the center of the
bit. A zero is represented by a transition only at the beginning of the bit.
Manchester A one is represented by a high-to-low transition at the center of the bit. A zero is represented by a low to
high transition at the center of the bit. In both cases there may be a transition at the beginning of the bit
to set up the level required to make the correct center transition.
Differential A one is represented by a transition at the center of the bit with the opposite direction from the transition
Manchester at the center of the preceding bit. A zero is represented by a transition at the center of the bit with the
same polarity from the transition at the center of the preceding bit.
20.3.7 Reconfiguring the SCCs
The proper reconfiguration sequence must be followed for SCC parameters that cannot be changed
dynamically. For instance, the internal baud rate generators allow on-the-fly changes, but the
DPLL-related GSMR does not. The steps in the following sections show how to disable, reconfigure and
re-enable an SCC to ensure that buffers currently in use are properly closed before reconfiguring the SCC
and that subsequent data goes to or from new buffers according to the new configuration.
Modifying parameter RAM does not require the SCC to be fully disabled. See the parameter RAM
description for when values can be changed. To disable all peripheral controllers, set CPCR[RST] to reset
the entire CPM.
20.3.7.1 General Reconfiguration Sequence for an SCC Transmitter
An SCC transmitter can be reconfigured by following these general steps:
1. If the SCC is sending data, issue a STOP TRANSMIT command. Transmission should stop smoothly.
If the SCC is not transmitting (no TxBDs are ready or the GRACEFUL STOP TRANSMIT command
has been issued and completed) or the INIT TX PARAMETERS command is issued, the STOP
TRANSMIT command is not required.
2. Clear GSMR_L[ENT] to disable the SCC transmitter and put it in reset state.
3. Modify SCC Tx parameters or parameter RAM. To switch protocols or restore the initial Tx
parameters, issue an INIT TX PARAMETERS command.
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Serial Communications Controllers (SCCs)
4. If an INIT TX PARAMETERS command was not issued in step 3, issue a RESTART TRANSMIT
command.
5. Set GSMR_L[ENT]. Transmission begins using the TxBD pointed to by TBPTR, assuming
the R bit is set.
20.3.7.2 Reset Sequence for an SCC Transmitter
The following steps reinitialize an SCC transmit parameters to the reset state:
1. Clear GSMR_L[ENT].
2. Make any modifications then issue the INIT TX PARAMETERS command.
3. Set GSMR_L[ENT].
20.3.7.3 General Reconfiguration Sequence for an SCC Receiver
An SCC receiver can be reconfigured by following these steps:
1. Clear GSMR_L[ENR]. The SCC receiver is now disabled and put in a reset state.
2. Modify SCC Rx parameters or parameter RAM. To switch protocols or restore Rx parameters to
their initial state, issue an INIT RX PARAMETERS command.
3. If the INIT RX PARAMETERS command was not issued in step 2, issue an ENTER HUNT MODE
command.
4. Set GSMR_L[ENR]. Reception begins using the RxBD pointed to by RBPTR, assuming
the E bit is set.
20.3.7.4 Reset Sequence for an SCC Receiver
To reinitialize the SCC receiver to the state it was in after reset, follow these steps:
1. Clear GSMR_L[ENR].
2. Make any modifications then issue the INIT RX PARAMETERS command.
3. Set GSMR_L[ENR].
20.3.7.5 Switching Protocols
To switch an SCC’s protocol without resetting the board or affecting other SCCs, follow these steps:
1. Clear GSMR_L[ENT, ENR].
2. Make protocol changes in the GSMR and additional parameters then issue the INIT TX and RX
PARAMETERS command to initialize both Tx and Rx parameters.
3. Set GSMR_L[ENT, ENR] to enable the SCC with the new protocol.
20.3.8 Saving Power
To save power when not in use, an SCC can be disabled by clearing GSMR_L[ENT, ENR].
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Chapter 21
SCC UART Mode
The universal asynchronous receiver transmitter (UART) protocol is commonly used to send low-speed
data between devices. The term asynchronous is used because it is not necessary to send clocking
information along with the data being sent. UART links are typically 38400 baud or less and are
character-based. Asynchronous links are used to connect terminals with other devices. Even where
synchronous communications are required, the UART is often used as a local port to run board debugger
UART TCLK
8x, 16x, or 32x
(Not to scale)
UART TXD
Start
Bit
5, 6, 7, or 8 data bits with the
least significant bit first
Addr Parity
Bit Bit
9/16 to 2
stop bits
(Optional)
Figure 21-1. UART Character Format
Because the transmitter and receiver operate asynchronously, there is no need to connect the transmit and
receive clocks. Instead, the receiver oversamples the incoming data stream (usually by a factor of 16) and
uses some of these samples to determine the bit value. Traditionally, the middle 3 of the 16 samples are
used. Two UARTs can communicate using this system if the transmitter and receiver use the same
parameters, such as the parity scheme and character length.
When data is not sent, a continuous stream of ones is sent (idle condition). Because the start bit is always
a zero, the receiver can detect when real data is once again on the line. UART specifies an all-zeros break
character, which ends a character transfer sequence.
The most popular protocol that uses asynchronous characters is the RS-232 standard, which specifies baud
rates, handshaking protocols, and mechanical/electrical details. Another popular format is RS-485, which
defines a balanced line system allowing longer cables than RS-232 links. Even synchronous protocols like
HDLC are sometimes defined to run over asynchronous links. The Profibus standard extends UART
protocol to include LAN-oriented features such as token passing.
All standards provide handshaking signals, but some systems require only three physical lines—Tx data,
Rx data, and ground. Many proprietary standards have been built around the UART’s asynchronous
character frame, some of which implement a multidrop configuration where multiple stations, each with a
specific address, can be present on a network. In multidrop mode, frames of characters are broadcast with
the first character acting as a destination address. To accommodate this, the UART frame is extended one
bit to distinguish address characters from normal data characters.
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SCC UART Mode
In synchronous UART (isochronous operation), a separate clock signal is explicitly provided with the data.
Start and stop bits are present in synchronous UART, but oversampling is not required because the clock
is provided with each bit.
The general SCC mode register (GSMR) is used to configure an SCC channel to function in UART mode,
which provides standard serial I/O using asynchronous character-based (start-stop) protocols with
RS-232C-type lines. Using standard asynchronous bit rates and protocols, an SCC UART controller can
communicate with any existing RS-232-type device and provides a serial communications port to other
microprocessors and terminals (either locally or via modems). The independent transmit and receive
sections, whose operations are asynchronous with the core, send data from memory (either internal or
external) to TXD and receive data from RXD. The UART controller supports a multidrop mode for
master/slave operations with wake-up capability on both the idle signal and address bit. It also supports
synchronous operation where a clock (internal or external) must be provided with each bit received.
21.1 Features
The following list summarizes main features of an SCC UART controller:
•
•
•
•
•
Flexible message-based data structure
Implements synchronous and asynchronous UART
Multidrop operation
Receiver wake-up on idle line or address bit
Receive entire messages into buffers as indicated by receiver idle timeout or by control character
reception
•
•
•
•
•
•
•
•
•
•
•
Eight control character comparison
Two address comparison in multidrop configurations
Maintenance of four 16-bit error counters
Received break character length indication
Programmable data length (5–8 bits)
Programmable fractional stop bit lengths (from 9/16 to 2 bits) in transmission
Capable of reception without a stop bit
Even/odd/force/no parity generation and check
Frame error, noise error, break, and idle detection
Transmit preamble and break sequences
Freeze transmission option with low-latency stop
21.2 Normal Asynchronous Mode
In normal asynchronous mode, the receive shift register receives incoming data on RXDx. Control bits in
the UART mode register (PSMR) define the length and format of the UART character. Bits are received
in the following order:
1. Start bit
2. 5–8 data bits (lsb first)
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SCC UART Mode
3. Address/data bit (optional)
4. Parity bit (optional)
5. Stop bits
The receiver uses a clock 8×, 16×, or 32× faster than the baud rate and samples each bit of the incoming
data three times around its center. The value of the bit is determined by the majority of those samples; if
all do not agree, the noise indication counter (NOSEC) in parameter RAM is incremented. When a
complete character has been clocked in, the contents of the receive shift register are transferred to the
receive FIFO before proceeding to the receive buffer. The CPM flags UART events, including reception
errors, in SCCE and the RxBD status and control fields.
The SCC can receive fractional stop bits. The next character’s start bit can begin any time after the three
middle samples are taken. The UART transmit shift register sends outgoing data on TXDx. Data is then
clocked synchronously with the transmit clock, which may have either an internal or external source.
Characters are sent lsb first. Only the data portion of the UART frame is stored in the buffers because start
and stop bits are generated and stripped by the SCC. A parity bit can be generated in transmission and
checked during reception; although it is not stored in the buffer, its value can be inferred from the buffer’s
reporting mechanism. Similarly, the optional address bit is not stored in the transmit or receive buffer, but
is supplied in the BD itself. Parity generation and checking includes the optional address bit.
GSMR_H[RFW] must be set for an 8-bit receive FIFO in the UART receiver.
21.3 Synchronous Mode
In synchronous mode, the controller uses a 1× data clock for timing. The receive shift register receives
incoming data on RXDx synchronous with the clock. The bit length and format of the serial character are
defined by the control bits in the PSMR in the same way as in asynchronous mode. When a complete byte
has been clocked in, the contents of the receive shift register are transferred to the receive FIFO before
proceeding to the receive buffer. The CPM flags UART events, including reception errors, in SCCE and
the RxBD status and control fields. GSMR_H[RFW] must be set for an 8-bit receive FIFO.
The synchronous UART transmit shift register sends outgoing data on TXDx. Data is then clocked
synchronously with the transmit clock, which can have an internal or external source.
21.4 SCC UART Parameter RAM
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SCC UART Mode
Table 21-1. UART-Specific SCC Parameter RAM Memory Map
1
Offset
Name
Width
Description
0x30
0x38
—
DWord Reserved
MAX_IDL
Hword Maximum idle characters. When a character is received, the receiver begins
counting idle characters. If MAX_IDL idle characters are received before the next
data character, an idle timeout occurs and the buffer is closed, generating a
maskable interrupt request to the core to receive the data from the buffer. Thus,
MAX_IDL offers a way to demarcate frames. To disable the feature, clear
MAX_IDL. The bit length of an idle character is calculated as follows: 1 + data
length (5–9) + 1 (if parity is used) + number of stop bits (1–2). For 8 data bits, no
parity, and 1 stop bit, the character length is 10 bits.
0x3A
0x3C
IDLC
Hword Temporary idle counter. Holds the current idle count for the idle timeout process.
IDLC is a down-counter and does not need to be initialized or accessed.
BRKCR
Hword Break count register (transmit). Determines the number of break characters the
transmitter sends. The transmitter sends a break character sequence when a
STOP TRANSMIT command is issued. For 8 data bits, no parity, 1 stop bit, and
1 start bit, each break character consists of 10 zero bits.
16
0x3E
0x40
0x42
0x44
0x46
PAREC
FRMEC
NOSEC
BRKEC
BRKLN
Hword User-initialized,16-bit (modulo–2 ) counters incremented by the CP.
PAREC counts received parity errors.
FRMEC counts received characters with framing errors.
NOSEC counts received characters with noise errors.
BRKEC counts break conditions on the signal. A break condition can last for
Hword
Hword
Hword
hundreds of bit times, yet BRKEC is incremented only once during that period.
Hword Last received break length. Holds the length of the last received break character
sequence measured in character units. For example, if RXDx is low for 20 bit
times and the defined character length is 10 bits, BRKLN = 0x002, indicating that
the break sequence is at least 2 characters long. BRKLN is accurate to within
one character length.
0x48
0x4A
UADDR1
UADDR2
Hword UART address character 1/2. In multidrop mode, the receiver provides automatic
address recognition for two addresses. In this case, program the lower order
Hword
bytes of UADDR1 and UADDR2 with the two preferred addresses.
0x4C
0x4E
RTEMP
Hword Temp storage
TOSEQ
Hword Transmit out-of-sequence character. Inserts out-of-sequence characters, such
as XOFF and XON, into the transmit stream. The TOSEQ character is put in the
Tx FIFO without affecting a Tx buffer in progress. See Section 21.11, “Inserting
0x50
0x52
0x54
0x56
0x58
0x5A
0x5C
0x5E
CHARACTER1 Hword Control character 1–8. These characters define the Rx control characters on
which interrupts can be generated.
CHARACTER2 Hword
CHARACTER3 Hword
CHARACTER4 Hword
CHARACTER5 Hword
CHARACTER6 Hword
CHARACTER7 Hword
CHARACTER8 Hword
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SCC UART Mode
Table 21-1. UART-Specific SCC Parameter RAM Memory Map (continued)
1
Offset
Name
Width
Description
0x4C
0x60
RTEMP
Hword Temp storage
RCCM
Hword Receive control character mask. Used to mask comparison of CHARACTER1–8
so classes of control characters can be defined. A one enables the comparison,
and a zero masks it.
0x62
0x64
RCCR
RLBC
Hword Receive control character register. Used to hold the last rejected control
character (not written to the Rx buffer). Generates a maskable interrupt. If the
core does not process the interrupt and read RCCR before a new control
character arrives, the previous control character is overwritten.
Hword Receive last break character. Used in synchronous UART when PSMR[RZS] =
1; holds the last break character pattern. By counting zeros in RLBC, the core
can measure break length to a one-bit resolution. Read RLBC by counting the
zeros written from bit 0 to where the first one was written. RLBC =
0b001xxxxxxxxxxxxx indicates two zeros; 0b1xxxxxxxxxxxxxxx indicates no
zeros.
Note that RLBC can be used in combination with BRKLN above to calculate the
number of bits in the break sequence: (BRKLN * character length) + (number of
zeros in RLBC).
1
21.5 Data-Handling Methods: Character- or Message-Based
An SCC UART controller uses the same BD table and buffer structures as the other protocols and supports
both multibuffer, message-based and single-buffer, character-based operation.
For character-based transfers, each character is sent with stop bits and parity and received into separate
1-byte buffers. A maskable interrupt is generated when each buffer is received.
In a message-based environment, transfers can be made on entire messages rather than on individual
characters. To simplify programming and save processor overhead, a message is transferred as a linked list
of buffers without core intervention. For example, before handling input data, a terminal driver may wait
for an end-of-line character or an idle timeout rather than be interrupted when each character is received.
Conversely, ASCII files can be sent as messages ending with an end-of-line character.
When receiving messages, up to eight control characters can be configured to mark the end of a message
or generate a maskable interrupt without being stored in the buffer. This option is useful when flow control
characters such as XON or XOFF are needed but are not part of the received message. See Section 21.9,
21.6 Error and Status Reporting
Overrun, parity, noise, and framing errors are reported via the BDs and/or error counters in the UART
parameter RAM. Signal status is indicated in the status register; a maskable interrupt is generated when
status changes.
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SCC UART Mode
21.7 SCC UART Commands
Table 21-2. Transmit Commands
Command
Description
STOP
After a hardware or software reset and a channel is enabled in the GSMR, the transmitter starts polling
the first BD in the TxBD table every 8 Tx clocks. STOP TRANSMIT disables character transmission. If the
SCC receives STOP TRANSMIT as a message is being sent, the message is aborted. The transmitter
finishes sending data transferred to its FIFO and stops. The TBPTR is not advanced. The UART
transmitter sends a programmable break sequence and starts sending idles. The number of break
characters in the sequence (which can be zero) should be written to BRKCR in the parameter RAM
before issuing this command.
TRANSMIT
GRACEFUL
STOP
Used to stop transmitting smoothly. The transmitter stops after the current buffer has been completely
sent or immediately if no buffer is being sent. SCCE[GRA] is set once transmission stops, then the
UART Tx parameters, including the TxBD, can be modified. TBPTR points to the next TxBD in the table.
Transmission begins once the R bit of the next BD is set and a RESTART TRANSMIT command is issued.
TRANSMIT
RESTART
TRANSMIT
Enables transmission. The controller expects this command after it disables the channel in its PSMR,
after a STOP TRANSMIT command, after a GRACEFUL STOP TRANSMIT command, or after a transmitter error.
Transmission resumes from the current BD.
INIT TX
Resets the transmit parameters in the parameter RAM. Issue only when the transmitter is disabled. Note
PARAMETERS that INIT TX AND RX PARAMETERS resets both Tx and Rx parameters.
Table 21-3. Receive Commands
Command
Description
ENTER HUNT Forces the receiver to close the RxBD in use and enter hunt mode. After a hardware or software reset,
MODE
once an SCC is enabled in the GSMR, the receiver is automatically enabled and uses the first BD in the
RxBD table. If a message is in progress, the receiver continues receiving in the next BD. In multidrop
hunt mode, the receiver continually scans the input data stream for the address character. When it is
not in multidrop mode, it waits for the idle sequence (one character of idle). Data present in the Rx FIFO
is not lost when this command is executed.
CLOSE RXBD Forces the SCC to close the RxBD in use and use the next BD for subsequent received data. If the SCC
is not in the process of receiving data, no action is taken.
Note that in an SCC UART controller, CLOSE RXBD functions like ENTER HUNT MODE but does not need to
receive an idle character to continue receiving.
INIT RX
Resets the receive parameters in the parameter RAM. Should be issued when the receiver is disabled.
PARAMETERS Note that INIT TX AND RX PARAMETERS resets both Tx and Rx parameters.
21.8 Multidrop Systems and Address Recognition
In multidrop systems, more than two stations can be on a network, each with a specific address.
Figure 21-2 shows two examples of this configuration. Frames made up of many characters can be
broadcast as long as the first character is the destination address. The UART frame is extended by one bit
to distinguish an address character from standard data characters. Programmed in PSMR[UM], the
controller supports the following two multidrop modes:
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SCC UART Mode
•
•
Automatic multidrop mode—The controller checks the incoming address character and accepts
subsequent data only if the address matches one of two user-defined values. The two 16-bit address
registers, UADDR1 and UADDR2, support address recognition. Only the lower 8 bits are used so
the upper 8 bits should be cleared; for addresses less than 8 bits, unused high-order bits should also
be cleared. The incoming address is checked against UADDR1 and UADDR2. When a match
occurs, RxBD[AM] indicates whether UADDR1 or UADDR2 matched.
Manual multidrop mode—The controller receives all characters. An address character is always
written to a new buffer and can be followed by data characters. User software performs the address
comparison.
1
2
3
4
+ V
Tx
Rx
Tx
Rx
Tx
Rx
Tx
Rx
R
Master
Tx Rx
Slave 1
Tx Rx
Slave 2
Tx Rx
Slave 3
Tx Rx
+ V
R
UADDR1
UADDR2
PAODR
Choose wired-or operation in the port A
open-drain register to allow multiple transmit
pins to be directly connected
Two 8-bit addresses can be automatically
recognized in either configuration
Figure 21-2. Two UART Multidrop Configurations
21.9 Receiving Control Characters
The UART receiver can recognize special control characters used in a message-based environment. Eight
control characters can be defined in a control character table in the UART parameter RAM. Each incoming
character is compared to the table entries using a mask (the received control character mask, RCCM) to
strip don’t cares. If a match occurs, the received control character can either be written to the receive buffer
or rejected.
If the received control character is not rejected, it is written to the receive buffer. The receive buffer is then
automatically closed to allow software to handle end-of-message characters. Control characters that are
not part of the actual message, such as XOFF, can be rejected. Rejected characters bypass the receive
buffer and are written directly to the received control character register (RCCR), which triggers maskable
interrupt.
The 16-bit entries in the control character table support control character recognition. Each entry consists
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SCC UART Mode
1
Offset
0
1
2
7
8
15
0x50
0x52
E
R
—
—
CHARACTER1
CHARACTER2
E
R
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
0x5E
0x60
E
1
R
1
—
—
CHARACTER8
RCCM
0x62
—
RCCR
1
From SCCx base address
Figure 21-3. Control Character Table
Table 21-4 describes the data structure used in control character recognition.
Table 21-4. Control Character Table, RCCM, and RCCR Descriptions
Offset Bits
Name
Description
0x50–
0x5E
0
E
R
End of table. In tables with eight control characters, E is always 0.
0 This entry is valid.
1 The entry is not valid and is not used.
1
Reject character.
0 A matching character is not rejected but is written into the Rx buffer, which is
then closed. If RxBD[I] is set, the buffer closing generates a maskable interrupt
through SCCE[RX]. A new buffer is opened if more data is in the message.
1 A matching character is written to RCCR and not to the Rx buffer. A maskable
interrupt is generated through SCCE[CCR]. The current Rx buffer is not closed.
2–7
—
Reserved
8–15 CHARACTERn Control character values 1–8. Defines control characters to be compared to the
incoming character. For characters smaller than 8 bits, the most significant bits
should be zero.
0x60
0–1 0b11
Must be set. Used to mark the end of the control character table in case eight
characters are used. Setting these bits ensures correct operation during control
character recognition.
2–7
—
Reserved
8–15 RCCM
Received control character mask. Used to mask the comparison of
CHARACTERn. Each RCCM bit corresponds to the respective bit of
CHARACTERn and decodes as follows.
0 Ignore this bit when comparing the incoming character to CHARACTERn.
1 Use this bit when comparing the incoming character to CHARACTERn.
0x62
0–7
—
Reserved
8–15 RCCR
Received control character register. If the newly arrived character matches and is
rejected from the buffer (R = 1), the PIP controller writes the character into the
RCCR and generates a maskable interrupt. If the core does not process the
interrupt and read RCCR before a new control character arrives, the previous
control character is overwritten.
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SCC UART Mode
21.10 Hunt Mode (Receiver)
A UART receiver in hunt mode remains deactivated until an idle or address character is recognized,
depending on PSMR[UM]. A receiver is forced into hunt mode by issuing an ENTER HUNT MODE
command.
The receiver aborts any message in progress when ENTER HUNT MODE is issued. When the message is
finished, the receiver is reenabled by detecting the idle line (one idle character) or by the address bit of the
next message, depending on PSMR[UM]. When a receiver in hunt mode receives a break sequence, it
increments BRKEC and generates a BRK interrupt condition.
21.11 Inserting Control Characters into the Transmit Data Stream
The SCC UART transmitter can send out-of-sequence, flow-control characters like XON and XOFF. The
transmitter is enabled for UART operation, including during a UART freeze operation, UART buffer
transmission, and when no buffer is ready for transmission. The TOSEQ character (in CHARSEND) is
sent at a higher priority than the other characters in the transmit buffer, but does not preempt characters
already in the transmit FIFO. This means that the XON or XOFF character may not be sent for eight or
four (SCC) character times. To reduce this latency, set GSMR_H[TFL] to decrease the FIFO size to one
character before enabling the transmitter.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Field
Reset
R/W
—
REA
I
CT
—
A
CHARSEND
0000_0000_0000_0000
R/W
Addr
SCC base + 0x4E
Figure 21-4. Transmit Out-of-Sequence Register (TOSEQ)
Table 21-5 describes TOSEQ fields.
Table 21-5. TOSEQ Field Descriptions
Bit
Name
Description
0–1
2
—
Reserved, should be cleared.
REA
Ready. Set when the character is ready for transmission. Remains 1 while the character is being
sent. The CP clears this bit after transmission.
3
4
I
Interrupt. If this bit is set, transmission completion is flagged in the event register (SCCE[TX] is
set), triggering a maskable interrupt to the core.
CT
Clear-to-send lost. Operates only if the SCC monitors CTS (GSMR_L[DIAG]). The CP sets this
bit if CTS negates when the TOSEQ character is sent. If CTS negates and the TOSEQ character
is sent during a buffer transmission, the TxBD[CT] status bit is also set.
5–6
—
Reserved, should be cleared.
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Freescale Semiconductor
21-9
SCC UART Mode
Table 21-5. TOSEQ Field Descriptions (continued)
Bit
Name
A
Description
7
Address. Setting this bit indicates an address character for multidrop mode.
8–15 CHARSEND Character send. Contains the character to be sent. Any 5- to 8-bit character value can be sent
in accordance with the UART configuration. The character should be placed in the lsbs of
CHARSEND. This value can be changed only while REA = 0.
21.12 Sending a Break (Transmitter)
A break is an all-zeros character with no stop bit that is sent by issuing a STOP TRANSMIT command. The
SCC finishes transmitting outstanding data, sends a programmable number of break characters
(determined by BRKCR), and reverts to idle or sends data if a RESTART TRANSMIT command is given
before completion. When the break code is complete, the transmitter sends at least one high bit before
sending more data, to guarantee recognition of a valid start bit. Because break characters do not preempt
characters in the transmit FIFO, they may not be sent for eight (SCC) or four (SCC) character times. To
reduce this latency, set GSMR_H[TFL] to decrease the FIFO size to one character before enabling the
transmitter.
21.13 Sending a Preamble (Transmitter)
Sending a preamble sequence of consecutive ones ensures that a line is idle before sending a message. If
the preamble bit TxBD[P] is set, the SCC sends a preamble sequence (idle character) before sending the
buffer. For example, for 8 data bits, no parity, 1 stop bit, and 1 start bit, a preamble of 10 ones is sent before
the first character in the buffer.
21.14 Fractional Stop Bits (Transmitter)
bits. The FSB field in the data synchronization register (DSR) determines the fractional length of the last
stop bit to be sent. FSB can be modified at any time. If two stop bits are sent, only the second is affected.
Idle characters are always sent as full-length characters
.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Field
Reset
R/W
—
FSB
—
—
—
—
—
—
—
—
—
—
—
0
1111
1
1
0
0
1
1
1
1
1
1
0
R/W
Addr
Figure 21-5. Asynchronous UART Transmitter
Table 21-6 describes DSR fields.
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SCC UART Mode
Table 21-6. DSR Fields Descriptions
Description
Bit
Name
0
—
0b0
1–4
FSB Fractional stop bits. For 16× oversampling:
1111 Last transmitted stop bit 16/16. Default value after reset.
1110 Last transmitted stop bit 15/16.
…
1000 Last transmitted stop bit 9/16.
0xxx Invalid. Do not use.
For 32× oversampling:
1111 Last transmitted stop bit 32/32. Default value after reset.
1110 Last transmitted stop bit 31/32.
…
0000 Last transmitted stop bit 17/32.
For 8× oversampling:
1111 Last transmitted stop bit 8/8. Default value after reset.
1110 Last transmitted stop bit 7/8.
1101 Last transmitted stop bit 6/8.
1100 Last transmitted stop bit 5/8.
10xx Invalid. Do not use.
0xxx Invalid. Do not use.
The UART receiver can always receive fractional stop bits. The next character’s start bit can begin
any time after the three middle samples have been taken.
5–6
7–8
9–14
15
—
—
—
—
0b11
0b00
0b111111
0b0
21.15 Handling Errors in the SCC UART Controller
The UART controller reports character reception and transmission error conditions via the BDs, the error
counters, and the SCCE. Modem interface lines can be monitored by the port C pins. Transmission errors
Table 21-7. Transmission Errors
Error
Description
CTS Lost
during
Character
When CTS negates during transmission, the channel stops after finishing the current character. The
CP sets TxBD[CT] and generates the TX interrupt if it is not masked. The channel resumes
transmission after the RESTART TRANSMIT command is issued and CTS is asserted.
Transmission Note that if CTS is used, the UART also offers an asynchronous flow control option that does not
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
21-11
SCC UART Mode
Table 21-8. Reception Errors
Description
Error
Overrun
Occurs when the channel overwrites the previous character in the Rx FIFO with a new character, losing
the previous character. The channel then writes the new character to the buffer, closes it, sets
RxBD[OV], and generates an RX interrupt if not masked. In automatic multidrop mode, the receiver
enters hunt mode immediately.
CD Lost
during
Character
Reception
If this error occurs and the channel is using this pin to automatically control reception, the channel
terminates character reception, closes the buffer, sets RxBD[CD], and generates the RX interrupt if not
masked. This error has the highest priority. The last character in the buffer is lost and other errors are
not checked. In automatic multidrop mode, the receiver enters the hunt mode immediately.
Parity
Noise
When a parity error occurs, the channel writes the received character to the buffer, closes the buffer,
sets RxBD[PR], and generates the RX interrupt if not masked. The channel also increments the parity
error counter PAREC. In automatic multidrop mode, the receiver enters hunt mode immediately.
A noise error occurs when the three samples of a bit are not identical. When this error occurs, the
channel writes the received character to the buffer, proceeds normally, but increments the noise error
counter NOSEC. Note that this error does not occur in synchronous mode.
Idle
Sequence
Receive
If the UART is receiving data and gets an idle character (all ones), the channel begins counting
consecutive idle characters received. If MAX_IDL is reached, the buffer is closed and an RX interrupt
is generated if not masked. If no buffer is open, this event does not generate an interrupt or any status
information. The internal idle counter (IDLC) is reset every time a character is received. To disable the
idle sequence function, clear MAX_IDL.
Framing
The UART reports a framing errors when it receives a character with no stop bit, regardless of the
mode. The channel writes the received character to the buffer, closes it, sets RxBD[FR], generates the
RX interrupt if not masked, increments FRMEC, but does not check parity for this character. In
automatic multidrop mode, the receiver immediately enters hunt mode. If the UART allows data with
no stop bits (PSMR[RZS] = 1) when in synchronous mode (PSMR[SYN] = 1), framing errors are
reported but reception continues assuming the unexpected zero is the start bit of the next character;
in this case, the user may ignore a reported framing error until multiple framing errors occur within a
short period.
Break
Sequence
When the first break sequence is received, the UART increments the break error counter BRKEC. It
updates BRKLN when the sequence completes. After the first 1 is received, the UART sets
SCCE[BRKE], which generates an interrupt if not masked. If the UART is receiving characters when it
receives a break, it closes the Rx buffer, sets RxBD[BR], and sets SCCE[RX], which can generate an
interrupt if not masked. If PSMR[RZS] = 1 when the UART is in synchronous mode, a break sequence
is detected after two successive break characters are received.
21.16 UART Mode Register (PSMR)
For UART mode, the SCC protocol-specific mode register (PSMR) is called the UART mode register.
Many bits can be modified while the receiver and transmitter are enabled. Figure 21-6 shows the PSMR
in UART mode.
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SCC UART Mode
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Field FLC SL
Reset
CL
UM
FRZ RZS SYN DRT
—
PEN
RPM
TPM
0
R/W
R/W
Addr
Figure 21-6. Protocol-Specific Mode Register for UART (PSMR)
Table 21-9 describes PSMR UART fields.
Table 21-9. PSMR UART Field Descriptions
Bit
Name
Description
0
FLC Flow control.
0 Normal operation. The GSMR and port C registers determine the mode of CTS.
1 Asynchronous flow control. When CTS is negated, the transmitter stops at the end of the current
character. If CTS is negated past the middle of the current character, the next full character is sent
before transmission stops. When CTS is asserted again, transmission continues where it left off
and no CTS lost error is reported. Only idle characters are sent while CTS is negated.
1
SL
CL
Stop length. Selects the number of stop bits the SCC sends. SL can be modified on-the-fly. The
receiver is always enabled for one stop bit unless the SCC UART is in synchronous mode and
PSMR[RZS] is set. Fractional stop bits are configured in the DSR.
0 One stop bit.
1 Two stop bits.
2–3
Character length. Determines the number of data bits in the character, not including optional parity
or multidrop address bits. If a character is less than 8 bits, most-significant bits are received as zeros
and are ignored when the character is sent. CL can be modified on-the-fly.
00 5 data bits
01 6 data bits
10 7 data bits
11 8 data bits
4–5
UM
UART mode. Selects the asynchronous channel protocol. UM can be modified on-the-fly.
00 Normal UART operation. Multidrop mode is disabled and idle-line wake-up mode is selected.
The UART receiver leaves hunt mode by receiving an idle character (all ones).
01 Manual multidrop mode. An additional address/data bit is sent with each character. Multidrop
asynchronous modes are compatible with the MC68681 DUART, MC68HC11 SCI, DSP56000
SCI, and Intel 8051 serial interface. The receiver leaves hunt mode when the address/data bit is
a one, indicating the received character is an address that all inactive processors must process.
The controller receives the address character and writes it to a new buffer. The core then
compares the written address with its own address and decides whether to ignore or process
subsequent characters.
10 Reserved.
11 Automatic multidrop mode. The CPM compares the address of an incoming address character
with UADDRx parameter RAM values; subsequent data is accepted only if a match occurs.
6
FRZ Freeze transmission. Allows the UART transmitter to pause and later continue from that point.
0 Normal operation. If the buffer was previously frozen, it resumes transmission from the next
character in the same buffer that was frozen.
1 The SCC completes transmission of any data already transferred to the Tx FIFO (the number of
characters depends on GSMR_H[TFL]) and then freezes. After FRZ is cleared, transmission
resumes from the next character.
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21-13
SCC UART Mode
Table 21-9. PSMR UART Field Descriptions (continued)
Description
Bit
Name
7
RZS Receive zero stop bits.
0 The receiver operates normally, but at least one stop bit is needed between characters. A framing
error is issued if a stop bit is missing. Break status is set if an all-zero character is received with
a zero stop bit.
1 Configures the receiver to receive data without stop bits. Useful in V.14 applications where SCC
UART controller data is supplied synchronously and all stop bits of a particular character can be
omitted for cross-network rate adaptation. RZS should be set only if SYN is set. The receiver
continues if a stop bit is missing. If the stop bit is a zero, the next bit is considered the first data
bit of the next character. A framing error is issued if a stop bit is missing, but a break status is
reported only after two consecutive break characters have no stop bits.
8
9
SYN Synchronous mode.
0 Normal asynchronous operation. GSMR_L[TENC,RENC] must select NRZ and GSMR_L[TDCR,
RDCR] select either 8×, 16×, or 32×. 16× is recommended for most applications.
1 Synchronous SCC UART controller using 1× clock (isochronous UART operation).
GSMR_L[TENC, RENC] must select NRZ and GSMR_L[RDCR, TDCR] select 1× mode. A bit is
transferred with each clock and is synchronous to the clock, which can be internal or external.
DRT Disable receiver while transmitting.
0 Normal operation.
1 While the SCC is sending data, the internal RTS disables and gates the receiver. Useful for a
multidrop configuration in which the user does not want to receive its own transmission. For
multidrop UART mode, set the BDs’ preamble bit, TxBD[P].
Note: If DRT = 1, GSMR_H[CDS] should be cleared unless both of the following are true: the same
clock is used for TCLK and RCLK, and CTS either has synchronous timing or is always
asserted.
10
11
—
Reserved, should be cleared.
PEN Parity enable.
0 No parity.
1 Parity is enabled and determined by the parity mode bits.
12–13, RPM, Receiver/transmitter parity mode. Selects the type of parity check the receiver/transmitter performs;
14–15
TPM can be modified on-the-fly. Receive parity errors can be ignored but not disabled.
00 Odd parity. If a transmitter counts an even number of ones in the data word, it sets the parity bit
so an odd number is sent. If a receiver receives an even number, a parity error is reported.
01 Low parity (space parity). A transmitter sends a zero in the parity bit position. If a receiver does
not read a 0 in the parity bit, a parity error is reported.
10 Even parity. Like odd parity, the transmitter adjusts the parity bit, as necessary, to ensure that
the receiver receives an even number of one bits; otherwise, a parity error is reported.
11 High parity (mark parity). The transmitter sends a one in the parity bit position. If the receiver
does not read a 1 in the parity bit, a parity error is reported.
21.17 SCC UART Receive Buffer Descriptor (RxBD)
The CPM uses RxBDs to report on each buffer received. The CPM closes the current buffer, generates a
maskable interrupt, and starts receiving data into the next buffer after one of the following occurs:
•
•
•
•
A user-defined control character is received.
An error occurs during message processing.
A full receive buffer is detected.
A MAX_IDL number of consecutive idle characters is received.
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SCC UART Mode
•
•
An ENTER HUNT MODE or CLOSE RXBD command is issued.
An address character is received in multidrop mode. The address character is written to the next
buffer for a software comparison.
Figure 21-7 shows an example of how RxBDs are used in receiving.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
21-15
SCC UART Mode
MRBLR = 8 Bytes for this SCC
Buffer
Rx BD 0
ID
E
0
Status
Length
0
Byte 1
Byte 2
0008
Buffer Full
Pointer
32-Bit Buffer Pointer
8 Bytes
etc.
Byte 8
Rx BD 1
ID
Buffer
Byte 9
Byte 10
E
0
Status
Length
1
0002
8 Bytes
8 Bytes
8 Bytes
Idle Time-Out
Occurred
Pointer
32-Bit Buffer Pointer
Empty
Rx BD 2
Buffer
Byte 1
E
0
ID
0
FR
Status
Length
1
0004
Byte 2
Byte 4 has
Framing Error
Pointer
32-Bit Buffer Pointer
Byte 3
Byte 4 Error!
Empty
Rx BD 3
Buffer
Byte 5
E
1
Status
Length
XXXX
Additional Bytes
will be Stored Unless
Idle Count Expires
(MAX_IDL)
Pointer
32-Bit Buffer Pointer
Reception
Still in Progress
with this Buffer
10 Characters
5 Characters
Long Idle Period
Characters
Received by UART
Fourth Character Present
has Framing Error! Time
Time
Figure 21-7. SCC UART Receiving using RxBDs
Figure 21-8 shows the SCC UART RxBD.
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SCC UART Mode
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Offset + 0
Offset + 2
Offset + 4
Offset + 6
E
—
W
I
C
A
CM
ID
AM
—
BR
FR
PR
—
OV
CD
Data Length
Rx Buffer Pointer
Figure 21-8. SCC UART Receive Buffer Descriptor (RxBD)
Table 21-10 describes RxBD status and control fields.
Table 21-10. SCC UART RxBD Status and Control Field Descriptions
Bits
Name
E
Description
0
Empty.
0 The buffer is full or reception was aborted due to an error. The core can read or write to any fields
of this BD. The CPM does not reuse this BD while E = 0.
1 The buffer is not full. The CPM controls this BD and buffer. The core should not modify this BD.
1
2
—
Reserved, should be cleared.
W
Wrap (last buffer descriptor in the BD table).
0 Not the last descriptor in the table.
1 Last descriptor in the table. After this buffer is used, the CPM receives incoming data using the
BD pointed to by RBASE. The number of BDs in this table is programable and determined only
by the W bit and overall space constraints of the dual-port RAM.
3
I
Interrupt.
0 No interrupt is generated after this buffer is filled.
1 The CP sets SCCE[RX] when this buffer is completely filled by the CPM, indicating the need for
the core to process the buffer. Setting SCCE[RX] causes an interrupt if not masked.
4
5
C
A
Control character.
0 This buffer does not contain a control character.
1 The last byte in this buffer matches a user-defined control character.
Address.
0 The buffer contains only data.
1 For manual multidrop mode, A indicates the first byte of this buffer is an address byte. Software
should perform address comparison. In automatic multidrop mode, A indicates the buffer contains
a message received immediately after an address matched UADDR1 or UADDR2. The address
itself is not written to the buffer but is indicated by the AM bit.
6
CM
Continuous mode.
0 Normal operation. The CPM clears E after this BD is closed.
1 The CPM does not clear E after this BD is closed, allowing the buffer to be overwritten when the
CPM accesses this BD again. E is cleared if an error occurs during reception, regardless of CM.
7
8
ID
Buffer closed on reception of idles. The buffer is closed because a programmable number of
consecutive idle sequences (MAX_IDL) was received.
AM
Address match. Significant only if the address bit is set and automatic multidrop mode is selected
in PSMR[UM]. After an address match, AM identifies which user-defined address character was
matched.
0 The address matched the value in UADDR2.
1 The address matched the value in UADDR1.
9
—
Reserved, should be cleared.
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21-17
SCC UART Mode
Table 21-10. SCC UART RxBD Status and Control Field Descriptions (continued)
Bits
Name
Description
10
11
BR
FR
Break received. Set when a break sequence is received as data is being received into this buffer.
Framing error. Set when a character with a framing error (a character without a stop bit) is received
and located in the last byte of this buffer. A new Rx buffer is used to receive subsequent data.
12
PR
Parity error. Set when a character with a parity error is received and located in the last byte of this
buffer. A new Rx buffer is used to receive subsequent data.
13
14
15
—
Reserved, should be cleared.
OV
CD
Overrun. Set when a receiver overrun occurs during reception.
Carrier detect lost. Set when the carrier detect signal is negated during reception.
21.18 SCC UART Transmit Buffer Descriptor (TxBD)
The CPM uses BDs to confirm transmission and indicate error conditions so the core knows that buffers
0
1
2
3
4
5
6
7
8
9
15
Offset + 0
Offset + 2
Offset + 4
Offset + 6
R
—
W
I
CR
A
CM
P
NS
—
CT
Data Length
Tx Buffer Pointer
Figure 21-9. SCC UART Transmit Buffer Descriptor (TxBD)
Table 21-11 describes TxBD status and control fields.
Table 21-11. SCC UART TxBD Status and Control Field Descriptions
Bit
Name
R
Description
0
Ready.
0 The buffer is not ready. This BD and buffer can be modified. The CPM automatically clears R after
the buffer is sent or an error occurs.
1 The user-prepared buffer is waiting to begin transmission or is being transmitted. Do not modify
the BD once R is set.
1
2
—
Reserved, should be cleared.
W
Wrap (last buffer descriptor in TxBD table).
0 Not the last BD in the table.
1 Last BD in the table. After this buffer is used, the CPM sends data using the BD pointed to by
TBASE. The number of TxBDs in this table is determined only by the W bit and space constraints
of the dual-port RAM.
3
I
Interrupt.
0 No interrupt is generated after this buffer is processed.
1 SCCE[TX] is set after this buffer is processed by the CPM, which can cause an interrupt.
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SCC UART Mode
Table 21-11. SCC UART TxBD Status and Control Field Descriptions (continued)
Bit
Name
CR
Description
4
Clear-to-send report.
0 The next buffer is sent with no delay (assuming it is ready), but if a CTS lost condition occurs,
TxBD[CT] may not be set in the correct TxBD or may not be set at all. Asynchronous flow control,
however, continues to function normally.
1 Normal CTS lost error reporting and three bits of idle are sent between consecutive buffers.
5
6
A
Address. Valid only in multidrop mode—automatic or manual.
0 This buffer contains only data.
1 This buffer contains address characters. All data in this buffer is sent as address characters.
CM
Continuous mode.
0 Normal operation. The CPM clears R after this BD is closed.
1 The CPM does not clear R after this BD is closed, allowing the buffer to be resent next time the
CPM accesses this BD. However, R is cleared by transmission errors, regardless of CM.
7
8
P
Preamble.
0 No preamble sequence is sent.
1 Before sending data, the controller sends an idle character consisting of all ones. If the data
length of this BD is zero, only a preamble is sent.
NS
No stop bit or shaved stop bit sent.
0 Normal operation. Stop bits are sent with all characters in this buffer.
1 If PSMR[SYN] = 1, data in this buffer is sent without stop bits. If SYN = 0, the stop bit is shaved,
9–14
15
—
Reserved, should be cleared.
CT
CTS lost. The CPM writes this status bit after sending the associated buffer.
0 CTS remained asserted during transmission.
1 CTS negated during transmission.
The data length and buffer pointer fields are described in Section 20.2, “SCC Buffer Descriptors (BDs).”
21.19 SCC UART Event Register (SCCE) and Mask Register (SCCM)
The SCC event register (SCCE) is used to report events recognized by the UART channel and to generate
interrupts. When an event is recognized, the controller sets the corresponding SCCE bit. Interrupts can be
masked in the UART mask register (SCCM), which has the same format as SCCE. Setting a mask bit
enables the corresponding SCCE interrupt; clearing a bit masks it. Figure 21-10 shows example interrupts
that can be generated by the SCC UART controller.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
21-19
SCC UART Mode
Characters
Received by UART
10 Characters
Time
Line Idle
RXD
CD
Line Idle
Break
UART SCCE
Events
CD
IDL
RX
CCR
IDL
RX IDL BRKS BRKE IDL CD
Notes:
1. The first RX event assumes Rx buffers are 6 bytes each.
2. The second IDL event occurs after an all-ones character is received.
3. The second RX event position is programmable based on the MAX_IDL value.
4. The BRKS event occurs after the first break character is received.
5. The CD event must be programmed in the port C parallel I/O, not in the SCC itself.
Legend:
A receive control character defined not to be stored in the Rx buffer.
Characters
Transmitted by UART
7 Characters
TXD
Line Idle
Line Idle
RTS
CTS
UART SCCE
Events
CTS
TX
CTS
Notes:
1. TX event assumes all seven characters were put into a single buffer and TxBD[CR]=1.
2. The CTS event must be programmed in the port C parallel I/O, not in the SCC itself.
Figure 21-10. SCC UART Interrupt Event Example
SCCE bits are cleared by writing ones; writing zeros has no effect. Unmasked bits must be cleared before
0
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Field
Reset
R/W
—
AB
IDL GRA BRKE BRKS
—
CCR BSY TX
RX
0000_0000_0000_0000
R/W
Addr
Figure 21-11. SCC UART Event Register (SCCE) and Mask Register (SCCM)
Table 21-12 describes SCCE fields for UART mode.
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SCC UART Mode
1
Table 21-12. SCCE/SCCM Field Descriptions for UART Mode
Bit
Name
Description
0–5
6
—
Reserved, should be cleared. Refer to note 1 below.
AB
Autobaud. Set when an autobaud lock is detected. The core should rewrite the baud rate generator
7
8
IDL
Idle sequence status changed. Set when the channel detects a change in the serial line. The line’s
real-time status can be read in SCCS[ID]. Idle is entered when a character of all ones is received; it
is exited when a zero is received.
GRA Graceful stop complete. Set as soon as the transmitter finishes any buffer in progress after a
GRACEFUL STOP TRANSMIT command is issued. It is set immediately if no buffer is in progress.
9
BRKE Break end. Set when an idle bit is received after a break sequence.
10
BRKS Break start. Set when the first character of a break sequence is received. Multiple BRKS events are
not received if a long break sequence is received.
11
12
—
Reserved, should be cleared. Refer to note 1 below.
CCR Control character received and rejected. Set when a control character is recognized and stored in
the receive control character register RCCR.
13
BSY Busy. Set when a character is received and discarded due to a lack of buffers. In multidrop mode,
the receiver automatically enters hunt mode; otherwise, reception continues when a buffer is
available. The latest point that an RxBD can be changed to empty and guarantee avoiding the busy
condition is the middle of the stop bit of the first character to be stored in that buffer.
14
15
TX
Tx event. Set when a buffer is sent. If TxBD[CR] = 1, TX is set no sooner than when the last stop bit
of the last character in the buffer begins transmission. If TxBD[CR] = 0, TX is set after the last
character is written to the Tx FIFO. TX also represents a CTS lost error; check TxBD[CT].
RX
Rx event. Set when a buffer is received, which is no sooner than the middle of the first stop bit of the
character that caused the buffer to close. Also represents a general receiver error (overrun, CD lost,
parity, idle sequence, and framing errors); the RxBD status and control fields indicate the specific
error.
1
Reserved bits in the SCCE should not be masked in the SCCM register.
21.20 SCC UART Status Register (SCCS)
0
6
7
Field
Reset
R/W
—
ID
0000_0000_0000_0000
R
Addr
Figure 21-12. SCC Status Register for UART Mode (SCCS)
Table 21-13 describes UART SCCS fields.
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SCC UART Mode
Table 21-13. UART SCCS Field Descriptions
Description
Bits
Name
0–6
7
—
ID
Reserved, should be cleared.
Idle status. Set when RXD has been a logic one for at least a full character time.
0 The line is not idle.
1 The line is idle.
21.21 SCC UART Programming Example
The following initialization sequence is for the 9,600 baud, 8 data bits, no parity, and stop bit of an SCC
in UART mode assuming a 66-MHz system frequency. BRG1 and SCC2 are used. The controller is
configured with RTS2, CTS2, and CD2 active; CTS2 acts as an automatic flow-control signal.
1. Configure port D pins to enable TXD2 and RXD2. Set PPARD[27,28] and PDIRD[27] and clear
PDIRD[28] and PSORD[27,28].
2. Configure ports C and D pins to enable RTS2, CTS2 and CD2. Set PPARD[26], PPARC[12,13]
and PDIRD[26] and clear PDIRC[12,13], PSORC[12,13] and PSORD[26].
3. Configure BRG1. Write BRGC1 with 0x0001_035A. The DIV16 bit is not used and the divider is
429 (decimal). The resulting BRG1 clock is 16× the preferred bit rate.
4. Connect BRG1 to SCC2 using the CPM mux. Clear CMXSCR[RS2CS,TS2CS].
5. Connect the SCC2 to the NMSI. Clear CMXSCR[SC2].
6. Write RBASE and TBASE in the SCC2 parameter RAM to point to the RxBD and TxBD tables in
dual-port RAM. Assuming one RxBD at the start of dual-port RAM followed by one TxBD, write
RBASE with 0x0000 and TBASE with 0x0008.
7. Write 0x04A1_0000 to CPCR to execute the INIT RX AND TX PARAMS command for SCC2. This
command updates RBPTR and TBPTR of the serial channel with the new values of RBASE and
TBASE.
8. Write RFCR with 0x10 and TFCR with 0x10 for normal operation.
9. Write MRBLR with the maximum number of bytes per Rx buffer. For this case, assume 16 bytes,
so MRBLR = 0x0010.
10. Write MAX_IDL with 0x0000 in the parameter RAM to disable the maximum idle functionality
for this example.
11. Set BRKCR to 0x0001 so STOP TRANSMIT commands send only one break character.
12. Clear PAREC, FRMEC, NOSEC, and BRKEC in parameter RAM.
13. Clear UADDR1 and UADDR2. They are not used.
14. Clear TOSEQ. It is not used.
15. Write CHARACTER1–8 with 0x8000. They are not used.
16. Write RCCM with 0xC0FF. It is not used.
17. Initialize the RxBD. Assume the Rx buffer is at 0x0000_1000 in main memory. Write 0xB000 to
the RxBD[Status and Control], 0x0000 to RxBD[Data Length] (optional), and 0x0000_1000 to
RxBD[Buffer Pointer].
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SCC UART Mode
18. Initialize the TxBD. Assume the buffer is at 0x0000_2000 in main memory and contains sixteen
8-bit characters. Write 0xB000 to the TxBD[Status and Control], 0x0010 to TxBD[Data Length],
and 0x00002000 to TxBD[Buffer Pointer].
19. Write 0xFFFF to SCCE2 to clear any previous events.
20. Write 0x0003 to SCCM2 to allow the TX and RX interrupts.
21. Write 0x0040_0000 to the SIMR_L so SCC2 can generate a system interrupt. Initialize SIPNR_L
by writing 0xFFFF_FFFF to it.
22. Write 0x0000_0020 to GSMR_H2 to configure a small Rx FIFO width.
23. Write 0x0002_8004 to GSMR_L2 to configure 16× sampling for transmit and receive, CTS and
CD to automatically control transmission and reception (DIAG bits), and the SCC for UART mode.
Notice that the transmitter (ENT) and receiver (ENR) have not been enabled yet.
24. Set PSMR2 to 0xB000 to configure automatic flow control using CTS, 8-bit characters, no parity,
1 stop bit, and asynchronous SCC UART operation.
25. Write 0x0002_8034 to GSMR_L2 to enable the transmitter and receiver. This ensures that ENT
and ENR are enabled last.
NOTE
After 16 bytes are sent, the transmit buffer is closed. Additionally, the
receive buffer is closed after 16 bytes are received. Data received after 16
bytes causes a busy (out-of-buffers) condition because only one RxBD is
prepared.
21.22 S-Records Loader Application
This section describes a downloading application that uses an SCC UART controller. The application
performs S-record downloads and uploads between a host computer and an intelligent peripheral through
a serial asynchronous line. S-records are strings of ASCII characters that begin with ‘S’ and end in an
end-of-line character. This characteristic is used to impose a message structure on the communication
between the devices. For flow control, each device can transmit XON and XOFF characters, which are not
part of the program being uploaded or downloaded.
For simplicity, assume that the line is not multidrop (no addresses are sent) and that each S-record fits into
a single buffer. Follow the basic UART initialization sequence above in Section 21.21, “SCC UART
Programming Example,” except allow for more and larger buffers and create the control character table as
Table 21-14. UART Control Characters for S-Records Example
Character
Description
Line Feed Both the E and R bits should be cleared. When an end-of-line character is received, the current buffer is
closed and made available to the core for processing. This buffer contains an entire S record that the
processor can now check and copy to memory or disk as required.
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SCC UART Mode
Table 21-14. UART Control Characters for S-Records Example (continued)
Description
Character
XOFF
E should be cleared; R should be set. Whenever the core receives a control-character-received (CCR)
interrupt and the RCCR contains XOFF, the software should immediately stop transmitting by setting
PSMR[FRZ]. This keeps the other station from losing data when it runs out of Rx buffers.
XON
XON should be received after XOFF. E should be cleared and R should be set. PSMR[FRZ] on the
transmitter should now be cleared. The CPM automatically resumes transmission of the serial line at the
point at which it was previously stopped. Like XOFF, the XON character is not stored in the receive buffer.
To receive S-records, the core must wait for an RX interrupt, indicating that a complete S-record buffer
was received. Transmission requires assembling S-records into buffers and linking them to the TxBD
table; transmission can be paused when an XOFF character is received. This scheme minimizes the
number of interrupts the core receives (one per S-record) and relieves it from continually scanning for
control characters.
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Chapter 22
SCC HDLC Mode
High-level data link control (HDLC) is one of the most common protocols in the data link layer, layer 2
of the OSI model. Many other common layer 2 protocols, such as SDLC, SS#7, AppleTalk, LAPB, and
structure.
HDLC uses a zero insertion/deletion process (bit-stuffing) to ensure that a data bit pattern matching the
delimiter flag does not occur in a field between flags. The HDLC frame is synchronous and relies on the
physical layer for clocking and synchronization of the transmitter/receiver.
An address field is needed to carry the frame's destination address because the layer 2 frame can be sent
over point-to-point links, broadcast networks, packet-switched or circuit-switched systems. An address
field is commonly 0, 8, or 16 bits, depending on the data link layer protocol. SDLC and LAPB use an 8-bit
address. SS#7 has no address field because it is always used in point-to-point signaling links. LAPD
divides its 16-bit address into different fields to specify various access points within one device. LAPD
also defines a broadcast address. Some HDLC-type protocols permit addressing beyond 16 bits.
The 8- or 16-bit control field provides a flow control number and defines the frame type (control or data).
The exact use and structure of this field depends on the protocol using the frame. The length of the data in
the data field depends on the frame protocol. Layer 3 frames are carried in this data field. Error control is
implemented by appending a cyclic redundancy check (CRC) to the frame, which in most protocols is 16
bits long but can be as long as 32 bits. In HDLC, the lsb of each octet is sent first; the msb of the CRC is
sent first.
HDLC mode is selected for an SCC by writing GSMR_L[MODE] = 0b0000. In a nonmultiplexed modem
interface, SCC outputs connect directly to external pins. Modem signals can be supported through port C.
The Rx and Tx clocks can be supplied from either the bank of baud rate generators, by the DPLL, or
externally. An SCC can also be connected through the TDM channels of the serial interface (SI). In HDLC
mode, an SCC becomes an HDLC controller, and consists of separate transmit and receive sections whose
operations are asynchronous with the core and can either be synchronous or asynchronous with respect to
other SCCs.
22.1 SCC HDLC Features
The main features of an SCC in HDLC mode are follows:
•
•
•
•
Flexible buffers with multiple buffers per frame
Separate interrupts for frames and buffers (Rx and Tx)
Received-frames threshold to reduce interrupt overhead
Can be used with the SCC DPLL
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SCC HDLC Mode
•
•
•
•
•
•
•
•
•
Four address comparison registers with mask
Maintenance of five 16-bit error counters
Flag/abort/idle generation and detection
Zero insertion/deletion
16- or 32-bit CRC-CCITT generation and checking
Detection of nonoctet aligned frames
Detection of frames that are too long
Programmable flags (0–15) between successive frames
Automatic retransmission in case of collision
22.2 SCC HDLC Channel Frame Transmission
The HDLC transmitter is designed to work with little or no core intervention. Once enabled by the core, a
transmitter starts sending flags or idles as programmed in the HDLC mode register (PSMR). The HDLC
polls the first BD in the TxBD table. When there is a frame to transmit, the SCC fetches the data (address,
control, and information) from the first buffer and starts sending the frame after inserting the minimum
number of flags specified between frames. When the end of the current buffer is reached and TxBD[L]
(last buffer in frame) is set, the SCC appends the CRC and closing flag. In HDLC mode, the lsb of each
Opening Flag
8 bits
Address
16 bits
Control
8 bits
Information (Optional)
8n bits
CRC
Closing Flag
8 bits
16 bits
Figure 22-1. HDLC Framing Structure
After a closing flag is sent, the SCC updates the frame status bits of the BD and clears TxBD[R] (buffer
ready). At the end of the current buffer, if TxBD[L] is not set (multiple buffers per frame), only TxBD[R]
is cleared. Before the SCC proceeds to the next TxBD in the table, an interrupt can be issued if TxBD[I]
is set. This interrupt programmability allows the core to intervene after each buffer, after a specific buffer,
or after each frame.
The STOP TRANSMIT command can be used to expedite critical data ahead of previously linked buffers or
to support efficient error handling. When the SCC receives a STOP TRANSMIT command, it sends idles or
flags instead of the current frame until it receives a RESTART TRANSMIT command. The GRACEFUL STOP
TRANSMIT command can be used to insert a high-priority frame without aborting the current one—a
graceful-stop-complete event is generated in SCCE[GRA] when the current frame is finished. See
22.3 SCC HDLC Channel Frame Reception
The HDLC receiver is designed to work with little or no core intervention to perform address recognition,
CRC checking, and maximum frame length checking. Received frames can be used to implement any
HDLC-based protocol.
Once enabled by the core, the receiver waits for an opening flag character. When it detects the first byte
of the frame, the SCC compares the frame address with four user-programmable, 16-bit address registers
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SCC HDLC Mode
and an address mask. The SCC compares the received address field with the user-defined values after
masking with the address mask. To detect broadcast (all ones) address frames, one address register must
be written with all ones.
If an address match is detected, the SCC fetches the next BD and SCC starts transferring the incoming
frame to the buffer if it is empty. When the buffer is full, the SCC clears RxBD[E] and generates a
maskable interrupt if RxBD[I] is set. If the incoming frame is larger than the current buffer, the SCC
continues receiving using the next BD in the table.
During reception, the SCC checks for frames that are too long (using MFLR). When the frame ends, the
CRC field is checked against the recalculated value and written to the buffer. RxBD[Data Length] of the
last BD in the HDLC frame contains the entire frame length. This also enables software to identify the
frames in which the maximum frame length violations occur. The SCC sets RxBD[L] (last buffer in
frame), writes the frame status bits, and clears RxBD[E]. It then generates a maskable event (SCCE[RXF])
to indicate a frame was received. The SCC then waits for a new frame. Back-to-back frames can be
received with only one shared flag between frames.
The received frames threshold parameter (RFTHR) can be used to postpone interrupts until a specified
number of frames is received. This function can be combined with a timer to implement a timeout if fewer
than the specified number of threshold frames is received.
Note that SCCs in HDLC mode, or any other synchronous mode, must receive a minimum of eight clocks
after the last bit arrives to account for Rx FIFO delay.
22.4 SCC HDLC Parameter RAM
Table 22-1. HDLC-Specific SCC Parameter RAM Memory Map
1
Offset
Name
Width
Description
0x30
0x34
—
Word Reserved
C_MASK
Word CRC mask. For the 16-bit CRC-CCITT, initialize with 0x0000_F0B8. For 32-bit
CRC-CCITT, initialize with 0xDEBB_20E3.
0x38
C_PRES
Word CRC preset. For the 16-bit CRC-CCITT, initialize with 0x0000_FFFF. For 32-bit
CRC-CCITT, initialize with 0xFFFF_FFFF.
16
0x3C
0x3E
0x40
0x42
0x44
DISFC
CRCEC
ABTSC
NMARC
RETRC
Hword Modulo 2 counters maintained by the CP. Initialize them while the channel is
disabled.
Hword
DISFC (Discarded frame counter) Counts error-free frames discarded due to lack
of free buffers.
CRCEC (CRC error counter) Includes frames not addressed to the user or frames
received in the BSY condition, but does not include overrun errors.
ABTSC (Abort sequence counter)
NMARC (Nonmatching address received counter) Includes error-free frames only.
RETRC (Frame retransmission counter) Counts number of frames resent due to
collision.
Hword
Hword
Hword
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SCC HDLC Mode
Table 22-1. HDLC-Specific SCC Parameter RAM Memory Map (continued)
Width Description
1
Offset
Name
MFLR
0x46
Hword Max frame length register. The HDLC compares the incoming HDLC frame’s length
with the user-defined limit in MFLR. If the limit is exceeded, the rest of the frame is
discarded and RxBD[LG] is set in the last BD of that frame. At the end of the frame
the SCC reports frame status and frame length in the last RxBD. The MFLR is
defined as all in-frame bytes between the opening and closing flags.
0x48
0x4A
MAX_CNT Hword Maximum length counter. A temporary down-counter used to track frame length.
RFTHR
Hword Received frames threshold. Used to reduce potential interrupt overhead when each
in a series of short HDLC frames causes an SCCE[RXF] event. Setting RFTHR
determines the frequency of RXF interrupts, which occur only when the RFTHR
limit is reached. Provide enough empty RxBDs for the number of frames specified
in RFTHR.
0x4C
0x4E
0x50
0x52
0x54
0x56
RFCNT
HMASK
HADDR1
HADDR2
HADDR3
HADDR4
Hword Received frames count. RFCNT is a down-counter used to implement RFTHR.
Hword Mask register (HMASK) and four address registers (HADDRn) for address
recognition. The SCC reads the frame address from the HDLC receiver, compares
Hword
it with the HADDRs, and masks the result with HMASK. Setting an HMASK bit
enables the corresponding comparison bit, clearing a bit masks it. When a match
occurs, the frame address and data are written to the buffers. When no match
Hword
Hword
Hword
occurs and a frame is error-free, the nonmatching address received counter
(NMARC) is incremented.
The eight low-order bits of HADDRn should contain the first address byte after the
opening flag. For example, to recognize a frame that begins 0x7E (flag), 0x68,
0xAA, using 16-bit address recognition, HADDRn should contain 0xAA68 and
HMASK should contain 0xFFFF. For 8-bit addresses, clear the eight high-order
0x58
TMP
Hword Temporary storage.
Hword Temporary storage.
0x5A
TMP_MB
1
Figure 22-2 shows 16- and 8-bit address recognition.
16-Bit Address Recognition
8-Bit Address Recognition
Flag Address Control
Flag
0x7E
Address
0x68
Address
0xAA
Control
0x44
etc.
etc.
0x7E
0x55
0x44
HMASK
0xFFFF
HMASK
0x00FF
0xXX55
0xXX55
0xXX55
0xXX55
HADDR1
HADDR2
HADDR3
HADDR4
0xAA68
0xFFFF
0xAA68
0xAA68
HADDR1
HADDR2
HADDR3
HADDR4
Recognizes one 16-bit address (HADDR1) and
the 16-bit broadcast address (HADDR2)
Recognizes a single 8-bit address (HADDR
Figure 22-2. HDLC Address Recognition
22.5 Programming the SCC in HDLC Mode
HDLC mode is selected for an SCC by writing GSMR_L[MODE] = 0b0000. The HDLC controller
uses the same buffer and BD data structure as other modes and supports multibuffer operation and
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SCC HDLC Mode
address comparisons. Receive errors are reported through the RxBD; transmit errors are reported through
the TxBD.
22.6 SCC HDLC Commands
The transmit and receive commands are issued to the CP command register (CPCR). Transmit commands
Table 22-2. Transmit Commands
Command
Description
STOP
After a hardware or software reset and a channel is enabled in the GSMR, the transmitter starts polling
the first BD in the TxBD table every 64 Tx clocks, or immediately if TODR[TOD] = 1, and begins sending
data if TxBD[R] is set. If the SCC receives the STOP TRANSMIT command while not transmitting, the
transmitter stops polling the BDs. If the SCC receives the command during transmission, transmission
is aborted after a maximum of 64 additional bits, the Tx FIFO is flushed, and the current BD pointer
TBPTR is not advanced (no new BD is accessed). The transmitter then sends an abort sequence (0x7F)
and stops polling the BDs.
TRANSMIT
When not transmitting, the channel sends flags or idles as programmed in the GSMR.
Note that if PSMR[MFF] = 1, multiple small frames could be flushed from the Tx FIFO; a GRACEFUL STOP
TRANSMIT command prevents this.
GRACEFUL
STOP
Stops transmission smoothly. Unlike a STOP TRANSMIT command, it stops transmission after the current
frame is finished or immediately if no frame is being sent. SCCE[GRA] is set when transmission stops.
HDLC Tx parameters and Tx BDs can then be updated. TBPTR points to the next TxBD. Transmission
begins once TxBD[R] of the next BD is set and a RESTART TRANSMIT command is issued.
TRANSMIT
RESTART
TRANSMIT
Enables frames to be sent on the transmit channel. The HDLC controller expects this command after a
STOP TRANSMIT is issued and the channel in its GSMR is disabled, after a GRACEFUL STOP TRANSMIT
command, or after a transmitter error. The transmitter resumes from the current BD.
INIT TX
Resets the Tx parameters in the parameter RAM. Issue only when the transmitter is disabled. INIT TX
PARAMETERS AND RX PARAMETERS resets both Tx and Rx parameters.
Table 22-3. Receive Commands
Command
Description
ENTER HUNT After a hardware or software reset, once an SCC is enabled in the GSMR, the receiver is automatically
MODE
enabled and uses the first BD in the RxBD table. While the SCC is looking for the beginning of a frame,
that SCC is in hunt mode. The ENTER HUNT MODE command is used to force the HDLC receiver to stop
receiving the current frame and enter hunt mode, in which the HDLC continually scans the input data
stream for a flag sequence. After receiving the command, the buffer is closed and the CRC is reset.
Further frame reception uses the next BD.
CLOSE RXBD Should not be used in the HDLC protocol.
INIT RX
Resets the Rx parameters in the parameter RAM.; issue only when the receiver is disabled. Note that
PARAMETERS INIT TX AND RX PARAMETERS resets both Tx and Rx parameters.
22.7 Handling Errors in the SCC HDLC Controller
The SCC HDLC controller reports frame reception and transmission errors using BDs, error counters, and
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SCC HDLC Mode
Error
Table 22-4. Transmit Errors
Description
Transmitter
Underrun
The channel stops transmitting, closes the buffer, sets TxBD[UN], and generates a TXE interrupt if not
masked. Transmission resumes when a RESTART TRANSMIT command is issued. The SCC send and
receive FIFOs are 32 bytes each.
CTS Lost
The channel stops transmitting, closes the buffer, sets TxBD[CT], and generates the TXE interrupt if
duringFrame not masked. Transmission resumes after a RESTART TRANSMIT command. If this error occurs on the
Transmission first or second buffer of the frame and PSMR[RTE] = 1, the channel resends the frame when CTS is
reasserted and no error is reported. If collisions are possible, to ensure proper retransmission of
multi-buffer frames, the first two buffers of each frame should in total contain more than 36 bytes for
SCC or 20 bytes for SCC. The channel also increments the retransmission counter RETRC in the
parameter RAM.
Table 22-5. Receive Errors
Error
Description
Overrun
Each SCC maintains an internal FIFO for receiving data. The CP begins programming the SDMA
channel (if the buffer is in external memory) and updating the CRC when a full or partial FIFO’s worth
of data (according to GSMR_H[RFW]) is received in the Rx FIFO. When an Rx FIFO overrun occurs,
the previous byte is overwritten by the next byte. The previous data byte and the frame status are lost.
The channel closes the buffer with RxBD[OV] set and generates an RXF interrupt if not masked. The
receiver then enters hunt mode. Even if an overrun occurs during a frame whose address is not
recognized, an RxBD with data length two is opened to report the overrun and the interrupt is
generated.
CD Lost
during
Frame
Highest priority error. The channel stops frame reception, closes the buffer, sets RxBD[CD], and
generates the RXF interrupt if not masked. The rest of the frame is lost and other errors are not checked
in that frame. At this point, the receiver enters hunt mode.
Reception
Abort
Sequence
Occurs when seven or more consecutive ones are received. When this occurs while receiving a frame,
the channel closes the buffer, sets RxBD[AB] and generates a maskable RXF interrupt. The channel
also increments the abort sequence counter ABTSC. The CRC and nonoctet error status conditions are
not checked on aborted frames. The receiver then enters hunt mode.
Nonoctet
Aligned
Frame
The channel writes the received data to the buffer, closes the buffer, sets RxBD[NO], and generates a
maskable RXF interrupt. CRC error status should be disregarded on nonoctet frames. After a nonoctet
aligned frame is received, the receiver enters hunt mode. An immediate back-to-back frame is still
received. The nonoctet data may be derived from the last word in the buffer as follows:
msb
lsb
1
0
0
Valid Data
Nonvalid Data
Note: If buffer swapping is used (RFCR[BO] = 0b0x), the figure above refers to the last byte, rather than
the last word, of the buffer. The lsb of each octet is sent first while the msb of the CRC is sent first.
CRC
The channel writes the received CRC to the buffer, closes the buffer, sets RxBD[CR], generates a
maskable RXF interrupt, and increments the CRC error counter CRCEC. After receiving a frame with a
CRC error, the receiver enters hunt mode. An immediate back-to-back frame is still received. CRC
checking cannot be disabled, but the CRC error can be ignored if checking is not required.
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SCC HDLC Mode
22.8 HDLC Mode Register (PSMR)
The protocol-specific mode register (PSMR), shown in Figure 22-3, functions as the HDLC mode register.
0
3
4
5
6
7
8
9
10
11
12
13
15
Field
Reset
R/W
NOF
CRC
RTE
—
FSE DRT BUS BRM MFF
—
0
R/W
Addr
Figure 22-3. HDLC Mode Register (PSMR)
Table 22-6 describes PSMR HDLC fields.
Table 22-6. PSMR HDLC Field Descriptions
Bits
Name
Description
0-3
NOF Number of flags. Minimum number of flags between or before frames. If NOF = 0b0000, no flags are
inserted between frames and the closing flag of one frame is followed by the opening flag of the next
frame in the case of back-to-back frames. NOF can be modified on-the-fly.
4–5
CRC CRC selection.
00 16-bit CCITT-CRC (HDLC). X16 + X12 + X5 + 1.
x1 Reserved.
10 32-bit CCITT-CRC (Ethernet and HDLC). X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 +
X8 + X7 + X5 + X4 + X2 + X1 +1.
6
RTE Retransmit enable.
0 No retransmission.
1 Automatic frame retransmission is enabled. Particularly useful in the HDLC bus protocol and
ISDN applications where multiple HDLC controllers can collide. Note that retransmission occurs
only if a lost CTS occurs on the first or second buffer of the frame.
7
8
—
Reserved, should be cleared.
FSE Flag sharing enable. FSE can be set only if GSMR_H[RTSM] is already set. Can be modified
on-the-fly.
0 Normal operation.
1 If NOF[0–3] = 0b0000, a single shared flag is sent between back-to-back frames. Other values of
NOF[0–3] are decremented by 1. Useful in signaling system #7 applications.
9
DRT Disable receiver while transmitting.
0 Normal operation.
1 As the SCC sends data, the receiver is disabled and gated by the internal RTS. This helps if the
HDLC channel is on a multidrop line and the SCC does not need to receive its own transmission.
Note: If DRT = 1, GSMR_H[CDS] should be cleared unless both of the following are true: the same
clock is used for TCLK and RCLK, and CTS either has synchronous timing or is always
asserted.
10
BUS HDLC bus mode.
0 Normal HDLC operation.
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Freescale Semiconductor
22-7
SCC HDLC Mode
Table 22-6. PSMR HDLC Field Descriptions (continued)
Description
Bits
Name
11
BRM HDLC bus RTS mode. Valid only if BUS = 1. Otherwise, it is ignored.
0 Normal RTS operation during HDLC bus mode. RTS is asserted on the first bit of the Tx frame
and negated after the first collision bit is received.
1 Special RTS operation during HDLC bus mode. RTS is delayed by one bit with respect to the
normal case, which helps when the HDLC bus protocol is being run locally and sent over a
long-distance line at the same time. The one-bit delay allows RTS to be used to enable the
transmission line buffers so that the electrical effects of collisions are not sent over the
transmission line.
12
MFF Multiple frames in Tx FIFO. The receiver is not affected.
0 Normal operation. The Tx FIFO must never contain more than one HDLC frame. The CTS lost
status is reported accurately on a per-frame basis.
1 The Tx FIFO can hold multiple frames, but lost CTS may not be reported on the buffer/frame it
occurred on. This can improve performance of HDLC transmissions of small back-to-back frames
or when the number of flags between frames should be limited.
13–15
—
Reserved, should be cleared.
22.9 SCC HDLC Receive Buffer Descriptor (RxBD)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Offset + 0
Offset + 2
Offset + 4
Offset + 6
E
—
W
I
L
F
CM
—
DE
—
LG
NO
AB
CR
OV
CD
Data Length
Rx Buffer Pointer
Figure 22-4. SCC HDLC Receive Buffer Descriptor (RxBD)
Table 22-7 describes HDLC RxBD status and control fields.
Table 22-7. SCC HDLC RxBD Status and Control Field Descriptions
Bits
Name
E
Description
0
Empty.
0 The buffer is full or reception stopped because of an error. The core can read or write to any fields
of this RxBD. The CP does not use this BD while E = 0.
1 The buffer is not full. The CP controls the BD and buffer. The core should not update the BD.
1
2
—
Reserved, should be cleared.
W
Wrap (last BD in the RxBD table).
0 Not the last BD in the table.
1 Last BD in the table. After this buffer is used, the CP receives incoming data using the BD pointed
to by RBASE. The number of BDs in this table are programmable and determined only by
RxBD[W] and overall space constraints of the dual-port RAM.
3
I
Interrupt.
0 SCCE[RXB] is not set after this buffer is used; SCCE[RXF] is unaffected.
1 SCCE[RXB] or SCCE[RXF] is set when the SCC uses this buffer.
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SCC HDLC Mode
Table 22-7. SCC HDLC RxBD Status and Control Field Descriptions (continued)
Bits
Name
Description
4
L
Last buffer in frame.
0 Not the last buffer in frame.
1 Last buffer in frame. Indicates reception of a closing flag or an error, in which case one or more
of the CD, OV, AB, and LG bits are set. The SCC writes the number of frame octets to the data
length field.
5
6
F
First in frame.
0 Not the first buffer in a frame.
1 First buffer in a frame.
CM
Continuous mode. Note that RxBD[E] is cleared if an error occurs during reception, regardless of
CM.
0 Normal operation.
1 RxBD[E] is not cleared by the CP after this BD is closed, allowing the associated buffer to be
overwritten next time the CP accesses it.
7
8
—
Reserved, should be cleared.
DE
DPLL error. Set when a DPLL error occurs while this buffer is being received. DE is also set due to
a missing transition when using decoding modes in which a transition is required for every bit. Note
that when a DPLL error occurs, the frame closes and error checking halts.
9
—
Reserved, should be cleared.
10
LG
Rx frame length violation. Set when a frame larger than the maximum defined for this channel is
recognized. Only the maximum-allowed number of bytes (MFLR) is written to the buffer. This event
is not reported until the buffer is closed, SCCE[RXF] is set, and the closing flag is received. The total
number of bytes received between flags is still written to the data length field.
11
NO
Rx nonoctet aligned frame. Set when a received frame contains a number of bits not divisible by
eight.
12
13
AB
CR
Rx abort sequence. Set when at least seven consecutive ones are received during frame reception.
Rx CRC error. Set when a frame contains a CRC error. CRC bytes received are always written to
the Rx buffer.
14
15
OV
CD
Overrun. Set when a receiver overrun occurs during frame reception.
Carrier detect lost (NMSI mode only). Set when CD is negated during frame reception.
Data length and buffer pointer fields are described in Section 20.2, “SCC Buffer Descriptors (BDs).”
Because HDLC is a frame-based protocol, RxBD[Data Length] of the last buffer of a frame contains the
total number of frame bytes, including the 2 or 4 bytes for CRC. Figure 22-5 shows an example of how
RxBDs are used in receiving.
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22-9
SCC HDLC Mode
MRBLR = 8 Bytes for this SCC
Buffer
Receive BD 0
E
0
L
F
Status
0
1
Address 1
Address 2
Length
Pointer
0x0008
Buffer Full
32-Bit Buffer Pointer
8 Bytes
Control Byte
5
Information
(I-Field) Bytes
Receive BD 1
Buffer
E
0
L
F
Status
Length
1
0
Last I-Field Byte
CRC Byte 1
CRC Byte 2
0x000B
Buffer Closed
When Closing Flag
Received
Pointer
32-Bit Buffer Pointer
8 Bytes
Empty
Receive BD 2
Buffer
E
0
L
1
F
1
AB
1
Status
Length
Address 1
Address 2
Control Byte
0x0003
8 Bytes
Abort Was
Received After
Control Byte
Pointer
32-Bit Buffer Pointer
Receive BD 3
Empty
Buffer
E
1
Status
Length
XXXX
8 Bytes
Empty
Buffer
Still Empty
Pointer
32-Bit Buffer Pointer
Stored in Rx Buffer
Stored in Rx Buffer
F
A
A
C
I
I
I
I
I
I
CR CR F
Line Idle
F
A
A
C
Abort/Idle
Two Frames
Received in HDLC
Unexpected Abort Present
Time
Occurs Before
Closing Flag
Time
Legend:
F = Flag
A = Address byte
C = Control byte
I = Information byte
CR = CRC Byte
Figure 22-5. SCC HDLC Receiving Using RxBDs
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SCC HDLC Mode
22.10 SCC HDLC Transmit Buffer Descriptor (TxBD)
0
1
2
3
4
5
6
7
13
14
15
Offset + 0
Offset + 2
Offset + 4
Offset + 6
R
—
W
I
L
TC
CM
—
UN
CT
Data Length
Tx Buffer Pointer
Figure 22-6. SCC HDLC Transmit Buffer Descriptor (TxBD)
Table 22-8 describes HDLC TxBD status and control fields.
Table 22-8. SCC HDLC TxBD Status and Control Field Descriptions
Bits
Name
R
Description
0
Ready.
0 The buffer is not ready for transmission. Both the buffer and the BD can be updated. The CP
clears R after the buffer is sent or an error is encountered.
1 The buffer has not been sent or is being sent and the BD cannot be updated.
1
2
—
Reserved, should be cleared.
W
Wrap (last BD in TxBD table).
0 Not the last BD in the table.
1 Last BD in the BD table. After this buffer is used, the CP sends data using the BD pointed to by
TBASE. The number of TxBDs in this table is determined by TxBD[W] and the space constraints
of the dual-port RAM.
3
4
5
I
Interrupt.
0 No interrupt is generated after this buffer is processed.
1 SCCE[TXB] or SCCE[TXE] is set when this buffer is processed, causing interrupts if not masked.
L
Last.
0 Not the last buffer in the frame.
1 Last buffer in the frame.
TC
Tx CRC. Valid only when TxBD[L] = 1. Otherwise, it is ignored.
0 Transmit the closing flag after the last data byte. This setting can be used to send a bad CRC after
the data for testing purposes.
1 Transmit the CRC sequence after the last data byte.
6
CM
Continuous mode.
0 Normal operation.
1 The CP does not clear TxBD[R] after this BD is closed allowing the buffer to be resent the next
time the CP accesses this BD. However, TxBD[R] is cleared if an error occurs during
transmission, regardless of CM.
7–13
14
—
UN
CT
Reserved, should be cleared.
Underrun. Set after the SCC sends a buffer and a transmitter underrun occurred.
15
CTS lost. Indicates when CTS in NMSI mode or layer 1 grant is lost in GCI or IDL mode during frame
transmission. If data from more than one buffer is currently in the FIFO when this error occurs, the
HDLC writes CT in the current BD after sending the buffer.
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Freescale Semiconductor
22-11
SCC HDLC Mode
The data length and buffer pointer fields are described in Section 20.2, “SCC Buffer Descriptors (BDs).”
22.11 HDLC Event Register (SCCE)/HDLC Mask Register (SCCM)
The SCC event register (SCCE) is used as the HDLC event register to report events recognized by the
HDLC channel and to generate interrupts. When an event is recognized, the SCC sets the corresponding
SCCE bit. Interrupts generated through SCCE can be masked in the SCC mask register (SCCM) which has
the same bit format as the SCCE. Setting an SCCM bit enables the corresponding interrupt; clearing a bit
masks it. SCCE bits are cleared by writing ones; writing zeros has no effect. All unmasked bits must be
operation.
0
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Field
Reset
R/W
—
DCC FLG IDL GRA
—
TXE RXF BSY TXB RXB
0000_0000_0000_0000
R/W
Addr
Figure 22-7. HDLC Event Register (SCCE)/HDLC Mask Register (SCCM)
Table 22-9 describes SCCE/SCCM fields.
1
Table 22-9. SCCE/SCCM Field Descriptions
Description
Reserved, should be cleared. Refer to note 1 below.
Bits
Name
0–4
5
—
DCC DPLL carrier sense changed. Set when the carrier sense status generated by the DPLL changes.
Real-time status can be read in SCCS[CS]. This is not the CD status reported in port C. Valid only when
the DPLL is used.
6
7
8
FLG Flag status. Set when the SCC stops or starts receiving HDLC flags. Real-time status can be read in
SCCS[FG].
IDL
Idle sequence status changed. Set when HDLC line status changes. Real-time status of the line can be
read in SCCS[ID].
GRA Graceful stop complete. A GRACEFUL STOP TRANSMIT command completed execution. Set as soon as the
transmitter has sent a frame in progress when the command was issued. Set immediately if no frame
was in progress when the command was issued.
9–10
11
—
Reserved, should be cleared. Refer to note 1 below.
TXE Tx error. Indicates an error (CTS lost or underrun) has occurred on the transmitter channel.
12
RXF Rx frame. Set when the number of receive frames specified in RFTHR are received on the HDLC
channel. It is set no sooner than two clocks after the last bit of the closing flag is received. This event is
not maskable via the RxBD[I] bit.
13
BSY Busy condition. Indicates a frame arrived but was discarded due to a lack of buffers.
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SCC HDLC Mode
1
Table 22-9. SCCE/SCCM Field Descriptions (continued)
Description
Bits
Name
14
TXB Transmit buffer. Enabled by setting TxBD[I]. TXB is set when a buffer is sent on the HDLC channel. For
the last buffer in the frame, TXB is not set before the last bit of the closing flag begins its transmission;
otherwise, it is set after the last byte of the buffer is written to the Tx FIFO.
15
RXB Receive buffer. Enabled by setting RxBD[I]. RXB is set when the HDLC channel receives a buffer that
is not the last in a frame.
1
Reserved bits in the SCCE should not be masked in the SCCM register.
Figure 22-8 shows interrupts that can be generated using the HDLC protocol.
Frame
Received by HDLC
Stored in Rx Buffer
Time
F
F
A
A
C
I
I
I
CR CR F
RXD
Line Idle
Line Idle
CD
HDLC SCCE
Events
CD
IDL FLG FLG
RXB
RXFFLG IDL
FLG
CD
NOTES:
1. RXB event assumes receive buffers are 6 bytes each.
2. The second IDL event occurs after 15 ones are received in a row.
3. The FLG interrupts show the beginning and end of flag reception.
4. The FLG interrupt at the end of the frame may precede the RXF interrupt due to receive FIFO latency.
5. The CD event must be programmed in the port C parallel I/O, not in the SCC itself.
6. F = flag, A = address byte, C = control byte, I = information byte, and CR = CRC byte
Stored in Tx Buffer
Frame
Transmitted by HDLC
TXD
RTS
CTS
Line Idle
F
F
A
A
C CR CR F
Line Idle
HDLC SCCE
Events
CTS
TXB
CTS
NOTES:
1. TXB event shown assumes all three bytes were put into a single buffer.
2. Example shows one additional opening flag. This is programmable.
3. The CTS event must be programmed in the port C parallel I/O, not in the SCC itself.
Figure 22-8. SCC HDLC Interrupt Event Example
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22-13
SCC HDLC Mode
22.12 SCC HDLC Status Register (SCCS)
The SCC status register (SCCS), shown in Figure 22-9, permits monitoring of real-time status conditions
on RXD. The real-time status of CTS and CD are part of the port C parallel I/O.
0
4
5
6
7
Field
Reset
R/W
—
FG
CS
ID
0000_0000
R
Addr
Figure 22-9. CC HDLC Status Register (SCCS)
Table 22-10 describes HDLC SCCS fields.
Table 22-10. HDLC SCCS Field Descriptions
Bits
Name
Description
0–4
5
—
Reserved, should be cleared.
Flags. The line is checked after the data has been decoded by the DPLL.
FG
0 HDLC flags are not being received. The most recently received 8 bits are examined every bit time
to see if a flag is present.
1 HDLC flags are being received. FG is set as soon as an HDLC flag (0x7E) is received on the line.
Once it is set, it remains set at least 8 bit times and the next eight received bits are examined. If
another flag occurs, FG stays set for at least another eight bits. If not, it is cleared and the search
begins again.
6
7
CS
ID
Carrier sense (DPLL). Shows the real-time carrier sense of the line as determined by the DPLL.
0 The DPLL does not sense a carrier.
1 The DPLL senses a carrier.
Idle status.
0 The line is busy.
1 Set when RXD is a logic 1 (idle) for 15 or more consecutive bit times. It is cleared after a single
logic 0 is received.
22.13 SCC HDLC Programming Examples
The following sections show examples for programming SCCs in HDLC mode. The first example uses an
external clock. The second example implements Manchester encoding.
22.14 SCC HDLC Programming Example #1
The following initialization sequence is for an SCC HDLC channel with an external clock. SCC2 is used
with RTS2, CTS2, and CD2 active; CLK3 is used for both the HDLC receiver and transmitter.
1. Configure port D pins to enable TXD2 and RXD2. Set PPARD[27,28] and PDIRD[27] and clear
PDIRD[28] and PSORD[27,28].
2. Configure ports C and D pins to enable RTS2, CTS2 and CD2. Set PPARD[26], PPARC[12,13]
and PDIRD[26] and clear PDIRC[12,13], PSORC[12,13] and PSORD[26].
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SCC HDLC Mode
3. Configure port C pin 29 to enable the CLK3 pin. Set PPARC[29] and clear PDIRC[29] and
PSORC[29].
4. Connect CLK3 to SCC2 using the CPM mux. Write 0b110 to CMXSCR[R2CS] and
CMXSCR[T2CS].
5. Connect the SCC2 to the NMSI (its own set of pins). clear CMXSCR[SC2].
6. Write RBASE and TBASE in the SCC2 parameter RAM to point to the RxBD and TxBD tables in
dual-port RAM. Assuming one RxBD at the start of dual-port RAM and one TxBD following it,
write RBASE with 0x0000 and TBASE with 0x0008.
7. Write RBASE and TBASE in the SCC2 parameter RAM to point to the RxBD and TxBD tables in
dual-port RAM. Assuming one RxBD at the start of dual-port RAM and one TxBD following it,
write RBASE with 0x0000 and TBASE with 0x0008.
8. Write 0x04A1_0000 to CPCR to execute the INIT RX AND TX PARAMS command for SCC2. This
command updates RBPTR and TBPTR of the serial channel with the new values of RBASE and
TBASE.
9. Write RFCR with 0x10 and TFCR with 0x10 for normal operation.
10. Write MRBLR with the maximum number of bytes per Rx buffer. Choose 256 bytes (MRBLR =
0x0100) so an entire Rx frame can fit in one buffer.
11. Write C_MASK with 0x0000F0B8 to comply with 16-bit CCITT-CRC.
12. Write C_PRES with 0x0000FFFF to comply with 16-bit CCITT-CRC.
13. Clear DISFC, CRCEC, ABTSC, NMARC, and RETRC for clarity.
14. Write MFLR with 0x0100 so the maximum frame size is 256 bytes.
15. Write RFTHR with 0x0001 to allow interrupts after each frame.
16. Write HMASK with 0x0000 to allow all addresses to be recognized.
17. Clear HADDR1–HADDR4 for clarity.
18. Initialize the RxBD. Assume the buffer is at 0x0000_1000 in main memory. RxBD[Status and
Control]= 0xB000, RxBD[Data Length] = 0x0000 (not required), and RxBD[Buffer Pointer] =
0x0000_1000.
19. Initialize the TxBD. Assume the Tx data frame is at 0x0000_2000 in main memory and contains
five 8-bit characters. TxBD[Status and Control] = 0xBC00, TxBD[Data Length] = 0x0005, and
TxBD[Buffer Pointer] = 0x0000_2000.
20. Write 0xFFFF to SCCE to clear any previous events.
21. Write 0x001A to SCCM to enable TXE, RXF, and TXB interrupts.
22. Write 0x0040_0000 to the SIU interrupt mask register low (SIMR_L) so the SMC1 can generate a
system interrupt. Initialize SIU interrupt pending register low (SIPNR_L) by writing
0xFFFF_FFFF to it.
23. Write 0x0000_0000 to GSMR_H2 to enable normal CTS and CD behavior with idles (not flags)
between frames.
24. Write 0x0000_0000 to GSMR_L2 to configure CTS and CD to control transmission and reception
in HDLC mode. Normal Tx clock operation is used. Notice that the transmitter (ENT) and receiver
(ENR) have not been enabled. If inverted HDLC operation is preferred, set RINV and TINV.
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SCC HDLC Mode
25. Write 0x0000 to PSMR2 to configure one opening and one closing flag, 16-bit CCITT-CRC, and
prevent multiple frames in the FIFO.
26. Write 0x00000030 to GSMR_L2 to enable the SCC2 transmitter and receiver. This additional write
ensures that ENT and ENR are enabled last.
NOTE
After 5 bytes and CRC have been sent, the Tx buffer is closed; the Rx buffer
is closed after a frame is received. Frames larger than 256 bytes cause a busy
(out-of-buffers) condition because only one RxBD is prepared.
22.14.1 SCC HDLC Programming Example #2
The following sequence initializes an HDLC channel that uses the DPLL in a Manchester encoding.
Provide a clock which is 16× the chosen bit rate of CLK3. Then connect CLK3 to the HDLC transmitter
and receiver. (A baud rate generator could be used instead.) Configure SCC2 to use RTS2, CTS2, and CD2.
1. Follow steps 1–22 in example #1 above.
2. Write 0x004A_A400 to GSMR_L2 to make carrier sense always active, a 16-bit preamble of ‘01’
patterns, 16× operation of the DPLL and Manchester encoding for the receiver and transmitter, and
HDLC mode. CTS and CD should be configured to control transmission and reception. Do not set
GSMR[ENT, ENR].
3. Write 0x0000 to PSMR2 to use one opening and one closing flag and 16-bit CCITT-CRC and to
reject multiple frames in the FIFO.
4. Write 0x004A_A430 to GSMR_L2 to enable the SCC2 transmitter and receiver. This additional
write to GSMR_L2 ensures that ENT and ENR are enabled last.
22.15 HDLC Bus Mode with Collision Detection
The HDLC controller includes an option for hardware collision detection and retransmission on an
open-drain connected HDLC bus, referred to as HDLC bus mode. Most HDLC-based controllers provide
only point-to-point communications; however, the HDLC bus enhancement allows implementation of an
HDLC-based LAN and other point-to-multipoint configurations. The HDLC bus is based on techniques
used in the CCITT ISDN I.430 and ANSI T1.605 standards for D-channel point-to-multipoint operation
over the S/T interface. However, the HDLC bus does not fully comply with I.430 or T1.605 and cannot
replace devices that implement these protocols. Instead, it is more suited to non-ISDN LAN and
point-to-multipoint configurations.
Review the basic features of the I.430 and T1.605 before learning about the HDLC bus. The I.430 and
T1.605 define a way to connect eight terminals over the D-channel of the S/T ISDN bus. The layer 2
protocol is a variant of HDLC, called LAPD. However, at layer 1, a method is provided to allow the eight
terminals to send frames to the switch through the physical S/T bus.
To determine whether a channel is clear, the S/T interface device looks at an echo bit on the line designed
to echo the last bit sent on the D channel. Depending on the class of terminal and the context, an S/T
interface device waits for 7–10 ones on the echo bit before letting the LAPD frame begin transmission,
after which the S/T interface monitors transmitted data. As long as the echo bit matches the sent data,
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SCC HDLC Mode
transmission continues. If the echo bit is ever 0 when the transmit bit is 1, a collision occurs between
terminals; the station(s) that sent a zero stops transmitting. The station that sent a 1 continues as normal.
The I.430 and T1.605 standards provide a physical layer protocol that allows multiple terminals to share
one physical connection. These protocols handle collisions efficiently because one station can always
complete its transmission, at which point, it lowers its own priority to give other devices fair access to the
physical connection.
The HDLC bus differs from the I.430 and T1.605 standards as follows:
•
The HDLC bus uses a separate input signal rather than the echo bit to monitor data; the transmitted
data is simply connected to the CTS input.
•
The HDLC bus is a synchronous, digital open-drain connection for short-distance configurations,
rather than the more complex S/T interface.
•
•
Any HDLC-based frame protocol can be used at layer 2, not just LAPD.
HDLC bus devices wait 8–10 rather than 7–10 bit times before transmitting. (HDLC bus has only
one class.)
The collision-detection mechanism supports only:
•
•
•
•
NRZ-encoded data
A common synchronous clock for all receivers and transmitters
Non-inverted data (GSMR[RINV, TINV] = 0)
Open-drain connection with no external transceivers
Figure 22-10 shows the most common HDLC bus LAN configuration, a multimaster configuration. A
station can transfer data to or from any other LAN station. Transmissions are half-duplex, which is typical
in LANs.
+ 3.3 V
R
HDLC Bus LAN
RXD TXD CTS
RXD TXD CTS
RXD TXD CTS
HDLC Bus
Controller
B
HDLC Bus
Controller
C
HDLC Bus
Controller
A
RCLK/TCLK
RCLK/TCLK
RCLK/TCLK
Clock
Master
Master
Master
NOTES:
1. Transceivers may be used to extend the LAN size.
2. The TXD pins of slave devices should be configured to open-drain in the port C parallel I/O port.
3. Clock is a common RCLK/TCLK for all stations.
Figure 22-10. Typical HDLC Bus Multimaster Configuration
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SCC HDLC Mode
In single-master configuration, a master station transmits to any slave station without collisions. Slaves
communicate only with the master, but can experience collisions in their access over the bus. In this
configuration, a slave that communicates with another slave must first transmit its data to the master, where
the data is buffered in RAM and then resent to the other slave. The benefit of this configuration, however,
is that full-duplex operation can be obtained. In a point-to-multipoint environment, this is the preferred
+ 3.3 V
HDLC Bus LAN
R
RXD
TXD
RXD TXD CTS
RXD TXD CTS
HDLC
Controller
A
HDLC Bus
Controller
B
HDLC Bus
Controller
C
RCLK TCLK
RCLK TCLK
RCLK TCLK
Clock1
Clock2
Master
Slave
Slave
NOTES:
1. Transceivers may be used to extend the LAN size.
2. The TXD pins of slave devices should be configured to open-drain in the port C parallel I/O port.
3. Clock1 is the master RCLK and the slave TCLK.
4. Clock2 is the master TCLK and the slave RCLK.
Figure 22-11. Typical HDLC Bus Single-Master Configuration
22.15.1 HDLC Bus Features
The main features of the HDLC bus are as follows:
•
•
•
•
•
Superset of the HDLC controller features
Automatic HDLC bus access
Automatic retransmission in case of collision
May be used with the NMSI or a TDM bus
Delayed RTS mode
22.15.2 Accessing the HDLC Bus
The HDLC bus protocol ensures orderly bus control when multiple transmitters attempt simultaneous
access. The transmitter sending a zero bit at the time of collision completes the transmission. If a station
sends out an opening flag (0x7E) while another station is already sending, the collision is always detected
within the first byte, because the transmission in progress is using zero bit insertion to prevent flag
imitation.
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22-18
Freescale Semiconductor
SCC HDLC Mode
While in the active condition (ready to transmit), the HDLC bus controller monitors the bus using CTS. It
counts the one bits on CTS. When eight consecutive ones are counted, the HDLC bus controller starts
transmitting on the line; if a zero is detected, the internal counter is cleared. During transmission, data is
continuously compared with the external bus using CTS. CTS is sampled halfway through the bit time
using the rising edge of the Tx clock. If the transmitted bit matches the received CTS bus sample,
transmission continues. However, if the received CTS sample is 0 and the transmitted bit is 1, transmission
stops after that bit and waits for an idle line before attempting retransmission. Since the HDLC bus uses a
wired-OR scheme, a transmitted zero has priority over a transmitted 1. Figure 22-12 shows how CTS is
used to detect collisions.
TCLK
TXD
(Output)
CTS
(Input)
CTS sampled at halfway point.
Collision detected when
TXD=1, but CTS=0.
Figure 22-12. Detecting an HDLC Bus Collision
If both the destination address and source address are included in the HDLC frame, then a predefined
priority of stations results; if two stations begin to transmit simultaneously, they necessarily detect a
collision no later than the end of the source address.
The HDLC bus priority mechanism ensures that stations share the bus equally. To minimize idle time
between messages, a station normally waits for eight one bits on the line before attempting transmission.
After successfully sending a frame, a station waits for 10 rather than eight consecutive one bits before
attempting another transmission. This mechanism ensures that another station waiting to transmit acquires
the bus before a station can transmit twice. When a low priority station detects 10 consecutive ones, it tries
to transmit; if it fails, it reinstates the high priority of waiting for only eight ones.
22.15.3 Increasing Performance
Because it uses a wired-OR configuration, HDLC bus performance is limited by the rise time of the one
bit. To increase performance, give the one bit more rise time by using a clock that is low longer than it is
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
22-19
SCC HDLC Mode
TCLK
TXD
(Output)
CTS
(Input)
CTS sampled at three quarter point.
Collision detected when
TXD=1, but CTS=0.
Figure 22-13. Nonsymmetrical Tx Clock Duty Cycle for Increased Performance
22.15.4 Delayed RTS Mode
Figure 22-14 shows local HDLC bus controllers using a standard transmission line and a local bus. The
controllers do not communicate with each other but with a station on the transmission line; yet the HDLC
bus protocol controls access to the transmission line.
+ 3.3 V
Local HDLC Bus
Rx
R
Line Driver
Tx
(1-Bit Delay)
RXD TXD CTS
RXD TXD CTS
HDLC Bus
Controller
A
HDLC Bus
Controller
B
EN
RTS
RTS
NOTES:
1. The TXD pins of slave devices should be configured to open-drain in the port C parallel I/O port.
2. The RTS pins of each HDLC bus controller are configured to delayed RTS mode.
Figure 22-14. HDLC Bus Transmission Line Configuration
Normally, RTS goes active at the beginning of the opening flag’s first bit. Setting PSMR[BRM] delays
RTS by one bit, which is useful when the HDLC bus connects multiple local stations to a transmission line.
If the transmission line driver has a one-bit delay, the delayed RTS can be used to enable the output of the
line driver. As a result, the electrical effects of collisions are isolated locally. Figure 22-15 shows RTS
timing.
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22-20
Freescale Semiconductor
SCC HDLC Mode
Collision
3rd Bit
TCLK
TXD
CTS
RTS
1st Bit
2nd Bit
RTS active for
only 2 bit times
Figure 22-15. Delayed RTS Mode
22.15.5 Using the Time-Slot Assigner (TSA)
HDLC bus controllers can be used with a time-division multiplexed transmission line and a local bus, as
stations that share a time slot use the HDLC bus protocol to control access to the local bus.
+ 3.3 V
Local HDLC Bus
Rx
R
Tx
Line Driver
L1RXD L1TXD CTS
L1RXDL1TXD CTS
L1RXD L1TXD CTS
L1RXD L1TXD CTS
HDLC Bus
Controller
A
HDLC Bus
Controller
B
HDLC Bus
Controller
C
HDLC Bus
Controller
D
Stations share time-slot n
Stations share time-slot m
NOTES:
1. All TXD pins of slave devices should be configured to open-drain in the port C parallel I/O port.
2. The TSA in the SI of each station is used to configure the preferred time slot.
3. The choice of the number of stations to share a time slot is user-defined. It is two in this example.
Figure 22-16. HDLC Bus TDM Transmission Line Configuration
The local SCCs in HDLC bus mode communicate only with the transmission line and not with each other.
The SCCs use the TSA of the serial interface, receiving and sending data over L1TXDx and L1RXDx.
Because collisions are still detected from the individual SCC CTS pin, it must be configured to connect to
the chosen SCC. Because the SCC only receives clocks during its time slot, CTS is sampled only during
the Tx clock edges of the particular SCC time slot.
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Freescale Semiconductor
22-21
SCC HDLC Mode
22.15.6 HDLC Bus Protocol Programming
The HDLC bus on the PowerQUICC II is implemented using the SCC in HDLC mode with bus-specific
options selected in the PSMR and GSMR, as outlined below. See also Section 22.5, “Programming the
22.15.6.1 Programming GSMR and PSMR for the HDLC Bus Protocol
To program the protocol-specific mode register (PSMR), set the bits as described below:
•
•
•
•
•
Configure NOF as preferred
Set RTE and BUS to 1
Set BRM to 1 if delayed RTS is desired
Configure CRC to 16-bit CRC CCITT (0b00).
Configure other bits to zero or default.
To program the general SCC mode register (GSMR), set the bits as described below:
•
•
•
•
•
•
•
Set MODE to HDLC mode (0b0000).
Configure CTSS to 1 and all other bits to zero or default.
Configure the DIAG bits for normal operation (0b00).
Configure RDCR and TDCR for 1× clock (0b00).
Configure TENC and RENC for NRZ (0b000).
Clear RTSM to send idles between frames.
Set GSMR_L[ENT, ENR] as the last step to begin operation.
22.15.6.2 HDLC Bus Controller Programming Example
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Freescale Semiconductor
Chapter 23
SCC BISYNC Mode
The byte-oriented BISYNC protocol was developed by IBM for use in networking products. There are
three classes of BISYNC frames—transparent, nontransparent with header, and nontransparent without
header, shown in Figure 23-1. The transparent frame type in BISYNC is not related to transparent mode,
be sent with any possible character pattern. Each class of frame starts with a standard two-octet
synchronization pattern and ends with a block check code (BCC). The end-of-text character (ETX) is used
to separate the text and BCC fields.
Nontransparent with Header
SYN1
SYN1
SYN1
SYN2
SYN2
SYN2
SOH
STX
DLE
Header
STX
Text
ETX
ETX
ETX
BCC
BCC
BCC
Nontransparent without Header
Text
Transparent
STX
Transparent Text
DLE
Figure 23-1. Classes of BISYNC Frames
The bulk of a frame is divided into fields whose meaning depends on the frame type. The BCC is a 16-bit
CRC format if 8-bit characters are used; it is a combination longitudinal (sum check) and vertical (parity)
redundancy check if 7-bit characters are used. In transparent operation, a special character (DLE) is
defined that tells the receiver that the next character is text, allowing BISYNC control characters to be
valid text data in a frame. A DLE sent as data must be preceded by a DLE character. This is sometimes
called byte-stuffing. The physical layer of the BISYNC communications link must synchronize the
receiver and transmitter, usually by sending at least one pair of synchronization characters before each
frame.
BISYNC protocol is unusual in that a transmit underrun need not be an error. If an underrun occurs, a
synchronization pattern is sent until data is again ready. In nontransparent operation, the receiver discards
additional synchronization characters (SYNCs) as they are received. In transparent mode, DLE-SYNC
pairs are discarded. Normally, for proper transmission, an underrun must not occur between the DLE and
its following character. This failure mode cannot occur with the PowerQUICC II.
An SCC can be configured as a BISYNC controller to handle basic BISYNC protocol in normal and
transparent modes. The controller can work with the time-slot assigner (TSA) or nonmultiplexed serial
interface (NMSI). The controller has separate transmit and receive sections whose operations are
asynchronous with the core and either synchronous or asynchronous with other SCCs.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
23-1
SCC BISYNC Mode
23.1 Features
The following list summarizes features of the SCC in BISYNC mode:
•
•
•
•
•
•
•
•
•
•
•
•
•
Flexible data buffers
Eight control character recognition registers
Automatic SYNC1–SYNC2 detection
16-bit pattern (bisync)
8-bit pattern (monosync)
4-bit pattern (nibblesync)
External SYNC pin support
SYNC/DLE stripping and insertion
CRC16 and LRC (sum check) generation/checking
VRC (parity) generation/checking
Supports BISYNC transparent operation
Maintains parity error counter
Reverse data mode capability
23.2 SCC BISYNC Channel Frame Transmission
The BISYNC transmitter is designed to work with almost no core intervention. When the transmitter is
enabled, it starts sending SYN1–SYN2 pairs in the data synchronization register (DSR) or idles as
programmed in the PSMR. The BISYNC controller polls the first BD in the channel’s TxBD table. If there
is a message to send, the controller fetches the message from memory and starts sending it after the
SYN1–SYN2 pair. The entire pair is always sent, regardless of GSMR[SYNL].
After a buffer is sent, if the last (TxBD[L]) and the Tx block check sequence (TxBD[TB]) bits are set, the
BISYNC controller appends the CRC16/LRC and then writes the message status bits in TxBD status and
control fields and clears the ready bit, TxBD[R]. It then starts sending the SYN1–SYN2 pairs or idles,
according to GSMR[RTSM]. If the end of the current BD is reached and TxBD[L] is not set, only
TxBD[R] is cleared. In both cases, an interrupt is issued according to TxBD[I]. TxBD[I] controls whether
interrupts are generated after transmission of each buffer, a specific buffer, or each block. The controller
then proceeds to the next BD.
If no additional buffers have been sent to the controller for transmission, an in-frame underrun is detected
and the controller starts sending syncs or idles. If the controller is in transparent mode, it sends DLE-sync
pairs. Characters are included in the block check sequence (BCS) calculation on a per-buffer basis. Each
buffer can be programmed independently to be included or excluded from the BCS calculation; thus,
excluded characters must reside in a separate buffer. The controller can reset the BCS generator before
sending a specific buffer. In transparent mode, the controller inserts a DLE before sending a DLE
character, so that only one DLE is used in the calculation.
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Freescale Semiconductor
SCC BISYNC Mode
23.3 SCC BISYNC Channel Frame Reception
Although the receiver is designed to work with almost no core intervention, the user can intervene on a
per-byte basis if necessary. The receiver performs CRC16, longitudinal (LRC) or vertical redundancy
(VRC) checking, sync stripping in normal mode, DLE-sync stripping, stripping of the first DLE in
DLE-DLE pairs in transparent mode, and control character recognition. Control characters are discussed
When enabled, the receiver enters hunt mode where the data is shifted into the receiver shift register one
bit at a time and the contents of the shift register are compared to the contents of DSR[SYN1, SYN2]. If
the two are unequal, the next bit is shifted in and the comparison is repeated. When registers match, hunt
mode is terminated and character assembly begins. The controller is character-synchronized and performs
SYNC stripping and message reception. It reverts to hunt mode when it receives an ENTER HUNT MODE
command, an error condition, or an appropriate control character.
When receiving data, the controller updates the CR bit in the BD for each byte transferred. When the buffer
is full, the controller clears the E bit in the BD and generates an interrupt if the I bit in the BD is set. If
incoming data exceeds the buffer length, the controller fetches the next BD; if E is zero, reception
continues to its buffer.
When a BCS is received, it is checked and written to the buffer. The BISYNC controller sets the last bit,
writes the message status bits into the BD, clears the E bit, and then generates a maskable interrupt,
indicating that a block of data was received and is in memory. The BCS calculations do not include SYNCs
(in nontransparent mode) or DLE-SYNC pairs (in transparent mode).
Note that GSMR_H[RFW] should be set for an 8-bit-wide receive FIFO for the BISYNC receiver. See
23.4 SCC BISYNC Parameter RAM
Table 23-1. SCC BISYNC Parameter RAM Memory Map
1
Offset
Name
Width
Description
0x30
0x34
0x38
0x3A
0x3C
—
Word Reserved
CRCC
PRCRC
PTCRC
PAREC
Word CRC constant temp value.
Hword Preset receiver/transmitter CRC16/LRC. These values should be preset to all
ones or zeros, depending on the BCS used.
Hword
16
Hword Receive parity error counter. This 16-bit (modulo 2 ) counter maintained by the
CP counts parity errors on receive if the parity feature of BISYNC is enabled.
Initialize PAREC while the channel is disabled.
0x3E
BSYNC
Hword BISYNC SYNC register. Contains the value of the SYNC to be sent as the second
byte of a DLE–SYNC pair in an underrun condition and stripped from incoming
data on receive once the receiver synchronizes to the data using the DSR and
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Freescale Semiconductor
23-3
SCC BISYNC Mode
Table 23-1. SCC BISYNC Parameter RAM Memory Map
Width Description
1
Offset
Name
BDLE
0x40
Hword BISYNC DLE register. Contains the value to be sent as the first byte of a
DLE–SYNC pair and stripped on receive. See Section 23.8, “SCC BISYNC DLE
0x42
0x44
0x46
0x48
CHARACTER1 Hword Control character 1–8. These values represent control characters that the
BISYNC controller recognizes. See Section 23.6, “SCC BISYNC Control
CHARACTER2 Hword
CHARACTER3 Hword
CHARACTER4 Hword
0x4A CHARACTER5 Hword
0x4C CHARACTER6 Hword
0x4E CHARACTER7 Hword
0x50
0x52
CHARACTER8 Hword
RCCM Hword Receive control character mask. Masks CHARACTERn comparison so control
character classes can be defined. Setting a bit enables and clearing a bit masks
1
GSMR[MODE] determines the protocol for each SCC. The SYN1–SYN2 synchronization characters are
controller uses the same basic data structure as other modes; receive and transmit errors are reported
through their respective BDs. There are two basic ways to handle BISYNC channels:
•
The controller inspects the data on a per-byte basis and interrupts the core each time a byte is
received.
•
The controller can be programmed so software handles the first two or three bytes. The controller
directly handles subsequent data without interrupting the core.
23.5 SCC BISYNC Commands
Transmit and receive commands are issued to the CP command register (CPCR). Transmit commands are
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Freescale Semiconductor
SCC BISYNC Mode
Table 23-2. Transmit Commands
Description
Command
STOP TRANSMIT
After hardware or software is reset and the channel is enabled in the GSMR, the channel is in
transmit enable mode and starts polling the first BD every 64 transmit clocks. This command stops
transmission after a maximum of 64 additional bits without waiting for the end of the buffer and the
transmit FIFO to be flushed. TBPTR is not advanced, no new BD is accessed, and no new buffers
are sent for this channel. SYNC–SYNC or DLE–SYNC pairs are sent continually until a RESTART
TRANSMIT is issued. A STOP TRANSMIT can be used when an EOT sequence should be sent and
transmission should stop. After transmission resumes, the EOT sequence should be the first buffer
sent to the controller.
Note that the controller remains in transparent or normal mode after it receives a STOP TRANSMIT or
RESTART TRANSMIT command.
GRACEFUL STOP Stops transmission after the current frame finishes sending or immediately if there is no frame being
TRANSMIT
sent. SCCE[GRA] is set once transmission stops. Then BISYNC transmit parameters and TxBDs
can be modified. The TBPTR points to the next TxBD. Transmission resumes when the R bit of the
next BD is set and a RESTART TRANSMIT is issued.
RESTART
TRANSMIT
Lets characters be sent on the transmit channel. The BISYNC controller expects it after a STOP
TRANSMIT or a GRACEFUL STOP TRANSMIT command is issued, after a transmitter error occurs, or after
a STOP TRANSMIT is issued and the channel is disabled in its SCCM. The controller resumes
transmission from the current TBPTR in the channel’s TxBD table.
INIT TX
Initializes all transmit parameters in the serial channel’s parameter RAM to their reset state. Issue
only when the transmitter is disabled. INIT TX AND RX PARAMETERS resets transmit and receive
parameters.
PARAMETERS
Table 23-3. Receive Commands
Command
Description
RESET BCS
Immediately resets the receive BCS accumulator. It can be used to reset the BCS after recognizing
a control character, thus signifying that a new block is beginning.
CALCULATION
ENTER HUNT
MODE
After hardware or software is reset and the channel is enabled in SCCM, the channel is in receive
enable mode and uses the first BD. This command forces the controller to stop receiving and enter
hunt mode, during which the controller continually scans the data stream for an SYN1–SYN2
sequence as programmed in the DSR. After receiving the command, the current receive buffer is
closed and the BCS is reset. Message reception continues using the next BD.
CLOSE RXBD
Used to force the SCC to close the current RxBD if it is in use and to use the next BD for subsequent
data. If data is not being received, no action is taken.
INIT RX
Initializes receive parameters in this serial channel’s parameter RAM to reset state. Issue only when
the receiver is disabled. An INIT TX AND RX PARAMETERS resets transmit and receive parameters.
PARAMETERS
23.6 SCC BISYNC Control Character Recognition
The BISYNC controller recognizes special control characters that customize the protocol implemented by
the BISYNC controller and aid its operation in a DMA-oriented environment. They are used for receive
buffers longer than one byte. In single-byte buffers, each byte can be easily inspected so control character
recognition should be disabled.
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Freescale Semiconductor
23-5
SCC BISYNC Mode
The control character table lets the BISYNC controller recognize the end of the current block. Because the
controller imposes no restrictions on the format of BISYNC blocks, software must respond to received
characters and inform the controller of mode changes and of certain protocol events, such as resetting the
BCS. Using the control character table correctly allows the remainder of the block to be received without
interrupting software.
Up to eight control characters can be defined to inform the BISYNC controller that the end of the current
block is reached and whether a BCS is expected after the character. For example, the end-of-text character
(ETX) implies an end-of-block (ETB) with a subsequent BCS. An enquiry (ENQ) character designates an
end of block without a subsequent BCS. All the control characters are written into the data buffer. The
BISYNC controller uses a table of 16-bit entries to support control character recognition. Each entry
consists of the control character, an end-of-table bit (E), a BCS expected bit (B), and a hunt mode bit (H).
The RCCM entry defines classes of control characters that support masking option. The control character
Offset from
SCCx Base
0
1
2
3
7
8
15
0x42
E
B
H
—
—
—
—
—
—
—
—
—
CHARACTER1
CHARACTER2
CHARACTER3
CHARACTER4
CHARACTER5
CHARACTER6
CHARACTER7
CHARACTER8
MASK VALUE(RCCM)
0x44
E
E
E
E
E
E
E
1
B
B
B
B
B
B
B
1
H
H
H
H
H
H
H
1
0x46
0x48
0x4A
0x4D
0x4E
0x50
0x52
Figure 23-2. Control Character Table and RCCM
Table 23-4 describes control character table and RCCM fields.
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Freescale Semiconductor
SCC BISYNC Mode
Table 23-4. Control Character Table and RCCM Field Descriptions
Offset
Bit
Name
Description
0x42–
0x50
0
E
End of table.
0 This entry is valid. The lower eight bits are checked against the incoming
character. In tables with eight control characters, E should be zero in all eight
positions.
1 The entry is not valid. No other valid entries exist beyond this entry.
1
2
B
H
BCS expected. A maskable interrupt is generated after the buffer is closed.
0 The character is written into the receive buffer and the buffer is closed.
1 The character is written into the receive buffer. The receiver waits for one LRC
or two CRC bytes of BCS and then closes the buffer. This should be used for
ETB, ETX, and ITB.
Hunt mode. Enables hunt mode when the current buffer is closed.
0 The BISYNC controller maintains character synchronization after closing this
buffer.
1 The BISYNC controller enters hunt mode after closing the buffer. When the B
bit is set, the controller enters hunt mode after receiving the BCS.
3–7
—
Reserved
8–15
CHARACTERn Control character 1–8. When using 7-bit characters with parity, include the parity
bit in the character value.
0x52
0–2
3–7
—
—
All ones.
Reserved
8–15
RCCM
Received control character mask. Masks comparison of CHARACTERn. Each bit
of RCCM masks the corresponding bit of CHARACTERn.
0 Mask this bit in the comparison of the incoming character and CHARACTERn.
1 The address comparison on this bit proceeds normally and no masking occurs.
If RCCM is not set, erratic operation can occur during control character
recognition.
23.7 BISYNC SYNC Register (BSYNC)
When an underrun occurs, the BISYNC controller inserts SYNC characters until the next buffer is
available for transmission. If the receiver is not in hunt mode when a SYNC character is received, it
discards this character if the valid bit (BSYNC[V]) is set.When using 7-bit characters with parity, the
parity bit should be included in the SYNC register value.
0
1
2
3
4
5
6
7
8
15
Field
Reset
R/W
V
DIS
0
0
0
0
0
0
SYNC
Undefined
R/W
Addr
SCC Base + 0x3E
Figure 23-3. BISYNC SYNC (BSYNC)
Table 23-5 describes BSYNC fields.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
23-7
SCC BISYNC Mode
Table 23-5. BSYNC Field Descriptions
Description
Bits
Name
0
V
Valid. If V = 1 and the receiver is not in hunt mode when a SYNC character is received, this character
is discarded.
1
DIS
Disable BSYNC stripping
0 Normal mode.
1 BSYNC stripping disabled (BISYNC transparent mode only).
2–7
—
All zeros
8–15
SYNC SYNC character
23.8 SCC BISYNC DLE Register (BDLE)
characters. When an underrun occurs while a message is being sent in transparent mode, the BISYNC
controller inserts DLE-SYNC pairs until the next buffer is available for transmission.
In transparent mode, the receiver discards any DLE character received and excludes it from the BCS if the
valid bit (BDLE[V]) is set. If the second character is SYNC, the controller discards it and excludes it from
the BCS. If it is a DLE, the controller writes it to the buffer and includes it in the BCS. If it is not a DLE
or SYNC, the controller examines the control character table and acts accordingly. If the character is not
in the table, the buffer is closed with the DLE follow character error bit set. If the valid bit is not set, the
receiver treats the character as a normal character. When using 7-bit characters with parity, the parity bit
should be included in the DLE register value.
0
1
2
3
4
5
6
7
8
15
Field
Reset
R/W
V
DIS
0
0
0
0
0
0
DLE
Undefined
R/W
Addr
SCC Base + 0x40
Figure 23-4. BISYNC DLE (BDLE)
Table 23-6 describes BDLE fields.
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Freescale Semiconductor
SCC BISYNC Mode
Table 23-6. BDLE Field Descriptions
Description
Bits
Name
0
1
V
Valid. If V = 1 and the receiver is not in hunt mode when a SYNC character is received, this character
is discarded.
DIS
Disable DLE stripping
0 Normal mode.
1
DLE stripping disabled. When DIS is enabled in BDLE and on BSYNC the following cases occur:
DLE-DLE sequence. Both characters are written to the memory. The BCS is calculated only on
the second DLE.
DLE-SYNC sequence. Both characters are written to the memory, but neither are included in the
BCS calculation.
DLE-ETX, DLE-ITB, DLE-ETB sequence, both characters are written to memory. The BCS is
calculated only on the second character.
2–7
—
All zeros
8–15
DLE
DLE character
23.9 Sending and Receiving the Synchronization Sequence
The BISYNC channel can be programmed to send and receive a synchronization pattern defined in the
pattern. Unless SYNL is zero (external sync), the transmitter always sends the entire DSR contents, lsb
first, before each frame—the chosen 4- or 8-bit pattern can be repeated in the lower-order bits.
Table 23-7. Receiver SYNC Pattern Lengths of the DSR
Bit Assignments
GSMR_H[SYNL]
Setting
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
00
01
10
11
An external SYNC signal is used instead of the SYNC pattern in the DSR.
4-Bit
8-Bit
16-Bit
23.10 Handling Errors in the SCC BISYNC
The controller reports message transmit and receive errors using the channel BDs, error counters, and the
SCCE. Modem lines can be directly monitored via the parallel port pins. Table 23-8 describes transmit
errors.
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23-9
SCC BISYNC Mode
Error
Table 23-8. Transmit Errors
Description
Transmitter
Underrun
The channel stops sending the buffer, closes it, sets TxBD[UN], and generates aTXE interrupt if it
is enabled. The channel resumes transmission after a RESTART TRANSMIT command is received.
Underrun cannot occur between frames or during a DLE–XXX pair in transparent mode.
CTS Lost during The channel stops sending the buffer, closes it, sets TxBD[CT], and generates a TXE interrupt if not
Message
masked. Transmission resumes when a RESTART TRANSMIT command is received.
Transmission
Table 23-9 describes receive errors.
Table 23-9. Receive Errors
Error
Description
Overrun
The controller maintains a receiver FIFO for receiving data. The CP begins programming the SDMA
channel (if the buffer is in external memory) and updating the CRC when the first byte is received in
the Rx FIFO. If an Rx FIFO overrun occurs, the controller writes the received byte over the previously
received byte. The previous character and its status bits are lost. The channel then closes the buffer,
sets RxBD[OV], and generates the RXB interrupt if it is enabled. Finally, the receiver enters hunt
mode.
CD Lost during The channel stops receiving, closes the buffer, sets RxBD[CD], and generates the RXB interrupt if
Message
Reception
not masked. This error has the highest priority. If the rest of the message is lost, no other errors are
checked in the message. The receiver immediately enters hunt mode.
Parity
The channel writes the received character to the buffer and sets RxBD[PR]. The channel stops
receiving, closes the buffer, sets RxBD[PR], and generates the RXB interrupt if it is enabled. The
channel also increments PAREC and the receiver immediately enters hunt mode.
CRC
The channel updates the CR bit in the BD every time a character is received with a byte delay of
eight serial clocks between the status update and the CRC calculation. When control character
recognition is used to detect the end of the block and cause CRC checking, the channel closes the
buffer, sets the CR bit in the BD, and generates the RXB interrupt if it is enabled.
23.11 BISYNC Mode Register (PSMR)
can be modified on-the-fly.
0
3
4
5
6
7
8
9
10
11
12
13
14
15
Field
Reset
R/W
NOS
CRC
RBCS RTR RVD DRT
—
RPM
TPM
0
R/W
Addr
Figure 23-5. Protocol-Specific Mode Register for BISYNC (PSMR)
Table 23-10 describes PSMR fields.
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SCC BISYNC Mode
Table 23-10. PSMR Field Descriptions
Description
Bits
Name
0–3
NOS Minimum number of SYN1–SYN2 pairs (defined in DSR) sent between or before messages.If NOS
= 0000, one pair is sent. If NOS = 1111, 16 pairs are sent. The entire pair is always sent, regardless
of how GSMR[SYNL) is set. NOS can be modified on-the-fly.
4–5
CRC CRC selection.
x0 Reserved.
01 CRC16 (BISYNC). X16 + X15 + X2 + 1. PRCRC and PTCRC should be initialized to all zeros or
all ones before the channel is enabled. In either case, the transmitter sends the calculated CRC
noninverted and the receiver checks the CRC against zero. Eight-bit data characters (without
parity) are configured when CRC16 is chosen.
11 LRC (sum check). (BISYNC). For even LRC, initialize PRCRC and PTCRC to zeros before the
channel is enabled; for odd LRC, they should be initialized to ones.
Note that the receiver checks character parity when BCS is programmed to LRC and the receiver
is not in transparent mode. The transmitter sends character parity when BCS is programmed to
LRC and the transmitter is not in transparent mode. Use of parity in BISYNC assumes that 7-bit
data characters are being used.
6
7
RBCS Receive BCS. The receiver internally stores two BCS calculations separated by an eight serial clock
delay to allow examination of a received byte to determine whether it should used in BCS
calculation.
0 Disable receive BCS.
1 Enable receive BCS. Should be set (or reset) within the time taken to receive the following data
byte. When RBCS is reset, BCS calculations exclude the latest fully received data byte. When
RBCS is set, BCS calculations continue as normal.
RTR Receiver transparent mode.
0 Normal receiver mode with SYNC stripping and control character recognition.
1 Transparent receiver mode. SYNCs, DLEs, and control characters are recognized only after a
leading DLE character. The receiver calculates the CRC16 sequence even if it is programmed to
LRC while in transparent mode. Initialize PRCRC to the CRC16 preset value before setting RTR.
8
9
RVD Reverse data.
0 Normal operation.
1 Any portion of this SCC defined to operate in BISYNC mode operates by reversing the character
bit order and sending the msb first.
DRT Disable receiver while sending. DRT should not be set for typical BISYNC operation.
0 Normal operation.
1 As the SCC sends data, the receiver is disabled and gated by the internal RTS signal. This helps
if the BISYNC channel is being configured onto a multidrop line and the user does not want to
receive its own transmission. Although BISYNC usually uses a half-duplex protocol, the receiver
is not actually disabled during transmission.
Note: If DRT = 1, GSMR_H[CDS] should be cleared unless both of the following are true: the same
clock is used for TCLK and RCLK, and CTS either has synchronous timing or is always
asserted.
10–11
—
Reserved, should be cleared.
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Freescale Semiconductor
23-11
SCC BISYNC Mode
Table 23-10. PSMR Field Descriptions (continued)
Description
Bits
Name
12–13
RPM Receiver parity mode. Selects the type of parity check that the receiver performs. RPM can be
modified on-the-fly and is ignored unless CRC = 11 (LRC). Receive parity errors cannot be disabled
but can be ignored.
00 Odd parity. The transmitter counts ones in the data word. If the sum is not odd, the parity bit is
set to ensure an odd number. An even sum indicates a transmission error.
01 Low parity. If the parity bit is not low, a parity error is reported.
10 Even parity. An even number must result from the calculation performed at both ends of the line.
11 High parity. If the parity bit is not high, a parity error is reported.
14–15
TPM Transmitter parity mode. Selects the type of parity the transmitter performs and can be modified
on-the-fly. TPM is ignored unless CRC = 11 (LRC).
00 Odd parity.
01 Force low parity (always send a zero in the parity bit position).
10 Even parity.
11 Force high parity (always send a one in the parity bit position).
23.12 SCC BISYNC Receive BD (RxBD)
The CP uses BDs to report on each buffer received. It closes the buffer, generates a maskable interrupt,
and starts receiving data into the next buffer after any of the following:
•
•
•
•
•
A user-defined control character is received.
An error is detected.
A full receive buffer is detected.
The ENTER HUNT MODE command is issued.
The CLOSE RX BD command is issued.
Figure 23-6 shows the SCC BISYNC RxBD.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Offset + 0
Offset + 2
Offset + 4
Offset + 6
E
—
W
I
C
B
CM
—
DE
—
DL
PR
CR
OV
CD
Data Length
Rx Data Buffer Pointer
Figure 23-6. SCC BISYNC RxBD
Table 23-11 describes SCC BISYNC RxBD status and control fields.
Table 23-11. SCC BISYNC RxBD Status and Control Field Descriptions
Bits
Name
E
Description
0
Empty.
0 The buffer is full or stopped receiving because of an error. The core can read or write any fields
of this RxBD. The CP does not use this BD as long as the E bit is zero.
1 The buffer is not full. The CP controls this BD and buffer. The core should not update this BD.
1
—
Reserved, should be cleared.
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SCC BISYNC Mode
Table 23-11. SCC BISYNC RxBD Status and Control Field Descriptions (continued)
Bits
Name
W
Description
2
Wrap (last BD in table).
0 Not the last BD in the table.
1 Last BD in the table. After this buffer is used, the CP receives incoming data into the first BD that
RBASE points to. The number of BDs in this table is determined by the W bit and by overall space
constraints of the dual-port RAM.
3
I
Interrupt.
0 No interrupt is generated after this buffer is used.
1 SCCE[RXB] is set when the controller closes this buffer, which can cause an interrupt if it is
enabled.
4
5
6
C
B
Control Character. The last byte in the buffer is a user-defined control character.
0 The last byte of this buffer does not contain a control character.
1 The last byte of this buffer contains a control character.
BCS received. The last bytes in the buffer contain the received BCS.
0 This buffer does not contain the BCS.
1 This buffer contains the BCS. A control character may also reside one byte prior to this BCS.
CM
Continuous mode.
0 Normal operation.
1 The CP does not clear E after this BD is closed; the buffer is overwritten when the CP accesses
this BD next. However, E is cleared if an error occurs during reception, regardless of how CM is
set.
7
8
—
Reserved, should be cleared.
DE
DPLL error. Set when a DPLL error occurs during reception. In decoding modes where a transition
is should occur every bit, the DPLL error is set when a transition is missing.
9–10
11
—
Reserved, should be cleared.
DL
DLE follow character error. While in transparent mode, a DLE character was received, and the next
character was not DLE, SYNC, or a valid entry in the control characters table.
12
13
PR
CR
Parity error. Set when a character with parity error is received. Upon a parity error, the buffer is
closed; thus, the corrupted character is the last byte of the buffer. A new Rx buffer receives
subsequent data.
BCS error. Updated every time a byte is written to the buffer. The CR bit includes the calculation for
the current byte. By clearing PSMR[RCBS] within eight serial clocks, the user can exclude the
current character from the message BCS calculation. The data length field may be read to
determine the current character’s position.
14
15
OV
CD
Overrun. Set when a receiver overrun occurs during frame reception.
Carrier detect lost. Indicates when the carrier detect signal, CD, is negated during frame reception.
Data length and buffer pointer fields are described in Section 20.2, “SCC Buffer Descriptors (BDs).” Data
length represents the number of octets the CP writes into this buffer, including the BCS. For BISYNC
mode, clear these bits. It is incremented each time a received character is written to the buffer.
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23-13
SCC BISYNC Mode
23.13 SCC BISYNC Transmit BD (TxBD)
The CP arranges data to be sent on an SCC channel in buffers referenced by the channel TxBD table. The
CP uses BDs to confirm transmission or indicate errors so the core knows buffers have been serviced. The
user configures status and control bits before transmission, but the CP sets them after the buffer is sent.
0
1
2
3
4
5
6
7
8
9
10
11
13
14
15
Offset + 0
Offset + 2
Offset + 4
Offset + 6
R
—
W
I
L
TB
CM BR
TD
TR
B
—
UN
CT
Data Length
Tx Data Buffer Pointer
Figure 23-7. SCC BISYNC Transmit BD (TxBD)
Table 23-12 describes SCC BISYNC TxBD status and control fields.
Table 23-12. SCC BISYNC TxBD Status and Control Field Descriptions
Bits
Name
R
Description
0
Ready.
0 The buffer is not ready for transmission. The current BD and buffer can be updated. The CP
clears R after the buffer is sent or after an error condition.
1 The user-prepared buffer has not been sent or is being sent. This BD cannot be updated while R
= 1.
1
2
—
W
Reserved, should be cleared.
Wrap (last BD in table).
0 Not the last BD in the table.
1 Last BD in the table. After this buffer is used, the CP sends data using the BD pointed to by
TBASE. The number of TxBDs in this table is determined only by the W bit and overall space
constraints of the dual-ported RAM.
3
4
I
Interrupt.
0 No interrupt is generated after this buffer is serviced.
1 SCCE[TXB] or SCCE[TXE] is set after the CP services this buffer, which can cause an interrupt.
L
Last in message.
0 The last character in the buffer is not the last character in the current block.
1 The last character in the buffer is the last character in the current block. The transmitter enters
and stays in normal mode after sending the last character in the buffer and the BCS, if enabled.
5
6
TB
Transmit BCS. Valid only when the L bit is set.
0 Send an SYN1–SYN2 or idle sequence (specified in GSMR[RTSM]) after the last character in the
buffer.
1 Send the BCS sequence after the last character. The controller also resets the BCS generator
after sending the BCS.
CM
Continuous mode.
0 Normal operation.
1 The CP does not clear R after this BD is closed, so the buffer is resent when the CP next
accesses this BD. However, R is cleared if an error occurs during transmission, regardless of how
CM is set.
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SCC BISYNC Mode
Table 23-12. SCC BISYNC TxBD Status and Control Field Descriptions (continued)
Bits
Name
BR
Description
7
BCS reset. Determines whether transmitter BCS accumulation is reset before sending the data
buffer.
0 BCS accumulation is not reset.
1 BCS accumulation is reset before sending the data buffer.
8
9
TD
TR
Transmit DLE.
0 No automatic DLE transmission can occur before the data buffer.
1 The transmitter sends a DLE character before sending the buffer, which saves writing the first
DLE to a separate buffer in transparent mode. See TR for information on control characters.
Transparent mode.
0 The transmitter enters and stays in normal mode after sending the buffer. The transmitter
automatically inserts SYNCs if an underrun condition occurs.
1 The transmitter enters or stays in transparent mode after sending the buffer. It automatically
inserts DLE–SYNC pairs if an underrun occurs (the controller finishes a buffer with L = 0 and the
next BD is not available). It also checks all characters before sending them. If a DLE is detected,
another DLE is sent automatically. Insert a DLE or program the controller to insert one before
each control character. The transmitter calculates the CRC16 BCS even if PSMR[BCS] is
programmed to LRC. Initialize PTCRC to CRC16 before setting TR.
10
B
BCS enable.
0 The buffer consists of characters that are excluded from BCS accumulation.
1 The buffer consists of characters that are included in BCS accumulation.
11–13
14
—
Reserved, should be cleared.
UN
Underrun. Set when the BISYNC controller encounters a transmitter underrun error while sending
the associated data buffer. The CPM writes UN after it sends the associated buffer.
15
CT
CTS lost. The CP sets CT when CTS is lost during message transmission after it sends the data
buffer.
Data length and buffer pointer fields are described in Section 20.2, “SCC Buffer Descriptors (BDs).”
Although it is never modified by the CP, data length should be greater than zero. The CPM writes these
fields after it finishes sending the buffer.
23.14 BISYNC Event Register (SCCE)/BISYNC Mask Register (SCCM)
The BISYNC controller uses the SCC event register (SCCE) to report events recognized by the BISYNC
channel and to generate interrupts. When an event is recognized, the controller sets the corresponding
SCCE bit. Interrupts are enabled by setting, and masked by clearing, the equivalent bits in the BISYNC
mask register (SCCM). SCCE bits are reset by writing ones; writing zeros has no effect. Unmasked bits
must be reset before the CP negates the internal interrupt request signal.
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23-15
SCC BISYNC Mode
0
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Field
—
DCC
—
GRA
—
TXE RCH BSY TXB RXB
Reset
R/W
0000_0000_0000_0000
R/W
Addr
Figure 23-8. BISYNC Event Register (SCCE)/BISYNC Mask Register (SCCM)
Table 23-13 describes SCCE and SCCM fields.
1
Table 23-13. SCCE/SCCM Field Descriptions
Description
Reserved, should be cleared. Refer to note 1 below.
Bits
Name
0–4
5
—
DCC DPLL CS changed. Set when carrier sense status generated by the DPLL changes. Real-time
status can be found in SCCS. This is not the CD status discussed elsewhere. Valid only when DPLL
is used.
6–7
8
—
Reserved, should be cleared. Refer to note 1 below.
GRA Graceful stop complete. Set as soon the transmitter finishes any message in progress when a
GRACEFUL STOP TRANSMIT is issued (immediately if no message is in progress).
9–10
11
—
Reserved, should be cleared. Refer to note 1 below.
TXE Tx Error. Set when an error occurs on the transmitter channel.
12
RCH Receive character. Set when a character is received and written to the buffer.
13
BSY Busy. Set when a character is received and discarded due to a lack of buffers. The receiver resumes
reception after an ENTER HUNT MODE command.
14
15
TXB Tx buffer. Set when a buffer is sent. TXB is set as the last bit of data or the BCS begins transmission.
RXB Rx buffer. Set when the CPM closes the receive buffer on the BISYNC channel.
1
Reserved bits in the SCCE should not be masked in the SCCM register.
23.15 SCC Status Registers (SCCS)
The SCC status (SCCS) register, seen in Figure 23-9, allows real-time monitoring of RXD. The real-time
status of CTS and CD are part of the parallel I/O.
0
5
6
7
Field
Reset
R/W
—
CS
—
0000_0000
R
Addr
Figure 23-9. SCC Status Registers (SCCS)
Table 23-14 describes SCCS fields.
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SCC BISYNC Mode
Table 23-14. SCCS Field Descriptions
Description
Bit
Name
0–5
6
—
Reserved, should be cleared.
CS
Carrier sense (DPLL). Shows the real-time carrier sense of the line as determined by the DPLL.
0 The DPLL does not sense a carrier.
1 The DPLL senses a carrier.
7
—
Reserved, should be cleared.
23.16 Programming the SCC BISYNC Controller
Software has two ways to handle data received by the BISYNC controller. The simplest is to allocate
single-byte receive buffers, request an interrupt on reception of each buffer, and implement BISYNC
protocol entirely in software on a byte-by-byte basis. This flexible approach can be adapted to any
BISYNC implementation. The obvious penalty is the overhead caused by interrupts on each received
character.
A more efficient method is to prepare and link multi-byte buffers in the RxBD table and use software to
analyze the first two to three bytes of the buffer to determine the type of block received. When this is
determined, reception continues without further software intervention until it encounters a control
character, which signifies the end of the block and causes software to revert to byte-by-byte reception.
To accomplish this, set SCCM[RCH] to enable an interrupt on every received byte so software can analyze
each byte. After analyzing the initial characters of a block, either set PSMR[RTR] or issue a RESET BCS
CALCULATION command. For example, if a DLE-STX is received, enter transparent mode. By setting the
appropriate PSMR bit, the controller strips the leading DLE from DLE-character sequences. Thus, control
characters are recognized only when they follow a DLE character. PSMR[RTR] should be cleared after a
DLE-ETX is received.
Alternatively, after an SOH is received, a RESET BCS CALCULATION should be issued to exclude SOH from
BCS accumulation and reset the BCS. Notice that PSMR[RBCS] is not needed because the controller
automatically excludes SYNCs and leading DLEs.
After the type of block is recognized, SCCE[RCH] should be masked. The core does not interrupt data
reception until the end of the current block, which is indicated by the reception of a control character
matching the one in the receive control character table. Using Table 23-15, the control character table
should be set to recognize the end of the block.
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23-17
SCC BISYNC Mode
Table 23-15. Control Characters
Control Characters
E
B
H
ETX
ITB
0
0
0
0
0
1
1
1
0
X
1
0
1
0
X
ETB
ENQ
Next entry
After ETX, a BCS is expected; then the buffer should be closed. Hunt mode should be entered when a line
turnaround occurs. ENQ characters are used to stop sending a block and to designate the end of the block
for a receiver, but no CRC is expected. After control character reception, set SCCM[RCH] to reenable
interrupts for each byte of data received.
23.17 SCC BISYNC Programming Example
This BISYNC controller initialization example for SCC2 uses an external clock. The controller is
configured with RTS2, CTS2, and CD2 active. Both the receiver and transmitter use CLK3.
1. Configure port D pins to enable TXD2 and RXD2. Set PPARD[27,28] and PDIRD[27] and clear
PDIRD[28] and PSORD[27,28].
2. Configure ports C and D pins to enable RTS2, CTS2 and CD2. Set PPARD[26], PPARC[12,13]
and PDIRD[26] and clear PDIRC[12,13], PSORC[12,13], and PSORD[26].
3. Configure port C pin 29 to enable the CLK3 pin. Set PPARC[29] and clear PDIRC[29] and
PSORC[29].
4. Connect CLK3 to SCC2 using the CPM mux. Write 0b110 to CMXSCR[R2CS] and
CMXSCR[T2CS].
5. Connect the SCC2 to the NMSI (its own set of pins). Clear CMXSCR[SC2].
6. Assuming one RxBD at the beginning of dual-port RAM followed by one TxBD, write RBASE
with 0x0000 and TBASE with 0x0008.
7. Write 0x04a1_0000 to CPCR to execute INIT RX AND TX PARAMETERS. This updates RBPTR and
TBPTR to the new values of RBASE and TBASE.
8. Write RFCR and TFCR with 0x10 for normal operation.
9. Write MRBLR with the maximum number of bytes per receive buffer. For this case, assume 16
bytes, so MRBLR = 0x0010.
10. Write PRCRC with 0x0000 to comply with CRC16.
11. Write PTCRC with 0x0000 to comply with CRC16.
12. Clear PAREC for clarity.
13. Write BSYNC with 0x8033, assuming a SYNC value of 0x33.
14. Write DSR with 0x3333.
15. Write BDLE with 0x8055, assuming a DLE value of 0x55.
16. Write CHARACTER1 with 0x6077, assuming ETX = 0x77.
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SCC BISYNC Mode
17. Write CHARACTER2–8 with 0x8000. They are not used.
18. Write RCCM with 0xE0FF. It is not used.
19. Initialize the RxBD and assume the data buffer is at 0x00001000 in main memory. Then write
0xB000 to RxBD[Status and Control], 0x0000 to RxBD[Data Length] (optional), and 0x00001000
to RxBD[Buffer Pointer].
20. Initialize the TxBD and assume the Tx data buffer is at 0x00002000 in main memory and contains
five 8-bit characters. Then write 0xBD20 to TxBD[Status and Control] 0x0005 to TxBD[Data
Length], and 0x00002000 to TxBD[Buffer Pointer]. Note that ETX character should be written at
the end of user’s data.
21. Write 0xFFFF to SCCE to clear any previous events.
22. Write 0x0013 to SCCM to enable the TXE, TXB, and RXB interrupts.
23. Write 0x0040_0000 to the SIU interrupt mask register low (SIMR_L) so the SMC1 can generate a
system interrupt. Initialize SIU interrupt pending register low (SIPNR_L) by writing
0xFFFF_FFFF to it.
24. Write 0x0000002C to GSMR_H2 to configure a small receive FIFO width.
25. Write 0x00000008 to GSMR_L2 to configure CTS and CD to automatically control transmission
and reception (DIAG bits) and the BISYNC mode. Notice that the transmitter (ENT) and receiver
(ENR) are not yet enabled.
26. Set PSMR to 0x0600 to configure CRC16, CRC checking on receive, and normal operation (not
transparent).
27. Write 0x00000038 to GSMR_L2 to enable the SCC2 transmitter and receiver. This additional write
ensures that ENT and ENR are enabled last.
Write 0x00000038 to GSMR_L2 to enable the SCC2 transmitter and receiver. This additional write
ensures that ENT and ENR are enabled last. After 5 bytes are sent, the TxBD is closed. The buffer is closed
after 16 bytes are received. Any received data beyond 16 bytes causes a busy (out-of-buffers) condition
since only one RxBD is prepared.
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SCC BISYNC Mode
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Chapter 24
SCC Transparent Mode
Transparent mode (also called totally transparent or promiscuous mode) provides a clear channel on which
the SCC can send or receive serial data without bit-level manipulation. Software implements protocols run
over transparent mode. An SCC in transparent mode functions as a high-speed serial-to-parallel and
parallel-to-serial converter.
Transparent mode can be used for serially moving data that requires no superimposed protocol, for
applications that require serial-to-parallel and parallel-to-serial conversion for communication among
chips on the same board, and for applications that require data to be switched without interfering with the
protocol encoding itself, such as when data from a high-speed time-multiplexed serial stream is
multiplexed into low-speed data streams. The concept is to switch the data path without altering the
protocol encoded on that data path.
Transparent mode is configured in the GSMR; see Section 20.1.1, “The General SCC Mode Registers
receiver, respectively. Setting both bits enables full-duplex transparent operation. If only one is set, the
other half of the SCC uses the protocol specified in GSMR_L[MODE]. This allows loop-back modes to
DMA data from one memory location to another while data is converted to a specific serial format.
The SCC operations are asynchronous with the core and can be synchronous or asynchronous with other
SCCs. Each clock can be supplied from the internal baud rate generator bank, DPLL output, or external
pins.
The SCC can work with the time-slot assigner (TSA) or nonmultiplexed serial interface (NMSI) and
supports modem lines with the general-purpose I/O pins. Data can be transferred either the msb or lsb first
in each octet.
24.1 Features
The following list summarizes the main features of the SCC in transparent mode:
•
•
•
•
•
•
Flexible buffers
Automatic SYNC detection on receive
CRCs can be sent and received
Reverse data mode
Another protocol can be performed on the other half of the SCC
MC68360-compatible SYNC options
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
24-1
SCC Transparent Mode
24.2 SCC Transparent Channel Frame Transmission Process
The transparent transmitter is designed to work almost no intervention from the core. When the core
enables the SCC transmitter in transparent mode, it starts sending idles, which are logic high or encoded
ones, as programmed in GSMR_L[TEND]. The SCC polls the first BD in the TxBD table. When there is
a message to send, the SCC fetches data from memory, loads the transmit FIFO, and waits for transmitter
synchronization, which is achieved with CTS or by waiting for the receiver to achieve synchronization,
depending on GSMR_H[TXSY]. Transmission begins when transmitter synchronization is achieved.
When all BD data has been sent, if TxBD[L] is set, the SCC writes the message status bits into the BD,
clears TxBD[R], and sends idles until the next BD is ready. If it is ready, some idles are still sent. The
transmitter resumes sending only after it achieves synchronization.
If TxBD[L] is cleared when the end of the BD is reached, only TxBD[R] is cleared and the transmitter
moves immediately to the next buffer to begin transmission with no gap on the serial line between buffers.
Failure to provide the next buffer in time causes a transmit underrun which sets SCCE[TXE].
In both cases, an interrupt is issued according to TxBD[I]. By appropriately setting TxBD[I] in each BD,
interrupts are generated after each buffer or group of buffers is sent. The SCC then proceeds to the next
BD in the table and any whole number of bytes can be sent. If GSMR_H[REVD] is set, the bit order of
each byte is reversed before being sent; the msb of each octet is sent first.
Setting GSMR_H[TFL] makes the transmit FIFO smaller and reduces transmitter latency, but it can cause
transmitter underruns at higher transmission speeds. An optional CRC, selected in GSMR_H[TCRC], can
be appended to each transparent frame if it is enabled in the TxBD.
When the time-slot assigner (TSA) is used with a transparent-mode channel, synchronization is provided
by the TSA. There is a start-up delay for the transmitter, but delays will always be some whole number of
complete TSA frames. This means that n-byte transmit buffers can be mapped directly into n-byte time
slots in the TSA frames.
24.3 SCC Transparent Channel Frame Reception Process
When the core enables the SCC receiver in transparent mode, it waits to achieve synchronization before
data is received. The receiver can be synchronized to the data by a synchronization pulse or SYNC pattern.
After a buffer is full, the SCC clears RxBD[E] and generates a maskable interrupt if RxBD[I] is set. It
moves to the next RxBD in the table and begins moving data to its buffer. If the next buffer is not available,
SCCE[BSY] signifies a busy signal that can generate a maskable interrupt. The receiver reverts to hunt
mode when an ENTER HUNT MODE command or an error is received. If GSMR_H[REVD] is set, the bit
order of each byte is reversed before it is written to memory.
Setting GSMR_H[RFW] reduces receiver latency by making the receive FIFO smaller, which may cause
receiver overruns at higher transmission speeds. The receiver always checks the CRC of the received
frame, according to GSMR_H[TCRC]. If a CRC is not required, resulting errors can be ignored.
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Freescale Semiconductor
SCC Transparent Mode
24.4 Achieving Synchronization in Transparent Mode
Once the SCC transmitter is enabled for transparent operation, the TxBD is prepared and the transmit FIFO
is preloaded by the SDMA channel, another process must occur before data can be sent. It is called transmit
synchronization. Similarly, once the SCC receiver is enabled for transparent operation in the GSMR and
the RxBD is made empty for the SCC, receive synchronization must occur before data can be received. An
in-line synchronization pattern or an external synchronization signal can provide bit-level control of the
synchronization process when sending or receiving.
24.4.1 Synchronization in NMSI Mode
This section describes synchronization in NMSI mode.
24.4.1.1 In-Line Synchronization Pattern
The transparent channel can be programmed to receive a synchronization pattern. This pattern is defined
in the data synchronization register, DSR; see Section 20.1.3, “Data Synchronization Register (DSR).”
Table 24-1. Receiver SYNC Pattern Lengths of the DSR
Bit Assignments
GSMR_H[SYNL]
Setting
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
00
01
10
11
An external SYNC signal is used instead of the SYNC pattern in the DSR.
4-bit
8-bit
16-bit
If a 4-bit SYNC is selected, reception begins as soon as these four bits are received, beginning with the
first bit following the 4-bit SYNC. The transmitter synchronizes on the receiver pattern if
GSMR_H[RSYN] = 1.
NOTE
The transparent controller does not automatically send the synchronization
pattern; therefore, the synchronization pattern must be included in the
transmit buffer.
24.4.1.2 External Synchronization Signals
If GSMR_H[SYNL] is 0b00, the transmitter uses CTS and the receiver uses CD to begin the sequence.
These signals share two options—pulsing and sampling.
GSMR_H[CDP] and GSMR_H[CTSP] determine whether CD or CTS need to be asserted only once to
begin reception/transmission or whether they must remain asserted for the duration of the transparent
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24-3
SCC Transparent Mode
frame. Pulse operation allows an uninterrupted stream of data. However, use envelope mode to identify
frames of transparent data.
The sampling option determines the delay between CD and CTS being asserted and the resulting action by
the SCC. Assume either that these signals are asynchronous to the data and internally synchronized by the
SCC or that they are synchronous to the data with faster operation. This option allows RTS of one SCC to
be connected to CD of another SCC and to have the data synchronized and bit aligned. It is also an option
to link the transmitter synchronization to the receiver synchronization. Diagrams for the pulse/envelope
24.4.1.2.1
External Synchronization Example
Figure 24-1 shows synchronization using external signals.
PowerQUICC II (A)
PowerQUICC II (B)
TXD
RTS
RXD
CD
BRGOx
RXD
CLKx
TXD
CD
RTS
CLKx
BRGOx
BRGOx
(Output is CLKx Input)
TXD
(Output is RXD Input)
Last Bit of Frame Data
First Bit of Frame Data
RTS
or CRC
(Output is CD Input)
TxBD[L] = 1 Causes Negation of RTS
CD Lost Condition Terminates Reception of Frame
Notes:
1. Each PowerQUICC II generates its own transmit clocks. If the transmit and receive clocks are the same, one
PowerQUICC II can generate transmit and receive clocks for the other PowerQUICC II. For example, CLKx on
PowerQUICC II (B) could be used to clock the transmitter and receiver.
2. CTS should be configured as always asserted in the parallel I/O or connected to ground externally.
3. The required GSMR configurations are DIAG= 00, CTSS=1, CTSP is a “don’t care”, CDS=1, CDP=0, TTX=1, and
TRX=1. REVD and TCRC are application-dependent.
4. The transparent frame contains a CRC if TxBD[TC] is set.
Figure 24-1. Sending Transparent Frames between PowerQUICC IIs
PowerQUICC II(A) and PowerQUICC II(B) exchange transparent frames and synchronize each other
using RTS and CD. However, CTS is not required because transmission begins at any time. Thus, RTS is
connected directly to the other PowerQUICC II CD pin. GSMR_H[RSYN] is not used and transmission
and reception from each PowerQUICC II are independent.
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SCC Transparent Mode
24.4.1.3 Transparent Mode without Explicit Synchronization
If there is no need to synchronize the transparent controller at a specific point, the user can ‘fake’
synchronization in one of the following ways:
•
Tie a parallel I/O pin to the CTS and CD lines. Then, after enabling the receiver and transmitter,
provide a falling edge by manipulating the I/O pin in software.
•
Enable the receiver and transmitter for the SCC in loopback mode and then change
GSMR_L[DIAG] to 0b00 while the transmitter and receiver and enabled.
24.4.2 Synchronization and the TSA
A transparent-mode SCC using the time-slot assigner can synchronize either on a user-defined inline
pattern or by inherent synchronization.
Note that when using the TSA, a newly-enabled transmitter sends from 10 to 15 frames of idles before
sending the actual transparent data due to startup requirements of the TDM. Therefore, when loopback
testing through the TDM, expect to receive several bytes of 0xFF before the actual data.
24.4.2.1 Inline Synchronization Pattern
The receiver can be programmed to begin receiving data into the receive buffers only after a specified data
pattern arrives. To synchronize on an inline pattern:
•
•
•
•
Set GSMR_H[SYNL].
Program the DSR with the desired pattern.
Clear GSMR_H[CDP].
Set GSMR_H[CTSP, CTSS, CDS].
If GSMR_H[TXSY] is also used, the transmitter begins transmission eight clocks after the receiver
achieves synchronization.
24.4.2.2 Inherent Synchronization
Inherent synchronization assumes synchronization by default when the channel is enabled; all data sent
from the TDM to the SCC is received. To implement inherent synchronization:
•
Set GSMR_H[CDP, CDS, CTSP, CTSS].
If these bits are not set, the received bit stream will be bit-shifted. The SCC loses the first received bit
because CD and CTS are treated as asynchronous signals.
24.4.3 End of Frame Detection
An end of frame cannot be detected in the transparent data stream since there is no defined closing flag in
transparent mode. Therefore, if framing is needed, the user must use the CD line to alert the transparent
controller of an end of frame.
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24-5
SCC Transparent Mode
24.5 CRC Calculation in Transparent Mode
The CRC calculations follow the ITU/IEEE standard. The CRC is calculated on the transmitted data
stream; that is, from lsb to msb for non-bit-reversed (GSMR_H[REVD] = 0) and from msb to lsb for
bit-reversed (GSMR_H[REVD] = 1) transmission. The appended CRC is sent msb to lsb. When receiving,
the CRC is calculated as the incoming bits arrive. The optional reversal of data (GSMR_H[REVD] = 1) is
done just before data is stored in memory (after the CRC calculation).
24.6 SCC Transparent Parameter RAM
For transparent mode, the protocol-specific area of the SCC parameter RAM is mapped as in Table 24-2.
Table 24-2. SCC Transparent Parameter RAM Memory Map
1
Offset Name Width
Description
0x 30 CRC_ Long
P
CRC preset for totally transparent. For the 16-bit CRC-CCITT, initialize with 0x0000_FFFF.
For the 32-bit CRC-CCITT, initialize with 0xFFFF_FFFF and for the CRC-16, initialize with
ones (0x0000_FFFF) or zeros (0x0000_0000).
0x 34 CRC_ Long
C
CRC constant for totally transparent receiver. For the 16-bit CRC-CCITT, initialize with
0x0000_F0B8. For the 32-bit CRC-CCITT, CRC_C initialize with 0xDEBB_20E3 and for the
CRC-16, which is normally used with BISYNC, initialize with 0x0000_0000.
1
CRC_P and CRC_C overlap with the CRC parameters for the HDLC-based protocols. However, this
overlap is not detrimental since the CRC constant is used only for the receiver and the CRC preset is used
only for the transmitter, so only one entry is required for each. Thus, the user can choose an HDLC
transmitter with a transparent receiver or a transparent transmitter with an HDLC receiver.
24.7 SCC Transparent Commands
The following transmit and receive commands are issued to the CP command register. Table 24-3
describes transmit commands.
Table 24-3. Transmit Commands
Command
Description
STOP TRANSMIT
After hardware or software is reset and the channel is enabled in the GSMR, the channel is in
transmit enable mode and starts polling the first BD every 64 clocks (or immediately if TODR[TOD]
= 1). STOP TRANSMIT disables frame transmission on the transmit channel. If the transparent
controller receives the command during frame transmission, transmission is aborted after a
maximum of 64 additional bits and the transmit FIFO is flushed. The current TxBD pointer (TBPTR)
is not advanced, no new BD is accessed and no new buffers are sent for this channel. The
transmitter will send idles.
GRACEFUL STOP Stops transmission smoothly, rather than abruptly, in much the same way that the regular STOP
TRANSMIT
TRANSMIT command stops. It stops transmission after the current frame finishes or immediately if no
frame is being sent. A transparent frame is not complete until a BD with TxBD[L] set has its buffer
completely sent. SCCE[GRA] is set once transmission stops; transmit parameters and their BDs can
then be modified. The current TxBD pointer (TBPTR) advances to the next TxBD in the table.
Transmission resumes once TxBD[R] is set and a RESTART TRANSMIT command is issued.
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SCC Transparent Mode
Table 24-3. Transmit Commands (continued)
Description
Command
RESTART
Reenables transmission of characters on the transmit channel. The transparent controller expects
it after a STOP TRANSMIT command is issued (at which point the channel is disabled in SCCM), after
a GRACEFUL STOP TRANSMIT command is issued, or after a transmitter error. The transparent
controller resumes transmission from the current TBPTR in the channel TxBD table.
TRANSMIT
INIT TX
Initializes all transmit parameters in the serial channel parameter RAM to reset state. Issue only
when the transmitter is disabled. INIT TX AND RX PARAMETERS resets receive and transmit
parameters.
PARAMETERS
Table 24-4 describes receive commands.
Table 24-4. Receive Commands
Command
Description
ENTER HUNT
MODE
After hardware or software is reset and the channel is enabled, the channel is in receive enable
mode and uses the first BD in the table. ENTER HUNT MODE forces the transparent receiver to the
current frame and enter hunt mode where the transparent controller waits for the synchronization
sequence. After receiving the command, the current buffer is closed. Further data reception uses
the next BD.
CLOSE RXBD
Forces the SCC to close the RxBD if it is being used and to use the next BD for any subsequently
received data. If the SCC is not receiving data, no action is taken by this command.
INIT RX
Initializes all receive parameters in this serial channel parameter RAM to reset state. Issue only
when the receiver is disabled. INIT TX AND RX PARAMETERS resets receive and transmit parameters.
PARAMETERS
24.8 Handling Errors in the Transparent Controller
The SCC reports message reception and transmission errors using the channel buffer descriptors, the error
Table 24-5. Transmit Errors
Error
Description
Transmitter
Underrun
When this occurs, the channel stops sending the buffer, closes it, sets TxBD[UN], and generates a
TXE interrupt if it is enabled. Transmission resumes after a RESTART TRANSMIT command is received.
Underrun occurs after a transmit frame for which TxBD[L] was not set. In this case, only SCCE[TXE]
is set. Underrun cannot occur between transparent frames.
CTS LostDuring When this occurs, the channel stops sending the buffer, closes it, sets TxBD[CT], and generates the
Message
TXE interrupt if it is enabled. The channel resumes sending after RESTART TRANSMIT is received.
Transmission
Table 24-6 describes receive errors.
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SCC Transparent Mode
Table 24-6. Receive Errors
Description
Error
Overrun
The SCC maintains a receive FIFO. The CPM starts programming the SDMA channel if the buffer
is in external memory and updating the CRC when 8 or 32 bits are received in the FIFO as
determined by GSMR_H[RFW]. If a FIFO overrun occurs, the SCC writes the received byte over the
previously received byte. The previous character and its status bits are lost. Afterwards, the channel
closes the buffer, sets OV in the BD, and generates the RXB interrupt if it is enabled. The receiver
immediately enters hunt mode.
CD Lost During When this occurs, the channel stops receiving messages, closes the buffer, sets RxBD[CD], and
Message
Reception
generates the RXB interrupt if it is enabled. This error has highest priority. The rest of the message
is lost, and no other errors are checked in the message. The receiver immediately enters hunt mode.
24.9 Transparent Mode and the PSMR
The protocol-specific mode register (PSMR) is not used by the transparent controller because all
transparent mode selections are made in the GSMR. If only half of an SCC (transmitter or receiver) is
running the transparent protocol, the other half (receiver or transmitter) can support another protocol. In
such a case, use the PSMR for the non-transparent protocol.
24.10 SCC Transparent Receive Buffer Descriptor (RxBD)
The CPM reports information about the received data for each buffer using an RxBD, closes the current
buffer, generates a maskable interrupt, and starts receiving data into the next buffer after one of the
following occurs:
•
•
•
•
An error is detected.
A full receive buffer is detected.
An ENTER HUNT MODE command is issued.
A CLOSE RXBD command is issued.
Figure 24-2 displays an SCC transparent receive buffer descriptor.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Offset + 0
Offset + 2
Offset + 4
Offset + 6
E
—
W
I
L
F
CM
—
DE
—
NO
—
CR
OV
CD
Data Length
Rx Buffer Pointer
Figure 24-2. SCC Transparent Receive Buffer Descriptor (RxBD)
Table 24-7 describes RxBD status and control fields.
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SCC Transparent Mode
Table 24-7. SCC Transparent RxBD Status and Control Field
Descriptions
Bits
Name
E
Description
0
Empty.
0 The buffer is full or stopped receiving data because an error occurred. The core can read or write
to any fields of this RxBD. The CPM does not use this BD when RxBD[E] is zero.
1 The buffer is not full. This RxBD and buffer are owned by the CPM. Once E is set, the core should
not write any fields of this RxBD.
1
2
—
Reserved, should be cleared.
W
Wrap (final BD in table).
0
Not the last BD in the table.
1 Last BD in the table. After this buffer is used, the CPM receives data into the first BD that RBASE
points to. The number of BDs in this table is determined only by RxBD[W] and overall space
constraints of the dual-port RAM.
3
4
I
Interrupt.
0 No interrupt is generated after this buffer is used.
1 When this buffer is closed by the transparent controller, the SCCE[RXB] is set. SCCE[RXB] can
cause an interrupt if it is enabled.
L
Last in frame. Set by the transparent controller when this buffer is the last in a frame, which occurs
when CD is negated (if GSMR_H[CDP] = 0) or an error is received. If an error is received, one or
more of RxBD[OV, CD, DE] are set. Note that the SCC transparent controller writes the number of
buffer (not frame) octets to the last BD’s data length field.
0 Not the last buffer in a frame.
1 Last buffer in a frame.
5
6
F
First in frame. The transparent controller sets F when this buffer is the first in the frame:
0 Not the first buffer in a frame.
1 First buffer in a frame.
CM
Continuous mode.
0 Normal operation.
1 The CPM does not clear RxBD[E] after this BD is closed, letting the buffer be overwritten when
the CPM next accesses this BD. However, RxBD[E] is cleared if an error occurs during reception,
regardless of how CM is set.
7
8
—
Reserved, should be cleared.
DE
DPLL error. Set by the transparent controller when a DPLL error occurs as this buffer is received. In
decoding modes, where a transition is promised every bit, DE is set when a missing transition
occurs. If a DPLL error occurs, no other error checking is performed.
9–10
11
—
NO
—
Reserved, should be cleared.
Rx non-octet. Set when a frame containing a number of bits not exactly divisible by eight is received.
Reserved, should be cleared.
12
13
CR
CRC error indication bits. Indicates that this frame contains a CRC error. The received CRC bytes
are always written to the receive buffer. CRC checking cannot be disabled, but it can be ignored.
14
15
OV
CD
Overrun. Indicates that a receiver overrun occurred during buffer reception.
Carrier detect lost. Indicates when CD is negated during buffer reception.
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24-9
SCC Transparent Mode
Data length and buffer pointer fields are described in Section 20.2, “SCC Buffer Descriptors (BDs).” The
Rx buffer pointer must be divisible by four, unless GSMR_H[RFW] is set to 8 bits wide, in which case the
pointer can be even or odd. The buffer can reside in internal or external memory.
24.11 SCC Transparent Transmit Buffer Descriptor (TxBD)
Data is sent to the CPM for transmission on an SCC channel by arranging it in buffers referenced by the
TxBD table. The CPM uses BDs to confirm transmission or indicate error conditions so the processor
knows buffers have been serviced. Prepare status and control bits before transmission; they are set by the
CPM after the buffer is sent.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Offset + 0
Offset + 2
Offset + 4
Offset + 6
R
—
W
I
L
TC
CM
—
UN
CT
Data Length
Tx Buffer Pointer
Figure 24-3. SCC Transparent Transmit Buffer Descriptor (TxBD)
Table 24-8 describes SCC Transparent TxBD status and control fields.
Table 24-8. SCC Transparent TxBD Status and Control Field Descriptions
Bit
Name Description
0
R
Ready.
0 The buffer is not ready for transmission. The BD and buffer can be updated. The CPM clears R
after the buffer is sent or after an error is encountered.
1 The user-prepared buffer is not sent yet or is being sent. This BD cannot be updated while R = 1.
1
2
—
Reserved, should be cleared.
W
Wrap (final BD in table).
0 Not the last BD in the table.
1 Last BD in the table. After this buffer is used, the CPM receives incoming data into the first BD
that TBASE points to. The number of TxBDs in this table is determined only by TxBD[W] and
overall space constraints of the dual-port RAM.
3
4
I
Interrupt. Note that clearing this bit does not disable all SCCE[TXE] events.
0 No interrupt is generated after this buffer is serviced.
1 When the CPM services this buffer, SCCE[TXB] or SCCE[TXE] is set. These bits can cause
interrupts if they are enabled.
L
Last in message.
0 The last byte in the buffer is not the last byte in the transmitted transparent frame. Data from the
next transmit buffer is sent immediately after the last byte of this buffer.
1 The last byte in the buffer is the last byte in the transmitted transparent frame. After this buffer is
sent, the transmitter requires synchronization before the next buffer is sent.
5
TC
Transmit CRC.
0 No CRC sequence is sent after this buffer.
1 A frame check sequence defined by GSMR_H[TCRC] is sent after the last byte of this buffer.
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SCC Transparent Mode
Table 24-8. SCC Transparent TxBD Status and Control Field Descriptions (continued) (continued)
Bit
Name
CM
Description
6
Continuous mode.
0 Normal operation.
1 The CPM does not clear TxBD[R] after this BD is closed, so the buffer is automatically resent
when the CPM accesses this BD next. However, TxBD[R] is cleared if an error occurs during
transmission, regardless of how CM is set.
7–13
14
—
UN
CT
Reserved, should be cleared.
Underrun. Set when the SCC encounters a transmitter underrun condition while sending the buffer.
CTS lost. Indicates the CTS was lost during frame transmission.
15
Data length and buffer pointer fields are described in Section 20.2, “SCC Buffer Descriptors (BDs).”
Although it is never modified by the CP, data length should be greater than zero. The buffer pointer can be
even or odd and can reside in internal or external memory.
24.12 SCC Transparent Event Register (SCCE)/Mask Register (SCCM)
When the SCC is in transparent mode, the SCC event register (SCCE) functions as the transparent event
register to report events recognized by the transparent channel and to generate interrupts. When an event
is recognized, the transparent controller sets the corresponding SCCE bit. Interrupts are enabled by setting,
and masked by clearing, the equivalent bits in the transparent mask register (SCCM).
Event bits are reset by writing ones; writing zeros has no effect. All unmasked bits must be reset before
the CP clears the internal interrupt request to the SIU interrupt controller. Figure 24-4 shows the event and
mask registers.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Field
Reset
R/W
—
DCC
—
GRA
—
TXE
—
BSY TXB RXB
0000_0000_0000_0000
R/W
Addr
Figure 24-4. SCC Transparent Event Register (SCCE)/Mask Register (SCCM)
Table 24-9 describes SCCE/SCCM fields.
1
Table 24-9. SCCE/SCCM Field Descriptions
Description
Reserved, should be cleared. Refer to note 1 below.
Bit
Name
0–4
5
—
DCC DPLL CS changed. Set when the DPLL-generated carrier sense status changes (valid only when
the DPLL is used). Real-time status can be read in SCCS. This is not the CD status mentioned
elsewhere.
6–7
—
Reserved, should be cleared. Refer to note 1 below.
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SCC Transparent Mode
1
Table 24-9. SCCE/SCCM Field Descriptions (continued)
Description
Bit
Name
8
GRA Graceful stop complete. Set when a graceful stop initiated by completes as soon as the transmitter
finishes any frame in progress when the GRACEFUL STOP TRANSMIT command was issued.
Immediately if no frame was in progress when the command was issued.
9–10
11
—
Reserved, should be cleared. Refer to note 1 below.
TXE Tx error. Set when an error occurs on the transmitter channel.
Reserved, should be cleared. Refer to note 1 below.
12
—
13
BSY Busy condition. Set when a byte or word is received and discarded due to a lack of buffers. The
receiver resumes reception after it gets an ENTER HUNT MODE command.
14
15
TXB Tx buffer. Set no sooner than when the last bit of the last byte of the buffer begins transmission,
assuming L is set in the TxBD. If it is not, TXB is set when the last byte is written to the transmit FIFO.
RXB Rx buffer. Set when a complete buffer was received on the SCC channel, no sooner than two serial
clocks after the last bit of the last byte in which the buffer is received on RXD.
1
Reserved bits in the SCCE should not be masked in the SCCM register.
24.13 SCC Status Register in Transparent Mode (SCCS)
The SCC status register (SCCS) allows monitoring of real-time status conditions on the RXD line. The
real-time status of CTS and CD are part of the parallel I/O.
0
1
2
3
4
5
6
7
Field
Reset
R/W
—
CS
—
0000_0000
R
Addr
Figure 24-5. SCC Status Register in Transparent Mode (SCCS)
Table 24-10 describes SCCS fields.
Table 24-10. SCCS Field Descriptions
Bit
Name
Description
0–5
6
—
Reserved, should be cleared.
CS
Carrier sense (DPLL). Shows the real-time carrier sense of the line as determined by the DPLL.
0 The DPLL does not sense a carrier.
1 The DPLL senses a carrier.
7
—
Reserved, should be cleared.
24.14 SCC2 Transparent Programming Example
The following initialization sequence enables the transmitter and receiver, which operate independently of
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SCC Transparent Mode
The transmit and receive clocks are externally provided to PowerQUICC II(B) using CLK3. SCC2 is used.
The transparent controller is configured with the RTS2 and CD2 pins active and CTS2 is configured to be
grounded internally. A 16-bit CRC-CCITT is sent with each transparent frame. The FIFOs are configured
for fast operation.
1. Configure port D pins to enable TXD2 and RXD2. Set PPARD[27,28] and PDIRD[27] and clear
PDIRD[28] and PSORD[27,28].
2. Configure ports C and D pins to enable RTS2, CTS2 and CD2. Set PPARD[26], PPARC[12,13]
and PDIRD[26] and clear PDIRC[12,13], PSORC[12,13] and PSORD[26].
3. Configure port C pin 29 to enable the CLK3 pin. Set PPARC[29] and clear PDIRC[29] and
PSORC[29].
4. Connect CLK3 to SCC2 using the CPM mux. Program CMXSCR[R2CS] and CMXSCR[T2CS]
to 0b110.
5. Connect the SCC2 to the NMSI and clear CMXSCR[SC2].
6. Write RBASE with 0x0000 and TBASE with 0x0008 in the SCC2 parameter RAM to point to one
RxBD at the beginning of dual-port RAM followed by one TxBD.
7. Write 0x04A1_0000 to the CPCR to execute INIT RX AND TX PARAMETERS for SCC2.
8. Write 0x0041 to the CPCR to execute INIT RX AND TX PARAMETERS for SCC2.
9. Write RFCR and TFCR with 0x10 for normal operation.
10. Write MRBLR with the maximum number of bytes per receive buffer and assume 16-bytes, so
MRBLR = 0x0010.
11. Write CRC_P with 0x0000_FFFF to comply with the 16-bit CRC-CCITT.
12. Write CRC_C with 0x0000_F0B8 to comply with the 16-bit CRC-CCITT.
13. Initialize the RxBD. Assume the Rx buffer is at 0x0000_1000 in main memory. Write 0xB000 to
RxBD[Status and Control], 0x0000 to RxBD[Data Length] (optional), and 0x0000_1000 to
RxBD[Buffer Pointer].
14. Initialize the TxBD. Assume the Tx buffer is at 0x0000_2000 in main memory and contains five
8-bit characters. Write 0xBC00 to TxBD[Status and Control], 0x0005 to TxBD[Data Length], and
0x0000_2000 to TxBD[Buffer Pointer].
15. Write 0xFFFF to SCCE to clear any previous events.
16. Write 0x0013 to SCCM to enable the TXE, TXB, and RXB interrupts.
17. Write 0x0040_0000 to the SIU interrupt mask register low (SIMR_L) so SCC2 can generate a
system interrupt. Initialize SIU interrupt pending register low (SIPNR_L) by writing
0xFFFF_FFFF to it.
18. Write 0x0000_1980 to GSMR_H2 to configure the transparent channel.
19. Write 0x0000_0000 to GSMR_L2 to configure CTS and CD to automatically control transmission
and reception (DIAG bits). Normal operation of the transmit clock is used. Note that the transmitter
(ENT) and receiver (ENR) are not enabled yet.
20. Write 0x0000_0030 to GSMR_L2 to enable the SCC2 transmitter and receiver. This additional
write ensures that the ENT and ENR bits are enabled last.
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24-13
SCC Transparent Mode
NOTE
After 5 bytes are sent, the Tx buffer is closed and after 16 bytes are received
the Rx buffer is closed. Any data received after 16 bytes causes a busy
(out-of-buffers) condition since only one RxBD is prepared.
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Freescale Semiconductor
Chapter 25
SCC Ethernet Mode
The Ethernet IEEE 802.3 protocol is a widely used LAN protocol based on the carrier sense multiple
access/collision detect (CSMA/CD) approach. Because Ethernet and IEEE 802.3 protocols are similar and
can coexist on the same LAN, both are referred to as Ethernet in this manual, unless otherwise noted.
Figure 25-1 shows Ethernet and IEEE 802.3 frame structure.
Frame Length is 64–1518 Bytes
Start Frame
Delimiter
Destination
Address
Source
Address
Type/
Length
Frame Check
Sequence
Preamble
7 Bytes
Data
1 Byte
6 Bytes
6 Bytes
2 Bytes
46–1500 Bytes
4 Bytes
NOTE: The lsb of each octet is transmitted first.
Figure 25-1. Ethernet Frame Structure
The frame begins with a 7-byte preamble of alternating ones and zeros. Because the frame is Manchester
encoded, the preamble gives receiving stations a known pattern on which to lock. The start frame delimiter
follows the preamble, signifying the beginning of the frame. The 48-bit destination address is next,
followed by the 48-bit source address. Original versions of the IEEE 802.3 specification allowed 16-bit
addressing, but this addressing has never been widely used and is not supported.
The next field is the Ethernet type field/IEEE 802.3 length field. The type field signifies the protocol used
in the rest of the frame and the length field specifies the length of the data portion of the frame. For Ethernet
and IEEE 802.3 frames to coexist on the same LAN, the length field of the frame must always be different
from any type fields used in Ethernet. This limits the length of the data portion of the frame to 1,500 bytes
and total frame length to 1,518 bytes. The last 4 bytes of the frame are the frame check sequence (FCS), a
standard 32-bit CCITT-CRC polynomial used in many protocols.
When a station needs to transmit, it checks for LAN activity. When the LAN is silent for a specified period,
the station starts sending. At that time, the station continually checks for collisions on the LAN; if one is
found, the station forces a jam pattern (all ones) on its frame and stops sending. Most collisions occur close
to the beginning of a frame. The station waits a random period of time, called a backoff, before trying to
retransmit. Once the backoff time expires, the station waits for silence on the LAN before retransmitting,
which is called a retry. If the frame cannot be sent within 15 retries, an error occurs
10-Mbps Ethernet transmits at 0.8 µs per byte. The preamble plus start frame delimiter is sent in 6.4 µs.
The minimum 10-Mbps Ethernet interframe gap is 9.6 µs and the slot time is 52 µs.
25.1 Ethernet on the PowerQUICC II
Setting GSMR[MODE] to 0b1100 selects Ethernet. The SCC performs the full set of IEEE 802.3/Ethernet
CSMA/CD media access control and channel interface functions.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
25-1
SCC Ethernet Mode
60x Bus
Slot Time
and Defer
Counter
Control
Registers
RCLK
TCLK
Clock
Generator
Peripheral Bus
Internal Clocks
REJECT
RSTRT
RTS = TENA
Rx
Data
FIFO
Tx
Data
FIFO
Receiver
Control
Unit
Transmitter
Control
Unit
CD = RENA
CTS = CLSN
CD = RENA
CTS = CLSN
TXD
Shifter
Shifter
RXD
Figure 25-2. Ethernet Block Diagram
The PowerQUICC II Ethernet controller requires an external serial interface adaptor (SIA) and transceiver
function to complete the interface to the media.
Although the PowerQUICC II contains DPLLs that allow Manchester encoding and decoding, these
DPLLs were not designed for Ethernet rates. Therefore, the PowerQUICC II Ethernet controller bypasses
the on-chip DPLLs and uses the external system interface adaptor on the EEST instead. The on-chip DPLL
cannot be used for low-speed (1-Mbps) Ethernet either because it cannot properly detect start-of-frame or
end-of-frame.
Note that the CPM of the PowerQUICC II requires a minimum system clock frequency of 24 MHz to
support Ethernet.
25.2 Features
The following list summarizes the main features of the SCC in Ethernet mode:
•
•
Performs MAC layer functions of Ethernet and IEEE 802.3
Performs framing functions
— Preamble generation and stripping
— Destination address checking
— CRC generation and checking
— Automatically pads short frames on transmit
— Framing error (dribbling bits) handling
Full collision support
•
— Enforces the collision (jamming)
— Truncated binary exponential backoff algorithm for random wait
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Freescale Semiconductor
SCC Ethernet Mode
— Two nonaggressive backoff modes
— Automatic frame retransmission (until the attempt limit is reached)
— Automatic discard of incoming collided frames
— Delay transmission of new frames for specified interframe gap
Maximum 10 Mbps bit rate
•
•
•
•
•
•
Optional full-duplex support
Back-to-back frame reception
Detection of receive frames that are too long
Multibuffer data structure
Supports 48-bit addresses in three modes
— Physical: One 48-bit address recognized or 64-bin hash table for physical addresses
— Logical: 64-bin group address hash table plus broadcast address checking
— Promiscuous: Receives all addresses, but discards frame if REJECT is asserted
External content-addressable memory (CAM) support on serial bus interfaces
Up to eight parallel I/O pins can be sampled and appended to any frame
Optional heartbeat indication
•
•
•
•
Transmitter network management and diagnostics
— Lost carrier sense
— Underrun
— Number of collisions exceeded the maximum allowed
— Number of retries per frame
— Deferred frame indication
— Late collision
•
Receiver network management and diagnostics
— CRC error indication
— Nonoctet alignment error
— Frame too short
— Frame too long
— Overrun
— Busy (out of buffers)
•
•
Error counters
— Discarded frames (out of buffers or overrun occurred)
— CRC errors
— Alignment errors
Internal and external loopback mode
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25-3
SCC Ethernet Mode
25.3 Connecting the PowerQUICC II to Ethernet
The basic interface to the external SIA chip consists of the following Ethernet signals:
•
•
Receive clock (RCLK)—a CLKx signal routed through the bank of clocks on the PowerQUICC II.
Transmit clock (TCLK)—a CLKx signal routed through the bank of clocks on the PowerQUICC II.
Note that RCLK and TCLK should not be connected to the same CLKx since the SIA provides
separate transmit and receive clock signals.
•
•
Transmit data (TXD)—the PowerQUICC II TXD signal.
Receive data (RXD)—the PowerQUICC II RXD signal.
The following signals take on different functionality when the SCC is in Ethernet mode:
•
Transmit enable (TENA)—RTS becomes TENA. The polarity of TENA is active high, whereas the
polarity of RTS is active low.
•
•
Receive enable (RENA)—CD becomes RENA.
Collision (CLSN)—CTS becomes CLSN. The carrier sense signal is referenced in Ethernet
descriptions because it indicates when the LAN is in use. Carrier sense is defined as the logical OR
of RENA and CLSN.
Figure 25-3. shows the basic components and signals required to make an Ethernet connection between
the PowerQUICC II and EEST.
PowerQUICC II
EEST
MC68160
SCC
TXD
Tx
RJ-45
D-15
TENA (RTS)
TCLK (CLKx)
RXD
TENA
TCLK
Rx
Twisted
Pair
Passive
Passive
RENA (CD)
RCLK (CLKx)
CLSN (CTS)
RENA
RCLK
CLSN
AUI
Parallel I/O
Loop
Stored in Receive Buffer
Stored in Transmit Buffer
Start Frame
Delimiter
Destination
Address
Source
Address
Type/
Length
Frame Check
Sequence
Preamble
7 Bytes
Data
46–1500 Bytes
(Pads)
1 Byte
6 Bytes
6 Bytes
2 Bytes
4 Bytes
NOTE: Short Tx frames are padded automatically by the PowerQUICC II.
Figure 25-3. Connecting the PowerQUICC II to Ethernet
The EEST has similar names for its connection to the above seven PowerQUICC II signals. The EEST also
provides a loopback input so the PowerQUICC II can perform external loopback testing, which can be
controlled by any available PowerQUICC II parallel I/O signal. The passive components needed to
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
25-4
Freescale Semiconductor
SCC Ethernet Mode
connect to AUI or twisted-pair media are external to the EEST. The MC68160 documentation describes
EEST connection circuits.
The PowerQUICC II uses SDMA channels to store bytes received after the start frame delimiter in system
memory. When sending, provide the destination address, source address, type/length field, and the transmit
data. To meet minimum frame requirements, the PowerQUICC II pads frames with fewer than 46 bytes in
the data field and appends the FCS to the frame.
25.4 SCC Ethernet Channel Frame Transmission
The Ethernet transmitter works with almost no core intervention. When the core enables the transmitter,
the SCC polls the first TxBD in the table every 128 serial clocks. Setting TODR[TOD] lets the next frame
be sent without waiting for the next poll.
To begin transmission, the SCC in Ethernet mode (called the Ethernet controller) fetches data from the
buffer, asserts TENA to the EEST, and starts sending the preamble sequence, the start frame delimiter, and
frame information. If the line is busy, it waits for carrier sense to remain inactive for 6.0 µs, at which point
it waits an additional 3.6 µs before it starts sending (9.6 µs after carrier sense originally became inactive).
If a collision occurs during frame transmission, the Ethernet controller follows a specified backoff
procedure and tries to retransmit the frame until the retry limit threshold is reached. The Ethernet controller
stores the first 5 to 8 bytes of the transmit frame in dual-port RAM so they need not be retrieved from
system memory in case of a collision. This improves bus usage and latency when the backoff timer output
requires an immediate retransmission. If a collision occurs during frame transmission, the controller
returns to the first buffer for a retransmission. The only restriction is that the first buffer must contain at
least 9 bytes.
NOTE
If an Ethernet frame consists of multiple buffers, do not reuse the first BD
until the CPM clears the R bit of the last BD.
When the end of the current BD is reached and TxBD[L] is set, the FCS bytes are appended (if the TC bit
is set in the TxBD), and TENA is negated. This notifies the EEST of the need to generate the illegal
Manchester encoding that marks the end of an Ethernet frame. After CRC transmission, the Ethernet
controller writes the frame status bits into the BD and clears the R bit. When the end of the current BD is
reached and the L bit is not set, only the R bit is cleared.
In either mode, whether an interrupt is issued depends on how the I bit is set in the TxBD. The Ethernet
controller proceeds to the next TxBD. Transmission can be interrupted after each frame, after each buffer,
or after a specific buffer is sent. The Ethernet controller can pad characters to short frames. If TxBD[PAD]
is set, the frame is padded up to the value of the minimum frame length register (MINFLR).
To send expedited data before previously linked buffers or for error situations, the GRACEFUL STOP
TRANSMIT command can be used to rearrange transmit queue before the CPM sends all the frames; the
Ethernet controller stops immediately if no transmission is in progress or it will keep sending until the
current frame either finishes or terminates with a collision. When the Ethernet controller receives a
RESTART TRANSMIT command, it resumes transmission. The Ethernet controller sends bytes
least-significant bit first.
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25-5
SCC Ethernet Mode
25.5 SCC Ethernet Channel Frame Reception
The Ethernet receiver handles address recognition and performs CRC, short frame, maximum DMA
transfer, and maximum frame length checking with almost no core intervention. When the core enables the
Ethernet receiver, it enters hunt mode as soon as RENA is asserted while CLSN is negated. In hunt mode,
as data is shifted into the receive shift register one bit at a time, the register contents are compared to the
contents of the SYN1 field in the data synchronization register (DSR). This compare function becomes
valid a certain number of clocks after the start of the frame (depending on PSMR[NIB]). If the two are not
equal, the next bit is shifted in and the comparison is repeated. If a double-zero or double-one fault is
detected between bits 14 to 21 from the first received preamble bit, the frame is rejected. If a double-zero
fault is detected after 21 bits from the first received preamble bit and before detection of the start frame
delimiter (SFD), the frame is also rejected. When the incoming pattern is not rejected and matches the
DSR, the SFD has been detected; hunt mode is terminated and character assembly begins.
When the receiver detects the first bytes of the frame, the Ethernet controller performs address recognition
on the frame. The receiver can receive physical (individual), group (multicast), and broadcast addresses.
Ethernet receive frame data is not written to memory until the internal address recognition process
completes, which improves bus usage with frames not addressed to this station.
If a match is found, the Ethernet controller fetches the next RxBD and, if it is empty, starts transferring the
incoming frame to the RxBD associated data buffer. If a collision is detected during the frame, the RxBDs
associated with this frame are reused. Thus, there will be no collision frames presented to you except late
collisions, which indicate serious LAN problems. When the data buffer has been filled, the Ethernet
controller clears the E bit in the RxBD and generates an interrupt if the I bit is set. If the incoming frame
exceeds the length of the data buffer, the Ethernet controller fetches the next RxBD in the table and, if it
is empty, continues transferring the rest of the frame to this buffer. The RxBD length is determined by
MRBLR in the SCC general-purpose parameter RAM, which should be at least 64 bytes.
During reception, the Ethernet controller checks for a frame that is either too short or too long. When the
frame ends, the receive CRC field is checked and written to the buffer. The data length written to the last
BD in the Ethernet frame is the length of the entire frame and it enables the software to correctly recognize
the frame-too-long condition.
The Ethernet controller then sets the L bit in the RxBD, writes the other frame status bits into the RxBD,
and clears the E bit. Then it generates a maskable interrupt, which indicates that a frame has been received
and is in memory. The Ethernet controller then waits for a new frame. It receives serial data
least-significant bit first.
25.6 The Content-Addressable Memory (CAM) Interface
The Ethernet controller has one option for connecting to an external CAM—a serial interface. The reject
signal (REJECT) is used to signify that the current frame should be discarded. The PowerQUICC II’s
internal address recognition logic can be used in combination with an external CAM. See Section 25.10,
The PowerQUICC II outputs a receive start (RSTRT) signal when the start frame delimiter is recognized.
This signal is asserted for one bit time on the second destination address bit. The CAM control logic uses
RSTRT (in combination with the RXD and RCLK signals) to store the destination or source address and
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25-6
Freescale Semiconductor
SCC Ethernet Mode
generate writes to the CAM for address recognition. In addition, the RENA signal supplied from the SIA
can be used to abort the comparison if a collision occurs on the receive frame.
After the comparison, the CAM control logic asserts the receive reject signal (REJECT), if the current
receive frame is rejected. The PowerQUICC II’s Ethernet controller then immediately stops writing data
to system memory and reuses the buffer(s) for the next frame. If the CAM accepts the frame, the CAM
control logic does nothing (REJECT is not asserted). However, if REJECT is asserted, it must be done
prior to the end of the receive frame.
NOTE
The bus atomicity mechanism for CAM accesses may not function correctly
when the CPM performs a DMA access to an external CAM device. This
only impacts systems in which multiple CPMs will access the CAM.
25.7 SCC Ethernet Parameter RAM
Table 25-1. SCC Ethernet Parameter RAM Memory Map
1
Offset
Name
Width
Description
0x30
0x34
0x38
0x3C
0x40
C_PRES
C_MASK
CRCEC
ALEC
Word Preset CRC. For the 32-bit CRC-CCITT, initialize to 0xFFFFFFFF.
Word Constant mask for CRC. For the 32-bit CRC-CCITT, initialized to 0xDEBB20E3.
Word CRC error, alignment error, and discard frame counters. The CPM maintains
32
these 32-bit (modulo 2 ) counters that can be initialized while the channel is
disabled. CRCEC is incremented for each received frame with a CRC error, not
including frames not addressed to the controller, frames received in the
out-of-buffers condition, frames with overrun errors, or frames with alignment
errors. ALEC is incremented for frames received with dribbling bits, but does not
include frames not addressed to the controller, frames received in the
out-of-buffers condition, or frames with overrun errors. DISFC is incremented for
frames discarded because of the out-of-buffers condition or an overrun error. The
CRC does not have to be correct for DISFC to be incremented.
DISFC
0x44
0x46
PADS
Hword Short frame PAD character. Write the pad character pattern to be sent when short
frame padding is implemented into PADS. The pattern may be of any value, but
both the high and low bytes should be the same.
RET_LIM
Hword Retry limit. Number of retries (typically 15 decimal) that can be made to send a
frame. An interrupt can be generated if the limit is reached.
0x48
0x4A
RET_CNT
Hword Retry limit counter. Temporary down-counter for counting retries.
MFLR
Hword Maximum frame length register (Typically 1518 decimal). The Ethernet controller
checks the length of an incoming Ethernet frame against this limit. If it is
exceeded, the rest of the frame is discarded and LG is set in the last BD of that
frame. The controller reports frame status and length in the last BD. MFLR is
defined as all in-frame bytes between the start frame delimiter and the end of the
frame.
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25-7
SCC Ethernet Mode
Table 25-1. SCC Ethernet Parameter RAM Memory Map (continued)
1
Offset
Name
Width
Description
0x4C
MINFLR
Hword Minimum frame length register. The Ethernet controller checks the incoming
frame’s length against MINFLR (typically 64 decimal). If the received frame is
smaller than MINFLR, it is discarded unless PSMR[RSH] is set, in which case,
SH is set in the last BD for the frame. For transmitting a frame that is too short,
the Ethernet controller pads the frame to make it MINFLR bytes long, depending
on how PAD is set in the TxBD and on the PAD value in the parameter RAM.
0x4E
0x50
MAXD1
MAXD2
Hword Max DMAn length register. Gives the option to stop system bus writes after a
frame exceeds a certain size. However, this value is valid only if an address
Hword
match is found. The Ethernet controller checks the length of an incoming Ethernet
frame against this user-defined value (usually 1520 decimal). If this limit is
exceeded, the rest of the incoming frame is discarded. The Ethernet controller
waits until the end of the frame or until MFLR bytes are received and reports the
frame status and the frame length in the last RxBD.
MAXD1 is used when an address matches an individual or group address.
MAXD2 is used in promiscuous mode when no address match is detected. In a
monitor station, MAXD2 can be much less than MAXD1 to receive entire frames
addressed to this station, but only the headers of the other frames are received.
0x52
MAXD
Hword Rx max DMA.
0x54
0x56
0x58
0x5A
0x5C
0x5E
0x60
0x64
0x68
0x6C
0x70
0x72
0x74
0x76
0x78
DMA_CNT
MAX_B
Hword Rx DMA counter. A temporary down-counter used to track frame length.
Hword Maximum BD byte count.
GADDR1
GADDR2
GADDR3
GADDR4
Hword Group address filter 1–4. Used in the hash table function of the group addressing
mode. Write zeros to these values after reset and before the Ethernet channel is
enabled to disable all group hash address recognition functions. The SET GROUP
ADDRESS command is used to enable the hash table.
TBUF0_DATA0 Word Save area 0—current frame.
TBUF0_DATA1 Word Save area 1—current frame.
TBUF0_RBA0 Word
TBUF0_CRC
Word
TBUF0_BCNT Hword
PADDR1_H
PADDR1_M
PADDR1_L
P_PER
Hword The 48-bit individual address of this station into this location. PADDR1_L is the
lowest order hword and PADDR1_H is the highest order hword.
Hword Persistence. Lets the Ethernet controller be less aggressive after a collision.
Normally, 0x0000. It can be a value between 1 and 9 (1 is most aggressive). The
value is added to the retry count in the backoff algorithm to reduce the chance of
transmission on the next time slot.
Note: Using P_PER is fully allowed in the Ethernet/802.3 specifications. A less
aggressive backoff algorithm used by multiple stations on a congested Ethernet
LAN increases overall throughput by reducing the chance of collision.
PSMR[SBT] offers another way to reduce the aggressiveness of the Ethernet
controller.
0x7A
RFBD_PTR
Hword Rx first BD pointer.
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25-8
Freescale Semiconductor
SCC Ethernet Mode
Table 25-1. SCC Ethernet Parameter RAM Memory Map (continued)
1
Offset
Name
Width
Description
0x7C
0x7E
0x80
0x84
0x88
0x8C
0x90
0x92
0x94
0x96
0x98
0x9A
0x9C
0x9E
0x A0
0x A2
TFBD_PTR
TLBD_PTR
Hword Tx first BD pointer.
Hword Tx last BD pointer.
TBUF1_DATA0 Word Save area 0—next frame.
TBUF1_DATA1 Word Save area 1—next frame.
TBUF1_RBA0 Word
TBUF1_CRC
Word
TBUF1_BCNT Hword
TX_LEN
IADDR1
Hword Tx frame length counter.
Hword Individual address filter 1–4. Used in the hash table function of the individual
addressing mode. Zeros can be written to these values after reset and before the
Ethernet channel is enabled to disable all individual hash address recognition
functions. The SET GROUP ADDRESS command is used to enable the hash table.
IADDR2
IADDR3
IADDR4
BOFF_CNT
TADDR_H
TADDR_M
TADDR_L
Hword Backoff counter.
Hword Allows addition and deletion of addresses from individual and group hash tables.
After placing an address in TADDR, issue a SET GROUP ADDRESS command.
TADDR_L (temp address low) is the least-significant half word and TADDR_H
(temp address high) is the most-significant half word.
1
25.8 Programming the Ethernet Controller
The core configures the SCC to operate as an Ethernet controller by setting GSMR[MODE] to 0b1100.
Receive and transmit errors are reported through RxBD and TxBD. Several GSMR fields must be
programmed to special values for Ethernet. Set DSR[SYN1] to 0x55 and DSR[SYN2] to 0xD5. The 6
bytes of preamble programmed in the GSMR, in combination with the DSR programming, causes 8 bytes
of preamble on transmit (including the 1-byte start delimiter with the value 0xD5).
25.9 SCC Ethernet Commands
transmit commands.
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25-9
SCC Ethernet Mode
Command
Table 25-2. Transmit Commands
Description
STOP
When used with the Ethernet controller, this command violates a specific behavior of an Ethernet/IEEE
802.3 station. It should not be used.
TRANSMIT
GRACEFUL
STOP
Used to ensure that transmission stops smoothly after the current frame finishes or has a collision.
SCCE[GRA] is set once transmission stops, at which point Ethernet transmit parameters and their BDs
can be updated. TBPTR points to the next TxBD. Transmission begins once the R bit of the next BD is
set and a RESTART TRANSMIT command is issued.
TRANSMIT
Note that if GRACEFUL STOP TRANSMIT is issued and the current frame ends in a collision, TBPTR points
to the start of the collided frame with the R bit still set in the BD. The frame looks as if it was never sent.
RESTART
TRANSMIT
Enables transmission of characters on the transmit channel. The Ethernet controller expects it after a
GRACEFUL STOP TRANSMIT command is issued or a transmitter error. The Ethernet controller resumes
transmission from the current TBPTR in the channel TxBD table.
INIT TX
Initializes transmit parameters in this serial channel parameter RAM to reset state. Issue only when the
PARAMETERS transmitter is disabled. INIT TX and RX PARAMETERS resets both transmit and receive parameters.
Table 25-3 describes receive commands.
Table 25-3. Receive Commands
Command
Description
ENTER HUNT After hardware or software is reset and the channel is enabled in GSMR_L, the channel is in receive
MODE
enable mode and uses the first BD in the table. The receiver then enters hunt mode, waiting for an
incoming frame. The ENTER HUNT MODE command is generally used to force the Ethernet receiver to
stop receiving the current frame and enter hunt mode, in which the Ethernet controller continually scans
the input data stream for a transition of carrier sense from inactive to active and then a preamble
sequence followed by the start frame delimiter. After receiving the command, the buffer is closed and
the CRC calculation is reset. The next RxBD is used to receive more frames.
CLOSE RXBD Should not be used with the Ethernet controller.
Initializes receive parameters in this serial channel parameter RAM to their reset state. Issue it only
INIT RX
PARAMETERS when the receiver is disabled. INIT TX and RX PARAMETERS resets receive and transmit parameters.
SET GROUP
ADDRESS
Used to set one of the 64 bits of the four individual/group address hash filter registers. The address to
be added to the hash table should be written to TADDR_L, TADDR_M, and TADDR_H in the parameter
RAM before executing this command. The CP uses an individual address if the I/G bit in the address
stored in TADDR is 0; otherwise, it uses a group address. This command can be executed at any time,
regardless of whether the Ethernet channel is enabled.
To delete an address from the hash table, disable the Ethernet channel, clear the hash table registers,
and execute this command for the remaining addresses. Do not simply clear the channel’s associated
hash table bit because the hash table may have multiple addresses mapped to the same hash table bit.
NOTE
After a CPM reset via CPCR[RST], the Ethernet transmit enable (TENA)
signal defaults to its RTS, active-low functionality. To prevent false TENA
assertions to an external transceiver, configure TENA as an input before
issuing a CPM reset. See step 3 in Section 25.21, “SCC Ethernet
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
25-10
Freescale Semiconductor
SCC Ethernet Mode
25.10 SCC Ethernet Address Recognition
The Ethernet controller can filter received frames based on different addressing types—physical
(individual), group (multicast), broadcast (all-ones group address), and promiscuous. The difference
between an individual address and a group address is determined by the I/G bit in the destination address
In the physical type of address recognition, the Ethernet controller compares the destination address field
of the received frame with the user-programmed physical address in PADDR1. Address recognition can
be performed on multiple individual addresses using the IADDR1–4 hash table.
Check Address
G
I
I/G Address
?
Broadcast
Address
?
True
False
True
Multiple IND
?
Multiple Individual
Addresses
False
Hash_Search
Use Indicated
Table
Hash Search
Use Group
Table
Broadcast
Enabled
?
True
False
Single
Address
True True
Match
?
Match
?
False
False
Receive Frame
Ignore REJECT
Receive Frame
Ignore REJECT
False
Match
?
True
Receive Frame
Ignore REJECT
False
True
PROMISC
?
Start Receive
Discard Frame if REJECT
is Asserted
Discard Frame
Figure 25-4. Ethernet Address Recognition Flowchart
In group address recognition, the controller determines whether the group address is a broadcast address.
If broadcast addresses are enabled, the frame is accepted, but if the group address is not a broadcast
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25-11
SCC Ethernet Mode
address, address recognition can be performed on multiple group addresses using the GADDRn hash table.
In promiscuous mode, the controller receives all incoming frames regardless of their address, unless
REJECT is asserted.
If an external CAM is used for address recognition, select promiscuous mode; the frame can be rejected
by asserting REJECT while the frame is being received. The on-chip address recognition functions can be
used in addition to the external CAM address recognition functions.
If the external CAM stores addresses that should be rejected rather than accepted, the use of REJECT by
the CAM should be logically inverted.
25.11 Hash Table Algorithm
Individual and group hash filtering operate using certain processes. The Ethernet controller maps any
48-bit address into one of 64 bins, each represented by a bit stored in GADDRx or IADDRx. When a SET
GROUP ADDRESS command is executed, the Ethernet controller maps the selected 48-bit address into one
of the 64 bits by passing the 48-bit address through the on-chip 32-bit CRC generator and selecting 6 bits
of the CRC-encoded result to generate a number between 1 and 64. Bits 31–30 of the CRC result select
one of the GADDRs or IADDRs; bits 29–26 of the CRC result indicate the bit in that register.
When the Ethernet controller receives a frame, the same process is used. If the CRC generator selects a bit
that is set in the group/individual hash table, the frame is accepted. Otherwise, it is rejected. So, if eight
group addresses are stored in the hash table and random group addresses are received, the hash table
prevents roughly 56/64 (87.5%) of the group address frames from reaching memory. Frames that reach
memory must be further filtered by the processor to determine if they contain one of the eight preferred
addresses.
Better performance is achieved by using the group and individual hash tables simultaneously. For instance,
if eight group and eight physical addresses are stored in their respective hash tables, 87.5% of all frames
are prevented from reaching memory. The effectiveness of the hash table declines as the number of
addresses increases. For instance, with 128 addresses stored in a 64-bin hash table, the vast majority of the
hash table bits are set, thus preventing a small fraction of the frames from reaching memory.
Hash tables cannot be used to reject frames that match a set of entered addresses because unintended
addresses are mapped to the same bit in the hash table.
25.12 Interpacket Gap Time
The receiver receives back-to-back frames with a minimum interpacket spacing of 9.6 µs. In addition, after
the backoff algorithm, the transmitter waits for carrier sense to be negated before resending the frame.
Retransmission begins 9.6 µs after carrier sense is negated if it stays negated for at least 6.4 µs.
25.13 Handling Collisions
If a collision occurs as a frame is being sent, the Ethernet controller continues sending for at least 32 bit
times, thus sending a JAM pattern of 32 ones. If a collision occurs during the preamble sequence, the JAM
pattern is sent at the end of the sequence.
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SCC Ethernet Mode
If a collision occurs within 64 byte times, the retry process is initiated. The transmitter waits a random
number of slot times (512 bit times or 52 µs). If a collision occurs after 64 byte times, no retransmission
is performed and the buffer is closed with an LC error indication. If a collision occurs while a frame is
being received, reception stops. This error is reported only in the BD if the length of the frame exceeds
MINFLR or if PSMR[RSH] = 1.
25.14 Internal and External Loopback
Both internal and external loopback are supported by the Ethernet controller. In loopback mode, both of
the SCC FIFOs are used and the channel actually operates in a full-duplex fashion. Both internal and
external loopback are configured using combinations of PSMR[LPB] and GSMR[DIAG]. Because of the
full-duplex nature of the loopback operation, the performance of other SCCs is degraded.
Internal loopback disconnects the SCC from the serial interface. Receive data is connected to the transmit
data and the receive clock is connected to the transmit clock. Both FIFOs are used. Data from the transmit
FIFO is received immediately into the receive FIFO. There is no heartbeat check in this mode; configure
TENA as a general-purpose output.
In external loopback operation, the Ethernet controller listens for data being received from the EEST at the
same time that it is sending.
25.15 Full-Duplex Ethernet Support
To run full-duplex Ethernet, select loopback and full-duplex Ethernet modes in the SCC’s
protocol-specific mode register, (PSMR[LPB, FDE] = 1). The loopback mode tells the Ethernet controller
to accept received frames without signaling a collision. Setting PSMR[FDE] tells the controller that it can
send while receiving without waiting for a clear line (carrier sense).
25.16 Handling Errors in the Ethernet Controller
The Ethernet controller reports frame reception and transmission error conditions using channel BDs, error
Table 25-4. Transmission Errors
Error
Description
Transmitter underrun If this error occurs, the channel sends 32 bits that ensures a CRC error, stops sending the
buffer, closes it, sets the UN bit in the TxBD and SCCE[TXE]. The channel resumes
transmission after it receives a RESTART TRANSMIT command.
Carrier sense lost
during frame
transmission
When this error occurs and no collision is found in the frame, the channel sets the CSL bit in
the TxBD, sets SCCE[TXE], and continues sending the buffer normally. No retries are
performed after this error occurs. Carrier sense is the logical OR of RENA and CLSN.
Retransmission
The channel stops sending the buffer, closes it, sets the RL bit in the TxBD and SCCE[TXE].
attempts limit expired The channel resumes transmission after it receives a RESTART TRANSMIT command.
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25-13
SCC Ethernet Mode
Table 25-4. Transmission Errors (continued)
Description
Error
Late collision
When this error occurs, the channel stops sending the buffer, closes it, sets SCCE[TXE] and
the LC bit in the TxBD. The channel resumes transmission after it receives the RESTART
TRANSMIT command. This error is discussed further in the definition of PSMR[LCW].
Heartbeat
Some transceivers have a heartbeat (signal-quality error) self-test. To signify a good self-test,
the transceiver indicates a collision to the PowerQUICC II within 20 clocks after the Ethernet
controller sends a frame. This heartbeat condition does not imply a collision error, but that the
transceiver seems to be functioning properly. If SCCE[HBC] = 1 and the PowerQUICC II does not
detect a heartbeat condition after sending a frame, a heartbeat error occurs; the channel
closes the buffer, sets the HB bit in the TxBD, and generates the TXE interrupt if it is enabled.
Table 25-5 describes reception errors.
Table 25-5. Reception Errors
Description
Error
Overrun
Busy
The Ethernet controller maintains an internal FIFO for receiving data. When it overruns, the channel
writes the received byte over the previously received byte. The previous byte and frame status are lost.
The channel closes the buffer, sets RxBD[OV] and SCCE[RXF], and increments the discarded frame
counter (DISFC). The receiver then enters hunt mode.
A frame was received and discarded because of a lack of buffers. The channel sets SCCE[BSY] and
increments DISFC. The receiver then enters hunt mode.
Non-Octet The Ethernet controller handles up to seven dribbling bits when the receive frame terminates nonoctet
Error
(Dribbling
Bits)
aligned. It checks the CRC of the frame on the last octet boundary. If there is a CRC error, a frame
nonoctet aligned error is reported, SCCE[RXF] is set, and the alignment error counter is incremented. If
there is no CRC error, no error is reported. The receiver then enters hunt mode.
CRC
When a CRC error occurs, the channel closes the buffer, sets SCCE[RXF] and CR in the RxBD, and
increments the CRC error counter (CRCEC). After receiving a frame with a CRC error, the receiver
enters hunt mode. CRC checking cannot be disabled, but CRC errors can be ignored if checking is not
required.
25.17 Ethernet Mode Register (PSMR)
Ethernet mode register.
0
1
2
3
4
5
6
7
8
9
10
11
12
14
15
Field HBC FC RSH IAM
CRC
PRO BRO SBT LPB
0000_0000_0000_0000
R/W
—
LCW
NIB
FDE
Reset
R/W
Addr
Figure 25-5. Ethernet Mode Register (PSMR)
Table 25-6 describes PSMR fields.
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SCC Ethernet Mode
Table 25-6. PSMR Field Descriptions
Description
Bits
Name
0
1
HBC
Heartbeat checking.
0 No heartbeat checking is performed. Do not wait for a collision after transmission.
1 Wait 20 transmit clocks or 2 µs for a collision asserted by the transceiver after transmission. The
HB bit in the TxBD is set if the heartbeat is not heard within 20 transmit clocks.
FC
Force collision.
0 Normal operation.
1 The channel forces a collision when each frame is sent. To test collision logic configure the
PowerQUICC II in loopback operation. In the end, the retry limit for each transmit frame is exceeded.
2
3
RSH
IAM
Receive short frames.
0 Discard short frames that are not as long as MINFLR.
1 Receive short frames.
Individual address mode.
0 Normal operation. A single 48-bit physical address in PADDR1 is checked when it is received.
1 The individual hash table is used to check all individual addresses that are received.
4–5
6
CRC
PRO
CRC selection. Only CRC = 10 is valid. Complies with Ethernet specifications. 32-bit CCITT-CRC.
X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X1 +1.
Promiscuous.
0 Check the destination address of incoming frames.
1 Receive the frame regardless of its address unless REJECT is asserted as it is being received.
7
8
BRO
SBT
Broadcast address.
0 Receive all frames containing the broadcast address.
1 Reject all frames containing the broadcast address, unless PRO = 1.
Stop backoff timer.
0 The backoff timer is functioning normally.
1 The backoff timer for the random wait after a collision is stopped when carrier sense is active.
Retransmission is less aggressive than the maximum allowed in IEEE 802.3. The persistence
(P_PER) feature in the parameter RAM can be used in combination with or in place of SBT.
9
LPB
Local protect bit
0 Receiver is blocked when transmitter sends (default).
1 Receiver is not blocked when transmitter sends. Must be set for full-duplex operation. For
loopback operation, GSMR[DIAG] must be programmed also; see Section 20.1.1, “The General
10
11
—
Reserved. Should be cleared.
LCW
Late collision window.
0 A late collision is any collision that occurs at least 64 bytes from the preamble.
1 A late collision is any collision that occurs at least 56 bytes from the preamble.
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25-15
SCC Ethernet Mode
Table 25-6. PSMR Field Descriptions
Description
Bits
Name
12–14 NIB
Number of ignored bits. Determines how soon after RENA assertion the Ethernet controller should
begin looking for the start frame delimiter. Typically NIB = 101 (22 bits).
000 Begin searching 13 bits after the assertion of RENA.
001 Begin searching 14 bits after the assertion of RENA.
...
111 Begin searching 24 bits after the assertion of RENA.
15
FDE
Full duplex Ethernet.
0 Disable full-duplex Ethernet mode.
1 Enable full-duplex Ethernet mode.
Note: When FDE = 1, PSMR[LPB] must be set also.
25.18 SCC Ethernet Receive BD
The Ethernet controller uses the RxBD to report on the received data for each buffer.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Offset + 0
Offset + 2
Offset + 4
Offset + 6
E
—
W
I
L
F
—
M
—
LG
NO
SH
CR
OV
CL
Data Length
Rx Data Buffer Pointer
Figure 25-6. SCC Ethernet RxBD
Table 25-7 describes RxBD status and control fields.
Table 25-7. SCC Ethernet RxBD Status and Control Field Descriptions
Bits
Name
Description
0
E
Empty.
0 The buffer is full or stopped receiving data because an error occurred. The core can read or write
any fields of this RxBD. The CPM does not use this BD as long as the E bit is zero.
1 The buffer is not full. The CPM controls this BD and its buffer; do not modify this BD.
1
2
—
W
Reserved, should be cleared.
Wrap (final BD in table).
0 Not the last BD in the table.
1 Last BD in the table. After this buffer is used, the CPM receives incoming data into the first BD
that RBASE points to. The number of BDs is determined only by the W bit and overall space
constraints of the dual-port RAM.
3
I
Interrupt. Note that this bit does not mask SCCE[RXF] interrupts.
0 No SCCE[RXB] interrupt is generated after this buffer is used.
1 SCCE[RXB] or SCCE[RXF] is set when this buffer is used by the Ethernet controller. These two
bits can cause interrupts if they are enabled.
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SCC Ethernet Mode
Table 25-7. SCC Ethernet RxBD Status and Control Field Descriptions (continued)
Bits
Name
Description
4
L
Last in frame. The Ethernet controller sets this bit when this buffer is the last one in a frame, which
occurs when the end of a frame is reached or an error is received. In the case of error, one or more
of the CL, OV, CR, SH, NO, and LG bits are set. The Ethernet controller writes the number of frame
octets to the data length field.
0 The buffer is not the last one in a frame.
1 The buffer is the last one in a frame.
5
F
First in frame. The Ethernet controller sets this bit when this buffer is the first one in a frame.
0 The buffer is not the first one in a frame.
1 The buffer is the first one in a frame.
6
7
—
M
Reserved, should be cleared.
Miss. (valid only if L = 1) The Ethernet controller sets M for frames that are accepted in promiscuous
mode, but are flagged as a miss by internal address recognition. Thus, in promiscuous mode, M
determines whether a frame is destined for this station.
0 The frame is received because of an address recognition hit.
1 The frame is received because of promiscuous mode.
8–9
10
—
Reserved, should be cleared.
LG
Rx frame length violation. Set when a frame length greater than the maximum defined for this
channel has been recognized. Only the maximum number of bytes allowed is written to the buffer.
11
12
NO
SH
Rx nonoctet-aligned frame. Set when a frame containing a number of bits not divisible by eight is
received. Also, the CRC check that occurs at the preceding byte boundary generated an error.
Short frame. Set if a frame smaller than the minimum defined for this channel was recognized.
Occurs if PSMR[RSH] = 1.
13
14
15
CR
OV
CL
Rx CRC error. set when a frame contains a CRC error.
Overrun. Set when a receiver overrun occurs during frame reception.
Collision. This frame is closed because a collision occurred during frame reception. CL is set only if
a late collision occurs or if PSMR[RSH] is enabled. Late collisions are better defined in PSMR[LCW].
Data length and buffer pointer fields are described in Section 20.2, “SCC Buffer Descriptors (BDs).” Data
length includes the total number of frame octets (including four bytes for CRC).
Figure 25-7 shows an example of how RxBDs are used in receiving.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
25-17
SCC Ethernet Mode
MRBLR = 64 Bytes for this SCC
Buffer
Receive BD 0
E
0
L
F
Status
0
1
Destination Address (6)
Source Address (6)
Length
Pointer
0x0040
Buffer Full
32-Bit Buffer Pointer
64 Bytes
Type/Length (2)
Data Bytes (50)
Receive BD 1
Buffer
CRC Bytes (4)
Tag Byte (1)
Empty
E
0
L
F
Status
Length
1
0
0x0045
Buffer Closed
after CRC Received.
Optional Tag Byte
Appended
Pointer
32-Bit Buffer Pointer
64 Bytes
Receive BD 2
Buffer
E
1
Status
Length
Old Data from
Collided Frame Will
be Overwritten
XXXX
64 Bytes
Collision
Causes Buffer
Pointer
32-Bit Buffer Pointer
to be Reused
Empty
Buffer
Receive BD 3
E
1
Status
Length
XXXX
64 Bytes
Empty
Buffer
Still Empty
Pointer
32-Bit Buffer Pointer
Non-Collided Ethernet Frame 1
Line Idle
Frame 2
Two Frames
Received in Ethernet
Collision Present
Time
Time
Figure 25-7. Ethernet Receiving using RxBDs
25.19 SCC Ethernet Transmit Buffer Descriptor
Data is sent to the Ethernet controller for transmission on an SCC channel by arranging it in buffers
referenced by the channel TxBD table. The Ethernet controller uses TxBDs to confirm transmission or
indicate errors so the core knows buffers have been serviced. Figure 25-8 represents an SCC ethernet
transmit buffer descriptor.
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SCC Ethernet Mode
0
1
2
3
4
5
6
7
8
9
10
13
14
15
Offset + 0
Offset + 2
Offset + 4
Offset + 6
R
PAD
W
I
L
TC DEF HB
LC
RL
RC
UN CSL
Data Length
Tx Data Buffer Pointer
Figure 25-8. SCC Ethernet TxBD
Table 25-8 describes TxBD status and control fields.
Table 25-8. SCC Ethernet TxBD Status and Control Field Descriptions
Bits
Name
R
Description
0
Ready.
0 The buffer is not ready for transmission. The user can update this BD or its data buffer. The CPM
clears R after the buffer has been sent or after an error occurs.
1 The user-prepared buffer has not been sent or is currently being sent. Do not modify this BD.
1
2
PAD Short frame padding. Valid only when L is set. Otherwise, it is ignored.
0 Do not add PADs to short frames.
1 Add PADs to short frames. Pad bytes are inserted until the length of the sent frame equals the
MINFLR and they are stored in PADs in the parameter RAM.
W
Wrap (final BD in table).
0 Not the last BD in the table.
1 Last BD in the table. After this buffer is used, the CPM receives incoming data into the first BD
that TBASE points to in the table. The number of TxBDs in this table is determined only by the W
bit and overall space constraints of the dual-port RAM.
Note: The TxBD table must contain more than one BD in Ethernet mode.
3
I
Interrupt.
0 No interrupt is generated after this buffer is serviced.
1 SCCE[TXB] or SCCE[TXE] is set after this buffer is serviced. These bits can cause interrupts if
they are enabled.
4
5
6
7
L
Last.
0 Not the last buffer in the transmit frame.
1 Last buffer in the transmit frame.
TC
Tx CRC. Valid only when L = 1. Otherwise, it is ignored.
0 End transmission immediately after the last data byte.
1 Transmit the CRC sequence after the last data byte.
DEF Defer indication. The frame was deferred before being sent successfully, that is, the transmitter had
to wait for carrier sense before sending because the line was busy. This is not a collision indication;
collisions are indicated in RC.
HB
Heartbeat. Set when the collision input was not asserted within 20 transmit clocks after
transmission. HB cannot be set unless PSMR[HBC] = 1. The SCC writes HB after it finishes sending
the buffer.
8
9
LC
RL
Late collision. Set when a collision occurred after the number of bytes defined for PSMR[LCW] are
sent. The Ethernet controller stops sending and writes this bit after it finishes sending the buffer.
Retransmission limit. Set when the transmitter fails (Retry Limit + 1) attempts to successfully
transmit a message because of repeated collisions on the medium. The Ethernet controller writes
this bit after it finishes attempting to send the buffer.
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25-19
SCC Ethernet Mode
Table 25-8. SCC Ethernet TxBD Status and Control Field Descriptions (continued)
Bits
Name
Description
10–13
RC
Retry count. Indicates the number of retries required before the frame was sent successfully. If RC
= 0, the frame was sent correctly the first time. If RC = 15 and RET_LIM = 15 in the parameter RAM,
15 retries were required. Because the counter saturates at 15, if RC = 15 and RET_LIM > 15, then
15 or more retries were required. The controller writes this field after it successfully sends the buffer.
14
15
UN
Underrun. Set when the Ethernet controller encounters a transmitter underrun while sending the
buffer. The Ethernet controller writes UN after it finishes sending the buffer.
CSL Carrier sense lost. Set when carrier sense is lost during frame transmission. The Ethernet controller
writes CSL after it finishes sending the buffer.
Data length and buffer pointer fields are described in Section 20.2, “SCC Buffer Descriptors (BDs).”
25.20 SCC Ethernet Event Register (SCCE)/Mask Register (SCCM)
The SCC event register (SCCE) is used as the Ethernet event register to generate interrupts and report
events recognized by the Ethernet channel. When an event is recognized, the Ethernet controller sets the
corresponding SCCE bit. Interrupts are enabled by setting, and masked by clearing, the equivalent bits in
the Ethernet mask register (SCCM). SCCE bits are cleared by writing ones; writing zeros has no effect.
All unmasked bits must be cleared before the CPM clears the internal interrupt request. The SCCE/SCCM
0
7
8
9
10
11
12
13
14
15
Field
Reset
R/W
—
GRA
—
TXE RXF BSY TXB RXB
0000_0000_0000_0000
R/W
Addr
Figure 25-9. SCC Ethernet Event Register (SCCE)/Mask Register (SCCM)
Table 25-9 describes SCCE and SCCM fields.
Table 25-9. SCCE/SCCM Field Descriptions
Bits
Name
Description
0–7
8
—
Reserved, should be cleared.
GRA Graceful stop complete. Set as soon the transmitter finishes any frame that was in progress when
a GRACEFUL STOP TRANSMIT command was issued. It is set immediately if no frame was in progress.
9–10
11
—
Reserved, should be cleared.
TXE Set when an error occurs on the transmitter channel.
12
RXF Rx frame. Set when a complete frame has been received on the Ethernet channel.
BSY Busy condition. Set when a frame is received and discarded due to a lack of buffers.
13
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SCC Ethernet Mode
Table 25-9. SCCE/SCCM Field Descriptions (continued)
Description
Bits
Name
14
15
TXB Tx buffer. Set when a buffer has been sent on the Ethernet channel.
RXB Rx buffer. Set when a buffer that was not a complete frame was received on the Ethernet channel.
Figure 25-10 shows an example of interrupts that can be generated in Ethernet protocol.
Frame
Received in Ethernet
Stored in Rx Buffer
Time
P
SFD DA SA T/L
D
CR
RXD
Line Idle
Line Idle
RENA
Ethernet SCCE
Events
RXB
RXF
NOTES
:
1. RXB event assumes receive buffers are 64 bytes each.
2. The RENA events, if required, must be programmed in the parallel I/O ports, not in the SCC itself.
3. The RxF interrupt may occur later than RENA due to receive FIFO latency.
Frame
Transmitted by Ethernet
Stored in Tx Buffer
P
SFD DA SA T/L
D
CR
TXD
Line Idle
Line Idle
TENA
CLSN
Ethernet SCCE
Events
TXB
TXB, GRA
NOTES:
1. TXB events assume the frame required two transmit buffers.
2. The GRA event assumes a GRACEFUL STOP TRANSMIT command was issued during frame transmission.
3. The TENA or CLSN events, if required, must be programmed in the parallel I/O ports, not in the SCC itself.
LEGEND:
P = Preamble, SFD = Start frame delimiter, DA and SA = Source/Destination address,
T/L = Type/Length, D = Data, CR = CRC bytes
Figure 25-10. Ethernet Interrupt Events Example
Note that the SCC status register (SCCS) cannot be used with the Ethernet protocol. The current state of
the RENA and CLSN signals can be found in the parallel I/O ports.
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Freescale Semiconductor
25-21
SCC Ethernet Mode
25.21 SCC Ethernet Programming Example
The following is an initialization sequence for the SCC2 in Ethernet mode. The CLK3 pin is used for the
Ethernet receiver and CLK4 is used for the transmitter.
1. Configure port D pins to enable TXD2 and RXD2. Set PPARD[27,28] and PDIRD[27] and clear
PDIRD[28] and PSORD[27,28].
2. Configure ports C and D pins to enable TENA2 (RTS2), CLSN2 (CTS2) and RENA2 (CD2). Set
PPARD[26], PPARC[12,13] and PDIRD[26] and clear PDIRC[12,13], PSORC[12,13] and
PSORD[26].
3. Configure port C pins to enable CLK3 and CLK4. Set PPARC[28,29] and clear PDIRC[28,29] and
PSORC[28,29].
4. Connect CLK3 to the SCC2 receiver and CLK4 to the transmitter using the CPM mux. Program
CMXSCR[R2CS] to 0b110 and CMXSCR[T2CS] to 0b111.
5. Connect the SCC2 to the NMSI and clear CMXSCR[SC2].
6. Write RBASE and TBASE in the SCC2 parameter RAM to point to the RxBD and TxBD in the
dual-port RAM. Assuming one RxBD at the beginning of the dual-port RAM and one TxBD
following that RxBD, write RBASE with 0x0000 and TBASE with 0x0008.
7. Write 0x04A1_0000 to the CPCR to execute an INIT RX AND TX PARAMETERS command for this
channel.
8. Clear CRCEC, ALEC, and DISFC for clarity.
9. Write PAD with 0x8888 for the PAD value.
10. Write RET_LIM with 0x000F.
11. Write MFLR with 0x05EE to make the maximum frame size 1518 bytes.
12. Write MINFLR with 0x0040 to make the minimum frame size 64 bytes.
13. Write MAXD1 and MAXD2 with 0x05F0 to make the maximum DMA count 1520 bytes.
14. Clear GADDR1–GADDR4. The group hash table is not used.
15. Write PADDR1_H with 0x0000, PADDR1_M with 0x0000, and PADDR1_L with 0x0040 to
configure the physical address.
16. Clear P_PER. It is not used.
17. Clear IADDR1–IADDR4. The individual hash table is not used.
18. Clear TADDR_H, TADDR_M, and TADDR_L for clarity.
19. Initialize the RxBD and assume the Rx data buffer is at 0x0000_1000 in main memory. Write
0xB000 to RxBD[Status and Control], 0x0000 to RxBD[Data Length] (optional), and
0x0000_1000 to RxBD[Buffer Pointer].
20. Initialize the TxBD and assume the Tx data frame is at 0x0000_2000 in main memory and contains
fourteen 8-bit characters (destination and source addresses plus the type field). Write 0xFC00 to
TxBD[Status and Control], add PAD to the frame and generate a CRC. Then write 0x000D to
TxBD[Data Length] and 0x0000_2000 to TxBD[Buffer Pointer].
21. Write 0xFFFF to the SCCE register to clear any previous events.
22. Write 0x001A to the SCCM register to enable the TXE, RXF, and TXB interrupts.
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SCC Ethernet Mode
23. Write 0x0040_0000 to the SIU interrupt mask register low (SIMR_L) so the SMC1 can generate a
system interrupt. Initialize SIU interrupt pending register low (SIPNR_L) by writing
0xFFFF_FFFF to it.
24. Write 0x0000_0000 to GSMR_H2 to enable normal operation of all modes.
25. Write 0x1088_000C to the GSMR_L2 register to configure CTS (CLSN) and CD (RENA) to
automatically control transmission and reception (DIAG bits) and the Ethernet mode. TCI is set to
allow more setup time for the EEST to receive the PowerQUICC II transmit data. TPL and TPP
are set for Ethernet requirements. The DPLL is not used with Ethernet. Note that the ENT and ENR
are not enabled yet.
26. Write 0xD555 to the DSR.
27. Set the PSMR2 to 0x0A0A to configure 32-bit CRC, promiscuous mode, and begin searching for
the start frame delimiter 22 bits after RENA2 (CD2).
28. Write 0x1088_003C to GSMR_L2 to enable the SCC2 transmitter and receiver. This
additional write ensures that ENT and ENR are enabled last.
After 14 bytes and the 46 bytes of automatic pad (plus the 4 bytes of CRC) are sent, the TxBD is closed.
Additionally, the receive buffer is closed after a frame is received. Any data received after 1520 bytes or
a single frame causes a busy (out-of-buffers) condition because only one RxBD is prepared.
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SCC Ethernet Mode
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Chapter 26
SCC AppleTalk Mode
AppleTalk is a set of protocols developed by Apple Computer, Inc. to provide a LAN service between
Macintosh computers and printers. Although AppleTalk can be implemented over a variety of physical and
link layers, including Ethernet, AppleTalk protocols have been most closely associated with the LocalTalk
physical and link-layer protocol, an HDLC-based protocol that runs at 230.4 kbps. In this manual, the term
‘AppleTalk controller’ refers to the support that the PowerQUICC II provides for LocalTalk protocol. The
AppleTalk controller provides required frame synchronization, bit sequence, preamble, and postamble
onto standard HDLC frames. These capabilities, with the use of the HDLC controller in conjunction with
DPLL operation in FM0 mode, provide the proper connection formats to the LocalTalk bus.
26.1 Operating the LocalTalk Bus
Sync
Sequence
HDLC
Flags
Destination Source
Control
Byte
Data
(Optional)
Closing
Flag
Abort
Sequence
CRC-16
2 bytes
Address
Address
> 3 bits
2 or more
bytes
1 byte
1 byte
1 byte
0-600 bytes
1 byte
12–18 ones
Figure 26-1. LocalTalk Frame Format
First, a synchronization sequence of more than three bits is sent. This sequence consists of at least one
logical one bit (FM0 encoded) followed by two bit times or more of line idle with no particular maximum
time specified. The idle time allows LocalTalk equipment to sense a carrier by detecting a missing clock
on the line. The remainder of the frame is a typical half-duplex HDLC frame. Two or more flags are sent,
allowing bit, byte, and frame delineation or detection. Two bytes of address, destination, and source are
sent next, followed by a byte of control and 0–600 data bytes. Next, two bytes of CRC (the common 16-bit
CRC-CCITT polynomial referenced in the HDLC standard protocol) are sent. The LocalTalk frame is then
terminated by a flag and a restricted HDLC abort sequence. Then the transmitter’s driver is disabled.
The control byte within the LocalTalk frame indicates the type of frame. Control byte values from
0x01–0x7F are data frames; control byte values from 0x80–0xFF are control frames. Four control frames
are defined:
•
•
•
•
ENQ—Enquiry
ACK—Enquiry acknowledgment
RTS—Request to send a data frame
CTS—Clear to send a data frame
Frames are sent in groups known as dialogs, which are handled by the software. For instance, to transfer
a data frame, three frames are sent over the network. An RTS frame (not to be confused with the RS-232
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26-1
SCC AppleTalk Mode
RTS pin) is sent to request the network, a CTS frame is sent by the destination node, and the data frame is
sent by the requesting node. These three frames comprise one possible type of dialog. After a dialog
begins, other nodes cannot start sending until the dialog is complete. Frames within a dialog are sent with
a maximum interframe gap (IFG) of 200 µs. Although the LocalTalk specification does not state it, there
is also a minimum recommended IFG of 50 µs. Dialogs must be separated by a minimum interdialog gap
(IDG) of 400 µs. In general, these gaps are implemented by the software.
Depending on the protocol, collisions should be encountered only during RTS and ENQ frames. Once
frame transmission begins, it is fully sent, regardless of whether it collides with another frame. ENQ
frames are infrequent and are sent only when a node powers up and enters the network. A higher-level
protocol controls the uniqueness and transmission of ENQ frames.
In addition to the frame fields, LocalTalk requires that the frame be FM0 (differential Manchester space)
encoded, which requires one level transition on every bit boundary. If the value to be encoded is a logical
zero, FM0 requires a second transition in the middle of the bit time. The purpose of FM0 encoding is to
avoid having to transmit clocking information on a separate wire. With FM0, the clocking information is
present whenever valid data is present.
26.2 Features
The following list summarizes the features of the SCC in AppleTalk mode:
•
•
•
•
•
•
•
•
Superset of the HDLC controller features
FM0 encoding/decoding
Programmable transmission of sync sequence
Automatic postamble transmission
Reception of sync sequence does not cause extra SCCE[DCC] interrupts
Reception is automatically disabled while sending a frame
Transmit-on-demand feature expedites frames
Connects directly to an RS-422 transceiver
26.3 Connecting to AppleTalk
an interface for the RS-422 transceiver. The RS-422, in turn, is an interface for the LocalTalk connector.
Although it is not shown, a passive RC circuit is recommended between the transceiver and connector.
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Freescale Semiconductor
SCC AppleTalk Mode
PowerQUICC II
RS-422
MINI-DIN 8
Connection
Tx Data
Tx Enable
Rx Data
SCC
TXD
RTS
RXD
Stored in Receive Buffer
Stored in Transmit Buffer
6-Bit Sync Two HDLC Destination Source
Sequence Flags Address Address
Control
Byte
Closing 16 Ones
Flag (Abort)
TXD
RTS
Data
CRC-16
Standard HDLC frame handling
Figure 26-2. Connecting the PowerQUICC II to LocalTalk
The 16× overspeed of a 3.686-MHz clock can be generated from an external frequency source or from one
of the baud rate generators if the resulting output frequency is close to a multiple of the 3.686 MHz
frequency. The PowerQUICC II asserts RTS throughout the duration of the frame so that RTS can be used
to enable the RS-422 transmit driver.
26.4 Programming the SCC in AppleTalk Mode
The AppleTalk controller is implemented by setting certain bits in the HDLC controller. Otherwise,
TODR to program the AppleTalk controller.
26.4.1 Programming the GSMR
Program the GSMR as described below:
1. Set MODE to 0b0010 (AppleTalk).
2. Set DIAG to 0b00 for normal operation, with CD and CTS grounded or configured for parallel I/O.
This causes CD and CTS to be internally asserted to the SCC.
3. Set RDCR and TDCR to (0b10) a 16× clock.
4. Set the TENC and RENC bits to 0b010 (FM0).
5. Clear TEND for default operation.
6. Set TPP to 0b11 for a preamble pattern of all ones.
7. Set TPL to 0b000 to transmit the next frame with no synchronization sequence and to 001 to
transmit the next frame with the LocalTalk synchronization sequence. For example, data frames do
not require a preceding synchronization sequence. These bits may be modified on-the-fly if the
AppleTalk protocol is selected.
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SCC AppleTalk Mode
8. Clear TINV and RINV so data will not be inverted.
9. Set TSNC to 1.5 bit times (0b10).
10. Clear EDGE. Both the positive and negative edges are used to change the sample point (default).
11. Clear RTSM (default).
12. Set all other bits to zero or default.
13. Set ENT and ENR as the last step to begin operation.
26.4.2 Programming the PSMR
Follow these steps to program the protocol-specific mode register:
1. Set NOF to 0b0001 giving two flags before frames (one opening flag, plus one additional flag).
2. Set CRC 16-bit CRC-CCITT.
3. Set DRT.
4. Set all other bits to zero or default.
26.4.3 Programming the TODR
Use the transmit-on-demand (TODR) register to expedite a transmit frame. See Section 20.1.4,
26.4.4 SCC AppleTalk Programming Example
Except for the previously discussed register programming, use the example in Section 22.15.6, “HDLC
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Chapter 27
Serial Management Controllers (SMCs)
The two serial management controllers (SMCs) are full-duplex ports that can be configured independently
to support one of three protocols or modes—UART, transparent, or general-circuit interface (GCI). Simple
UART operation is used to provide a debug/monitor port in an application, which allows the SCCs to be
free for other purposes. The SMC in UART mode is not as complex as that of the SCC in UART mode.
The SMC clock can be derived from one of the internal baud rate generators or from an external clock
signal. However, the clock should be a 16× clock.
In totally transparent mode, the SMC can be connected to a TDM channel (such as a T1 line) or directly
to its own set of signals. The receive and transmit clocks are derived from the TDM channel, the internal
baud rate generators, or from an external 1× clock. The transparent protocol allows the transmitter and
receiver to use the external synchronization signal. The SMC in transparent mode is not as complex as that
of the SCC in transparent mode.
Each SMC supports the C/I and monitor channels of the GCI bus, for which the SMC connects to a
time-division multiplex (TDM) channel in a serial interface (SIx). SMCs support loopback and echo
modes for testing. The SMC receiver and transmitter are double-buffered, corresponding to an effective
FIFO size (latency) of two characters. Chapter 15, “Serial Interface with Time-Slot Assigner,” describes
GCI interface configuration.
Figure 27-1 shows the SMC block diagram.
60x Bus
SYNC
CLK
Control
Registers
Control
Logic
Peripheral Bus
Rx
Data
Tx
Data
Register
Register
TXD
RXD
Shifter
Shifter
Figure 27-1. SMC Block Diagram
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27-1
Serial Management Controllers (SMCs)
The receive data source can be L1RXD if the SMC is connected to a TDM channel of an SIx, or SMRXD
if it is connected to the NMSI. The transmit data source can be L1TXD if the SMC is connected to a TDM
or SMTXD if it is connected to the NMSI.
If the SMC is connected to a TDM, the SMC receive and transmit clocks can be independent from each
connected to the NMSI, receive and transmit clocks must be connected to a single clock source (SMCLK),
an internal signal name for a clock generated from the bank of clocks. SMCLK originates from an external
signal or one of the four internal baud rate generators.
An SMC connected to a TDM derives a synchronization pulse from the TSA. An SMC connected to the
NMSI using transparent protocol can use SMSYN for synchronization to determine when to start a
transfer. SMSYN is not used when the SMC is in UART mode.
27.1 Features
The following is a list of the SMC’s main features:
•
•
Each SMC can implement the UART protocol on its own signals
Each SMC can implement a totally transparent protocol on a multiplexed or nonmultiplexed line.
This mode can also be used for a fast connection between PowerQUICC IIs.
•
Each SMC channel fully supports the C/I and monitor channels of the GCI (IOM-2) in ISDN
applications
•
•
•
Two SMCs support the two sets of C/I and monitor channels in the SCIT channels 0 and 1
Full-duplex operation
Local loopback and echo capability for testing
27.2 Common SMC Settings and Configurations
The following sections describe settings and configurations that are common to the SMCs.
27.2.1 SMC Mode Registers (SMCMR1/SMCMR2)
as mode-specific parameters. The functions of SMCMR[8–15] are the same for each protocol. Bits 0–7
vary according to protocol selected by the SM bits.
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Serial Management Controllers (SMCs)
Bit
Field: UART
Transparent
GCI
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
—
CLEN
SL PEN
PM
—
SM
DM
TEN REN
—
BS REVD
C#
ME
—
Reset
0000_0000_0000_0000
R/W
R/W
Addr
Figure 27-2. SMC Mode Registers (SMCMR1/SMCMR2)
Table 27-1 describes SMCMR fields.
Table 27-1. SMCMR1/SMCMR2 Field Descriptions
Bits
Name
Description
0
—
Reserved, should be cleared
1–4
CLEN Character length (UART). Number of bits in the character minus one. The total is the sum of 1 (start
bit always present) + number of data bits (5–14) + number of parity bits (0 or 1) + number of stop
bits (1 or 2). For example, for 8 data bits, no parity, and 1 stop bit, the total number of bits in the
character is 1 + 8 + 0 + 1 = 10. So, CLEN should be programmed to 9.
Characters range from 5–14 bits. If the data bit length is less than 8, the msbs of each byte in
memory are not used on transmit and are written with zeros on receive. If the length is more than 8,
the msbs of each 16-bit word are not used on transmit and are written with zeros on receive.
The character must not exceed 16 bits. For a 14-bit data length, set SL to one stop bit and disable
parity. For a 13-bit data length with parity enabled, set SL to one stop bit. Writing values 0 to 3 to
CLEN causes erratic behavior.
Character length (transparent). The values 3–15 specify 4–16 bits per character. If a character is
less than 8 bits, the most-significant bits of the byte in buffer memory are not used on transmit and
are written with zeros on receive. If character length is more than 8 bits but less than 16, the
most-significant bits of the half-word in buffer memory are not used on transmit and are written with
zeros on receive.
Note: Using values 0–2 causes erratic behavior. Larger character lengths increase an SMC
channel’s potential performance and lowers the performance impact of other channels. For
instance, using 16- rather than 8-bit characters is encouraged if 16-bit characters are acceptable in
the end application.
Character length (GCI). Number of bits in the C/I and monitor channels of the SCIT channels 0 or
1. (values 0–15 correspond to 1–16 bits) CLEN should be 13 for SCIT channel 0 or GCI (8 data bits,
plus A and E bits, plus 4 C/I bits = 14 bits). It should be 15 for the SCIT channel 1 (8 data, bits, plus
A and E bits, plus 6 C/I bits = 16 bits).
5
SL
Stop length. (UART)
0 One stop bit.
1 Two stop bits.
—
Reserved, should be cleared. (transparent)
ME
Monitor enable. (GCI)
0 The SMC does not support the monitor channel.
1 The SMC supports the monitor channel.
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Serial Management Controllers (SMCs)
Table 27-1. SMCMR1/SMCMR2 Field Descriptions (continued)
Description
Bits
Name
6
PEN Parity enable. (UART)
0 No parity.
1 Parity is enabled for the transmitter and receiver as determined by the PM bit.
BS
Byte sequence(transparent). Controls the byte transmission sequence if REVD is set for a character
length greater than 8 bits. Clear BS to maintain behavior compatibility with MC68360 QUICC.
0 Normal mode. This should be selected if the character length is not larger than 8 bits.
1 Transmit lower address byte first.
—
Reserved, should be cleared. (GCI)
7
PM
Parity mode. (UART)
0 Odd parity.
1 Even parity.
REVD Reverse data. (transparent)
0 Normal mode.
1 Reverse the character bit order. The msb is sent first.
C#
SCIT channel number. (GCI)
0 SCIT channel 0
1 SCIT channel 1. Required for Siemens ARCOFI and SGS S/T chips.
8–9
—
Reserved, should be cleared.
10–11
SM
SMC mode.
00 GCI or SCIT support.
01 Reserved.
10 UART (must be selected for SMC UART operation).
11 Totally transparent operation.
12–13
DM
Diagnostic mode.
00 Normal operation.
01 Local loopback mode.
10 Echo mode.
11 Reserved.
14
15
TEN SMC transmit enable.
0 SMC transmitter disabled.
1 SMC transmitter enabled.
REN SMC receive enable.
0 SMC receiver disabled.
1 SMC receiver enabled.
27.2.2 SMC Buffer Descriptor Operation
In UART and transparent modes, the SMC’s memory structure is like the SCC’s, except that
SMC-associated data is stored in buffers. Each buffer is referenced by a BD and organized in a BD table
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Serial Management Controllers (SMCs)
Dual-Port RAM
External Memory
TxBD Table
Status and Control
Data Length
SMC TxBD
Table
Buffer Pointer
Tx Data Buffer
RxBD Table
Status and Control
Data Length
SMC RxBD
Table
Buffer Pointer
Rx Data Buffer
Pointer to SMCx
RxBD Table
Pointer to SMCx
TxBD Table
Figure 27-3. SMC Memory Structure
The BD table allows buffers to be defined for transmission and reception. Each table forms a circular
queue. The CP uses BDs to confirm reception and transmission so that the processor knows buffers have
been serviced. The data resides in external or internal buffers.
When SMCs are configured to operate in GCI mode, their memory structure is predefined to be one
half-word long for transmit and one half-word long for receive. For more information on these half-word
27.2.3 SMC Parameter RAM
The CP accesses each SMC’s parameter table using a user-programmed pointer (SMCx_BASE) located in
placed at any 64-byte aligned address in the dual-port RAM’s general-purpose area (banks 1–8, 11 and 12).
The protocol-specific portions of the SMC parameter RAM are discussed in the sections that follow. The
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Serial Management Controllers (SMCs)
Table 27-2. SMC UART and Transparent Parameter RAM Memory Map
Offset
Name
Width
Description
1
0x00
0x02
RBASE
TBASE
Hword RxBDs and TxBDs base address. (BD table pointer) Define starting points in the
dual-port RAM of the set of BDs for the SMC send and receive functions. They allow
Hword
flexible partitioning of the BDs. By selecting RBASE and TBASE entries for all SMCs
and by setting W in the last BD in each list, BDs are allocated for the send and receive
side of every SMC. Initialize these entries before enabling the corresponding channel.
Configuring BD tables of two enabled SMCs to overlap causes erratic operation.
RBASE and TBASE should be a multiple of eight.
0x04
0x05
0x06
RFCR
TFCR
Byte
MRBLR
Hword Maximum receive buffer length. The most bytes the PowerQUICC II writes to a receive
buffer before moving to the next buffer. It can write fewer bytes than MRBLR if a
condition like an error or end-of-frame occurs, but it cannot exceed MRBLR.
PowerQUICC II buffers should not be smaller than MRBLR. SMC transmit buffers are
unaffected by MRBLR.
Transmit buffers can be individually given varying lengths through the data length field.
MRBLR can be changed while an SMC is operating only if it is done in a single bus
cycle with one 16-bit move (not two 8-bit bus cycles back-to-back). This occurs when
the CP shifts control to the next RxBD, so the change does not take effect immediately.
To guarantee the exact RxBD on which the change occurs, change MRBLR only while
the SMC receiver is disabled. MRBLR should be greater than zero and should be even
if character length exceeds 8 bits.
2
0x08
0x0C
RSTATE
—
Word Rx internal state. Can be used only by the CP.
2
Word Rx internal data pointer. Updated by the SDMA channels to show the next address in
the buffer to be accessed.
0x10
RBPTR
Hword RxBD pointer. Points to the next BD for each SMC channel that the receiver transfers
data to when it is in idle state, or to the current BD during frame processing. After a
reset or when the end of the BD table is reached, the CP initializes RBPTR to the value
in RBASE. Most applications never need to write RBPTR, but it can be written when
the receiver is disabled or when no receive buffer is in use.
2
0x12
—
Hword Rx internal byte count. A down-count value initialized with the MRBLR value and
decremented with every byte the SDMA channels write.
2
0x14
0x18
0x1C
—
TSTATE
—
Word Rx temp Can be used only by the CP.
2
Word Tx internal state. Can be used only by the CP.
2
Word Tx internal data pointer. Updated by the SDMA channels to show the next address in
the buffer to be accessed.
0x20
TBPTR
Hword TxBD pointer. Points to the next BD for each SMC channel the transmitter transfers
data from when it is in idle state or to the current BD during frame transmission. After
reset or when the end of the table is reached, the CP initializes TBPTR to the TBASE
value. Most applications never need to write TBPTR, but it can be written when the
transmitter is disabled or when no transmit buffer is in use. For instance, after a STOP
TRANSMIT or GRACEFUL STOP TRANSMIT command is issued and the frame completes its
transmission.
2
0x22
—
Hword Tx internal byte count. A down-count value initialized with the TxBD data length and
decremented with every byte the SDMA channels read.
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Serial Management Controllers (SMCs)
Table 27-2. SMC UART and Transparent Parameter RAM Memory Map (continued)
Offset
Name
Width
Description
1
2
0x24
0x28
—
Word Tx temp. Can be used only by the CP.
MAX_IDL Hword Maximum idle characters. (UART protocol-specific parameter) When a character is
received on the line, the SMC starts counting idle characters received. If MAX_IDL idle
characters arrive before the next character, an idle time-out occurs and the buffer
closes, which sends an interrupt request to the core to receive data from the buffer.
MAX_IDL demarcates frames in UART mode. Clearing MAX_IDL disables the function
so the buffer never closes, regardless of how many idle characters are received. An idle
character is calculated as follows: 1 + data length (5 to 14) + 1 (if parity bit is used) +
number of stop bits (1 or 2). For example, for 8 data bits, no parity, and 1 stop bit,
character length is 10 bits.
0x2A
0x2C
IDLC
Hword Temporary idle counter. (UART protocol-specific parameter) Down-counter in which the
CP stores the current idle counter value in the MAX_IDL time-out process.
BRKLN
Hword Last received break length. (UART protocol-specific parameter) Holds the length of the
last received break character sequence measured in character units. For example, if
the receive signal is low for 20 bit times and the defined character length is 10 bits,
BRKLN = 0x002, indicating that the break sequence is at least 2 characters long.
BRKLN is accurate to within one character length.
0x2E
0x30
BRKEC
BRKCR
Hword Receive break condition counter. (UART protocol-specific parameter) Counts break
conditions on the line. A break condition may last for hundreds of bit times, yet BRKEC
increments only once during that period.
Hword Break count register (transmit). (UART protocol-specific parameter) Determines the
number of break characters the UART controller sends. Set when the SMC sends a
break character sequence after a STOP TRANSMIT command. For 8 data bits, no parity,
1 stop bit, and 1 start bit, each break character is 10 zeros.
0x32
0x34
R_MASK Hword Temporary bit mask. (UART protocol-specific parameter)
Word SDMA Temp
—
1
2
From the pointer value programmed in SMCx_BASE: SMC1_BASE at 0x87FC, SMC2_BASE at IMMR + 0x88FC.
Not accessed for normal operation. May hold helpful information for experienced users and for debugging.
To extract data from a partially full receive buffer, issue a CLOSE RXBD command.
Certain parameter RAM values must be initialized before the SMC is enabled. Other values are initialized
or written by the CP. Once values are initialized, software typically does not need to update them because
activity centers mostly around transmit and receive BDs rather than parameter RAM. However, note the
following:
•
•
Parameter RAM can be read at any time.
Values that pertain to the SMC transmitter can be written only if SMCMR[TEN] is zero or between
the STOP TRANSMIT and RESTART TRANSMIT commands.
•
Values for the SMC receiver can be written only when SMCMR[REN] is zero, or, if the receiver
is previously enabled, after an ENTER HUNT MODE command is issued but before the CLOSE RXBD
command is issued and REN is set.
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Serial Management Controllers (SMCs)
27.2.3.1 SMC Function Code Registers (RFCR/TFCR)
The function code registers contain the transaction specification associated with SDMA channel accesses
0
1
2
3
4
5
6
7
Field
R/W
Addr
GBL
BO
TC2
DTB
—
R/W
SMC base + 0x04 (RFCR)/SMC base + 0x05 (TFCR)
Figure 27-4. SMC Function Code Registers (RFCR/TFCR)
Table 27-3 describes FCR fields.
Table 27-3. RFCR/TFCR Field Descriptions
Bit
Name
Description
0–1
2
—
Reserved, should be cleared.
GBL Global access bit
0 Disable memory snooping
1 Enable memory snooping
3–4
BO
Byte ordering. Selects byte ordering of the data buffer.
00 The DEC/Intel convention (swapped operation or little-endian). The transmission order of bytes
within a buffer word is opposite of Freescale mode. (32-bit port size memory only).
01 Munged little-endian. As data is sent onto the serial line from the buffer, the LSB of the buffer
double word contains data to be sent earlier than the MSB of the same double word.
1x Freescale (big-endian) byte ordering (normal operation). As data is sent onto the serial line from
the buffer, the MSB of the buffer word contains data to be sent earlier than the LSB of the same
word.
5
6
TC2 Transfer code 2. Contains the transfer code value of TC[2], used during this SDMA channel memory
access. TC[0–1] is driven with a 0b11 to identify this SDMA channel access as a DMA-type access.
DTB Data bus indicator.
0 Use 60x bus for SDMA operation.
1 Use local bus for SDMA operation.
7
—
Reserved, should be cleared.
27.2.4 Disabling SMCs On-the-Fly
An SMC can be disabled and reenabled later by ensuring that buffers are closed properly and new data is
transferred to or from a new buffer. Such a sequence is required if the parameters to be changed are not
dynamic. If the register or bit description states that dynamic changes are allowed, the sequences need not
be followed and the register or bits may be changed immediately.
NOTE
The SMC does not have to be fully disabled for parameter RAM to be
2
modified. To disable all SCCs, SMCs, the SPI, and the I C, use the CPCR
to reset the CPM with a single command.
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Serial Management Controllers (SMCs)
27.2.4.1 SMC Transmitter Full Sequence
Follow these steps to fully enable or disable the SMC transmitter:
1. If the SMC is sending data, issue a STOP TRANSMIT command to stop transmission smoothly. If the
SMC is not sending, if TBPTR is overwritten, or if an INIT TX PARAMETERS command is executed,
this command is not required.
2. Clear SMCMR[TEN] to disable the SMC transmitter and put it in reset state.
3. Update SMC transmit parameters, including the parameter RAM. To switch protocols or
reinitialize parameters, issue an INIT TX PARAMETERS command.
4. Issue a RESTART TRANSMIT if an INIT TX PARAMETERS was issued in step 3.
5. Set SMCMR[TEN]. Transmission now begins using the TxBD that the TBPTR value pointed to as
soon as the R bit is set in the TxBD.
27.2.4.2 SMC Transmitter Shortcut Sequence
This shorter sequence reinitializes transmit parameters to the state they had after reset.
1. Clear SMCMR[TEN].
2. Issue an INIT TX PARAMETERS command and make any additional changes.
3. Set SMCMR[TEN].
27.2.4.3 SMC Receiver Full Sequence
Follow these steps to fully enable or disable the receiver:
1. Clear SMCMR[REN]. Reception is aborted immediately, which disables the SMC receiver and
puts it in a reset state.
2. Modify SMC receive parameters, including parameter RAM. To switch protocols or reinitialize
SMC receive parameters, issue an INIT RX PARAMETERS command.
3. Issue a CLOSE RXBD command if INIT RX PARAMETERS was not issued in step 2.
4. Set SMCMR[REN]. Reception immediately uses the RxBD that RBPTR pointed to if E is set in
the RxBD.
27.2.4.4 SMC Receiver Shortcut Sequence
This shorter sequence reinitializes receive parameters to their state after reset.
1. Clear SMCMR[REN].
2. Issue an INIT RX PARAMETERS command and make any additional changes.
3. Set SMCMR[REN].
27.2.4.5 Switching Protocols
To switch the protocol that the SMC is executing without resetting the board or affecting any other SMC,
use one command and follow these steps:
1. Clear SMCMR[REN] and SMCMR[TEN].
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Serial Management Controllers (SMCs)
2. Issue an INIT TX AND RX PARAMETERS COMMAND to initialize transmit and receive parameters.
Make any additional SMCMR changes.
3. Set SMCMR[REN, TEN]. The SMC is now enabled with the new protocol.
27.2.5 Saving Power
When SMCMR[TEN, REN] are cleared, the SMC consumes little power.
27.2.6 Handling Interrupts in the SMC
Follow these steps to handle an interrupt in the SMC:
1. Once an interrupt occurs, read SMCE to identify the interrupt source. The SMCE bits are usually
cleared at this time.
2. Process the TxBD to reuse it if SMCE[TXB] is set. Extract data from the RxBD if SMCE[RXB]
is set. To send another buffer, set TxBD[R].
3. Execute the rfi instruction.
27.3 SMC in UART Mode
SMCs generally offer less functionality and performance in UART mode than do SCCs, which makes them
more suitable for simpler debug/monitor ports instead of full-featured UARTs. SMCs do not support the
following features in UART mode.
•
•
•
•
•
•
•
•
•
•
RTS, CTS, and CD signals
Receive and transmit sections clocked at different rates
Fractional stop bits
Built-in multidrop modes
Freeze mode for implementing flow control
Isochronous (1× clock) operation (A 16× clock is required for UART operation.)
Interrupts on special control character reception
Ability to transmit data on demand using the TODR
SCCS register to determine idle status of the receive signal
Other features for the SCCs as described in the GSMR
However, SMCs allow a data length of up to 14 bits; SCCs support up to 8 bits.
SMCLK
16x
(not to scale)
SMTXD
Start
Bit
5 to 14 Data Bits with the
Least Significant Bit First
Parity
Bit
1 or 2
Stop Bits
(Optional)
Figure 27-5. SMC UART Frame Format
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27.3.1 Features
The following list summarizes the main features of the SMC in UART mode:
•
•
•
•
•
•
•
•
Flexible message-oriented data structure
Programmable data length (5–14 bits)
Programmable 1 or 2 stop bits
Even/odd/no parity generation and checking
Frame error, break, and idle detection
Transmit preamble and break sequences
Received break character length indication
Continuous receive and transmit modes
27.3.2 SMC UART Channel Transmission Process
The UART transmitter is designed to work with almost no intervention from the core. When the core
enables the SMC transmitter, it starts sending idles. The SMC immediately polls the first BD in the
transmit channel BD table and once every character time after that, depending on character length. When
there is a message to transmit, the SMC fetches data from memory and starts sending the message.
When a BD data is completely written to the transmit FIFO, the SMC writes the message status bits into
the BD and clears R. An interrupt is issued if the I bit in the BD is set. If the next TxBD is ready, the data
from its buffer is appended to the previous data and sent over the transmit signal without any gaps between
buffers. If the next TxBD is not ready, the SMC starts sending idles and waits for the next TxBD to be
ready.
By appropriately setting the I bit in each BD, interrupts can be generated after each buffer, a specific buffer,
or each block is sent. The SMC then proceeds to the next BD. If the CM bit is set in the TxBD, the R bit
is not cleared, allowing a buffer to be automatically resent next time the CP accesses this buffer. For
instance, if a single TxBD is initialized with the CM and W bits set, the buffer is sent continuously until R
is cleared in the BD.
27.3.3 SMC UART Channel Reception Process
When the core enables the SMC receiver, it enters hunt mode and waits for the first character. The CP then
checks the first RxBD to see if it is empty and starts storing characters in the buffer. When the buffer is
full or the MAX_IDL timer expires (if enabled), the SMC clears the E bit in the BD and generates an
interrupt if the I bit in the BD is set. If incoming data exceeds the buffer’s length, the SMC fetches the next
BD, and, if it is empty, continues transferring data to this BD’s buffer. If CM is set in the RxBD, the E bit
is not cleared, so the CP can overwrite this buffer on its next access.
27.3.4 Programming the SMC UART Controller
UART mode is selected by setting SMCMR[SM] to 0b10. See Section 27.2.1, “SMC Mode Registers
multibuffer operation and allows break and preamble sequences to be sent. Overrun, parity, and framing
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Serial Management Controllers (SMCs)
errors are reported via the BDs. At its simplest, the SMC UART controller functions in a character-oriented
environment, whereas each character is sent with the selected stop bits and parity. They are received into
separate 1-byte buffers. A maskable interrupt can be generated when each buffer is received.
Many applications can take advantage of the message-oriented capabilities that the SMC UART supports
through linked buffers for sending or receiving. Data is handled in a message-oriented environment, so
entire messages can be handled instead of individual characters. A message can span several linked
buffers; each one can be sent and received as a linked list of buffers without core intervention, which
simplifies programming and saves processor overhead. In a message-oriented environment, an idle
sequence is used as the message delimiter. The transmitter can generate an idle sequence before starting a
new message and the receiver can close a buffer when an idle sequence is found.
27.3.5 SMC UART Transmit and Receive Commands
Table 27-4 on page 27-12 describes transmit commands issued to the CPCR.
Table 27-4. Transmit Commands
Command
Description
STOP
Disables transmission of characters on the transmit channel. If the SMC UART controller receives this
command while sending a message, it stops sending. The SMC UART controller finishes sending any
data that has already been sent to its FIFO and shift register and then stops sending data. The TBPTR
is not advanced when this command is issued. The SMC UART controller sends a programmable
number of break sequences and then sends idles. The number of break sequences, which can be zero,
should be written to the BRKCR before this command is issued to the SMC UART controller.
TRANSMIT
RESTART
TRANSMIT
Enables characters to be sent on the transmit channel. The SMC UART controller expects it after
disabling the channel in its SMCMR and after issuing the STOP TRANSMIT command. The SMC UART
controller resumes transmission from the current TBPTR in the channel’s TxBD table.
INIT TX
Initializes transmit parameters in this serial channel’s parameter RAM to their reset state and should
PARAMETERS only be issued when the transmitter is disabled. The INIT TX and RX PARAMETERS command can also be
used to reset the transmit and receive parameters.
Table 27-5 describes receive commands issued to the CPCR.
Table 27-5. Receive Commands
Command
Description
ENTER HUNT Use the CLOSE RXBD command instead ENTER HUNT MODE for an SMC UART channel.
MODE
CLOSE RXBD Forces the SMC to close the current receive BD if it is currently being used and to use the next BD in
the list for any subsequently received data. If the SMC is not receiving data, no action is taken.
INIT RX
Initializes receive parameters in this serial channel parameter RAM to reset state. Issue it only if the
PARAMETERS receiver is disabled. INIT TX AND RX PARAMETERS resets both receive and transmit parameters.
27.3.6 Sending a Break
A break is an all-zeros character without stop bits. It is sent by issuing a STOP TRANSMIT command. After
sending any outstanding data, the SMC sends a character of consecutive zeros, the number of which is the
sum of the character length, plus the number of start, parity, and stop bits. The SMC sends a programmable
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number of break characters according to BRKCR and then reverts to idle or sends data if a RESTART
TRANSMIT is issued before completion. When the break completes, the transmitter sends at least one idle
character before sending any data to guarantee recognition of a valid start bit.
27.3.7 Sending a Preamble
A preamble sequence provides a way to ensure that the line is idle before a new message transfer begins.
The length of the preamble sequence is constructed of consecutive ones that are one-character long. If the
preamble bit in a BD is set, the SMC sends a preamble sequence before sending that buffer. For 8 data bits,
no parity, 1 stop bit, and 1 start bit, a preamble of 10 ones would be sent before the first character in the
buffer. If no preamble sequence is sent, data from two ready transmit buffers can be sent on the transmit
signal with no delay between them.
27.3.8 Handling Errors in the SMC UART Controller
The SMC UART controller reports character reception error conditions via the channel BDs and the
SMCE. Table 27-6 describes the reception errors. The SMC UART controller has no transmission errors.
Table 27-6. SMC UART Errors
Error
Description
Overrun
The SMC maintains a two-character length FIFO for receiving data. Data is moved to the buffer after the
first character is received into the FIFO; if a receiver FIFO overrun occurs, the channel writes the
received character into the internal FIFO. It then writes the character to the buffer, closes it, sets the OV
bit in the BD, and generates the RXB interrupt if it is enabled. Reception then resumes as normal.
Overrun errors that occasionally occur when the line is idle can be ignored.
Parity
The channel writes the received character to the buffer, closes it, sets the PR bit in the BD, and
generates the RXB interrupt if it is enabled. Reception then resumes as normal.
Idle
Sequence
Receive
An idle is found when a character of all ones is received, at which point the channel counts consecutive
idle characters. If the count reaches MAX_IDL, the buffer is closed and an RXB interrupt is generated.
If no receive buffer is open, this does not generate an interrupt or any status information. The idle
counter is reset each time a character is received.
Framing
The SMC received a character with no stop bit. When it occurs, the channel writes the received
character to the buffer, closes the buffer, sets FR in the BD, and generates the RXB interrupt if it is
enabled. When this error occurs, parity is not checked for the character.
Break
Sequence
The SMC receiver received an all-zero character with a framing error. The channel increments BRKEC,
generates a maskable BRK interrupt in SMCE, measures the length of the break sequence, and stores
this value in BRKLN. If the channel was processing a buffer when the break was received, the buffer is
closed with the BR bit in the RxBD set. The RXB interrupt is generated if it is enabled.
27.3.9 SMC UART RxBD
Using the BDs, the CP reports information about the received data on a per-buffer basis. Then it closes the
current buffer, generates a maskable interrupt, and starts receiving data into the next buffer after one of the
following occurs:
•
•
An error is received during message processing
A full receive buffer is detected
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•
A programmable number of consecutive idle characters are received
Figure 27-6 shows the format of the SMC UART RxBD.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Offset + 0
Offset + 2
Offset + 4
Offset + 6
E
—
W
I
—
CM
ID
—
BR
FR
PR
—
OV
—
Data Length
Rx Data Buffer Pointer
Figure 27-6. SMC UART RxBD
Table 27-7 describes RxBD fields.
Table 27-7. SMC UART RxBD Field Descriptions
Bit
Name
E
Description
0
Empty.
0 The buffer is full or data reception stopped due to an error. The core can read or write any fields
of this RxBD. The CP does not use this BD while E is zero.
1 The buffer is empty or reception is in progress. This RxBD and its buffer are owned by the CP.
Once E is set, the core should not write any fields of this RxBD.
1
2
—
Reserved, should be cleared.
W
Wrap (last BD in RxBD table).
0 Not the last BD in the table.
1 Last BD in the table. After this buffer is used, the CP receives incoming data into the first BD that
RBASE points to in the table. The number of RxBDs in this table is determined only by the W bit
and overall space constraints of the dual-port RAM.
3
I
Interrupt.
0 No interrupt is generated after this buffer is filled.
1 The SMCE[RXB] is set when this buffer is completely filled by the CP, indicating the need for the
core to process the buffer. RXB can cause an interrupt if it is enabled.
4–5
6
—
Reserved, should be cleared.
CM
Continuous mode.
0 Normal operation.
1 The CP does not clear the E bit after this BD is closed, allowing the CP to automatically overwrite
the buffer when it next accesses the BD. However, E is cleared if an error occurs during reception,
regardless of how CM is set.
7
ID
Buffer closed on reception of idles. Set when the buffer has closed because a programmable
number of consecutive idle sequences is received. The CP writes ID after received data is in the
buffer.
8–9
10
—
Reserved, should be cleared.
BR
Buffer closed on reception of break. Set when the buffer closes because a break sequence was
received. The CP writes BR after the received data is in the buffer.
11
FR
Framing error. Set when a character with a framing error is received and located in the last byte of
this buffer. A framing error is a character with no stop bit. A new receive buffer is used to receive
additional data. The CP writes FR after the received data is in the buffer.
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Table 27-7. SMC UART RxBD Field Descriptions (continued)
Bit
Name
Description
12
PR
Parity error. Set when a character with a parity error is received in the last byte of the buffer. A new
buffer is used for additional data. The CP writes PR after received data is in the buffer.
13
14
—
Reserved, should be cleared.
OV
Overrun. Set when a receiver overrun occurs during reception. The CP writes OV after the received
data is in the buffer.
15
—
Reserved, should be cleared.
Data length represents the number of octets the CP writes into the buffer. After data is received in buffer,
the CP only writes them once as the BD closes. Note that the memory allocated for this buffer should be
no smaller than MRBLR. The Rx data buffer pointer points to the first location of the buffer and must be
showing RxBDs after they receive 10 characters, an idle period, and five characters (one with a framing
error). The example assumes that MRBLR = 8.
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MRBLR = 8 Bytes for this SMC
Buffer
Receive BD 0
E
0
ID
Status
Length
0
Byte 1
Byte 2
0008
Buffer Full
Pointer
32-Bit Buffer Pointer
8 Bytes
etc.
Byte 8
Receive BD 1
ID
Buffer
Byte 9
Byte 10
E
0
Status
Length
1
0002
8 Bytes
8 Bytes
8 Bytes
Idle Time-Out
Occurred
Pointer
32-Bit Buffer Pointer
Empty
Receive BD 2
Buffer
Byte 1
E
0
ID
0
FR
Status
Length
1
0004
Byte 2
Byte 4 has
Framing Error
Pointer
32-Bit Buffer Pointer
Byte 3
Byte 4 Error!
Empty
Receive BD 3
Buffer
Byte 5
E
1
Status
Length
XXXX
Additional Bytes
are Stored Unless
Idle Count Expires
(MAX_IDL)
Reception
Still in Progress
with this Buffer
Pointer
32-Bit Buffer Pointer
10 Characters
5 Characters
Long Idle Period
Characters
Received by UART
Fourth Character Present
has Framing Error! Time
Time
Figure 27-7. RxBD Example
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27.3.10 SMC UART TxBD
Data is sent to the CP for transmission on an SMC channel by arranging it in buffers referenced by the
channel TxBD table. Using the BDs, the CP confirms transmission or indicates error conditions so that the
0
1
2
3
4
5
6
7
8
15
Offset + 0
Offset + 2
Offset + 4
Offset + 6
R
—
W
I
—
CM
P
—
Data Length
Tx Data Buffer Pointer
Figure 27-8. SMC UART TxBD
Table 27-8 describes SMC UART TxBD fields.
Table 27-8. SMC UART TxBD Field Descriptions
Bits
Name
R
Description
0
Ready
0 The buffer is not ready for transmission; BD and its buffer can be altered. The CP clears R after
the buffer has been sent or an error occurs.
1 The buffer has not been completely sent. This BD cannot updated while R is set.
1
2
—
Reserved, should be cleared.
W
Wrap (final BD in the TxBD table)
0 Not the last BD in the table.
1 Last BD in the table. After this buffer is used, the CP receives incoming data into the first BD that
TBASE points to. The number of TxBDs in this table is determined only by the W bit and overall
space constraints of the dual-port RAM.
3
I
Interrupt
0 No interrupt is generated after this buffer is serviced.
1 The SMCE[TXB] is set when this buffer is serviced. TXB can cause an interrupt if it is enabled.
4–5
6
—
Reserved, should be cleared.
CM
Continuous mode
0 Normal operation.
1 The CP does not clear R after this BD is closed and automatically retransmits the buffer when it
accesses this BD next.
7
P
Preamble
0 No preamble sequence is sent.
1 The UART sends one all-ones character before it sends the data so that the other end detects an
idle line before the data is received. If this bit is set and the data length of this BD is zero, only a
preamble is sent.
8–15
—
Reserved, should be cleared.
Data length represents the number of octets that the CP should transmit from this BD data buffer. However,
it is never modified by the CP and normally is greater than zero. It can be zero if P is set and only a
preamble is sent. If there are more than 8 bits in the UART character, data length should be even. For
example, to transmit three UART characters of 8-bit data, 1 start, and 1 stop, initialize the data length field
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to 3. To send three UART characters of 9-bit data, 1 start, and 1 stop, the data length field should 6, because
the three 9-bit data fields occupy three half words in memory (the 9 least-significant bits of each half
word).
Tx data buffer pointer points to the first location of the buffer. It can be even or odd, unless the number of
data bits in the UART character is greater than 8 bits. Then the buffer pointer must be even. For instance,
the pointer to 8-bit data, 1 start, and 1 stop characters can be even or odd, but the pointer to 9-bit data,
1 start, and 1 stop characters must be even. The buffer can reside in internal or external memory.
27.3.11 SMC UART Event Register (SMCE)/Mask Register (SMCM)
The SMC event register (SMCE) generates interrupts and report events recognized by the SMC UART
channel. When an event is recognized, the SMC UART controller sets the corresponding SMCE bit. Bits
are cleared by writing a 1; writing 0 has no effect. The SMC mask register (SMCM) has the same bit format
as SMCE. Setting an SMCM bit enables, and clearing it disables, the corresponding interrupt. All
unmasked bits must be cleared before the CP clears the internal interrupt request. Figure 27-9 represents
the SMCE/SMCM registers.
0
1
2
3
4
5
6
7
Field
Reset
R/W
—
BRKE
—
BRK
—
BSY
TXB
RXB
0
R/W
Addr
Figure 27-9. SMC UART Event Register (SMCE)/Mask Register (SMCM)
Table 27-9 describes SMCE/SMCM fields.
Table 27-9. SMCE/SMCM Field Descriptions
Bits
Name
Description
0
1
2
3
—
Reserved, should be cleared.
BRKE Break end. Set no sooner than after one idle bit is received after the break sequence.
Reserved, should be cleared.
—
BRK Break character received. Set when a break character is received. If a very long break sequence
occurs, this interrupt occurs only once after the first all-zeros character is received.
4
5
—
Reserved, should be cleared.
BSY Busy condition. Set when a character is received and discarded due to a lack of buffers. Set no
sooner than the middle of the last stop bit of the first receive character for which there is no available
buffer. Reception resumes when an empty buffer is provided.
6
7
TXB Tx buffer. Set when the transmit data of the last character in the buffer is written to the transmit FIFO.
Wait two character times to ensure that data is completely sent over the transmit signal.
RXB Rx buffer. Set when a buffer is received and its associated RxBD is closed. Set no sooner than the
middle of the last stop bit of the last character that is written to the receive buffer.
Figure 27-10 shows an example of the timing of various events in the SMCE.
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Characters
Received by SMC UART
10 Characters
Time
Line Idle
RX
RXD
Line Idle
Break
SMC UART SMCE
Events
RX
BRK
BRKE
NOTES:
1. The first RX event assumes receive buffers are 6 bytes each.
2. The second RX event position is programmable based on the MAX_IDL value.
3. The BRK event occurs after the first break character is received.
Characters
Transmitted by SMC UART
7 Characters
TXD
Line Idle
Line Idle
SMC UART SMCE
Events
TX
NOTES:
1. The TX event assumes all seven characters were put into a single buffer, and the TX event occurred when the seventh
character was written to the SMC transmit FIFO.
Figure 27-10. SMC UART Interrupts Example
27.3.12 SMC UART Controller Programming Example
The following initialization sequence assumes 9,600 baud, 8 data bits, no parity, and 1 stop bit in a 66-MHz
system. BRG1 and SMC1 are used. (The SMC transparent programming example uses an external clock
1. Configure the port D pins to enable SMTXD1 and SMRXD1. Set PPARD[8,9] and PDIRD[9].
Clear PDIRD[8] and PSORD[8,9].
2. Configure the BRG1. Write BRGC1 with 0x0001_035A. The DIV16 bit is not used and the divider
is 429 (decimal). The resulting BRG1 clock is 16× the preferred bit rate.
3. Connect BRG1 to SMC1 using the CPM mux by clearing CMXSMR[SMC1, SMC1CS].
4. In address 0x87FC, assign a pointer to the SMC1 parameter RAM.
5. Assuming one RxBD at the beginning of dual-port RAM followed by one TxBD, write RBASE
with 0x0000 and TBASE with 0x0008.
6. Write 0x1D01_0000 to CPCR to execute the INIT RX AND TX PARAMETERS command.
7. Write RFCR and TFCR with 0x10 for normal operation.
8. Write MRBLR with the maximum number of bytes per receive buffer. Assume 16 bytes, so
MRBLR = 0x0010.
9. Write MAX_IDL with 0x0000 in the SMC UART-specific parameter RAM to disable the
MAX_IDL functionality for this example.
10. Clear BRKLN and BRKEC in the SMC UART-specific parameter RAM.
11. Set BRKCR to 0x0001; if a STOP TRANSMIT COMMAND is issued, one break character is sent.
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12. Initialize the RxBD. Assume the Rx data buffer is at 0x0000_1000 in main memory. Write 0xB000
to RxBD[Status and Control], 0x0000 to RxBD[Data Length] (not required), and 0x0000_1000 to
RxBD[Buffer Pointer].
13. Assuming the Tx data buffer is at 0x0000_2000 in main memory and contains five 8-bit characters,
write 0xB000 to TxBD[Status and Control], 0x0005 to TxBD[Data Length], and 0x0000_2000 to
TxBD[Buffer Pointer].
14. Write 0xFF to the SMCE1 register to clear any previous events.
15. Write 0x57 to the SMCM1 register to enable all possible SMC1 interrupts.
16. Write 0x0000_1000 to the SIU interrupt mask register low (SIMR_L) so the SMC1 can generate a
system interrupt. Write 0xFFFF_FFFF to the SIU interrupt pending register low (SIPNR_L) to
clear events.
17. Write 0x4820 to SMCMR to configure normal operation (not loopback), 8-bit characters, no parity,
1 stop bit. The transmitter and receiver are not yet enabled.
18. Write 0x4823 to SMCMR to enable the SMC transmitter and receiver. This additional write
ensures that the TEN and REN bits are enabled last.
After 5 bytes are sent, the TxBD is closed. The receive buffer closes after receiving 16 bytes. Subsequent
data causes a busy (out-of-buffers) condition since only one RxBD is ready.
27.4 SMC in Transparent Mode
Compared to the SCC in transparent mode, the SMCs generally offer less functionality, which helps them
provide simpler functions and slower speeds. Transparent mode is selected by programming
protocol-specific bits in the SMCMR. The SMC in transparent mode does not support the following
features:
•
•
•
•
•
•
•
Independent transmit and receive clocks, unless connected to a TDM channel of an SIx
CRC generation and checking
Full RTS, CTS, and CD signals (supports only one SMSYN signal)
Ability to transmit data on demand using the TODR
Receiver/transmitter in transparent mode while executing another protocol
4-, 8-, or 16-bit SYNC recognition
Internal DPLL support
However, the SMC in transparent mode provides a data character length option of 4 to 16 bits, whereas the
SCCs provide 8 or 32 bits, depending on GSMR[RFW]. The SMC in transparent mode is also referred to
as the SMC transparent controller.
27.4.1 Features
The following list summarizes the features of the SMC in transparent mode:
•
•
Flexible data buffers
Connects to a TDM bus using the TSA in an SIx
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•
Transmits and receives transparently on its own set of signals using a sync signal to synchronize
the beginning of transmission and reception to an external event
•
•
•
•
Programmable character length (4–16)
Reverse data mode
Continuous transmission and reception modes
Four commands
27.4.2 SMC Transparent Channel Transmission Process
The transparent transmitter is designed to work with almost no core intervention. When the core enables
the SMC transmitter in transparent mode, it starts sending idles. The SMC immediately polls the first BD
in the transmit channel BD table and once every character time, depending on the character length (every
4 to 16 serial clocks). When there is a message to transmit, the SMC fetches the data from memory and
starts sending the message when synchronization is achieved.
Synchronization can be achieved in two ways. First, when the transmitter is connected to a TDM channel,
it can be synchronized to a time slot. Once the frame sync is received, the transmitter waits for the first bit
of its time slot before it starts transmitting. Data is sent only during the time slots defined by the TSA.
Secondly, when working with its own set of signals, the transmitter starts sending when SMSYNx is
asserted.
When a BD data is completely written to the transmit FIFO, the L bit is checked and if it is set, the SMC
writes the message status bits into the BD and clears the R bit. It then starts transmitting idles. When the
end of the current BD is reached and the L bit is not set, only R is cleared. In both cases, an interrupt is
issued according to the I bit in the BD. By appropriately setting the I bit in each BD, interrupts can be
generated after each buffer, a specific buffer, or each block is sent. The SMC then proceeds to the next BD.
If no additional buffers have been presented to the SMC for transmission and the L bit was cleared, an
underrun is detected and the SMC begins sending idles.
If the CM bit is set in the TxBD, the R bit is not cleared, so the CP can overwrite the buffer on its next
access. For instance, if a single TxBD is initialized with the CM and W bits set, the buffer is sent
continuously until R is cleared in the BD.
27.4.3 SMC Transparent Channel Reception Process
When the core enables the SMC receiver in transparent mode, it waits for synchronization before receiving
data. Once synchronization is achieved, the receiver transfers the incoming data into memory according
to the first RxBD in the table. Synchronization can be achieved in two ways. First, when the receiver is
connected to a TDM channel, it can be synchronized to a time slot. Once the frame sync is received, the
receiver waits for the first bit of its time slot to occur before reception begins. Data is received only during
the time slots defined by the TSA. Secondly, when working with its own set of signals, the receiver starts
reception when SMSYNx is asserted.
When the buffer full, the SMC clears the E bit in the BD and generates an interrupt if the I bit in the BD
is set. If incoming data exceeds the data buffer length, the SMC fetches the next BD; if it is empty, the
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Serial Management Controllers (SMCs)
SMC continues transferring data to this BD’s buffer. If the CM bit is set in the RxBD, the E bit is not
cleared, so the CP can automatically overwrite the buffer on its next access.
27.4.4 Using SMSYN for Synchronization
The SMSYN signal offers a way to externally synchronize the SMC channel. This method differs
somewhat from the synchronization options available in the SCCs and should be studied carefully. See
Figure 27-11 for an example.
Once SMCMR[REN] is set, the first rising edge of SMCLK that finds SMSYN low causes the SMC
receiver to achieve synchronization. Data starts being received or latched on the same rising edge of
SMCLK that latched SMSYN. This is the first bit of data received. The receiver does not lose
synchronization again, regardless of the state of SMSYN, until REN is cleared.
Once SMCMR[TEN] is set, the first rising edge of SMCLK that finds SMSYN low synchronizes the SMC
transmitter which begins sending ones asynchronously from the falling edge of SMSYN. After one
character of ones is sent, if the transmit FIFO is loaded (the TxBD is ready with data), data starts being
send on the next falling edge of SMCLK after one character of ones is sent. If the transmit FIFO is loaded
later, data starts being sent after some multiple number of all-ones characters is sent.
Note that regardless of whether the transmitter or receiver uses SMSYN, it must make glitch-free
transitions from high-to-low or low-to-high. Glitches on SMSYN can cause errant behavior of the SMC.
The transmitter never loses synchronization again, regardless of the state of SMSYN, until the TEN bit is
cleared or an ENTER HUNT MODE command is issued.
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Serial Management Controllers (SMCs)
SMCLK
SMSYN
SMTXD
1s are sent
Five 1s are sent
SMC1 Transmit Data
TEN set
here
SMSYN
detected
low here approximatelycharacter
Tx FIFO
loaded
Five 1s
assume
First bit of
first 5-bit
transmit
character
(lsb)
Transmission
could begin
here if Tx FIFO
not loaded
here
length
equals 5
in time
SMCLK
SMSYN
SMRXD
SMC1 Receive Data
REN set SMSYN
here or detected of receive
First bit
NOTES:
1. SMCLK is an internal clock derived from an external
enter hunt low here
mode
command
issued
data
(lsb)
CLKx or a baud rate generator.
2. This example shows the SMC receiver and transmitter
enabled separately. If the REN and TEN bits were set at
the same time, a single falling edge of SMSYN would
synchronize both.
Figure 27-11. Synchronization with SMSYNx
If both SMCMR[REN] and SMCMR[TEN] are set, the first falling edge of SMSYN causes both the
transmitter and receiver to achieve synchronization. The SMC transmitter can be disabled and reenabled
and SMSYN can be used again to resynchronize the transmitter itself. Section 27.2.4, “Disabling SMCs
On-the-Fly,” describes how to safely disable and reenable the SMC. Simply clearing and setting TEN may
be insufficient. The receiver can also be resynchronized this way.
27.4.5 Using the Time-Slot Assigner (TSA) for Synchronization
The TSA offers an alternative to using SMSYN to internally synchronize the SMC channel. This method
is similar, except that the synchronization event is the first time-slot for this SMC receiver/transmitter after
the frame sync indication rather than the falling edge of SMSYN. Chapter 15, “Serial Interface with
transmitter to be enabled simultaneously and synchronized separately; SMSYN does not provide this
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Serial Management Controllers (SMCs)
TDM Tx CLK
TDM Tx SYNC
SMC1
SMC1
TDM Tx
After TEN
is set,
transmission
begins here.
If SMC runs out of Tx buffers and new ones
are provided later, transmission begins at
the beginning of either time slot.
TDM Rx CLK
TDM Rx SYNC
TDM Rx
SMC1
SMC1
After REN is set or after
enter hunt mode command,
reception begins here.
Figure 27-12. Synchronization with the TSA
Once SMCMR[REN] is set, the first time-slot after the frame sync causes the SMC receiver to achieve
synchronization. Data is received immediately, but only during defined receive time slots. The receiver
continues receiving data during its defined time slots until REN is cleared. If an ENTER HUNT MODE
command is issued, the receiver loses synchronization, closes the buffer, and resynchronizes to the first
time slot after the frame sync.
Once SMCMR[TEN] is set, the SMC waits for the transmit FIFO to be loaded before trying to achieve
synchronization. When the transmit FIFO is loaded, synchronization and transmission begins depending
on the following:
•
•
•
If a buffer is made ready when the SMC2 is enabled, the first byte is placed in time slot 1 if CLSN
is 8 and to slot 2 if CLSN is 16.
If a buffer has its SMC enabled, then the first byte in the next buffer can appear in any time slot
associated with this channel.
If a buffer is ended with the L bit set, then the next buffer can appear in any time slot associated
with this channel.
If the SMC runs out of transmit buffers and a new buffer is provided later, idles are sent in the gap between
buffers. Data transmission from the later buffer begins at the start of an SMC time slot, but not necessarily
the first time slot after the frame sync. So, to maintain a certain bit alignment beginning with the first time
slot, make sure that at least one TxBD is always ready and that underruns do not occur. Otherwise, the
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Serial Management Controllers (SMCs)
describes how to safely disable and reenable the SMC. Simply clearing and setting TEN may not be
enough.
27.4.6 SMC Transparent Commands
Table 27-10 describes transmit commands issued to the CPCR.
Table 27-10. SMC Transparent Transmit Commands
Command
Description
STOP
After hardware or software is reset and the channel is enabled in the SMCM, the channel is in transmit
enable mode and polls the first BD. This command disables transmission of frames on the transmit
channel. If the transparent controller receives this command while sending a frame, it stops after the
contents of the FIFO are sent (up to 2 characters). The TBPTR is not advanced to the next BD, no new
BD is accessed, and no new buffers are sent for this channel. The transmitter sends idles until a
RESTART TRANSMIT command is issued.
TRANSMIT
RESTART
TRANSMIT
Starts or resumes transmission from the current TBPTR in the channel TxBD table. When the channel
receives this command, it polls the R bit in this BD. The SMC expects this command after a STOP
TRANSMIT is issued. The channel in its mode register is disabled or after a transmitter error occurs.
INIT TX
Initializes transmit parameters in this serial channel to reset state. Use only if the transmitter is disabled.
PARAMETERS The INIT TX AND RX PARAMETERS command resets transmit and receive parameters.
Table 27-11 describes receive commands issued to the CPCR.
Table 27-11. SMC Transparent Receive Commands
Command
Description
ENTER HUNT Forces the SMC to close the current receive BD if it is in use and to use the next BD for subsequent
MODE
data. If the SMC is not receiving data, the buffer is not closed. Additionally, this command causes the
receiver to wait for a resynchronization before reception resumes.
CLOSE RXBD Forces the SMC to close the current receive BD if it in use and to use the next BD in the list for
subsequent received data. If the SMC is not in the process of receiving data, no action is taken.
iNIT RX
Initializes receive parameters in this serial channel to reset state. Use only if the receiver is disabled.
PARAMETERS The INIT TX AND RX PARAMETERS command resets receive and transmit parameters.
27.4.7 Handling Errors in the SMC Transparent Controller
The SMC uses BDs and the SMCE to report message send and receive errors.
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Serial Management Controllers (SMCs)
Table 27-12. SMC Transparent Error Conditions
Descriptions
Error
Underrun
The channel stops sending the buffer, closes it, sets UN in the BD, and generates a TXE interrupt if it is
enabled. The channel resumes sending after a RESTART TRANSMIT command. Underrun cannot occur
between frames.
Overrun
The SMC maintains an internal FIFO for receiving data. If the buffer is in external memory, the CP
begins programming the SDMA channel when the first character is received into the FIFO. If a FIFO
overrun occurs, the SMC writes the received data character over the previously received character. The
previous character and its status bits are lost. Then the channel closes the buffer, sets OV in the BD,
and generates the RXB interrupt if it is enabled. Reception continues as normal.
27.4.8 SMC Transparent RxBD
Using BDs, the CP reports information about the received data for each buffer and closes the current
buffer, generates a maskable interrupt, and starts to receive data into the next buffer after one of the
following events:
•
•
•
An overrun error occurs.
A full receive buffer is detected.
The ENTER HUNT MODE command is issued.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Offset + 0
Offset + 2
Offset + 4
Offset + 6
E
—
W
I
—
CM
—
OV
—
Data Length
Rx Data Buffer Pointer
Figure 27-13. SMC Transparent RxBD
Table 27-13 describes SMC transparent RxBD fields.
Table 27-13. SMC Transparent RxBD Field Descriptions
Bits
Name
E
Description
0
Empty.
0 The buffer is full or reception was aborted due to an error. The core can read or write any fields
of this RxBD. The CP does not use this BD while E = 0.
1 The buffer is empty or is receiving data. The CP owns this RxBD and its buffer. Once E is set, the
core should not write any fields of this RxBD.
1
2
—
Reserved, should be cleared.
W
Wrap (last BD in RxBD table).
0 Not the last BD in the table.
1 Last BD in the table. After this buffer is used, the CP receives incoming data into the first BD that
RBASE points to. The number of RxBDs is determined only by the W bit and overall space
constraints of the dual-port RAM.
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Table 27-13. SMC Transparent RxBD Field Descriptions (continued)
Description
Bits
Name
I
3
Interrupt.
0 No interrupt is generated after this buffer is filled.
1 SMCE[RXB] is set when the CP completely fills this buffer indicating that the core must process
the buffer. The RXB bit can cause an interrupt if it is enabled.
4–5
6
—
Reserved, should be cleared.
CM
Continuous mode.
0 Normal operation.
1 The CP does not clear E after this BD is closed, allowing the buffer to be overwritten when the
CP next accesses this BD. However, E is cleared if an error occurs during reception, regardless
of how CM is set.
7–13
14
—
Reserved, should be cleared.
OV
Overrun. Set when a receiver overrun occurs during reception. The CP writes OV after the received
data is placed into the buffer.
15
—
Reserved, should be cleared.
Data length and buffer pointer fields are described in Section 20.2, “SCC Buffer Descriptors (BDs).”
27.4.9 SMC Transparent TxBD
Data is sent to the CP for transmission on an SMC channel by arranging it in buffers referenced by the
channel TxBD table. The CP uses BDs to confirm transmission or indicate error conditions so the
processor knows buffers have been serviced.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Offset + 0
Offset + 2
Offset + 4
Offset + 6
R
—
W
I
L
—
CM
—
UN
—
Data Length
Tx Data Buffer Pointer
Table 27-14. SMC Transparent TxBD
Table 27-15 describes SMC transparent TxBD fields.
Table 27-15. SMC Transparent TxBD Field Descriptions
Bits
Name
R
Description
0
Ready.
0 The buffer is not ready for transmission. The BD and buffer can be updated. The CP clears R after
the buffer is sent or after an error occurs.
1 The user-prepared data buffer is not sent or is being sent. BD fields cannot be updated if R is set.
1
—
Reserved, should be cleared.
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Serial Management Controllers (SMCs)
Table 27-15. SMC Transparent TxBD Field Descriptions
Description
Bits
Name
W
2
Wrap (final BD in table).
0 Not the last BD in the table.
1 Last BD in the table. After this buffer is used, the CP receives incoming data into the first BD that
TBASE points to. The number of TxBDs in this table is programmable and determined by theW
bit and overall space constraints of the dual-port RAM.
3
4
I
Interrupt.
0 No interrupt is generated after this buffer is serviced.
1 SMCE[TXB] or SMCE[TXE] are set when the buffer is serviced. They can cause interrupts if they
are enabled.
L
Last in message.
0 The last byte in the buffer is not the last byte in the transmitted transparent frame. Data from the
next transmit buffer (if ready) is sent immediately after the last byte of this buffer.
1 The last byte in this buffer is the last byte in the transmitted transparent frame. After this buffer is
sent, the transmitter requires synchronization before the next buffer is sent.
5
6
—
Reserved, should be cleared.
CM
Continuous mode.
0 Normal operation.
1 The CP does not clear R after this BD is closed, allowing the buffer to be automatically resent
when the CP accesses this BD again. However, the R bit is cleared if an error occurs during
transmission, regardless of how CM is set.
7–13
14
—
UM
—
Reserved, should be cleared.
Underrun. Set when the SMC encounters a transmitter underrun condition while sending the buffer.
Reserved, should be cleared.
15
Data length represents the number of octets the CP should transmit from this buffer. It is never modified
by the CP. The data length can be even or odd, but if the number of bits in the transparent character is
greater than 8, the data length should be even. For example, to transmit three transparent 8-bit characters,
the data length field should be initialized to 3. However, to transmit three transparent 9-bit characters, the
data length field should be initialized to 6 because the three 9-bit characters occupy three half words in
memory.
The data buffer pointer points to the first byte of the buffer. They can be even or odd, unless character
length is greater than 8 bits, in which case the transmit buffer pointer must be even. For instance, the
pointer to 8-bit transparent characters can be even or odd, but the pointer to 9-bit transparent characters
must be even. The buffer can reside in internal or external memory.
27.4.10 SMC Transparent Event Register (SMCE)/Mask Register (SMCM)
The SMC event register (SMCE) generates interrupts and reports events recognized by the SMC channel.
When an event is recognized, the SMC sets the corresponding SMCE bit. Interrupts are masked in the
SMCM, which has the same format as the SMCE. SMCE bits are cleared by writing a 1 (writing 0 has no
effect). Unmasked bits must be cleared before the CP clears the internal interrupt request. The SMCE and
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0
1
2
3
4
5
6
7
Field
Reset
R/W
—
TXE
—
BSY
TXB
RXB
0
R/W
Addr
Figure 27-14. SMC Transparent Event Register (SMCE)/Mask Register (SMCM)
Table 27-16 describes SMCE/SMCM fields.
Table 27-16. SMCE/SMCM Field Descriptions
Bits
Name
—
Description
0–2
3
Reserved, should be cleared.
TXE Tx error. Set when an underrun error occurs on the transmitter channel.
Reserved, should be cleared.
4
—
5
BSY Busy condition. Set when a character is received and discarded due to a lack of buffers. Reception
begins after a new buffer is provided. Executing an ENTER HUNT MODE command makes the receiver
wait for resynchronization.
6
7
TXB Tx buffer. Set after a buffer is sent. If the L bit of the TxBD is set, TXB is set when the last character
starts being sent. A one character-time delay is required to ensure that data is completely sent over
the transmit signal. If the L bit of the TxBD is cleared, TXB is set when the last character is written
to the transmit FIFO. A two character-time delay is required to ensure that data is completely sent.
RXB Rx buffer. Set when a buffer is received (after the last character is written) on the SMC channel and
its associated RxBD is now closed.
27.4.11 SMC Transparent NMSI Programming Example
The following example initializes the SMC1 transparent channel over its own set of signals. The CLK9
signal supplies the transmit and receive clocks; the SMSYNx signal is used for synchronization. (The SMC
UART programming example uses a BRG configuration; see Section 27.3.12, “SMC UART Controller
1. Configure the port D pins to enable SMTXD1, SMRXD1, and SMSYN1. Set PPARD[7,8,9] and
PDIRD[9]. Clear PDIRD[7,8] and PSORD[7,8,9].
2. Configure the port C pins to enable CLK9. Set PPARC[23]. Clear PDIRC[23] and PSORC[23].
3. Connect CLK9 to SMC1 using the CPM mux. Clear CMXSMR[SMC1] and program
CMXSMR[SMC1CS] to 0b11.
4. In address 0x87FC, assign a pointer to the SMC1 parameter RAM.
5. Write RBASE and TBASE in the SMC parameter RAM to point to the RxBD and TxBD in the
dual-port RAM. Assuming one RxBD at the beginning of the dual-port RAM followed by one
TxBD, write RBASE with 0x0000 and TBASE with 0x0008.
6. Write 0x1D01_0000 to CPCR to execute the INIT RX AND TX PARAMETERS command.
7. Write RFCR and TFCR with 0x10 for normal operation.
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Serial Management Controllers (SMCs)
8. Write MRBLR with the maximum bytes per receive buffer. Assuming 16 bytes MRBLR = 0x0010.
9. Initialize the RxBD assuming the buffer is at 0x0000_1000 in main memory. Write 0xB000 to
RxBD[Status and Control], 0x0000 to RxBD[Data Length] (optional), and 0x0000_1000 to
RxBD[Buffer Pointer].
10. Initialize the TxBD assuming the Tx buffer is at 0x0000_2000 in main memory and contains five
8-bit characters. Write 0xB800 to TxBD[Status and Control], 0x0005 to TxBD[Data Length], and
0x0000_2000 to TxBD[Buffer Pointer].
11. Write 0xFF to SMCE1 to clear any previous events.
12. Write 0x13 to SMCM1 to enable all possible SMC1 interrupts.
13. Write 0x0000_1000 to the SIU interrupt mask register low (SIMR_L) so the SMC1 can generate a
system interrupt. Write 0xFFFF_FFFF to the SIU interrupt pending register low (SIPNR_L) to
clear events.
14. Write 0x3830 to the SMCMR to configure 8-bit characters, unreversed data, and normal operation
(not loopback). The transmitter and receiver are not enabled yet.
15. Write 0x3833 to the SMCMR to enable the SMC transmitter and receiver. This additional write
ensures that TEN and REN are enabled last.
After 5 bytes are sent, the TxBD is closed; after 16 bytes are received the receive buffer is closed. Any data
received after 16 bytes causes a busy (out-of-buffers) condition since only one RxBD is prepared.
27.5 The SMC in GCI Mode
The SMC can control the C/I and monitor channels of the GCI frame. When using the SCIT configuration
of a GCI, one SMC can handle SCIT channel 0 and the other can handle SCIT channel 1. The main features
of the SMC in GCI mode are as follows:
•
Each SMC channel supports the C/I and monitor channels of the GCI (IOM-2) in ISDN
applications
•
•
•
Two SMCs support both sets of C/I and monitor channels in SCIT channels 0 and 1
Full-duplex operation
Local loopback and echo capability for testing
To use the SMC GCI channels properly, the TSA must be configured to route the monitor and C/I channels
to the preferred SMC. Chapter 15, “Serial Interface with Time-Slot Assigner,” describes how to program
this configuration. GCI mode is selected by setting SMCMR[SM] to 0b10. Section 27.2.1, “SMC Mode
Registers (SMCMR1/SMCMR2),” describes other protocol-specific SMCMR bits.
27.5.1 SMC GCI Parameter RAM
The GCI parameter RAM differs from that for UART and transparent mode. The CP accesses each SMC’s
GCI parameter table using a user-programmed pointer (SMCx_BASE) located in the parameter RAM; see
aligned address in the dual-port RAM’s general-purpose area (banks 1–8, 11 and 12). In GCI mode,
page 27-6 to see the differences. (In GCI mode, the SMC has no extra protocol-specific parameter RAM.)
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Table 27-17. SMC GCI Parameter RAM Memory Map
1
Offset
Name
Width
Description
0x00
M_RxBD
Half
word
0x02
0x04
0x06
0x08
0x0C
0x0E
0x10
0x12
M_TxBD
Half
word
CI_RxB
D
Half
word
CI_TxB
D
Half
word
RSTATE
Word
Rx/Tx Internal State
Monitor Rx Data
Monitor Tx Data
C/I Rx Data
2
2
M_RxD
Half
word
2
M_TxD
Half
word
CI_RxD
Half
word
2
2
CI_TxD
Half
C/I Tx Data
word
1
2
From the pointer value programmed in SMCx_BASE: SMC1_BASE at 0x87FC, SMC2_BASE at 0x88FC.
RSTATE, M_RxD, M_TxD, CI_RxD, and CI_TxD do not need to be accessed by the user in normal operation, and are
reserved for RISC use only.
27.5.2 Handling the GCI Monitor Channel
The following sections describe how the GCI monitor channel is handled.
27.5.2.1 SMC GCI Monitor Channel Transmission Process
Monitor channel 0 is used to exchange data with a layer 1 device (reading and writing internal registers
and transferring of the S and Q bits). Monitor channel 1 is used for programming and controlling
voice/data modules such as CODECs. The core writes the byte into the TxBD. The SMC sends the data
on the monitor channel and handles the A and E control bits according to the GCI monitor channel
protocol. The TIMEOUT command resolves deadlocks when errors in the A and E bit states occur on the
data line.
27.5.2.2 SMC GCI Monitor Channel Reception Process
The SMC receives data and handles the A and E control bits according to the GCI monitor channel
protocol. When the CP stores a received data byte in the SMC RxBD, a maskable interrupt is generated.
A TRANSMIT ABORT REQUEST command causes the PowerQUICC II to send an abort request on the E bit.
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Serial Management Controllers (SMCs)
27.5.3 Handling the GCI C/I Channel
The C/I channel is used to control the layer 1 device. The layer 2 device in the TE sends commands and
receives indication to or from the upstream layer 1 device through C/I channel 0. In the SCIT
configuration, C/I channel 1 is used to convey real-time status information between the layer 2 device and
nonlayer 1 peripheral devices (CODECs).
27.5.3.1 SMC GCI C/I Channel Transmission Process
The core writes the data byte into the C/I TxBD and the SMC transmits the data continuously on the C/I
channel to the physical layer device.
27.5.3.2 SMC GCI C/I Channel Reception Process
The SMC receiver continuously monitors the C/I channel. When it recognizes a change in the data and this
value is received in two successive frames, it is interpreted as valid data. This is called the double last-look
method. The CP stores the received data byte in the C/I RxBD and a maskable interrupt is generated. If the
SMC is configured to support SCIT channel 1, the double last-look method is not used.
27.5.4 SMC GCI Commands
Table 27-18. SMC GCI Commands
Command
Description
INIT TX AND
RX
Initializes transmit and receive parameters in the parameter RAM to their reset state. It is especially
useful when switching protocols on a given serial channel.
PARAMETERS
TRANSMIT
ABORT
This receiver command can be issued when the PowerQUICC II implements the monitor channel
protocol. When it is issued, the PowerQUICC II sends an abort request on the A bit.
REQUEST
TIMEOUT
This transmitter command can be issued when the PowerQUICC II implements the monitor channel
protocol. It is usually issued because the device is not responding or A bit errors are detected. The
PowerQUICC II sends an abort request on the E bit at the time this command is issued.
27.5.5 SMC GCI Monitor Channel RxBD
This BD, seen in Figure 27-15, is used by the CP to report information about the monitor channel receive
byte.
0
1
2
3
4
7
8
15
Offset + 0
E
l
ER
MS
—
DATA
Figure 27-15. SMC Monitor Channel RxBD
Table 27-19 describes SMC monitor channel RxBD fields.
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Table 27-19. SMC Monitor Channel RxBD Field Descriptions
Description
Bits
Name
E
0
Empty.
0 The CP clears E when the byte associated with this BD is available to the core.
1 The core sets E when the byte associated with this BD has been read.
1
2
3
L
Last (EOM). Valid only for monitor channel protocol and is set when the EOM indication is received
on the E bit. Note that when this bit is set, the data byte is invalid.
ER
MS
Error condition. Valid only for monitor channel protocol. Set when an error occurs on the monitor
channel protocol. A new byte is sent before the SMC acknowledges the previous byte.
Data mismatch. Valid only for monitor channel protocol. Set when two different consecutive bytes
are received; cleared when the last two consecutive bytes match. The SMC waits for the reception
of two identical consecutive bytes before writing new data to the RxBD.
4–7
—
Reserved, should be cleared.
8–15
DATA Data field. Contains the monitor channel data byte that the SMC received.
27.5.6 SMC GCI Monitor Channel TxBD
0
1
2
3
7
8
15
Offset + 0
R
L
AR
—
DATA
Figure 27-16. SMC Monitor Channel TxBD
Table 27-20 describes SMC monitor channel TxBD fields.
Table 27-20. SMC Monitor Channel TxBD Field Descriptions
Bits
Name
R
Description
0
Ready.
0 Cleared by the CP after transmission. The TxBD is now available to the core.
1 Set by the core when the data byte associated with this BD is ready for transmission.
1
2
L
Last (EOM). Valid only for monitor channel protocol. When L = 1, the SMC first transmits the buffer
data and then transmits the EOM indication on the E bit.
AR
—
Abort request. Valid only for monitor channel protocol. Set by the SMC when an abort request is
received on the A bit. The transmitter sends the EOM on the E bit after receiving an abort request.
3–7
Reserved, should be cleared.
8–15
DATA Data field. Contains the data to be sent by the SMC on the monitor channel.
27.5.7 SMC GCI C/I Channel RxBD
The CP uses this BD, seen in Figure 27-17, to report information about the C/I channel receive byte.
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Serial Management Controllers (SMCs)
0
1
7
8
13
14
15
Offset + 0
E
—
C/I DATA
—
Figure 27-17. SMC C/I Channel RxBD
Table 27-21 describes SMC C/I channel RxBD fields.
Table 27-21. SMC C/I Channel RxBD Field Descriptions
Bits
Name
E
Description
0
Empty.
0 Cleared by the CP to indicate that the byte associated with this BD is available to the core.
1 The core sets E to indicate that the byte associated with this BD has been read.
Note that additional data received is discarded until E bit is set.
1–7
—
Reserved, should be cleared.
8–13
C/I
Command/indication data bits. For C/I channel 0, bits 10–13 contain the 4-bit data field and bits 8–9
DATA are always written with zeros. For C/I channel 1, bits 8–13 contain the 6-bit data field.
14–15
—
Reserved, should be cleared.
27.5.8 SMC GCI C/I Channel TxBD
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Offset + 0
R
—
C/I DATA
—
Figure 27-18. SMC C/I Channel TxBD
Table 27-22 describes SMC C/I channel TxBD fields.
Table 27-22. SMC C/I Channel TxBD Field Descriptions
Bits
Name
R
Description
0
Ready.
0 Cleared by the CP after transmission to indicate that the BD is available to the core.
1 Set by the core when data associated with this BD is ready for transmission.
1–7
—
Reserved, should be cleared.
8–13
C/I
Command/indication data bits. For C/I channel 0, bits 10–13 hold the 4-bit data field (bits 8 and 9
DATA are always written with zeros). For C/I channel 1, bits 8–13 contain the 6-bit data field.
14–15
—
Reserved, should be cleared.
27.5.9 SMC GCI Event Register (SMCE)/Mask Register (SMCM)
The SMCE generates interrupts and report events recognized by the SMC channel. When an event is
recognized, the SMC sets its corresponding SMCE bit. SMCE bits are cleared by writing ones; writing
zeros has no effect. SMCM has the same bit format as SMCE. Setting an SMCM bit enables, and clearing
an SMCM bit disables, the corresponding interrupt. Unmasked bits must be cleared before the CP clears
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Serial Management Controllers (SMCs)
registers.
0
1
2
3
4
5
6
7
Field
Reset
R/W
—
CTXB
CRXB
MTXB
MRXB
0000_0000
R/W
Addr
Figure 27-19. SMC GCI Event Register (SMCE)/Mask Register (SMCM)
Table 27-23 describes SMCE/SMCM fields.
Table 27-23. SMCE/SMCM Field Descriptions
Bits
Name
Description
0–3
4
—
Reserved, should be cleared.
CTXB C/I channel buffer transmitted. Set when the C/I transmit buffer is now empty.
CRXB C/I channel buffer received. Set when the C/I receive buffer is full.
5
6
MTXB Monitor channel buffer transmitted. Set when the monitor transmit buffer is now empty.
MRXB Monitor channel buffer received. Set when the monitor receive buffer is full.
7
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Chapter 28
Multi-Channel Controllers (MCCs)
NOTE
The MPC8250 and the MPC8255 have only one MCC.
The signalling system #7 (SS7) functionality described in this chapter is not
available on rev A.1 .29µm (HiP3) silicon.
Refer to www.freescale.com for the latest RAM microcode packages that
support enhancements.
A multi-channel controller (MCC) allows the PowerQUICC II to support up to 128 separate time-division
serial channels on one peripheral. The PowerQUICC II has two MCCs. Each MCC is paired with a serial
interface (SI), allowing the MCC to communicate over any of that SI’s 4 time-division multiplexed streams
(TDM).
An MCC’s channels are assigned to a particular TDM in subgroups of 32 channels. MCC1’s channels
(0-127) may not be programmed to work with SI2, nor MCC2’s channels (128-255) to work with SI1. Each
channel of an MCC can be programmed to perform in a mode separate from the other channels of that
MCC.
Proper programming of the SI and SIRAM is responsible for the routing of timeslots within a TDM stream
to the appropriate MCC channel at the desired time. Programming the SI is covered in Chapter 15, “Serial
proceeding.
Each MCC has the following features:
•
•
•
•
Up to 128 independent HDLC or transparent communication channels or up to 64 SS7 channels
Independent mapping for receive/transmit
Supports HDLC, transparent, or SS7 protocols on a per-channel basis
Supports additional circuit emulation service functionality when used in conjunction with ATM
AAL1
•
•
•
Supports interworking with AAL0
Up to 256 DMA channels with independent buffer descriptor (BD) tables
Five interrupt circular tables with programmable size and overflow identification. One for transmit
and four for receive.
•
•
•
Global loop mode
Individual channel loop mode
Efficient bus usage (no bus usage for inactive channel or for active channels with nothing to
transmit)
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Multi-Channel Controllers (MCCs)
•
•
•
•
•
•
•
•
Efficient control of the interrupts to the core
Uses external BD tables.
Uses on-chip dual-port RAM (DPRAM) for parameter storage
Uses 64-bit data transactions for reading and writing data in BDs
Supports automatic routing in transparent mode using negative empty polarity
Supports inverted data per channel
Supports super channel synchronization in transparent mode (slot synchronization)
Supports in-line synchronization in transparent mode (synchronization on a pattern of 1 or 2 bytes)
28.1 MCC Operation Overview
Each MCC relies upon its corresponding SI block as its physical interface to a TDM. Once an SI’s TDM
has been programmed to contain MCC-related timeslots (accomplished via SIRAM programming) and has
been enabled, the SI clocks data out of an MCC channel's TX FIFO or clocks data into an MCC channel's
RX FIFO as appropriate. Note that the SI contains no data buffering; data moving to or from an MCC
channel’s FIFO is clocked directly through the SI to or from the TDM data lines.
Activity in an MCC channel’s FIFO triggers a request to the CPM. The CPM then uses a variety of
MCC-related data structures to handle that channel’s traffic. MCC global parameters govern the overall
state of the MCC block and also contain some threshold settings and base pointers used by all channels for
their operation. There is also one set of channel-specific parameters and channel-extra parameters per
MCC channel, containing protocol state information for that channel and pointers to that particular
channel's receive and transmit buffer descriptors. These parameter RAM areas are described in more detail
in the following sections.
Note that the channel-specific parameter area may be interpreted differently depending on what protocol
is being used on that particular channel, whether it is HDLC, transparent, or SS7. If an MCC channel is
being used in conjunction with AAL1 CES, there are additional programming model changes that take
place. Also, if a TDM is programmed to make use of superchannelled MCC timeslots, a structure called
the Superchannel Table is also used. All these parameter RAM areas are described in more detail in the
following sections.
28.1.1 MCC Data Structure Organization
Each MCC uses the following data structures:
•
Global MCC parameters (common to all the 128 channels of that MCC) placed in the DPRAM
from the offset (relative to the DPRAM base address) defined in Table 14-10 on page 14-21.
•
Channel-specific parameters. In HDLC and transparent modes each channel uses 64 bytes of
specific parameters placed in the DPRAM at offset 64*CH_NUM (relative to the DPRAM base
address). In SS7 mode each channel uses 128 bytes of specific parameters placed DPRAM at offset
128*CH_NUM. CH_NUM is the channel number (0–127 for MCC1 and 128–255 for MCC2).
Channel-specific parameters are described in the following sections:
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Multi-Channel Controllers (MCCs)
Note that the DPRAM memory corresponding to the inactive channels can be used for other
purposes.
•
•
•
Channel extra parameters. Each channel use 8 bytes of extra parameters placed in the DPRAM at
offset XTRABASE + 8*CH_NUM (relative to the DPRAM base address). XTRABASE is one of
DPRAM memory corresponding to the inactive channels can be used for other purposes.
Superchannel table (used only if superchannelled timeslots are defined in SIRAM programming).
This table is placed in the DPRAM from the offset SCTPBASE (relative to the DPRAM base
address). SCTPBASE is one of the global MCC parameters. The super channel table is described
BD tables placed in the external memory. All the BD tables associated with one MCC must reside
in a 512-KByte segment. The absolute base addresses of a channel BD table is MCCBASE +
8*RBASE (for the receiver) and MCCBASE + 8*TBASE (for the transmitter). MCCBASE is one
of the global MCC parameters and RBASE/TBASE are channel extra parameters. Each BD table
is a circular queue. One BD includes status bits, start address and length of a data buffer.
Figure 28-1 shows the BD structure for one MCC.
•
•
Circular interrupt tables placed in the external memory. There is one table for the transmitter
interrupts (base address TINTBASE) and between one and four tables for receiver interrupts (base
address RINTBASE0–RINTBASE4). TINTBASE and RINTBASE0–RINTBASE4 are global
MCC parameters.
Buffer Descriptor
Table Base Address
External Memory
DPRAM
DPRAM_base
Channel 0 Parameter
Channel 1 Parameter
x8
Channel j Extra
Parameter
RBASE
TBASE
+
Channel j RxBD
Table
512 Kbytes
Global MCC
Parameters
MCCBASE
x8
+
Channel j TxBD
Table
Figure 28-1. BD Structure for One MCC
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Multi-Channel Controllers (MCCs)
28.2 Global MCC Parameters
Table 28-1. Global MCC Parameters
1
Offset
Name
Width
Description
0x00
MCCBASE Word MCC base pointer. User-initialized parameter points to the starting address of a
512-Kbyte BD segment in external memory.
0x04
0x06
MCCSTATE Hword MCC state. Used by the CP for global state definition. Should be cleared during
initialization.
MRBLR
Hword Maximum receive buffer length (user-initialized). Defines the maximum number of
bytes written to a receive buffer before moving to the next buffer for this channel. This
value must be a multiple of 8.
0x08
GRFTHR
Hword Global receive frame threshold. Used to reduce interrupt overhead that would
otherwise occur when many short HDLC frames arrive that each cause an RXF
interrupt. Programming GRFTHR can be used to limit the frequency of RXF
interrupts. In normal operation, an unmasked RXF event is written to the interrupt
table on each received frame. However, a user may choose to mask the RXF event
and program GRFTHR instead. If the user places a non-zero value in GRFTHR,
RINTx is asserted in the MCC event register when the number of RXF events reaches
the GRFTHR value. Therefore, note that in addition to indicating new interrupt queue
entries, the assertion of RINTx could then also be due to the threshold of received
frames being reached due to activity on any of this MCC’s receive channels.
Therefore, software should look for frames in all active buffer descriptor rings. This
parameter does not need to be reset after an interrupt.
0x0A
0x0C
GRFCNT
Hword Global receive frame count. A down counter used to implement the GRFTHR feature.
It should be initialized to the GRFTHR value. The CP writes an entry in a circular
interrupt table and decrements GRFCNT each time a frame is received. When
GRFCNT reaches zero, the CP generates an interrupt and re-initializes GRFCNT with
GRFTHR. This parameter does not need to be reset after an interrupt.
RINTTMP
Word Temporary location for holding the receive interrupt queue entry, used by the CP
(reserved)
0x10
0x14
0x18
DATA0
DATA1
Word Temporary location for holding data, used by the CP (reserved)
Word Temporary location for holding data, used by the CP (reserved)
TINTBASE Word Multi-channel transmitter circular interrupt table base address. The interrupt circular
table is a cyclic table (FIFO-like). Each table entry contains information about an
interrupt request generated by the MCC to the host.
0x1C
0x20
TINTPTR
Word Pointer to the transmitter circular interrupt table. The CP writes the next interrupt
information to this entry when an exception occurs. The user must copy the
TINTBASE value to TINTPTR before enabling interrupts. Further updates of the
TINTPTR are done by the CP.
TINTTMP
Word Temporary location for holding the transmit interrupt queue entry, used by the CP. The
60x initializes this field before initializing the MCC. The user must clear it before
enabling interrupts.
0x24
0x26
SCTPBASE Hword Internal pointer for the super channel transmit table, offset from the DPRAM address
Hword
—
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Table 28-1. Global MCC Parameters (continued)
Width Description
1
Offset
Name
0x28
C_MASK32 Word CRC constant (user initialized to 0xDEBB20E3). Used for 32-bit CRC-CCITT
calculation if HDLC mode is chosen for a selected channel. (This option is
programmable. For each HDLC channel, one of two CRC-CCITT can be selected
through the CHAMR.)
0x2C
0x2E
XTRABASE Hword Pointer the beginning of the extra parameters information, offset from the DPRAM
address
C_MASK16 Hword CRC constant (user initialized to 0xF0B8). Used for 16-bit CRC-CCITT calculation if
HDLC mode is chosen for a selected channel. This option is programmable. For each
HDLC channel, one of two CRC-CCITT can be selected through the CHAMR.
0x30
0x34
0x38
0x3C
0x40
0x44
0x48
0x4C
0x50
0x54
0x58
0x5C
0x60
RINTTMP0 Word RINTTMPx. Temporary location for holding a receive circular interrupt circular table
entry (for tables 0–4), used by the CP. The user must clear it before enabling
RINTTMP1 Word
RINTTMP2 Word
RINTTMP3 Word
RINTBASE0 Word RINTBASEx—Multi-channel receiver circular interrupt table base address. The
interrupt circular table is a cyclic table (FIFO-like). Each table entry contains
information about an interrupt request generated by the MCC to the host.
RINTPTR0 Word
RINTPTRx—Pointer to the receiver circular interrupt table. The CP writes the next
interrupt information to this entry when an exception occurs. The user must copy the
RINTBASE1 Word
RINTPTR1 Word
RINTBASE2 Word
RINTPTR2 Word
RINTBASE3 Word
RINTPTR3 Word
RINTBASEx value to RINTPTRx before enabling interrupts. Further updates of the
RINTPTRx are done by the CP.
TS_TMP
Offset to MCC Base
Word Temporary place for time stamp
1
28.3 Channel-Specific Parameters
Each FIFO in the MCC is managed by a set of channel-specific parameters. These parameters can change
based upon what protocol is being used on that channel. The following sections describe the various
programming models used for an MCC channel.
28.3.1 Channel-Specific HDLC Parameters
Table 28-2 describes channel-specific parameters for HDLC.
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Multi-Channel Controllers (MCCs)
Table 28-2. Channel-Specific Parameters for HDLC
1
Offset
Name
Width
Description
0x00
TSTATE
Word Tx internal state. To start a transmitter channel the user must write to TSTATE
0x04
ZISTATE Word Zero-insertion machine state. User-initialized to one of the following values:
0x10000207 for regular channel transmitting all 1s before first frame of data
0x00000207 for regular channel transmitting flags before first frame of data
0x30000207 for inverted channel transmitting all 1s before first frame of data
0x20000207 for inverted channel transmitting flags before first frame of data
Note: Used in conjunction with ZIDATA0 and ZIDATA1.
0x08
0x0C
ZIDATA0 Word Zero-insertion high word data buffer. User-initialized to one of the following values:
0xFFFFFFFF allows transmission of all 1s before first frame of data
0x7E7E7E7E allows transmission of flags before first frame of data
Note: Used in conjunction with ZISTATE and ZIDATA1.
ZIDATA1 Word Zero-insertion low word data buffer. User-initialized to one of the following values:
0xFFFFFFFF allows transmission of all 1s before first frame of data
0x7E7E7E7E allows transmission of flags before first frame of data
Note: Used in conjunction with ZISTATE and ZIDATA0.
0x10
0x12
TBDFlags Hword TxDB flags, used by the CP (read-only for the user)
TBDCNT Hword Tx internal byte count. Number of remaining bytes in buffer, used by the CP (read-only
for the user)
0x14
0x18
0x1A
0x1C
0x20
TBDPTR Word Tx internal data pointer. Points to current absolute data address of channel, used by the
CP (read-only for the user)
TCRC
Word Temp transmit CRC. Temp value of CRC calculation result, used by the CP (read-only
for the user)
RSTATE Word Rx internal state. To start a receiver channel the user must write to RSTATE
0x24
ZDSTATE Word Zero-deletion machine state (User-initialized to 0x00FFFFE0 for regular channel and
0x20FFFFE0 for inverted channel)
0x28
0x2C
0x30
0x32
ZDDATA0 Word Zero-deletion high word data buffer (User-initialized to 0xFFFFFFFF)
ZDDATA1 Word Zero-deletion low word data buffer (User-initialized to 0xFFFFFFFF)
RBDFlags Hword RxBD flags, used by the CP (read-only for the user)
RBDCNT Hword Rx internal byte count. Number of remaining bytes in buffer, used by the CP (read-only
for the user)
0x34
RBDPTR Word Rx internal data pointer. Points to current absolute data address of channel, used by
the CP (read-only for the user)
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Multi-Channel Controllers (MCCs)
Table 28-2. Channel-Specific Parameters for HDLC (continued)
Width Description
1
Offset
Name
MFLR
0x38
Hword Maximum frame length register. Defines the longest expectable frame for this channel.
(64-Kbyte maximum). The remainder of a frame that is larger than MFLR is discarded
and the LG flag is set in the last frame’s BD. An interrupt request might be generated
(RXF and RXB) depending on the interrupt mask. A frame’s length is considered to be
everything between flags, including CRC. No more data is written into the current buffer
when the MFLR violation is detected.
0x3A MAX_CNT Hword Max_length counter, used by the CP (read-only for the user)
0x3C RCRC Word Temp receive CRC, used by the CP (read-only for the user)
The offset is relative to dual-port RAM (DPRAM) base address + 64*CH_NUM
1
28.3.1.1 Internal Transmitter State (TSTATE)—HDLC Mode
Internal transmitter state (TSTATE) is a 4-byte register provides transaction parameters associated with
SDMA channel accesses (like function code registers) and starts the transmitter channel.
To start the channel, write 0xHH800000 to TSTATE, where HH is the TSTATE high byte (see
Figure 28-2). When the channel is active, the CP changes the value of the three LSBs, hence these 3 bytes
must be masked if the user reads back the TSTATE.
0
1
2
3
4
5
6
7
Field
Reset
R/W
—
GBL
BO
—
TC2
DTB
BDB
R/W
Figure 28-2. TSTATE High Byte
Table 28-3. TSTATE High-Byte Field Descriptions
Bits
Name
Description
0–1
2
—
Reserved, should be cleared.
GBL Global. Setting GLB activates snooping (only the 60X bus can be snooped, this parameter is ignored
for local bus transactions).
3–4
BO
Byte ordering. Set BO to select the required byte ordering for the buffer. If BO is changed on-the-fly,
it takes effect at the beginning of the next frame or at the beginning of the next BD.
00 Reserved
01 Munged little-endian.
1x Big-endian
5
TC2 Transfer code. Contains the transfer code value of TC[2], used during this SDMA channel memory
access. TC[0–1] is driven with a 0b11 to identify this SDMA channel access as a DMA-type access.
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Multi-Channel Controllers (MCCs)
Table 28-3. TSTATE High-Byte Field Descriptions
Description
Bits
Name
6
DTB Data bus indicator. Selects the bus that handles transfers to and from data buffers.
0 60x bus SDMA
1 Local bus SDMA
7
BDB BD bus. Selects the bus that handles transfers to/from BD and interrupt circular tables.
0 60x bus SDMA used for accessing BDs
1 Local bus SDMA used for accessing BDs
28.3.1.2 Interrupt Mask (INTMSK)—HDLC Mode
The interrupt mask (INTMSK) provides bits for enabling/disabling the reporting of each possible event
defined in the interrupt circular table entry. For descriptions of each event bit, refer to Section 28.8.1.1,
0
5
6
7
8
9
10
11
12
13
14
15
Interrupt Entry
INTMSK
—
—
UN TXB
—
—
NID IDL MRF RXF BSY RXB
Mask Bits
Mask Bits
Figure 28-3. INTMSK Mask Bits
To enable an interrupt, set the corresponding bit. If a bit is cleared, no interrupt request is generated and
no new entry is written in the circular interrupt table. The user must initialize INTMSK prior to operation.
Reserved bits should remain cleared.
28.3.1.3 Channel Mode Register (CHAMR)—HDLC Mode
respectively. For channels that are used in conjunction with CES functionality, the user should refer to
0
1
2
3
4
5
6
7
8
9
10
11
12
13
15
Field MODE POL
1
IDLM
—
RD
—
CRC
—
TS
RQN
NOF
Reset
R/W
—
R/W
0x1A
Figure 28-4. Channel Mode Register (CHAMR)
Offset
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Multi-Channel Controllers (MCCs)
Table 28-4. CHAMR Field Descriptions
Description
Bits
Name
0
MODE This mode bit determines whether the HDLC or transparent mode is used. It also determines how
other CHAMR bits are interpreted.
Mode.”
1 HDLC mode
1
POL Enable polling. POL enables the transmitter to poll the TxBDs.
0 Polling is disabled (The CPM does not access the external bus to check the R bit in the TxBD).
1 Polling is enabled.
POL is used to optimize the use of the external bus. Software should always set POL at the
beginning of a transmit sequence of one or more frames. The CP clears POL when no more buffers
are ready in the transmit queue, i.e. when it finds a BD with R = 0 (for example, at the end of a frame
or at the end of a multi-frame transmission). To minimize useless transactions on the external bus,
software should always prepare the new BD, or multiple BDs, and set BD[R] before enabling polling.
2
3
1
Must be set.
IDLM Idle mode.
0 No idle patterns are sent between frames. After sending NOF+1 flags, the transmitter starts
sending the data of the frame. If the transmission is between frames and the frame buffers are
not ready, the transmitter sends flags until it can start transmitting the data.
1 At least one idle pattern is sent between adjacent frames. The NOF value shall be no smaller than
the PAD setting, see TxBD. If NOF = 0, this is identical to flag sharing in HDLC. Mode flags
precede the actual data. When IDLM = 1, at least one idle pattern is sent between adjacent
frames. If the transmission is between frames and the frame buffer is not ready, the transmitter
sends idle characters. When data is ready, the NOF+1 flags are sent followed by the data frame.
If IDLE mode is selected and NOF = 1, the following sequence is sent:
......init value, FF, FF, flag, flag, data, ........
The init value before the idle will be ones.
4
5
—
This bit must be cleared.
RD
0 Normal bit order (transmit/receive the lsb of each octet first)
1
Reversed bit order (transmit/receive the msb of each octet first)
6–7
8
—
These bits must be cleared.
CRC Selects the type of CRC when HDLC channel mode is used.
0 16-bit CCITT-CRC
1 32-bit CCITT-CRC
9
—
This bit must be cleared.
10
TS
Receive time stamp. If this bit is set a 4 byte time stamp is written at the beginning of every data
buffer that the BD points to.If this bit is set the data buffer must start from an address equal to 8*n-4
(n is any integer larger than 0).
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Multi-Channel Controllers (MCCs)
Table 28-4. CHAMR Field Descriptions (continued)
Description
Bits
Name
11–12
RQN Receive queue number. Specifies the receive interrupt queue number.
00 Queue number 0.
01 Queue number 1.
10 Queue number 2.
11 Queue number 3.
13–15
NOF Number of flags. NOF defines the minimum number of flags before frames:
000 At least 1 flag
001 At least 2 flags
....
111 At least 8 flags
28.3.1.4 Internal Receiver State (RSTATE)—HDLC Mode
Internal receiver state (RSTATE) is a 4-byte register that provides transaction parameters associated with
SDMA channel accesses (like function code registers) and starts the receiver channel.
To start the channel the user must write 0xHH800000 to RSTATE, where HH is the RSTATE high byte
(see Figure 28-5). When the channel is active the CP changes the value of the 3 LSBs, hence these 3 bytes
must be masked if the user reads back the RSTATE.
0
1
2
3
4
5
6
7
Field
Reset
R/W
—
GBL
BO
—
TC2
DTB
BDB
R/W
0x20
Addr
Figure 28-5. Rx Internal State (RSTATE) High Byte
Table 28-5. RSTATE High-Byte Field Descriptions
Bits
Name
Description
0–1
2
—
Reserved, should be cleared.
GBL
Global. Setting GLB activates snooping (only the 60X bus can be snooped, this parameter is ignored
for local bus transactions).
BO
3–4
Byte ordering. Set BO to select the required byte ordering for the buffer. If BO is changed on-the-fly,
it takes effect at the beginning of the next frame or at the beginning of the next BD.
00 Reserved
01 Munged little-endian.
1x Big-endian
TC2
5
Transfer code. Contains the transfer code value of TC[2], used during this SDMA channel memory
access. TC[0–1] is driven with a 0b11 to identify this SDMA channel access as a DMA-type access.
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Multi-Channel Controllers (MCCs)
Table 28-5. RSTATE High-Byte Field Descriptions (continued)
Description
Bits
Name
DTB
6
Data bus indicator.
The transfers to data buffers are handled by the:
0 60x bus SDMA
1 Local bus SDMA
BDB
7
BD and interrupt circular tables bus indicator.
The transfers to/from BD and interrupt circular tables are handled by the:
0 60x bus SDMA
1 Local bus SDMA
Note: The following restrictions result from the fact that there is a common bus selection bit for BDs
and interrupt circular tables:
• The RxBDs of all the channels that use a particular interrupt table must reside on the same bus
(60x or local).
• All TxBDs must reside on the same bus (60x or local).
28.3.2 Channel-Specific Transparent Parameters
Table 28-6 describes channel-specific parameters for transparent operation.
Table 28-6. Channel-Specific Parameters for Transparent Operation
1
Offset
Name
Width
Description
0x00
TSTATE
Word Tx internal state. To start a transmitter channel the user must write to TSTATE
0x04
ZISTATE Word Zero-insertion machine state.(User-initialized to 0x10000207 for regular channel, and
0x30000207 for inverted channel)
0x08
0x0C
0x10
0x12
ZIDATA0 Word Zero-insertion high word data buffer (User-initialized to 0xFFFFFFFF)
ZIDATA1 Word Zero-insertion low word data buffer (User-initialized to 0xFFFFFFFF)
TBDFlags Hword TxDB flags, used by the CP (read-only for the user)
TBDCNT Hword Tx internal byte count. Number of remaining bytes in buffer, used by the CP (read-only
for the user)
0x14
0x18
0x1A
TBDPTR Word Tx internal data pointer. Points to current absolute data address of channel, used by the
CP (read-only for the user)
0x1C
0x20
—
Word Reserved
RSTATE
Word Rx internal state. To start a receiver channel the user must write to RSTATE
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Multi-Channel Controllers (MCCs)
Table 28-6. Channel-Specific Parameters for Transparent Operation (continued)
Name Width Description
1
Offset
0x24
ZDSTATE Word Zero-deletion machine state. Initialize ZDSTATE as in the following table:
ZDSTATE Initial
Programmed Value
Channel Type
RCVSYNC
If pattern synchronization is used (CHAMR[SYNC] = 1x), then…
Regular
Inverted
0bxxxx_xxxx_xxxx_xxx0
0bxxxx_xxxx_xxxx_xxx1
0bxxxx_xxxx_xxxx_xxx0
0bxxxx_xxxx_xxxx_xxx1
0x00FF_FFE0
0x0000_0000
0x20FF_FFE0
0x2000_0000
If pattern synchronization is not used (CHAMR[SYNC] = 00), then…
Regular
Inverted
0x0000
0x0000
0x50FF_FFE0
0x70FF_FFE0
0x28
ZDDATA0 Word Zero-deletion high word data buffer (User-initialized to 0xFFFFFFFF)
0x2C ZDDATA1 Word Zero-deletion low word data buffer (User-initialized to 0xFFFFFFFF)
0x30 RBDFlags Hword RxBD flags, used by the CP (read-only for the user)
0x32
0x34
0x38
RBDCNT Hword Rx internal byte count. Number of remaining bytes in buffer, used by the CP (read-only
for the user)
RBDPTR Word Rx internal data pointer. Points to current absolute data address of channel, used by the
CP (read-only for the user)
TMRBLR Hword Transparent maximum receive buffer length. Defines the maximum number of bytes
written to a receiver buffer before moving to the next buffer for the respective channel.
This value must be 8 byte aligned.
0x3A RCVSYNC Hword Receive synchronization pattern. Defines the synchronization pattern when
CHAMR[SYNC] is 0b1x. The two bytes are checked in reverse order (byte from address
0x3B first and byte from address 0x3A last). Non-inverted data is used for
synchronization even if the channel is programmed to invert the data. Clear RCVSYNC
when CHAMR[SYNC] = 0b0x.
0x3C
—
Word Reserved
1
The offset is relative to dual-port RAM address 64*CH_NUM
28.3.2.1 Internal Transmitter State (TSTATE)—Transparent Mode
In transparent mode, TSTATE functions the same as in HDLC mode. For a description, refer to Section
28.3.2.2 Interrupt Mask (INTMSK)—Transparent Mode
In transparent mode, INTMSK functions the same as in HDLC mode. For a description, refer to Section
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Multi-Channel Controllers (MCCs)
28.3.2.3 Channel Mode Register (CHAMR)—Transparent Mode
Figure 28-6 shows the user-initialized channel mode register, CHAMR, for transparent mode. For
channels that are used in conjunction with CES functionality, the user should refer to Section 28.3.3.2,
0
1
2
3
4
5
6
7
8
9
10
11
12
13
15
Field MODE POL
1
1
EP
RD
SYNC
—
TS
RQN
—
Reset
R/W
—
R/W
0x1A
Figure 28-6. Channel Mode Register (CHAMR)—Transparent Mode
Offset
Table 28-7. CHAMR Field Descriptions—Transparent Mode
Bits
Name
Description
0
MODE Channel mode. Selects either HDLC or transparent mode.
0 Transparent mode.
1 HDLC mode
1
POL
Enable polling. POL enables the transmitter to poll the TxBDs.
0 Polling is disabled (The CPM does not access the external bus to check the R bit in the TxBD).
1 Polling is enabled.
POL is used to optimize the use of the external bus. Software should always set POL at the
beginning of a transmit sequence of one or more frames. The CP clears POL when no more buffers
are ready in the transmit queue, i.e. when it finds a BD with R = 0 (for example, at the end of a frame
or at the end of a multi-frame transmission). To prevent a significant number of useless transactions
on the external bus, software should always prepare the new BD, or multiple BDs, and set BD[R]
before enabling polling.
2–3 0b11
Must be set.
4
EP
Empty polarity and enable polling.
0 The E bit in the RxBD is handled in positive logic (1 = empty; 0 = not empty). Polling occurs only
if POL is set.
1 The E bit in the RxBD is handled in negative logic (0 = empty, 1 = not empty). Polling occurs
disregarding the value of POL.
5
RD
0 Normal bit order (transmit/receive the lsb of each octet first)
1 Reversed bit order (transmit/receive the msb of each octet first)
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Multi-Channel Controllers (MCCs)
Table 28-7. CHAMR Field Descriptions—Transparent Mode (continued)
Description
6–7 SYNC Synchronization. SYNC controls synchronization of multi-channel operation in transparent mode.
Bits
Name
SYNC Receive Transmit
Description
00
None
None
Transmitter and receiver operate with no synchronization algorithm.
RCVSYNC should be cleared or erroneous behavior may occur. If
data synchronization is not used, the beginning of receive data may
contain an arbitrary amount of bytes before actual data appears in
the receive buffer. These unrelated bytes can be data or idles that
were in the receive FIFO when reception began or can be data that
was on the line previous to the arrival of the intended data.
01
10
11
Slot
Slot
The first data is sent/received in the slot defined in the slot
assignment table (for super channels only). RCVSYNC should be
cleared or received data may be shifted.
8-bit
16-bit
None
None
Receive data synchronization uses an 8-bit pattern specified by the
8 msb of RCVSYNC. The sync bytes are not written to the receive
buffer.
Receive data synchronization uses a 16-bit pattern specified by
RCVSYNC. The first byte of the sync pattern will not be written to the
receive buffer. The second byte of the sync pattern will be written to
the receive buffer (first and second represent the order in which the
two bytes of the sync pattern are received on the serial channel).
8–9
10
—
Reserved, must be cleared.
TS
Receive time stamp. If this bit is set a 4 byte time stamp is written at the beginning of every data
buffer that the BD points to.If this bit is set the data buffer must start from an address equal to 8*N-4
(N is any number larger than 0).
11–12 RQN
Receive queue number. Specifies the receive interrupt queue number.
00 Queue number 0.
01 Queue number 1.
10 Queue number 2.
11 Queue number 3.
13–15
—
Reserved, must be cleared.
28.3.2.4 Internal Receiver State (RSTATE)—Transparent Mode
In transparent mode, RSTATE functions the same as in HDLC mode. For a description, refer to Section
28.3.3 MCC Parameters for AAL1 CES Usage
When using AAL1 CES, the structured and unstructured data are transferred between the ATM and MCC
The following subsections describe the additional parameters required for AAL1 CES.
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Multi-Channel Controllers (MCCs)
28.3.3.1 Channel-Specific Parameters—AAL1 CES
The following are changes that occur in the channel-specific parameter RAM when using AAL1 CES.
Table 28-8 describes the additional global MCC parameters specific to CES operation.
Table 28-8. CES-Specific Global MCC Parameters
1
Offset
Name
CATB
Width
Description
0x00
Hword CES adaptive threshold tables base address. Points to the dual-port RAM area
containing the CES slip control thresholds and the adaptive counter See Section 31.5,
AAL1-MCC channel). User-defined and should match the CATB value programmed in
0x02
—
Hword Reserved, should be cleared during initialization.
0x04,
0x08,
0x0C,
0x10
UTAa,
UTAb,
UTAc,
UTAd,
Hword Underrun template address for TDMx. Points to the dual-port RAM area containing the
user-defined template to be sent during an MCC transmitter pre-underrun condition.
0x06,
0x0A,
0x0E,
0x12
UTSa,
UTSb,
UTSc,
UTSd,
Hword Underrun template size for TDMx. This is the size in bytes of the underrun template
buffer.
1
The offset to the CES-specific global MCC parameter RAM for MCC1 is 0x8780. For MCC2, it is 0x8880.
28.3.3.1.1
Interrupt Circular Table Entry and Interrupt Mask (INTMSK)—AAL1 CES
Interrupt circular table entries contain information about channel-specific events. The interrupt mask
(INTMSK) provides bits for enabling/disabling the reporting of each possible event defined in the interrupt
circular table entry. Note that two CES-related interrupts provide slip indications for the MCC transmitter;
these interrupts are reflected in both the interrupt circular table entries and the INTMSK fields. They are
0
3
4
5
6
7
8
9
10
11
12
13
14
15
Interrupt Entry
INTMSK
—
—
SLIPE SLIPS
UN TXB
—
—
NID IDL MRF RXF BSY RXB
CES Mask Bits Mask Bits
Mask Bits
Figure 28-7. INTMSK Mask Bits
To enable an interrupt, set the corresponding bit. If a bit is cleared, no interrupt request is generated and
no new entry is written in the interrupt circular table. The user must initialize INTMSK prior to operation.
Reserved bits are cleared.
28.3.3.2 Channel Mode Register (CHAMR)—AAL1 CES
Figure 28-6 shows the user-initialized channel mode register, CHAMR, for CES operation. It is the same
as the CHAMR in transparent mode with three extra CES fields in bits 13–15.
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Multi-Channel Controllers (MCCs)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Field MODE POL
1
1
EP
RD
SYNC
—
TS
RQN
CESM UDC UTM
Reset
R/W
—
R/W
Offset
0x1A
Figure 28-8. Channel Mode Register (CHAMR)—CES Mode
Table 28-9. CHAMR Field Descriptions—CES Mode
Bits Name
Description
0
MODE Channel mode. Selects either HDLC or transparent mode. Must be cleared for CES operation.
0 Transparent mode.
1 HDLC mode
1
POL
Enable polling. POL enables the transmitter to poll the TxBDs.
0 Polling is disabled (The CPM does not access the external bus to check the R bit in the TxBD).
1 Polling is enabled.
POL is used to optimize the use of the external bus. Software should always set POL at the beginning
of a transmit sequence of one or more frames. The CP clears POL when no more buffers are ready
in the transmit queue, i.e. when it finds a BD with R = 0 (for example, at the end of a frame or at the
end of a multi-frame transmission). To prevent a significant number of useless transactions on the
external bus, software should always prepare the new BD, or multiple BDs, and set BD[R] before
enabling polling.
2–3 0b11
Must be set.
4
EP
Empty polarity and enable polling.
0 The E bit in the RxBD is handled in positive logic (1 = empty; 0 = not empty). Polling occurs only if
POL is set.
1 The E bit in the RxBD is handled in negative logic (0 = empty, 1 = not empty). Polling occurs
disregarding the value of POL.
5
RD
0 Normal bit order (transmit/receive the lsb of each octet first)
1
Reversed bit order to be reversed (transmit/receive the msb of each octet first).
6–7 SYNC Synchronization. SYNC controls synchronization of multi-channel operation in transparent mode.
SYNC Receive Transmit
Description
00
01
None
Slot
None
Slot
Transmitter and receiver operate with no synchronization algorithm
The first data is sent/received in the slot defined in the slot assignment
table (for super channels only)
10
11
8-bit
None
None
Receive data synchronization uses an 8-bit pattern specified by the 8
msb of RCVSYNC. The sync bytes will not be written to the receive
buffer
16-bit
Receive data synchronization uses a 16-bit pattern specified by
RCVSYNC. The first byte of the sync pattern will not be written to the
receive buffer. The second byte of the sync pattern will be written to
the receive buffer (first and second represent the order in which the
two bytes of the sync pattern are received on the serial channel).
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Table 28-9. CHAMR Field Descriptions—CES Mode (continued)
Description
Reserved, should be cleared during initialization.
Bits Name
8–9
10
—
TS
Receive time stamp. If this bit is set a 4 byte time stamp is written at the beginning of every data buffer
that the BD points to.If this bit is set the data buffer must start from an address equal to 8*N-4 (N is
any number larger than 0).
11–12 RQN
Receive queue number. Specifies the receive interrupt queue number.
00 Queue number 0
01 Queue number 1
10 Queue number 2
11 Queue number 3
13
14
15
CESM Circuit emulation service mode.
0
Normal mode
1
CES mode
UDC
UTM
User-defined cell support.
0 User-defined ATM cells are not supported.
1 User-defined ATM cells are supported.
Underrun template mode.
0 Retransmit the last buffer.
1 Send the user-defined template.
28.3.4 Channel-Specific SS7 Parameters
Based on the HDLC protocol, the signalling system #7 (SS7) protocol is used to manage public service
networks. The SS7 protocol operates on signal units (SU), which are analogous to HDLC frames. The
physical, data link, and network layer functions of the SS7 protocol are called the message transfer part
(MTP). Implementing the MTP layer 2 (data link) functions in host software is difficult with multiple
performance issues. The PowerQUICC II SS7 microcode enables applications requiring multi-channel
SS7 processing.
The SS7 controller is implemented using the MCC hardware with microcode running on the CPM. Each
MCC implements the following layer 2 portions of the MTP:
•
•
•
•
•
•
•
•
Signal unit (SU) retransmission
Automatic fill-in signal unit (FISU) transmission
Short SU filtering
Duplicate fill-in and link-status signal unit (FISU/LSSU) filtering
Octet counting
Signal unit error rate monitoring
Good frame counter and bad frame counting
Initial alignment (supports alignment error rate monitoring)
Host software, however, is needed to handle the following higher-level functions of the MTP layer 2 not
supported by the SS7 controller:
•
Link state control
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Multi-Channel Controllers (MCCs)
•
Flow control
SS7 features are as follows:
•
•
•
Up to 128 independent communication channels (64 channels per MCC)
Independent mapping for receive and transmit
Standard HDLC features
— Flag/Abort/Idle generation/detection
— Zero insertion/deletion
— 16-bit CRC-CCITT generation/checking
— Detection of non-octet aligned signal units
— Programmable number of flags between signal units
Maintenance of signal unit error monitor (SUERM)
Maintenance of alignment error rate monitor (AERM)
Maintenance of separate counters for error-free and bad frames
Detection and stripping of long signal units
•
•
•
•
•
•
•
•
•
•
•
Discard of short signal units (less than 5 octets)
Transmission of signal units with a programmable delay (applies to JT-Q.703 standard)
Automatic transmission of fill-in signal units (FISU)
Automatic retransmission of signal units (for link-status signal unit (LSSU) retransmission)
Automatic discard of identical FISUs and LSSUs using a user-defined mask
Octet counting mode in case of long signal units and receiver overrun
Five circular interrupt tables with programmable size and overflow identification—one for
transmit and four for receive.
•
•
•
•
•
•
Global or individual channel loop modes
Efficient bus usage (no bus usage for inactive channels or for active channels with nothing to send)
Efficient control of interrupts to the CPU
Supports external BD tables
Uses on-chip dual-port RAM for parameter storage
Uses 64-bit data transactions for reading and writing data in BDs
Table 28-10 describes channel-specific parameters for SS7. Note that a given parameter location may have
a different definition depending on the standard used (ITU-T/ANSI or Japanese standard).
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Multi-Channel Controllers (MCCs)
Table 28-10. Channel-Specific Parameters for SS7
Width Description
1
2
Offset
Name
0x00
TSTATE
Word
Tx internal state. The user must write to TSTATE 0xHH80_0000. HH is the TSTATE
0x04
ZISTATE
Word
Zero-insertion machine state. User-initialized to one of the following values:
0x10000207 for regular channel transmitting all 1s before first frame of data
0x00000207 for regular channel transmitting flags before first frame of data
0x30000207 for inverted channel transmitting all 1s before first frame of data
0x20000207 for inverted channel transmitting flags before first frame of data
Note: Used in conjunction with ZIDATA0 and ZIDATA1.
0x08
0x0C
ZIDATA0
ZIDATA1
Word
Word
Zero-insertion high word data buffer. User-initialized to one of the following values:
0xFFFFFFFF allows transmission of all 1s before first frame of data
0x7E7E7E7E allows transmission of flags before first frame of data
Note: Used in conjunction with ZISTATE and ZIDATA1.
Zero-insertion low word data buffer. User-initialized to one of the following values:
0xFFFFFFFF allows transmission of all 1s before first frame of data
0x7E7E7E7E allows transmission of flags before first frame of data
Note: Used in conjunction with ZISTATE and ZIDATA0.
0x10
0x12
TBDFlags
TBDCNT
Hword TxBD flags, used by the CP (read-only for the user)
Hword Tx internal byte count. Number of remaining bytes in buffer, used by the CP
(read-only for the user)
0x14
0x18
0x1C
0x20
TBDPTR
ECHAMR
TCRC
Word
Word
Word
Word
Tx internal data pointer. Points to current absolute data address of channel, used by
the CP (read-only for the user)
Extended channel mode register. See 28.3.4.1, “Extended Channel Mode Register
Temporary transmit CRC. Temporary value of CRC calculation result, used by the CP
(read-only for the user)
RSTATE
Rx internal state. To start a receiver channel the user must write to RSTATE
0x24
ZDSTATE
Word
Zero-deletion machine state (User-initialized to 0x00FFFFE0 for regular channel,
and 0x20FFFFE0 for reversed bit order channel)
0x28
0x2C
0x30
0x32
ZDDATA0
ZDDATA1
RBDFlags
RBDCNT
Word
Word
Zero-deletion high word data buffer (User-initialized to 0xFFFFFFFF)
Zero-deletion low word data buffer (User-initialized to 0xFFFFFFFF)
Hword RxBD flags, used by the CP (read-only for the user)
Hword Rx internal byte count. Number of remaining bytes in buffer, used by the CP
(read-only for the user)
0x34
RBDPTR
Word
Rx internal data pointer. Points to current absolute data address of channel, used by
the CP (read-only for the user)
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Multi-Channel Controllers (MCCs)
Table 28-10. Channel-Specific Parameters for SS7 (continued)
1
2
Offset
Name
MFLR
Width
Description
0x38
Hword Maximum frame length register. Defines the longest expected frame for this channel.
(64-Kbyte maximum). The remainder of a frame that is larger than MFLR is discarded
and the LG flag is set in the last frame’s BD. An interrupt request might be generated
(RXF and RXB) depending on the interrupt mask. A frame’s length is considered to
be everything between flags, including CRC. No more data is written into the current
buffer when the MFLR violation is detected.
0x3A
0x3C
0x40
MAX_cnt
RCRC
N
Hword Max_length counter, used by the CP (read-only for the user)
Word
Temporary receive CRC, used by the CP (read-only for the user)
Hword Applies to ITU-T/ANSI SS7 only. Interrupt threshold in octet counting mode (N=16).
N_cnt
Hword Applies to ITU-T/ANSI SS7 only. Temporary down counter for N (user initialized to
the value of N).
JTSTTmp
D
Word
Applies to Japanese SS7 only. Temporary storage for Time-Stamp Register Value.
Used by the CP to implement a 24-ms delay before sending FISU.
0x44
0x46
Hword Signal unit to signal unit error ratio (SUERM parameter, user initialized to 256). See
D_cnt
Hword Applies to ITU-T/ANSI SS7 only. Temporary down-counter for D (user initialized to
the value of D). D_cnt is decremented only when receive buffers are available.
JTTDelay
Applies to Japanese SS7 only. FISU retransmission delay (specified in units of
512¨µs). According to the Japanese SS7 standard, the delay should be 24 ms and
thus JTTDelay should be programmed to 24 ms/512 µs = 46.875 (approximately 47).
Hence, the user should program JTTDelay to 0x2F and the RTSCR to generate a 1
µs time stamp period. Refer to Section 14.3.8, “RISC Time-Stamp Control Register
(RTSCR)”.
0x48
0x4C
0x4E
Mask1
Word
Mask for SU filtering, bytes 0-3. See 28.3.4.4, “SU Filtering—SS7 Mode
Mask2
SS7_OPT
0x50
0x54
0x56
LRB1_Tmp Word
Temporary storage, used by CP for SU filtering.
LRB2_Tmp Hword Temporary storage, used by CP for SU filtering.
SUERM
LRB1
LRB2
T
0x58
0x5C
0x5E
0x60
0x64
Word
Four first bytes of last received signal unit. Used by CP for SU filtering. See 28.3.4.4,
LHDR
Word
The BSN, BIB, FSN, FIB fields of last transmitted signal unit and result of CRC. Used
by CP for automatic FISU transmission.
LHDR_Tmp Word
Temporary storage, used by CP for automatic FISU transmission.
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Table 28-10. Channel-Specific Parameters for SS7 (continued)
1
2
Offset
Name
Width
Description
0x68
EFSUC
Word
Error-free signal unit counter, user initialized to 0. The counter is incremented
whenever an error-free (no CRC error, no non-octet aligned error, no short or long
frame errors) signal unit is received.
0x6C
SUEC
Word
Signal unit error counter, user initialized to 0. Incremented each time an SU is
received that contains an error. These errors are: short frame, long frame, CRC error,
and non-octet aligned error.
0x70
0x74
SS7STATE Word
Internal state of SS7 controller, user initialized to 0.
JTSRTmp
Word
Temporary storage for time-stamp register value. Applies to Japanese SS7 only;
otherwise should be cleared. Used by the CP to implement the 24-ms delay for signal
unit error rate monitoring in Japanese SS7.
0x78
JTRDelay
Hword FISU transmit delay (specified in units of 512us). Applies to Japanese SS7 only;
otherwise should be cleared. According to the Japanese SS7 standard, the delay
should be 24 ms and thus JTRDelay should be programmed to 24 ms/512
µs = 46.875 (approximately 47). Hence, the user should program JTRDelay to 0x2F
and the RTSCR to generate a 1 µs time stamp period. Refer to Section 14.3.8, “RISC
0x7A
0x7C
M
Hword ITU threshold for AERM. If M_cnt reaches M, an AERM interrupt is generated. Note
that M is normally programmed to 5.
M_cnt
Hword Up-counter for M. Should be cleared during initialization.
1
The offset is relative to the dual-port RAM address + 64*CH_NUM. SS7 channel specific parameters require twice
the amount of dual-port RAM required for HDLC or Transparent channel specific parameters. Therefore for SS7 even
channel numbers (0, 2, 4, etc.) must be used and odd channel number must be left unused.
2
Items in boldface must be initialized by the user. Unless otherwise stated, all other items are managed by microcode
and should be initialized to zero.
28.3.4.1 Extended Channel Mode Register (ECHAMR)—SS7 Mode
includes both the interrupt mask bits and channel configuration bits.
The interrupt mask provides bits for enabling/disabling each event defined in the interrupt circular table
entry. Other bits provide various channel configuration options.
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Multi-Channel Controllers (MCCs)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Field MODE0
—
OCT SUERM FISU
—
UN TXB
—
AERM NID IDL MRF RXF BSY RXB
Reset
R/W
No reset value
R/W
Offset
0x18
16
17
18
19
20
25
26
27
28
29
31
Field MODE1 POL
1
IDLM
—
TS
RQN
NOF
Reset
R/W
No reset value
R/W
Offset
0x1A
Figure 28-9. Extended Channel Mode Register (ECHAMR)
ECHAMR fields are described in Table 28-11.
Table 28-11. ECHAMR Fields Description
Bits
0,16
Name
Description
MODE0 00 Transparent mode
MODE1 01 HDLC mode
10 Reserved
11 SS7 mode (This is the required bit setting for an MCC to perform SS7.)
1, 5,
8
0
Reserved, should be cleared during initialization.
2-4
INTMSK Interrupt mask bits. These bits are used for enabling/disabling the reporting of each possible event
6-7
defined in the interrupt circular table entry. See Section 28.8.1.1, “Interrupt Circular Table Entry.”
9-15
0 Disabled
1 Enable
17
POL
Enable polling. POL enables the transmitter to poll the TxBDs.
0 Polling is disabled (The CPM does not access the external bus to check the R bit in the TxBD).
1 Polling is enabled.
POL is used to optimize the use of the external bus. Software should always set POL at the
beginning of a transmit sequence of one or more frames. The CP clears POL when no more
buffers are ready in the transmit queue, i.e. when it finds a BD with R = 0 (for example, at the
end of a frame or at the end of a multi-frame transmission). To prevent a significant number of
useless transactions on the external bus, software should always prepare the new BD, or
multiple BDs, and set BD[R] before enabling polling.
18
1
Reserved, must be set.
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Multi-Channel Controllers (MCCs)
Table 28-11. ECHAMR Fields Description (continued)
Description
Bits
19
Name
IDLM
Idle mode.
0 No idle patterns are transmitted between frames. After transmitting NOF+1 flags, the transmitter
starts sending the data of the frame. If the transmission is between frames and the frame buffers
are not ready, the transmitter sends flags until it can start transmitting the data received for SS7
operation.
1 At least one idle pattern is sent between adjacent frames. The NOF value shall be no smaller
than the PAD setting, see TxBD. If NOF = 0, this is identical to flag sharing in SS7. Mode flags
precede the actual data. When IDLM = 1, at least one idle pattern is sent between adjacent
frames. If the transmission is between frames and the frame buffer is not ready, the transmitter
sends idle characters. When data is ready, the NOF+1 flags are sent followed by the data frame.
If IDLE mode is selected and NOF = 1, the following sequence is sent:
......init value, FF, FF, flag, flag, data, ........
The init value before the idle will be ones.
20-25
10
—
Reserved, should be cleared during initialization.
TS
Receive time stamp. If this bit is set a 4 byte time stamp is written at the beginning of every data
buffer that the BD points to.If this bit is set the data buffer must start from an address equal to 8*n-4
(n is any integer larger than 0).
11–12 RQN
13–15 NOF
Receive queue number. Specifies the receive interrupt queue number.
00 Queue number 0.
01 Queue number 1.
10 Queue number 2.
11 Queue number 3.
Number of flags. NOF defines the minimum number of flags before frames:
000 - at least 1 flag
001 - at least 2 flags
....
111 - at least 8 flags
Note that items in bold must be initialized by the user.
28.3.4.2 Signal Unit Error Monitor (SUERM)—SS7 Mode
The microcode maintains the signal unit error rate monitor as described in ITU-T Q.703 paragraph 10, and
ANSI T1.111-1996 paragraph 10.
The microcode uses SUERM, N, N_cnt, D, D_cnt and T parameters for the leaky-bucket implementation
of the SU error monitor.
•
•
•
After every N octets received while in octet counting mode, SUERM is incremented and an
interrupt request can be generated (SUERM) depending on the interrupt mask.
After D error-free frames have been received, SUERM is decremented. SUERM will not be
decremented below zero.
If SUERM reaches T, the SUERM is cleared and an interrupt is generated.
28.3.4.2.1
SUERM in Japanese SS7
The Japanese SS7 uses a time interval to monitor errors. If an error is present, it checks every 24 ms.
•
An error flag is set that indicates whether current frame is errored or not.
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Multi-Channel Controllers (MCCs)
•
•
•
•
For every JTRDelay an error flag is checked.
If there is no error, decrement the counter SUERM by 1 (not below zero).
If there is an error, increment the counter SUERM by D.
If SUERM reaches T, the counter SUERM is cleared and a “signal unit error rate monitor” interrupt
is generated.
Table 28-12. Parameter Values for SUERM in Japanese SS7
Paramete
Definition
Value
r
T
Threshold
Upcount
285
16
D
JTRDelay Length of interval (24ms)
0x2F
28.3.4.3 SS7 Configuration Register—SS7 Mode
0
3
4
5
6
7
8
9
10
11
12
15
Field
Reset
R/W
—
AERM SUERM_DIS STD SF_DIS SU_FIL SEN_FIS O_ORN O_ITUT FISU_PAD
R/W
Figure 28-10. SS7 Configuration Register (SS7_OPT)
Table 28-13 describes SS7 configuration register fields.
Table 28-13. SS7 Configuration Register Fields Description
Description
Reserved, should be cleared during initialization.
Bits
0-3
Name
—
4
5
6
7
8
AERM
0 Do not enable AERM.
1 Enable AERM.
SUERM_
DIS
0 Enable SUERM.
1 Disables both SUERM and AERM.
STD
Standard compliance
0 ITU-T/ANSI compliant
1 Japanese SS7 compliant
SF_DIS
SU_FIL
Discard short frames (less than 5 octets)
0 Do not discard short frames.
1 Discard short frames.
SU Filtering
0 Disable SU filtering.
1 Enable SU filtering.
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Multi-Channel Controllers (MCCs)
Table 28-13. SS7 Configuration Register Fields Description
Description
Send FISU if first BD of frame is not ready.
Bits
Name
9
SEN_FIS
0 Flags are sent if the current BD, which is the first BD of the frame, does not have its ready bit set.
1 FISUs are automatically sent if the current BD, which is the first BD of the frame, does not have
its ready bit set.
10
11
O_ORN
O_ITUT
Enter octet counting mode (OCM) on overrun. Should be cleared if using the Japanese standard.
0 Disable entering OCM if there are no receive BDs available.
1 Enter OCM if there are no receive BDs available.
Note that when STD = 1, O_ORN = 1, and no receive buffers are ready, a ny received signal unit
is treated as an erred signal unit.
Enter octet counting mode (OCM) on ITU-T conditions (after an abort sequence or when an SU is
too long). Should be cleared if using the Japanese standard.
0 Disable entering OCM on ITU-T conditions.
1 Enable entering OCM on ITU-T conditions.
12-15 FISU_PAD Padding of the automatically transmitted FISUs. If the SEN_FISU bit is set, the CP will use the
28.3.4.3.1
AERM Implementation
The SS7 microcode implements the ITU Q.703 alignment error rate monitor (AERM). The microcode uses
the T, SUERM, M and M_cnt parameters. The M_cnt parameter is incremented for every T errored frames.
If M_cnt reaches M, an AERM interrupt is generated to layer 3.
Note that in AERM mode no SUERM interrupt is generated. Also, the algorithm associated with D and
D_cnt is disabled as per the ITU specification.
28.3.4.3.2
AERM in Japanese SS7
To meet the Japanese AERM requirements the user must change the parameters T and D. Note that the
interrupt generated is not AERM but SUERM.
During proving, do the following:
1. Set SS7_OPT register to 0b0000 001X XX00 XXXX. The value of X doesn’t matter because these
bits do not affect the operation of the error counter.
2. Clear JTRdelay parameter to'0.'
3. Set parameters T (threshold) and D (up counter) to'1.'
4. Clear parameter SUERM (error counter) to'0.'
5. Set JTTDelay to value required to generate 24ms delay.
These settings allow FISU or LSSU transmission to be delayed by the required 24ms (JTTDelay). They
also allow the correct operation of the JT Q703 error counter and ensure that an SUERM interrupt is
generated on the first SU received in error.
After proving period, set the parameters (T and D) to values according to the Japanese SUERM. See
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Multi-Channel Controllers (MCCs)
To disable AERM and enter SUERM, do the following:
1. Set SUERM_DIS bit in SS7_OPT.
2. Set parameters (T, D & SUERM) for Japanese SUERM.
3. Clear SUERM_DIS bit in SS7_OPT.
28.3.4.3.3
Disabling SUERM
When SS7_OPT[SUERM_DIS] is set, the N_cnt and D_cnt parameters are not decremented by the
microcode and no SUERM interrupt is generated. This allows these parameters to be updated, for example,
at the end of the proving period in alignment error monitoring.
Note: If the SS7 controller is in the octet counting mode (OCM) when SUERM_DIS is set, then if no idles
(only flags/data) are received while SUERM_DIS is set, then after the host updates N_cnt and D_cnt and
clears SUERM_DIS the receiver will start in OCM. However if SUERM_DIS is set while in OCM and
idles are then received then the OCM state is left.
28.3.4.4 SU Filtering—SS7 Mode
To reduce the overhead to the user software, a filtering algorithm has been adopted to allow superfluous
frames to be discarded. This algorithm compares the first 3–5 bytes (depending on the type) of the current
FISU or LSSU to the last SU received and discards the current SU if it has already been received twice.
28.3.4.4.1
Comparison Mask
A user programmable 5-byte mask exists in the parameter RAM map. When an SU is received, the
controller checks the contents of the LI field. If LI is between 0 and 2, the SU (except for the CRC portion)
will be masked according to the user programmable mask and will then be compared to the last SU
received. The state machine for the matching algorithm is in Subsection 28.3.4.4.2, “Comparison State
The Mask1 and Mask2 channel-specific parameters construct the 5-byte user mask. The exact format and
msb
lsb
Byte 1
Byte 2
Byte 3
Byte 4
Figure 28-11. Mask1 Format
msb
Reserved, should be cleared.
Figure 28-12. Mask2 Format
lsb
Byte 5
28.3.4.4.2
Comparison State Machine
The following state machine exists for filtering.
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Multi-Channel Controllers (MCCs)
•
•
•
State 0—The first 3-5 bytes (depending on the contents of the LI field) are masked and then
compared with the first 3-5 bytes of the last SU. If there is a match, go to State 1, else remain in
State 0. The current SU will be received into a buffer descriptor.
State 1—The first 3-5 bytes (depending on the contents of the LI field) are masked and then
compared with the first 3-5 bytes of the last SU. If there is a match, go to State 2, else go to State
0. The current SU will be received into a buffer descriptor.
State 2—The first 3-5 bytes (depending on the contents of the LI field) are masked and then
compared with the first 3-5 bytes of the last SU. If there is a match, the current SU will be discarded
(unless there is an error), the channel will remain in state 2 and SU error monitor will be adjusted
accordingly. If the frames do not match, the current SU will be received into a buffer descriptor and
the channel will return to State 0.
28.3.4.4.3
Filtering Limitations
Because the algorithm is purely checking identical SUs, two FISUs will be received after each MSU rather
than merely one, even though they have the same sequence numbers.
Reception of an MSU resets the filtering algorithm. Also, reception of a short frame resets the filtering
algorithm when SS7_OPT[SF_DIS] = 0; however, when SS7_OPT[SF_DIS] = 1 (short frames are
discarded), the filtering algorithm remains unchanged.
28.3.4.4.4
Resetting the SU Filtering Mechanism
This command resets the filtering algorithm to ensure that the next SU will be received, even if it would
normally have been filtered. This command could be issued periodically so that the 603e core can check
to make sure that the link is really up and not simply receiving flags.
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Multi-Channel Controllers (MCCs)
28.3.4.5 Octet Counting Mode—SS7 Mode
When entering the octet counting mode (OCM), the CP will load the user defined N register to its internal
octet counter. While in the octet counting mode the CP will decrement its internal counter for every
unstuffed octet received. When the internal counter is decremented to zero, the CP increment the SUERM
register and reload the N register into the internal count register. In addition an interrupt (OCT) might be
generated depending on the interrupt mask. The SS7 controller will enter octet counting mode under the
following circumstances:
•
•
An ABORT character is received at any time and SS7_OPT[O_ITUT] is set.
The SU currently being received has exceeded the length programmed in the MFLR register and
SS7_OPT[O_ITUT] is set.
•
The receiver overruns and SS7_OPT[O_ORN] is set. Note that when no receive buffers are
available, only octets are counted; that is, D_cnt is not decremented after receiving the frame.
The SS7 controller will leave octet counting mode when a valid signal unit is detected (with a valid CRC
and a length less than MFLR and greater than 4).
NOTE
Octet counting mode applies only to the ITU-T and ANSI standards. The
SS7 microcode will not work if both the Japanese standard and OCM
features are selected.
28.4 Channel Extra Parameters
In addition to the information kept in the channel-specific parameter ram, a channel also has a set of
pointers used to index its transmit and receive buffer descriptors. This information is kept in a set of
indexed using the channel number, as described in the table.
Table 28-14. Channel Extra Parameters
1
Offset
Name Width
Description
0x00
TBASE Hword TxBD base address. Used to calculate offset of the channel’s TxBD table relative to the
MCCBASE (The base address of the BD table for this channel MCCBASE+8*TBASE)
0x02
TBPTR Hword TxBD pointer. Used to calculate offset of the current BD relative to the MCCBASE. TBPTR
is user-initialized to TBASE before enabling the channel or after a fatal error before
reinitializing the channel. (The address of the BD in use for this channel
MCCBASE+8*TBPTR)
0x04
0x06
RBASE Hword RxBD base address. Used to calculate offset of the channel’s RxBD table relative to the
MCCBASE. (The base address of the BD table for this channel MCCBASE+8*RBASE)
RBPTR Hword RxBD pointer. Used to calculate offset of the current BD relative to the MCCBASE.
RBPTR is user-initialized to RBASE before enabling the channel or after a fatal error
before reinitializing the channel. (The address of the BD in use for this channel
MCCBASE+8*RTBPTR)
1
The offset relative to dual-port RAM base address + XTRABASE + 8*CH_NUM
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Multi-Channel Controllers (MCCs)
28.5 Superchannels
A TDM may not be programmed to contiguously transmit more than one byte of data from the same MCC
channel. This is true whether the user wants to program more than one byte in the same SI entry or have
back-to-back SI entries for the same channel. Instead, superchannelling is used to achieve sending multiple
back-to-back bytes from the same MCC channel. Refer to Section 15.4.3, “Programming SIx RAM
A single MCC channel is the combination of one MCC FIFO and one set of related channel parameters
and buffer descriptors. A superchannel is the combination of multiple MCC TX channels’ FIFOs and one
set of an MCC channel’s parameters and buffer descriptors. In this case, the one set of parameters and
buffer descriptors is used to manage this group of FIFOs. In effect, this provides the ability to construct a
larger overall FIFO than that of a single normal MCC TX channel.
MCC TX channels whose numbers appear in superchannelled SIRAM entries are dedicating their TX
FIFOs to that superchannel and may not be used for any other purpose (i.e. cannot also be used elsewhere
in a TDM as a normal channel). The FIFO of the channel whose parameters are used to control a
superchannel may still be used as part of the superchannel.
Although a timeslot for a normal MCC channel may be of any length up to 8 bits, a superchannelled
timeslot must always be 8 bits.
Although a normal MCC transmit FIFO is 4 bytes, one that is used as part of a superchannel is 2 bytes.
Note that an MCC channel whose FIFO is in superchannel mode consumes twice as much CPM bandwidth
as a normal channel.
28.5.1 Superchannel Table
When the SI encounters an SIRAM entry that is programmed to be part of a superchannel, the channel
number in that SIRAM entry represents which MCC channel’s FIFO is to be used during that timeslot.
Later, when that FIFO requires service from the CPM, a lookup occurs using the Superchannel Table
(SCT).
The SCT serves as a mapping between the FIFOs being used as part of a superchannel (as programmed in
SIRAM) and which channel’s parameters are being used to manage that superchannel. The MCC channel
FIFO number used in the MCSEL field of the superchannelled SIRAM entry is used to calculate an offset
to a superchannel table entry that contains the MCC channel number whose parameters and buffer
superchannel table which must be initialized are those whose numbers appear in superchannelled entries
in the SIRAM.
0
1
2
9
10
11
12
13
14
15
Field
Addr
0
0
Channel Number
0
0
0
0
0
0
DPRAM_base_address+SCTPBASE+2*MCC_FIFO_number
(MCC_FIFO_number is the number written in the MCSEL field of the corresponding SI RAM entry)
Figure 28-13. Super Channel Table Entry
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Multi-Channel Controllers (MCCs)
28.5.2 Superchannels and Receiving
The restrictions stated in Section 28.5 regarding using back-to-back timeslots with the same channel do
not apply to the receive side of the MCC. A user does not have to mark receive timeslots as
superchannelled in SIRAM programming unless transparent slot synchronization is being used (see
Section 28.5.3, “Transparent Slot Synchronization”). Note that no SCT is used for the receive side and the
channel numbers used when programming receive SIRAM timeslots should always be that of the actual
intended MCC receive channel FIFO.
A normal MCC receive FIFO is 2 bytes and a superchannelled MCC receive FIFO is 1 byte.
28.5.3 Transparent Slot Synchronization
Transparent slot synchronization (TSS) is used to ensure that data transmission and reception for a
transparent superchannel begins on the intended timeslot of that superchannel. It is not required that the
first timeslot that appears in the SIRAM programming for a transparent superchannel be the first to send
or receive when the superchannel first starts. The user indicates which timeslot in a superchannel should
be the first to send or receive by programming the CNT and BYT fields of the superchannelled timeslots
28.5.4 Superchannelling Programming Examples
different transmitter superchannels running on the same TDM interface. One superchannel includes TDM
timeslots 1, 6, and 7, which also happen to be programmed to use MCC FIFO numbers 1, 6, and 7. The
second superchannel in this example is comprised of timeslots 2, 3, and 4 using MCC FIFOs 2, 3, and 4.
This approach of using a FIFO number which is the same as the timeslot number is arbitrary and no a
requirement.
Note that entries in the superchannel table for MCC FIFOs 1, 6 and 7 all are programmed to point to the
channel-specific and channel-extra parameters for channel 1. Superchannel table entries for MCC FIFOs
2, 3 and 4 are programmed such that these FIFOs are managed by the parameters of channel 2.
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Multi-Channel Controllers (MCCs)
SI RAM
3–10
Super Channel Table
0
1
2
11–13
CNT
14
15
0–1
2–9
10–15
MCC LOOP SUPER MCSEL
SI RAM Address
BYT LST
CHANNEL NO
DPRAM_Base + SCTPBASE +
—
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
0
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
1
1
1
0
0
1
0
0
1
0
0
0
0
0
0
0
0
1
0x0
0x0
0x2
0x4
0x6
0x8
0xA
0xC
0xE
0x10
1
0x1
0x2
0x2
0x2
—
0x0
1
0x0
2
0x7
2
0x7
0x0
2
0x1
0x1
—
0x7
2
0x7
0x0
1
2
First slot of the super channel
Regular (not first) slot of the super channel
.
The super channel BD tables are associated with channels 1 and 2 (no BD tables are necessary for
channels 3, 4, 6, and 7)
Figure 28-14. Transmitter Super Channel Example
In this example, data is expected to be sent on the first timeslots allocated for each superchannel. Thus for
the first superchannel, timeslot 1 has CNT=0 and BYT=1, the “first byte” condition described in
Table 15-2 and the remaining timeslots that are part of this superchannel—timeslots 6 and 7, have
CNT=0x7 and BYT=1. This indicates to the MCC that when this transparent superchannel becomes active
it should begin sending data on timeslot 1. If the application required that data not be sent on this
superchannel until timeslot 7, for example, then timeslots 1 and 6 have CNT=0x7 and BYT=1 and timeslot
7 would be programmed with CNT=0 and BYT=1.
Similarly, the second superchannel in this example sends data beginning with its first timeslot, timeslot 2.
It contains the “first byte” condition of CNT=0 and BYT=1. If the application required a different timeslot
in this superchannel, either timeslot 3 or 4, that channel could be programmed to have the “first byte”
condition instead.
Figure 28-15 shows the SI RAM programming for transparent receiver superchannels which uses the slot
synchronization. This example assumes a timeslot configuration similar to the transmit example in
Figure 28-14. For this receive example, to guarantee that reception begins on the first timeslots for each
superchannel, all timeslots that correspond to superchannels are programmed as superchannelled timeslots
and the first timeslot for each superchannel is programmed with the “first byte” CNT and BYT conditions.
Note that the receive examples do not include a superchannel table because a superchannel table is only
used on the transmit side. Receive SIRAM entries should always be programmed using the FIFO number
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Multi-Channel Controllers (MCCs)
of the managing MCC channel for that superchannel (the same MCC channel number used in the
superchannel table entries corresponding to the transmit FIFOs for that superchannel).
SI RAM
0
1
2
3–10
11–13
CNT
14
15
MCC LOOP SUPER MCSEL
SI RAM Address
BYT LST
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
0
0x0
0x1
0x2
0x2
0x2
0x5
0x1
0x1
0x8
1
1
1
0
0
1
0
0
1
0
0
0
0
0
0
0
0
1
Regular Channel
Super Channel 1
Super Channel 2
Super Channel 2
Super Channel 2
Regular Channel
Super Channel 1
Super Channel 1
Regular Channel
0x0
1
0x0
1
0x0
2
0x7
2
0x7
0x0
2
0x7
2
0x7
0x0
1
2
First slot of the super channel
Regular (not first) slot of the super channel
The super channel BD tables are associated with channels 1 and 2
Figure 28-15. Receiver Super Channel with Slot Synchronization Example
Figure 28-16 shows the SI RAM programming for the same overall configuration as the previous
examples, but in this case it does not matter to the application what timeslot of a superchannel reception
begins on. Thus, slot synchronization is not necessary and the timeslots do not need to be programmed as
superchannelled timeslots and the CNT and BYT fields may be programed normally.
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Multi-Channel Controllers (MCCs)
SI RAM
3–10
0
1
2
11–13
CNT
14
15
MCC LOOP SUPER MCSEL
SI RAM Address
BYT LST
1
0
0
0x0
1
0
Regular Channel
0x0
0x0
1
1
0
0
0
0
0x1
0x2
1
1
0
0
Super Channel 1
Super Channel 2
0x0
0x0
1
1
0
0
0
0
0x2
0x2
1
1
0
0
Super Channel 2
Super Channel 2
0x0
0x0
1
1
0
0
0
0
0x5
0x1
1
1
0
0
Regular Channel
Super Channel 1
0x0
1
0
0
0x1
1
1
0
1
Super Channel 1
Regular Channel
0x0
0x0
1
0
0
0x8
The super channel BD tables are associated with channels 1 and 2
Figure 28-16. Receiver Super Channel without Slot Synchronization Example
28.6 MCC Configuration Registers (MCCFx)
channels to the TDM channels. MCC1 can be connected to SI1 and MCC2 can be connected to SI2. For
each MCCx-SIx pair, each of the four 32 channels subgroups can be connected to one of the four TDM
highways (TDMA, TDMB, TDMC, and TDMD).
0
1
2
3
4
5
6
7
Field
Reset
R/W
Group 1
Group 2
Group 3
Group 4
0000_0000
R/W
Addr
Figure 28-17. SI MCC Configuration Register (MCCF)
Table 28-15 describes MCCF fields.
Table 28-15. MCCF Field Descriptions
Bits
Name Description
00 Group x is used by TDM A.
01 Group x is used by TDM B.
10 Group x is used by TDM C.
11 Group x is used by TDM D.
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Multi-Channel Controllers (MCCs)
Table 28-16 describes group assignments.
Table 28-16. Group Channel Assignments
Group
Channels
1
1
1
1
Group1 in MCCF1
Group2 in MCCF1
Group3 in MCCF1
Group4 in MCCF1
0–31
32–63
64–95
96–127
128–159
160–191
192–223
224–255
Group1 in MCCF2
Group2 in MCCF2
Group3 in MCCF2
Group4 in MCCF2
1
Not on the MPC8250 nor the MPC8255.
NOTE
The TDM group channel assignments made in MCCF must be coherent with
the SI register programming and SI RAM programming; see Section 15.5,
Entries.” The user must also program MCCF before enabling the TDM
channel in the SIGMR; see Section 15.5.1, “SI Global Mode Registers
(SIxGMR).”
28.7 MCC Commands
The user starts channels by writing to the TSTATE/RSTATE registers as described in Section 28.3.1.4,
The following commands, used to stop and initialize channels, are issued to the MCC by writing to CPCR
using one of the following commands before being used in an active TDM. Not all commands are available
in all revisions of silicon and the user should refer to Section 14.4.1.1, “CP Commands,” for further details.
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Table 28-17. MCC Commands
Description
Command
1
INIT RX AND TX
Performs both INIT RX and INIT TX commands contiguously, using the channel number supplied
with the command.
1
INIT RX
Initializes MCC receive FIFOs in groups of 32 channels, starting with the channel number
programmed in the CPCR[MCN] field when the command is issued. This command should only be
issued when the channels are disabled. To initialize more than 32 channels, reissue the command
with the appropriate channel numbers. The INIT TX AND RX command may be used to initialize
both the receive and transmit sides of an MCC channel at the same time. Note that this command
will initialize the first 16 FIFOs to be preloaded with 16 bits of idle, and the second set of FIFOs will
be completely empty and ready for data. This is done to stagger when FIFOs require servicing and
spread out CPM loading.
1
INIT TX
Initializes MCC transmit FIFOs in groups of 32 channels, starting with the channel number
programmed in the CPCR[MCN] field when the command is issued. This command should only be
issued when the channels are disabled. To initialize more than 32 channels, reissue the command
with the appropriate channel numbers. The INIT TX AND RX command may be used to initialize
both the receive and transmit sides of an MCC channel at the same time. Note that this command
will initialize the first 16 FIFOs to be preloaded with 16 bits of idle, and the second set of FIFOs will
be preloaded with 32 bits of idle. This is done to stagger when FIFOs require servicing and spread
out CPM loading.
1,2
INIT TX AND RX
(16 BITS)
Same as regular INIT RX AND TX, except that all FIFOs are equally preloaded with idle. For
applications in which all channels must begin sending or receiving data in the same TDM frame.
1,2
INIT TX, ONE
CHANNEL
Performs the INIT TX command but only for the channel number programmed in CPCR[MCN] as
opposed to initializing 32 channels at once.
1,2
INIT RX, ONE
CHANNEL
Performs the INIT RX command but only for the channel number programmed in CPCR[MCN] as
opposed to initializing 32 channels at once.
2
MCC RESET
Initializes the state machine hardware of the MCC indicated in CPCR[PAGE] and CPCR[SBC], has
the same effect on the MCC block that a CPM reset does. Required after the GUN or GOV MCC
event occurs. If this command is not available in the revision of silicon being used, a CPM reset is
required instead.
STOP TRANSMIT
STOP RECEIVE
Disables the transmission on the selected channel and clears CHAMR[POL]. When this command
is issued in the middle of a frame, the CP sends an ABORT indication and then idles/flags on the
selected channel. If this command is issued between frames, the CP sends only idles or flags
(depending on CHAMR[IDLM]). TBPTR points for the buffer that the CP was using when the STOP
TRANSMIT command was issued.
Forces the receiver of the selected channel to terminate reception. After this command is executed,
the CP does not change the receive parameters in the dual-port RAM. The user must initialize the
channel receive parameters in order to restart reception.
1
2
The INIT PARAMETERS style commands are also used to reset the MCC channel FIFOs and these commands need to
be issued to cover any channel number used, whether used normally or as part of a superchannel
This command only available on .29µm (HiP3) Revision B.3 and subsequent silicon.
28.8 MCC Exceptions
The MCC interrupt reporting scheme has two levels. The circular interrupt tables (illustrated in
Figure 28-18) report channel-specific events and are masked by each channel’s INTMSK field located in
channel-specific parameter RAM. The MCCE global event register (described in Section 28.8.1, “MCC
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activity has taken place in any of that MCC’s interrupt tables. These events can be masked by the MCCM.
Interrupt Circular Table Entry
T/RINTBASE
0
1
2–17
18–25
26–31
Interrupt Flags
Interrupt Flags
Interrupt Flags
Interrupt Flags
Interrupt Flags
Interrupt Flags
Interrupt Flags
Interrupt Flags
Interrupt Flags
Channel Number
Channel Number
Channel Number
Channel Number
Channel Number
Channel Number
Channel Number
Channel Number
Channel Number
V=0
V=0
V=0
V=0
V=1
V=1
V=0
V=0
V=0
W=0
W=0
W=0
W=0
W=0
W=0
W=0
W=0
W=1
Software Pointer
T/RINTPTR
Figure 28-18. Interrupt Circular Table
There is one table for transmitter interrupts and from one to four tables for receiver interrupts. Each
channel is programmed to report receiver interrupts in one of the receiver tables. This way receiver
interrupts can be sorted, for example, by priority. Each interrupt circular table must be least two entries
long.
T/RINTBASE and T/RINTPTR, which are user-initialized global MCC parameters (See Section 28.2,
“Global MCC Parameters”), point to the starting location of the table (in external memory) and the current
empty position (initialized at the top of the table) available to the CP. All the entries in the table must be
user-initialized with 0x00000000, except for the last one which must be initialized with 0x40000000 (W
= 1, thus defining the end of the table). When an MCC channel generates an interrupt request, the CP writes
a new entry to the table (with V = 1) and increments T/RINTPTR (if W = 1 for the current entry,
T/RINTPTR is loaded with T/RINTBASE).
The circular interrupt tables consist of channel-specific events, with a bit for each possible event as well
as the number of the channel reporting that event. Each channel has an INTMSK field that determines
which events on that particular channel trigger the creation of a new entry in the interrupt tables. Whenever
a new entry is added to an interrupt table, the MCC will set the appropriate TINT or RINTx bit in the
MCCE global event register, if that bit is properly enabled in MCCM global mask register. If there was no
room in the interrupt table for a new entry the corresponding queue overflow (QOVx) bit will be set in the
MCCE and the interrupt information is lost although operation will continue.
After an MCC interrupt reaches the core, the software should read the corresponding MCCE. After
clearing the appropriate event bits by writing ones to them, the software may begin processing the table(s)
that contain pending events, as indicated by the bits MCCE[RINTx] and MCCE[TINT]. When processing
the interrupt tables, the software must clear each entry’s valid bit (V) (see Section 28.8.1.1, “Interrupt
Circular Table Entry”). The user follows this procedure until it reaches an entry with V = 0. It may not be
appropriate for an application to process every new entry of all interrupt tables at once, depending on
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desired interrupt handler latency or other factors. It is up to the user to determine an interrupt handling
scheme that provides desired performance and functionality.
28.8.1 MCC Event Register (MCCE)/Mask Register (MCCM)
The MCC event register (MCCE) is used to report events and generate interrupt requests. For each of its
flags, a programmable mask/enable bit in MCCM determines whether an interrupt request is generated.
The MCC mask register (MCCM) is used to enable/disable interrupt requests. For each flag in the MCCE
there is a programmable mask/enable bit in MCCM which determines whether an interrupt request is
generated. Setting an MCCM bit enables and clearing an MCCM bit disables the corresponding interrupt.
MCCE bits are cleared by writing ones to them; writing zeros has no effect.
Figure 28-19 shows MCCE and MCCM bits.
0
1
2
3
4
5
6
7
8
11
12
13
14
15
Field QOV0 RINT0 QOV1 RINT1 QOV2 RINT2 QOV3 RINT3
—
TQOV TINT GUN GOV
Reset
R/W
0000_0000_0000_0000
R/W
Addr
Figure 28-19. MCC Event Register (MCCE)/Mask Register (MCCM)
Table 28-18 describes MCCE fields.
Table 28-18. MCCE/MCCM Register Field Descriptions
Bits
Name
Description
0
1
QOV0 QOVx—Receive interrupt queue overflow. IQOV is set (and an interrupt request generated) by the CP
whenever an overflow occurs in the transmit circular interrupt table. This occurs if the CP tries to
RINT0
update an interrupt entry that was not handled by the user (such an entry is identified by V = 1).
RINTx—Receive interrupt. When RINT = 1, the MCC generated at least one new entry in the receive
interrupt circular table. After clearing it, the user reads the next entry from the receive interrupt circular
2
QOV1
table and starts processing a specific channel’s exception. The user returns from the interrupt handler
when it reaches a table entry with V = 0.
3
RINT1
QOV2
RINT2
QOV3
RINT3
—
4
5
6
7
8–11
12
Reserved, should be cleared.
TQOV Transmit interrupt queue overflow. TQOV is set (and interrupt request generated) by the CP whenever
an overflow occurs in the transmit circular interrupt table. This condition occurs if the CP attempts to
write a new interrupt entry into an entry that was not handled by the user. Such an entry is identified
by V = 1.
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Table 28-18. MCCE/MCCM Register Field Descriptions (continued)
Description
Bits
Name
13
TINT Transmit interrupt. When TINT = 1, at least one new entry in the transmit interrupt circular table was
generated by MCC. After clearing it, the user reads the next entry from the transmit interrupt circular
table and starts processing a specific channel’s exception. The user returns from the interrupt handler
when it reaches a table entry with V = 0.
14
15
GUN Global transmit underrun. This flag indicates whether an underrun occurred inside the MCC’s transmit
FIFO array (see Section 28.8.1.2, “Global Transmitter Underrun (GUN)”). The user must clear this bit.
GOV Global receiver overrun. This flag indicates whether an overrun occurred inside the MCC’s receive
28.8.1.1 Interrupt Circular Table Entry
Each interrupt circular table entry, shown in Figure 28-20, contains information about channel-specific
events. The transmit circular table shows only events caused by transmission; the receive circular tables
shows only events caused by reception. The corresponding interrupt mask bits are mode-dependent; refer
to the appropriate section:
•
•
•
•
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
1
1
1
Field
R/W
V
W
OCT SUERM FISU
—
UN TXB
—
AERM NID IDL MRF RXF BSY RXB
—
2
2
—
—
SLIPE SLIPS
R/W
16
17
18
25
26
31
Field
R/W
—
Channel Number
—
R/W
Figure 28-20. Interrupt Circular Table Entry
1
2
SS7 mode only. Otherwise, reserved.
Only used in conjunction with AAL1 CES.
Table 28-19 describes interrupt circular table fields.
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Table 28-19. Interrupt Circular Table Entry Field Descriptions
Bits
Name
V
Description
0
Valid bit. V = 1 indicates that this entry contains valid interrupt information. Upon generating a new
entry, the CP sets V = 1. The user clears V immediately after it reads the interrupt flags of the entry
(before processing the interrupt). The V bits in the table are user-initialized. During initialization, the
user must clear those bits in all table entries.
1
2
W
Wrap bit. W = 1 indicates the last interrupt circular table entry. The next event’s entry is written/read
initialization, the user must clear all W bits in the table except for the last one which must be set.
—
Reserved, should be cleared. (If SS7 mode, refer to the following description.)
OCT
SS7 mode only: N octets received. If the channel is in octet counting, this bit is set when N octets
have been received.
3
4
—
Reserved, should be cleared. (If SS7 mode, refer to the following description.)
SUER SS7 mode only: SU error monitor threshold reached. The SU error monitor has reached the
M
programmed threshold T.
FISU
SS7 mode only: FISU transmission started. The CP has started automatic FISU transmission if the
first BD of frame does not have its ready bit set and the SEN_FISU bit is enabled in SS7_OPT
register. Please refer to SEN_FISU bit in Section 28.3.4.3, “SS7 Configuration Register—SS7
Mode.
SLIPE Only used in conjunction with AAL1 CES. Slip End. Set when an MCC channel interworking with an
ATM channel exits the slip state (the connection’s CESAC falls to the MCC_Start threshold). At this
point, the transmitter stops sending the underrun template (or last buffer) and starts sending valid
data.
5
—
Reserved, should be cleared.
SLIPS Only used in conjunction with AAL1 CES.Slip Start. Set when an MCC channel interworking with an
ATM channel enters a slip state (the channel’s CESAC reaches the MCC_Stop threshold). At this
point the transmitter freezes and begins sending the underrun template (or last buffer) until CESAC
falls to the MCC_Start threshold.
6
7
UN
Tx no data. The CP sets this flag if there is no data available to be sent to the transmitter. The
transmitter sends an ABORT indication and then sends idles.
TXB Tx buffer. A buffer has been completely transmitted. TXB is set (and an interrupt request is
generated) as soon as the programmed number of PAD characters (or the closing flag, for PAD = 0)
is written to MCC transmit FIFO. This controls when the TXB interrupt is given in relation to the
characters are used.
8
9
—
—
Reserved, should be cleared.
Reserved, should be cleared. (If SS7 mode, refer to the following description.)
AERM SS7 mode only: Alignment error rate monitor threshold (M value in SS7 channel-specific
parameters) has been reached.
10
11
NID
IDL
Set whenever a pattern that is not an idle pattern is identified.
Idle. Set when the channel’s receiver identifies the first occurrence of idle (0xFFFE) after any
non-idle pattern.
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Table 28-19. Interrupt Circular Table Entry Field Descriptions (continued)
Name Description
Bits
12
MRF Maximum receive frame length violation. This interrupt occurs when more bytes are received than
the value specified in MFLR. This interrupt is generated as soon as the MFLR value is exceeded;
the remainder of the frame is discarded
13
14
15
RXF Rx frame. A complete HDLC frame has been received.
BSY Busy. A frame was received but was discarded due to lack of buffers.
RXB Rx buffer. A buffer has been received on this channel that was not the last buffer in frame. This
interrupt is also given for different error types that can happen during reception. Error conditions are
reported in the RxBD.
16–17
18–25
26–31
—
CN
—
Reserved, should be cleared.
Channel number. Identifies the requests channel index (0–255).
Reserved, should be cleared.
28.8.1.2 Global Transmitter Underrun (GUN)
A global underrun (GUN) event indicates that the MCC’s transmit FIFO array experienced an underrun
condition. This is not due to a lack of ready transmit buffer descriptors (as in the UN condition in an
interrupt queue entry); rather, it indicates a hardware latency issue which could be caused in several ways.
It is not possible to determine exactly which channel's FIFO experienced the underrun, therefore a GUN
is considered a global event affecting that entire MCC. Following the assertion of MCCE[GUN], the MCC
stops transmitting data on all channels and all ones are sent instead. The MCC must be reset either through
an MCC RESET command or a CPM RESET after this error and then the MCC may be reinitialized.
There are several possible causes for an MCC GUN error:
•
•
•
•
•
Glitching on the TDM clock. Refer to Section 28.8.1.2.1.
Synchronization pulse (sync pulse). Refer to Section 28.8.1.2.2.
CPM bandwidth. Refer to Section 28.8.1.2.5.
CPM priority. Refer to Section 28.8.1.2.6.
28.8.1.2.1
TDM Clock
Glitches on the TDM clock may be interpreted as an overwhelming number of clocks that the SI may try
to process (amongst other anomalous behavior), thus draining the MCC FIFOs on that TDM much too
quickly. This results in a GUN.
28.8.1.2.2
Synchronization Pulse
A TDM frame length, as programmed in SIRAM, that is shorter than the actual gap between sync pulses
may cause an underrun condition (in other words, if SIRAM programming hits an entry with
SIxRam[LST] set and then encounters dead time before the next sync pulse on the line). This may result
in anomalous behavior in the SI and therefore an underrun condition.
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To avoid these cases, pad out the SIRAM programming with “null entries,” entries with no CPM peripheral
specified (MCC=0 and CSEL = 0000 in SIRAM entry) at the end of the SIRAM programming. Make the
null SIRAM entries represent the appropriate amount of time so that the SI frame length matches the gap
between sync pulses.
28.8.1.2.3
SIRAM Programming
Failure to follow SIRAM programing guidelines can result in erratic behavior or possibly GUN errors. The
following is a list of common programming errors:
•
Failing to set “LAST” in the final entry of an even-numbered total of SIRAM entries (i.e. there
cannot be an odd total of SIRAM entries for a TDM)
•
Programming an SIRAM entry to use an un-initialized MCC channel (or if the MCC as whole has
not been initialized with the appropriate “INIT TX RX” commands).
•
•
•
Programming an SIRAM entry to use an MCC channel that is not assigned to that particular TDM.
Using a channel too often (which would overload the FIFO) without going to superchannels.
Turning on too many MCC channels at once in the SIRAM (we suggest not to enable more than 32
channels per TDM frame's worth of time when you are first programming the SI).
•
Other programming errors, such as incorrect values in the SIRAM entries, etc.
28.8.1.2.4
MCC Initialization
CPCR commands for the MCC (such as Init Tx Parameters and Init Rx Parameters) must be issued to cover
all MCC channel numbers that appear in either the SIRAM or superchannel table before that channel
number is used on an active TDM. Note that the command initializes 32 channels at a time, starting with
the channel number given in the command. All channels used in any fashion must be initialized by the
Init Tx parameters and the Init Rx parameters command.
Before a TDM is enabled to use an MCC channel, the following must be initialized:
•
•
•
•
Global MCC parameters
Channel Extra Parameters
Channel-Specific Parameters
Super-Channel Table (if appropriate) and registers
If the MCC has invalid data in any of these areas when the SI tries to talk to the MCC, a GUN is one of
the possible symptoms. Before a TDM is programmed to use an MCC channel, the channel-specific fields
RSTATE and TSTATE must either contain the start value or “STOP TX” and “STOP RX” commands must
be issued to that channel. It is not a valid condition to leave RSTATE and TSTATE unitialized before TDM
operation using that channel
28.8.1.2.5
CPM Bandwidth
If the CPM is overloaded, the MCC is usually one of the first communications controllers to exhibit
problems, often in the form of the GUN. The MCC's sensitivity to bandwidth issues is due to the
shallowness of the FIFOs and the CPM prioritization of the MCC TX.
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28.8.1.2.6
CPM Priority
It is possible for the MCC to experience a GUN due to prioritization in the CPM. See Section 14.3.5,
“Peripheral Interface,” for details on the CPM prioritization scheme. There are some options available for
altering how the CPM peripheral prioritization works. These options provide the opportunity for the user
to raise the priority of the MCC itself or lower the priority of other peripherals.
In .29 µm (HiP3) Rev C.2 and subsequent silicon, RCCR[MCCPR] controls the MCC priority in relation
to other CPM peripherals (refer to Section 14.3.7, “RISC Controller Configuration Register (RCCR)”).
When MCCPR is set, the MCCs are constantly at emergency priority level within the CPM prioritization
scheme. If used, this configuration should be tested to ensure that the setting of MCCPR does not have
adverse effects on the performance of other peripherals being used in an application. When MCCPR is
Each FCC FIFO has threshold values, determined by the mode it is using, for determining normal and
emergency CPM request prioritization. When an FCC is in emergency mode, that FCC's TX or RX request
may have higher priority than MCC TX or RX. When FCC1 in particular is in emergency priority mode,
it will always be of higher priority than an MCC. This opens up the possibility of the FCC starving out the
MCC if the FCC continues to be overutilized. This can lead to a GUN. To help alleviate this situation,
setting FPSMR[TPRI] prevents the FCC’s TX from going into emergency mode and can minimize the risk
of global underrun.
28.8.1.2.7
Bus Latency
A GUN may also occur if the external memory bus bandwidth is insufficient for the system. Factors could
include a bus that is too slow or external masters keeping the bus for extended periods of time. Bus
parking master and bus arbiter configurations as described in Section 4.3.2, “System Configuration and
prioritized for bus access.
28.8.1.3 Recovery from GUN Errors
The GUN error is considered fatal because it cannot be determined which channel was at fault. In .29 µm
(HiP3) Rev. B.2 and earlier silicon, the only way to recover from MCC global underrun event is by
resetting the entire CPM. In .29 µm Rev. B.3 and subsequent silicon, the MCC Reset command was added
to CP command register [CPCR]. The MCC RESET provides a hard reset to the MCC FIFOs. Refer to the
following tables.
Table 28-20. GUN Error Recovery—.29µm (HiP3) Rev A.1 and B.2 Silicon
Step
Action
1
2
Disable the TDM by clearing the appropriate enable bit in SIxGMR[4-7].
Reset the CPM by writing 0x8000_0000 to the CPCR (setting RST). This resets the registers and
parameters for all the channels as well as the CP and RISC timer tales.
3
4
5
Issue the INIT RX AND TX command to cover the channels in use.
Reprogram the specific MCC channel, global parameters, and any BDs that need to be updated.
Enable TDM by setting appropriate bit.
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Table 28-21. GUN Error Recovery—.29µm (HiP3) Rev B.3 and Subsequent Silicon
Step
Action
1
2
3
4
5
Disable the TDM by clearing the appropriate enable bit in SIxGMR[4-7].
Issue the MCC RESET command.
Issue the INIT RX AND TX command to cover the channels in use.
Reprogram the specific MCC channel, global parameters, and any BDs that need to be updated.
Enable TDM by setting appropriate bit.
28.8.1.4 Global Overrun (GOV)
An MCC receiver global overrun (GOV) is the receive version of the transmit GUN. Due to different
prioritization and implementation of MCC RX, the likelihood of a GOV occurring is less than a the
likelihood of a GUN. Despite this, all possible causes and recovery procedures apply.
28.9 MCC Buffer Descriptors
Each MCC channel requires two BD tables (one for transmit and one for receive). Each BD contains key
information about the buffer it defines. The BDs are accessed by the MCC as needed; BDs can be added
dynamically to the BDs chain. The RxBDs chain must include at least two BDs; the TxBD chain must
include at least one BDs.
The MCC BDs are located in the external memory.
28.9.1 Receive Buffer Descriptor (RxBD)
Figure 28-21 shows the RxBD.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
Offset + 0
Offset + 2
Offset + 4
Offset + 6
E
—
W
I
L
F
CM
—
UB
—
LG
NO
AB
CR SF
—
Data Length
Rx Data Buffer Pointer
Figure 28-21. MCC Receive Buffer Descriptor (RxBD)
SS7 mode only. Otherwise, reserved.
1
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Table 28-22. RxBD Field Descriptions
Description
Bits
Name
E
0
Empty
0 The data buffer associated with this BD has been filled with received data, or data reception has
been aborted due to an error condition. The user is free to examine or write to any fields of this
RxBD. The CP does not use this BD again while the empty bit remains zero.
1 The data buffer associated with this BD is empty, or reception is in progress. This RxBD and its
associated receive buffer are in use by the CP. When E = 1, the user should not write any fields
of this RxBD.
1
2
—
Reserved, should be cleared.
W
Wrap (final BD in table)
0 This is not the last BD in the RxBD table.
1 This is the last BD in the RxBD table. After this buffer has been used, the CP receives incoming
data into the first BD in the table (the BD pointed to by RBASE). The number of RxBDs in this
table is programmable and is determined by the wrap bit.
3
4
I
Interrupt
0 The RXB bit is not set after this buffer has been used, but RXF operation remains unaffected.
1 The RXB or RXF bit in the HDLC interrupt circular table entry is set when this buffer has been
used by the HDLC controller. These two bits may cause interrupts (if enabled).
L
Last in frame (only for HDLC mode of operation). The HDLC controller sets L = 1, when this buffer
is the last in a frame. This implies the reception either of a closing flag or of an error, in which case
one or more of the CD, OV, AB, and LG bits are set. The HDLC controller writes the number of frame
octets to the data length field.
0 This buffer is not the last in a frame.
1 This buffer is the last in a frame.
5
6
F
First in frame. The HDLC controller sets F = 1 for the first buffer in a frame. In transparent mode, F
indicates that there was a synchronization before receiving data in this BD.
0 This is not the first buffer in a frame.
1 This is the first buffer in a frame.
CM
Continuous mode
0 Normal operation (The empty bit (bit 0) is cleared by the CP after this BD is closed).
1 The empty bit (bit 0) is not cleared by the CP after this BD is closed, allowing the associated data
buffer to be overwritten automatically when the CP next accesses this BD. However, if an error
occurs during reception, the empty bit is cleared regardless of the CM bit setting.
7
8
—
Reserved, should be cleared.
UB
User bit. UB is a user-defined bit that the CPM never sets nor clears. The user determines how this
bit is used.
9
—
Reserved, should be cleared.
10
LG
Rx frame length violation (HDLC mode only). Indicates that a frame length greater than the
maximum value was received in this channel. Only the maximum-allowed number of bytes, MFLR
rounded to the nearest higher word alignment, are written to the data buffer. This event is recognized
as soon as the MFLR value is exceeded when data is word-aligned. When data is not word-aligned,
this interrupt occurs when the SDMA writes 64 bits to memory. The worst-case latency from MFLR
violation until detected is 7 bytes timing for this channel. When MFLR violation is detected, the
receiver is still receiving even though the data is discarded. The buffer is closed upon detecting a
flag, and this is considered to be the closing flag for this buffer. At this point, LG is set (1) and an
interrupt may be generated. The length field for this buffer is everything between the opening flag
and this last identifying flag.
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Table 28-22. RxBD Field Descriptions (continued)
Description
Bits
Name
11
NO
Rx nonoctet-aligned frame. A frame of bits not divisible exactly by eight was received. NO = 1 for
any type of nonalignment regardless of frame length. The shortest frame that can be detected is of
type FLAG-BIT-FLAG, which causes the buffer to be closed with NO error indicated.
The following shows how the nonoctet alignment is reported and where data can be found.
msb
xxx .................................... xx
Valid data
lsb
000...... 0
Invalid data
1
To accommodate the extra word of data that may be written at the end of the frame, it is
recommended to reserve MFLR + 8 bytes for each buffer data.
12
AB
CR
Rx abort sequence. A minimum of seven consecutive 1s was received during frame reception. Abort
is not detected between frames. The sequence
Closing-Flag, data, CRC, AB, data, opening-flag...
does not cause an abort error. If the abort is long enough to be an idle, an idle line interrupt may be
generated. An abort within the frame is not reported by a unique interrupt but rather with a RXF
interrupt and the user has to examine the BD.
13
14
Rx CRC error. This frame contains a CRC error. The received CRC bytes are always written to the
receive buffer.
—
SF
—
Reserved, should be cleared.
SS7 mode only: Short frame indication. Set if the received frame is less than 5 octets.
Reserved, should be cleared.
15
The data length and buffer pointer are described as follows:
•
Data length. Data length is the number of octets written by the CP into this BD’s data buffer. It is
written by the CP when the BD is closed. When this is the last BD in the frame (L = 1), the data
length contains the total number of frame octets (including two or four bytes for CRC). Note that
memory allocated for buffers should be not smaller than the contents of the maximum receive
buffer length register (MRBLR). The data length does not include the time stamp.
•
Rx buffer pointer. The receive buffer pointer points to the first location of the associated data
buffer. This value must be equal to 8*n if CHAMR[TS] = 0 and equal to 8*n - 4 if CHAMR[TS]
= 1 (where n is any integer larger than 0).
28.9.2 Transmit Buffer Descriptor (TxBD)
Figure 28-22 shows the TxBD.
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28-45
Multi-Channel Controllers (MCCs)
0
1
2
3
4
5
6
7
8
9
10
11
12
15
1
1
Offset + 0
Offset + 2
Offset + 4
Offset + 6
R
RT
W
I
L
TC
CM
—
UB
—
SUD
PAD
Data Length
Tx Data Buffer Pointer
1
SS7 mode only. Otherwise, reserved.
Figure 28-22. MCC Transmit Buffer Descriptor (TxBD)
Table 28-23 describes TxBD fields.
Table 28-23. TxBD Field Descriptions
Bits
Name
R
Description
0
Ready
0 The buffer associated with this BD is not ready for transmission. The user is free to manipulate
this BD or its associated data buffer. The CP clears this bit after the buffer has been transmitted
or after an error condition is encountered.
1 The data buffer is ready to be transmitted. The transmission may have begun, but it has not
completed. The user cannot modify this BD once this bit is set.
1
RT
SS7 mode only: Retransmit.
0 Normal operation
1 The CP repeats transmission of this BD until the RT bit is cleared. After the RT bit is cleared the
CP advances to the next BD in the table. This feature is useful for automatic LSSU
retransmission.
Note: This bit is reserved in all other modes of operation.
2
3
W
Wrap (final BD in table)
0 This is not the last BD in the TxBD table.
1 This is the last BD in the TxBD table. After this buffer is used, the CP receives incoming data into
the first BD in the table (the BD pointed to by TBASE). The number of TxBDs in this table is
programmable and is determined the wrap bit.
I
Interrupt
0 No interrupt is generated after this buffer has been serviced.
1 The TXB bit in the event register is set when this buffer is serviced. TXB can cause an interrupt
if enabled.
4
5
L
Last
0 This is not the last buffer in the frame.
1 This is the last buffer in the current frame.
TC
Tx CRC. Valid only when L = 1. Otherwise it is ignored.
0 Transmit the closing flag after the last data byte. This setting can be used for testing purposes to
send an erroneous CRC after the data.
1 Transmit the CRC sequence after the last data byte.
6
7
CM
Continuous mode
0 Normal operation.
1 The CP does not clear the ready bit after this BD is closed, allowing the associated data buffer to
be retransmitted automatically when the CP next accesses this BD. However, the R bit is cleared
if an error occurs during transmission, regardless of the CM bit setting.
—
Reserved, should be cleared.
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Multi-Channel Controllers (MCCs)
Table 28-23. TxBD Field Descriptions (continued)
Description
Bits
Name
UB
8
User bit. UB is a user-defined bit that the CPM never sets nor clears. The user determines how this
bit is used.
9–10
11
—
—
Reserved, should be cleared.
Reserved, should be cleared.
SUD
SS7 mode only: Signal unit delay
0 This buffer does not have a transmission delay.
1 A time delay of JTTDelay x 512 µs passes before this buffer is transmitted. Can be used for LSSU
transmission according to the JT Q.703 Standard which defines a 24 ms delay between
back-to-back LSSUs. This bit is only valid when SS7_OPT[STD] is set.
12–15
PAD Pad characters. These four bits indicate the number of PAD characters (0x7E or 0xFF depending on
the IDLM mode selected in the CHAMR register) that the transmitter sends after the closing flag.
The transmitter issues a TXB interrupt only after sending the programmed number of pads to the Tx
FIFO buffer. The user can use the PAD value to guarantee that the TXB interrupt occurs after the
closing flag has been sent out on the TXD line. PAD = 0, means that the TXB interrupt is issued
immediately after the closing flag is sent to the Tx FIFO buffer. The number of PAD characters
depends on the FIFO size assigned to the channel in the MCC hardware. If the channel is not part
of a super channel then the MCC hardware assigns to this channel a fifo of 4 bytes. So in this case
a pad of 4 bytes ensures that the TXB interrupt is not given before the closing flag has been
transmitted over the TXD line. For a super channel, the FIFO length equals the number of time slots
assigned to the super channel multiplied by two.
The data length and buffer pointer are described below:
•
Data length. The data length is the number of bytes the MCC should transmit from this BD’s data
buffer. It is never modified by the CP. The value of this field should be greater than zero.
•
Tx buffer pointer. The transmit buffer pointer, which contains the address of the associated data
buffer, may be even or odd provided that SS7_OPT[SEN_FIS] = 0 (refer to Section 28.3.4.3, “SS7
must be 4-byte aligned. The buffer must reside in external memory. This value is never modified
by the CP.
28.10 MCC Initialization and Start/Stop Sequence
The MCC must be initialized and started/stopped in relation with the corresponding TDMs. The following
section presents the initialization and start/stop sequences which must be followed for single and super
channels.
The following is a general sequence for initializing an MCC and its channels after reset:
1. Program the parallel I/O port interface for the TDM to be used (refer to Chapter 40, “Parallel I/O
2. Program the SIU’s interrupt controller to mask or enable MCC-related interrupts as desired (refer
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28-47
Multi-Channel Controllers (MCCs)
3. Program the SI’s SIRAM and related registers. If the user wishes to enable the TDM at this time,
the SIRAM programming cannot yet contain MCC-related timeslots. Those timeslots should be
NULL entries and not programmed for MCC usage until after MCC-related initialization is
details.
4. Initialize buffer descriptors and data buffers as needed.
5. Initialize all MCC global parameters.
6. Initialize MCC channel-specific parameters for channels to be used. (Note that, if SI was not
already enabled in step 3, TSTATE and RSTATE can be fully programmed here to begin data
transmission and reception as soon as the TDM is enabled. If a user wishes to wait until after the
TDM is enabled before starting data transmission and reception, the user may program only the
FCR portions of RSTATE and TSTATE; and STOP TX and STOP RX commands should be issued
for the appropriate channels before enabling the TDM.)
7. Initialize MCC channel-extra parameters for channels to be used.
8. Initialize Superchannel Table if superchannels are to be used.
9. Issue MCC INIT commands as appropriate to make sure all MCC FIFOs that are to be used are
initialized.
10. Enable TDM (or if TDM is already enabled, the user may now reprogram the TDM to include
MCC-related timeslots).
11. If the user did not program a channel’s TSTATE and RSTATE in step 6 to begin data transmission
and reception immediately upon having an active TDM, the user may program the start conditions
at this time.
NOTE
Some steps may be performed out of order. However, it is critical, regardless
of their relative sequence, that steps 5, 6, 7, 8 and 9 occur before the
enabling of the TDM or an active TDM is reprogrammed to include
MCC-related timeslots. Failure to properly initialize MCC parameters and
issue appropriate INIT commands before MCC-related timeslots are
programmed in an active TDM may result in spurious GUN events or other
anomalous behavior.
28.10.1 Stopping and Restarting a Single-Channel
The following sequence must be followed to stop a single channel in order to change the MCC parameters
of the respective channel:
wait for two frame periods in order to clear the internal FIFOs.
2. Change the channel parameters.
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Multi-Channel Controllers (MCCs)
The following sequence must be followed to stop a single channel in order to change the SI without using
the shadow SI:
Commands.”
2. Change the SI.
Mode.”
It is possible to change the SI using the SI shadow while the channel is active. Both the primary and the
shadow configuration of the SI RAM must observe the configuration defined in MCCF (see Section 28.6,
channels.
28.10.2 Stopping and Restarting a Superchannel
The following sequence must be followed to stop a super channel in order to change the SI:
Commands.”
2. Disable the TDM.
3. Change the SI.
4. Enable the TDM.
5. If necessary, change the MCC parameters (in DPRAM and external memory).
Mode.”
Under the following restrictions, the SI can be changed using the SI shadow while the channel is active:
•
Both the primary and the shadow configuration of the SI RAM must observe the configuration of
the super channel. Note that the super-channel table and MCCF register cannot be changed
dynamically.
•
A time slot that was previously used by a single channel and had a width different from 8 bits
cannot be added dynamically to a super channel.
28.11 MCC Latency and Performance
The CPM moves data between an MCC channel's FIFOs and temporary 8 byte data buffers in the
corresponding channel-specific parameter RAM. RX FIFOs provide data to the ZDSTATE fields and TX
FIFOs are fed from the ZISTATE fields. This traffic is considered completely internal to the CPM.
In addition to the loading and storing of buffer descriptors, the CPM transfers data for an MCC channel
to/from external memory 8 bytes at a time, to replenish or empty the ZISTATE and ZDSTATE fields as
appropriate. The user may then estimate how frequently the MCC will need to transfer data on an external
bus for a particular channel by calculating how quickly 8 bytes will be sent or received on that channel.
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Multi-Channel Controllers (MCCs)
If multiple synchronized TDMs are used (as an example 8 T1 with common clock/sync) it is recommended
to start the TDMs out of phase relative to each other, in order to spread out CPM and bus utilization. This
avoids CPM and bus activity peaks when all the channels would require CPM attention and possibly have
to transfer data to/from the memory simultaneously.
When MCC FIFO activity starts, the MCC begins to consume CPM bandwidth immediately upon enabling
a TDM which has MCC-related SIRAM programming. This is regardless of whether a channel is stopped
or has the “start condition” programmed in the RSTATE and TSTATE channel-specific parameters. If a
user wishes to spread out CPM and bus utilization for the MCC channels on a particular TDM, those
channels must be dynamically added to the SIRAM programming in an evenly distributed fashion over
multiple TDM frames.
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Chapter 29
Fast Communications Controllers (FCCs)
NOTE
The MPC8255 has only two FCCs—FCC1 and FCC2.
The PowerQUICC II’s three fast communications controllers (FCCs) are serial communications
controllers (SCCs) optimized for synchronous high-rate protocols. FCC key features include the
following:
•
•
•
•
•
Supports HDLC/SDLC and totally transparent protocols
FCC clocks can be derived from a baud-rate generator or an external signal.
Supports RTS, CTS, and CD modem control signals
Use of bursts to improve bus usage
Multibuffer data structure for receive and transmit, external buffer descriptors (BDs) anywhere in
system memory
•
•
•
192-byte FIFO buffers
Full-duplex operation
Fully transparent option for one half of an FCC (receiver/transmitter) while HDLC/SDLC protocol
executes on the other half (transmitter/receiver)
•
•
Echo and local loopback modes for testing
Assuming a 100-MHz CPM clock, the FCCs support the following:
– Full 10/100-Mbps Ethernet/IEEE 802.3x through an MII
– Full 155-Mbps ATM segmentation and reassembly (SAR) through UTOPIA (on FCC1 and
FCC2 only) (not available on the MPC8250)
– 45-Mbps (DS-3/E3 rates) HDLC and/or transparent data rates supported on each FCC
FCCs differ from SCCs as follows:
•
•
•
•
No DPLL support.
No BISYNC, UART, or AppleTalk/LocalTalk support.
No HDLC bus.
Ethernet support only through an MII.
29.1 Overview
PowerQUICC II FCCs can be configured independently to implement different protocols. Together, they
can be used to implement bridging functions, routers, and gateways, and to interface with a wide variety
of standard WANs, LANs, and proprietary networks. FCCs have many physical interface options such as
interfacing to TDM buses, ISDN buses, standard modem interfaces, fast Ethernet interface (MII), and
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Fast Communications Controllers (FCCs)
ATM interfaces (UTOPIA); see Chapter 15, “Serial Interface with Time-Slot Assigner,” Chapter 35, “Fast
independent from the physical interface, but FCC logic formats and manipulates data from the physical
interface. That is why the interfaces are described separately.
The FCC is described in terms of the protocol that it is chosen to run. When an FCC is programmed to a
certain protocol, it implements a certain level of functionality associated with that protocol. For most
protocols, this corresponds to portions of the link layer (layer 2 of the seven-layer OSI model). Many
functions of the FCC are common to all of the protocols. These functions are described in the FCC
description. Following that, the implementation details that differentiate protocols from one another are
discussed, beginning with the transparent protocol. Thus, the reader should read from this point to the
transparent protocol and then skip to the appropriate protocol. Since the FCCs use similar data structures
across all protocols, the reader's learning time decreases dramatically after understanding the first protocol.
Each FCC supports a number of protocols—Ethernet, HDLC/SDLC, ATM, and totally transparent
operation. Although the selected protocol usually applies to both the FCC transmitter and receiver, half of
one FCC can run transparent operation while the other runs HDLC/SDLC protocol. The internal clocks
(RCLK, TCLK) for each FCC can be programmed with either an external or internal source. The internal
clocks originate from one of the baud-rate generators or one of the external clock signals. The limitation
of the internal clocks frequency depends on the protocol being used, see Table 29-1. See Chapter 15,
“Serial Interface with Time-Slot Assigner.” However, the FCC’s ability to support a sustained bit stream
depends on the protocol as well as on other factors.
Each FCC can be connected to its own set of pins on the PowerQUICC II. This configuration, the
nonmultiplexed serial interface, or NMSI, is described in Chapter 15, “Serial Interface with Time-Slot
Assigner.” In this configuration, each FCC can support the standard modem interface signals (RTS, CTS,
and CD) through the appropriate port pins and the interrupt controller. Additional handshake signals can
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Fast Communications Controllers (FCCs)
60x Bus
Control
Registers
TCLK
Clock
Peripheral Bus
Generator
RCLK
Internal Clocks
Receive
Data
FIFO
Transmit
Data
FIFO
Receive
Control
Unit
Transmit
Modem Lines
Control
Modem Lines
Decoder
Unit
TXD
RXD
Delimiter
Shifter
Shifter
Delimiter
Encoder
Figure 29-1. FCC Block Diagram
Table 29-1. Internal Clocks to CPM Clock Frequency Ratio
Mode Internal Clock: CPM clock frequency ratio
HDLC 1 bit
1:4
1:4
1:6
Transparent 1 bit
HDLC nibble
Fast Ethernet
ATM
1:3 (1:3.5 preferred)
1:3 (1:3.5 preferred)
29.2 General FCC Mode Registers (GFMRx)
Each FCC contains a general FCC mode register (GFMRx) that defines common FCC options and selects
the protocol to be run. The GFMRx are read/write registers cleared at reset. Figure 29-2 shows the GFMR
format.
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29-3
Fast Communications Controllers (FCCs)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Field
Reset
R/W
DIAG
TCI TRX TTX CDP CTSP CDS CTSS
—
0000_0000_0000_0000
R/W
Addr
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Field
Reset
R/W
SYNL
RTSM
RENC
REVD
TENC
TCRC
ENR ENT
MODE
0000_0000_0000_0000
R/W
Addr
0x11302 (GFMR1), 0x11322 (GFMR2), 0x11342 (GFMR3)
Figure 29-2. General FCC Mode Register (GFMR)
Table 29-2. describes GFMR fields.
Table 29-2. GFMR Register Field Descriptions
Bits
Name
Description
0–1
DIAG Diagnostic mode.
00 Normal operation—Receive data enters through RXD, and transmit data is shifted out through
TXD. The FCC uses the modem signals (CD and CTS) to automatically enable and disable
01 Local loopback mode—Transmitter output is connected internally to the receiver input, while the
receiver and the transmitter operate normally. RXD is ignored. Data can be programmed to
appear on TXD, or TXD can remain high by programming the appropriate parallel port register.
RTS can be disabled in the appropriate parallel I/O register. The transmitter and receiver must
use the same clock source, but separate CLKx pins can be used if connected to the same
external clock source.
If external loopback is preferred, program DIAG for normal operation and externally connect TXD
and RXD. Then, physically connect the control signals (RTS connected to CD, and CTS
grounded) or set the parallel I/O registers so CD and CTS are permanently asserted to the FCC
by configuring the associated CTS and CD pins as general-purpose I/O.; see Chapter 40,
10 Automatic echo mode—The channel automatically retransmits received data, using the receive
clock provided. The receiver operates normally and receives data if CD is asserted. The
transmitter simply transmits received data. In this mode, CTS is ignored. The echo function can
also be accomplished in software by receiving buffers from an FCC, linking them to TxBDs, and
transmitting them back out of that FCC.
11 Loopback and echo mode—Loopback and echo operation occur simultaneously. CD and CTS
are ignored. Refer to the loopback bit description for clocking requirements.
2
TCI
Transmit clock invert
0
1
Normal operation.
The FCC inverts the internal transmit clock.
The edge on which the FCC outputs the data depends on the protocol:
• In HDLC and Transparent mode, when TCI=0, data is sent on the falling edge; when TCI=1, on
the rising edge.
• In Ethernet mode, when TCI=0, data is sent on the rising edge; when TCI=1, on the falling edge.
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Fast Communications Controllers (FCCs)
Table 29-2. GFMR Register Field Descriptions (continued)
Description
Bits
Name
3
TRX Transparent receiver. The PowerQUICC II FCCs offer totally transparent operation. However, to
increase flexibility, totally transparent operation is configured with the TTX and TRX bits instead of
the MODE bits. This lets the user implement unique applications such as an FCC transmitter
configured to HDLC and a receiver configured to totally transparent operation. To do this, program
MODE = HDLC, TTX = 0, and TRX = 1.
0 Normal operation
1 The receiver operates in totally transparent mode, regardless of the protocol selected for the
transmitter in the MODE bits.
Note: Full-duplex, totally transparent operation for an FCC is obtained by setting both TTX and TRX.
Attempting to operate an FCC with Ethernet or ATM on its transmitter and transparent
operation on its receiver causes erratic behavior. In other words, if the MODE = Ethernet or
ATM, TTX must equal TRX.
4
TTX Transparent transmitter. The PowerQUICC II FCCs offer totally transparent operation. However, to
increase flexibility, totally transparent operation is configured with the TTX and TRX bits instead of
the MODE bits. This lets the user implement unique applications, such as configuring an FCC
receiver to HDLC and a transmitter to totally transparent operation. To do this, program MODE =
HDLC, TTX = 1, and TRX = 0.
0 Normal operation.
1 The transmitter operates in totally transparent mode, regardless of the receiver protocol selected
in the MODE bits.
Note: Full-duplex totally transparent operation for an FCC is obtained by setting both TTX and TRX.
Attempting to operate an FCC with Ethernet or ATM on its receiver and transparent operation
on its transmitter causes erratic behavior. In other words, if GFMR[MODE] selects Ethernet
or ATM, TTX must equal TRX.
5
6
7
CDP CD pulse (transparent mode only)
0 Normal operation (envelope mode). CD should envelope the frame; to negate CD while receiving
causes a CD lost error.
1 Pulse mode. Once CD is asserted (high to low transition), synchronization has been achieved,
and further transitions of CD do not affect reception.
Note: CDP must be set if this FCC is used with the TSA in transparent mode.
CTSP CTS pulse
0 Normal operation (envelope mode). CTS should envelope the frame; to negate CTS while
1 Pulse mode. CTS is asserted when synchronization is achieved; further transitions of CTS do not
affect transmission. When running HDLC, the FCC samples CTS only once before sending the
first frame after the transmitter is enabled (ENT = 1).
CDS CD sampling
0 The CD input is assumed to be asynchronous with the data. The FCC synchronizes it internally
before data is received. (This mode is not allowed in transparent mode when SYNL = 0b00.)
1 The CD input is assumed to be synchronous with the data, giving faster operation. In this mode,
CD must transition while the receive clock is in the low state. When CD goes low, data is received.
This is useful when connecting PowerQUICC IIs in transparent mode since it allows the RTS
signal of one PowerQUICC II to be connected directly to the CD signal of another PowerQUICC II.
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Fast Communications Controllers (FCCs)
Table 29-2. GFMR Register Field Descriptions (continued)
Description
Bits
Name
8
CTSS CTS sampling
0 The CTS input is assumed to be asynchronous with the data. When it is internally synchronized
by the FCC, data is sent after a delay of no more than two serial clocks.
1 The CTS input is assumed to be synchronous with the data, giving faster operation. In this mode,
CTS must transition while the transmit clock is in the low state. As soon as CTS is low, data
transmission begins. This mode is useful when connecting PowerQUICC II in transparent mode
because it allows the RTS signal of one PowerQUICC II to be connected directly to the CTS
signal of another PowerQUICC II.
9--15
—
Reserved, should be 0.
16–17 SYNL Sync length (transparent mode only). Determines the operation of an FCC receiver configured for
00 The sync pattern in the FDSR is not used. An external sync signal is used instead (CD signal
asserted: high to low transition).
01 Automatic sync (assumes always synchronized, ignores CD signal).
10 8-bit sync. The receiver synchronizes on an 8-bit sync pattern stored in the FDSR. Negation of
CD causes CD lost error.
11 16-bit sync. The receiver synchronizes on a 16-bit sync pattern stored in the FDSR. Negation of
CD causes CD lost error.
Note: If SYNL = 1x, CDP should be cleared (not in CD pulse mode).
18
RTSM RTS mode
0 Send idles between frames as defined by the protocol. RTS is negated between frames (default).
1 Send flags/syncs between frames according to the protocol. RTS is asserted whenever the FCC
is enabled.
19–20 RENC Receiver decoding method. The user should set RENC = TENC in most applications.
00 NRZ
01 NRZI (one bit mode HDLC or transparent only)
1x Reserved
21
REVD Reverse data (valid for a totally transparent channel only)
0 Normal operation
1 The totally transparent channels on this FCC (either the receiver, transmitter, or both, as defined
by TTX and TRX) reverse bit order, transmitting the MSB of each octet first.
22–23 TENC Transmitter encoding method. The user should set TENC = RENC in most applications.
00 NRZ
01 NRZI (one bit mode HDLC or transparent only)
1x Reserved
24-25 TCRC Transparent CRC (totally transparent channel only). Selects the type of frame checking provided on
the transparent channels of the FCC (either the receiver, transmitter, or both, as defined by TTX and
TRX). This configuration selects a frame check type; the decision to send the frame check is made
in the TxBD. Thus, it is not required to send a frame check in transparent mode. If a frame check is
not used, the user can ignore any frame check errors generated on the receiver.
00 16-bit CCITT CRC (HDLC). (X16 + X12 + X5 + 1)
01 Reserved
10 32-bit CCITT CRC (Ethernet and HDLC) (X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 +
X8 + X7 + X5 + X4 + X2 + X1 +1)
11 Reserved
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Fast Communications Controllers (FCCs)
Table 29-2. GFMR Register Field Descriptions (continued)
Description
Bits
Name
26
ENR Enable receive. Enables the receiver hardware state machine for this FCC.
0 The receiver is disabled and any data in the receive FIFO buffer is lost. If ENR is cleared during
reception, the receiver aborts the current character.
1 The receiver is enabled.
ENR may be set or cleared regardless of whether serial clocks are present. Describes how to
disable and reenable an FCC. Note that the FCC provides other tools for controlling reception—the
ENTER HUNT MODE command, CLOSE RXBD command, and RxBD[E].
27
ENT Enable transmit. Enables the transmitter hardware state machine for this FCC.
0 The transmitter is disabled. If ENT is cleared during transmission, the transmitter aborts the
current character and TXD returns to idle state. Data in the transmit shift register is not sent.
1 The transmitter is enabled.
ENT can be set or cleared, regardless of whether serial clocks are present. See Section 29.12,
“Disabling the FCCs On-the-Fly,” for a description of the proper methods to disable and reenable an
FCC. Note that the FCC provides other tools for controlling transmission besides the ENT bit—the
STOP TRANSMIT, GRACEFUL STOP TRANSMIT, and RESTART TRANSMIT commands, CTS flow control, and
TxBD[R].
28–31 MODE Channel protocol mode
0000 HDLC
0001 Reserved for RAM microcode
0010 Reserved
0011 Reserved for RAM microcode
0100 Reserved
0101 Reserved for RAM microcode
0110 Reserved
0111 Reserved for RAM microcode
1000 Reserved
1001 Reserved for RAM microcode
1010 ATM
1011 Reserved for RAM microcode
1100 Ethernet
11xx Reserved
NOTE
In addition to selecting the correct mode of operation in GFMRx[MODE],
the user must issue the appropriate CP command and choose the correct
protocol in CPCR (refer to Section 14.4.1, “CP Command Register
29.3 FCC Protocol-Specific Mode Registers (FPSMRx)
The functionality of the FCC varies according to the protocol selected by GFMR[MODE]. Each FCC has
an additional 32-bit, memory-mapped, read/write protocol-specific mode register (FPSMR) that
configures them specifically for a chosen mode. The section for each specific protocol describes the
FPSMR bits.
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Fast Communications Controllers (FCCs)
29.4 FCC Data Synchronization Registers (FDSRx)
Each FCC has a 16-bit, memory-mapped, read/write data synchronization register (FDSR) that specifies
the pattern used in the frame synchronization procedure of the synchronous protocols. In the totally
transparent protocol, the FDSR should be programmed with the preferred SYNC pattern. For Ethernet
protocol, it should be programmed with 0xD555. For the ATM protocol, FSDRx is used to generate a
constant byte for the HEC. It does not generate the HEC; instead it only outputs this constant byte as a
‘placeholder’ for the HEC. This byte is then replaced by the ATM PHY with the actual value.
At reset, FDSRx defaults to 0x7E7E (two HDLC flags), so it does not need to be written for HDLC mode.
The FDSR contents are always sent lsb first.
0
7
8
15
Field
Reset
R/W
SYN2
SYN1
0
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
R/W
Figure 29-3. FCC Data Synchronization Register (FDSR)
Addr
29.5 FCC Transmit-on-Demand Registers (FTODRx)
If no frame is being sent by the FCC, the CP periodically polls the R bit of the next TxBD to see if the user
has requested a new frame/buffer to be sent. Polling occurs every 256 serial transmit clocks. The polling
algorithm depends on the FCC configuration, as shown in the following equations:
Fast Ethernet:
10BaseT:
256 clocks / 25 MHz = 10 µs
256 clocks / 2.5 MHz = 100 µs
The user, however, can request that the CP begin processing the new frame/buffer without waiting the
normal polling time. For immediate processing, after setting TxBD[R], set the transmit-on-demand (TOD)
bit in the transmit-on-demand register (FTODR) twice to activate. If TOD is set only once, the new
frame/buffer will not be transmitted until the next periodic polling request.
This feature, which decreases the transmission latency of the transmit buffer/frame, is particularly useful
in LAN-type protocols where maximum interframe GAP times are limited by the protocol specification.
Since the transmit-on-demand feature gives a high priority to the specified TxBD, it can conceivably affect
the servicing of the other FCC FIFO buffers. Therefore, it is recommended that the transmit-on-demand
feature be used only for a high-priority TxBD and when transmission on this FCC has not occurred for a
given time period, which is protocol-dependent.
If a new TxBD is added to the BD table while preceding TxBDs have not completed transmission, the new
TxBD is processed immediately after the older TxBDs are sent.
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0
1
15
Field TOD
—
0000_0000_0000_0000
R/W
Reset
R/W
Addr
Figure 29-4. FCC Transmit-on-Demand Register (FTODR)
Fields in the FTODR are described in Table 29-3.
.
Table 29-3. FTODR Field Descriptions
Field Name
Description
0
TOD Transmit on demand
0 Normal polling.
1 The CP gives high priority to the current TxBD and begins sending the frame does without waiting
for the normal polling time to check TxBD[R]. TOD is cleared automatically.
1–15
—
Reserved, should be cleared.
29.6 FCC Buffer Descriptors
Data associated with each FCC is stored in buffers. Each buffer is referenced by a buffer descriptor (BD).
All of the transmit BDs for an FCC are grouped into a TxBD circular table with a programmable length.
Likewise, receive BDs form an RxBD table. The user can program the start address of the BD tables
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Fast Communications Controllers (FCCs)
Dual-Port RAM
System Memory
Tx Buffer Descriptors
Status and Control
Data Length
FCCx TxBD
Table
Buffer Pointer
FCCx RxBD
Table Pointer
(RBASE)
Tx Buffer
FCCx TxBD
Table Pointer
(TBASE)
Rx Buffer Descriptors
FCCx RxBD
Table
Status and Control
Data Length
Buffer Pointer
Rx Buffer
Figure 29-5. FCC Memory Structure
operation except ATM mode; see Section 30.10.5, “ATM Controller Buffer Descriptors (BDs).” The first
16 bits in each BD contain status and control information, which differs for each protocol. The second 16
bits indicate the data buffer length in bytes (the wrap bit is the BD table length indicator). The remaining
32-bits contain the 32-bit address pointer to the actual buffer in memory.
0
15
Offset + 0
Offset + 2
Offset + 4
Offset + 6
Status and Control
Data Length
High-Order Data Buffer Pointer
Low-Order Data Buffer Pointer
Figure 29-6. Buffer Descriptor Format
For frame-based protocols, a message can reside in as many buffers as necessary (transmit or receive).
Each buffer has a maximum length of (64K–1) bytes. The CP does not assume that all buffers of a single
frame are currently linked to the BD table. It does assume, however, that unlinked buffers are provided by
the core soon enough to be sent or received. Failure to do so causes an error condition being reported by
the CP. An underrun error is reported in the case of transmit; a busy error is reported in the case of receive.
Because BDs are prefetched, the receive BD table must always contain at least one empty BD to avoid a
busy error; therefore, RxBD tables must always have at least two BDs.
The BDs and data buffers can be anywhere in the system memory.
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The CP processes the TxBDs in a straightforward fashion. Once the transmit side of an FCC is enabled, it
starts with the first BD in that FCC’s TxBD table. When the CP detects that TxBD[R] is set, it begins
processing the buffer. The CP detects that the BD is ready either by polling the R bit periodically or by the
user writing to the FTODR. When the data from the BD has been placed in the transmit FIFO buffer, the
CP moves on to the next BD, again waiting for the R bit to be set. Thus, the CP does no look-ahead BD
processing, nor does it skip over BDs that are not ready. When the CP sees the wrap (W) bit set in a BD,
it goes back to the beginning of the BD table after processing of the BD is complete.
After using a BD, the CP normally clears R (not-ready); thus, the CP does not use a BD again until the BD
has been prepared by the core. Some protocols support continuous mode, which allows repeated
transmission and for which the R bit remains set (always ready).
The CP uses RxBDs in a similar fashion. Once the receive side of an FCC is enabled, it starts with the first
BD in the FCC’s RxBD table. Once data arrives from the serial line into the FCC, the CP performs the
required protocol processing on the data and moves the resultant data to the buffer pointed to by the first
BD. Use of a BD is complete when no room is left in the buffer or when certain events occur, such as the
detection of an error or end-of-frame. Regardless of the reason, the buffer is then said to be closed and
additional data is stored using the next BD. Whenever the CP needs to begin using a BD because new data
is arriving, it checks the E bit of that BD. This check is made on a prefetched copy of the current BD. If
the current BD is not empty, it reports a busy error. However, it does not move from the current BD until
it is empty. Because there is a periodic prefetch of the RxBD, the busy error may recur if the BD is not
prepared soon enough.
When the CP sees the W bit set in a BD, it returns to the beginning of the BD table after processing of the
BD is complete. After using a BD, the CP clears the E bit (not empty) and does not use a BD again until
the BD has been processed by the core. However, in continuous mode, available to some protocols, the E
bit remains set (always empty).
29.7 FCC Parameter RAM
Each FCC parameter RAM area begins at the same offset from each FCC base area. The protocol-specific
portions of the FCC parameter RAM are discussed in the specific protocol descriptions. Table 29-4. shows
portions common to all FCC protocols.
Some parameter RAM values must be initialized before the FCC is enabled; other values are
initialized/written by the CP. Once initialized, most parameter RAM values do not need to be accessed by
user software because most activity centers around the TxBDs and RxBDs rather than the parameter RAM.
However, if the parameter RAM is accessed, note the following:
•
•
Parameter RAM can be read at any time.
Tx parameter RAM can be written only when the transmitter is disabled—after a STOP TRANSMIT
command and before a RESTART TRANSMIT command or after the buffer/frame finishes
transmitting after a GRACEFUL STOP TRANSMIT command and before a RESTART TRANSMIT
command.
•
Rx parameter RAM can be written only when the receiver is disabled. Note the CLOSE RXBD
command does not stop reception, but it does allow the user to extract data from a partially full Rx
buffer.
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•
experienced users and for debugging. The user need not access these parameters in normal operation.
Table 29-4. FCC Parameter RAM Common to All Protocols except ATM
1
Offset
Name
Width
Description
0x00
RIPTR Hword Receive internal temporary data pointer. Used by microcode as a temporary buffer for
data. Must be 32-byte aligned and the size of the internal buffer must be 32 bytes unless
it is stated otherwise in the protocol specification. For best performance, it should be
located in the following address ranges: 0x3000–0x4000 or 0xB000–0xC000.
0x02
TIPTR Hword Transmit internal temporary data pointer. Used by microcode as a temporary buffer for
data. Must be 32-byte aligned and the size of the internal buffer must be 32 bytes unless
it is stated otherwise in the protocol specification. For best performance it should be
located in the following address ranges: 0x3000–0x4000 or 0xB000–0xC000.
0x04
0x06
—
Hword Reserved, should be cleared.
MRBLR Hword Maximum receive buffer length (a multiple of 32 for all modes). The number of bytes that
the FCC receiver writes to a receive buffer before moving to the next buffer. The receiver
can write fewer bytes to the buffer than MRBLR if a condition such as an error or
end-of-frame occurs, but it never exceeds the MRBLR value. Therefore, user-supplied
buffers should be at least as large as the MRBLR.
Note that FCC transmit buffers can have varying lengths by programming TxBD[Data
Length], as needed, and are not affected by the value in MRBLR.
MRBLR is not intended to be changed dynamically while an FCC is operating. Change
MRBLR only when the FCC receiver is disabled.
0x08
0x0C
RSTATE Word Receive internal state. The high byte, RSTATE[0–7], contains the function code register;
the CP and must be cleared initially.
RBASE Word RxBD base address (must be divisible by eight). Defines the starting location in the
memory map for the FCC RxBDs. This provides great flexibility in how FCC RxBDs are
partitioned. By selecting RBASE entries for all FCCs and by setting the W bit in the last
BD in each BD table, the user can select how many BDs to allocate for the receive side
of every FCC. The user must initialize RBASE before enabling the corresponding
channel. Furthermore, the user should not configure BD tables of two enabled FCCs to
overlap or erratic operation occurs.
0x10 RBDSTA Hword RxBD status and control. Reserved for CP use only.
T
0x12 RBDLEN Hword RxBD data length. A down-count value initialized by the CP with MRBLR and
decremented with every byte written by the SDMA channels.
0x14
RDPTR Word RxBD data pointer. Updated by the SDMA channels to show the next address in the buffer
to be accessed.
0x18
TSTATE Word Tx internal state. The high byte, TSTATE[0–7], contains the function code register; see
and must be cleared initially.
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Table 29-4. FCC Parameter RAM Common to All Protocols except ATM (continued)
1
Offset
Name
Width
Description
0x1C
TBASE Word TxBD base address (must be divisible by eight). Defines the starting location in the
memory map for the FCC TxBDs. This provides great flexibility in how FCC TxBDs are
partitioned. By selecting TBASE entries for all FCCs and by setting the W bit in the last
BD in each BD table, the user can select how many BDs to allocate for the transmit side
of every FCC. The user must initialize TBASE before enabling the corresponding channel.
Furthermore, the user should not configure BD tables of two enabled FCCs to overlap or
erratic operation occurs.
0x20 TBDSTAT Hword TxBD status and control. Reserved for CP use only.
0x22 TBDLEN Hword TxBD data length. A down-count value initialized with the TxBD data length and
decremented with every byte read by the SDMA channels.
0x24
TDPTR Word TxBD data pointer. Updated by the SDMA channels to show the next address in the buffer
to be accessed.
0x28
RBPTR Word RxBD pointer. Points to the next BD that the receiver transfers data to when it is in idle
state or to the current BD during frame processing. After a reset or when the end of the
BD table is reached, the CP sets RBPTR = RBASE. Although the user need never write
to RBPTR in most applications, the user can modify it when the receiver is disabled or
when no receive buffer is in use.
0x2C
TBPTR
Word TxBD pointer. Points either to the next BD that the transmitter transfers data from when it
is in idle state or to the current BD during frame transmission. After a reset or when the
end of the BD table is reached, the CP sets TBPTR = TBASE. Although the user need
never write to TBPTR in most applications, the user can modify it when the transmitter is
disabled or when no transmit buffer is in use (after a STOP TRANSMIT or GRACEFUL STOP
TRANSMIT command is issued and the frame completes transmission).
0x30
0x34
0x38
0x3C
RCRC
—
Word Temporary receive CRC
Word Reserved
TCRC
—
Word Temporary transmit CRC
Word First word of protocol-specific area
1
Offset from FCC base: 0x8400 (FCC1), 0x8500 (FCC2) and 0x8600 (FCC3); see Section 14.5.2, “Parameter RAM.”
29.7.1 FCC Function Code Registers (FCRx)
The function code registers contain the transaction specification associated with SDMA channel accesses
to external memory. Figure 29-7 shows the format of the transmit and receive function code registers,
0
1
2
3
4
5
6
7
Field
—
FCCP
GBL
BO
TC2
DTB
BDB
Figure 29-7. Function Code Register (FCRx)
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Table 29-5. FCRx Field Descriptions
Description
Bits
Name
0
1
—
Reserved, should be cleared.
FCCP FCC priority. Used in conjunction with PPC_ACR[PRKM] (see section 4.3.2.2) and
LCL_ACR[PRKM] (see section 4.3.2.4) for a low request level.
0
1
Disables CPM low request level to refer to FCCs and MCCs.
Enables CPM low request level to refer to FCCs and MCCs.
2
GBL Global. Indicates whether the memory operation should be snooped.
0 Snooping disabled.
1 Snooping enabled.
3–4
BO
Byte ordering. Used to select the byte ordering of the buffer. If BO is modified on-the-fly, it takes
effect at the start of the next frame (Ethernet, HDLC, and transparent) or at the beginning of the next
BD.
01 Munged little-endian byte ordering. As data is sent onto the serial line from the data buffer, the
LSB of the buffer double-word contains data to be sent earlier than the MSB of the same buffer
double-word.
10 Freescale byte ordering (normal operation). It is also called big-endian byte ordering. As data is
sent onto the serial line from the data buffer, the MSB of the buffer word contains data to be sent
earlier than the LSB of the same buffer word.
5
6
TC2 Transfer code. Contains the transfer code value of TC[2], used during this SDMA channel memory
access. TC[0–1] is driven with a 0b11 to identify this SDMA channel access as a DMA-type access.
DTB Indicates on what bus the data is located.
0
On the 60x bus.
1
On the local.
7
BDB Indicates on what bus the BDs are located.
0
1
On the 60x bus.
On the local bus.
29.8 Interrupts from the FCCs
Interrupt handling for each of the FCC channels is configured on a global (per channel) basis in the
interrupt pending register (SIPNR_L) and interrupt mask register (SIMR_L). One bit in each register is
used to either mask, enable, or report an interrupt in an FCC channel. The interrupt priority between the
FCCs is programmable in the CPM interrupt priority register (SCPRR_H). The interrupt vector register
(SIVEC) indicates which pending channel has highest priority. Registers within the FCCs manage
interrupt handling for FCC-specific events.
Events that can cause the FCC to interrupt the processor vary slightly among protocols and are described
with each protocol. These events are handled independently for each channel by the FCC event and mask
registers (FCCE and FCCM).
29.8.1 FCC Event Registers (FCCEx)
Each FCC has an FCC event register (FCCE) used to report events. On recognition of an event, the FCC
sets its corresponding FCCE bit regardless of the corresponding mask bit. To the user it appears as a
memory-mapped register that can be read at any time. Bits are cleared by writing ones; writing zeros has
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no effect on bit values. FCCE is cleared at reset. Fields of this register are protocol-dependent and are
described in the respective protocol sections.
29.8.2 FCC Mask Registers (FCCMx)
Each FCC has a read/write FCC mask register (FCCM) used to enable or disable CP interrupts to the core
for events reported in an event register (FCCE). Bit positions in FCCM are identical to those in FCCE.
Note that an interrupt is generated only if the FCC interrupts are also enabled in the SIU; see
If an FCCM bit is zero, the CP does not proceed with its usual interrupt handling whenever that event
occurs. Any time a bit in the FCCM register is set, a 1 in the corresponding bit in the FCCE register sets
the FCC event bit in the interrupt pending register; see Section 4.3.1.4, “SIU Interrupt Pending Registers
29.8.3 FCC Status Registers (FCCSx)
Each FCC has an 8-bit, read/write FCC status register (FCCS) that lets the user monitor real-time status
conditions (flags, idle) on the RXD line. It does not show the status of CTS and CD; their real-time status
29.9 FCC Initialization
The FCCs require a number of registers and parameters to be configured after a power-on reset. The
following outline gives the proper sequence for initializing the FCCs, regardless of the protocol used.
1. Write the parallel I/O ports to configure and connect the I/O pins to the FCCs.
2. Write the appropriate port registers to configure CTS and CD to be parallel I/O with interrupt
capability or to connect directly to the FCC (if modem support is needed).
3. If the TSA is used, the SI must be configured. If the FCC is used in the NMSI mode, the CPM
multiplexing logic (CMX) must still be initialized.
4. Write the GFMR, but do not write the ENT or ENR bits yet.
5. Write the FPSMR.
6. Write the FDSR.
7. Initialize the required values for this FCC in its parameter RAM.
8. Clear out any current events in FCCE, as needed.
9. Write the FCCM register to enable the interrupts in the FCCE register.
10. Write the SCPRR_H to configure the FCC interrupt priority.
11. Clear out any current interrupts in the SIPNR_L, if preferred.
12. Write the SIMR_L to enable interrupts to the CP interrupt controller.
13. Issue an INIT TX AND RX PARAMETERS command (with the correct protocol number).
14. Set GFMR[ENT] and GFMR[ENR].
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Fast Communications Controllers (FCCs)
The first RxBD’s empty bit must be set before the INIT RX COMMAND. However TxBDs can have their
ready bits set at any time. Notice that the CPCR does not need to be accessed after a power-on reset until
an FCC is to be used. An FCC should be disabled and reenabled after any dynamic change in its parallel
I/O ports or serial channel physical interface configuration. A full reset using CPCR[RST] is a
comprehensive reset that also can be used.
29.10 FCC Interrupt Handling
The following describes what usually occurs within an FCC interrupt handler:
1. When an interrupt occurs, read FCCE to determine interrupt sources. FCCE bits to be handled in
this interrupt handler are normally cleared at this time.
2. Process the TxBDs to reuse them if the FCCE[TX,TXE] were set. If the transmit speed is fast or
the interrupt delay is long, more than one transmit buffer may have been sent by the FCC. Thus, it
is important to check more than just one TxBD during the interrupt handler. One common practice
is to process all TxBDs in the interrupt handler until one is found with R set.
3. Extract data from the RxBD if FCCE[RX, RXB, or RXF] is set. If the receive speed is fast or the
interrupt delay is long, the FCC may have received more than one receive buffer. Thus, it is
important to check more than just one RxBD during interrupt handling. Typically, all RxBDs in the
interrupt handler are processed until one is found with E set. Because the FCC prefetches BDs, the
BD table must be big enough such that always there will be another empty BD to prefetch.
4. Clear FCCE.
5. Continue normal execution.
29.10.1 FCC Transmit Errors
There are four errors in the FCC transmitter that make it necessary for software to act on the transmitter
before correct operation can continue. The errors are as follows:
•
•
•
•
CTS-lost indication in HDLC transmitter (use re-initialization procedure)
Underrun in any of the serial FCC transmitter protocols (use re-initialization procedure)
Late collision in fast Ethernet transmitter (use recovery or re-initialization procedure)
Expiration of retry limit in fast Ethernet (use recovery or re-initialization procedure)
In addition to status bits in the current TxBD, these errors are reported via the TXE event bit in the FCCE
as a convenience for the user to implement error handling. TXE is a safe indication that a recovery or
re-initialization procedure must be started.
29.10.1.1 Re-Initialization Procedure
1. Disable the FCC transmission by clearing GFMR[ENT].
2. Remember the TBPTR value taken from the FCC parameter RAM.
3. Issue a “RESTART TX” command using the CPCR.
4. Restore the remembered TBPTR into the FCC parameter RAM.
5. Adjust TxBD handling as described in Section 28.10.1.3.
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6. Enable FCC transmission by setting GFMR[ENT].
29.10.1.2 Recovery Sequence
1. Determine which BD is to be transmitted next and, if necessary, modify BDs.
2. Modify TBPTR field in Parameter RAM to point to next BD (if necessary).
3. Issue a “RESTART TX” command using the CPCR.
29.10.1.3 Adjusting Transmitter BD Handling
When a TXE event occurs, the TBPTR may already point beyond BDs still marked as ready due to internal
pipelining. If the TBPTR is not adjusted, these BDs would be skipped while still being marked as ready.
Software must determine if these BDs should be retransmitted or if they should be skipped, depending on
the protocol and application needs. This requires the following steps:
1. From the current TBPTR value, search backwards over all (if any) BDs still marked as ready to
find the first BD that has not been closed by the CPM. The search process should stop if the BD to
be checked next is not ready or if it is the most recent BD marked as ready by the CPU transmit
software. This is to avoid an endless loop in case the CPU software fills the BD ring completely.
2. A) For skipping BDs, manually close all BDs from the BD just found up to and including the BD
just before TBPTR. Leave the TBPTR value untouched.
B) For retransmitting BDs, change the TBPTR value to point to the BD just found.
29.11 FCC Timing Control
When GFMR[DIAG] is programmed to normal operation, CD and CTS are automatically controlled by
the FCC. GFMR[TCI] is assumed to be cleared, which implies normal transmit clock operation.
RTS is asserted when FCC has data to transmit in the transmit FIFO and a falling transmit clock occurs.
At this point, the FCC begins sending the data, once the appropriate conditions occur on CTS. In all cases,
the first bit of data is the start of the opening flag, or sync pattern.
Figure 29-8 shows that the delay between RTS and data is 0 bit times, regardless of the setting of
GFMR[CTSS]. This operation assumes that CTS is either already asserted to the FCC or is reprogrammed
to be a parallel I/O line, in which case the CTS signal to the FCC is always asserted. RTS is negated one
clock after the last bit in the frame.
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Fast Communications Controllers (FCCs)
TCLK
TXD
(Output)
RTS
(Output)
First Bit of Frame Data
Last Bit of Frame Data
CTS
(Input)
Note:
1. A frame includes opening and closing flags and syncs, if present in the protocol.
Figure 29-8. Output Delay from RTS Asserted
If CTS is not already asserted when RTS is asserted, the delays to the first bit of data depend on when CTS
is asserted. Figure 29-9 shows that the delay between CTS and the data can be approximately 0.5 to 1 bit
times or no delay, depending on GFMR[CTSS].
TCLK
TXD
(Output)
RTS
(Output)
First Bit Of Frame Data
CTS Sampled Low
Last Bit of Frame Data
CTS
(Input)
Note:
1. GFMR[CTSS] = 0. CTSP is a don’t care.
TCLK
TXD
(Output)
RTS
(Output)
First Bit of Frame Data
Last Bit of Frame Data
CTS
(Input)
Note:
1. GFMR[CTSS] = 1. CTSP is a don’t care.
Figure 29-9. Output Delay from CTS Asserted
If it is programmed to envelope the data, CTS must remain asserted during frame transmission or a CTS
lost error occurs. The negation of CTS forces RTS high and the transmit data to the idle state. If
GFMR[CTSS] = 0, the FCC must sample CTS before a CTS lost is recognized. Otherwise, the negation
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TCLK
TXD
(Output)
Data Forced High
RTS Forced High
First Bit of Frame Data
RTS
(Output)
CTS
(Input)
CTS Sampled Low
CTS Sampled High
CTS Lost Signaled in BD
Note:
1. GFMR[CTSS] = 0. CTSP=0 or no CTS lost can occur.
TCLK
TXD
(Output)
Data Forced High
RTS Forced High
First Bit of Frame Data
RTS
(Output)
CTS
(Input)
CTS Lost Signaled in BD
Note:
1. GFMR[CTSS] = 1. CTSP=0 or no CTS lost can occur.
Figure 29-10. CTS Lost
NOTE
If GFMR[CTSS] = 1, all CTS transitions must occur while the transmit
clock is low.
rising receive clock edge before data is received. If GFMR[CDS] = 1, CD transitions immediately cause
data to be gated into the receiver.
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Fast Communications Controllers (FCCs)
RCLK
RXD
(Input)
CD
(Input)
First Bit of Frame Data
CD Sampled Low
Last Bit of Frame Data
CD Sampled High
Notes:
1. GFMR[CDS] = 0. CDP=0.
2. If CD is negated prior to the last bit of the receive frame, CD lost is signaled in the BD.
3. If CDP=1, CD lost cannot occur and CD negation has no effect on reception.
RCLK
RXD
(Input)
CD
(Input)
First Bit of Frame Data
Last Bit of Frame Data
CD Assertion Immediately
Gates Reception
CD Negation Immediately
Halts Reception
Notes:
1. GFMR[CDS] = 1. CDP=0.
2. If CD is negated prior to the last bit of the receive frame, CD lost is signaled in the BD.
3. If CDP=1, CD lost cannot occur and CD negation has no effect on reception.
Figure 29-11. Using CD to Control Reception
If it is programmed to envelope data, CD must remain asserted during frame transmission or a CD lost
error occurs. The negation of CD terminates reception. If [CDS] = 0, CD must be sampled by the FCC
before a CD lost is recognized. Otherwise, the negation of CD immediately causes the CD lost condition.
NOTE
If GFMR[CDS] = 1, all CD transitions must occur while the receive clock
is low.
29.12 Disabling the FCCs On-the-Fly
Unused FCCs can be temporarily disabled. In this case, a operation sequence is followed that ensures that
any buffers in use are closed properly and that new data is transferred to or from a new buffer. Such a
sequence is required if the parameters that must be changed are not allowed to be changed dynamically. If
the register or bit description states that dynamic changes are allowed, the following sequences are not
required and the register or bit may be changed immediately. In all other cases, the sequence should be
used.
Modifying parameter RAM does not require the FCC to be fully disabled. See the parameter RAM
description for when values can be changed. To disable all peripheral controllers, set CPCR[RST] to reset
the entire CPM.
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Fast Communications Controllers (FCCs)
29.12.1 FCC Transmitter Full Sequence
For the FCC transmitter, the full disable and enable sequence is as follows.
1. Issue the STOP TRANSMIT command. This is recommended if the FCC is currently transmitting data
because it stops transmission in an orderly way. If the FCC is not transmitting (no TxBDs are ready
or the GRACEFUL STOP TRANSMIT command has been issued and completed), then the STOP
TRANSMIT command is not required. Furthermore, if the TBPTR is overwritten by the user or the
INIT TX PARAMETERS command is executed, this command is not required.
2. Clear GFMR[ENT]. This disables the FCC transmitter and puts it in a reset state.
3. Make changes. The user can modify FCC transmit parameters, including the parameter RAM. To
switch protocols or restore the FCC transmit parameters to their initial state, the INIT TX
PARAMETERS command must be issued.
4. If an INIT TX PARAMETERS command was not issued in step 3, issue a RESTART TRANSMIT
command.
5. Set GFMR[ENT]. Transmission begins using the TxBD that the TBPTR points to as soon as
TxBD[R] = 1.
29.12.2 FCC Transmitter Shortcut Sequence
A shorter sequence is possible if the user prefers to reinitialize the transmit parameters to the state they had
after reset. This sequence is as follows:
1. Clear GFMR[ENT].
2. Issue the INIT TX PARAMETERS command. Any additional changes can be made now.
3. Set GFMR[ENT].
29.12.3 FCC Receiver Full Sequence
The full disable and enable sequence for the receiver is as follows:
1. Clear GFMR[ENR]. Reception is aborted immediately, which disables the receiver of the FCC and
puts it in a reset state.
2. Make changes. The user can modify the FCC receive parameters, including the parameter RAM.
If the user prefers to switch protocols or restore the FCC receive parameters to their initial state,
the INIT RX PARAMETERS command must be issued.
3. Issue the ENTER HUNT MODE command. This command is required if the INIT RX PARAMETERS
command was not issued in step 2.
4. Set GFMR[ENR]. Reception begins immediately using the RxBD that the RBPTR points to if
RxBD[E] = 1.
29.12.4 FCC Receiver Shortcut Sequence
A shorter sequence is possible if the user prefers to reinitialize the receive parameters to the state they had
after reset. This sequence is as follows:
1. Clear GFMR[ENR].
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Fast Communications Controllers (FCCs)
2. Issue the INIT RX PARAMETERS command. Any additional changes can be made now.
3. Set GFMR[ENR].
29.12.5 Switching Protocols
A user can switch the protocol that the FCC is executing (HDLC) without resetting the board or affecting
any other FCC by taking the following steps:
1. Clear GFMR[ENT] and GFMR[ENR].
2. Issue the INIT TX AND RX PARAMETERS command. This command initializes both transmit and
receive parameters. Additional changes can be made in the GFMR to change the protocol.
3. Set GFMR[ENT] and GFMR[ENR]. The FCC is enabled with the new protocol.
29.13 Saving Power
Clearing an FCC’s ENT and ENR bits minimizes its power consumption.
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Chapter 30
ATM Controller and
AAL0, AAL1, and AAL5
NOTE
The functionality described in this chapter is not available on the MPC8250.
The ATM controller provides the ATM and AAL layers of the ATM protocol using the universal test and
operations physical layer (PHY) interface for ATM (UTOPIA level II) for both master and slave modes. It
performs segmentation and reassembly (SAR) functions of AAL5, AAL1 circuit emulation service (CES),
AAL2, and AAL0, and most of the common parts of the convergence sublayer (CP-CS) of these protocols.
For each virtual channel (VC), the controller’s ATM pace control (APC) unit generates a cell transmission
rate to implement constant bit rate (CBR), variable bit rate (VBR), available bit rate (ABR), unspecified
bit rate (UBR) or UBR+ traffic. To regulate VBR traffic, the APC unit performs a continuous-state leaky
bucket algorithm. The APC unit also uses up to eight priority levels to prioritize real-time ATM channels,
such as CBR and real-time VBR, over non-real-time ATM channels such as VBR, ABR and UBR.
The ATM controller performs the ATM Forum (UNI-4.0) ABR flow control. To perform feedback rate
adaptation, it supports forward and backward resource management (RM) cell generation and ATM Forum
floating-point calculation. ABR flow control is implemented in hardware and firmware (without software
intervention) to prevent potential delays during backward RM cell processing and feedback rate
adaptation.
The PowerQUICC II supports a special mode for ATM/TDM interworking. The CPM performs automatic
data forwarding between ATM channels and the MCCs’ TDM channels without core intervention.
The PowerQUICC II ATM SAR controller applications are as follows:
•
•
•
•
•
ATM line card controllers
ATM-to-WAN interworking (frame relay, T1/E1 circuit emulation)
Residential broadband network interface units (NIU) (ATM-to-Ethernet)
High-performance ATM network interface cards (NIC)
Bridges and routers with ATM interface
30.1 Features
The ATM controller has the following features:
•
•
•
Full duplex segmentation and reassembly at 155 Mbps
UTOPIA level II master and slave modes 8/16 bit
AAL5, AAL1, AAL2, AAL0 protocols
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ATM Controller and AAL0, AAL1, and AAL5
•
•
•
•
•
•
•
•
•
•
•
Up to 255 active VCs internally, and up to 64K VCs using external memory
TM 4.0 CBR, VBR, UBR, UBR+ traffic types
VBR type 1 and 2 traffic using leaky buckets (GCRA)
TM 4.0 ABR flow control (EFCI and ER)
Idle/unassign cells screening/transmission option
External and internal rate transmit modes
Special mode for ATM-to-TDM or ATM-to-ATM data forwarding
CLP and congestion indication marking
User-defined cells up to 65 bytes
Separate TxBD and RxBD tables for each virtual channel (VC)
Special mode of global free buffer pools for dynamic and efficient memory allocation with early
packet discard (EPD) support
•
•
•
Interrupt report per channel using four priority interrupt queues
Compliant with ATMF UNI 4.0 and ITU specification
AAL5 cell format
— Reassembly
– Reassemble PDU directly to external memory
– CRC32 check
– CLP and congestion report
– CPCS_UU, CPI, and length check
– Abort message report
— Segmentation
– Segment PDU directly from external memory
– Performs PDU padding
– CRC32 generation
– Automatic last cell marking
– Automatic CPCS_UU, CPI, and length insertion
– Abort message option
•
AAL1 cell format
— Reassembly
– Reassemble PDU directly to external memory
– Support for partially filled cells (configurable on a per-VC basis)
– Sequence number check
– Sequence number protection (CRC-3 and parity) check
— Segmentation
– Segment PDU directly from external memory
– Partially filled cells support (configurable on a per-VC basis)
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ATM Controller and AAL0, AAL1, and AAL5
– Sequence number generation
– Sequence number protection (CRC-3 and even parity) generation
— Structured AAL1 cell format
– Automatic synchronization using the structured pointer during reassembly
– Structured pointer generation during segmentation
— Unstructured AAL1 cell format
– Clock recovery using external SRTS (synchronous residual time stamp) logic during
reassembly
– SRTS generation using external logic during segmentation
AAL0 format
•
— Receive
– Whole cell is put in memory
– CRC10 pass/fail indication
— Transmit
– Reads a whole cell from memory
– CRC10 insertion option
•
•
more information)
AAL2 format
Support for user-defined cells
•
— Support cells up to 65 bytes
— Extra header insert/load on a per-frame basis
— Extra header size has byte resolution
— Asymmetric cell size for send and receive
— HEC octet insertion option
•
•
PHY
— UTOPIA level II supports 8/16 bits 25/50 MHz
– Supports UTOPIA master and slave modes
– Supports cell-level handshake
– Supports multiple-PHY polling mode
ATM pace control (APC) unit
— Peak cell rate pacing on a per-VC basis
— Peak-and-sustain cell rate pacing using GCRA on a per-VC basis
— Peak-and-minimum cell rate pacing on a per-VC basis
— Up to eight priority levels
— Fully managed by CP with no host intervention
Available bit rate (ABR)
•
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ATM Controller and AAL0, AAL1, and AAL5
— Performs ATMF UNI 4.0 ABR flow control on a per-VC basis
— Automatic forward-RM, backward-RM cells generation
— Automatic feedback rate adaptation
— Support for EFCI (explicit forward congestion indication) and ER (explicit rate)
— RM cell floating-point calculations
— Fully managed by CP with no host intervention
•
•
Receive address look-up mechanism
— Two modes of address look-up are supported
– External CAM
– Address compression
OAM (operations and maintenance) cells
— OAM filtering according to PTI field and reserved VCI field
— Raw cell queues for transmission and reception
— CRC-10 generation/check
— Performance monitoring support
– Support up to 64 bidirectional block tests simultaneously
– Automatic FMC and BRC cell generation and termination
– User transmit cell count
0+1
– User transmit cell count
0
– PM cells time stamp insertion
– Block error detection code (BEDC ) generation/check
0+1
– Total receive cell
count
0+1
– Total receive cell count
0
— Specifying channel code for F5 OAM cells
ATM layer statistic gathering on a per PHY basis.
— UTOPIA receiver error cells count (Rx parity error or short/long cells error)
— Misinserted cell count
•
•
— CRC-10 error cells count (ABR flow only)
Memory management
— RxBD table per VC with option of global free buffer pool for AAL5
— TxBD table per VC
30.2 ATM Controller Overview
The following sections provide an overview of the transmitter and receiver portions of the ATM controller.
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ATM Controller and AAL0, AAL1, and AAL5
30.2.1 Transmitter Overview
Before the transmitter is enabled, the host must initialize the PowerQUICC II and create the transmit data
structure, described in Section 30.10, “ATM Memory Structure.” When data is ready for transmission, the
host arranges the BD table and writes the pointer of the first BD in the transmit connection table (TCT).
The host issues an ATM TRANSMIT command, which inserts the current channel to the ATM pace control
(APC) unit. The APC unit controls the ATM traffic of the transmitter. It reads the traffic parameters of each
channel and divides the total bandwidth among them. The APC unit can pace the peak cell rate,
peak-and-sustain cell rate (GCRA traffic) or peak-and-minimum cell rate traffic. The APC implements up
to eight priority levels for servicing real-time channels before non-real-time channels.
The transmitter ATM cell is 53–65 bytes and includes 4 bytes of ATM cell header, a 1-byte HEC, and 48
bytes of payload. The HEC is a constant taken from FDSRx[0–15] when using UTOPIA 16 and from
User-defined cells (UDC mode) include an extra header of 1–12 bytes with an optional HEC octet. Cell
transfers use the UTOPIA level II, cell-level handshake.
Transmission starts when the APC schedules a channel. According to the channel code, the ATM controller
reads the channel’s entry in the TCT and opens the first BD for transmission. In auto-VC-off mode, the
APC automatically deactivates the current channel when no buffer is ready to transmit. In this case, a new
ATM TRANSMIT command is needed for transmission of the VC to resume.
30.2.1.1 AAL5 Transmitter Overview
The transmitter reads 48 bytes from the external buffer, adds the cell header, and sends the cell through the
UTOPIA interface. The transmitter adds any padding needed and appends the AAL5 trailer in the last cell
of the AAL5 frame. The trailer consists of CPCS-UU+CPI, data length, and CRC-32 as defined in ITU
I.363. The CPCS-UU+CPI (2-byte entry) can be specified by the user or optionally cleared by the
transmitter; see Section 30.10.2.3, “Transmit Connection Table (TCT).” The transmitter identifies the last
cell of the AAL5 message by setting the last (L) indication bit in the PTI field of the cell header. An
interrupt may be generated to indicate the end of the frame.
When the transmission of the current frame ends and no additional valid buffers are in the BD table, the
transmit process ends. The transmitter keeps polling the BD table every time this channel is scheduled to
transmit. Note that a buffer-not-ready indication during frame transmission aborts the frame transfer.
30.2.1.2 AAL1 Transmitter Overview
The PowerQUICC II supports both structured and unstructured AAL1 formats. For the unstructured
format, the transmitter reads 47 bytes from the external buffer and inserts them into the AAL1 user data
field. The AAL1 PDU header, which consists of the sequence number (SN) and the sequence number
protection (SNP) (CRC-3 and parity bit), is generated and inserted into the cell. The PowerQUICC II
supports synchronous residual time stamp (SRTS) generation using external PLL. If this mode is enabled,
the PowerQUICC II reads the SRTS code from the external logic and inserts it into four outgoing cells.
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ATM Controller and AAL0, AAL1, and AAL5
For the structured format, the transmitter reads 47 or 46 bytes from the external buffer and inserts them
into the AAL1 user data field. The CP generates the AAL1 PDU header and inserts it into the cell. The
header consists of the SN, SNP, and the structured pointer.
The PowerQUICC II supports partially filled cells configured on a per-VC basis. In this mode (TCT[PFM]
= 1), only valid octets are copied from the buffer to the ATM cell; the rest of the cell is filled with padding
octets.
30.2.1.2.1
AAL1 CES Transmitter Overview
30.2.1.3 AAL0 Transmitter Overview
No specific adaptation layer is provided for AAL0. The ATM controller reads a whole cell from an external
buffer, which always contains exactly one AAL0 cell. The ATM controller optionally generates CRC10
on the cell payload and places it at the end of the payload (CRC10 field). AAL0 mode can be used to send
OAM cells or AAL3/4 raw cells.
30.2.1.4 AAL2 Transmitter Overview
30.2.1.5 Transmit External Rate and Internal Rate Modes
The ATM controller supports the following two rate modes:
•
External rate mode—The total transmission rate is determined by the PHY transmission rate. The
FCC sends cells to keep the PHY FIFOs full; the FCC inserts idle/unassign cells to maintain the
transmission rate.
•
Internal rate mode—The total transmission rate is determined by the FCC internal rate timers. In
this mode, the FCC does not insert idle/unassign cells. The internal rate mechanism supports up to
4 different rates. Each PHY has its own FTIRR, described in Section 30.13.4, “FCC Transmit
of the internal rate timer. A cell transmit request is sent when an internal rate timer expires. When
using internal rate mode, the user assigns one of the baud-rate generators (BRGs) to clock the four
internal rate timers.
30.2.2 Receiver Overview
Before the receiver is enabled, the host must initialize the PowerQUICC II and create the receive data
ATM channel. Buffers for each connection can be statically allocated (that is, each BD in the BD table is
associated with a fixed buffer location) or in the case of AAL5, can be fetched by the CP from a global
The receiver ATM cell size is 53–65 bytes. The cell includes: 4 bytes ATM cell header, 1 byte HEC, which
can be checked by setting FPSMR[HECC] (refer to Table 30-47), and 48 bytes payload. User-defined cells
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ATM Controller and AAL0, AAL1, and AAL5
(UDC mode) include an extra header of 1–12 bytes with an optional HEC octet. Cell transfers use the
UTOPIA level II, cell-level handshake.
Reception starts when the PHY asserts the receive cell available signal (RxCLAV) to indicate that the PHY
has a complete cell in its receive FIFO. The receiver reads a complete cell from the UTOPIA interface and
translates the header address (VP/VC) to a channel code by performing an address look-up. If no matches
are found, the cell is discarded and the user-network interface (UNI) statistics tables are updated. The
receiver uses the channel code to read the channel parameters from the receive connection table (RCT).
30.2.2.1 AAL5 Receiver Overview
The receiver copies the 48-byte cell payload to the external buffer and calculates CRC-32 on the entire
CPCS-PDU. When the last AAL5 cell arrives, the receiver checks the length, CRC-32, and
CPCS-UU+CPI fields and sets the corresponding RxBD status bits. An interrupt may be generated to one
of the four interrupt queues. The receiver copies the last cell to memory including the padding and the
AAL5 trailer. The CPCS-UU+CPI (16-bit entry) may be read directly from the AAL5 trailer.
The ATM controller monitors the CLP and CNG state of the incoming cells. When the message is closed,
these events set RxBD[CLP] and RxBD[CNG].
When no buffer is ready to receive cells (busy state), the receiver switches to hunt state and drops all cells
associated with the current frame (partial packet discard). The receiver tries to open new buffers for cell
reception only after the last cell of the discarded AAL5 frame arrives.
30.2.2.2 AAL1 Receiver Overview
The ATM controller supports both AAL1 structured and unstructured formats. For the unstructured format,
47 octets are copied to the current receive buffer. The AAL1 PDU header, which consists of the sequence
number (SN) and the sequence number protection (SNP) (CRC-3 and parity bit), is checked. The
PowerQUICC II supports SRTS clock recovery using an external PLL. In this mode, the PowerQUICC II
tracks the SRTS from the four incoming cells and writes the SRTS code to external logic. See
In the unstructured format, when the receive process begins, the receiver hunts for the first cell with a valid
sequence number (SN field). When one arrives, the receiver leaves the hunt state and starts receiving. If
an SN mismatch is detected, the receiver closes the RxBD, sets the sequence number error flag
(RxBD[SNE]), and switches to hunt state, where it stays until a cell with a valid SN field is received.
For the structured format, 47 or 46 octets are copied to the current receive buffer. The AAL1 PDU header,
which consists of SN and SNP, is checked and the PDU status is written to the BD.
In the structured format, when the receive process begins, the receiver hunts for the first cell with a valid
structured pointer to gain synchronization. When one arrives, the receiver leaves the hunt state and starts
receiving. Then the receiver opens a new buffer. The structured pointer points to the first octet of the
structured block, which then becomes the first byte of the new buffer. If an SN mismatch is detected, the
ATM receiver closes the current RxBD, sets RxBD[SNE], and returns to the hunt state. The receiver then
waits for a cell with a valid structured pointer to regain synchronization.
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ATM Controller and AAL0, AAL1, and AAL5
The PowerQUICC II supports partially filled cells configured on a per-VC basis. In this mode (RCT[PFM]
= 1), the ATM controller copies only the valid octets from the cell user data field to the buffer.
30.2.2.2.1
AAL1 CES Receiver Overview
30.2.2.3 AAL0 Receiver Overview
For AAL0, no specific adaptation layer processing is done. The ATM controller copies the whole cell to
an external buffer. Each buffer contains exactly one AAL0 cell. The ATM controller calculates and checks
the CRC10 of the cell payload and sets RxBD[CRE] if a CRC error occurs. AAL0 mode can be useful for
receiving OAM cells or AAL3/4 raw cells.
30.2.2.4 AAL2 Receiver Overview
30.2.3 Performance Monitoring
The ATM controller supports performance monitoring testing according to ITU I.610. When performance
monitoring is enabled, the ATM controller automatically generates and terminates FMCs (forward
monitoring cells) and BRCs (backward reporting cells). See Section 30.6.6, “Performance Monitoring.”
30.2.4 ABR Flow Control
When AAL5-ABR is enabled, the ATM controller implements the ATM Forum TM 4.0 available-bit-rate
flow. It automatically inserts forward- and backward-RM cells into the user cell stream and adjusts the
transmission rate according to the backwards RM cell feedback; see Section 30.10.2.2.2, “AAL5-ABR
30.3 ATM Pace Control (APC) Unit
The ATM pace control (APC) unit schedules the ATM channels for transmitting. While performing this
task, the APC unit uses the following parameters:
•
•
•
Frequency (bandwidth) of each ATM channel
ATM traffic pacing—Peak cell rate (PCR), sustain cell rate (SCR), and minimum rate (MCR)
Priority level—Real-time channels (CBR or VBR-RT) are scheduled at high-priority levels;
non-real-time channels (VBR-NRT, ABR, UBR) are scheduled at low-priority levels. Up to eight
priority levels are available.
30.3.1 APC Modes and ATM Service Types
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ATM Controller and AAL0, AAL1, and AAL5
Table 30-1. ATM Service Types
Cell Rate Pacing
Real-Time/
Non-Real-Time
Service Type
Relative Priority
CBR
PCR
RT
RT
1 (highest)
VBR-RT
PCR, SCR (peak-and-sustain)
PCR, SCR (peak-and-sustain)
PCR
2
VBR-NRT
NRT
NRT
NRT
NRT
3
1
ABR
4
5
UBR+
UBR
PCR, MCR (peak-and-minimum)
PCR
6 (lowest)
1
When ABR flow control is active, the CP automatically adapts the APC parameters PCR,
PCR_FRACTION. These parameters function as the channel’s allowed cell rate (ACR).
For information about cell rate pacing, see Section 30.3.5, “ATM Traffic Type.” For information about
30.3.2 APC Unit Scheduling Mechanism
The APC unit consists of an APC data structure in the dual-port RAM for each PHY and a special
scheduling algorithm performed by the CP. Each PHY’s APC data structure includes three elements: an
APC parameter table, an APC priority table, and cell transmission scheduling tables for each priority level.
Each PHY’s APC parameter table holds parameters that define the priority table location, the number of
priority levels, and other APC parameters. The priority table holds pointers that define the location and
size of each priority level’s scheduling table.
Each scheduling table is divided into time slots, as shown in Figure 30-1. The user determines the number
of ATM cells to be sent each time slot (cells per slot). After a channel is sent, it is removed from the current
time slot and advanced to a future time slot according to the channel’s assigned traffic rate (specified in
time slots). The PCR parameter in the TCT, or the SCR or MCR parameters in the TCT extension (TCTE)
determine the channel’s actual rate.
9
5
1
6
4
3
2
7
8
Number of Slots
Cell Rescheduling
Current Slot
Figure 30-1. APC Scheduling Table Mechanism
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ATM Controller and AAL0, AAL1, and AAL5
Each 2-byte time-slot entry points to one ATM channel. Additional channels scheduled to transmit in the
same slot are linked to each other using the APC linked-channel field in the TCT. The linked list is not
limited; however, if the number of channels for the current slot exceeds the cells per slot parameter (CPS),
the extra channels are sent in subsequent time slots. (The rescheduling of extra channels is based on the
original slot to maintain each channel’s pace.)
Note that a channel can appear only once in the scheduling table at a given time, because each channel has
only one APC linked-channel field.
30.3.3 Determining the Scheduling Table Size
The following sections describe how to determine the number of cells sent per time slot and the total
number of slots needed in a scheduling table.
30.3.3.1 Determining the Cells Per Slot (CPS) in a Scheduling Table
The number of cells sent per time slot is determined by the channel with the maximum bit rate; see
equation A. The maximum bit rate is achieved when a channel is rescheduled to the next slot. For example,
if the line rate is 155.52 Mbps and there are eight cells per slot, equation A yields a maximum VC rate of
19.44 Mbps.
line rate
(A)
Max bit rate =
cells per slot
Note that a channel can appear only once per time slot; thus, 19.44 Mbps = 155.52Mbps/8.
The cells per slot parameter (CPS) affects the cell delay variation (CDV). Because the APC unit does not
put cells in a definite order within each time slot (LIFO—last-in/first-out implementation), as CPS
increases, the CDV increases. However as CPS decreases, the size of the scheduling table in the dual-port
RAM increases and more CPM bandwidth is required.
30.3.3.2 Determining the Number of Slots in a Scheduling Table
The number of time slots in a scheduling table is determined by the channel with the minimum bit rate;
see equation B. The minimum bit rate is achieved when the channel reschedules only once in a whole table
scan. (The maximum schedule advance allowed is equal to number_of_slots-1.) For example, if the line
rate is 155.52 Mbps, the minimum bit rate is 32 kbps and the CPS is 4, then, according to equation B, the
number of slots should be 1,216.
NOTE
The following APC configuration is not recommended for values outside
the following ranges (PCR = peak cell rate, PCRF = peak cell rate fraction,
NOS = number of slots):
PCR = 1 and PCRF = 0
PCR = NOS - 1 and PCRF = 0
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ATM Controller and AAL0, AAL1, and AAL5
line rate
Min bit rate =
(B)
(number_of_slots - 1) × cells per slot
For the above example, 32 kbps = 155.52 Mbps/((1216-1) × 4).
Use equations (A) and (B) to obtain the maximum and minimum bit rates of a scheduling table. For
example, given a line rate = 155.52 Mbps, number_of_slots = 1025, and CPS = 8:
Max bit rate = (155.52 Mbps)/8 = 19.44 Mbps
Min bit rate = (155.52 Mbps)/(1024 × 8) = 18.98 kbps.
30.3.4 Determining the Time-Slot Scheduling Rate of a Channel
The time-slot scheduling rate of each ATM channel is defined by equation C. The resulting number of APC
slots is written in either TCT[PCR], TCTE[SCR] or TCTE[MCR], depending on the traffic type.
line rate [bps]
Rate [slots] =
(C)
VC rate [bps] × cells per slot
30.3.5 ATM Traffic Type
The APC uses the cell rate pacing parameters (PCR, SCR, and MCR) to generate CBR, VBR, ABR,
UBR+, and UBR traffic. The user determines the kind of traffic that is generated per VC by writing to
30.3.5.1 Peak Cell Rate Traffic Type
When the peak cell rate traffic type is selected, the APC schedules channels to transmit according to the
PCR and PCR_FRACTION traffic parameters. Other traffic parameters do not apply to this traffic type.
30.3.5.2 Determining the PCR Traffic Type Parameters
Suppose a VC uses 15.66 Mbps of the total 155.52 Mbps and CPS = 8. Equation C yields:
PCR [slots] = (155.52 Mbps)/(15.66 Mbps × 8) = 1.241
The resulting number of slots is written into TCT[PCR] and TCT[PCR_FRACTION]. Because
PCR_FRACTION is in units of 1/256 slots, the fraction must be converted as follows:
1.241 = 1+0.241 × 256/256 =1+ 61.79/256 ~ 1 + 62/256
PCR = 1
PCR_FRACTION = 62
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ATM Controller and AAL0, AAL1, and AAL5
30.3.5.3 Peak and Sustain Traffic Type (VBR)
Variable bit rate (VBR) traffic can burst at the peak cell rate as long as the long-term average rate does not
exceed the sustainable cell rate. To support VBR channels, the APC implements the GCRA (generic cell
rate algorithm) using three parameters—the peak cell rate (PCR), the sustained cell rate (SCR), and burst
Conforming VBR Traffic
Incoming cells fill the bucket at the peak cell rate (PCR) or at the SCR if the bucket is full.
Burst tolerance (BT)
Sustained cell rate (SCR)
Figure 30-2. VBR Pacing Using the GCRA (Leaky Bucket Algorithm)
When a VBR channel is activated, it bursts at the peak cell rate (PCR) until reaching its initial burst
tolerance (BT), which is the buffer length the network allocated for this VC. When the burst limit is
reached, the APC reduces the VC’s scheduling rate to the sustained cell rate (SCR). The VC continues
sending at SCR as long as TxBDs are ready. However, as each SCR time allotment elapses with no TxBD
ready to send, the APC grants the VC a credit for bursting at the peak cell rate (PCR). (Gaining credit
implies that the buffer at the switch is not full and can tolerate a burst transmission.) If a TxBD becomes
ready, the APC schedules the VC to burst at the PCR as long as credit remains. When the burst credit ends
(the network’s UPC leaky bucket reaches its limit), the APC schedules the VC according to SCR.
30.3.5.3.1
Example for Using VBR Traffic Parameters
Suppose the traffic parameters of a VBR channel are PCR = 6 Mbps, SCR = 2 Mbps, MBS (maximum
burst size) = 1000 cells, and CPS = 8.
Equation C (see Section 30.3.4, “Determining the Time-Slot Scheduling Rate of a Channel”) yields the
APC parameters, PCR, PCR_FRACTION, SCR, and SCR_FRACTION, which the user writes to the
channel’s TCT.
PCR [slots] = (155.52 Mbps)/(6 Mbps × 8) = 3.24
3.24 = 3 + 0.24 × 256/256 = 3 + 61.44/256 ~ 3 + 62/256
PCR = 3
PCR_FRACTION = 62
SCR [slots] = (155.52 Mbps)/(2 Mbps × 8) = 9.72
9.72 = 9 + (0.72 × 256/256) = 9 + 184.32/256 ~ 9 + 185/256
SCR = 9
SCR_FRACTION = 185
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ATM Controller and AAL0, AAL1, and AAL5
Equation D yields the number of slots the user writes to the channel’s TCT[BT].
BT [slots] = (MBS[cells] - 2) × (SCR[slots] - PCR[slots]) + SCR[slots]
= (1000 - 2) × ((9+185/256) - (3+62/256)) + (9 +185/256)
= 6477
(D)
30.3.5.3.2
Handling the Cell Loss Priority (CLP)—VBR Type 1 and 2
The PowerQUICC II supports two ways to schedule VBR traffic based on the cell loss priority (CLP).
When TCTE[VBR2] is cleared, CLP0+1 cells are scheduled by PCR or SCR according to the GCRA state.
When TCTE[VBR2] is set, CLP0 cells are still scheduled by PCR or SCR according to the GCRA state,
30.3.5.4 Peak and Minimum Cell Rate Traffic Type (UBR+)
To support UBR+ channels, the APC schedules transmission according to PCR and MCR. For each
priority level, the APC maintains a parameter that monitors the traffic load measured as the time-slot delay
between the service pointer (pointing to the current time slot waiting transmission) and a real-time slot
pointer. If the transmission delay is greater than MDA (maximum delay allowed), the APC begins
scheduling channels according to the MCR parameter. If the delay, however, drops below MDA, the APC
again schedules channels according to the PCR. Note that in order to guarantee a minimum cell rate for
UBR+ channels, there must be enough bandwidth to simultaneously send all possible channels at the
30.3.6 Determining the Priority of an ATM Channel
The priority mechanism is implemented by adding priority table levels, which point to separate scheduling
tables; see Section 30.10.4, “APC Data Structure.” The APC flow control services the APC_LEVEL1 slots
first. If there are no cells to send, the APC goes to the next priority level. The APC has up to eight priority
levels with APC_LEVEL8 being the lowest. The user specifies the priority of an ATM channel when
The real-time channels, CBR and VBR-RT, should be inserted in APC_LEVEL1; non-real-time channels,
VBR-NRT, ABR, and UBR should be inserted in lower priority levels.
30.4 VCI/VPI Address Lookup Mechanism
The PowerQUICC II supports two ways to look up addresses for incoming cells:
•
•
External CAM lookup
Address compression
Writing to GMODE[ALM] (address-lookup-mechanism bit) in the parameter RAM selects the
mechanism. Both mechanisms are described in the following sections.
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ATM Controller and AAL0, AAL1, and AAL5
30.4.1 External CAM Lookup
An external CAM is usually used when the range of VCI/VPI values varies widely or is unknown. Clearing
GMODE[ALM] selects the external CAM address lookup mechanism. If there is no match in the external
CAM, the cell is considered a misinserted cell. The external CAM can point to internal or external channels
(channels whose connection table resides in external memory). The CAM input, shown in Figure 30-3, is
the 32-bit cell address: PHY address, GFC + VPI, and VCI.
NOTE
The bus atomicity mechanism for CAM accesses may not function correctly
when the CPM performs a DMA access to an external CAM device. This
only impacts systems in which multiple CPMs will access the CAM.
0
3
4
15 16
31
PHY Addr
(MPHY)
GFC + VPI
VCI
Figure 30-3. External CAM Data Input Fields
The output of the CAM, shown in Figure 30-4, is a 32-bit entry (16-bit channel code and a match-status
bit).
0
1
15 16
31
MS
—
Channel Code
Figure 30-4. External CAM Output Fields
Table 30-2. External CAM Input and Output Field Descriptions
Description
PHY Addr In multiple PHY mode, this field contains the 4 least-significant bits of the current channel’s physical
Field
address. Because this CAM comparison field is limited to 4 bits, two CAM devices are needed if using
more than 16 PHYs.The msb of the PHY address (bit 4) selects between the two devices. If the msb is
zero, the CP accesses the CAM whose address is written in the EXT_CAM_BASE parameter in the
parameter RAM; if the msb is set, the CP uses EXT_CAM1_BASE. See Section 16.4.1, “CMX UTOPIA
In single PHY mode, clear this field.
GFC+VPI, The GFC, VPI, and VCI of the current channel.
VCI
Ch Code Pointer to internal or external connection table.
—
Reserved, should be cleared.
MS
Match status.
0 Match was found.
1 Match was not found.
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ATM Controller and AAL0, AAL1, and AAL5
30.4.2 Address Compression
The address compression mechanism uses two levels of address translation to help minimize the memory
space needed to cover the available address range. The first level of translation (VP-level) uses a look-up
table based on the 4-bit PHY address and the 12-bit virtual path identifier; the second level (VC-level) uses
the 16-bit virtual channel identifier. If there is no match during address compression, the cell is considered
a misinserted cell.
During the VP-level translation, VP_MASK in the ATM parameter RAM compresses an incoming cell’s
PHY address and VPI to create an index into the VP-level table. The VP-level table entry consists of
another mask (VC_MASK) and a pointer to one of the VC-level tables (VCOFFSET). Note that the VP
table should reside in the dual-port RAM.
In the VC-level translation, the VCI is compressed with the VC_MASK to generate a pointer to the
VC-level table entry containing the received cell’s channel code. The VC table should reside in external
memory.
Figure 30-5 shows an example of address compression.
4 bit
12 bit
VPI
VP-level addressing table
(in dual-port RAM recommended)
PHY Addr
31
0
VPT_BASE
VP_MASK
32-bit entries
0000
0000
00011111
0b00011
16 bit
16 bit
VPpointer
VC_MASK
VCOFFSET
VC-level addressing tables
(in external memory)
16 bit
VCI
32-bit entries
VCT_BASE
00000111 11110000
VCpointer
15 bit
—
16 bit
1 bit
MS
0
Ch Code[15–0]
31
Figure 30-5. Address Compression Mechanism
Figure 30-5 shows VP_MASK selecting five VPI bits to index the VP-level table. The VP-level table entry
contains the 16-bit mask (VC_MASK) and the VC-level table offset (VCOFFSET) for the next level of
address mapping. The VC_MASK selects VCI bits 4–10, which is used with VCT_BASE and VCOFFSET
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ATM Controller and AAL0, AAL1, and AAL5
to indicate the received cell’s channel code. Address compression field descriptions are shown in
Table 30-3. Field Descriptions for Address Compression
Field
Description
PHY
Addr
In multiple PHY mode, this field contains the 4 least-significant bits of the current channel’s physical
address. Because this comparison field is limited to 4 bits, two sets of look-up tables are needed if using
more than 16 PHYs.The msb of the PHY address (bit 4) selects between the two sets of tables. If the msb
is zero, the CP accesses the tables at VPT_BASE and VCT_BASE; if the msb is set, the CP uses
In single PHY mode, clear this field.
VCI, VPI The VCI and VPI of the current channel.
Ch Code Pointer to internal or external connection table.
—
Reserved, should be cleared.
MS
Match status.
0 Match was found.
1 Match was not found.
30.4.2.1 VP-Level Address Compression Table (VPLT)
The size of the VP-level table depends on the number of mask bits in VP_MASK. For example, if only
one PHY is available (PHY address = 0) and VPMASK = 0b11_1111_1111, VP pointer contains ten bits
and the table is 4 Kbytes. Because each VPLT entry is 4 bytes, the address of an entry is VPT_BASE + VP
pointer × 4.
Each VPLT entry has two parameters:
•
•
VC_MASK—A 16-bit VC-level mask for masking the incoming cell’s VCI
VCOFFSET—A 16-bit VC-level table offset from VC_BASE that points to the appropriate
VC-level table’s (VCLT) starting address. The address of the VCLT is VC_BASE + VCOFFSET
× 4.
If the VCLTs are to be placed contiguously in memory, each table’s VCOFFSET depends on the
size of preceding tables. Each table’s size depends on the number of ones in VC_MASK.
Figure 30-6 gives the general formula for determining VCOFFSET.
(number of ones in VC_MASKn)
General formula: VCOFFSET
= VCOFFSET + 2
(n+1)
n
Figure 30-6. General VCOFFSET Formula for Contiguous VCLTs
Table 30-4 shows example VCOFFSET calculations for a VP-level table with four entries.
Table 30-4. VCOFFSET Calculation Examples for Contiguous VCLTs
VP-Level
Table Entry
Number of Ones
in VC_MASK
VC-Level
Table Size
VC_MASK
VCOFFSET
6
0
1
0x0237
0x0230
6
3
2 = 64 entries
0
3
2 = 8 entries
64
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ATM Controller and AAL0, AAL1, and AAL5
Table 30-4. VCOFFSET Calculation Examples for Contiguous VCLTs
VP-Level
Table Entry
Number of Ones
in VC_MASK
VC-Level
Table Size
VC_MASK
VCOFFSET
5
2
3
0xA007
x
5
x
2 = 32 entries
x
64 + 8 = 72
72 + 32 = 104
The PowerQUICC II can check that all unallocated bits of the PHY + VPI are 0 by setting
GMODE[CUAB] (check unallocated bits) in the parameter RAM. If they are not, the cell is considered a
misinserted cell.
Table 30-5 gives an example of VP-level table entry address calculation.
Table 30-5. VP-Level Table Entry Address Calculation Example
VPT_BASE VP-Level Table Size VP_MASK
0x0024_0000 64 entries 0x0237
Phy+VPI
VP Pointer
VP Entry Address
0x0011
0x09
VP Base = 0x240000
0x09 x 4 = 0x000024
0x240024
PHY+VPI
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
1
0
0
0
1
0
1
1
1
VP_MASK
VP Pointer
0
0
1
0
0
1
Figure 30-7. VP Pointer Address Compression
30.4.2.2 VC-Level Address Compression Tables (VCLTs)
Each VPLT entry points to a single VCLT. Like the VPLT, the size of each VCLT depends on VC_MASK.
Because the VCLT contains word entries, if VC_MASK = 0b11_1111_1111, the table is 4 Kbytes. The
address of an entry in this table is VCT_BASE + VCOFFSET × 4 + VCpointer × 4.
The PowerQUICC II can check that all unallocated VCI bits are 0 by setting GMODE[CUAB] (check
unallocated bits). If they are not, the cell is considered a misinserted cell.
An example of VC-level table entry address calculation is shown in Table 30-6. Note that VCOFFSET is
assumed to be 0x100 for this example.
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ATM Controller and AAL0, AAL1, and AAL5
Table 30-6. VC-Level Table Entry Address Calculation Example
VCT_BASE
VCOffset
VC-Level Table Size VC_MASK
32 entries 0x0037
VCI
VC Pointer
VC Entry Address
0x0084_0000
0x0100
0x0031
0x19
VC Base = 0x840000
0x100 x 4 = 0x000400
0x19 x 4 = 0x000064
0x840464
VCI
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
1
0
1
1
1
VC_MASK
VC Pointer
1
1
0
0
1
Figure 30-8. VC Pointer Address Compression
30.4.3 Misinserted Cells
If the address lookup mechanism cannot find a match (MS=1), the cell is discarded and ATM layer
30.4.4 Receive Raw Cell Queue
Channel one in the RCT is reserved as a raw cell queue. The user should program channel one to operate
in AAL0 protocol. The receive raw cell queue is used for removing management cells from the regular cell
flow to the host. When a management cell is sent to the receive raw cell queue, the CP sets RxBD[OAM].
The ALL0 BD specifies the channel code associated with the current OAM cell.
The following are optionally removed from the regular flow and sent to the raw cell queue:
•
•
•
Segment F5 OAM (PTI = 0b100). To enable F5 segment filtering, set RCT[SEGF].
End-to-end F5 OAM (PTI = 0b101). To enable F5 end-to-end filtering, set RCT[ENDF].
RM cells (PTI = 0b110). When ABR flow is enabled the cells are terminated internally; otherwise,
they are sent to the raw cell queue.
•
•
Reserved PTI value (PTI = 0b111). Always sent to the raw cell queue.
VCI value: 3, 4, 6, 7–15. To enable VCI filtering set the associated bit in the VCIF entry in the
parameter RAM.
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ATM Controller and AAL0, AAL1, and AAL5
Check
address
No
Discard
cell
Match
Yes
No
PTI=1xx or
VCI=3,4,6,7-15
and filter enable
Send cell to VC
queue
Yes
Send cell to raw
cell queue
Figure 30-9. ATM Address Recognition Flowchart
NOTE
Even reserved VCI channels should appear in the CAM or address
compression tables; otherwise, a cell on a reserved channel will be
considered misinserted.
30.5 Available Bit Rate (ABR) Flow Control
While CBR service provides a fixed bandwidth and is useful for real-time applications with strictly
bounded end-to-end cell transfer delay and cell-delay variation, ABR service is intended for data
applications that can adapt to time-varying bandwidth and can tolerate significant cell transfer delay and
cell delay variation. The PowerQUICC II implements the two following mechanisms defined by the ATM
Forum TM 4.0 rate-based flow control.
•
•
Explicit forward congestion indication (EFCI). The network supplies binary indication of whether
congestion occurred along the connection path. This information is carried in the PTI field of the
ATM cell header (similar to that used in frame relay). The source initially clears each ATM cell’s
EFCI bit, but as the cell passes through the connection, any congested node can set it. The
PowerQUICC II detects this indication and sets the congestion indication (CI) bit in the next
backwards RM cell to signal the source end station to reduce its transmission rate.
Explicit rate (ER) feedback. The network carries explicit bandwidth information, to allow the
source to adjust its rate. The source sends forward RM cells specifying its chosen transmit rate
(source ER). A congested switch along the network may decrease ER to the exact rate it can
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ATM Controller and AAL0, AAL1, and AAL5
support. The destination receives forward RM cells and returns them to the source as backward RM
cells. The PowerQUICC II implements source behavior by adjusting the rate according to each
returning backward RM cell’s ER.
Explicit rate feedback has several advantages over binary feedback (EFCI). Explicit rate feedback allows
immediate source rate adaptation, eliminating rate oscillation caused by incremental rate changes. Using
the information in RM cells, the network can allocate bandwidth evenly among active ABR channels.
30.5.1 The ABR Model
Figure 30-10 shows the PowerQUICC II’s ABR model.
Source Behavior
Destination Behavior
Nrm Data Cells
Turn-around
F-RM Cell
F-RM Cell
CCR,ER
B-RM Cell
B-RM Cell
Set CI, NI
Reduce ER
Update Rate
ER, CI, NI
Figure 30-10. PowerQUICC II’s ABR Basic Model
The PowerQUICC II ABR flow control implements both source and destination behavior. The
30.5.1.1 ABR Flow Control Source End-System Behavior
The PowerQUICC II’s implementation of ABR flow control for end-system sources is described in the
following steps:
1. An ABR channel’s allowed cell rate (ACR) lies between the minimum cell rate (MCR) and the
peak cell rate (PCR).
2. ACR is initialized to the initial cell rate (ICR).
3. An F-RM (Forward-RM) cell is sent for every Nrm data cell sent. If more than Mrm cells are sent
and the time elapsed since the last F-RM exceeds Trm, an F-RM cell is sent.
4. When sending an F-RM cell, the current ACR is written in the CCR (current cell rate) field of the
RM cell.
5. When B-RM (backward-RM) cell is received with CI = 1 (congestion indication), ACR is reduced
by ACR × RDF (rate decrease factor). After the reduction, the new ACR is determined first by
letting ACRtemp be the min of (ACR, ER), and then taking the max of (ACRtemp, MCR).
6. When B-RM is received with CI=0 and NI=0 (no increase), ACR is increased by RIF × PCR (rate
increase factor). The new ACR is determined first by letting ACRtemp be the min of (ACR, ER),
and then taking the max of (ACRtemp, MCR).
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ATM Controller and AAL0, AAL1, and AAL5
7. Before sending an F-RM cell, if more than ADTF (ACR decrease time factor) has elapsed since
sending the last F-RM cell, ACR is reduced to ICR. In other words, if the source does not fully use
its gained bandwidth, it loses it and resumes sending at its initial cell rate.
8. Before sending an F-RM cell and after action 7, if more than Crm F-RM cells were sent since the
last B-RM cell was received with BN=0 (backward notification), the ACR is reduced by ACR ×
CDF (cutoff decrease factor).
9. A source whose ACR is less than the tag cell rate (TCR) sends out-of-rate cells at the TCR. This
behavior is intended for sources whose rates were set to zero by the network. These sources should
periodically sense the network state by sending out-of-rate RM cells. In this case data cells will not
be sent.
10. An RM cell with an incorrect CRC10 is discarded and the UNI statistics tables are updated.
30.5.1.2 ABR Flow Control Destination End-System Behavior
The PowerQUICC II’s implementation of ABR flow control for end-system destinations is described in
the following steps:
1. A received F-RM cell is turned around and sent as a B-RM cells.
2. The DIR field of the received F-RM cell is changed from 0 to 1 (backward DIR).
3. The CCR and MCR fields are taken from the F-RM and is not changed.
4. The CI bit of the B-RM cell is set if the previous data cell arrived with EFCI = 1 (congestion bit in
the ATM cell header).
5. The ER field of the turn around B-RM cells is limited by TCTE[ER-BRM].
6. If a F-RM cell arrives before the previous F-RM cell was turned around (for the same connection),
the new RM cell overwrites the old RM cell.
30.5.1.3 ABR Flowcharts
The PowerQUICC II’s ABR transmit and receive flow control is described in the following flowcharts.
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ATM Controller and AAL0, AAL1, and AAL5
Start Channel Tx
No
ACR < TCR
Source End-Sys 9
ACR is low sent only
out-of-rate cells at TCR
Yes
Send RM (DIR = forward, CCR = ACR, ER = PCR, CI = NI = 0, CLP =1)
Schedule: Time_to_send = now+1/TCR
EXIT
ACR>=TCR
RM/DATA In Rate Cell Tx
Figure 30-11. ABR Transmit Flow
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ATM Controller and AAL0, AAL1, and AAL5
RM/DATA In Rate Cell Tx
Source End-Sys 3
Count=Number of data cells from last F-RM.
Count >= Nrm
or (Count > Mrm
and Now ≥
Nrm=Number of data cells between every RM cell
Mrm=Fixed number=2
No
B-RM/DATA In Rate Cell Tx
Trm=Max time between every F-RM Cells.
(Last_RM+Trm))
F-RM In Rate Cell Tx
Yes
Checking “Time-Out Factor” Max time
allowed between RM Cells before a rate
Decrease is required.
Time = Now - Last_RM
No
Time >ADTF
Source End-Sys 7
ACR is too high
Idle adjust (“use it or loose it”)
Yes
ACR = ICR
No
Source End-Sys 8
Crm=Max number of F-RM cells without any
B-RM cell allowed before rate decrease
is required.
Unack≥Crm
Unack=Number of F-RM cells sent
without any B-RM cell received.
Yes
ACR = ACR-ACR¥CDF
ACR = max(ACR,MCR)
Source End-Sys 4
Send RM (DIR = forward, CCR = ACR, ER = PCR, CI = NI = CLP = 0)
Count=0
Last_RM = Now
First-turn = TRUE
Unack = Unack+1
Count = Count+1
First-turn = Flag indicates first turn of RM cell
with priority over data cells.
EXIT
Figure 30-12. ABR Transmit Flow (Continued)
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ATM Controller and AAL0, AAL1, and AAL5
B-RM/DATA In Rate Cell Tx
Turn-around
No
and
(First-turn or not
data-in-queue)
Destination End-Sys 1,2,3,4
B-RM In Rate Cell Tx
Yes
CI-TA = CI-TA || CI-VC
Send RM cell (DIR = backwards, CCR-TA, ER-TA, MCR-TA,
CI-TA, NI-TA, CLP=0)
CI-VC = 0
Turn-around = first-turn = FALSE
Count = Count+1
EXIT
Data Cell Tx
Send Data Cell
CLP = EFCI = 0
Count = Count+1
Schedule:Time_to_send = Now+1/ACR
EXIT
Figure 30-13. ABR Transmit Flow (Continued)
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ATM Controller and AAL0, AAL1, and AAL5
B-RM Cells Rx
No
CI = 1
Yes
Source End-Sys 5
ACR = ACR-ACR×RDF
No
NI = 0
Yes
Source End-Sys 1, 6
ACR = ACR+RIF×PCR
ACR = min(ACR,PCR)
ACR = min(ACR,ER)
ACR = max(ACR,MCR)
Source End-Sys 5, 6
No
BN = 0
The source generate this RM
Yes
Unack = 0
Unack = Number of F-RM in absence of B-RM = 0
EXIT
Figure 30-14. ABR Receive Flow
30.5.2 RM Cell Structure
Table 30-7 describes the structure of the RM cell supported by the PowerQUICC II. For more information,
see the ABR flow-control traffic management specification (TM 4.0) on the ATM Forum website.
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ATM Controller and AAL0, AAL1, and AAL5
Table 30-7. Fields and their Positions in RM Cells
Description
Fields
Octet
Bits
Value
RM-VCC
Header
1–5
All ATM cell header
PTI=6
ID
6
7
7
All Protocol ID
1
DIR
BN
0
1
Direction of RM cell (0 = forward, 1 = backward)
Backward notification (BN = 0, the cell was generated by the source;
BN=1, the cell was generated by the network or by the destination)
CI
NI
7
7
2
3
4
Congestion indication. (1 = congestion, 0 = otherwise)
No increase indication. (1 = no increase allowed, 0 = otherwise)
Not used (ATM Forum ABR)
RA
7
0
0
—
7
5-7 Reserved, should be cleared.
All Not used (ATM Forum ABR)
All Not used (ATM Forum ABR)
All Reserved, should be cleared.
0–5 Reserved, should be cleared.
6–7 CRC-10
ER
8–9
10–11
12–13
14–17
18–21
22–51
52
CCR
MCR
QL
0
SN
0
—
0x6A for each byte
0
—
CRC-10
52
53
All
30.5.2.1 RM Cell Rate Representation
Rates in the RM cells are represented in a binary floating-point format using a 5-bit exponent (e), a 9-bit
0
1
2
6
7
15
0
nz
Exponent
Mantissa
Figure 30-15. Rate Format for RM Cells
e
m
512
⎛
⎞
Rate = 2 × 1 + --------- × nz
⎝
⎠
Figure 30-16. Rate Formula for RM Cells
Initialize the traffic parameters (ER, MCR, PCR, or ICR) in the ABR protocol-specific connection tables
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ATM Controller and AAL0, AAL1, and AAL5
30.5.3 ABR Flow Control Setup
Follow these steps to setup ABR flow control:
1. Initialize the ABR data structure: RCT, TCT, RCT-ABR protocol-specific, TCTE-ABR
protocol-specific.
3. Program the AAL-type in the RCT and TCT to AAL5 and set TCT[ABRF].
NOTE
ABR flow control is available only with AAL5.
4. The time stamp timer generates the RM cell’s time stamp, which the ABR flow control monitors
to maintain source behavior in steps #3 and #7 of Section 30.5.1.1, “ABR Flow Control Source
5. Initialize the ABR parameters (CPS_ABR and LINE_RATE_ABR) in the APCT; see
parameter in the APCPT should be a power of two.
6. Finally, send the ATM TRANSMIT command to restart channel transmission.
30.6 OAM Support
This section describes the PowerQUICC II’s support for ATM-layer (F4 out-of-band, and F5 in-band)
operations and maintenance (OAM) of connections. Alarm surveillance, continuity checking, remote
defect indication, and loopback cells are supported using OAM receive and transmit AAL0 cell queues.
Using dedicated support, performance management block tests can be performed on up to 64 connections
simultaneously. The CP automatically inserts forward monitoring cells (FMC) and generates
backward-reporting cells (BRC) as recommended by ITU I.610.
30.6.1 ATM-Layer OAM Definitions
Table 30-8 lists pre-assigned header values at the user-network interface (UNI).
Table 30-8. Pre-Assigned Header Values at the UNI
Use
GFC
VPI
VCI
PTI
CLP
Segment OAM F4 flow cell
End-to-end OAM F4 flow cell
Segment OAM F5 flow cell
End-to-end OAM F5 flow cell
xxxx
xxxx
xxxx
xxxx
aaaa_aaaa
aaaa_aaaa
aaaa_aaaa
aaaa_aaaa
0000_0000_0000_0011
0000_0000_0000_0100
aaaa_aaaa_aaaa_aaaa
aaaa_aaaa_aaaa_aaaa
0a0
0a0
100
101
a
a
a
a
a = available for use by the appropriate ATM layer function
Table 30-9 lists pre-assigned header values at the network-node interface (NNI).
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ATM Controller and AAL0, AAL1, and AAL5
Table 30-9. Pre-Assigned Header Values at the NNI
Use
VPI
VCI
PTI
CLP
Segment OAM F4 flow cell
End-to-end OAM F4 flow cell
Segment OAM F5 flow cell
End-to-end OAM F5 flow cell
aaaa_aaaa_aaaa
aaaa_aaaa_aaaa
aaaa_aaaa_aaaa
aaaa_aaaa_aaaa
0000_0000_0000_0011
0000_0000_0000_0100
aaaa_aaaa_aaaa_aaaa
aaaa_aaaa_aaaa_aaaa
0a0
0a0
100
101
a
a
a
a
a= available for use by the appropriate ATM layer function
30.6.2 Virtual Path (F4) Flow Mechanism
The F4 flow is designated by pre-assigned virtual channel identifiers within the virtual path. The following
two kinds of F4 flows can exist simultaneously:
•
End-to-end (identified as VCI 4)—This flow is used for end-to-end VPC operations
communications. Cells inserted into this flow can be removed only by the endpoints of the virtual
path.
•
Segment (identified as VCI 3)—This flow is used for communicating operations information
within one VPC link or among multiple interconnected VPC links. The concatenation of VPC links
is called a VPC segment. Cells inserted into this flow can be removed only by the segment
endpoints, which must remove these cells to prevent confusion in adjacent segments.
30.6.3 Virtual Channel (F5) Flow Mechanism
The F5 flow is designated by pre-assigned payload type identifiers. The following two kinds of F5 flow
can exist simultaneously:
•
End-to-end (identified by PTI = 5)—This flow is used for end-to-end VCC operations
communications. Cells inserted into this flow can be removed only by VC endpoints.
•
Segment (identified by PTI = 4)—This flow is used for communicating operations information
with the bound of one VCC link or multiple interconnected VCC links. A concatenation of VCC
links is called a VCC segment. Segment endpoints must remove these cells to prevent confusion
in adjacent segments.
30.6.4 Receiving OAM F4 or F5 Cells
OAM F4/F5 flow cells are received using the raw cell queue, described in Section 30.4.4, “Receive Raw
considered a misinserted cell.
30.6.5 Transmitting OAM F4 or F5 Cells
OAM F4/F5 flow cells are sent using the usual AAL0 transmit flow. For OAM F4/F5 cell transmission,
program channel one in the TCT to operate in AAL0 mode. Enable the CR10 (CRC-10 insertion) mode as
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ATM Controller and AAL0, AAL1, and AAL5
insert it in an AAL0 TxBD. Finally, issue a ATM TRANSMIT command to send the OAM cell. For multiple
PHYs, use several AAL0 channels—each PHY should have one transmit raw cell queue that is associated
with its scheduling table.
A series of OAM cells can be sent using one ATM TRANSMIT command by creating a table of AAL0
TxBDs. If the channel’s TCT[AVCF] (auto VC off) is set, the transmitter automatically removes it from
the APC (that is, it does not generate periodic transmit requests for this channel after all AAL0 BDs are
processed).
30.6.6 Performance Monitoring
A connection’s performance is monitored by inspecting blocks of cells (delimited by forward monitoring
cells) sent between connection or segment endpoints. Each FMC contains statistics about the immediately
preceding block of cells. When an endpoint receives an FMC, it adds the statistics generated locally across
the same block to produce a backward reporting cell (BRC), which is then returned to the opposite
endpoint.
The PowerQUICC II can run up to 64 bidirectional block tests simultaneously. When a bidirectional test
is run, FMCs are generated for one direction and checked for the opposite.
Figure 30-17 shows the FMC and BRC cell structure.
Header = 5 bytes
Payload = 48 bytes
4
4
45 x 8
6
10
OAM
Cell
Type
Function
Specific
Fields
Function
Type
GFC/ VPI VCI PTI CLP HEC
VPI
Reserved CRC-10
0010 = Performance Management
0000 = Forward Monitoring (FMC)
0001 = Backward Reporting (BRC)
Monitoring Total User Block Error Total User
Total
Block
Total
Time-
Stamp
(TSTP)
Sequence Cell 0+1
Detection
Code
Cell 0
Count
Received
Cells 0
(TRCC0)
Error
Received
Cells 0+1
(TRCC0+1)
Unused
Number
(MCSN)
Count
Result
(BLER)
1
2
2
2
(TUC0+1) (BEDC0+1) (TUC0)
1 octet
2 octets
2 octets
2 octets
4 octets
29 octets 2 octets
1 octet
2 octets
1
2
BEDC
appears in FMCs only.
0+1
TRCC , BLER, and TRCC
appear in BRCs only.
0
0+1
Figure 30-17. Performance Monitoring Cell Structure (FMCs and BRCs)
Table 30-10 describes performance monitoring cell fields.
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ATM Controller and AAL0, AAL1, and AAL5
Table 30-10. Performance Monitoring Cell Fields
Field
Description
BRC
FMC
MCSN
Monitoring cell sequence number. The sequence number of the performance
monitoring cell (modulo 256).
Yes
Yes
TUC
Total user cell 0+1 count. Counts all user cells (modulo 65,536) sent before the
FMC was inserted.
Yes
Yes
Yes
Yes
0+1
TUC
Total user cell 0 count. Counts CLP = 0 user cells (modulo 65,536) sent before
the FMC was inserted.
0
TSTP
BEDC
Time stamp. Used to indicate when the cell was inserted.
Yes
No
Yes
Yes
Block error detection code. Even parity over the payload of the block of user cells
sent since the last FMC.
0+1
TRCC
Total received cell count 0. Counts CLP=0 user cells (modulo 65,536) received
before the FMC was received.
Yes
Yes
Yes
No
No
No
0
BLER
Block error result. Counts error parity bits detected by the BEDC of the received
FMC.
TRCC
Total received cell count 0+1. Counts all user cells (modulo 65,536) received
before the FMC was received.
0+1
30.6.6.1 Running a Performance Block Test
For bidirectional PM block tests, FMCs are monitored at the receive side and generated at the transmit side.
The following setup is required to run a bidirectional PM block test on an active VCC:
1. Assign one of the available 64 performance monitoring tables by writing to both RCT[PMT] and
TCT[PMT] and initializing the one chosen. See Section 30.10.3, “OAM Performance Monitoring
Tables.”
2. For PM F5 segment termination set RCT[SEGF]; for PM F5 end-to-end termination set
RCT[ENDF].
3. Finally, set the channel’s RCT[PM] and TCT[PM] and the receive raw cell’s RCT[PM].
For unidirectional PM block tests:
•
•
For PM block monitoring only, set only the RCT fields above.
For PM block generation only, set only the TCT fields above.
To run a block test on a VPC, assign all the VCCs of the tested VPC to the same performance monitoring
table. Configure RCT[PMT] and TCT[PMT] to specify the performance monitoring table associated with
each F4 channel.
30.6.6.2 PM Block Monitoring
PM block monitoring is done by the receiver. After initialization (see Section 30.6.6.1), whenever a cell is
received for a VCC or VPC, the TRCC counters are incremented and the BEDC is calculated. When an
FMC is received, the CP adds the BRC fields into the cell payload (TRCC0, TRCC0+1, BLER) and transfers
the cell to the receive raw cell queue. The user can monitor the BRC cell results and transfer the cell to the
transmit raw cell queue.
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ATM Controller and AAL0, AAL1, and AAL5
Before the BRC is transferred to the transmit raw cell queue, the PM function type should be changed to
backward reporting and additional checking should be done regarding the BLER field. If the sequence
numbers (MCSN) of the last two FMCs are not sequential or the differences between the last two TUCs
and the last two TRCCs are not equal, BLER should be set to all ones (see the ITU I.610 recommendation).
NOTE
TRCCs are free-running counters (modulo 65,536) that count user cells
received. The total received cells of a particular block is the difference
between TRCC values of two consecutive BRC cells. TRCC values are
taken from a VC’s performance monitoring table.
30.6.6.3 PM Block Generation
The transmitter generates the PM block. Each time the transmitted cell count parameter (TCC) in the
performance monitoring table reaches zero, the CP inserts an FMC into the user cell stream. The CP copies
the FMC header, SN-FMC, TUC0+1, TUC0, BEDC0+1-Tx from the performance monitoring table and
inserts them into the FMC payload. The TSTP value (FMC time stamp field) is taken from the
The TUCs are free-running counters (modulo 65,536) that count transmitted user cells. The total
transmitted cells of a particular block is the difference between TUC values of two consecutive FMCs. The
BEDC (BIP-16, bit interleaved parity) calculation is done on the payload of all user cells of the current
tested block. The performance monitoring block can range from 1 to 2K cells, as specified in the
BLCKSIZE parameter in the performance monitoring table; see Section 30.10.3, “OAM Performance
In Figure 30-18, the performance monitoring block size is 512 cells. For every 512 user cells sent, the ATM
controller automatically inserts an FMC into the regular cell stream as defined in ITU I.610. When an FMC
is received, the ATM controller adds the BRC fields to the cell payload and sends the cell to the raw cell
queue. The user can monitor the BRC cell results and transfer the cell to the transmit raw cell queue.
512 User Cells
512 User Cells
1
3
2
Source Cells
Stream
FMC Cell Data Cell
Data Cell FMC Cell
Data Cell
Data Cell
FMC Cell
TUC0
TUC0
TUC0
TUC0+1
BEDC
TSTP
TUC0+1
BEDC
TSTP
TUC0+1
BEDC
TSTP
3
2
1
BRC Cell
Destination BRC’s
Transmit Stream
BRC Cell
BRC Cell
TUC0
TUC0
TUC0
TUC0+1
TRCC0
TRCC0+1
BLER
TUC0+1
TRCC0
TRCC0+1
BLER
TUC0+1
TRCC0
TRCC0+1
BLER
TSTP
TSTP
TSTP
Figure 30-18. FMC, BRC Insertion
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ATM Controller and AAL0, AAL1, and AAL5
30.6.6.4 BRC Performance Calculations
BRC reception uses the regular AAL0 raw cell queue. On receiving two consecutive BRC cells, the
management layer can calculate the following:
•
•
The difference between two TUCs (Nt)
The difference between two TRCCs (Nr)
Information about the connection can be gained by comparing Nt and Nr:
•
•
•
If Nt > Nr, the difference indicates the number of lost cells of this block test.
If Nt < Nr, the difference indicates the number of misinserted cells of this block test.
When Nt = Nr, no cells are lost or misinserted.
30.7 User-Defined Cells (UDC)
Typical ATM cells are 53 bytes long and consist of a 4-byte header, 1-byte HEC, and 48-byte payload. The
PowerQUICC II also supports user-defined cells with up to 12 bytes of extra header fields for internal
information for switching applications. This choice is made during initialization by writing to the FPSMR;
extra header size can vary between 1 to 12 bytes (byte resolution) and the HEC octet is optional.
Extra Header (1–12 Bytes)
ATM Cell Header (4 Bytes) + HEC (optional)
Payload (48 Bytes)
Figure 30-19. Format of User-Defined Cells
For AAL5 and AAL1 CES the extra header is taken from the Rx and Tx BDs. The transmitter reads the
extra header from the UDC TxBD and adds it to each ATM cell associated with the current buffer. At the
receive side, the extra header of the last cell in the current buffer is written to the UDC RxBD.
For AAL0 the extra header is attached to the regular ATM cell in the buffer. The transmitter reads the extra
header and the ATM cell from the buffer. The receiver writes the extra header and the regular ATM cell to
the buffer.
30.7.1 UDC Extended Address Mode (UEAD)
For external CAM accesses, the UDC extra header can be used to supply extra routing information; see
address and the CAM match cycle performs a double-word access. UEAD_OFFSET in the parameter
RAM determines the offset from the beginning of the UDC extra header to the UEAD entry. The offset
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ATM Controller and AAL0, AAL1, and AAL5
16-bit
4-bit
12-bit
VPI
16-bit
VCI
CAM data in field:
UEAD
PHY addr
0
15 16
19 20
31 32
47
Figure 30-20. External CAM Address in UDC Extended Address Mode
30.8 ATM Layer Statistics
ATM layer statistics can be used to identify problems, such as the line-bit error rate, that affect the UNI
performance. Statistics are kept in three 16-bit wrap-around counters:
•
UTOPIA error dropped cells count—Counts cells discarded due to UTOPIA errors: Rx parity
errors and short or long cells.
•
•
Misinserted dropped cell count—Counts cells discarded due to address look-up failure.
CRC10 error dropped cell count—Counts cells discarded due to CRC10 errors. (ABR only).
Counters are implemented in the dual-port RAM for each PHY device. The counters of each PHY are
30.9 ATM-to-TDM Interworking
The PowerQUICC II supports ATM and TDM interworking. The MCCs and their corresponding SIs
handle the TDM data processing. (See Chapter 28, “Multi-Channel Controllers (MCCs),” and Chapter 15,
Possible interworking applications include the following:
•
•
•
Circuit emulation service (CES)
Carrying voice over ATM
Multiplexing several low speed services, such as voice and data, onto one ATM connection
Data forwarding between the ATM controller and an MCC can be done in two ways:
•
Core intervention. When an MCC receive buffer is full and its RxBD is closed, the MCC interrupts
the core. The core copies the MCC’s receive buffer pointer to an ATM TxBD and sets the ready bit
(TxBD[R]). Similarly, when an ATM receive buffer is full and its RxBD is closed, the core services
the ATM controller’s interrupt by copying the ATM receive buffer pointer to an MCC TxBD and
setting TxBD[R]. This mode is useful when additional core processing is required.
•
Automatic data forwarding. This mode enables automatic data forwarding between AAL1/AAL0
and transparent mode over a TDM interface.
30.9.1 Automatic Data Forwarding
The basic concept of automatic data forwarding is to program the ATM controller and the MCC to process
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ATM Controller and AAL0, AAL1, and AAL5
BD Table
TDM Interface
MCC
Buffer 1
Buffer 2
Buffer 3
Buffer 4
Buffer 5
Transmitter
0
BD 1
BD 2
BD 3
BD 4
BD 5
MCC Tx ptr
ATM Rx ptr
1
1
0
0
UTOPIA Interface
ATM*
Receiver
BD Table
UTOPIA Interface
TDM Interface
Buffer 1
Buffer 2
Buffer 3
Buffer 4
Buffer 5
ATM
Transmitter
0
BD 1
BD 2
BD 3
BD 4
BD 5
ATM Tx ptr
MCC Rx ptr
1
1
0
0
MCC*
Receiver
* The MCC and ATM receivers should be programmed to operate in opposite polarity E (empty) bit.
Figure 30-21. ATM-to-TDM Interworking
When going from TDM to ATM, the MCC receiver routes data from the TDM line to a specific BD table.
The ATM controller transmitter is programmed to operate on the same table. When the MCC fills a receive
buffer, the ATM controller sends it. The two controllers synchronize on the MCC’s RxBD[E] and the ATM
controller’s TxBD[R].
When going from ATM to TDM, the ATM receiver reassembles data received from a particular channel to
a specific BD table. The MCC transmitter is programmed to operate on the same table. When the ATM
controller fills a receive buffer, the MCC controller sends it. The controllers synchronize on the ATM
controller’s RxBD[E] and the MCC’s TxBD[R].
The MCC and ATM receivers must be programmed to operate in opposite E-bit polarity. That is, both
receivers receive data into buffers whose RxBD[E] = 0 and set RxBD[E] when a buffer is full. For the ATM
receiver, set RCT[INVE] of the AAL1- and AAL0-specific areas of the receive connection table; see
30.9.2 Using Interrupts in Automatic Data Forwarding
The core can program the MCC and ATM interrupt mechanism to trigger interrupts for events such as a
buffer closing or transfer errors. The interrupt mechanism can be used to synchronize the start of the
automatic bridging process. For example, to start the MCC transmitter after a specific buffer reaches the
ATM receiver (the buffering is required to cope with the ATM network’s CDV), set ATM RxBD[I]. When
the receive buffer is full, the RxBD is closed, RxBD[E] is set (because it is operating in opposite E-bit
polarity), and the core is interrupted. The core then starts the MCC transmitter.
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ATM Controller and AAL0, AAL1, and AAL5
30.9.3 Timing Issues
Use of the TDM interface assumes that all communicating entities are synchronized (that is, that they are
using a synchronized serial clock). If the TDM interfaces are not synchronized, a slip can occur in the
reassembly buffer. If a buffer-not-ready event occurs at the MCC transmitter, the user must restart the
MCC transmit channel. If a buffer-not-ready event occurs at the ATM transmitter, the user must restart the
ATM transmit channel.
30.9.4 Clock Synchronization (SRTS and Adaptive FIFOs)
Clock synchronization methods, such as using a time stamp (SRTS) or adaptive FIFOs, prevent buffer
slipping during reassembly. The SRTS method may be implemented using external logic. The
PowerQUICC II can read the SRTS from external logic and insert it into AAL1 CES cells, and can track
the SRTS from AAL1 CES cells and deliver it to external logic. See Section 30.15, “SRTS Generation and
Alternatively, an adaptive FIFOs method can be implemented using the core to maintain the bridging
buffer at a mid-level point. The difference between the MCC and ATM data pointers is a measure of buffer
synchronization. The core calculates the difference between pointers at regular intervals and adapts the
TDM clock accordingly to hold the difference constant.
30.9.5 Mapping TDM Time Slots to VCs
Using the MCC and the SI, any TDM time-slot combination can be routed to a specific data buffer. (See
Assigner.”) The same data buffers should be used by the ATM controller to route receive and transmit data.
30.9.6 CAS Support
For applications requiring channel-associated signaling (CAS), circuit emulation with CAS requires
additional core processing. External framers perform the CAS manipulation through a serial or parallel
interface.
When the MCC receives a multi-frame block, it generates an interrupt to the core. The core reads the CAS
block from the external framer and places it at the end of the ATM data buffer after the structured
multi-frame block. The core then passes the buffer pointer to the ATM controller, and the controller packs
the data and CAS block into AAL1 CES cells. All AAL1 CES functions, such as generating PDU-headers
and structured pointers, operate normally.
When the ATM controller receives a multi-frame block, it generates an interrupt to the core. The core reads
the CAS block from the data buffer and writes it to the external framer. The core then moves the buffer
pointer to the MCC. The buffer’s data length should not include the CAS octets.
To optimize the process, the framer may interrupt the core only when the CAS information changes. (CAS
information changes slowly.) The core can keep the CAS block in memory and connect to the framer only
when the CAS changes. The core can use regular read and write cycles when connecting to the framer
through a parallel interface.
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ATM Controller and AAL0, AAL1, and AAL5
The MCC and ATM controller should be synchronized with the framer’s multi-frame block boundary. At
the ATM side, the structured block size should equal the multi-frame block size plus the size of the CAS
block so that the structured pointer, inserted by the ATM controller, points to the start of the structured data
block. At the MCC side, the MCC must to be synchronized with the super frame sync signal. This
synchronization can be achieved by external logic that triggers on the super frame sync signal and starts
delivering the frame sync to the MCC. When loss of super frame synchronization occurs, this logic should
reset and trigger again on the next super frame indication.
30.9.7 Trunk Condition
According to the Bellcore standard, the interworking function (IWF) should be able to transmit special
payload on both ATM and TDM channels to signal alarm conditions (Bellcore TR-NWT-000170). The
core can be used to generate the trunk condition payload in special buffers (or existing buffers) for the
ATM controller or MCC.
30.9.8 ATM-to-ATM Data Forwarding
Automatic data forwarding can be used to switch ATM AAL0 cells from one ATM port to another without
core intervention. The ATM receiver and transmitter should be programed to process the same BD table.
When the ATM receiver fills an AAL0 buffer, the ATM transmitter sends it. The ATM receiver and
transmitter are synchronized using the same mechanism as described for ATM-to-TDM automatic
30.10 ATM Memory Structure
The ATM memory structure, described in the following sections, includes the parameter RAM, the
connection tables, OAM performance monitoring tables, the APC data structure, BD tables, the AAL1
CES sequence number protection table and the UNI statistics table.
30.10.1 Parameter RAM
Table 30-11. ATM Parameter RAM Map
1
Offset
Name
Width
Description
0x00–0x3
F
—
—
Reserved, should be cleared.
0x40
0x42
RCELL_TMP_
BASE
Hword Rx cell temporary base address. Points to a total of 64 bytes reserved
dual-port RAM area used by the CP. Should be 64 byte aligned.
User-defined offset from dual-port RAM base. (Recommended address
space: 0x3000-0x4000 or 0xB000–0xC000)
TCELL_TMP_BASE
Hword Tx cell temporary base address. Points to total of 64 bytes reserved
dual-port RAM area used by the CP. Should be 64-byte aligned.
User-defined offset from dual-port RAM base. (Recommended address
space: 0x3000–0x4000 or 0xB000–0xC000)
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ATM Controller and AAL0, AAL1, and AAL5
Table 30-11. ATM Parameter RAM Map (continued)
Width Description
1
Offset
Name
0x44
UDC_TMP_BASE
Hword UDC mode only. Points to a total of 64 bytes reserved dual-port RAM area
used by the CP. Should be 64-byte aligned. User-defined offset from
dual-port RAM base. (Recommended address space: 0x3000–0x4000 or
0xB000–0xC000)
0x46
0x48
0x4A
INT_RCT_BASE
INT_TCT_BASE
INT_TCTE_BASE
Hword Internal receive connection table base. User-defined offset from dual-port
RAM base.
Hword Internal transmit connection table base. User-defined offset from
dual-port RAM base.
Hword Internal transmit connection table extension base. User-defined offset
from dual-port RAM base.
0x4C
0x50
0x54
0x58
0x5C
—
Word Reserved, should be cleared.
EXT_RCT_BASE
EXT_TCT_BASE
EXT_TCTE_BASE
UEAD_OFFSET
Word External receive connection table base. User-defined.
Word External transmit connection table base. User-defined.
Word External transmit connection table extension base. User-defined.
Hword User-defined cells mode only. Offset to the user-defined extended
address (UEAD) in the UDC extra header. Must be an even address. See
If RCT[BO] = 01, UEAD_OFFSET should be in little-endian format. For
example, if the UEAD entry is the first half word of the extra header in
external memory, UEAD_OFFSET should be programmed to 2 (second
half word entry in dual-port RAM).
0x5E
0x60
—
Hword Reserved, should be cleared.
PMT_BASE
Hword Performance monitoring table base. User-defined offset from dual-port
RAM base.
0x62
0x64
0x66
APCP_BASE
FBT_BASE
INTT_BASE
Hword APC parameter table base address. User-defined offset from dual-port
RAM base.
Hword Free buffer pool parameter table base. User-defined offset from dual-port
RAM base.
Hword Interrupt queue parameter table base. User-defined offset from dual-port
RAM base.
0x68
0x6A
—
—
Reserved, should be cleared.
UNI_STATT_BASE
Hword UNI statistics table base. User-defined offset from dual-port RAM base.
Note that this must be set up according to Section 29.10.7, “UNI Statistics
Table>” It is not optional.
0x6C
BD_BASE_EXT
Word BD table base address extension. BD_BASE_EXT[0–7] holds the 8
most-significant bits of the Rx/Tx BD table base address.
BD_BASE_EXT[8–31] should be zero. User-defined.
0x70
0x74
VPT_BASE /
EXT_CAM_BASE
Word Base address of the address compression VP table/external CAM.
User-defined.
VCT_BASE
Word Base address of the address compression VC table. User-defined.
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ATM Controller and AAL0, AAL1, and AAL5
Table 30-11. ATM Parameter RAM Map (continued)
Width Description
1
Offset
Name
0x78
VPT1_BASE /
EXT_CAM1_BASE
Word Base address of the address compression VP1 table/EXT CAM1.
User-defined.
0x7C
0x80
0x82
VCT1_BASE
VP_MASK
VCIF
Word Base address of the address compression VC1 table. User-defined.
Hword VP mask for address compression lookup. User-defined.
Hword VCI filtering enable bits. When cells with VCI = 3, 4, 6, 7-15 are received
and the associated VCIF bit = 1 the cell is sent to the raw cell queue.
VCIF[0–2, 5] should be zero. See Section 30.10.1.2, “VCI Filtering
(VCIF).”
0x84
GMODE
(GMODE).”
0x86
0x88
0x8A
0x8C
0x90
0x94
0x98
COMM_INFO
Hword The information field associated with the last host command.
Hword
Hword
—
Word Reserved, should be cleared.
Word Preset for CRC32. Initialize to 0xFFFF_FFFF.
Word Constant mask for CRC32. Initialize to 0xDEBB_20E3.
CRC32_PRES
CRC32_MASK
AAL1_SNPT_BASE
Hword AAL1 SNP protection look-up table base address. (AAL1 CES only.) The
32-byte table resides in dual-port RAM. AAL1_SNPT_BASE must be
halfword-aligned. User-defined offset from dual-port RAM base. See
0x9A
0x9C
—
Hword Reserved, should be cleared.
SRTS_BASE
Word External SRTS logic base address. AAL1 CES only. Should be 16-byte
aligned. The four least-significant bits are taken from SRTS_DEV in the
AAL1-specific area of the connection table entries.
0xA0
IDLE/UNASSIGN_BAS Hword Idle/unassign cell base address. Points to dual-port RAM area contains
E
idle/unassign cell template (little-endian format). Should be 64-byte
aligned. User-defined offset from dual-port RAM base. The ATM header
should be 0x0000_0000 or 0x0100_0000 (CLP=1).
0xA2
0xA4
0xA8
IDLE/UNASSIGN_SIZE Hword Idle/unassign cell size. 52 in regular mode; 53–64 in UDC mode.
EPAYLOAD
Trm
Word Reserved payload. Initialize to 0x6A6A_6A6A.
Word (ABR only) The upper bound on the time between F-RM cells for an active
source. TM 4.0 defines the Trm period as 100 msec. The Trm value is
defined by the system clock and the time stamp timer prescaler; see
stamp prescalar of 1µs, program Trm to be 100 ms/1µs = 100,000.
0xAC
0xAE
Nrm
Mrm
Hword (ABR only) Controls the maximum cells the source may send for each
F-RM cell. Set to 32 cells.
Hword (ABR only) Controls the bandwidth between F-RM, B-RM and user data
cell. Set to 2 cells.
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ATM Controller and AAL0, AAL1, and AAL5
Table 30-11. ATM Parameter RAM Map (continued)
Width Description
1
Offset
Name
0xB0
TCR
Hword (ABR only) Tag cell rate. The minimum cell rate allowed for all ABR
channels. An ABR channel whose ACR is less than TCR sends only
out-of-rate F-RM cells at TCR. Should be set to 10 cells/sec as defined in
the TM 4.0. Uses the ATMF TM 4.0 floating-point format. Note that the
APC minimum cell rate (MCR) should be at least TCR.
0xB2
—
ABR_RX_TCTE
Hword (ABR only) Points to total of 16 bytes reserved dual-port RAM area used
by the CP. Should be 16-byte aligned. User-defined offset from dual-port
RAM base.
Additional parameters
—
1
30.10.1.1 Determining UEAD_OFFSET (UEAD Mode Only)
The UEAD_OFFSET value is based on the position of the user-defined extended address (UEAD) in the
halfword-aligned location of the UEAD, and then read the corresponding UEAD_OFFSET value.
Offset
0x0
0
15 16
31
UEAD_OFFSET = 0x2
UEAD_OFFSET = 0x6
UEAD_OFFSET = 0xA
UEAD_OFFSET = 0x0
UEAD_OFFSET = 0x4
UEAD_OFFSET = 0x8
0x4
0x8
Table 30-12. UEAD_OFFSETs for Extended Addresses in the UDC Extra Header
30.10.1.2 VCI Filtering (VCIF)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Field
0
0
0
VC3 VC4
0
VC6 VC7 VC8 VC9 VC10 VC11 VC12 VC13 VC14 VC15
Figure 30-22. VCI Filtering Enable Bits
Table 30-13 describes the operation of the VCI filtering enable bits.
Table 30-13. VCI Filtering Enable Field Descriptions
Bits
Name
Description
0–2, 5
—
Clear these bits.
3, 4, 6,
7–15
VCx VCI filtering enable
0 Do not send cells with this VCI to the raw cell queue.
1 Send cells with this VCI to the raw cell queue.
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ATM Controller and AAL0, AAL1, and AAL5
30.10.1.3 Global Mode Entry (GMODE)
Figure 30-23 shows the layout of the global mode entry (GMODE).
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
Field
0
0
GBL
0
0
0
ALB CTB REM
0
IMA_EN UEAD CUAB EVPT
0
ALM
Figure 30-23. Global Mode Entry (GMODE)
1
MPC8264 and MPC8266 only.
Table 30-14 describes GMODE fields.
Table 30-14. GMODE Field Descriptions
Bits
Name
Description
0–1
2
—
Reserved, should be cleared.
GBL Global. Asserting GBL enables snooping of connection tables. GBL should not be asserted if any of
the related DMAs will access the local bus.
3–5
6
—
Reserved, should be cleared.
ALB Address look up bus for CAM or address compression tables
0 Reside on the 60x bus.
1 Reside on the local bus.
7
8
CTB External connection tables bus
0 Reside on the 60x bus.
1 Reside on the local bus.
1
REM
Receive emergency mode
0 Enable REM operation. When the receive FIFO is full, the ATM transmitter stops sending data
cells until the receiver emergency state is cleared (FIFO not full). The transmitter pace is
maintained, although a small CDV may be introduced. This mode enables the receiver to receive
bursts of cells above the steady state performance.
1 Disable REM operation. Note that to check system performance the user may want to set this bit.
9–10
10
—
Reserved, should be cleared.
IMA_E MPC8264 and MPC8266 only: Enable the associated FCC in IMA mode.
N
0 Default. FCC Enabled in normal ATM mode
1 FCC enabled in IMA mode
Note that individual PHYs of those IMA-mode enabled FCCs may still be set for non-IMA
functionality via the IMAPHY register in the IMA root table.
11
(UEAD).”
0 Disable UEAD mode.
1 Enable UEAD mode.
12
13
CUAB Check unallocated bits
0 Do not check unallocated bits during address compression.
1 Check unallocated bits during address compression.
EVPT External address compression VP table
0 VP table resides in dual-port RAM.
1 VP table reside in external memory.
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ATM Controller and AAL0, AAL1, and AAL5
Table 30-14. GMODE Field Descriptions (continued)
Description
Bits
Name
14
15
—
Reserved, should be cleared.
0 External CAM lookup.
1 Address compression.
1
MPC8264 and MPC8266 only: GMODE[REM] must be set to disable receive emergency mode. If receive emergency
mode were enabled, it would result in IMA transmit protocol violations in cases of system overload, potentially avoiding
protocol errors in the IMA receiver at the expense of generating IMA transmit protocol violations to the far end. Rather
than causing erratic transmit operation, it is better to set GMODE[REM] and deal with the IMA receive protocol
violations locally. Note further that the system should be designed such that overload problems never occur in the
field; any errors due to overload should be eliminated during system design and debug.
30.10.2 Connection Tables (RCT, TCT, and TCTE)
The receive and transmit connection tables, RCT and TCT, store host-initialized connection parameters
after connection set-up. These include AAL type, connection traffic parameters, BD parameters and
temporary parameters used during segmentation and reassembly (SAR). The transmit connection table
extension (TCTE) supports special connections that use ABR, VBR or UBR+ services. Each connection
Table 30-15. Receive and Transmit Connection Table Sizes
ATM Service Class
RCT
TCT
TCTE
CBR, UBR service
32 bytes
32 bytes
32 bytes
32 bytes
—
ABR, VBR, UBR+ service
32 bytes
NOTE
An ATM channel is considered internal if its tables are in an internal
dual-port RAM; it is considered external if its tables are in external
memory.To improve performance, store parameters for fast channels in
internal dual-port RAM and parameters for slower channels in external
memory. Connection tables for external channels are read and written from
external memory each time the CP processes a cell. The CP does, however,
minimize memory access time by burst fetching the 32-byte entry and
writing back only the first 24 bytes.
In all connection tables, fields which are not used must be cleared.
30.10.2.1 ATM Channel Code
Each ATM channel has a channel code used as an index to the channel’s connection table entry. The first
channel in the table has channel code one, the second has channel code two, and so on. Codes of 255 or
less indicate internal channels; codes greater than 255 indicate external channels. Channel code one is
reserved as the raw cell queue and cannot be used for another purpose. The channel code is used to specify
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ATM Controller and AAL0, AAL1, and AAL5
a VC when sending a ATM TRANSMIT command, initiating the external CAM or address compression
tables, and when the CP sends an interrupt to an interrupt queue.
Example:
Suppose a configuration supports 1,024 regular ATM channels. To allocate 4 Kbytes of dual-port RAM
space to the internal connection table, determine that channel codes 0–63 are internal (64 VCs × 64 bytes
(RCT and TCT) = 4 K). Channels 0–1 are reserved. The remaining 962 (1024 - 62) external channels are
Dual-Port RAM
External Memory
EXT_RCT_BASE
INT_RCT_BASE
Reserved
RCT256
RCT257
RCT258
RCT259
Raw Cell (AAL0)
RCT2
RCT3
RCT63
RCT1217
Figure 30-24. Example of a 1024-Entry Receive Connection Table
The general formula for determining the real starting address for all internal and external connection table
entries is as follows:
Connection table base address + (channel code × 32)
Thus, the real starting address of the RCT entry associated with channel code 3 is as follows:
INT_RCT_BASE+ (3 × 32) = INT_RCT_BASE + 96
Even though it produces a gap in the connection table, the first external channel’s real starting address of
the RCT entry (channel code 256) is as follows:
EXT_RCT_BASE+ (256 × 32) = EXT_RCT_BASE + 8192
See Section 30.10.1, “Parameter RAM,” to find all the connection table base address parameters. (The
transmit connection table base address parameters are INT_TCT_BASE, EXT_TCT_BASE,
INT_TCTE_BASE, and EXT_TCTE_BASE.)
30.10.2.2 Receive Connection Table (RCT)
Figure 30-25 shows the format of an RCT entry.
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ATM Controller and AAL0, AAL1, and AAL5
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Offset + 0x00
—
GBL
BO
—
DTB BIB
—
—
BUFM SEGF ENDF
—
INTQ
AAL
Offset + 0x02 — INF
Offset + 0x04
Offset + 0x06
Offset + 0x08
Offset + 0x0A
Offset + 0x0C
Offset + 0x0E
Offset + 0x10
ABRF
RX Data Buffer Pointer (RXDBPTR)
Cell Time Stamp
RBD_Offset
Protocol Specific
Offset + 0x12
Offset + 0x14
Offset + 0x16
Offset + 0x18
Offset + 0x1A
Offset + 0x1C
Offset + 0x1E
MRBLR
—
PMT
RBD_BASE
RBD_BASE
Figure 30-25. Receive Connection Table (RCT) Entry
—
PM
Table 30-16 describes RCT fields.
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ATM Controller and AAL0, AAL1, and AAL5
Table 30-16. RCT Field Descriptions
Offset
Bits
Name
Description
0x00
0–1
2
—
Reserved, should be cleared.
GBL
Global. Asserting GBL enables snooping of data buffers, BD, interrupt queues and
free buffer pool.
3–4
BO
Byte ordering—used for data buffers.
00 Reserved
01 Munged little endian
1x Big endian
5
6
—
Reserved, should be cleared.
DTB
Data buffers bus
0 Data buffers reside on the 60x bus.
1 Data buffers reside on the local bus.
7
BIB
BD, interrupt queues, free buffer pool and external SRTS logic bus
0 Reside on the 60x bus.
1 Reside on the local bus.
Note that when using AAL5 or AAL1 CES in UDC mode, BDs must be placed on the
same bus (RCT[DTB] = RCT[BIB]). This is necessary because in UDC mode the
user-defined header, which is part of the cell data, is read using the same bus
configuration (byte ordering and bus type) as the payload. Therefore, if data is placed
on the 60x bus and the BD on the local bus, the SDMA accesses the UDC header on
the 60x bus with the address of the local bus.
8
9
—
Reserved, should be cleared.
BUFM
0 Static buffer allocation mode. Each BD is associated with a dedicated buffer.
1 Global buffer allocation mode. Free buffers are fetched from global free buffer pools.
10
11
SEGF
ENDF
OAM F5 segment filtering
0 Do not send cells with PTI = 100 to the raw cell queue.
1 Send cells with PTI = 100 to the raw cell queue.
OAM F5 end-to-end filtering
0 Do not send cells with PTI=101 to the raw cell queue.
1 Send cells with PTI=101 to the raw cell queue.
12–13
14–15
—
Reserved, should be cleared.
INTQ
Points to one of four interrupt queues available.
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ATM Controller and AAL0, AAL1, and AAL5
Table 30-16. RCT Field Descriptions (continued)
Description
Internal use only. Should be cleared.
Offset
Bits
Name
0x02
0
1
—
INF
(AAL5 only) Indicates the receiver state. Initialize to 0
0 In idle state.
1 In AAL5 frame reception state.
2–11
12
—
Internal use only. Should be cleared.
ABRF
(AAL5 only). Controls ABR flow.
0 ABR flow control is disabled.
1 ABR flow control is enabled.
13–15
AAL
AAL type
000 AAL0—Reassembly with no adaptation layer
001 AAL1—ATM adaptation layer 1 protocol
010 AAL5—ATM adaptation layer 5 protocol
All others reserved.
0x04
0x08
—
—
RxDBPTR Receive data buffer pointer. Holds real address of current position in the Rx buffer.
Cell Time Used for reassembly time-out. Whenever a cell is received, the PowerQUICC II time
Stamp
stamp timer is sampled and written to this field. See Section 14.3.8, “RISC
0x0C
—
RBD_Offset RxBD offset from RBD_BASE. Points to the channel’s current BD. User-initialized to
0; updated by the CP.
0x0E-0x
18
—
Protocol-specific area.
0x1A
0x1C
—
MRBLR
—
Maximum receive buffer length. Used in both static and dynamic buffer allocation.
Reserved, should be cleared.
0–1
2–7
PMT
Performance monitoring table. Points to one of the available 64 performance
monitoring tables. The starting address of the table is PMT_BASE+PMT × 32. Can be
changed on-the-fly.
8–15 RBD_BASE RxBD base. Points to the first BD in the channel’s RxBD table. The 8 most-significant
bits of the address are taken from BD_BASE_EXT in the parameter RAM. The four
0x1E
0–11
least-significant bits of the address are taken as zeros.
12–14
15
—
Reserved, should be cleared.
PM
Performance monitoring. Can be changed on-the-fly.
0 No performance monitoring for this VC.
1 Perform performance monitoring for this VC. Whenever a cell is received for this VC
the performance monitoring table that its code is written in the PMT field is updated.
30.10.2.2.1 AAL5 Protocol-Specific RCT
Figure 30-26 shows the AAL5 protocol-specific area of an RCT entry.
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ATM Controller and AAL0, AAL1, and AAL5
0
15
Offset + 0x0E
TML
Offset + 0x10
Offset + 0x12
Offset + 0x14
Offset + 0x16
Offset + 0x18
RX CRC
RBDCNT
—
—
RXBM RXFM
—
BPOOL
Figure 30-26. AAL5 Protocol-Specific RCT
Table 30-17 describes AAL5 protocol specific RCT fields.
Table 30-17. RCT Settings (AAL5 Protocol-Specific)
Offset
Bits
Name
Description
0x0E
0x10
0x14
—
—
—
TML
Total message length. This field is used by the CP.
CRC32 temporary result.
RxCRC
RBDCNT RxBD count. Indicates how may bytes remain in the current Rx buffer. RBDCNT is
initialized with MRBLR whenever the CP opens a new buffer.
0x16
0x18
—
0–7
8
—
—
Reserved, should be cleared.
Reserved, should be cleared.
RXBM
Receive buffer interrupt mask. Determines whether the receive buffer event is
disabled. Can be changed on-the-fly.
0 The event is disabled for this channel. (The RXB event is not sent to the interrupt
queue when receive buffers are closed.)
1 The event is enabled for this channel.
9
RXFM
Receive frame interrupt mask. Determines whether the receive frame event is
disabled. Can be changed on-the-fly.
0 The event is disabled for this channel. (RXF event is not sent to the interrupt queue.)
1 The event is enabled for this channel.
10–13
14–15
—
Reserved, should be cleared.
BPOOL
Buffer pool. Global buffer allocation mode only. Points to one of four free buffer pools.
30.10.2.2.2 AAL5-ABR Protocol-Specific RCT
Figure 30-27 shows the AAL5-ABR protocol-specific area of an RCT entry.
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ATM Controller and AAL0, AAL1, and AAL5
0
15
Offset + 0x0E
Offset + 0x10
Offset + 0x12
Offset + 0x14
Offset + 0x16
Offset + 0x18
AAL5 Protocol-Specific
PCR
RDF
RIF
AAL5 Protocol-Specific
Figure 30-27. AAL5-ABR Protocol-Specific RCT
Table 30-18 describes AAL5-ABR protocol-specific RCT fields.
Table 30-18. ABR Protocol-Specific RCT Field Descriptions
Offset
Bits
Name
Description
0x0E
0x16
—
—
—
AAL5 protocol-specific
PCR Peak cell rate. The peak number of cells per second of the current ABR channel. The ACR
(allowed cell rate) never exceeds this value. PCR uses the ATMF TM 4.0 floating-point
format.
0x18
0–3
4–7
RDF Rate decrease factor for the current ABR channel. Controls the decrease in cell
transmission rate upon receipt of a backward RM cell. RDF represents a negative
-RDF
exponent of two, that is, the decrease factor = 2
1/32768 (RDF=0xF) to 1 (RDF=0).
. The decrease factor ranges from
RIF
—
Rate increase factor of the current ABR channel. Controls the increase in the cell
transmission rate upon receipt of a backward RM cell. RIF represents a negative exponent
of two, that is, the increase factor = 2 . The increase factor ranges from 1/32768
-RIF
(RIF=0xF) to 1 (RIF=0).
8–15
AAL5 protocol-specific
30.10.2.2.3 AAL1 Protocol-Specific RCT
Figure 30-28 shows the AAL1 protocol-specific area of an RCT entry.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Offset + 0x0E
Offset + 0x10
Offset + 0x12
Offset + 0x14
Offset + 0x16
Offset + 0x18
—
PFM SRT INVE STF
—
—
SRTS_TMP
—
SRTS_DEV
—
Valid Octet Size (VOS)
SPV
Structured Pointer (SP)
RBDCNT
—
SN
—
SNEM
—
RXBM
—
Figure 30-28. AAL1 Protocol-Specific RCT
Table 30-19 describes AAL1 protocol-specific RCT fields.
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ATM Controller and AAL0, AAL1, and AAL5
Table 30-19. AAL1 Protocol-Specific RCT Field Descriptions
Offset Bits
Name
Description
0x0E
0–7
8
—
Reserved, should be cleared.
Partially filled mode.
PFM
0 Partially filled cells mode is not used.
1 Partially filled cells mode is used. The receiver copies only valid octets from the
AAL1 cell to the Rx buffer. The number of the valid octets from the beginning of the
AAL1 user data field is specified in the VOS (valid octet size) field.
9
SRT
Synchronous residual time stamp. Unstructured format only. The PowerQUICC II
supports clock recovery using an external SRTS PLL. The PowerQUICC II tracks the
SRTS from the incoming four cells with SN = 1, 3, 5, and 7 and writes it to the external
SRTS device. Every eight cells the CP writes a valid SRTS to external logic. (See
0 SRTS mode is not used.
1 SRTS mode is used.
10
11
INVE
STF
—
Inverted empty.
0 RxBD[E] is interpreted normally (1 = empty, 0 = not empty).
1 RxBD[E] is handled in negative logic (0 = empty, 1 = not empty).
Structured format
0 Unstructured format is used.
1 Structured format is used.
12–15
0–3
Reserved, should be cleared.
0x10
0x12
SRTS_TMP Used by the CP to store the received SRTS code. After a cell with SN = 7 is received,
the CP writes the SRTS code to the external SRTS device.
4–11
—
Reserved, should be cleared.
12–15 SRTS_DEV Selects an SRTS device, whose address is SRTS_BASE[0–27] + SRTS_DEV[28–31].
The 16 byte-aligned SRTS_BASE is taken from the parameter RAM.
0–1
2–7
—
Reserved, should be cleared.
VOS
Valid octet size. Specifies the number of valid octets from the beginning of the AAL1
user data field. For unstructured, service values 1–47 are valid; for structured service,
values 1-46 are valid. Partially filled cell mode only.
8
SPV
SP
Structured pointer valid. Should be user-initialized user to zero. Structured format only.
9–15
Structured pointer. Used by the CP to calculate the structured pointer. This field should
be initialized by the user to zero. Used in structured format only.
0x14
—
RBDCNT RxBD count. Indicates how may bytes remain in the current Rx buffer. Initialized with
MRBLR whenever the CP opens a new buffer.
0x16 0–12
13–15
—
Reserved, should be cleared.
SN
Sequence number. Used by the CP to check incoming cell’s sequence number.
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ATM Controller and AAL0, AAL1, and AAL5
Table 30-19. AAL1 Protocol-Specific RCT Field Descriptions (continued)
Offset Bits
Name
Description
0x18
0–3
4
—
Reserved, should be cleared.
SNEM
Sequence number error flag interrupt mask
0 This mode is disabled.
1 When an out-of-sequence error occurs, an RXB interrupt is sent to the interrupt
queue even if RCT[RXBM] is cleared. Note that this mode is the buffer error
reporting mechanism during automatic data forwarding (ATM-to-TDM bridging)
when no buffer processing is required (RCT[RXBM]=0).
5–7
8
—
Reserved, should be cleared.
RXBM
Receive buffer interrupt mask
0 The receive buffer event of this channel is disabled. (The event is not sent to the
interrupt queue.)
1 The receive buffer event of this channel is enabled.
9–15
—
Reserved, should be cleared.
30.10.2.2.4 AAL0 Protocol-Specific RCT
Figure 30-29 shows the layout for the AAL0 protocol-specific RCT.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Offset + 0x0E
Offset + 0x10
Offset + 0x12
Offset + 0x14
Offset + 0x16
Offset + 0x18
—
0
1
INVE
—
—
—
RXBM
—
Figure 30-29. AAL0 Protocol-Specific RCT
Table 30-20 describes AAL0 protocol specific RCT fields.
Table 30-20. AAL0-Specific RCT Field Descriptions
Offset Bits
Name
Description
0x0E
0-7
8-9
10
—
Reserved, should be cleared.
0b01
INVE
Must be programmed to 0b01 for AAL0.
Inverted empty.
0 RxBD[E] is interpreted normally (1 = empty, 0 = not empty).
1 RxBD[E] is handled in negative logic (0 = empty, 1 = not empty).
11-15
—
—
—
Reserved, should be cleared.
0x10
Reserved, should be cleared.
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Table 30-20. AAL0-Specific RCT Field Descriptions (continued)
Offset Bits
Name
Description
0x18
0–7
8
—
Reserved, should be cleared.
Receive buffer interrupt mask
RXBM
0 The receive buffer event of this channel is masked. (The RXB event is not sent to the
interrupt queue when receive buffers are closed.)
1 The receive buffer event of this channel is enabled.
9–15
—
Reserved, should be cleared.
30.10.2.2.5 AAL1 CES Protocol-Specific RCT
30.10.2.2.6 AAL2 Protocol-Specific RCT
30.10.2.3 Transmit Connection Table (TCT)
Figure 30-30 shows the format of an TCT entry.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Offset + 0x00
Offset + 0x02
Offset + 0x04
Offset + 0x06
Offset + 0x08
Offset + 0x0A
Offset + 0x0C
Offset + 0x0E
Offset + 0x10
Offset + 0x12
Offset + 0x14
—
GBL
BO
—
DTB BIB AVCF
—
—
ATT
CPUU VCON
ABRF
INTQ
AAL
—
INF
Tx Data Buffer Pointer (TXDBPTR)
TBDCNT
TBD_OFFSET
Rate Remainder
PCR Fraction
PCR
Protocol Specific
Offset + 0x16
Offset + 0x18
Offset + 0x1a
Offset + 0x1C
Offset + 0x1E
APC Linked Channel (APCLC)
ATM Cell Header (VPI,VCI,PTI,CLP)
—
PMT
TBD_BASE
TBD_BASE
BNM STPT IMK PM
Figure 30-30. Transmit Connection Table (TCT) Entry
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ATM Controller and AAL0, AAL1, and AAL5
Table 30-21 describes general TCT fields.
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ATM Controller and AAL0, AAL1, and AAL5
Table 30-21. TCT Field Descriptions
Offset Bits
Name
Description
0x00
0–1
2
—
Reserved, should be cleared.
GBL
Global. Asserting GBL enables snooping of data buffers, BDs, interrupt queues and free
buffer pool.
3–4
BO
Byte ordering. This field is used for data buffers.
00 Reserved
01 Power PC little endian
1x Big endian
5
6
—
Reserved, should be cleared.
DTB
Data buffer bus
0 Reside on the 60x bus.
1 Reside on the local bus.
7
8
BIB
BD, interrupt queue and external SRTS logic bus
0 Reside on the 60xbus.
1 Reside on the local bus.
Note: When using AAL5, AAL1 CES in UDC mode, BDs and data should be placed on
the same bus (TCT[DTB]=TCT[BIB]).
AVCF
Auto VC off. Determines the behavior of the APC when the last buffer associated with
this VC has been sent and no more ready buffers are in the VC’s TxBD table.
0 The APC does not remove this VC from the schedule table and continues to schedule
it to transmit.
1 The APC removes this VC from the schedule table. To continue transmission after the
host adds buffers for transmission, a new ATM TRANSMIT command is needed, which
can be issued only after the CP clears TCT[VCON].
Note: When over-subscribing UBR or UBR+ channels, set AVCF so that the CPM does
not become overloaded polling non-active VCs.
9
—
Reserved, should be cleared.
10–11
ATT
ATM traffic type
00 Peak cell-rate pacing. The host must initialize PCR and the PCR fraction. Other
traffic parameters are not used.
01 Peak and sustain cell rate pacing (VBR traffic). The APC performs a
continuous-state leaky bucket algorithm (GCRA) to pace the channel-sustain cell
rate. The host must initialize PCR, PCR fraction, SCR, SCR fraction, and BT (burst
tolerance).
10 Peak and minimum cell rate pacing (UBR+ traffic). The host must initialize PCR,
PCR fraction, MCR, MCR fraction, and MDA.
11 Reserved
12
13
CPUU
VCON
INTQ
CPCS-UU+CPI insertion (used for AAL5 only).
0 CPCS-UU+CPI insertion disabled. The transmitter clears the CPCS-UU+CPI fields.
1 CPCS-UU+CPI insertion enabled. The transmitter reads the CPCS-UU+CPI (16-bit
entry) from external memory. It should be placed after the end of the last buffer (it
should not be included in the buffer length).
Virtual channel is on.
Should be set by the host before it issues an ATM TRANSMIT command. When the host
sets TCT[STPT] (stop transmit), the CP deactivates this channel and clears VCON
when the channel is next encountered in the APC scheduling table. The host can issue
another ATM TRANSMIT command only after the CP clears VCON.
14–15
Points to one of four interrupt queues available.
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ATM Controller and AAL0, AAL1, and AAL5
Table 30-21. TCT Field Descriptions (continued)
Description
Offset Bits
Name
0x02
0
1
—
Internal use only. Should be cleared.
INF
Used for AAL5 Only. Indicates the transmitter state. Initialize to 0
0 In idle state.
1 In AAL5 frame transmission state.
2–11
12
—
Internal use only. Should be cleared.
ABRF
Used for AAL5 Only.
0 ABR Flow control is disabled.
1 ABR Flow control is enabled.
13–15
AAL
AAL type
000 AAL0—Reassembly with no adaptation layer
001 AAL1—ATM adaptation layer 1 protocol
010 AAL5—ATM adaptation layer 5 protocol
All others reserved.
0x04
0x08
—
—
TxDBPTR Tx data buffer pointer. Holds the real address of the current position in the Tx buffer.
TBDCNT Transmit BD count. Counts the remaining data to transmit in the current transmit buffer.
Its initial value is loaded from the data length field of the TxBD when a new buffer is
open; its value is subtracted for any transmitted cell associated with this channel.
0x0A
0x0C
—
0–7
8–15
—
TBD_OffSe Transmit BD offset. Holds offset from TBD_BASE of the current BD. Should be cleared
t
initially.
Rate
Rate remainder. Used by the APC to hold the rate remainder after adding the pace
Reminder fraction to the additive channel rate. Should be cleared initially.
PCR
Fraction
Peak cell rate fraction. Holds the peak cell rate fraction of this channel in units of 1/256
slot. If this is an ABR channel, this field is automatically updated by the CP.
0x0E
PCR
Peak cell rate. Holds the peak cell rate (in units of APC slots) permitted for this channel
according to the traffic contract. Note that for an ABR channel, the CP automatically
updates PCR to the ACR value.
0x10
0x16
0x18
—
—
—
—
Protocol-specific
APCLC
ATMCH
APC linked channel. Used by the CP. Initialize to 0 (null pointer).
ATM cell header. Holds the full (4-byte) ATM cell header of the current channel. The
transmitter appends ATMCH to the cell payload during transmission.
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ATM Controller and AAL0, AAL1, and AAL5
Table 30-21. TCT Field Descriptions (continued)
Description
Offset Bits
Name
0x1C
0–1
2–7
—
Reserved, should be cleared.
PMT
Performance monitoring table. Points to one of the available 64 performance monitoring
tables. The starting address of the table is PMT_BASE+PMT × 32. Can be changed
on-the-fly.
8–15 TBD_BASE TxBD base. Points to the first BD in the channel’s TxBD table. The 8 most-significant bits
of the address are taken from BD_BASE_EXT in the parameter RAM. The four
0x1E 0–11
least-significant bits of the address are taken as zero.
12
BNM
STPT
IMK
Buffer-not-ready interrupt mask. Can be changed on-the-fly.
0 The transmit buffer-not-ready event of this channel is masked. (TBNR event is not
sent to the interrupt queue.)
1 The buffer-not-ready event of this channel is enabled.
13
Stop transmit. Should be cleared initially. When the host sets this bit, the CP deactivates
this channel and clears TCT[VCON] when the channel is next encountered in the APC
scheduling table. Note that for AAL5 if STPT is set and frame transmission is already
started (TCT[INF]=1), an abort indication will be sent (last cell with zero length field).
0x1E
14
15
Interrupt mask. Can be changed on-the-fly.
0 The transmit buffer event of this channel is masked. (TXB event is not sent to the
interrupt queue.)
1 The transmit buffer event of this channel is enabled.
PM
Performance monitoring. Can be changed on-the-fly.
0 No performance monitoring for this VC.
1 Performance is monitored for this VC. When a cell is sent for this VC, the performance
monitoring table indicated in PMT field is updated.
30.10.2.3.1 AAL5 Protocol-Specific TCT
Figure 30-31 shows the AAL5 protocol-specific TCT.
0
15
Offset + 0x10
Tx CRC
Offset + 0x12
Offset + 0x14
Total Message Length
Figure 30-31. AAL5 Protocol-Specific TCT
Table 30-22 describes AAL5 protocol-specific TCT fields.
Table 30-22. AAL5-Specific TCT Field Descriptions
Offset
Name
Description
0x10
0x14
Tx CRC
CRC32 temporary result.
Total Message Length
This field is used by the CP.
30.10.2.3.2 AAL1 Protocol-Specific TCT
Figure 30-32 shows the AAL1 protocol-specific TCT.
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ATM Controller and AAL0, AAL1, and AAL5
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Offset + 0x10
Offset + 0x12
Offset + 0x14
—
Valid Octet Size (VOS)
PFM SRT SPF STF
Block Size
—
SN
SRTS_DEV
SRTS_TMP
Structured Pointer (SP)
Figure 30-32. AAL1 Protocol-Specific TCT
Table 30-23 describes AAL1 protocol-specific TCT fields.
Table 30-23. AAL1 Protocol-Specific TCT Field Descriptions
Offset Bits
Name
Description
0x10
0-1
—
Reserved, should be cleared.
2–7
VOS
Valid octet size. Partially filled cell mode only. Specifies the number of valid octets from
the beginning of the AAL1 user data field. For unstructured service, values 1-47 are
valid; for structured service, values 1-46 are valid.
8
9
PFM
SRT
Partially filled mode.
0 Partially filled cells mode is not used.
1 Partially filled cells mode is used. The transmitter copies only valid octets from the
buffer to the AAL1 cell. The size of the valid octets from the beginning of the AAL1
user data field is specified in the VOS (valid octet size) field.
Synchronous residual time stamp. Unstructured format only. The PowerQUICC II
supports SRTS generation using external logic. If this mode is enabled, the
PowerQUICC II reads the SRTS from external logic and inserts it into four cells for which
SN = 1, 3, 5, or 7. The PowerQUICC II reads the new SRTS from external logic every
eight cells. (See Section 30.15, “SRTS Generation and Clock Recovery Using External
0 SRTS mode is not used.
1 SRTS mode is used.
10
11
SPF
STF
Structured pointer flag. Indicates that a structured pointer has been inserted in the
current block. The user should initialize this field to zero. Used by the CP only.
Structured format
0 Unstructured format is used.
1 Structured format is used.
12
—
Reserved, should be cleared.
13–15
SN
Sequence number field. Used by the CP to check the incoming cells SN. Should be
cleared initially.
0x12
0x14
0–3 SRTS_DEV Used to select a SRTS device. The SRTS device address is
SRTS_BASE[0–27]+SRTS_DEV[28:31]. SRTS_BASE is taken from the parameter
RAM and is 16-byte aligned.
4–15 Block Size Used only in structured format. Specifies the structured block size (Block Size
= 0xFFF = 4 Kbytes maximum).
0–3 SRTS_TMP Before a cell with SN = 1 is sent, the CP reads the SRTS code from external SRTS logic,
writes it to SRTS_TMP, and then inserts SRTS_TMP into the next four cells with an odd
SN.
4–15
SP
Structured pointer. Used by the CP to calculate the structured pointer. Should be
cleared initially. Structured format only.
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ATM Controller and AAL0, AAL1, and AAL5
30.10.2.3.3 AAL0 Protocol-Specific TCT
Figure 30-33 shows the AAL0 protocol-specific TCT.
0
7
8
9
10
11
12
15
Offset + 0x10
Offset + 0x12
Offset + 0x14
—
0
CR10
—
ACHC
—
—
Figure 30-33. AAL0 Protocol-Specific TCT
Table 30-24 describes AAL0 protocol-specific TCT fields.
Table 30-24. AAL0-Specific TCT Field Descriptions
Offset
Bits
Name
Description
0x10
0–7
8
—
0
Reserved, should be cleared.
Must be 0.
9
CR10 CRC-10
0 CRC10 insertion is disabled.
1 CRC10 insertion is enabled.
10
11
—
Reserved, should be cleared.
ACHC ATM cell header change
0 Normal operation ATM cell header is taken from AAL0 buffer.
1 VPI/VCI (28 bits) are taken from TCT.
12–15
—
—
—
Reserved, should be cleared.
Reserved, should be cleared.
0x12–0x14
30.10.2.3.4 AAL1 CES Protocol-Specific TCT
30.10.2.3.5 AAL2 Protocol-Specific TCT
30.10.2.3.6 VBR Protocol-Specific TCTE
Figure 30-34 shows the VBR protocol-specific TCTE.
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ATM Controller and AAL0, AAL1, and AAL5
0
1
7
8
15
Offset + 0x00
Offset + 0x02
Offset + 0x04
Offset + 0x06
Offset + 0x08
Offset + 0x0A
SCR
Burst Tolerance (BT)
Out of Buffer Rate (OOBR)
Sustain Rate Remainder (SRR)
SCR Fraction (SCRF)
Sustain Rate (SR)
Offset + 0x0C VBR2
Offset + 0x0E-1E
—
—
Figure 30-34. Transmit Connection Table Extension (TCTE)—VBR Protocol-Specific
Table 30-25 describes VBR protocol-specific TCTE fields.
Table 30-25. VBR-Specific TCTE Field Descriptions
Offset
Bits
Name
Description
0x00
—
SCR Sustain cell rate. Holds the sustain cell rate (in slots) permitted for this channel according
to the traffic contract. To pace the channel’s sustain cell rate, the APC performs a
continuous-state leaky bucket algorithm (GCRA).
0x02
—
BT
Burst tolerance. Holds the burst tolerance permitted for this channel according to the traffic
contract. The relationship between the BT and the maximum burst size (MBS) is
BT=(MBS-2) × (SCR-PCR) + SCR.
0x04
0x06
—
OOBR Out-of-buffer rate. In out of buffer state (when the transmitter tries to open TxBD whose R
bit is not set) the APC reschedules the current channel according to OOBR rate.
0–7
SRR Sustain rate remainder. Holds the sustain rate remainder after adding the pace fraction
field to the additive channel sustain rate. Used by the APC to calculate the channel GCRA
(leaky bucket) state. Initialized to 0.
8–15
—
SCRF Holds the sustain cell rate fraction of this channel in units of 1/256 slot.
0x08
0x0C
SR
Sustain rate. Used by the APC to hold the sustain rate after adding the pace field to the
additive channel sustain rate. Used by the APC to calculate the channel GCRA (leaky
bucket) state.
0
VBR2 VBR type
0 Regular VBR. CLP=0+1 cells are rescheduled by PCR or SCR according to the GCRA
state.
1 VBR Type 2. CLP=0 cells are rescheduled by PCR or SCR according to the GCRA state.
CLP=1 cells are rescheduled by PCR.
1–15
—
—
—
Reserved, should be cleared.
Reserved, should be cleared.
0x0E–
0x1E
30.10.2.3.7 UBR+ Protocol-Specific TCTE
Figure 30-35 shows the UBR+ protocol-specific TCTE.
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ATM Controller and AAL0, AAL1, and AAL5
0
7
8
15
Offset + 0x00
Offset + 0x02
MCR
—
MCR Fraction (MCRF)
Offset + 0x04
Maximum Delay Allowed (MDA)
—
Offset + 0x06–0x1E
Figure 30-35. UBR+ Protocol-Specific TCTE
Table 30-26 describes UBR+ protocol-specific TCTE fields.
Table 30-26. UBR+ Protocol-Specific TCTE Field Descriptions
Offset
Bits
Name Description
0x00
0x02
—
MCR Minimum cell rate for this channel. MCR is in units of APC time slots.
Reserved, should be cleared.
0–7
—
8–15 MCRF Minimum cell rate fraction. Holds the minimum cell rate fraction of this channel in units of
1/256 slot.
0x04
—
MDA Maximum delay allowed. The maximum time-slot service delay allowed for this priority level
before the APC reduces the scheduling rate from PCR to MCR.
0x06–
0x1E
—
—
Reserved, should be cleared.
30.10.2.3.8 ABR Protocol-Specific TCTE
Figure 30-36 shows the ABR protocol-specific TCTE.
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ATM Controller and AAL0, AAL1, and AAL5
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Offset + 0x00
Offset + 0x02
Offset + 0x04
ER-TA
CCR-TA
MCR-TA
CP-TA
MCR
Offset + 0x06 TUAR
Offset + 0x08
—
CI-TA NI-TA
—
—
CI-VC
—
Offset + 0x0A
UNACK
ACR
Offset + 0x0C
Offset + 0x0E ACRC
Offset + 0x10
—
RM Cell Time Stamp (RCTS)
Offset + 0x12
Offset + 0x14 FRST
Offset + 0x16
—
CDF
COUNT
ICR
Offset + 0x18
CRM
ADTF
ER
Offset + 0x1A
Offset + 0x1C
Offset + 0x1E
ER-BRM
Figure 30-36. ABR Protocol-Specific TCTE
Table 30-27 describes ABR-specific TCTE fields.
Table 30-27. ABR-Specific TCTE Field Descriptions
Offset Bits
Name
Description
0x00
0x02
0x04
0x06
—
—
—
0
ER-TA Explicit rate–turn-around cell. Holds the ER of the last received F-RM cell. If another F-RM
cell arrives before the previous F-RM cell was turned around, this field is overwritten by the
new RM cell’s ER.
CCR-TA Current cell rate–turn-around cell. Holds the CCR of the last received F-RM cell. If another
F-RM cell arrives before the previous F-RM cell was turned around, this field is overwritten
by the new RM cell’s CCR.
MCR-TA Minimum cell rate–turn-around cell. Holds the MCR of the last received F-RM cell. If
another F-RM cell arrives before the previous F-RM cell is turned around, this field is
overwritten by the new RM cell’s MCR.
TUAR Turn-around flag. The CP sets TUAR to indicate that a new F-RM cell was received, which
causes the transmitter to send a B-RM cell whenever the ABR flow control permits. Should
be cleared initially.
1
2
—
Reserved, should be cleared.
CI-TA
Congestion indication–turn-around cell. Holds the CI of the last received F-RM cell. If
another F-RM cell arrives before the previous F-RM cell was turned around, CI-TA is
overwritten by the new RM cell’s CI.
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ATM Controller and AAL0, AAL1, and AAL5
Table 30-27. ABR-Specific TCTE Field Descriptions (continued)
Offset Bits
Name
Description
3
NI-TA
No increase–turn-around cell. Holds the NI of the last received F-RM cell. If another F-RM
cell arrives before the previous one was turned around, NI-TA is overwritten by the new RM
cell’s NI.
4–6
7
—
Reserved, should be cleared.
CP-TA Cell loss priority–turn-around cell. Holds the CLP of the last received F-RM cell. If another
F-RM cell arrives before the previous one was turned around, CP-TA is overwritten by the
new RM cell’s CLP.
8–9
10
—
Reserved, should be cleared.
CI-VC Congestion indication -VC. Holds the EFCI (explicit forward congestion indication) of the
last user data cell. The CI bit of the turned around RM cell is ORed with the CI-VC. Should
be cleared initially.
11–15
—
Reserved, should be cleared.
0x08
0x0A
0x0C
0x0E
—
—
—
MCR
Minimum cell rate Holds the minimum number of cells/sec of the current ABR channel.
Uses the ATMF TM 4.0 floating-point format.
UNACK Used by the CP to count F-RM cells sent in an absence of received B-RM cells. Should be
cleared initially.
ACR
Allowed cell rate The cells per second allowed for the current ABR channel. Uses the ATMF
TM 4.0 floating-point format. Initialize with ICR.
0
1–15
—
ACRC ACR change. Indicates a change in ACR. Initialize to one.
Reserved, should be cleared.
—
0x10
0x14
RCTS RM cell time stamp. Used exclusively by the CP. Initialize to zero.
0
FRST First turn. Used exclusively by the CP. Indicates the first turn of a backward RM cell, which
has priority over a data cell. Initialized to 0.
1–3
4–7
—
Reserved, should be cleared.
CDF
Cutoff decrease factor. Controls the decrease in the ACR associated with missing B-RM
cells feedback. CDF represents a negative exponent of two, that is, the cutoff decrease
-CDF
factor = 2
. The cutoff decrease factor ranges from 1/64 (CDF=0b0110) to 1
(CDF=0b0000). All other CDF values falling outside this range are invalid.
8–15 COUNT Count. Used only by the CP. Holds the number of cells sent since the last forward RM cell.
Initialize with Nrm (in the parameter RAM).
0x16
0x18
0x1A
—
—
—
ICR
Initial cell rate. The number of cells per second of the current ABR channel. The channel’s
ACR is initialized with ICR. ICR uses the ATMF TM 4.0 floating-point format.
CRM
Missing RM cells count. Limits the number of forward RM cells that may be sent in the
absence of received backward RM cell. The CRM is in units of cells.
ADTF ADTF–ACR decrease time factor. The ADTF period is 500 ms as defined in the TM 4.0.
The ADTF value is defined by the system clock and the time stamp timer prescaler; see
Section 14.3.8, “RISC Time-Stamp Control Register (RTSCR).” For a time stamp prescaler
of 1 µs, ADTF should be programmed to 500m/(1µs × 1024)= 488.
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Table 30-27. ABR-Specific TCTE Field Descriptions (continued)
Offset Bits
Name
Description
0x1C
—
ER
Explicit rate. Holds the explicit rate value (in cells/sec) of the current ABR channel. ER is
copied to the F-RM cell ER field. The user usually initializes this field to PCR. ER uses the
ATMF TM 4.0 floating-point format.
0x1E
—
ER-BRM Explicit rate-backward RM cell. Holds the maximum explicit rate value (in cells/sec) allowed
for B-RM cells. The ER-TA field which is inserted to each B-RM cell is limited by this value.
ER-BRM uses the ATMF TM 4.0 floating-point format.
30.10.3 OAM Performance Monitoring Tables
The OAM performance monitoring tables include performance monitoring block test parameters, as
shown in Figure 30-37. Each block test needs a 32-byte performance monitoring table in the dual-port
RAM. In the connection’s RCT and TCT, the user allocates an OAM performance table to a VCC or VPC.
address of the tables. The starting address of each PM table is given by PMT_BASE + RCT/TCT[PMT]
× 32.
0
1
2
4
5
7
8
15
Offset + 0x00 FMCE TSTE
Offset + 0x02
Offset + 0x04
Offset + 0x06
Offset + 0x08
Offset + 0x0A
Offset + 0x0C
Offset + 0x0E
Offset + 0x10
Offset + 0x12
Offset + 0x14
Offset + 0x16
Offset + 0x18
Offset + 0x1A
Offset + 0x1C
Offset + 0x1E
—
BLCKSIZE
—
TX Cell Count (TCC)
TUC1
TUC0
BEDC0+1-Tx
BEDC0+1-RX
TRCC1
TRCC0
—
SN-FMC
—
PM CELL HEADER (VPI,VCI,PTI,CLP)
—
Figure 30-37. OAM Performance Monitoring Table
Table 30-28 describes fields in the performance monitoring table.
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ATM Controller and AAL0, AAL1, and AAL5
Table 30-28. OAM—Performance Monitoring Table Field Descriptions
Offset Bits
Name
Description
0x00
0
1
FMCE
TSTE
Enables FMC transmission. Initialize to 1.
FMC time stamp enable
0 The time stamp field of the FMC is coded with all 1’s.
1 The value of the time stamp timer is inserted into the time stamp field of the FMC.
2–4
—
Reserved, should be cleared.
5–15
BLCKSIZE Performance monitoring block size ranging from 1 to 2,047 cells.
0x02 0–4
5–15
—
Reserved, should be cleared.
TCC
TUC1
TX cell count. Used by the CP to count data cells sent. Initialize to zero.
0x04
0x06
0x08
0x0A
0x0C
0x0E
—
—
—
—
—
—
Total user cell 1. Count of CLP = 1 user cells (modulo 65,536) sent. Should be cleared
initially.
TUC0
Total user cell 0. Count of CLP = 0 user cells (modulo 65,536) sent. Should be cleared
initially.
BEDC0+1-Tx Block error detection code 0+1–transmitted cells. Even parity over the payload of the
block of user cells sent since the last FMC. Should be cleared initially.
BEDC0+1-RX Block error detection code 0+1–received cells. Even parity over the payload of the
block of user cells received since the last FMC. Should be cleared initially.
TRCC1
TRCC0
Total received cell 1. Count of CLP = 1 user cells (modulo 65,536) received. Should
be cleared initially.
Total received cell 0. Count of CLP = 0 user cells (modulo 65,536) received. Should
be cleared initially.
0x10 0–7
8–15
—
SN-FMC
—
Reserved, should be cleared.
Sequence number of the last FMC sent. Should be cleared initially.
Reserved, should be cleared.
0x12
0x14
—
—
PMCH
PM cell header. Holds the ATM cell header of the FMC, BRC to be inserted by the CP
into the Tx cell flow.
0x18–
0x1E
—
—
Reserved, should be cleared.
30.10.4 APC Data Structure
The APC data structure consists of three elements: the APC parameter tables for the PHY devices, the APC
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APC Parameter Tables
APC Priority Table
APC Scheduling Tables
Priority 1
Priority 2
Priority 3
Priority 4
Priority 5
Priority 6
Priority 7
Priority 8
Priority 1 Scheduling Table
Priority 2 Scheduling Table
Priority 3 Scheduling Table
Priority 4 Scheduling Table
Priority 5 Scheduling Table
Priority 6 Scheduling Table
Priority 7 Scheduling Table
Priority 8 Scheduling Table
Parameter Table
PHY #0
Parameter Table
PHY #1
Parameter Table
PHY #31
Note: The shaded areas represent the active structures for an example implementation of PHY #0 with two
priorities. (The unshaded areas and dashed arrows represent unused structures.)
Figure 30-38. ATM Pace Control Data Structure
30.10.4.1 APC Parameter Tables
Each PHY’s APC parameter table, shown in Table 30-29, holds parameters that define the priority table
location, the number of priority levels, and other APC parameters. The table resides in the dual-port RAM.
of PHY#0’s parameter table.
For multiple PHYs, the table structure is duplicated. Each table resides in 32 bytes of memory. The starting
address of each APC parameter table is given by APCP_BASE + PHY# × 32. Note however that in slave
mode with multiple PHYs, the parameter table always resides at APCP_BASE regardless of the PHY
address.
Table 30-29. APC Parameter Table
1
Offset
Name
Width
Description
0x00
APCL_FIRST
Hword Address of first entry in the priority table. Must be 8-byte aligned.
User-initialized.
0x02
0x04
0x06
APCL_LAST
APCL_PTR
CPS
Hword Address of last entry in the priority table. Must be 8-byte aligned. User-initialized
as APCL_FIRST + 8 x (number_of_priorities - 1).
Hword Address of current priority entry used by the CP. User-initialized with
APCL_FIRST.
Byte Cells per slot. Determines the number of cells sent per APC slot. See
0xFF = 255 cells.)
Note: If ABR is used, CPS must be a power of two.
0x07
0x08
CPS_CNT
Byte Cells sent per APC slot counter. User-initialized to CPS; used by the CP.
MAX_ITERATIO Byte Max iteration allowed. Number of scan iterations allowed in the APC.
N
User-defined. This parameter limits the time spent in a single APC routine,
thereby avoiding excessive APC latency.
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ATM Controller and AAL0, AAL1, and AAL5
Table 30-29. APC Parameter Table (continued)
Width Description
1
Offset
Name
0x09
CPS_ABR
Byte ABR only. Cells per slot represented as a power of two. User-defined. (For
example, if CPS is 1, CPS_ABR = 0x00; if CPS is 8, CPS_ABR = 0x03.)
0x0A
LINE_RATE_AB Hword ABR only. The PHY line rate in cells/sec, represented in TM 4.0 floating-point
R
format. User-defined.
0xC
REAL_TSTP
APC_STATE
Word Real-time stamp pointer used internally by the APC. Should be cleared initially.
Word Used internally by the APC. Should be cleared initially.
0x10
1
Offset values are to APCP_BASE+PHY# × 32. However, in slave mode, the offset is from APCP_BASE regardless of
the PHY address.
30.10.4.2 APC Priority Table
Each PHY’s APC priority table holds pointers to the APC scheduling table of each priority level. It resides
in the dual-port RAM. The priority table can hold up to eight priority levels. Table 30-30 shows the
structure of a priority table entry.
Table 30-30. APC Priority Table Entry
Offset
Name
Width
Description
0x00 APC_LEVi_BASE Hword APC level i base address. Pointer to the first slot in the APC scheduling table for
level i. Should be half-word aligned. User-defined.
0x02
APC_LEVi_END Hword APC level i end address. Pointer to the last slot in the APC scheduling table for
level i. Should be half-word aligned. User-defined.
0x04 APC_LEVi_RPTR Hword APC level i real-time/service pointers. APC table pointers used internally by the
APC. Initialize both pointers to APC_LEVi_BASE.
0x06 APC_LEVi_SPTR Hword
30.10.4.3 APC Scheduling Tables
The APC uses APC scheduling tables (one table for each priority level) to schedule channel transmission.
A scheduling table is divided into time slots, as shown in Figure 30-39. Each slot is a half-word entry. Note
that the APC scheduling tables should be cleared before the APC unit is enabled.
APC_LEVi_BASE
Control
Slot
slot 0
slot 1
slot N
Half Word Entry
APC_LEVi_END
Figure 30-39. The APC Scheduling Table Structure
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ATM Controller and AAL0, AAL1, and AAL5
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Field TCTE
000_0000_0000_0000
Figure 30-40. Control Slot
Table 30-31 describes control slot fields.
Table 30-31. Control Slot Field Description
Bits
Name
Description
0
TCTE Used for external channels only.
0 Channels in this scheduling table do not use external TCTE. (No external VBR, ABR, UBR+
channels)
1 Channels in this scheduling table use external TCTE. (External VBR, ABR, UBR+ channels)
1–15
—
Reserved, should be cleared.
30.10.5 ATM Controller Buffer Descriptors (BDs)
Each ATM channel has separate receive and transmit BD tables. The number of BDs per channel and the
size of the buffers is user-defined. The last BD in each table holds a wrap indication. Each BD in the TxBD
table points to a buffer to send. At the receive side, the user can choose one of two modes:
•
Static buffer allocation. In this mode, the user allocates dedicated buffers to each ATM channel
(that is, the user associates each BD with one buffer). Static buffer allocation is useful when the
connection rate is known and constant and when data must be reassembled in a particular memory
space.
•
Global buffer allocation. Available for AAL5 only. In this mode, buffer allocation is dynamic. The
user allocates receive buffers and places them in global buffer pools. When the CP needs a receive
buffer, it first fetches a buffer pointer from one of the global buffer pools and writes the pointer to
the current RxBD. Global buffer allocation is optimized for allocating memory among many ATM
channels with variable data rates, such as ABR channels.
30.10.5.1 Transmit Buffer Operation
The user prepares a table of BDs pointing to the buffers to be sent. The address of the first BD is put in the
channel’s TCT[TBD_BASE]. The transmit process starts when the core issues an ATM TRANSMIT
command. The CP reads the first TxBD in the table and sends its associated buffer. When the current buffer
is finished, the CP increments TBD_Offset, which holds the offset from TBD_BASE to the current BD. It
then reads the next BD in the table. If the BD is ready (TxBD[R] = 1), the CP continues sending. If the
current BD is not ready, the CP polls the ready bit at the channel rate unless TCT[AVCF] = 1, in which
case the CP removes the channel from the APC and clears TCT[VCON]. The core must issue a new ATM
TRANSMIT command to restart transmission.
Figure 30-41 shows the ready bit in the TxBD tables and their associated buffers for two example ATM
channels.
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ATM Controller and AAL0, AAL1, and AAL5
Ch1 TxBD Table
Tx Buffer 1 of Channel 1
Tx Buffer 2 of Channel 1
Tx Buffer 3 of Channel 1
Tx Buffer 4 of Channel 1
Tx Buffer 5 of Channel 1
TBD_BASE
TBD_Offset
0
1
1
0
0
BD 1
BD 2
BD 3
BD 4
BD 5
Ch1 TxBD Table
Pointers in the TCT
Ch4 TxBD Table
Tx Buffer 1 of Channel 4
Tx Buffer 2 of Channel 4
Tx Buffer 3 of Channel 4
Tx Buffer 4 of Channel 4
Tx Buffer 5 of Channel 4
Tx Buffer 6 of Channel 4
Tx Buffer 7 of Channel 4
TBD_BASE
TBD_Offset
1
0
0
0
0
1
1
BD 1
BD 2
BD 3
BD 4
BD 5
BD 6
BD 7
Ch4 TxBD Table
Pointers in the TCT
Note: The shaded buffers are ready to be sent; unshaded buffers are waiting to be prepared.
Figure 30-41. Transmit Buffers and BD Table Example
30.10.5.2 Receive Buffer Operation
For AAL5 channels, the user should choose to operate in static buffer allocation or in global buffer
allocation by writing to RCT[BUFM]. AAL1 CES and AAL0 channels must use static buffer allocation.
30.10.5.2.1 Static Buffer Allocation
The user prepares a table of BDs pointing to the receive buffers. The address of the first BD is put in the
channel’s RCT[RBD_BASE]. When an ATM cell arrives, the CP opens the first BD in the table and starts
filling its associated buffer with received data. When the current buffer is full, the CP increments
RBD_Offset, which is the offset to the current BD from RBD_BASE, and reads the next BD in the table.
If the BD is empty (RxBD[E] = 1), the CP continues receiving. If the BD is not empty, a busy condition
has occurred and a busy interrupt is sent to the event queue.
Figure 30-42 shows the empty bit in the RxBD tables and their associated buffers for two example ATM
channels.
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ATM Controller and AAL0, AAL1, and AAL5
Ch1 RxBD Table
Rx Buffer 1 of Channel 1
Rx Buffer 2 of Channel 1
Rx Buffer 3 of Channel 1
Rx Buffer 4 of Channel 1
Rx Buffer 5 of Channel 1
RBD_BASE
0
1
1
0
0
BD 1
BD 2
BD 3
BD 4
BD 5
Ch1 RxBD Table
Pointers in the RCT
RBD_Offset
Ch4 RxBD Table
Rx Buffer 1 of Channel 4
Rx Buffer 2 of Channel 4
Rx Buffer 3 of Channel 4
Rx Buffer 4 of Channel 4
Rx Buffer 5 of Channel 4
Rx Buffer 6 of Channel 4
Rx Buffer 7 of Channel 4
RBD_BASE
RBD_Offset
1
0
0
0
0
1
1
BD 1
BD 2
BD 3
BD 4
BD 5
BD 6
BD 7
Ch4 RxBD Table
Pointers in the RCT
Note: The shaded buffers are empty; unshaded buffers are waiting to be processed.
Figure 30-42. Receive Static Buffer Allocation Example
30.10.5.2.2 Global Buffer Allocation
The user prepares a table of BDs without assigning buffers to them (no buffer pointers). The address of the
first BD is put into the channel’s RCT[RBD_BASE]. The user also prepares sets of free buffers (of size
RCT[MRBLR]) in up to four free buffer pools (chosen in RCT[BPOOL]); see Section 30.10.5.2.3, “Free
When an ATM cell arrives, the CP opens the first BD in the table, fetches a buffer pointer from the free
buffer pool associated with this channel, and writes the pointer to RxBD[RXDBPTR], the receive data
buffer pointer field in the BD. When the current buffer is full, the CP increments RBD_Offset, which is
the offset from the RBD_BASE to the current BD, and reads the next BD in the table. If the BD is empty
(RxBD[E] = 1), the CP fetches another buffer pointer from the free buffer pool and reception continues. If
the BD is not empty, a busy condition occurs and a busy interrupt is sent to the event queue specifying the
ATM channel code. As software then processes each full buffer (RxBD[E] = 0), it sets RxBD[E] and copies
the buffer pointer back to the free buffer pool.
Figure 30-43 shows two ATM channels’ BD tables and one free buffer pool. Both channels are associated
with free buffer pool 1. The CP allocates the first two buffers of buffer pool 1 to channel 1 and the third to
channel 4.
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ATM Controller and AAL0, AAL1, and AAL5
Ch1 RxBD Table
RBD_BASE
RBD_Offset
0
1
1
1
1
BD 1
BD 2
BD 3
BD 4
BD 5
Buffer 1 of FBP1
Buffer 2 of FBP1
Free Buffer Pool 1
FBP1_BASE
FBP1_PTR
Pointer 1
Pointer 2
Pointer 3
Pointer 4
Pointer 5
Pointer 6
Ch4 RxBD Table
Buffer 4
Buffer 5
Buffer 6
RBD_BASE,
RBD_Offset
1
1
1
1
BD 1
BD 2
BD 3
BD 4
Buffer 3 of FBP1
Notes: Buffers 2 and 3 are receiving data. After buffer 1 is processed, it can be returned to the pool.
Figure 30-43. Receive Global Buffer Allocation Example
30.10.5.2.3 Free Buffer Pools
As Figure 30-44 shows, when a buffer pointer is fetched from a pool, the CP clears the entry’s valid bit
and increments FBP#_PTR. After the CP uses an entry with the wrap bit set (W = 1), it returns to the first
entry in the pool. After a buffer pointer is returned to the pool, the user should set V to indicate that the
entry is valid. If the CP tries to read an invalid entry (V = 0), the buffer pool is out of free buffers; the
global-buffer-pool-busy event is then set in FCCE[GBPB] and a busy interrupt is sent to the interrupt
queue specifying the ATM channel code associated with the pool.
Word
FBP#_BASE
Software (Core) Pointer
FBP#_PTR
V = 1
V = 1
V = 1
V = 0
V = 0
V = 0
V = 1
V = 1
V = 1
W = 0
W = 0
W = 0
W = 0
W = 0
W = 0
W = 0
W = 0
W = 1
Buffer Pointer
Buffer Pointer
Buffer Pointer
Invalid
Invalid
Invalid
Buffer Pointer
Buffer Pointer
Buffer Pointer
Figure 30-44. Free Buffer Pool Structure
Figure 30-45 describes the structure of a free buffer pool entry.
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ATM Controller and AAL0, AAL1, and AAL5
0
1
2
3
4
15
Offset + 0x00
Offset + 0x02
V
—
W
I
Buffer Pointer (BP)
Buffer Pointer (BP)
Figure 30-45. Free Buffer Pool Entry
Table 30-32 describes free buffer pool entry fields.
Table 30-32. Free Buffer Pool Entry Field Descriptions
Offset
Bits
Name
V
Description
0x00
0
Valid buffer entry.
0 This free buffer pool entry contains an invalid buffer pointer.
1 This free buffer pool entry contains a valid buffer pointer.
1
2
—
Reserved, should be cleared.
W
Wrap bit. When set, this bit indicates the last entry in the circular table. During initialization,
the host must clear all W bits in the table except the last one, which must be set.
3
I
Red-line interrupt. Can be used to indicate that the free buffer pool has reached a red line
and additional buffers should be added to this pool to avoid a busy condition.
0 No interrupt is generated.
1 A red-line interrupt is generated when this buffer is fetched from the free buffer pool.
4–15
0–15
BP
Buffer pointer. Points to the start address of the receive buffer. The four msbs are control
bits, and the four msbs of the real buffer pointer are taken from the four msbs of the
parameter FBP_ENTRY_EXT in the free buffer pool parameter table.
0x02
30.10.5.2.4 Free Buffer Pool Parameter Tables
FBT_BASE in the parameter RAM points to the base address of these tables. Each of the four free buffer
pools has its own parameter table with a starting address given by FBT_BASE+ RCT[BPOOL] × 16.
Table 30-33. Free Buffer Pool Parameter Table
Offset
Bits
Name
Description
1
0x00
—
FBP_BASE
Free buffer pool base. Holds the pointer to the first entry in the free buffer pool.
FBP_BASE should be word aligned. User-defined.
0x04
0x08
—
—
FBP_PTR
Free buffer pool pointer. Pointer to the current entry in the free buffer pool.
Initialize to FBP_BASE.
FBP_ENTRY_EXT Free buffer pool entry extension. FBP_ENTRY_EXT[0–3] holds the four left bits
of FBP_ENTRY. FBP_ENTRY_EXT[4–15] should be cleared. User-defined.
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ATM Controller and AAL0, AAL1, and AAL5
Table 30-33. Free Buffer Pool Parameter Table (continued)
Offset
Bits
Name
BUSY
Description
1
0x0A
0
The CP sets this bit when it tries to fetch buffer pointer with V bit clear.
FCCE[GBPB] is also set. Initialize to zero.
1
RLI
Red-line interrupt. Set by the CP when it fetches a buffer pointer with I = 1.
FCCE[GRLI] is also set. Initialize to zero.
2–7
8
—
Reserved, should be cleared.
EPD
Early packet discard.
0 Normal operation.
1 AAL5 frames in progress are received, but new AAL5 frames associated with
this pool are discarded. Can be used to implement EPD under core control.
9–15
—
—
Reserved, should be cleared.
0x0C
FBP_ENTRY
Free buffer pool entry. Initialize with the first entry of the free buffer pool. Note that
FBP_ENTRY must be reinitialized with the entry pointed to by FBP_PTR when a
busy state occurs to reenable free buffer pool processing.
1
Offset from FBT_BASE+RCT[BPOOL] × 16
30.10.5.3 ATM Controller Buffers
Table 30-34. Receive and Transmit Buffers
Receive
Transmit
Size Alignment
AAL
Size
Alignment
AAL5 Multiple of 48 octets (except last buffer in frame) Burst-aligned
(recommended)
Any
No
requirement
AAL1 At least 47 octets
Burst-aligned
(recommended)
≥ 47 octets No
requirement
AAL0 52-64 octets.
Burst-aligned
52–64
octets
No
requirement
30.10.5.4 AAL5 RxBD
Figure 30-46 shows the AAL5 RxBD.
0
1
2
3
4
L
5
F
6
7
8
9
10
11
12
13
14
15
Offset + 0x00
Offset + 0x02
Offset + 0x04
Offset + 0x06
E
—
W
I
CM
—
CLP CNG ABRT CPUU LNE CRE
Data Length (DL)
Rx Data Buffer Pointer (RXDBPTR)
Figure 30-46. AAL5 RxBD
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Table 30-35 describes AAL5 RxBD fields.
m
Table 30-35. AAL5 RxBD Field Descriptions
Offset
Bits
Name
E
Description
0x00
0
Empty.
0 The buffer associated with this RxBD is full or data reception was aborted due to an
error. The core can read or write any fields of this RxBD. The CP does not use this
BD again while E remains zero.
1 The buffer associated with this RxBD is empty or reception is in progress. This RxBD
and its receive buffer are controlled by the CP. Once E is set, the core should not
write any fields of this RxBD.
1
2
—
Reserved, should be cleared.
W
Wrap (final BD in table)
0 This is not the last BD in the RxBD table of the current channel.
1 This is the last BD in the RxBD table of this current channel. After this buffer has
been used, the CP receives incoming data into the first BD in the table. The number
of RxBDs in this table is programmable and is determined only by the W bit. The
current table cannot exceed 64 Kbytes.
3
4
I
Interrupt
0 No interrupt is generated after this buffer has been used.
1 An Rx buffer event is sent to the interrupt queue after the ATM controller uses this
buffer. FCCE[GINTx] is set in the event register when INT_CNT reaches the global
interrupt threshold.
L
Last in frame. Set by the ATM controller for the last buffer in a frame.
0 Buffer is not last in a frame.
1 Buffer is last in a frame. ATM controller writes frame length in DL and updates the
error flags.
5
6
F
First in frame. Set by the ATM controller for the first buffer in a frame.
0 The buffer is not the first in a frame.
1 The buffer is the first in a frame.
CM
Continuous mode
0 Normal operation.
1 The CP does not clear the empty bit after this BD is closed, allowing the associated
buffer to be overwritten automatically when the CP next accesses this BD.
7–9
10
—
Reserved, should be cleared.
CLP
Cell loss priority. At least one cell associated with the current message was received
with CLP = 1. May be set at the last buffer of the message.
11
CNG
Congestion indication. The last cell associated with the current message was received
with PTI middle bit set. CNG may be set at the last buffer of the message.
12
13
ABRT
CPUU
Abort message indication. The current message was received with Length field zero.
CPCS-UU+CPI indication. Set when the CPCS-UU+CPI field is non zero. CPUU may
be set at the last buffer of the message.
14
15
LNE
CRE
Rx length error. AAL5 CPCS-PDU length violation. May be set only for the last BD of
the frame if the pad length is greater than 47 or less than zero octets.
Rx CRC error. Indicates CRC32 error in the current AAL5 PDU. Set only for the last BD
of the frame.
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ATM Controller and AAL0, AAL1, and AAL5
Table 30-35. AAL5 RxBD Field Descriptions (continued)
Offset
Bits
Name
Description
0x02
—
DL
Data length. The number of octets written by the CP into this BD’s buffer. It is written
by the CP once the BD is closed. In the last BD of a frame, DL contains the total frame
length.
0x04
RXDBPTR Rx data buffer pointer. Points to the first location of the associated buffer; may reside
in internal or external memory. It is recommended that the pointer be burst-aligned.
30.10.5.5 AAL1 RxBD
Figure 30-47 shows the AAL1 RxBD.
0
1
2
3
4
5
6
7
8
9
10
11
—
12
13
14
15
Offset + 0x00
Offset + 0x02
Offset + 0x04
Offset + 0x06
E
—
W
I
SNE
—
CM
Data Length
Rx Data Buffer Pointer
Figure 30-47. AAL1 RxBD
Table 30-36 describes AAL1 RxBD fields.
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Table 30-36. AAL1 RxBD Field Descriptions
Description
Offset Bits
Name
E
0x00
0
Empty
0 The buffer associated with this RxBD is filled with received data or data reception was
aborted due to an error. The core can read or write any fields of this RxBD. The CP
cannot use this BD again while E = 0.
1 The buffer is not full. This RxBD and its associated receive buffer are owned by the
CP. Once E is set, the core should not write any fields of this RxBD.
1
2
—
Reserved, should be cleared.
W
Wrap (final BD in table)
0 This is not the last BD in the RxBD table of the current channel.
1 This is the last BD in the RxBD table of this current channel. After this buffer is used,
the CP receives incoming data into the first BD in the table. The number of RxBDs in
this table is programmable and is determined only by the W bit. The current table
overall space is constrained to 64 Kbytes.
3
4
I
Interrupt
0 No interrupt is generated after this buffer has been used.
1 An Rx buffer event is sent to the interrupt queue after the ATM controller uses this
buffer. FCCE[GINTx] is set when the INT_CNT reaches the global interrupt threshold.
SNE
Sequence number error. SNE is set when a sequence number error is detected in the
current AAL1 CES buffer.
5
6
—
Reserved, should be cleared.
CM
Continuous mode
0 Normal operation.
1 The empty bit (RxBD[E]) is not cleared by the CP after this BD is closed, allowing the
associated buffer to be overwritten automatically when the CP next accesses this BD.
7–15
—
—
Reserved, should be cleared.
0x02
0x04
DL
Data length. The number of octets the CP writes into the buffer once its BD is closed.
—
RXDBPTR Rx data buffer pointer. Points to the first location of the associated buffer; may reside in
either internal or external memory. It is recommended that the pointer be burst-aligned.
30.10.5.6 AAL0 RxBD
Figure 30-48 shows the AAL0 RxBD.
0
1
2
3
4
5
6
7
9
10
11
12
15
Offset + 0x00
Offset + 0x02
Offset + 0x04
Offset + 0x06
E
—
W
I
—
CM
—
CRE OAM
—
Data Length (DL)/Channel Code (CC)
Rx Data Buffer Pointer (RXDBPTR)
Figure 30-48. AAL0 RxBD
Table 30-37 describes AAL0 RxBD fields.
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Table 30-37. AAL0 RxBD Field Descriptions
Description
Offset Bits
Name
E
0x00
0
Empty
0 The buffer associated with this RxBD is filled with received data, or data reception was
aborted due to an error. The core can examine or write to any fields of this RxBD. The
CP does not use this BD again while E remains zero.
1 The Rx buffer is empty or reception is in progress. This RxBD and its associated
receive buffer are owned by the CP. Once E is set, the core should not write any fields
of this RxBD.
1
2
—
Reserved, should be cleared.
W
Wrap (final BD in table)
0 This is not the last BD in the RxBD table of the current channel.
1 This is the last BD in the RxBD table of the current channel. After this buffer has been
used, the CP will receive incoming data into the first BD in the table. The number of
RxBDs in this table is programmable and is determined only by the W bit. The current
table cannot exceed 64 Kbytes.
3
I
Interrupt
0 No interrupt is generated after this buffer has been used.
1 An Rx buffer event is sent to the interrupt queue after the ATM controller uses this
buffer. FCCE[GINTx] is set when the INT_CNT reaches the global interrupt threshold.
4–5
6
—
Reserved, should be cleared.
CM
Continuous mode
0 Normal operation.
1 The CP does not clear the E bit after this BD is closed, allowing the associated buffer
to be overwritten automatically when the CP next accesses this BD.
7–9
10
—
Reserved, should be cleared.
CRE
Rx CRC error. Indicates a CRC10 error in the current AAL0 buffer. The CRE bit is
considered an error only if the received cell had a CRC10 field in the cell payload.
11
OAM
Operation and maintenance cell. If OAM is set, the current AAL0 buffer contains an OAM
cell. This cell is associated with the channel indicated by the channel code field (CC
field).
12-15
—
—
Reserved, should be cleared.
0x02
0x04
DL/CC
Data length/channel code. If RxBD[OAM] is set, this field functions as CC; otherwise, it
is DL. Data length is the size in octets of this buffer (MRBLR value). Channel code
specifies the channel code associated with this OAM cell.
—
RXDBPTR Rx data buffer pointer. Points to the first location of the associated buffer; may reside in
either internal or external memory. This pointer must be burst-aligned.
30.10.5.7 AAL1 CES RxBD
30.10.5.8 AAL2 RxBD
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30.10.5.9 AAL5, AAL1 CES User-Defined Cell—RxBD Extension
NOTE
For AAL0, a complete cell, including the UDC header, is stored in the
buffer; the AAL0 BD size is always 8 bytes.
Offset + 0x08
Extra Cell Header.
Used to store the user-defined cell’s extra cell header. The extra cell header can be 1–12 bytes long.
Offset + 0x14
Reserved (12 bytes)
Figure 30-49. User-Defined Cell—RxBD Extension
30.10.5.10 AAL5 TxBDs
Figure 30-50 shows the AAL5 TxBD.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Offset + 0x00
Offset + 0x02
Offset + 0x04
Offset + 0x06
R
—
W
I
L
—
CM
—
CLP CNG
—
Data Length (DL)
Tx Data Buffer Pointer (TXDBPTR)
Figure 30-50. AAL5 TxBD
Table 30-38 describes AAL5 TxBD fields.
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ATM Controller and AAL0, AAL1, and AAL5
Table 30-38. AAL5 TxBD Field Descriptions
Description
Offset Bits
Name
R
0x00
0
Ready
0 The buffer associated with this BD is not ready for transmission. The user is free to
manipulate this BD or its associated buffer. The CP clears R after the buffer is sent or
after an error condition is encountered.
1 The user-prepared buffer has not been sent or is currently being sent. No fields of this
BD may be written by the user once R is set.
1
2
—
Reserved, should be cleared.
W
Wrap (final BD in table)
0 Not the last BD in the TxBD table.
1 Last BD in the TxBD table. After this buffer is used, the CP sends outgoing data from
the first BD in the table (the BD pointed to by the channel’s TCT[TBD_BASE]). The
number of TxBDs in this table is determined only by the W bit. The current table cannot
exceed 64 Kbytes.
3
4
I
Interrupt
0 No interrupt is generated after this buffer has been serviced.
1 A Tx Buffer event is sent to the interrupt queue after this buffer is serviced.
FCCE[GINTx] is set when the INT_CNT counter reaches the global interrupt
threshold.
L
Last in frame. Set by the user to indicate the last buffer in a frame.
0 Buffer is not last in a frame.
1 Buffer is last in a frame.
5
6
—
Reserved, should be cleared.
CM
Continuous mode
0 Normal operation.
1 The CP does not clear R after this BD is closed, allowing the associated buffer to be
retransmitted automatically when the CP next accesses this BD. However, the R bit is
cleared if an error occurs during transmission, regardless of CM.
7-9
10
—
Reserved, should be cleared.
CLP
The ATM cell header CLP bit of the cells associated with the current frame are ORed with
this field. This field is valid only in the first BD of the frame.
11
CNG
The ATM cell header CNG bit of the cells associated with the current frame are ORed
with this field. This field is valid only in the first BD of the frame.
12–15
—
—
Reserved, should be cleared.
0x02
0x04
DL
The number of octets the ATM controller should transmit from this BD’s buffer. It is not
modified by the CP. The value of DL should be greater than zero.
—
TXDBPTR Tx data buffer pointer. Points to the address of the associated buffer, which may or may
not be 8-byte-aligned. The buffer may reside in either internal or external memory. This
value is not modified by the CP.
30.10.5.11 AAL1 TxBDs
Figure 30-51 shows the AAL1 TxBD.
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ATM Controller and AAL0, AAL1, and AAL5
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Offset + 0x00
Offset + 0x02
Offset + 0x04
Offset + 0x06
R
—
W
I
—
CM
—
Data Length (DL)
Tx Data Buffer Pointer (TXDBPTR)
Figure 30-51. AAL1 TxBD
Table 30-39 describes AAL1 TxBD fields.
Table 30-39. AAL1 TxBD Field Descriptions
Offset Bits
Name
R
Description
0x00
0
Ready
0 The buffer associated with this BD is not ready for transmission. The user is free to
manipulate this BD or its associated buffer. The CP clears this bit after the buffer has
been sent or after an error condition is encountered.
1 The buffer prepared for transmission by the user has not been sent or is being sent.
No fields of this BD may be written by the user once R is set.
1
2
—
Reserved, should be cleared.
W
Wrap (final BD in table)
0 Not the last BD in the TxBD table.
1 Last BD in the TxBD table. After this buffer is used, the CP sends outgoing data from
the first BD in the table (the BD pointed to by the channel’s TCT[TBD_BASE]). The
number of TxBDs in this table is determined only by the W bit. The current table cannot
exceed 64 Kbytes.
3
I
Interrupt
0 No interrupt is generated after this buffer has been serviced.
1 A Tx buffer event is sent to the interrupt queue after this buffer is serviced.
FCCE[GINTx] is set when the INT_CNT counter reaches the global interrupt
threshold.
4–5
6
—
Reserved, should be cleared.
CM
Continuous mode
0 Normal operation.
1 The CP does not clear the ready bit after this BD is closed, allowing the associated
buffer to be retransmitted automatically when the CP next accesses this BD.
7–11
—
—
Reserved, should be cleared.
0x02
0x04
DL
The number of octets the ATM controller should transmit from this BD’s buffer. It is not
modified by the CP. The value of DL should be greater than zero.
—
TXDBPTR Tx data buffer pointer. Points to the address of the associated buffer. The buffer may
reside in either internal or external memory. This value is not modified by the CP.
30.10.5.12 AAL0 TxBDs
Figure 30-52 shows AAL0 TxBDs. Note that the data length field is calculated internally as 52 bytes, plus
the extra header length (defined in FPSMR[TEHS]) when in UDC mode.
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ATM Controller and AAL0, AAL1, and AAL5
0
1
2
3
4
5
6
7
10
11
12
15
Offset + 0x00
Offset + 0x02
Offset + 0x04
Offset + 0x06
R
—
W
I
—
CM
—
OAM
—
—
Tx Data Buffer Pointer (TXDBPTR)
Figure 30-52. AAL0 TxBDs
Table 30-40 describes AAL0 TxBD fields.
Table 30-40. AAL0 TxBD Field Descriptions
Offset Bits
Name
R
Description
0x00
0
Ready
0 The buffer is not ready for transmission. The user can manipulate this BD or its buffer.
The CP clears R after the buffer has been sent or after an error occurs.
1 The buffer that the user prepared for transmission has not been sent or is being sent.
No fields of this BD may be written by the user once R is set.
1
2
—
Reserved, should be cleared.
W
Wrap (final BD in table)
0 Not the last BD in the TxBD table.
1 Last BD in the TxBD table. After this buffer is used, the CP sends outgoing data from
the first BD in the table (the BD pointed to by the channel’s TCT[TBD_BASE]). The
number of TxBDs in this table is determined by the W bit. The current table is
constrained to 64 Kbytes.
3
I
Interrupt
0 No interrupt is generated after this buffer has been serviced.
1 A Tx buffer event is sent to the interrupt queue after this buffer is serviced.
FCCE[GINTx] is set when the INT_CNT counter reaches the global interrupt
threshold.
4–5
6
—
Reserved, should be cleared.
CM
Continuous mode
0 Normal operation.
1 The CP does not clear the ready bit after this BD is closed, allowing the associated
buffer to be retransmitted automatically when the CP next accesses this BD.
7–10
11
—
Reserved, should be cleared.
OAM
Operation and maintenance cell. If OAM is set, the current AAL0 buffer contains an F5
or F4 OAM cell. Performance monitoring calculations are not done on OAM cells.
11–15
—
—
—
Reserved, should be cleared.
Reserved, should be cleared.
0x02
0x04
—
TXDBPTR Tx data buffer pointer. Points to the address of the associated buffer, which may or may
not be 8-byte-aligned. The buffer may reside in either internal or external memory. This
value is not modified by the CP.
30.10.5.13 AAL1 CES TxBDs
Refer to Section 31.12.2, “AAL1 CES TxBDs
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30.10.5.14 AAL2 TxBDs
30.10.5.15 AAL5, AAL1 User-Defined Cell—TxBD Extension
NOTE
For AAL0 a complete cell, including the UDC header, is stored in the buffer;
the AAL0 BD size is always 8 bytes.
Offset + 0x08
Extra Cell Header.
Used to store the user-defined cell’s extra cell header. The extra cell header can be 1–12 bytes long.
Offset + 0x14
Reserved (12 bytes)
Figure 30-53. User-Defined Cell—TxBD Extension
30.10.6 AAL1 Sequence Number (SN) Protection Table
The 32-byte sequence number protection table, pointed to by AAL1_SNPT_BASE in the ATM parameter
RAM, resides in dual-port RAM and is used for AAL1 only. The table should be initialized according to
0
15
Offset + 0x00
Offset + 0x02
Offset + 0x04
Offset + 0x06
Offset + 0x08
Offset + 0x0A
Offset + 0x0C
Offset + 0x0E
Offset + 0x10
Offset + 0x12
Offset + 0x14
Offset + 0x16
Offset + 0x18
Offset + 0x1A
Offset + 0x1C
Offset + 0x1E
0x0000
0x0007
0x000D
0x000A
0x000E
0x0009
0x0003
0x0004
0x000B
0x000C
0x0006
0x0001
0x0005
0x0002
0x0008
0x000F
Figure 30-54. AAL1 Sequence Number (SN) Protection Table
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30.10.7 UNI Statistics Table
The UNI statistics table, shown in Table 30-41, resides in the dual-port RAM and holds UNI statistics
parameters. UNI_STATT_BASE points to the base address of this table. Each PHY’s own table has a
starting address given by UNI_STATT_BASE+ PHY# × 8.
Table 30-41. UNI Statistics Table
1
Offset
Name
Width
Description
0x00
UTOPIAE
Hword Counts cells dropped as a result of UTOPIA/ATM protocol violations.
Violations include the following:
1. Parity error
2. HEC error
3. Invalid timing of RxSOC.
If RxClav is asserted for the selected PHY, RxSOC should be asserted the
cycle immediately following the assertion of RXENB. A violation occurs if
RxSOC is not asserted at that time (i.e. is late or is missing).
0x02
0x04
0x06
MIC_COUNT
Hword Counts misinserted cells dropped as a result of address look-up failure.
CRC10E_COUNT Hword Counts cells dropped as a result of CRC10 failure. AAL5-ABR only.
Hword Reserved, should be cleared.
—
1
Offset from UNI_STATT_BASE+PHY# × 8
30.11 ATM Exceptions
The ATM controller interrupt handling involves two principal data structures: FCCEs (FCC event
registers) and circular interrupt queues.
Four priority interrupt queues are available. By programming RCT[INTQ] and TCT[INTQ], the user
determines which queue receives the interrupt. Channel Rx buffer, Rx frame, or Tx buffer events can be
masked by clearing interrupt mask bits in RCT and TCT.
After an interrupt request, the host reads FCCE. If FCCE[GINTx] = 1, at least one entry was added to one
of the interrupt queues. After clearing FCCE[GINTx], the host processes the valid interrupt queue entries
and clears each entry’s valid bit. The host follows this procedure until it reaches an entry with V = 0. See
The host controls the number of interrupts sent to the core using a down counter in the interrupt queue’s
parameter table; see Section 30.11.3. For each event sent to an interrupt queue, a counter (that has been
initialized to a threshold number of interrupts) is decremented. When the counter reaches zero, the global
interrupt, FCCE[GINTx], is set.
30.11.1 Interrupt Queues
Interrupt queues are located in external memory. The parameters of each queue are stored in a table. See
When an interrupt occurs, the CP writes a new entry to the interrupt queue, the V bit is set, and the queue
pointer (INTQ_PTR) is incremented. Once the CP uses an entry with W = 1, it returns to the first entry in
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the queue. If the CP tries to overwrite a valid entry (V = 1), an overflow condition occurs and the queue’s
overflow flag, FCCE[INTOx], is set.
Word
INTQ_BASE
Software (Core) Pointer
INTQ_PTR
V = 0
V = 0
V = 0
V = 1
V = 1
V = 1
V = 0
V = 0
V = 0
W = 0
W = 0
W = 0
W = 0
W = 0
W = 0
W = 0
W = 0
W = 1
Invalid
Invalid
Invalid
Interrupt Entry
Interrupt Entry
Interrupt Entry
Invalid
Invalid
Invalid
Figure 30-55. Interrupt Queue Structure
30.11.2 Interrupt Queue Entry
Each one-word interrupt queue entry provides detailed interrupt information to the host. Figure 30-56
shows an entry.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Offset + 0x00
Offset + 0x02
V
—
W
—
TBNR RXF BSY TXB RXB
Channel Code (CC)
Figure 30-56. Interrupt Queue Entry
Table 30-42 describes interrupt queue entry fields.
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Table 30-42. Interrupt Queue Entry Field Description
Description
Offset
Bits
Name
V
0x00
0
Valid interrupt entry
0 This interrupt queue entry is free and can be use by the CP.
1 This interrupt queue entry is valid. The host should read this interrupt and clear this bit.
1
2
—
Reserved, should be cleared.
W
Wrap bit. When set, this is the last interrupt circular table entry. During initialization, the
host must clear all W bits in the table except the last one, which must be set.
3–10
11
—
Reserved, should be cleared.
TBNR Tx buffer-not-ready. Set when a transmit buffer-not-ready interrupt is issued. This interrupt
is issued when the CP tries to open a TxBD that is not ready (R = 0). This interrupt is sent
only if TCT[BNM] = 1. This interrupt has an associated channel code.
Note that for AAL5, this interrupt is sent only if frame transmission is started. In this case,
an abort frame transmission is sent (last cell with length=0), the channel is taken out of the
APC, and the TCT[VCON] flag is cleared.
12
RXF Rx frame. RXF is set when an Rx frame interrupt is issued. This interrupt is issued at the
end of AAL5 PDU reception. This interrupt is issued only if RCT[RXFM] = 1. This interrupt
has an associated channel code.
13
14
15
—
BSY Busy condition. The BD table or the free buffer pool associated with this channel is busy.
Cells were discarded due to this condition. This interrupt has an associated channel code.
TXB Tx buffer. TXB is set when a transmit buffer interrupt is issued. This interrupt is enabled
when both TxBD[I] and TCT[IMK] = 1. This interrupt has an associated channel code.
RXB Rx buffer. RXB is set when an Rx buffer interrupt is issued. This interrupt is enabled when
both RxBD[I] and RCT[RXBM] = 1. This interrupt has an associated channel code.
0x02
CC
Channel code specifies the channel associated with this interrupt.
30.11.3 Interrupt Queue Parameter Tables
INTT_BASE in the parameter RAM points to the base address of these tables. Each of the four interrupt
queues has its own parameter table with a starting address given by INTT_BASE+ RCT/TCT[INTQ] × 16.
Table 30-43. Interrupt Queue Parameter Table
Offset
Name
Width
Description
1
0x00
0x04
0x08
INTQ_BASE
INTQ_PTR
INT_CNT
Word
Word
Base address of the interrupt queue. User-defined.
Pointer to interrupt queue entry. Initialize to INTQ_BASE.
Half
Word
Interrupt counter. Initialize with INT_ICNT. The CP decrements INT_CNT for each
interrupt. When INT_CNT reaches zero, the queue’s global interrupt flag
FCCE[GINTx] is set.
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Table 30-43. Interrupt Queue Parameter Table (continued)
Offset
Name
Width
Description
1
0x0A
INT_ICNT
Half
Word
Interrupt initial count. User-defined global interrupt threshold—the number of
interrupts required before the CP issues a global interrupt (FCCE[GINTx]).
0x0C INTQ_ENTRY
Word
Interrupt queue entry. Must be initialized to the entry pointed to by INTQ_PTR,
which is initially the first empty entry of the queue. Note that after an overrun
occurs, this entry must be reset to the entry pointed to by INTQ_PTR to reenable
interrupt processing.
1
Offset from INTT_BASE+RCT/TCT[INTQ] × 16
30.12 The UTOPIA Interface
The ATM controller interfaces with a PHY device through the UTOPIA interface. The PowerQUICC II
supports UTOPIA level 2 for both master and slave modes.
30.12.1 UTOPIA Interface Master Mode
Cell transfer on an ATM device (with single or multiple PHYs) uses cell-level handshaking as defined in
the UTOPIA standards. The FCC does not pause cell transmission by the PHY and does not stop receiving
cells from the PHY.
TXDATA[15–0]/[7–0]
TxSOC
RXDATA[15–0]/[7–0]
RXSOC
TXENB
RXENB
PowerQUICC II
TXPRTY
PowerQUICC II
RXPRTY
TXCLK
RXCLK
TXCLAV[3–0]/TxClav
TXADD[4–0]
RXCLAV[3–0]/RxClav
RXADD[4–0]
Figure 30-57. UTOPIA Master Mode Signals
Table 30-44 describes UTOPIA master mode signals.
Table 30-44. UTOPIA Master Mode Signal Descriptions
Signal
Description
TxDATA[15–0]/[7–0] Carries transmit data from the ATM controller to a PHY device. TxDATA[15]/[7] is the msb when
using UTOPIA 16/8, TxDATA[0] is the lsb.
TxSOC
Transmit start of cell. Asserted by the ATM controller when the first byte of a cell is sent on
TxDATA lines.
TxENB
Transmit enable. Asserted by the ATM controller when valid data is placed on the TxDATA lines.
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Table 30-44. UTOPIA Master Mode Signal Descriptions (continued)
Description
Signal
TxClav/TxCLAV[3–0] Transmit cell available. Asserted by the PHY device to indicate that the PHY has room for a
complete cell.
TxPRTY
TxCLK
Transmit parity. Asserted by the ATM controller. It is an odd parity bit over the TxDATA bits.
Transmit clock. Provides the synchronization reference for the TxDATA, TxSOC, TxENB,
TxCLAV, TxPRTY signals. All the above signals are sampled at low-to-high transitions of
TxCLK.
TxADD[4–0]
Transmit address. Address bus from the ATM controller to the PHY device used to select the
appropriate M-PHY device. Each M-PHY device needs to maintain its address. TxADD[4] is the
msb.
RxDATA[15–0]/[7–0] Carries receive data from the PHY to the ATM controller. RxDATA[15]/[7] is the msb when using
UTOPIA 16/8, RxDATA[0] is the lsb.
RxSOC
Receive start of cell. Asserted by the PHY device as the first byte of a cell is received on
RxDATA.
RxENB
Receive enable. An ATM controller asserts to indicate that RxDATA and RxSOC will be sampled
at the end of the next RxCLK cycle. For multiple PHYs, RxENB is used to three-state RxDATA
and RxSOC at each PHY’s output. RxDATA and RxSOC should be enabled only in cycles after
those with RxENB asserted.
RxClav/RxCLAV[3–0 Receive cell available. Asserted by a PHY device when it has a complete cell to give the ATM
]
controller.
RxPRTY
Receive parity. Asserted by the PHY device. It is an odd parity bit over the RxDATA. If there is
a RxPRTY error and the receive parity check FPSMR[RxP] is cleared, the cell is discarded. See
RxCLK
Receiver clock. Synchronization reference for RxDATA, RxSOC, RxENB, RxCLAV, and
RxPRTY, all of which are sampled at low-to-high transitions of RxCLK.
RxADD[4–0]
Receive address. Address bus from the ATM controller to the PHY device used to select the
appropriate M-PHY device. Each M-PHY device needs to maintain its address. RxADD[4] is the
msb.
30.12.1.1 UTOPIA Master Multiple PHY Operation
The PowerQUICC II supports two polling modes:
•
Direct polling uses CLAV[3–0] with PHY selection using ADD[1–0]. Up to four PHYs can be
supported.
•
Single CLAV polling uses Clav and ADD[4–0]. ATM controller polls all active PHYs starting from
PHY address 0x0 to the address written in FPSMR[LAST_PHY]. Up to 31 PHY devices are
supported.
Both modes support round-robin priority or fixed priority, described in Section 30.13.2, “FCC
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30.12.2 UTOPIA Interface Slave Mode
In UTOPIA slave mode (single or multiple PHY), cells are transferred using cell-level and octet-level
handshakes as defined by the UTOPIA level-2 standard. The FCC allows cell transfer to be halted or
paused. If the master negates TXENB, the cell that the FCC is transmitting is halted. If the master negates
RXENB, the cell that the FCC is receiving is paused. Note the following restriction on halting a cell
transfer: there cannot be a halt immediately before the transfer of the last data word. There is no restriction
on pausing a cell transfer.
TXDATA[15–0]/[7–0]
TXSOC
RXDATA[15–0]/[7–0]
RXSOC
TXENB
RXENB
PowerQUICC II
TXPRTY
TXCLK
PowerQUICC II
RXPRTY
RXCLK
TXCLAV
TXADD[4–0]
RXCLAV
RXADD[4–0]
Figure 30-58. UTOPIA Slave Mode Signals
Table 30-45 describes UTOPIA slave mode signals.
Table 30-45. UTOPIA Slave Mode Signals
Signal
Description
TxDATA[15–0]/[7–0] Transmit data bus. Carries transmit data from the ATM controller to the master device.
TxDATA[15]/[7] is the msb, TxDATA[0] is the lsb.
TxSOC
TxENB
TxCLAV
Transmit start of cell. Asserted by an ATM controller as the first byte of a cell is sent on the
TxDATA lines.
Transmit enable. An input to the ATM controller. It is asserted by the UTOPIA master to signal
the slave to send data in the next TxCLK cycle.
Transmit cell available. Asserted by the ATM controller to indicate it has a complete cell to
transmit.
TxPRTY
TxCLK
Transmit parity. Asserted by the ATM controller. It is an odd parity bit over the TxDATA.
Transmit clock. Provides the synchronization reference for the TxDATA, TxSOC, TxENB,
TxCLAV, and TxPRTY signals. All of the above signals are sampled at low-to-high transitions of
TxCLK.
TxADD[4–0]
Transmit address. Address bus from the master to the ATM controller used to select the
appropriate M-PHY device.
RxDATA[15–0]/[7–0] Receive data bus. Carries receive data from the master to the ATM controller. RxDATA[15]/[7]
is the msb, RxDATA[0] is the lsb.
RxSOC
Receive start of cell. Asserted by the master device whenever the first byte of a cell is being
received on the RxDATA lines.
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Table 30-45. UTOPIA Slave Mode Signals (continued)
Signal
RxENB
Description
Receive enable. Asserted by the master device to signal the slave to sample the RxDATA and
RxSOC signals.
RxCLAV
RxPRTY
Receive cell available. Asserted by the ATM controller to indicate it can receive a complete cell.
Receive parity. Asserted by the PHY device. It is an odd parity bit over the RxDATA[15–0]. If
there is a RxPRTY error and the receive parity check FPSMR[RxP] is cleared, the cell is
RxCLK
Receive clock. Provides the synchronization reference for the RxDATA, RxSOC, RxENB,
RxCLAV, and RxPRTY signals. All the above signals are sampled at low-to-high transitions of
RxCLK.
RxADD[4–0]
Receive address. Address bus from master to the ATM controller device used to select the
appropriate M-PHY device.
30.12.2.1 UTOPIA Slave Multiple PHY Operation
The user should write the ATM controller PHY address in FPSMR[PHY ID].
30.12.2.2 UTOPIA Clocking Modes
The UTOPIA clock can be generated internally or externally. If the UTOPIA clock is to be generated
internally, the user should assign one of the baud-rate generators to supply the UTOPIA clock. See
30.12.2.3 UTOPIA Loop-Back Modes
The UTOPIA interface supports loop-back mode. In this mode, the Rx and Tx UTOPIA signals are shorted
internally. Output pins are driven; input pins are ignored.
Note that in loop-back mode, the transmitter and receiver must operate in complementary modes. For
example, if the transmitter is master, the receiver must be a slave (FPSMR[TUMS] = 0, FPSMR[RUMS]
= 1).
Table 30-46. UTOPIA Loop-Back Modes
DIAG
Description
00
01
1x
Normal mode
Loop-back. UTOPIA Rx and Tx signals are shorted internally. Output pins are driven, input pins are ignored.
Reserved
30.13 ATM Registers
The following sections describe the configuration of the registers in ATM mode.
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30.13.1 General FCC Mode Register (GFMR)
The GFMR mode field should be programmed for ATM mode. To enable transmit and receive functions,
ENT and ENR must be set as the last step in the initialization process. Full GFMR details are given in
30.13.2 FCC Protocol-Specific Mode Register (FPSMR)
protocol-specific FCC functions. The user should initialize the FPSMR. Erratic behavior may result if
there is an attempt to write to the FPSMR while the transmitter and receiver are enabled.
0
3
4
7
8
9
10
11
15
Field
Reset
R/W
TEHS
REHS
ICD TUMS RUMS
LAST PHY/PHY ID
0000_0000_0000_0000
R/W
Addr
0x11304 (FPSMR1), 0x11324 (FPSMR2), 0x11344(FPSMR3)
16 17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Field
Reset
R/W
—
TPRI TUDC RUDC RXP TUMP
—
TSIZE RSIZE UPRM UPLM RUMP HECI HECC COS
0000_0000_0000_0000
R/W
Addr
0x11306 (FPSMR1), 0x11326 (FPSMR2), 0x11346 (FPSMR3)
Figure 30-59. FCC ATM Mode Register (FPSMR)
Table 30-47 describes FPSMR fields.
Table 30-47. FCC ATM Mode Register (FPSMR)
Bits
Name
Description
0–3
TEHS
Transmit extra header size. Used only in user-defined cell mode to hold the Tx user-defined
cells’ extra header size. Values between 0–11 are valid. TEHS = 0 generates 1 byte of extra
header; TEHS = 11 generates 12 bytes of extra header.
Note: When working with a 16-bit UTOPIA interface, TEHS must represent an even number of
header bytes (so the actual programmed value should be odd).
1
Note: For IMA there is no extra header support for User defined cells so these bits should be
programmed to zero for IMA support.
4–7
REHS Receive extra header size. Used only in user-defined cell mode to hold the Rx user-defined
cells’ extra header size. Values between 0–11 are valid. For REHS = 0, the receiver expects 1
byte of extra header; for REHS = 11, it expects 12 bytes of extra header.
Note: When working with a 16-bit UTOPIA interface, REHS must represent an even number of
header bytes (so the actual programmed value should be odd).
1
Note: For IMA there is no extra header support for User defined cells so these bits should be
programmed to zero for IMA support.
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ATM Controller and AAL0, AAL1, and AAL5
Table 30-47. FCC ATM Mode Register (FPSMR) (continued)
Description
Bits
Name
8
ICD
Idle cells discard
0 Discard idle cells (GFC, VPI, VCI, PTI =0)
1 Do not discard idle cells
1
Note: For IMA It is recommended to program ICD=1 so that idle cells will not be discarded.
Idle cells should not occur on an IMA link, and their presence indicates an IMA protocol
violation. Software should disable the discarding of idle cells, route the idle cells to a
dedicated channel, and treat reception of cells on that dedicated channel as an indication
of a system or system configuration error
9
TUMS Transmit UTOPIA master/slave mode
1
0 Transmit UTOPIA master mode is selected (Use this mode for IMA support )
1 Transmit UTOPIA slave mode is selected
10
RUMS Receive UTOPIA master/slave mode
1
0 Receive UTOPIA master mode is selected (Use this mode for IMA support )
1 Receive UTOPIA slave mode is selected
11–15
LAST
PHY/
Last PHY. (Multiple PHY master mode only.) The UTOPIA interface polls all PHYs starting from
PHY address 0 and ending with the PHY address specified in LAST PHY. (The number of active
PHY ID PHYs are LAST PHY+1). LAST PHY should be specified in both single-Clav and direct-polling
modes.
PHY ID. (Multiple PHY slave mode only.) Determines the PHY address of the ATM controller
when configured as a slave in a multiple PHY ATM port.
1
Note: For IMA support this field must be programmed to the PHY address of the last PHY
device; it is unrelated to the “virtual PHY number” for the IMA group programmed into
VPHYNUM.
16–17
18
—
Reserved, should be cleared.
TPRI
Transmitter priority. Used to adjust the default priority of the FCC transmitter. It is strongly
recommended to set TPRI when in multi-PHY mode, or in single-PHY mode if the maximal bit
rate (either internal or external rate) is higher than that of the other FCCs; for other modes, it
should remain cleared.
0 Default operation
1 Prevents elevation to emergency mode
19
20
21
22
23
TUDC Transmit user-defined cells
1
0 Regular 53-byte cells (Disable this mode for IMA support )
1 User-defined cells
RUDC Receive user-defined cells
1
0 Regular 53-byte cells (Disable this mode for IMA support )
1 User-defined cells
RxP
Receive parity check.
0 Check Rx parity line
1 Do not check Rx parity line
TUMP Transmit UTOPIA multiple PHY mode
0 Transmit UTOPIA single PHY mode is selected
1
1 Transmit UTOPIA multiple PHY mode is selected (Use this mode for IMA support )
—
Reserved, should be cleared.
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ATM Controller and AAL0, AAL1, and AAL5
Table 30-47. FCC ATM Mode Register (FPSMR) (continued)
Description
Bits
Name
24
TSIZE Transmit UTOPIA data bus size
0 UTOPIA 8-bit data bus size
1 UTOPIA 16-bit data bus size
25
26
RSIZE Receive UTOPIA data bus size
0 UTOPIA 8-bit data bus size
1 UTOPIA 16-bit data bus size
UPRM UTOPIA priority mode.
0 Round robin. Polling is done from PHY zero to the PHY specified in LAST PHY. When a PHY
is selected, the UTOPIA interface continues to poll the next PHY in order.
1 Fixed priority. Polling is done from PHY zero to the PHY specified in LAST PHY. When a PHY
is selected, the UTOPIA interface continues to poll from PHY zero.
27
UPLM UTOPIA polling mode.
0 Single Clav polling. Polling is done using Add[4–0] and Clav. Selection is done using
Add[4–0]. Up to 31 PHYs can be polled.
1 Direct polling. Polling is done using Clav[3–0]. Selection is done using Add[1–0]. Up to 4
PHYs can be polled.
28
29
30
RUMP Receive UTOPIA multiple PHY mode.
0 Receive UTOPIA single PHY mode is selected
1
1 Receive UTOPIA multiple PHY mode is selected (Use this mode for IMA support )
HECI
HEC included. Used in UDC mode only.
0 HEC octet is not included when UDC mode is enabled.
1 HEC octet is included when UDC mode is enabled.
HECC Receive HEC check
0 Do not check Rx HEC
1 Check Rx HEC. HEC errors are reported in UTOPIAE counter (see Section 30.10.7, “UNI
31
COS
Coset mode enable
0 Check Rx HEC with no COSET
1 Check Rx HEC with COSET mode enabled
1
MPC8264 and MPC8266 only.
30.13.3 ATM Event Register (FCCE)/Mask Register (FCCM)
The FCCE register is the ATM controller event register when the FCC operates in ATM mode. When it
recognizes an event, the ATM controller sets the corresponding FCCE bit. Interrupts generated by this
register can be masked in FCCM. FCCE is memory-mapped and can be read at any time. Bits are cleared
by writing ones to them; writing zeros has no effect. Unmasked bits must be cleared before the CP clears
the internal interrupt request.
FCCM is the ATM controller mask register. The FCCM has the same bit format as FCCE. Setting an
FCCM bit enables and clearing a bit masks the corresponding interrupt in the FCCE.
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ATM Controller and AAL0, AAL1, and AAL5
0
4
5
6
7
8
9
10
11
12
13
14
15
Field
Reset
R/W
—
TIRU GRLI GBPB GINT3 GINT2 GINT1 GINT0 INTO3 INTO2 INTO1 INTO0
0000_0000_0000_0000
R/W
Addr
16
31
Field
Reset
R/W
—
0000_0000_0000_0000
R/W
Addr
0x11312 (FCCE1), 0x11332 (FCCE2), 0x11352 (FCCE3)/
0x11316 (FCCM1), 0x11336 (FCCM2), 0x11356 (FCCM3)
Figure 30-60. ATM Event Register (FCCE)/FCC Mask Register (FCCM)
Table 30-48 describes FCCE fields.
Table 30-48. FCCE/FCCM Field Descriptions
Bits
Name
Description
0–4
5
—
Reserved, should be cleared.
TIRU Transmit internal rate underrun. A cumulative lag of seven cells has formed between the
programmable rate and the actual rate for a specific Phy. A transmit internal rate counter expired
and a cell was not sent, either because of slow CPM performance or slow PHY performance. TIRU
6
7
GRLI Global red-line interrupt. GRLI is set when a free buffer pool’s RLI flag is set. The RLI flag is also set
in the free buffer pool’s parameter table.
GBPB Global buffer pool busy interrupt. GBPB is set when a free buffer pool’s BUSY flag is set. The BUSY
flag is also set in the free buffer pool’s parameter table.
8–11 GINTx Global interrupt. Set when the number of events sent to the corresponding interrupt queue reaches
12–15 INTOx Interrupt queue overflow. Set when an overflow condition occurs in the corresponding interrupt
16–31
—
Reserved, should be cleared.
30.13.4 FCC Transmit Internal Rate Registers (FTIRRx)
(FCC1 and FCC2 Only)
NOTE
The source clock of the internal rate timers is the BRGs clock, which is
configured in CMXUAR. THe frequency of this clock must be less than one
half of the FCC Tx clock of the UTOPIA interface.
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ATM Controller and AAL0, AAL1, and AAL5
The first four PHY devices (address 00– 03) on FCC1 and FCC2 have their own transmit internal rate
registers (FTIRRx_PHY0–FTIRRx_PHY3) for use in transmit internal rate mode. In this mode, the total
transmission rate is determined by FCC internal rate timers. As a master, the controller only polls the
PHY’s Clav status at the rate determined by the internal rate. As a slave, the controller attempts to insert
cells into the FIFO at the internal rate. The controller can handle a lag of up to seven cells per PHY between
the programmable and actual bus rate. When the cell count mismatch reaches seven, TIRU event is
mismatch occurs if the PHY rate or the CPM performance are lower then the internal rate. FTIRRx, shown
in Figure 30-61, includes the initial value of the internal rate timer. The source clock of the internal rate
timers is supplied by one of four baud-rate generators selected in CMXUAR; see Section 16.4.1, “CMX
the slave PHY address.
0
1
2
3
4
5
6
7
Field
Reset
R/W
TRM
Initial Value
0000_0000
R/W
Addr
Figure 30-61. FCC Transmit Internal Rate Registers (FTIRRx)
Table 30-49. FTIRRx Field Descriptions
Bits
Name
Description
0
TRM Transmit mode.
0 External rate mode.
1 Internal rate mode.
1–7
Initial The initial value of the internal rate timer. A value of 0x7F produces the minimum clock rate (BRG
Value CLK divided by 128); 0x00 produces the maximum clock rate (BRG CLK divided by 1).
Figure 30-62 shows how transmit clocks are determined.
.
PHY# 0 Tx Rate
PHY# 1 Tx Rate
PHY# 2 Tx Rate
PHY# 3 Tx Rate
PHY#0 Internal Rate Timer
PHY#1 Internal Rate Timer
PHY#2 Internal Rate Timer
PHY#3 Internal Rate Timer
BRG CLK
Figure 30-62. FCC Transmit Internal Rate Clocking
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ATM Controller and AAL0, AAL1, and AAL5
Example:
Suppose the PowerQUICC II is connected to four 155 Mbps PHY devices and the maximum transmission
rate is 155 Mbps for the first PHY and 10 Mbps for the rest of the PHYs. The BRG CLK should be set
according to the highest rate. If the CPM clock is 133 MHz and the BRG CLK is 66 MHz, the BRG should
be programmed to divide the CPM clock by 181 to generate cell transmit requests every 362 system clocks:
(66MHz × (53 × 8))
--------------------------------------------------
= 181
155.52Mbps
For the 155 Mbps PHY, the FTIRR divider should be programmed to zero (the BRG CLK is divided by
one); for the rest of the 10 Mbps PHYs, the FTIRR divider should be programmed to 14 (the BRG CLK
is divided by 15).
30.14 ATM Transmit Command
The CPM command set includes an ATM TRANSMIT that can be sent to the CP command register (CPCR),
described in Section 14.4.1.
The ATM TRANSMIT command (CPCR[opcode] = 0b1010, CPCR[SBC[code]] = 0b01110,
CPCR[SBC[page]] = 0b00100 or 0b00101 (FCC1 or FCC2), CPCR[MCN] = 0b0000_1010) turns a
passive channel into an active channel by inserting it into the APC scheduling table. Note that an ATM
TRANSMIT command should be issued only after the channel’s TCT is completely initialized and the
channel has BDs ready to transmit. Note also that CPCR[SBC[code]] = 0b01110 and not FCC1 or FCC2
code.
Before issuing the command, the user should initialize COMM_INFO fields in the parameter RAM as
Offset
0x86
0x88
0x8A
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
—
CTB
PHY#
ACT
PRI
Channel Code (CC)
BT
Figure 30-63. COMM_INFO Field
Table 30-50 describes COMM_INFO fields.
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Table 30-50. COMM_INFO Field Descriptions
Description
Offset
Bits
Name
0x86
0–4
5
—
Reserved, should be cleared.
CTB Connection tables bus. Used for external channels only
0 External connection tables reside on the 60x bus.
1 External connection tables reside on the local bus.
6–10
PHY# PHY number. In single PHY mode this field should be cleared In multiple PHY mode this
field is an index to the APC parameter table associated with this channel.
11–12
ACT ATM channel type
00 Other channel
01 VBR channel
1x Reserved
13-15
PRI
APC priority level.
000 Highest priority (APC_LEVEL1)
111 Lowest priority (APC_LEVEL8).
0x88
0x8A
0-15
0-15
CC
BT
Channel code. The channel code associated with the current channel.
Burst tolerance. For use by VBR channels only (ACT field is 0b01). Specifies the initial
burst tolerance (GCRA burst credit) of the current VC.
30.15 SRTS Generation and Clock Recovery Using External Logic
The PowerQUICC II supports SRTS generation using external logic. If SRTS generation is enabled
(TCT[SRT] = 1), the PowerQUICC II reads SRTS[0–3] from the external SRTS logic and inserts it into 4
External SRTS Logic
(N=3008 bits = 8 SAR PDU)
SRTS
fs
Counter
divided by N
Latch
2.43 MHz (E1/T1)
1/64
155.52 MHz
p = 4 bit counter
DMA reads new SRTS code
SN=1 SN=3 SN=5 SN=7
Figure 30-64. AAL1 CES SRTS Generation Using External Logic
For every eight cells, the external SRTS logic should supply a valid SRTS code. The CP reads the SRTS
code from the bus selected in TCT[BIB] using a DMA read cycle of 1-byte data size. Each AAL1 CES
channel can be programmed to select one of 16 addresses available for reading the SRTS result. The SRTS
code should be placed on the least-significant nibble of that address (SRTS[0]=lsb, SRTS[3]=msb). The
SRTS is synchronized with the sequence count cycle—SRTS[0] is inserted into the cell with SN = 7;
SRTS[3] is inserted into the cell with SN = 1. For every eighth AAL1 CES SAR PDU, the SRTS logic
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ATM Controller and AAL0, AAL1, and AAL5
samples a new SRTS and stores it internally. The SRTS is a sample of a 4-bit counter with a 2.43-MHz
reference clock (for E1/T1) synchronized with the network clock.
The PowerQUICC II supports clock recovery using an external SRTS PLL. If SRTS recovery is enabled
(RCT[SRT]=1), the PowerQUICC II tracks the SRTS from four incoming cells whose SN field equals 1,
External SRTS Logic
(N=3008 bits = 8 SAR PDU)
SRTS
fs
Counter
Latch
divided by N
2.43 MHz (E1/T1)
155.52 MHz
p = 4 bit
counter
1/64
+
-
VCO
SRTS Diff
Latch
DMA writes new SRTS code
SN=1 SN=3 SN=5 SN=7
Figure 30-65. AAL1 CES SRTS Clock Recovery Using External Logic
On every eighth cell, the PowerQUICC II writes a new SRTS code to the external logic using the bus
selected in RCT[BIB]. The CP writes the SRTS code using a DMA write cycle of 1-byte data size. Each
AAL1 CES channel can be programmed to select one of 16 addresses available for writing the SRTS result.
The SRTS code is written to the least-significant nibble of that address (SRTS[0]=lsb, SRTS[3]=msb). The
SRTS is synchronized with the sequence count cycle—SRTS[3] is read from the cell with SN = 1 and
SRTS[0] is read from the cell with SN = 7. The SRTS PLL makes periodic clock adjustments based on the
difference between a locally generated SRTS and a remotely generated SRTS retrieved every eight
received cells.
30.16 Configuring the ATM Controller for Maximum CPM Performance
The following sections recommend ATM controller configurations to maximize CPM performance.
30.16.1 Using Transmit Internal Rate Mode
When the total transmit rate is less than the PHY rate, use the transmit internal rate mode and configure
the internal rate clock to the maximum bit rate required. (See 30.2.1.5, “Transmit External Rate and
Internal Rate Modes.”) The PHY then automatically fills the unused bandwidth with idle cells, not the
ATM controller. If the internal rate mode is not used, CPM performance is consumed generating the idle
cell payload and using the scheduling algorithm to fill the unused bandwidth at the higher PHY rate.
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ATM Controller and AAL0, AAL1, and AAL5
For example, suppose a system uses a 155.52-Mbps OC-3 device as PHY0, but the maximum required data
rate is only 100 Mbps. In transmit internal rate mode, the user can configure the internal rate mechanism
to clock the ATM transmitter at a cell rate of 100 Mbps. If the system clock is 133 MHz, program a BRG
to divide the system clock by 563 to generate a transmit cell request every 563 CPM clocks:
(133MHz × (53 × 8))
-----------------------------------------------------
= 563
100Mbps
Set FTIRRx_PHY0[TRM] to enable the transmit internal rate mode and clear FTIRRx_PHY0[Initial
Value] since there is no need to further divide the BRG. See Section 30.13.4, “FCC Transmit Internal Rate
In external rate mode, however, the transmit cell request frequency is determined by the PHY’s maximum
rate, not by internal FCC counters. If an OC-3 PHY is used with the ATM controller in external rate mode,
the requests must be generated every 362 CPM clocks (assuming a 133-MHz CPM clock). If only 100
Mbps is used for real data, 36% of the transmit cell requests consume CPM processing time sending idle
cells.
30.16.2 APC Configuration
Maximizing the number of cells per slot (CPS) and minimizing the priority levels defined in the APC data
structure improves CPM performance:
•
Cells per slot. CPS defines the maximum number of ATM cells allowed to be sent during a time
scheduling algorithm is more efficient sending multiple cells per time slot using the linked-channel
field. Therefore, choose the maximum number of cells per slot allowed by the application.
•
Priority levels. The user can configure the APC data structure to have from one to eight priority
the scheduling algorithm scans all priority levels and maintains pointers for each level. Therefore,
enable only the minimum number of priority levels required.
30.16.3 Buffer Configuration
Using statically allocated buffers of optimal sizes also improves CPM performance:
•
Buffer size. Opening and closing buffer descriptors consumes CPM processing time. Because
smaller buffers require more opening and closing of BDs, the optimal buffer size for maximum
CPM performance is equal to the packet size (an AAL5 frame, for example).
•
Free buffer pool. When the free buffer pool is used, the CPM dynamically allocates buffers and
links them to a channel’s BD. In static buffer allocation, the core assigns a fixed data buffer to each
static buffer allocation to increase CPM performance.
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Chapter 31
ATM AAL1 Circuit Emulation Service
NOTE
The functionality described in this chapter is not available on the MPC8250
nor on .29µm (HiP3) rev A.1 silicon.
Refer to www.freescale.com for the latest RAM microcode packages that
support enhancements.
This chapter describes implementation of circuit emulation service (CES) using ATM adaptation layer
31.1 Features
The AAL1 CES features on the PowerQUICC II are as follows:
•
AAL1
— Reassembly
– Reassembles PDU directly to external memory
– Supports partially filled cells (configurable on a per-VC basis)
– Sequence number (SN) protection (CRC-3 and parity) check
– Implements a 3-step SN algorithm
– Detects and handles lost or misinserted cell
– Maintains bit count integrity (dummy cell insertion)
– Dummy cell contents can be programmed by the user (per FCC)
– Pointer verification in structured AAL1 cell format
– Automatic synchronization using the structured pointer during reassembly
– SRTS (synchronous residual time stamp) gathering on every cycle (8 cells) in unstructured
AAL1
– Statistics gathering on a per-VC basis:
– AAL1 valid cell count
– AAL1 lost cell count
– AAL1 misinserted cell count
– AAL1 pointer mismatch/parity error
– AAL1 Rx buffer pre-overflow
— Segmentation
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ATM AAL1 Circuit Emulation Service
– Segment PDU directly from external memory
– Partially filled cells support (configurable on a per-VC basis)
– Sequence number generation
– Sequence number protection (CRC-3 and even parity) generation
– Pointer generation during segmentation in structure AAL1 cell format
– Clock recovery using external SRTS logic during reassembly in unstructured AAL1
– Statistics gathering on a per-VC basis:
– AAL1 Tx cell count
– AAL1 Tx buffer underrun
•
Circuit emulation service (CES)
— ATM to TDM
– Structured and unstructured data are transferred between the ATM and MCC automatically
without CPU intervention
– In case of pre-underrun, the MCC start sending the last frame or the user-defined underrun
template. The MCC and ATM controller automatically perform slip control with no CPU
intervention.
– In case of pre-overrun, the ATM receiver discards incoming cells until the MCC transmitter
empties enough buffers for the receiver to restart.
– Supports common channel signaling (CCS)
– Supports channel associated signaling (CAS)
– Up to 4 (one per trunk) CAS blocks residing in internal RAM when in automatic
CAS mode and up to 8 blocks when in core CAS modify mode
– Supports Nx64 E1/T1 channels
– CAS routing table on per-VC basis
– Automatic un-packing of the CAS information during reassembly and updating
of the internal CAS block
— TDM to ATM
– Structured and unstructured data are automatically transferred between the MCC and ATM
controller without CPU intervention
– Supports common channel signaling (CCS)
– Supports channel associated signaling (CAS)
– Up to 4 (one per trunk) CAS blocks residing in internal RAM when in automatic
CAS mode and up to 8 blocks when in core CAS modify mode
– Support Nx64 E1/T1 channels
– CAS routing table on per-VC basis
– Automatic packing of CAS information from internal RAM to AAL1 Tx cells
– Once per superframe, the CPM fetches the CAS information from an external
framer and updates each internal CAS block.
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ATM AAL1 Circuit Emulation Service
31.2 AAL1 CES Transmitter Overview
The PowerQUICC II supports both structured and unstructured AAL1 cell formats. For unstructured
format, the transmitter reads 47 bytes from the external buffer and inserts them into the AAL1 user data
field. For structured format, the transmitter reads 46 or 47 bytes from the external buffer and inserts them
into the AAL1 user data field.
31.2.1 Data Path
The AAL1 PDU header, which consists of the sequence number (SN) and the sequence number protection
(SNP) (CRC-3 and parity bit), is generated and inserted into the AAL1 Tx cell, as shown in Figure 31-1.
SN
SNP
SAR-PDU payload
SAR PDU header
Figure 31-1. AAL1 Transmit Cell Format
When the transmitter operates in structured data transfer (SDT) mode, two types of AAL1 cells are
defined: P (pointer) format and non-P format. The two formats are shown below.
Non-P format AAL1 cell
SAR-PDU header
SAR-PDU header
AAL1 user information
P format AAL1 cell
ST pointer
Figure 31-2. AAL1 SDT Cells Type
AAL1 user information
The transmitter generates the structured pointer according to the I.363.1 ITU standard and inserts the
pointer exactly once every cycle (eight successive cells). The transmitter will insert the structured pointer,
at the first opportunity, into a cell with an even sequence count (SC). When the end of the structure is not
present in the current cycle, a P-format cell with a dummy pointer (127) is inserted into the last cell (SC=6)
of the cycle.
The PowerQUICC II supports partially filled cells configured on a per-VC basis. In this mode, only the
valid octets are filled with user information; the rest of the cell is filled with padding octets.
The PowerQUICC II supports synchronous residual time stamp (SRTS) generation using an external PLL.
If this mode is enabled, the PowerQUICC II reads the SRTS code from external logic and inserts it into
31.2.2 Signaling Path
The PowerQUICC II automatically handles the signaling information as part of the interworking function.
The ATM transmitter packs the signaling information at the end of each superframe during the data
segmentation process. Each VC is associated to one signaling block by an internal routing table; see
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ATM AAL1 Circuit Emulation Service
Section 31.4.6, “Channel Associated Signaling (CAS) Support.” The signaling information that resides in
the internal RAM is inserted into the AAL1 cell according to the af-vtoa-0078 specification.
The AAL1 structure is divided into two sections. The first section carries the Nx64 payload, and the second
carries the signaling bits that are associated with the payload.
The PowerQUICC II supports two framing modes: one for Nx64 DS1 ESF (extended superframe) framing,
and the other for Nx64 E1 G.704 framing. See Figure 31-3. Each of the internal signaling blocks can be
used to deliver only one of the framing formats; that is, they cannot be changed dynamically.
24xNx64
16xNx64
•
•
•
•
•
•
ABCD
ABCD
N signaling
nibbles
N signaling
nibbles
ABCD
AAL1 block T1 framing
ABCD
AAL1 block E1 framing
Note: The CAS block size is (N+1) nibble if N is an odd number.
Figure 31-3. AAL1 Framing Formats
31.3 AAL1 CES Receiver Overview
The ATM controller supports both AAL1 structured and unstructured formats. For the unstructured format,
47 octets are copied to the current receive buffer and for the structured format, 46 (P format) or 47 (non-P
format) octets are copied to the current receive buffer.
The AAL1 PDU header, which consists of the sequence number (SN) and the sequence number protection
(SNP) (CRC-3 and parity bit), is checked and the result is delivered to the 3-step-SN algorithm. The
misinserted cells. This algorithm can detect one lost or misinserted cell and maintain synchronization. If
more than one cell is lost or misinserted, the 3-step-SN algorithm switches to hunt mode where it stays
until a cell with a valid SN field is received. After the receiver switches to hunt mode, it closes the RxBD,
modifies the receive statistics, generates an optional interrupt to the CPU and performs a restart sequence.
The restart sequence is implemented only when the ATM channel works in CES mode (RCT[CESM]). In
CAS mode (RCT[CASM]), the ATM receiver channel begins the restart sequence by dropping all
incoming cells and advancing to the beginning of the next super frame, which is the first BD after the one
marked with EOSF (end of super frame). When this BD is ready and the adaptive counter reaches the
ATM_Start threshold, the receiver’s write pointer is not longer in danger of overrunning the read pointer
of the MCC transmitter; that is, it is safe to begin receiving cells again. The ATM receiver then begins the
resynchronization process: for unstructured AAL1 type the ATM receiver waits for the first valid cell, and
for structured AAL1 type the receiver waits for the first valid cell that contains a valid pointer. The first
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ATM AAL1 Circuit Emulation Service
received octet becomes the first byte of the new BD (new super frame). (See Section 31.5, “ATM-to-TDM
Note that when the ATM channel is not in CES mode, no restart sequence is performed; the ATM receiver
immediately starts hunting for the first valid cell. The first received octet becomes the first byte of the next
BD.
During reassembly, the ATM receiver channel’s 3-step-SN algorithm status is delivered to the pointer
verification mechanism. (See Section 31.7, “Pointer Verification Mechanism.”) If the receiver operates in
unstructured data format, the 3-step-SN algorithm status is delivered directly to the bit count integrity
module. When partially filled cells arrive, the bit count integrity module copies only the valid octets from
the received cell (or from the dummy cell if that cell is lost) to the current receive buffer.
In unstructured AAL1 format, when the receive process begins, the receiver hunts for the first cell with a
valid sequence number (SN field). When one arrives, the receiver leaves the hunt state and begins
receiving incoming cells.
In structured AAL1 format, when the receive process begins, the receiver hunts for the first cell with a
valid structured pointer (not a dummy pointer), that points to the start of a new structure. When one arrives,
the receiver leaves the hunt state, opens a new buffer and begins receiving. The structured pointer points
to the first octet of the structured block, which then becomes the first byte of the new buffer.
During the reassembly process, if the receiver switches to hunt mode (due to the 3-step-SN algorithm or
due to receiving two successive mismatched pointers), the ATM receiver closes the current RxBD,
discards incoming cells, modifies the receive statistics accordingly and initiates a restart sequence. The
receiver then waits for a cell with a valid structured pointer to regain synchronization and start receiving
incoming cells again.
The PowerQUICC II supports SRTS clock recovery using an external PLL. The PowerQUICC II tracks
the SRTS from the four incoming cells and writes the SRTS code to external logic. See Section 30.15,
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ATM AAL1 Circuit Emulation Service
Process payload
User information
Bit count integrity
Cell size
Valid cell
Valid SN
Valid/dummy/drop
Drop cell
Unstructured
data format
Pointer verification
Tag cell
3-step SN algorithm
Invalid SN
SN/SNP verification
AAL1 cell stream
Figure 31-4. AAL1 CES Receiver Data flow
31.4 Interworking Functions
The PowerQUICC II supports the interworking of ATM and TDM. The TDM data processing is done by
the MCC and the SI (refer to Chapter 28, “Multi-Channel Controllers (MCCs),” and Chapter 15, “Serial
Interface with Time-Slot Assigner,” for further information). The ATM controller processes the ATM data.
Data forwarding between the ATM controller and the MCC can be done in two ways:
•
Automatic data forwarding. This mode enables automatic data forwarding between AAL1 and
transparent mode over a TDM.
•
Core intervention. When an MCC receive buffer is full and its RxBD is closed, the MCC interrupts
the core. The core copies the MCC’s receive buffer pointer to an ATM TxBD and sets the ready bit
(TxBD[R]). Similarly, when an ATM receive buffer is full and its RxBD is closed, the core services
the ATM controller’s interrupt by copying the ATM receive buffer pointer to an MCC TxBD and
setting TxBD[R]. This mode is useful when additional core processing is required.
Possible interworking applications are as follows:
•
•
Circuit emulation service (CES)
Carrying voice over ATM
• Multiplexing low speed services, such as voice and data, onto one ATM connection
31.4.1 Automatic Data Forwarding
The basic concept of automatic data forwarding is to program the ATM controller and the MCC to process
the same BD table (ring).
The MCC and ATM receivers must be programmed to operate in opposite E-bit polarity. That is, both
receivers receive into buffers in which RxBD[E] = 0 and then set RxBD[E] when the buffer is full. For the
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ATM receiver, set RCT[INVE] of the AAL1 CES-specific areas of the receive connection table; see
31.4.1.1 ATM-to-TDM
from a particular channel to a specific BD table. The MCC transmitter is programmed to operate on the
same table. When the ATM controller fills a receive buffer, the MCC controller sends it. The controllers
synchronize on the ATM controller’s RxBD[E] and the MCC’s TxBD[R].
A threshold mechanism for the MCC transmitter is used to synchronize the automatic start of the
ATM-to-TDM data forwarding. The transmitter waits until the start threshold is reached (enough cells are
received) before sending the valid data. In effect, the MCC start threshold mechanism implements a jitter
buffer designed to accommodate the CDV of the ATM network.
In a CES application, software should first initialize the MCC transmitter, then initialize the ATM receiver.
This way the MCC transmitter sends idle data (0xFF) until the ATM receiver fills enough buffers to reach
the MCC start threshold. (The receiver is effectively filling a jitter buffer.) When the
CES_Adaptive_Counter (CESAC) reaches the MCC_Start threshold, the MCC super channel polling
CESAC starts sending the received data with the first frame SYNC. (The first octet using the first BD is
sent on the first assigned time slot.) Section 31.5, “ATM-to-TDM Adaptive Slip Control,” shows the flow
of ATM-to-TDM interworking.
BD table
TDM
interface
MCC
Tx pointer
MCC
Tx
Buffer 1
Buffer 2
Buffer 3
Buffer 4
Buffer 5
0
1
1
0
0
BD 1
BD 2
BD 3
BD 4
BD 5
UTOPIA
interface
ATM
Rx pointer
ATM
Rx
Note: The ATM Rx should be programmed to operate in
inverted polarity E (Empty) bit.
Figure 31-5. ATM-to-TDM Interworking
31.4.1.2 TDM-to-ATM
line to a specific BD table. The ATM transmitter is programmed to operate on the same BD table. When
the MCC fills a receive buffer, the ATM controller sends it. The two controllers synchronize on the MCC’s
RxBD[E] and the ATM controller’s TxBD[R].
In a CES application, first initialize the ATM transmitter, then initialize the MCC receiver and set
CHAMR[EP].
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ATM AAL1 Circuit Emulation Service
In order to prevent an overrun condition on the MCC receiver, the ATM transmitter should be programmed
to work at a faster rate than the MCC super channel. This ensures that the ATM channel polls the common
BD table at a higher rate than it is being filled by the MCC. In CES mode, the ATM controller ignores BSY
(busy) events when the ATM tries to open a buffer that is not yet full; it continues polling the BD until the
buffer is filled by the MCC receiver and then updates the relevant statistics; see Section 31.15, “Internal
Note that if an overrun condition occurs on the MCC, despite the above mechanism, software should
restart the MCC and ATM channels in order to recover.
BD table
UTOPIA
interface
ATM
Tx pointer
ATM
Tx
Buffer 1
Buffer 2
Buffer 3
Buffer 4
Buffer 5
0
1
1
0
0
BD 1
BD 2
BD 3
BD 4
BD 5
TDM
interface
MCC
Rx pointer
MCC
Rx
Note: The MCC Rx should be programmed to operate in
opposite polarity E (Empty) bit.
Figure 31-6. TDM-to-ATM Interworking
31.4.2 Timing Issues
Use of the TDM interface assumes that all communicating entities are synchronized; that is, that they are
using a synchronized serial clock. If the TDM interfaces are not synchronized, a slip can occur in the
reassembly buffer. In order to prevent the overrun and underrun condition, the PowerQUICC II maintains
an adaptive slip control using a set of 4 threshold pointers and a counter for each ATM-TDM (VC to super
channel) connection.
Before a buffer-not-ready event (ATM-to-TDM data forwarding) occurs at the MCC transmitter, the MCC
buffer pointer reaches the MCC_Stop threshold. Consequently, the MCC pointer freezes on the last
transmitted BD and starts sending the underrun template (or the last transmitted frame). In the meantime,
the ATM receiver continues to write valid data and advance the ATM buffer pointer. When the adaptive
counter CESAC reaches the MCC_start threshold and the MCC has finished sending a multiple frame size,
the MCC exits the pre-underrun state, starts sending the valid received data and advances the MCC buffer
The same mechanism is implemented on the ATM side. When the ATM receiver (ATM-to-TDM data
forwarding) reaches the ATM_Stop threshold (pre-overrun), the ATM controller switches to hunt mode
and discards the channel’s incoming cells. In the meantime, the MCC transmitter continues to send valid
data and advance the MCC buffer pointer. When CESAC falls to the ATM_start threshold, the ATM write
pointer is advanced to the first BD after the one marked with EOSF (in CAS mode). When this BD is ready
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and CESAC reaches the ATM_Start threshold, the receiver’s write pointer is not longer in danger of
overrunning the read pointer of the MCC transmitter; that is, it is safe to begin receiving cells again. The
ATM receiver then begins the resynchronization process: for unstructured AAL1 type the ATM receiver
waits for the first valid cell, and for structured AAL1 type the receiver waits for the first valid cell that
contains a valid pointer. The first received octet becomes the first byte of the new BD (new super frame).
Note that when the ATM receiver is in hunt mode due to one of the following:
•
•
•
•
Sequence number protection error (SNPE)
Sequence count error (SCE)
Structured pointer error (SPE)
Slip condition
The signaling information (CAS) and SRTS information is not updated by the ATM controller until the
ATM receiver switches to SYNC mode, that is, a valid cell is received in unstructured cell format or a valid
pointer is received in structured cell formats.
Software should distinguish between the two types of overrun and underrun conditions:
4. The MCC and ATM controller can automatically recover from overruns and underruns caused by
5. Global underrun (MCCE[GUN]) and overrun (MCCE[GOV]) conditions are errors that need CPU
intervention because it is not known which channels are affected. The CPU should accordingly
reinitialize the transmit parameters and/or the receive parameters to recover.
31.4.3 Clock Synchronization (SRTS, Adaptive FIFO)
Clock synchronization methods, such as SRTS and adaptive FIFO, may be used to prevent reassembly
buffer slip. The SRTS method may be implemented using external logic. The PowerQUICC II can read the
SRTS from external logic and insert it into outgoing AAL1 cells and conversely, can track the SRTS from
incoming AAL1 cells and deliver it to external logic. See Section 30.15, “SRTS Generation and Clock
Alternatively, an adaptive FIFO method can be implemented under core control. Adaptive FIFO is a way
to hold the bridging buffer at its mid-level point. One way to implement it is to periodically poll the
adaptive counter CESAC (difference between the MCC and ATM data pointers) and use this difference as
same external PLL logic used in the SRTS method adjusts the TDM clock.
31.4.4 Mapping TDM Time Slots to VCs
Any TDM time-slot combination can be routed to a specific data buffer using the MCC and its SI. (Refer
Assigner,” for further information.) A common set of data buffers (one BD table) should be used by the
ATM controller to route both the receive and transmit data. For information about ATM buffers see
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ATM AAL1 Circuit Emulation Service
31.4.5 Trunk Condition
According to the Bellcore standard, the interworking function should be able to transmit special payloads
on both the ATM and TDM channels to signal alarm conditions (bellcore TR-NWT-000170). The trunk
condition can be generated under core control. The core may deliver buffers containing special data (trunk
condition payload) to the ATM controller or MCC or even overwrite data buffers being used by the
channels.
31.4.6 Channel Associated Signaling (CAS) Support
For applications requiring channel associated signaling (CAS) support, the CAS manipulation is done by
an external framer. The MCC should be programmed to receive or transmit the internal CAS block
transparently through the external framer’s serial interface. The internal CAS block (depicted in
Figure 31-8) can be adjusted to comply with a specific framer’s serial interface. (See Section 31.4.7.1,
8-bits per channel
• • • • • • • •
Ch 1
Ch 2
Ch 3
Ch 24
Framer serial interface for T1 signaling format
• • • • • • • •
XXXX ABCD
XXXX ABCD
8-bits per channel
Ch 2 Ch 3
• • • • • • • •
Ch 1
Ch 24
Framer serial interface for T1 signaling format (SF)
• • • • • • • •
XXXX ABA’B’
XXXX ABA’B’
8-bits per channel
Ch 2 Ch 3
Ch 32
Ch 1
• • • • • • • •
Framer serial interface for E1 signaling format
• • • • • • • •
XXXX ABCD
XXXX ABCD
Note: The MCC should capture the signaling data on the last frame of a super frame.
See Section 1.4.7.2, “TDM-to-ATM CAS Support”.
Figure 31-7. Mapping CAS Data on a Serial Interface
The MCC and ATM CAS are synchronized with the superframe block boundary. At the ATM side, the
structured block size should be set to the superframe block size plus the size of the CAS block so that the
structured pointer inserted by the ATM controller points to the start of the structured data block. At the
MCC side, the MCC is synchronized with the frame sync signal; the external framer has the ability to place
the signaling information at the appropriate place in a superframe. The PowerQUICC II supports an
automatic mode for forwarding the signaling information from the TDM to the ATM and vice versa. The
ATM controller maintains two CAS blocks per trunk (eight total). One contains the signaling information
unpacked from the AAL1 cells (ATM-to-TDM), and the other contains the signaling information fetched
from an external framer (TDM-to-ATM). All 8 CAS blocks reside in the internal RAM.
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CAS block per trunk
E1 CAS block (32 bytes) T1 – ESF CAS block (24 bytes)
0
1
XXXX
XXXX
XXXX
ABCD
ABCD
ABCD
0
1
XXXX
XXXX
XXXX
ABCD
ABCD
ABCD
•
•
•
•
•
•
•
•
•
•
•
•
•
•
31
XXXX
ABCD
23
XXXX
ABCD
T1 – SF CAS block (24 bytes)
0
1
XXXX
XXXX
XXXX
ABA’B’
ABA’B’
ABA’B’
1
2
•
•
•
•
•
ABCD
ABCD
•
•
23
XXXX
ABA’B’
CAS block resides in the internal RAM.
To allow maximum flexibility in working
ABCD
XXXX
with external framers, the signaling nibble
can occupy the first or second nibble in
the CAS entry.
Figure 31-8. Internal CAS Block Formats
31.4.7 Mapping VC Signaling to CAS Blocks
Each ATM channel is connected to a specific CAS block. The ATM controller implements CAS routing
tables (CRT) to maintain the routing of the signaling information from the AAL1 cells to the internal CAS
blocks for receiving, and vice versa for transmitting. Each ATM channel is connected to one receive or
transmit routing table. A CRT resides in a 32-byte space with each entry pointing to one signaling nibble.
To allow maximum flexibility with external framers, the signaling nibble can occupy the first or second
The CRT entries should be initialized only once before the ATM channel is enabled (receiver or
transmitter). The number of entries that should be initialized must be equal to the number of active slots
(channels) in the corresponding MCC super channel. Each super channel is mapped to a unique ATM
connection (VC). The CRT entries are in ascending order based on the channel slots assigned for the MCC
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One MCC super channel that
contains only 4 active channels
F/S=0
ABCD
One ATM CAS
routing table
XXXX
0
0
0
1
0
0
0
0
0
0
0
0
0
1
2
23
Slot 0 Slot 1 Slot 2
• • • • • •
Slot 23
Example of one MCC super channel in ESF framing (T1) containing 4 TDM slots connected to
an ATM channel with one CAS routing table (CRT). See Section 1.4.7.1, “CAS Routing Table.”
Figure 31-9. Mapping CAS Entry
31.4.7.1 CAS Routing Table
Figure 31-10 shows the structure of a CAS routing table. The CP maintains a pointer which steps through
the table and wraps back to the beginning of the table after servicing the last entry (W=1).
Byte
First signaling nibble
W=0
W=0
W=0
W=0
W=0
W=1
—
—
—
—
—
—
F/S
F/S
F/S
F/S
F/S
F/S
Signaling offset pointer
Signaling offset pointer
Signaling offset pointer
Signaling offset pointer
Signaling offset pointer
Signaling offset pointer
ATM current pointer
Last signaling nibble
Figure 31-10. AAL1 CES CAS Routing Table (CRT)
Figure 31-11 describes the structure of a CAS routing table entry.
0
1
2
3
7
Offset + 0x00
W
—
F/S
Signaling offset pointer (SOP)
Figure 31-11. AAL1 CES CAS Routing Table Entry
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Table 31-1 describes CAS routing table entry fields.
Table 31-1. CAS Routing Table Entry Field Descriptions
Bits Name
Description
0
W
Wrap bit. When set, this bit indicates the last circular table entry. During initialization, the host must clear
all W bits in the table except the last one, which must be set.
1
2
—
Reserved, should be cleared during initialization.
F/S
First/Second.
0 Indicates that the signaling information occupies the first nibble in the CAS block (LSB).
1 Indicates that the signaling information occupies the second nibble in the CAS block (MSB).
3-7
SOP
Signaling Offset Pointer. Offset of the signaling nibble from the internal CAS base address.
Note that in ESF mode the maximum offset is 23 and in E1 framing format the maximum offset is 31.
31.4.7.2 TDM-to-ATM CAS Support
During the segmentation process, the AAL1 CES transmitter reads the CAS data from the internal CAS
block and packs the data and the signaling information at the end of an AAL1 super frame (depicted in
Figure 31-3). All AAL1 functions operate normally (generating AAL1 PDU-headers, structured pointers,
etc.). Each common (MCC, ATM) BD table should point to buffers that can contain a whole number of
super frames. The last buffer of the super frame is marked as the end of a super frame (BD[EOSF]=1).
After closing a buffer with the EOSF indication, the ATM transmitter processes the CAS data—reads it
from the internal CAS block and inserts it into the cell payload at the transmit side. The EOSF indication
in the BD is statically set by the CPU when initializing the BD table.
Buffer 1
Data I/F
T1/E1 framer
MCC
Rx pointer
MCC
Rx
Super
frame
BD table per VC
Buffer 2
UTOPIA
interface
ATM
Tx pointer
ATM
Tx
EOSF
EOSF
Buffer 3
Buffer 4
Super
frame
Transmit
CAS routing
table
Shown in
Figure 1-10
Incoming CAS block per trunk
(internal RAM)
CAS serial I/F
T1/E1 framer
MCC
Rx
Note: With CAS only 4 T1/E1 are supported.
Figure 31-12. CAS Flow TDM-to-ATM
The CAS block is automatically written to internal RAM by the MCC receiver using a separate TDM.
When a super frame is received the MCC should be triggered with a super-frame (multi-frame) SYNC
from the external framer. The incoming CAS block should be captured by the MCC only once for each
super frame (on the last frame).
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The user may use external logic to convert the framer super-frame SYNC to trigger the MCC. The MCC
captures the CAS block from the external framer and copies it transparently into one of four internal CAS
blocks. Each byte in the CAS block contains a nibble of valid CAS information (depicted in Figure 31-8).
Note that the buffer data size should not include the CAS octets.
31.4.7.2.1
CAS Mapping Using the Core (Optional)
To avoid using another TDM dedicated to CAS information, the user can use a parallel interface
(controlled by the core) to deliver the CAS information from the framer to the incoming CAS block. In
this case, the core service routine reads the CAS information from the external framer and writes it to the
incoming CAS block. To optimize the process, the framer can interrupt the core only when new
information is received.
31.4.7.3 ATM-to-TDM CAS Support
During the reassembly process, the AAL1 CES receiver unpacks the signaling information from the end
receive CAS routing table). All AAL1 functions operate normally (AAL1 PDU-header verification, bit
count integrity, 3-step-SN algorithm, etc.). Each common (MCC, ATM) BD table should point to buffers
that can contain a whole number of super
frames. The last buffer of the super frame is marked with EOSF. After closing a buffer with an EOSF
indication, the ATM receiver processes the CAS data (copies it to the internal CAS block from the AAL1
cell payload at the receive side). The EOSF indication in the BD is statically set by the CPU while
Buffer 1
Data I/F
T1/E1 framer
MCC
Tx pointer
MCC
Tx
Super
frame
BD table per VC
Buffer 2
UTOPIA
interface
ATM
Rx pointer
ATM
Rx
EOSF
EOSF
Buffer 3
Buffer 4
Super
frame
Receive
CAS routing
table
Shown in
Figure 1-10
Outgoing CAS block per trunk
(internal RAM)
CAS serial I/F
T1/E1 framer
MCC
Tx
Note: With CAS only 4 T1/E1 are supported.
Figure 31-13. CAS Flow ATM-to-TDM
The CAS block is read from the internal RAM by the MCC. The MCC transmitter continuously reads the
signaling information from one of the four outgoing internal CAS blocks and writes it transparently into
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the external framer. Each byte in the CAS block contains one nibble of valid CAS information (depicted
Note that the buffer data size should not include the CAS octets.
31.4.7.3.1
CAS Updates Using the Core (Optional)
To avoid using another TDM dedicated to CAS information, the user can use a parallel interface controlled
by the core to deliver the outgoing CAS block to the framer. In this case, the ATM receiver should be
programmed to operate in core CAS modify mode RCT[CCASM=1] (and RCT[CASM=1]). In this mode,
the CP adds an entry to the ATM interrupt queue and sets the appropriate sticky bit in OCASSR each time
an AAL1 cell is received with new signaling information (one or more signaling nibble has changed). (See
write the updated outgoing CAS block to the framer.
Note to avoid additional latency, the interrupt queue assigned to this connection should have a global
interrupt threshold of one. See the INT_ICNT parameter discussed in Section 30.11.3, “Interrupt Queue
31.5 ATM-to-TDM Adaptive Slip Control
Two types of slip can occur in ATM-to-TDM operation: overrun and underrun. The two cases are handled
by the MCC and ATM controller automatically without requiring CPU intervention.
Overrun occurs when the MCC transmitter fetches data from the common BD table at a slower rate than
it is being filled by the ATM receiver. In this case, the ATM write pointer meets the MCC read pointer and
a BSY state is declared (an entry is added to the ATM interrupt table) on the ATM side.
Underrun occurs when the MCC transmitter fetches data from the common BD table at a higher rate than
it is being filled by the ATM receiver. In this case, the MCC read pointer reaches a BD that is not ready
and a buffer-not-ready state is declared on the MCC side.
In both slip cases, the MCC and ATM controller automatically recover and restart the ATM-to-TDM
interworking function.
In order to prevent overrun and underrun conditions, the PowerQUICC II maintains an adaptive slip
control using a set of 4 threshold pointers for each ATM-TDM (VC - super channel) connection.
The pre-underrun state (shown in Figure 31-14) occurs when the MCC read pointer goes faster than the
ATM write pointer. When the adaptive counter reaches the MCC_Stop threshold, the MCC read pointer
does not advance. At this point, the current BD (or the underrun template) is retransmitted a multiple of
the frame size. In the meantime, the ATM receiver continues to receive valid data and advance the ATM
write pointer. When the adaptive counter reaches the MCC_start threshold and the MCC has finished
sending a multiple of the frame size, the MCC starts to transmit the valid received data and advance the
MCC read pointer.
Note that when the pre-underrun state occurs, the MCC transmitter can transmit the last buffer
continuously or the underrun template. This is determined by the MCC channel configuration; see the
CHAMR[UTM] bit description in Section 28.3.2.3, “Channel Mode Register (CHAMR)—Transparent
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ATM AAL1 Circuit Emulation Service
Mode.” In the example shown in Figure 31-14, the MCC is programmed to send the current BD during the
pre-underrun condition.
The pre-overrun state occurs when the ATM write pointer goes faster than the MCC read pointer. When
the adaptive counter reaches the ATM_Stop threshold, the ATM write pointer does not advance. The ATM
receiver waits until the adaptive counter reaches the ATM_start threshold. In the meantime, the MCC read
pointer continues to process valid data from the common BD table. When CESAC reaches the ATM start
threshold, the ATM write pointer advances to the first BD after the one that marked with EOSF (in CAS
mode). When this BD is ready, the ATM receiver begins the resynchronization process: for unstructured
AAL1 type the ATM receiver waits for the first valid cell, and for structured AAL1 type the receiver waits
for the first valid cell that contains a valid pointer. The first received octet becomes the first byte of the
new BD (new super frame).
Note that this implementation for slip control provides a good interface for an adaptive FIFO implemented
in software. CESAC represents the difference between the ATM and MCC pointers; the software
application need only convert this value into an SRTS format. Figure 31-14 shows the 8-byte data structure
used to implement ATM-to-TDM slip control. (Three of the bytes are unused.)
MCC
channel
ATM
channel
Core
Polling
(1)
Count down
Count up
Adaptive counter
ATM start threshold
ATM stop threshold
MCC start threshold
MCC stop threshold
When the MCC
closes the BD, the
adaptive counter
(CESAC) is
When the ATM controller
closes the BD, the
adaptive counter
(CESAC) is
decremented
incremented
CES adaptive threshold table address: CATB + MCC_Super_Channel*8
NOTES
1. The MCC start threshold, in effect, implements a CDV jitter buffer.
2. MCC stop threshold should be programmed to (BD Table size -b) to prevent buffer underrun.
3. ATM stop threshold should be programmed to (BD Table size - a) to prevent buffer overrun.
4. The MCC and ATM stop thresholds determine the CDVT.
5. The ATM start threshold determines the time the ATM receiver waits before restarting synchronization process.
6. (MCC start - MCC stop) >= frame size.
7. b and a are integers less the BD table size.
Figure 31-14. Data Structure for ATM-to-TDM Adaptive Slip Control
31.5.1 CES Adaptive Threshold Tables
thresholds on a per-VC basis. The CES adaptive threshold base (CATB), located in the AAL1 CES
parameter RAM, points to the base address of these tables. Each AAL1-MCC channel has its own table
with a starting address given by CATB + RCT[Super_Channel_Number]# × 8.
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0
7
8
15
Offset + 0x00
Offset + 0x02
Offset + 0x04
Offset + 0x06
—
CES Adaptive Counter
ATM Stop Threshold
MCC Stop Threshold
ATM Start Threshold
MCC Start Threshold
—
Figure 31-15. CES Adaptive Threshold Table
Table 31-2 describes CES adaptive threshold table fields.
Table 31-2. CES Adaptive Threshold Table Field Descriptions
1
Offset
Bits Name
0-7
Description
0x00
—
Reserved, should be cleared during initialization.
8-15 CESAC CES adaptive counter.This field contains the difference between the ATM write pointer and
the MCC read pointer on the common BD table.This field should be cleared by the user
during the channel initialization.
0x02
0x04
0-7
ASTP
ATM stop threshold.This threshold determines the maximum amount of buffering (CDVT)
this value a pre-overrun condition occurs.This field should be defined by the user during the
channel initialization.
8-15 ASTRT ATM start threshold.This threshold determines the Time interval that will take the ATM
condition.This field should be defined by the user during the channel initialization.
0-7
MSTP
MCC stop threshold.This threshold determines the minimum amount of buffering in the
pre-underrun condition occur and the MCC starts to transmit the underrun template or the
by the user during the channel initialization.
8-15 MSTRT MCC start threshold.This threshold determines the effective depth of the jitter buffer, the
amount of buffering required to cope with the ATM network’s CDV (shown in
Figure 31-16).When the CESAC reaches this value the MCC transmitter starts sending the
valid data from the common BD table.This field should be defined by the user during the
channel initialization.
0x06
0-15
—
Reserved, should be cleared during initialization.
1
The offset is CATB + RCT[Super_Channel_Number]# × 8
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ATM AAL1 Circuit Emulation Service
ATM-to-TDM
BD table
MCC Tx pointer
0
BD 1
BD 2
BD 3
BD 4
BD 5
BD 6
BD 7
ATM Rx pointer
MCC_Start
0
0
0
0
0
0
Step 1:
Initialize the MCC and ATM pointers
to the same BD table.
CESAC=0
MCC_Start=3, MCC_Stop=1
ATM_Start=5, ATM_Stop=7-1=6
W
ATM-to-TDM
BD table
MCC Tx pointer
1
BD 1
BD 2
BD 3
BD 4
BD 5
BD 6
BD 7
1
1
0
0
0
0
Step 2:
MCC_Start
ATM Rx pointer
When CESAC reaches MCC_Start,
the MCC starts transmitting.
CESAC=3
MCC_Start=3, MCC_Stop=1
ATM_Start=5, ATM_Stop=7-1=6
W
Step 3:
ATM-to-TDM
BD table
Because the MCC is reading the data
faster than the ATM, CESAC falls to the
MCC_Stop threshold. The MCC pointer
0
BD 1
BD 2
BD 3
BD 4
BD 5
BD 6
BD 7
1
then freezes, and the current buffer is
0
0
0
1
0
0
retransmitted for a multiple of the frame
size. (The buffer size should be a multiple
of the frame size.)
CESAC=1
MCC_Start=3, MCC_Stop=1
ATM_Start=5, ATM_Stop=7-1=6
MCC Tx pointer
ATM Rx pointer
MCC_Start
W
1
The MCC can optionally transmit
the underrun template.
Step 4:
The MCC switches to pre-underrun
state and continues to send the current
buffer (the last buffer that was sent).
When CESAC reaches MCC_Start and
a multiple of complete frames has been
sent, the MCC starts to transmit again
(returns to Step 2 in this flow).
Figure 31-16. Pre-Underrun Sequence
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ATM AAL1 Circuit Emulation Service
ATM-to-TDM
BD table
MCC Tx pointer
0
BD 1
BD 2
BD 3
BD 4
BD 5
BD 6
BD 7
ATM Rx pointer
MCC_Start
0
0
0
0
0
0
Step 1:
Initialize the MCC and ATM pointers
to the same BD table.
CESAC=0
MCC_Start=3, MCC_Stop=1
ATM_Start=5, ATM_Stop=7-1=6
W
ATM-to-TDM
BD table
MCC Tx pointer
1
BD 1
BD 2
BD 3
BD 4
BD 5
BD 6
BD 7
1
1
0
0
0
0
Step 2:
MCC_Start
ATM Rx pointer
When CESAC reaches MCC_Start,
the MCC starts transmitting.
CESAC=3
MCC_Start=3, MCC_Stop=1
ATM_Start=5, ATM_Stop=7-1=6
W
ATM-to-TDM
BD table
0
BD 1
BD 2
BD 3
BD 4
BD 5
BD 6
BD 7
MCC Tx pointer
0
1
1
1
1
0
Step 3:
The MCC reads the data slower than
the ATM fills it. The ATM points to the
last BD in the common BD table.
CESAC=4
MCC_Start=3, MCC_Stop=1
ATM_Start=5, ATM_Stop=7-1=6
W
ATM Rx pointer
ATM Rx pointer
ATM-to-TDM
BD table
Step 4:
1
BD 1
BD 2
BD 3
BD 4
BD 5
BD 6
BD 7
The ATM wraps around, and CESAC
reaches the ATM_Stop threshold. The
ATM write pointer freezes on the
current BD.
The MCC continues to process the
valid data. When the CESAC falls to the
ATM_Start threshold, the ATM advances
to the first BD after EOSF.
MCC Tx pointer
0
1
1
1
1
1
ATM_Start
CESAC=6
W
Step 5:
After CESAC reaches the ATM_Start
threshold and the ATM advances to the
BD after EOSF, the ATM resynchronizes
and starts to receive valid data using
the new BD (start of SF).
Figure 31-17. Pre-Overrun Sequence
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ATM AAL1 Circuit Emulation Service
31.6 3-Step-SN Algorithm
The 3-step-SN algorithm is a fast and efficient state machine that has the ability to recover one lost or
misinserted cell. The 3-step-SN algorithm does not add significant delay to the AAL1 CES reassembly
process due to the fact that the decision to accept a cell is taken immediately after cell arrival. If a lost cell
is detected, the receiver will insert a dummy cell. If a misinserted cell is detected, the receiver will discard
the cell received after the misinserted cell. If more than one successive cell was lost or misinserted, the
3-step-SN algorithm will switch to hunt mode, where it stays until a cell with a valid SN field is received.
31.6.1 The Three States of the Algorithm
The 3-step-SN algorithm has three states:
1. Hunt—The Hunt state is the initial state of the algorithm or the first state after the receiver loses its
synchronization. In this state no cell is delivered to the Rx buffer. When a valid cell is detected, the
algorithm switches to the Sync state and delivers the current cell to the Rx buffer.
2. Sync—The Sync state is the steady state of the algorithm. In this state any received cell is
automatically passed to the Rx buffer. The algorithm will switch from this state when an invalid
cell is received (SNP error), or it receives a cell that does not sequence with the last valid cell (SC
error).
3. Sync Fail—The Sync Fail state is a transient state. In this state the receiver checks the difference
between the received sequence count (RSC) and the expected sequence count (ESC). If the
difference between the two (ESC-RSC) is -1, 0, or 1, the receiver switches to sync mode and either
discards the current cell, receives the current cell, or inserts a dummy cell, correspondingly. In any
other cases the receiver will switch to hunt mode and discard the current cell.
SYNC
SYNC
ESC = RSC
RSC = X
SYNC
ESC = RSC
RSC = X
ESC = RSC
RSC = X
ESC = RSC–1
ESC = RSC+1
ESC = RSC
Insert dummy cell
One cell was lost
Discard current cell
Misinserted cell
Received current cell
SNP fault
ESC: Expected sequence count.
RSC: Received sequence count.
RSN=X: Invalid cell received or, a cell that does not match to the ESC.
Figure 31-18. Recoverable Sync Fail sequence options
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No valid SN
Valid SN
Else
Hunt mode
Valid SN
ESC=RSC–1/0/1
Sync fail
Invalid SN or
out of sequence
Sync mode
Valid SN
Figure 31-19. 3-Step-SN-Algorithm
31.7 Pointer Verification Mechanism
After the 3-step-SN algorithm processes the incoming cells, the cells status (Valid, Tag, Drop or Dummy)
is delivered to the pointer verification mechanism. This state machine calculates the expected received
pointer. If the current cell is valid and supposed to deliver a pointer, the received pointer is compared with
the expected one. In the case of pointer mismatch or pointer error (i.e parity error), the pointer state
machine switches to “Pre-Hunt-Mode”. If the cell status is not valid (i.e Tag, Drop or Dummy) and it
supposed to carry a pointer, the pointer declared a mismatch and the pointer state machine switches to
“Pre-Hunt-Mode”. The receiver stays in this transient state for only one AAL1 cell cycle (8 successive
cells). When the pointer received in this state is different from the expected one or had a non-valid status,
the receiver switches to hunt mode where it stays until a valid cell with a “start” structured pointer is
received to regain synchronization.
Note that a “start” pointer is a valid pointer with a value not equal to 93 or 127.
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ATM AAL1 Circuit Emulation Service
Pointer mismatch/error
Missing pointer
No pointer
Hunt mode
Valid pointer
new structured
Valid pointer
Pre-hunt mode
Pointer mismatch/error
Missing pointer
Sync mode
Valid pointer
Figure 31-20. Pointer verification mechanism
31.8 AAL-1 Memory Structure
The CPM manages ATM traffic by means of transmit and receive buffer descriptors (BD) and by transmit
and receive connection tables (referred to as TCTs and RCTs, respectively). Buffer descriptors are circular
lists of pointers into transmit and receive buffer space in external memory. The following sections describe
the organization and configuration of the buffer descriptors, TCTs, and RCTs.
31.8.1 AAL1 CES Parameter RAM
The PowerQUICC II parameter RAM is used to configure the three FCCs. The CP also uses the parameter
RAM to store operational and temporary values. When configured for ATM mode, PowerQUICC II
overlays the configuration structures shown in the next tables. The following table includes fields for ATM
operation generally and AAL1 CES fields particularly.
Note that some of the values must be initialized by the user; values set by the CP should not be modified
by the user.
Table 31-3. AAL1 CES Field Descriptions
Offset
Name
Width
Description
0x00–
0x3F
—
—
Reserved, should be cleared during initialization.
0x40
0x42
RCELL_TMP_BASE
TCELL_TMP_BASE
Hword Rx cell temporary base address. Points to a total of 64 bytes reserved
dual-port RAM area used by the CP. Should be 64 byte aligned.
User-defined. (recommended address space: 3000h-4000h or
b000h-c000h)
Hword Tx cell temporary base address. Points to total of 64 bytes reserved
dual-port RAM area used by the CP. Should be 64-byte aligned.
User-defined.
(recommended address space: 3000h-4000h or b000h-c000h)
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Table 31-3. AAL1 CES Field Descriptions (continued)
Width Description
Offset
Name
0x44
UDC_TMP_BASE
Hword UDC mode only. Points to a total of 32 bytes reserved dual-port RAM
area used by the CP. Should be 64-byte aligned. User-defined.
(recommended address space: 3000h-4000h or b000h-c000h)
0x46
0x48
0x4A
INT_RCT_BASE
INT_TCT_BASE
INT_TCTE_BASE
Hword Internal receive connection table base. User-defined.
Hword Internal transmit connection table base. User-defined.
Hword Internal transmit connection table extension base. User-defined. Note
that the TCT extension is not needed in AAL1 CES and that the AAL1
CES microcode uses this Hword to point to a CAS routing table.
0x4C
0x50
0x54
0x58
—
Word Reserved, should be cleared during initialization.
Word External receive connection table base. User-defined.
Word External transmit connection table base. User-defined.
EXT_RCT_BASE
EXT_TCT_BASE
EXT_TCTE_BASE
Word External transmit connection table extension base. User-defined. Note
that the TCT extension is not needed in AAL1 CES and that the AAL1
CES microcode uses this Hword to point to a CAS routing table.
0x5C
UEAD_OFFSET
Hword User-defined cells mode only. The offset of the UEAD entry in the UDC
extra header. Should be an even address. If RCT[BO]=01
UEAD_OFFSET should be in little-endian format. For example if UEAD
entry is the first half word of the extra header in external memory,
UEAD_OFFSET should be set to 2 (second half word entry in internal
RAM).
0x5E
0x60
0x62
0x64
0x66
0x5E
0x6A
0x6C
—
Hword Reserved, should be cleared during initialization.
Hword Performance monitoring table base. User-defined.
Hword APC parameters table base address. User-defined.
Hword Free buffer pool parameters table base. User-defined.
Hword Interrupt queue parameters table base. User-defined.
PMT_BASE
APCP_BASE
FBT_BASE
INTT_BASE
—
—
Reserved, should be cleared during initialization.
UNI_STATT_BASE
BD_BASE_EXT
Hword UNI statistics table base. User-defined.
Word BD table base address extension. BD_BASE_EXT[0–7] holds the 8 left
bits of the Rx/Tx BD table base address. BD_BASE_EXT[8–31] should
be zero. User-defined.
0x70
VPT_BASE /
EXT_CAM_BASE
Word Base address of the address compression VP table/external CAM.
User-defined.
0x74
0x78
VCT_BASE
Word Base address of the address compression VC table. User-defined.
VPT1_BASE /
EXT_CAM1_BASE
Word Base address of the address compression VP1 table/EXT CAM1.
User-defined.
0x7C
0x80
VCT1_BASE
VP_MASK
Word Base address of the address compression VC1 table. User-defined.
Hword VP mask for address compression lookup. User-defined.
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Table 31-3. AAL1 CES Field Descriptions (continued)
Width Description
Offset
Name
VCI_Filtering
0x82
Hword VCI filtering enable bits. When cells with VCI = 3, 4, 6, 7-15 are received
and the associated VCI_Filtering bit = 1 the cell is sent to the raw cell
queue. VCI=3 is associated with VCI_Filtering[3], VCI=15 is associated
with VCI_Filtering[15]. VCI_Filtering[0–2, 5] should be zero. See
0x84
GMODE
0x86
0x88
0x8A
0x8C
0x90
0x94
0x98
COMM_INFO
Hword The information field associated with the last host command.
Hword
Hword
Reserved
Word Reserved, should be cleared during initialization.
Word Preset for CRC32. Initialize to 0xFFFFFFFF.
Word Constant mask for CRC32. Initialize to 0xDEBB20E3.
CRC32_PRES
CRC32_MASK
AAL1_SNPT_BASE
Hword AAL1 SNP protection look up table base address. (AAL1 and AAL1 CES
only.) The 32-byte table resides in dual-port RAM and must be initialized
by the user (See Section 31.14, “AAL1 Sequence Number (SN)
0x9A
0x9C
—
Hword Reserved, should be cleared during initialization.
SRTS_BASE
Word External SRTS logic base address. (AAL1and AAL1 CES only.) Should
be 16-byte aligned.
0xA0
IDLE/UNASSIGN_BASE Hword Idle/unassign cell base address. Points to dual-port RAM area contains
idle/unassign cell template (little-endian format). Should be 64-byte
aligned. User-defined. The ATM header should be 0x0000_0000 or
0x0100_0000 (CLP=1).
0xA2
0xA4
0xA8
IDLE/UNASSIGN_SIZE Hword Idle/Unassign cell size. 52 in regular mode. 53–64 in UDC mode.
EPAYLOAD
Trm
Word Reserved payload. Initialize to 0x6A6A6A6A.
Word (ABR only) The upper bound on the time between F-RM cells for an active
source. TM 4.0 defines the Trm period as 100 msec. The Trm value is
defined by the system clock and the time stamp timer prescaler (See
RTSCR). For time stamp prescalar of 1µS, Trm should be set to 100
ms/1µs = 100,000.
0xAC
0xAE
0xB0
Nrm
Mrm
TCR
Hword (ABR only) Controls the maximum cells the source may send for each
F-RM cell. Set to 32 cells.
Hword (ABR only) Controls the bandwidth between F-RM, B-RM and user data
cell. Set to 2 cells.
Hword (ABR only) Tag cell rate. The minimum cell rate allowed for all ABR
channels. An ABR channel whose ACR is less then TCR sends only
out-of-rate F-RM cells at TCR. Should be set to 10 cells/sec as defined in
the TM 4.0. Uses the ATMF TM 4.0 floating-point format. Note that the
APC minimum cell rate should be at least TCR.
0xB2
ABR_RX_TCTE
Hword (ABR only) Points to total of 16 bytes reserved dual-port RAM area used
by the CP. Should be 16 byte aligned. User-defined.
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ATM AAL1 Circuit Emulation Service
Additional CES parameters needed by the AAL1 microcode are described in the following table.
Table 31-4. AAL1 CES Parameters
Offset
Name
Width Description
0x4A
INT_RTCRT_BASE Hword Internal receive/transmit CAS routing table extension base. User-defined. Note
that because AAL1 CES does not need the TCT extension, the AAL1 CES
microcode uses this Hword to point to a CAS routing table. Should be 32 byte
aligned. User-defined.
0x58
EXT_RTCRT_BASE Word External receive/transmit CAS routing table extension base. User-defined. Note
that because AAL1 CES does not need the TCT extension, the AAL1 CES
microcode uses this word to point to a CAS routing table.
0xB2
0xd0
0xE0
AAL1_INT_RX_CRT Hword (CES only) Points to a reserved scratchpad area of 32 bytes in the dual-port
RAM used by the CES microcode. Should be 32 byte aligned. User-defined.
OCASSR
Byte
Outgoing CAS Status Register. See Section 31.10, “Outgoing CAS Status
TCELL_TMP_BASE Word Transmit Cell Temporary base address (64-byte aligned). Points to an external
_EXT
memory block reserved for partially filled cells (64 octets for each CES
channel). This area is allocated by the user but used by the CP.
0xE4
0xE6
0xE8
ASE Should be 32-byte aligned. User-defined.
BASE Should be 32-byte aligned. User-defined.
AAL1_Int_STATT_B Hword AAL1 Internal Statistics Table Base. Points to dual-port RAM. Should be 16-byte
ASE
aligned. User-defined. See Section 31.15, “Internal AAL1 CES Statistics
0xEA
0xEC
AAL1_DUMMY_CEL Hword ALL1 Dummy cell base address. Points to dual-port RAM area contains the
L_BASE
AAL1 dummy cell template (little-endian format). Should be 64-byte aligned.
User-defined.
CATB
Hword CES adaptive threshold tables base address. Points to the dual-port RAM area
containing the CES slip control thresholds and the adaptive counter See
(8 octets for each AAL1-MCC channel). User-defined and should match the
0xF0
AAL1_Ext_STATT_B Word AAL1 External Statistics Table Base. Points to External memory. Should be
ASE
16-byte aligned (16 octets for each AAL1 channel).User-defined. See
31.9 Receive and Transmit Connection Tables
(RCT, TCT)
The connection tables, RCT and TCT, hold channel configuration and temporary parameters for each
receive and transmit channel (AAL type, connection traffic parameters, BDs’ parameters and temporary
parameters used during segmentation and reassembly).
The internal connection tables hold parameters for up to 128 channels (channels 0–127). In extended
channel mode, parameters for channels 256 and above are kept in external memory. The only relationship
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ATM AAL1 Circuit Emulation Service
between transmit and receive connection tables of the same channel is the CRT (CAS routing table); see
Each connection table entry resides in 32 bytes. The pointers to these connection tables reside in the
parameter RAM.
31.9.1 Receive Connection Table (RCT)
Figure 31-21 shows the format of an RCT entry.
0
1
2
3
4
5
6
7
8
9
10
11
12
—
13
14 15
INTQ
Offset + 0x00
Offset + 0x02
Offset + 0x04
Offset + 0x06
Offset + 0x08
Offset + 0x0A
Offset + 0x0C
Offset + 0x0E
Offset + 0x10
Offset + 0x12
Offset + 0x14
Offset + 0x16
Offset + 0x18
Offset + 0x1A
Offset + 0x1C
Offset + 0x1E
—
GBL
BO
—
DTB BIB
—
—
SEGF ENDF
SYNC
CASM ABRF
AAL
RX Data Buffer Pointer (RXDBPTR)
Cell Time Stamp
RBD_Offset
MRBLR
—
PMT
RBD_BASE
CCASM CESM
RBD_BASE
—
PM
Figure 31-21. Receive Connection Table (RCT) Entry
NOTE
For an active channel, the CP uses a burst cycle to fetch the 32-byte RCT
and writes back only the first 24 bytes.
Table 31-5 describes RCT fields.
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Table 31-5. RCT Field Descriptions
Offset Bits
Name
Description
0x00
0–1
2
—
Reserved, should be cleared during initialization.
GBL
Global. Asserting GBL enables snooping of data buffers, BD, interrupt queues and free
buffer pool.
3–4
BO
Byte ordering—used for data buffers.
00 Reserved
01munged little endian
1x Big endian
5
6
—
Reserved, should be cleared during initialization.
DTB
Data buffers bus
0 Data buffers reside on the 60x bus.
1 Data buffers reside on the local bus.
7
BIB
BD interrupt queues, free buffer pool, and CES external statistics tables bus placement
0 Reside on the 60x bus.
1 Reside on the local bus.
Notes:
1. When in UDC mode (AAL5 or AAL1 or AAL1 CES), BDs and data should be placed
on the same bus (RCT[DTB]=RCT[BIB]).
2. RCT[BIB] programming must be consistent across all CES receive channels
because they share the same AAL1_Ext_STATT_BASE parameter.
8–9
10
—
Reserved, should be cleared during initialization.
SEGF
OAM F5 segment filtering
0 Do not send cells with PTI=100 to the raw cell queue.
1 Send cells with PTI=100 to the raw cell queue.
11
ENDF
OAM F5 end-to-end filtering
0 Do not send cells with PTI=101 to the raw cell queue.
1 Send cells with PTI=101 to the raw cell queue.
12
13
—
Reserved, should be cleared during initialization.
SYNC
AAL1 SYNC. The user should set this bit for first AAL1 synchronization. Used internally
by the CP.
14–15 INTQ
Points to one of four interrupt queues available.
Internal use only. Initialize to 0.
0x02
0-3
—
4–10
11
—
Internal use only. Initialize to 0.
CASM
Common associated signaling mode.
0
CAS operation mode is disable.
1 CAS operation mode is enable.
12
—
Reserved, should be cleared during initialization.
13–15 AAL
AAL type
000 AAL0 —Reassembly with no adaptation layer
001 AAL1 —ATM adaptation layer 1
010 AAL5 —ATM adaptation layer 5
101 AAL1_CES —ATM adaptation layer 1 with circuit emulation service
All others reserved.
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Table 31-5. RCT Field Descriptions (continued)
Offset Bits
Name
Description
0x04
0x08
—
—
RxDBPTR
Receive data buffer pointer. Holds real address of current position in the Rx buffer.
Cell Time
Stamp
Used for reassembly time-out. Whenever a cell is received, the PowerQUICC II time
stamp timer is sampled and written to this field. See Section 14.3.8, “RISC
0x0C
—
RBD_Offset RxBD offset from RBD_BASE. Points to the channel’s current BD. User-initialized to 0;
updated by the CP.
0x0E-0
x18
—
Protocol-specific area.
0x1A
—
MRBLR
Maximum receive buffer length. Used in both static and dynamic buffer allocation.
Note that in CES mode (CESM=1) this value must be a multiple of 8 (MCC limited).
0x1C
0–1
2–7
—
Reserved, should be cleared during initialization.
PMT
Performance monitoring table. Points to one of the available 64 performance
monitoring tables. The starting address of the table is PMT_BASE+PMT × 32. Can be
changed on-the-fly.
8–15 RBD_BASE RxBD base. Points to the first BD in the channel’s RxBD table. The 8 most-significant
bits of the address are taken from BD_BASE_EXT in the parameter RAM. The four
0x1E
0–11
least-significant bits of the address are taken as zeros.
12
CCASM
Core CAS modify. When this mode is enabled, the CP sets OCASSR[MCASBn] sticky
bit each time the outgoing (ATM to TDM) CAS block is changed.
0
Core CAS modify mode is disabled.
1 Core CAS modify mode is enabled.
13
CESM
Circuit Emulation Service Mode.
0
CES operation mode is disable. Adaptive Slip control mechanism is disabled.
1 CES operation mode is enable. Adaptive Slip control mechanism is enabled.
14
15
—
Reserved, should be cleared during initialization.
PM
Performance monitoring. Can be changed on-the-fly.
0 No performance monitoring for this VC.
1 Perform performance monitoring for this VC. Whenever a cell is received for this VC
the performance monitoring table that its code is written in the PMT field is updated.
31.9.1.1 AAL1 CES Protocol-Specific RCT
Figure 31-22 shows the AAL1 CES protocol-specific area of an RCT entry.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Offset + 0x0E
Offset + 0x10
SRTS_DEV
OCASB/SRTS_TMP
—
PFM
SRT INVE STF
Valid Octet Size (VOS)
Structured Pointer (SP)
RBDCNT
—
—
—
Offset + 0x12 SPV
Offset + 0x14
—
Figure 31-22. AAL1 CES Protocol-Specific RCT
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Offset + 0x16
Offset + 0x18
Block Size
Super Channel Number
Figure 31-22. AAL1 CES Protocol-Specific RCT
SN
CASBS
—
RXBM
SLIPIM
—
Table 31-6 describes AAL1 CES protocol-specific RCT fields.
Table 31-6. AAL1 CES Protocol-Specific RCT Field Descriptions
Offset Bits
Name Description
0x0E
0–3
SRTS_DEV Selects an SRTS device, whose address is SRTS_BASE[0–27] + SRTS_DEV[28–31].
The 16 byte-aligned SRTS_BASE is taken from the parameter RAM.
4–7
8
—
Reserved, should be cleared during initialization.
PFM
Partially filled mode.
0 Partially filled cells mode is not used.
1 Partially filled cells mode is used. The receiver copies only valid octets from the AAL1
cell to the Rx buffer. The number of the valid octets from the beginning of the AAL1
user data field is specified in the VOS (valid octet size) field.
9
SRT
Synchronous residual time stamp. Unstructured format only. The PowerQUICC II
supports clock recovery using an external SRTS PLL. The PowerQUICC II tracks the
SRTS from the incoming four cells with SN = 1, 3, 5, and 7 and writes it to the external
SRTS device. Every eight cells the CP writes a valid SRTS to external logic. (See
0 SRTS mode is not used.
1 SRTS mode is used.
10
11
INVE
STF
Inverted empty.
0 RxBD[E] is interpreted normally (1 = empty, 0 = not empty).
1 RxBD[E] is handled in negative logic (0 = empty, 1 = not empty).
Note that in CAS mode (CESM=1) this bit must be set by the user; see Section 31.4.1,
Structured format.
0 Unstructured format is used.
1 Structured format is used.
Note that although the structured format may be used, if the block size is one, the user
should clear STF. Only non P-format AAL1 cells are received. The receiver does not
check the AAL1 structured pointer because there is no need to when the block size is one.
12-15
0–3
—
Reserved, should be cleared during initialization.
0x10
OCASB/SR OCASB applies when in CAS mode. Outgoing CAS Block. Points to one of the eight
TS_TMP
available internal CAS blocks. The starting address of the table is
more details.
Note that the RCT and TCT use the same CAS routing table (CRT).
SRTS_TMP applies when not in CAS mode. Used by the CP to store the received SRTS
code. After a cell with SN = 7 is received, the CP writes the SRTS code to the external
SRTS device.
Note that when the receiver is in hunt mode SRTS information is not updated.
4–9
—
Reserved, should be cleared during initialization.
10–15 VOS
Valid octet size. Specifies the number of valid octets from the beginning of the AAL1 user
data field. For unstructured, service values 1–47 are valid; for structured service, values
1-46 are valid. Partially filled cell mode only.
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ATM AAL1 Circuit Emulation Service
Table 31-6. AAL1 CES Protocol-Specific RCT Field Descriptions (continued)
Offset Bits
Name
SPV
Description
0x12
0
Structured pointer valid. Should be user-initialized user to zero. Structured format only.
Reserved, should be cleared during initialization.
1–3
—
4–15 SP
Structured pointer. Used by the CP to calculate the structured pointer. This field should
be initialized by the user to zero. Used in structured format only.
0x14
0x16
—
RBDCNT
RxBD count. Indicates how many bytes remain in the current Rx buffer. Initialized with
MRBLR whenever the CP opens a new buffer.
0–11 Block Size Used only in structured format. Specifies the structured block size (Block Size = 0xFFF =
4 Kbytes maximum).
Note that when working in CAS mode (CESM=1 and CASM=1), the block size should be
programmed to the superframe block size plus the size of the CAS block. However, when
working in basic mode (CES without CAS: CESM=1 and CASM=0) the block size should
be programmed to the number of MCC slots (Nx64) per frame assigned to this channel.
12
—
Reserved, should be cleared during initialization.
13–15 SN
Sequence number. Used by the CP to check incoming cell’s sequence number.
0x18
0-7
8
SCN
Super Channel Number.
This field should contain the MCC Super Channel Number that mapped to this ATM
channel. This field must be initialized by the user in CES mode only. See
RXBM
Receive buffer interrupt mask
0 The receive buffer event of this channel is disabled. (The event is not sent to the
interrupt queue.)
1 The receive buffer event of this channel is enabled.
9
SLIPIM
Slip interrupt mask
0 The slip interrupts SLIPS and SLIPE are both masked.
1 When the receiver switches to hunt mode due to a 3-step-SN algorithm fault, or due to
two successive mismatched pointers, or due to a pre-overrun condition, the SLIPS
interrupt is sent to the interrupt queue. Note that this is the error reporting mechanism
during automatic data forwarding (ATM-to-TDM bridging).
10-11
—
Reserved, should be cleared during initialization.
12-15 CASBS
CAS block size.This field contains the number divided by two (N/2) of signaling nibbles
Blocks.”
Note that if the number of signaling nibbles is odd, this field should be programmed to
Example: ESF with three T1 time slots connected to one ATM channel. The Data_Size
= 3*24 = 72 octets and the CAS Block= 2 octets (N=3, (N+1)/2 = 2), so in this case the
Block_Size = 72+2 = 74
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ATM AAL1 Circuit Emulation Service
31.9.2 Transmit Connection Table (TCT)
Figure 31-23 shows the format of an TCT entry.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Offset + 0x00
Offset + 0x02
Offset + 0x04
Offset + 0x06
Offset + 0x08
Offset + 0x0A
Offset + 0x0C
Offset + 0x0E
Offset + 0x10
Offset + 0x12
Offset + 0x14
Offset + 0x16
Offset + 0x18
Offset + 0x1a
Offset + 0x1C
Offset + 0x1E
—
GBL
BO
—
DTB BIB
—
—
ATT
AVCF VCON
INTQ
AAL
Tx Data Buffer Pointer (TXDBPTR)
TBDCNT
TBD_OFFSET
Rate Remainder
PCR Fraction
PCR
APC Linked Channel
ATM Cell Header (VPI,VCI,PTI,CLP)
—
PMT
TBD_BASE
Figure 31-23. Transmit Connection Table (TCT) Entry
TBD_BASE
BNM STPT IMK PM
Table 31-7 describes general TCT fields.
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ATM AAL1 Circuit Emulation Service
Table 31-7. TCT Field Descriptions
Offset Bits
Name
Description
0x00
0–1
2
—
Reserved, should be cleared during initialization.
GBL
Global. Asserting GBL enables snooping of data buffers, BDs, interrupt queues and free
buffer pool.
3–4
BO
Byte ordering. This field is used for data buffers.
00 Reserved.
01 Power PC little endian.
1x Big endian.
5
6
—
Reserved, should be cleared during initialization.
DTB
Data buffer and CES transmit cell scratchpad bus placement
0 Reside on the 60x bus.
1 Reside on the local bus.
Note: TCT[DTB] programming must be consistent across all CES transmit channels
because they share the same TCELL_TMP_BASE_EXT parameter.
7
BIB
BD and interrupt queue bus
0 Reside on the 60xbus.
1 Reside on the local bus.
Note: When using AAL5, AAL1 or AAL1 CES in UDC mode, BDs and data should be
placed on the same bus (TCT[DTB]=TCT[BIB]).
8-9
—
Reserved, should be cleared during initialization.
10-11
ATT
ATM traffic type
00 Peak cell-rate pacing. The host must initialize PCR and the PCR fraction. Other
traffic parameters are not used.
01 Peak and sustain cell rate pacing (VBR traffic). The APC performs a
continuous-state leaky bucket algorithm (GCRA) to pace the channel-sustain cell
rate. The host must initialize PCR, PCR fraction, SCR, SCR fraction, and BT (burst
tolerance).
10 Peak and minimum cell rate pacing (UBR+ traffic). The host must initialize PCR, PCR
fraction, MCR, MCR fraction, and MDA.
11 Reserved.
12
AVCF
Auto VC off. Determines APC behavior when the last buffer associated with this VC has
been sent and no more buffers are in the VC’s TxBD table,
0 The APC does not remove this VC from the schedule table and continues to schedule
it to transmit.
1 The APC removes this VC from the schedule table. To continue transmission after the
host adds buffers for transmission, a new ATM TRANSMIT command is needed, which
can be issued only after the CP clears the VCON bit. (Bit 13)
13
VCON
INTQ
Virtual channel is on
Should be set by the host before it issues an ATM TRANSMIT command. When the host
sets TCT[STPS] (stop transmit), the CP deactivates this channel and clears VCON
when the channel is next encountered in the APC scheduling table. The host can issue
another ATM TRANSMIT command only after the CP clears VCON.
14–15
Points to one of four interrupt queues available.
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ATM AAL1 Circuit Emulation Service
Table 31-7. TCT Field Descriptions (continued)
Offset Bits
Name
Description
0x02
0-12
—
Reserved, should be cleared during initialization.
13–15
AAL
AAL type
000 AAL0 —Reassembly with no adaptation layer
001 AAL1 —ATM adaptation layer 1
010 AAL5 —ATM adaptation layer 5.
101 AAL1_CES —ATM adaptation layer 1 with circuit emulation service
All others reserved.
0x04
0x08
—
—
TxDBPTR Tx data buffer pointer. Holds the real address of the current position in the Tx buffer.
TBDCNT
Transmit BD count. Counts the remaining data to transmit in the current transmit buffer.
Its initial value is loaded from the data length field of the TxBD when a new buffer is
open; its value is subtracted for any transmitted cell associated with this channel.
0x0A
0x0C
—
TBD_Offset Transmit BD offset. Holds offset from TBD_BASE of the current BD. Initialize to 0.
0–7
Rate
Rate remainder. Used by the APC to hold the rate remainder after adding the pace
fraction to the additive channel rate. Initialize to 0.
Reminder
8–15 PCR Fraction Peak cell rate fraction. Holds the peak cell rate fraction of this channel in units of 1/256
slot. If this is an ABR channel, this field is automatically updated by the CP.
0x0E
—
PCR
Peak cell rate. Holds the peak cell rate (in units of APC slots) permitted for this channel
according to the traffic contract. Note that for an ABR channel, the CP automatically
updates PCR to the ACR value.
0x10
0x16
0x18
—
—
—
—
Protocol-specific
APCLC
ATMCH
APC linked channel. Used by the CP. Initialize to 0 (null pointer).
ATM cell header. Holds the full (4-byte) ATM cell header of the current channel. The
transmitter appends ATMCH to the cell payload during transmission.
0x1C
0–1
2–7
—
Reserved, should be cleared during initialization.
PMT
Performance monitoring table. Points to one of the available 64 performance monitoring
tables. The starting address of the table is PMT_BASE+PMT × 32. Can be changed
on-the-fly.
8–15
0–11
TBD_BASE TxBD base. Points to the first BD in the channel’s TxBD table. The 8 most-significant
bits of the address are taken from BD_BASE_EXT in the parameter RAM. The four
least-significant bits of the address are taken as zero.
0x1E
12
13
14
15
BNM
STPT
IMK
Buffer-not-ready interrupt mask. Can be changed on-the-fly.
0 The transmit buffer-not-ready event of this channel is masked. (TBNR event is not
sent to the interrupt queue.)
1 The buffer-not-ready event of this channel is enabled.
Stop transmit. Initialize to 0. When the host sets this bit, the CP deactivates this channel
and clears TCT[VCON] when the channel is next encountered in the APC scheduling
table. Note that for AAL5 if STPT is set and frame transmission is already started
(TCT[INF]=1), an abort indication will be sent (last cell with zero length field).
Interrupt mask. Can be changed on-the-fly.
0 The transmit buffer event of this channel is masked. (TXB event is not sent to the
interrupt queue.)
1 The transmit buffer event of this channel is enabled.
PM
Performance monitoring. Can be changed on-the-fly.
0 No performance monitoring for this VC.
1 Performance is monitored for this VC. When a cell is sent for this VC, the performance
monitoring table indicated in PMT field is updated.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
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31-33
ATM AAL1 Circuit Emulation Service
31.9.2.1 AAL1 CES Protocol-Specific TCT
Figure 31-24 shows the AAL1 CES protocol-specific transmission connection tables (TCT).
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Offset + 0x10
Offset + 0x12
Offset + 0x14
—
Valid Octet Size (VOS)
PFM SRT SPIF STF
Block Size
—
SN
SRTS_DEV
ICASB/SRTS_TMP
Structured Pointer (SP)
Figure 31-24. AAL1 CES Protocol-Specific TCT
Table 31-8 describes AAL1 CES protocol-specific TCT fields.
Table 31-8. AAL1 CES Protocol-Specific TCT Field Descriptions
Offset Bits
Name
Description
0x10
0-1
—
Reserved, should be cleared during initialization.
2–7
VOS
PFM
Valid octet size. Partially filled cell mode only. Specifies the number of valid octets from
the beginning of the AAL1 user data field. For unstructured service, values 1-47 are
valid; for structured service, values 1-46 are valid.
8
9
Partially filled mode.
0 Partially filled cells mode is not used.
1 Partially filled cells mode is used. The transmitter copies only valid octets from the
buffer to the AAL1 cell. The size of the valid octets from the beginning of the AAL1
user data field is specified in the VOS (valid octet size) field.
SRT
Synchronous residual time stamp. Unstructured format only. The PowerQUICC II
supports SRTS generation using external logic. If this mode is enabled, the
PowerQUICC II reads the SRTS from external logic and inserts it into four cells for
which SN = 1, 3, 5, or 7. The PowerQUICC II reads the new SRTS from external logic
every eight cells. (See Section , “.”)
0 SRTS mode is not used.
1 SRTS mode is used.
10
11
SPIF
STF
Structured pointer inserted flag. Indicates that a structured pointer has been inserted
in the current cycle. The user should initialize this field to zero. Used by the CP only.
Structured format.
0 Unstructured format is used.
1 Structured format is used.
Note that although the structured format may be used, if the block size is one, the user
should clear STF so that only non P-format AAL1 cells are generated.
12
—
Reserved, should be cleared during initialization.
13–15 SN
0–3
Sequence number field. Used by the CP to check the incoming cells SN. Initialize to 0.
0x12
SRTS_DEV Used to select a SRTS device. The SRTS device address is
SRTS_BASE[0–27]+SRTS_DEV[28:31]. SRTS_BASE is taken from the parameter
RAM and is 16-byte aligned.
4–15 Block Size Used only in structured format. Specifies the structured block size (Block Size = 0xFFF
= 4 Kbytes maximum).
Note that when working in CAS mode (CESM=1 and CASM=1), the block size should
be programmed to the superframe block size plus the size of the CAS block. However,
when working in basic mode (CES without CAS: CESM=1 and CASM=0) the block size
should be programmed to the number of MCC slots (Nx64) per frame assigned to this
channel.
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ATM AAL1 Circuit Emulation Service
Table 31-8. AAL1 CES Protocol-Specific TCT Field Descriptions (continued)
Offset Bits Name Description
0x14 0–3 ICASB/SRT ICASB applies when in CAS mode. Incoming CAS Block. Points to one of the eight
S_TMP
available internal CAS block. The starting address of the table is
more details.
Note that the RCT and TCT use the same CAS routing table (CRT).
SRTS_TMP applies when not in CAS mode. Before a cell with SN = 1 is sent, the CP
reads the SRTS code from external SRTS logic, writes it to SRTS_TMP, and then
inserts SRTS_TMP into the next four cells with an odd SN.
4–15 SP
Structured pointer. Used by the CP to calculate the structured pointer. Initialize to 0.
Structured format only.
31.10 Outgoing CAS Status Register (OCASSR)
Figure 31-25 shows the layout of the outgoing CAS block status register (OCASSR).
0
7
8
9
10
11
12
13
14
15
Field
—
MCASB7 MCASB6 MCASB5 MCASB4 MCASB3 MCASB2 MCASB1 MCASB0
Figure 31-25. Outgoing CAS Status Register (OCASSR)
This status register contains sticky bits that give the software application an indication that the CP has
modified the associated CAS block. When the ATM receiver operates in core CAS modify mode
RCT[CCASM=1], the CP generates an interrupt and sets the appropriate sticky bit in OCASSR each time
an AAL1 cell is received with new signaling information (one or more signaling nibble has changed).
Note that this flag bit stays set until it is cleared by software. If new signaling is received and the relevant
sticky bit is already set, the CP updates the CAS block without generating another interrupt.
Table 31-9 describes OCASSR fields.
Table 31-9. OCASSR Field Descriptions
Bits
Name
Description
Reserved, should be cleared during initialization.
0–7
—
8, 9, MCASBn Modify CAS Block n.
10, 11,
12, 13,
14, 15
When the CP updates this outgoing CAS block, it sets the MCASBn sticky bit and generates an
interrupt to notify the core that the signaling information has changed in block n. Each channel
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31-35
ATM AAL1 Circuit Emulation Service
31.11 Buffer Descriptors
The AAL1 CES controller operates as a multi-channel protocol, performing simultaneous segmenting and
reassembling of transmit and receive data, to and from different sets of memory buffers for all channels.
This behavior makes it necessary to have a separate list of BDs for each channel. Each channel is
configured with two BD lists: one for transmit and the other for receive operations. The amount of BDs’
in the table is defined by the user.
The BD table is a circular list, the last BD in the table holds a wrap indication. When the PowerQUICC II
reaches the last BD, it returns to the head of the list. Each BD in the TxBD table points to a buffer to send.
At the receive side, the user allocates dedicated buffers to each channel (that is, one BD for each buffer).
When the receiver or transmitter completes writing or reading the buffer, it moves to the next buffer in the
list and optionally issues an interrupt.
31.11.1 Transmit Buffer Operation
The user prepares a table of BDs pointing to the buffers to be sent. The address of the first BD is put in the
channel’s TCT[TBD_BASE]. The transmit process starts when the core issues an atm transmit command.
The CP reads the first TxBD in the table and sends its associated buffer. When the current buffer is
finished, the CP increments TBD_OFFSET, which holds the offset from TBD_BASE to the current BD.
It then reads the next BD in the table. If the BD is ready (TxBD[R] = 1), the CP continues sending. If the
current BD is not ready, the CP polls the ready bit at the channel rate unless TCT[AVCF] = 1, in which
case the CP removes the channel from the APC and clears TCT[VCON]. The core must issue a new atm
transmit command to restart transmission.
Note that when the ATM transmitter is in CES mode, the buffer-not-ready state is ignored by the ATM
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ATM AAL1 Circuit Emulation Service
BD memory space
Data memory space
Tx BD table
of ch 1
Tx buffer 1 of
channel 1
TBD_Base
TBD_Offset
Pointers
from ch 1
entry of
TCT
TxBD 1
TxBD 2
TxBD 3
TxBD 4
TxBD 5
TxBD 6
Tx buffer 3 of
channel 1
•
•
Tx buffer 4 of
channel 1
•
Tx buffer 1 of
channel 4
Tx BD table
of ch 4
TBD_Base
TxBD 1
TxBD 2
TxBD 3
Tx buffer 2 of
channel 1
Pointers
from ch 4
entry of
TCT
Tx buffer 2 of
channel 4
TxBD 4
TxBD 5
TxBD 6
TxBD 7
TxBD 8
TxBD 9
•
•
•
Tx buffer 3 of
channel 4
TBD_Offset
Tx buffer 8 of
channel 4
Figure 31-26. Transmit Buffers and BD Table Example
31.11.2 Receive Buffer Operation
The user prepares a table of BDs pointing to the receive buffers. The address of the first BD is put in the
channel’s RCT[RBD_BASE]. When an ATM cell arrives, the CP opens the first BD in the table and starts
filling its associated buffer with received data. When the current buffer is full, the CP increments
RBD_OFFSET, which is the offset to the current BD from RBD_BASE, and reads the next BD in the table.
If the BD is empty (RxBD[E] = 1), the CP continues receiving. If the BD is not empty, a busy condition
has occurred and the ATM receiver optionally issues an interrupt to the event queue.
Note that when the ATM receiver is in CES mode, the buffer-not-ready (busy) state is handled by an
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
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ATM AAL1 Circuit Emulation Service
BD memory space
Data memory space
Rx BD table
of ch 1
Rx buffer 1 of
channel 1
RBD_Base
RBD_Offset
Pointers
from ch 1
entry of
RCT
RxBD 1
RxBD 2
RxBD 3
RxBD 4
RxBD 5
RxBD 6
Rx buffer 3 of
channel 1
•
•
Rx buffer 4 of
channel 1
•
Rx buffer 1 of
channel 4
Rx BD table
of ch 4
RBD_Base
RxBD 1
RxBD 2
RxBD 3
Rx buffer 2 of
channel 1
Pointers
from ch 4
entry of
RCT
Rx buffer 2 of
channel 4
RxBD 4
RxBD 5
RxBD 6
RxBD 7
RxBD 8
RxBD 9
•
•
•
Rx buffer 3 of
channel 4
RBD_Offset
Rx buffer 8 of
channel 4
Figure 31-27. Receive Buffers and BD Table Example
31.12 ATM Controller Buffers
Table 31-10. Receive and Transmit Buffers
Receive
Transmit
AAL
Size
Alignment
Size
Alignment
AAL5
Multiple of 48 octets (except last buffer in frame) Double word aligned Any
No requirement
AAL3/4 At least 44 octets (except last buffer in frame)
Double word aligned At least 44 octets No requirement
AAL1/ Multiple of 8 octets
AAL1
CES
No requirement
Burst-aligned
Multiple of 8 octets No requirement
AAL0
52-64 octets.
52–64 octets.
No requirement
31.12.1 AAL1 CES RxBD
Figure 31-28 shows the AAL1 CES RxBD.
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ATM AAL1 Circuit Emulation Service
0
1
2
3
4
5
6
7
8
9
10
11
15
Offset + 0x00
Offset + 0x02
Offset + 0x06
Offset + 0x08
E
—
W
I
—
—
CM
—
—
EOSF
—
Data Length
Rx Data Buffer Pointer
Figure 31-28. AAL1 CES RxBD
Table 31-11 describes AAL1 CES RxBD fields.
Table 31-11. AAL1 CES RxBD Field Descriptions
Offset Bits
Name
Description
0x00
0
E
Empty.
0 The buffer associated with this RxBD is filled with received data or data reception was
aborted due to an error. The core can read or write any fields of this RxBD. The CP
cannot use this BD again while E = 0.
1 The buffer is not full. This RxBD and its associated receive buffer are owned by the CP.
Once E is set, the core should not write any fields of this RxBD.
1
2
—
W
—
Wrap (final BD in table)
0 This is not the last BD in the RxBD table of the current channel.
1 This is the last BD in the RxBD table of this current channel. After this buffer is used, the
CP receives incoming data into the first BD in the table. The number of RxBDs in this
table is programmable and is determined only by the W bit. The current table overall
space is constrained to 64 Kbytes.
3
I
Interrupt
0 No interrupt is generated after this buffer has been used.
1 An Rx buffer event is sent to the interrupt queue after the ATM controller uses this buffer.
FCCE[GINTx] is set when the INT_CNT reaches the global interrupt threshold.
4-5
6
—
—
CM
• Continuous mode
0 Normal operation.
1 The empty bit (RxBD[E]) is not cleared by the CP after this BD is closed, allowing the
associated buffer to be overwritten automatically when the CP next accesses this BD.
7-8
9
—
—
EOSF
End of super frame. CES mode (RCT[CESM=1]) only.
0 No signaling information should be inserted after closing this buffer.
1 When closing this buffer, the ATM receiver unpacks the CAS information from the
incoming AAL1 cells and stores it in the internal CAS block.
Note that this bit should be set by the user at the end of each super-frame in the common
Support.”
10-15 —
—
0x02
0x04
—
—
DL
Data length. The number of octets the CP writes into the buffer once its BD is closed.
RXDBPTR Rx data buffer pointer. Points to the first location of the associated buffer; may reside in
either internal or external memory. This pointer must be burst-aligned.
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ATM AAL1 Circuit Emulation Service
31.12.2 AAL1 CES TxBDs
Figure 31-29 shows the AAL1 CES TxBD.
0
1
2
3
4
5
6
7
8
9
10
15
Offset + 0x00
Offset + 0x02
Offset + 0x04
Offset + 0x06
R
—
W
I
—
CM
—
EOSF
—
Data Length (DL)
Tx Data Buffer Pointer (TXDBPTR)
Figure 31-29. AAL1 CES TxBD
Table 31-12 describes AAL1 CES TxBD fields.
Table 31-12. AAL1 CES TxBD Field Descriptions
Offset
Bits
Name
Description
0x00
0
R
Ready
0 The buffer associated with this BD is not ready for transmission. The user is free to
manipulate this BD or its associated buffer. The CP clears this bit after the buffer has
been sent or after an error condition is encountered.
1 The buffer prepared for transmission by the user has not been sent or is being sent.
No fields of this BD may be written by the user once R is set.
1
2
—
W
—
Wrap (final BD in table)
0 Not the last BD in the TxBD table.
1 Last BD in the TxBD table. After this buffer is used, the CP sends outgoing data from
the first BD in the table (the BD pointed to by the channel’s TCT[TBD_BASE]). The
number of TxBDs in this table is determined only by the W bit. The current table
cannot exceed 64 Kbytes.
3
I
Interrupt
0 No interrupt is generated after this buffer has been serviced.
1 A Tx buffer event is sent to the interrupt queue after this buffer is serviced.
FCCE[GINTx] is set when the INT_CNT counter reaches the global interrupt
threshold.
4–5
6
—
—
CM
Continuous mode
0 Normal operation.
1 The CP does not clear the ready bit after this BD is closed, allowing the associated
buffer to be retransmitted automatically when the CP next accesses this BD.
7–8
9
—
—
EOSF
End of super frame. CES mode (TCT[CESM=1]) only.
0 No signaling information should be inserted after closing this buffer.
1 When closing this buffer the ATM transmitter fetches the CAS information from the
internal CAS block and packs it to the outgoing AAL1 cells.
Note that this bit should be set by the user at the end of each super-frame in the
10–15 —
—
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ATM AAL1 Circuit Emulation Service
Table 31-12. AAL1 CES TxBD Field Descriptions (continued)
Offset
Bits
Name
DL
Description
0x02
—
The number of octets the ATM controller should transmit from this BD’s buffer. It is not
modified by the CP. The value of DL should be greater than zero.
0x04
—
TXDBPTR Tx data buffer pointer. Points to the address of the associated buffer. The buffer may
reside in either internal or external memory. This value is not modified by the CP.
31.13 AAL1 CES Exceptions
There are four circular interrupt queues available for each channel. The interrupt queue number is
programmed in RCT[INTQ] and TCT[INTQ]. Events can be masked by clearing interrupt mask bits in the
RCT and TCT.
When one of the AAL1 channels generates an interrupt request, the CP writes a new entry to the table
consisting of the channel’s number and a description of the exception. The valid (V) bit is then set and
INTQ_PTR is incremented. When INTQ_PTR reaches the entry in which W is set, it returns to the first
entry of the queue. Each one-word entry provides detailed interrupt information to the host. More details
can be found in Section 29.11, “ATM Exceptions.”
31.13.1 AAL1 CES Interrupt Queue Entry
The figure below shows an interrupt queue entry.
0
1
2
3
7
8
9
10
11
12
13
14
15
V
—
W
—
TBNR RXF BSY TXB RXB
Offset + 0x00
Offset + 0x02
SLIPE
SLIPS
CASUP
Channel Code (CC)
Figure 31-30. AAL1 CES Interrupt Queue Entry
The table below describes interrupt queue entry fields.
Table 31-13. AAL1 CES Interrupt Queue Entry Field Descriptions
Offset
Bits
Name
Description
0x00
0
V
Valid interrupt entry
0 This interrupt queue entry is free and can be use by the CP.
1 This interrupt queue entry is valid. The host should read this interrupt and clear this
bit.
1
2
—
W
—
Wrap bit. When set, this is the last interrupt circular table entry. During initialization, the
host must clear all W bits in the table except the last one, which must be set.
3–7
8
—
—
SLIPE Slip End.Set when an AAL1 channel exits a slip state (the channel’s adaptive counter
reaches the ATM_Start threshold and the ATM channel regains its SYNC). At this
point the receiver starts to receive the incoming cells. See Section 31.6, “3-Step-SN
Note that this interrupt can be masked with RCT[SLIPIM=0]. See Section 31.9.1,
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Table 31-13. AAL1 CES Interrupt Queue Entry Field Descriptions (continued)
Offset
Bits
Name
Description
9
SLIPS Slip Start.Set when an AAL1 channel enters a slip state (the channel’s adaptive
counter reaches the ATM_Stop threshold or the ATM channel loses its SYNC). At this
point the receiver drops incoming cells until the adaptive counter reaches the
Note that this interrupt can be masked with RCT[SLIPIM=0]. See Section 31.9.1,
10
11
CASUP CAS Update Interrupt. Set when one of the eight outgoing CAS blocks is updated by
the CP. New signaling information has been received within the received AAL1 cells.
Note that this interrupt available in CES mode and when RCT[CCASM=1] mode.
This interrupt has an associated channel code.
TBNR Tx buffer-not-ready. Set when a transmit buffer-not-ready interrupt is issued. This
interrupt is issued when the CP tries to open a TxBD that is not ready (R = 0). This
interrupt is sent only if TCT[BNM] = 1. This interrupt has an associated channel code.
Note that for AAL5, this interrupt is sent only if frame transmission is started. In this
case, an abort frame transmission is sent (last cell with length=0), the channel is taken
out of the APC, and the TCT[VCON] flag is cleared.
12
13
RXF
Rx frame. RXF is set when an Rx frame interrupt is issued. This interrupt is issued at
the end of AAL5 PDU reception. This interrupt is issued only if RCT[RXFM] = 1. This
interrupt has an associated channel code.
BSY
Busy condition. The BD table or the free buffer pool associated with this channel is busy.
Cells were discarded due to this condition. This interrupt has an associated channel
code.
14
15
TXB
RXB
Tx buffer. TXB is set when a transmit buffer interrupt is issued. This interrupt is enabled
when both TxBD[I] and TCT[IMK] = 1. This interrupt has an associated channel code.
Rx buffer. RXB is set when an Rx buffer interrupt is issued. This interrupt is enabled
when both RxBD[I] and RCT[RXBM] = 1. This interrupt has an associated channel
code.
0x02
—
CC
Channel code specifies the channel associated with this interrupt.
31.14 AAL1 Sequence Number (SN) Protection Table
The 32-byte sequence number protection table, pointed to by AAL1_SNPT_BASE in the ATM parameter
RAM, resides in dual-port RAM and is used for AAL1 only. The table should be initialized according to
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ATM AAL1 Circuit Emulation Service
0
15
Offset + 0x00
Offset + 0x02
Offset + 0x04
Offset + 0x06
Offset + 0x08
Offset + 0x0A
Offset + 0x0C
Offset + 0x0E
Offset + 0x10
Offset + 0x12
Offset + 0x14
Offset + 0x16
Offset + 0x18
Offset + 0x1A
Offset + 0x1C
Offset + 0x1E
0x0000
0x0007
0x000D
0x000A
0x000E
0x0009
0x0003
0x0004
0x000B
0x000C
0x0006
0x0001
0x0005
0x0002
0x0008
0x000F
Figure 31-31. AAL1 Sequence Number (SN) Protection Table
31.15 Internal AAL1 CES Statistics Tables
statistics on a per-VC basis. AAL1_Int_STATT_BASE points to the base address of these tables. Each
AAL1 channel has its own table with a starting address given by AAL1_Int_STATT_BASE +
ATM_CHANNEL# × 8.
Table 31-14. AAL1 CES DPR Statistics Table
Offset
0x00
Name
Width
Description
Rx_AAL1_VALID Hword 16-bit cyclic counter. Counts the total received AAL1 cells delivered to the
receive buffers. This counter includes the tag cells (with SCE, SNE).
0x02
Rx_AAL1_BOV
Hword 16-bit cyclic counter. Counts the number of ATM buffer-pre overrun events i.e
0x04
0x06
Tx_AAL1_VALID
Tx_AAL1_BUN
Hword 16-bit cyclic counter. Counts the transmitted AAL1 cells.
Hword 16-bit cyclic counter. Counts the number of ATM buffer underrun events. See
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ATM AAL1 Circuit Emulation Service
31.16 External AAL1 CES Statistics Tables
An AAL1 CES statistics table, shown in Table 31-15, resides in the external memory and holds AAL1 CES
statistics on a per-VC basis. AAL1_Ext_STATT_BASE points to the base address of these tables. Each
AAL1 channel has its own table with a starting address given by AAL1_Ext_STATT_BASE +
ATM_CHANNEL# × 16.
Table 31-15. AAL1 CES External Statistics Table
Offset
0x00
Name
Width
Description
Rx_AAL1_LOST
Hword 16-bit cyclic counter. Counts the number of AAL1 lost cells events. See
0x02
0x04
Rx_AAL1_MISS
Rx_AAL1_SCE
Hword 16-bit cyclic counter. Counts the number of AAL1 misinserted events. See
Hword 16-bit cyclic counter. Counts the number of AAL1 sequence errors i.e the
expected SC is not match with the received one (ESC!= RSC). See
0x06
0x08
Rx_SNP_Error
Rx_AAL1_SPE
Hword 16-bit cyclic counter. Counts the number of ATM cell that received with
SNP error. (AAL1 PDU Header Error)
Hword 16-bit cyclic counter. Counts the number of structured pointer error events
0x0A
Rx_ReSYNC
Hword 16-bit cyclic counter. Counts the number of AAL1 resynchronized events:
pointer reframes, slip events, two consecutive cells with errors (SNE,
SCE, Tag…), and two consecutive pointers with errors (parity error or
pointer mismatch).
0x0C–
0x0E
—
Word
Reserved, should be cleared during initialization.
Note that both the internal and the external statistics tables should be cleared by the user.
31.17 CES-Specific Additions to the MCC
Additions to the MCC global parameter RAM and modifications to the channel-specific CHAMR and
INTMASK registers have been implemented to support CES operation. Refer to Section 28.3.3, “MCC
Parameters for AAL1 CES Usage,” Section 28.3.3.1.1, “Interrupt Circular Table Entry and Interrupt Mask
for more information.
31.18 Application Considerations
•
The buffer size (MCC [MRBLR]) must be a multiple of 8 octets.
•
The CAS buffer operates in continuous mode with newer signaling information continuously
overwriting older signaling.
•
The CES application does not use super-frame synchronization for the data flow in ATM-to-TDM
and TDM-to-ATM interworking. However, for the signaling flow, the PowerQUICC II uses the
super-frame sync signal to know when to supply the signaling information to the external framer.
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ATM AAL1 Circuit Emulation Service
The external framer then places the signaling information at the appropriate position in the super
•
Simple external logic is needed to synchronize the MCC-to-framer serial connection. When going
from TDM-to-ATM, the CAS information should be read by the MCC on the 24th frame of a super
frame.
•
•
The adaptive rate FIFO method can be implemented by the core by calculating the difference
between the ATM and MCC pointers.
When going from TDM-to-ATM, the ATM channel should be programmed to work at a higher rate
than the MCC super-channel rate. We expect that the jitter caused by the APC traffic reshaping will
MCC timing:
BDs are ready to be transmitted at the rate shown below.
ATM timing:
The optimal ATM channel rate would match the MCC super channel rate exactly.
ATM timing (adjusted to higher rate):
If PCR and PCR_FACTION cannot provide the exact MCC super channel rate, the
ATM channel should be programmed to a higher rate to avoid the MCC buffer-not-ready
state. It is recommended that the ATM rate be double that of the MCC.
Extra request at the higher rate to compensate for jitter.
Note that some of the extra requests will not be needed (buffer-not-ready) and will
be ignored by the ATM controller.
Figure 31-32. TDM-to-ATM Timing Issue
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Chapter 32
ATM AAL2
NOTE
The functionality described in this chapter is not available on the MPC8250
nor on rev A.1 .29µm (HiP3) silicon.
Refer to www.freescale.com for the latest RAM microcode packages that
support enhancements.
The microcode implementation of the ATM adaptation layer type 2 (AAL2) on the PowerQUICC II is
compliant with the ITU-T recommendations I.363.2 and I.366.1. This chapter describes the functionality
and data structures of AAL2 CPS, CPS switching, and SSSAR and should be used as a supplement to
32.1 Introduction
AAL2 enables the multiplexing of voice and data channels over a single ATM VC. The channels consist
of packets transported within individual ATM cells (see Figure 32-1). Packet lengths are allowed to vary
in order to accommodate bandwidth fluctuations of the individual channels. Each packet has a channel
identifier (CID) so that each AAL2 user (channel) is uniquely identified by the triplet VP | VC | CID.
SSSAR SDU
SSSAR
CPS
SSSAR PDU
PH PP
PH
PP
CPS PDU
PH
STF PH
PP
PP
PP
PP
Padding
Padding
ATM
ATM cell
ATM header STF PH
PH
Figure 32-1. AAL2 Data Units
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ATM AAL2
•
Common part sublayer (CPS)—In the CPS sublayer, variable length packets coming from multiple
users are assembled into CPS-PDUs belonging to a single ATM VC.
•
Service-specific convergence sublayer (SSCS)—The SSCS sublayer handles the mapping of user
data to the CPS sublayer. The SSCS segments large data frames into smaller CPS packets and also
provides different services to the user, such as transmission error detection. The SSCS sublayer is
further divided into three service-specific layers:
— Service-specific segmentation and reassembly sublayer (SSSAR)
— Service-specific transmission error detection sublayer (SSTED)
— Service-specific assured data transfer sublayer (SSADT)
User
User
User
User
SAP
SSADT
Service specific assured data transfer
SAP
SSTED
Service specific transmission error detection
SSSAR
SSCS
AAL2
SAP
Service specific segmentation & reassembly
SAP
CPS
CPS
Common part sublayer
(SAP): Service access point
Figure 32-2. AAL2 Sublayer Structure
The AAL2 microcode implements the CPS and SSSAR sublayers. (The SSADT and SSTED sublayers are
not implemented.) As shown in Figure 32-2, the user can access the CPS sublayer directly or through the
SSSAR sublayer. The SSSAR sublayer is used mainly for transferring large data frames.
The AAL2 microcode also enables switching from one PHY | VP | VC | CID combination to another; an
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ATM AAL2
VP=5|VC=20|CID=13
UTOPIA
PHY4
X
UTOPIA
PHY7
VP=27|VC=3|CID=212
Figure 32-3. AAL2 Switching Example
32.2 Features
The PowerQUICC II’s AAL2 features are as follows:
•
•
Fully complies with ITU-T I.363.2 (09/97 and 11/00) and ITU-T I.366.1 (06/98) specifications.
Number of AAL2 external channels supported is subject to internal memory constraints
— Each external channel requires space for one Transmit Queue Descriptor in internal memory.
Typically, up to 1000 external channels can be supported.
•
•
Supports CBR, VBR and UBR+ traffic types
— PCR pacing (with optional Timer_CU)
— VBR pacing (with optional Timer_CU)
— UBR+ pacing (no Timer_CU support)
Priority mechanism for transmitting per VC. The priority mechanism provides for TX queues
having equal or differing priorities. The SSSAR TX queues can be prioritized flexibly among the
CPS TX queues.
•
•
•
•
•
Timer_CU support
NoSTF mode support
Support for partially filled cells
Interrupt indications include the ATM channel number, the CID, and the event type. The events
reported are TX buffer not ready, TX buffer transmitted, RX buffer not ready, RX buffer, RX
SSSAR frame, and RX AAL2 error events.
•
CPS switching
— Switching from a receive PHY | VP | VC | CID combination to another transmit PHY |
1
1
1
1
2
VP | VC | CID combination
2
2
2
— Partial packet discard support
— For each switched queue, a counter for the total number of packets in the queue is available.
CPS Receiver
•
— Segmentation of CPS PDU directly to external memory queues
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ATM AAL2
— A separate queue for every VP | VC | CID or a common queue for multiple VP | VC | CID
combinations
— Receive one or multiple VP | VC | CIDs directly to a specific TX queue to enable switching
— Sequence number (SN) protection check for CPS-PDU
— CRC5 (HEC) check to detect errors in the CPS-PH of the CPS-Packet
— OSF (offset field) of the STF (start of frame) check (a valid value is less than 48)
— An SDU length limit parameter (Max_SDU_Deliver_Length) per ATM VC
— Odd parity check for the STF octet of the CPS-PDU
CPS Transmitter
•
— Reassemble CPS PDU directly from external memory
— Perform CPS-PDU padding as needed
— Insert Sequence Number bit of the CPS-PDU
— Parity bit is calculated to provide odd parity over the STF octet
— Calculation of CRC-5 on the first 19 bits of the CPS-PH
— UUI field in the CPS-Packet header is programmed according to the value of the CPS_UUI
parameter (per packet)
— A free running counter (per TX Queue) is decremented for each packet sent.
SSSAR Receiver
•
— Reassemble CPS packets from the same CID into an SSSAR SDU
— A separate queue for every PHY | VP | VC | CID
— Perform all the above mentioned CPS receiver functions
— A Ras_Timer mode is provided. When the Ras_Timer expires the buffer is closed with a timer
expired error. The next packet received starts a new SSSAR SDU in a new buffer.
— The SDU length is checked. If the frame exceeds the length limit
(SSSAR_Max_SDU_Length), the receiver discards the rest of the packets from the current
frame, closes the buffer and reports a Max_SDU violation error in the BD. The next packet
received starts a new SSSAR SDU in a new buffer.
— Partial Packet Discard. If no buffer is available when a packet arrives, the receiver enters a
frame hunt state and discards each incoming packet from the current frame.
— The UUI field is stored for the host into the RxBD after receiving the whole SSSAR frame.
SSSAR Transmitter
•
— Segmentation of SSSAR SDUs from SSSAR TX queue into CPS packets
— An SSSAR TX queue may contain several CIDs
— Performs all the above mentioned CPS transmitter functions
— A programmable segment length (Seg_Len) is copied from the SSSAR SDU into the CPS
packet payload, except for when at the end of the frame or buffer.
— UUI mode available. When UUI mode is enabled, the SSSAR UUI is copied from the byte
following the last byte of the frame.
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ATM AAL2
32.3 AAL2 Transmitter
The following sections describe the AAL2 transmitter.
32.3.1 Transmitter Overview
A transmitter cycle starts when the APC schedules an ATM channel number for transmission. The TCT is
fetched and the AAL type of the channel is checked. For AAL2 cells, the transmitter first handles
uncompleted packets from the previous cell of the current CID (partial and split cases) by filling the
beginning of the cell with the remainder of the last packet.
Then, the transmitter performs the priority mechanism (see Section 32.3.2, “Transmit Priority
Mechanism”) in order to fill the cell with new packets. The priority mechanism determines the order in
which the TX queues are serviced. The transmitter continues to search for ready packets in the TX Queues
until either the cell is successfully filled with packets, or no more packets are ready but the cell is not yet
completed. In the first case the cell is simply sent. In the latter case, the optional Timer_CU (described in
uncompleted cell is padded with zeros and sent; otherwise, the cell is temporarily stored in external
memory for the CP to attempt to complete it the next time the channel is scheduled.
The TX queues are the data structures that store the CPS packets and SSSAR frames. Each TX queue can
contain different CIDs. Each TX queue is maintained by a Tx queue descriptor (TxQD) that holds the
queue pointer and parameters to manage the queue.
When the transmitter fetches a packet out of an SSSAR TX Queue, it usually takes out of the SSSAR buffer
channel CID is taken from the BD of the first buffer of the SSSAR frame (see Section 32.3.5.5, “SSSAR
Transmit Buffer Descriptor”). A CPS UUI = 27 is used for all the in-frame packets until the last packet
from the SSSAR frame is sent. The last packet can optionally contain a per frame, user-defined UUI. After
an SSSAR buffer is completely sent, an optional interrupt event is issued to the host. Also, if an SSSAR
TX queue is empty an optional interrupt event is issued to the host.
In case of CPS TX Queue, the transmitter fetches the packet header out of a buffer descriptor and the
packet payload out of a CPS buffer (see Section 32.3.5.3, “CPS Buffer Structure”). The HEC in the packet
header is calculated by the CP or taken from the buffer descriptor based on the user configuration. After a
CPS packet is sent, an optional interrupt event is issued to the host. Also, if the CPS TX queue is empty
an optional interrupt event is issued to the host.
The optional partial filled mode (see Section 32.3.3, “Partial Fill Mode (PFM)”) limits the number of data
octets per cell. This can be used to ensure that a cell does not contain a split packet or to limit transmission
to one packet per TX cell by setting a low partial fill threshold (PFT).
cells that do not include the STF byte, thus allowing for 48-byte packets.
32.3.2 Transmit Priority Mechanism
The transmit priority mechanism operates in two modes:
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ATM AAL2
•
•
Round robin (TCT[Fix]=0)
Fixed priority (TCT[Fix]=1)
The following sections describe the priority options.
32.3.2.1 Round Robin Priority
In round robin priority mode, the Tx queues all have equal priority. The transmitter starts with the TxQD
services from each queue is determined by the one-packet bit (TCT[OneP]). If TCT[OneP]=0, the
transmitter tries to process as many packets in the queue as needed to fill up the cell. Only when the queue
is empty does the transmitter move on to the next queue (assuming the cell is not completed). If
TCT[OneP]=1, the transmitter attempts to take only one packet out of each queue. (Set TCT[OneP] for
implementations where each queue contains only one CID.)
TxQD
NextQueue
TxQD
TCT
Fix=0
FirstQueue
NextQueue
TxQD
NextQueue
Figure 32-4. Round Robin Priority
The transmitter steps from one TxQD to the next along the queue links. The TCT[MaxStep] parameter
limits the number of TX Queues that the transmitter visits during a cell time. If MaxStep is reached before
the cell has been completely filled, one of the following events takes place:
•
•
TCT[ET]=0 (Timer CU disabled). The cell is padded with zeros and sent.
TCT[ET]=1 (Timer CU enabled). If the timer has not expired, the cell is not sent. (The transmitter
attempts to fill the cell the next time this channel is scheduled.) If the timer has expired, the cell is
padded with zeros and sent
After the transmitter sends a cell, it saves the queue link of the last TxQD serviced in TCT[FirstQueue].
32.3.2.2 Fixed Priority
In fixed priority mode (TCT[Fix]=1), the transmitter, with each new cell, starts with searching the highest
priority queue and then moves on to the lower priority queues. The TCT[FirstQueue] points to the highest
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ATM AAL2
TxQD
Highest priority queue
NextQueue
TxQD
TCT
Fix=1
FirstQueue
NextQueue
TxQD
Lowest priority queue
0x0000 (null link)
Figure 32-5. Fixed Priority Mode
The TCT[OneP] determines the number of packets that the transmitter attempts to take from each queue
(see the explanation in round robin mode).
The NextQueue field of the lowest priority TxQD should be cleared (null link), and TCT[MaxStep] should
be programmed to the total number of TX queues in the channel. When the transmitter reaches the null
link and the cell is still not complete, the transmitter checks the TIMER CU mode as described above for
the round robin mode.
32.3.3 Partial Fill Mode (PFM)
The partial fill mode (TCT[PFM]=1) allows the user to specify a partial fill threshold (TCT[PFT]), which
limits the number of data octets sent with each ATM cell. Partial fill mode assures that packets are not split
over two cells, unless the first packet of the cell is greater than 47 bytes.
In partial fill mode, the transmitter starts by filling the ATM cell with the first packet. After the first packet,
the CP determines if including the next packet in the cell would exceed the PFT limit. If so, the second
packet is not inserted into the current cell, the unused payload is padded with zeros, and the cell is sent. If
the second packet does not exceed PFT, the CP inserts it into the CPS-PDU and moves on to the third
packet, and so on.
By programming PFT = 1, the partial fill mode can also serve to assure that only one packet is sent per cell.
The following figures provide examples of partial fill mode operation:
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ATM AAL2
1. Five packets fit exactly within the PFT limit
Cell
AAL2
AAL2
packet 2
AAL2
packet 3
AAL2
AAL2
header STF packet 1
packet 4 packet 5 Padding
Transmit
0
PFT
2. Because PFT is less than the combined lengths of packet 1, packet 2 and packet 3,
the ATM cell is sent only with packets 1 and 2. (Packet 3 will be sent with the next cell.)
Cell
AAL2
AAL2
packet 2
AAL2
packet 3
header STF packet 1
Empty
0
Remove packet 3
PFT
Cell
AAL2
AAL2
packet 2
header STF packet 1
Padding
Transmit
Transmit
0
PFT
3. Because the first packet exceeds the PFT value, the CPS-PDU consists only of this packet
(and the unused octets are padded with zeros).
Cell
AAL2
packet 1
header STF
Padding
0
PFT
32.3.4 No STF Mode
The no-STF (no start of frame) mode enables the transmission of 48-byte packets by not including the STF
byte in the CPS PDU. The no-STF mode should always be used with PFT programmed to 47 in order to
prevent split and partial packets. For the AAL2 channels that use this mode, packets must not be larger
than a maximum packet size of 48.
The user activates this mode per ATM channel by doing the following:
1. Setting TCT[NoSTF]=1 and TCT[PFM]=1
2. Establishing a partial fill threshold by programming TCT[PFT]=47
The following figure shows a cell using no-STF mode:
Cell
header
AAL2 packet of 48 bytes
0
32.3.5 AAL2 Tx Data Structures
The following sections describe the transmit connection tables (TCT) and the structures in which CPS
packets and SSSAR SDUs are stored in memory.
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32.3.5.1 AAL2 Protocol-Specific TCT
The transmit connection table (TCT) is a VC-level table and is where the AAL type for the ATM channel
number is selected. The parameters related to the ATM channel number or to all the TX Queues of the
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Offset + 0x00
Offset + 0x02
Offset + 0x04
Offset + 0x06
Offset + 0x08
Offset + 0x0A
Offset + 0x0C
Offset + 0x0E
Offset + 0x10
Offset + 0x12
Offset + 0x14
Offset + 0x16
Offset + 0x18
Offset + 0x1a
Offset + 0x1C
Offset + 0x1E
—
GBL
BO
—
DTB BIB AVCF PFM
ATT
ET
VCON
INTQ
AAL
—
NoSTF
—
—
FirstQueue
Rate Remainder
PCR Fraction
PCR
Timer_CU_period
Timer_Period_Shadow
—
APC Linked Channel
ATM Cell Header (VPI,VCI,PTI,CLP)
—
—
PMT
PFT
MaxStep
OneP STPT Fix PM
—
Figure 32-6. AAL2 Protocol-Specific Transmit Connection Table (TCT)
NOTE
When the channel is active, the CP fetches the TCT (32 bytes) using burst
cycle and writes back only the first (24 bytes).
Table 32-1 describes the AAL2 TCT fields.
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ATM AAL2
.
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ATM AAL2
Table 32-1. AAL2 Protocol-Specific Transmit Connection Table (TCT)
Field Descriptions
1
Offset Bits
Name
Description
0x00
0–1
2
—
Reserved, should be cleared during initialization.
GBL
Global. Setting GBL enables snooping of data buffers, BD, interrupt
queues and free buffer pool.
3–4
BO
Byte ordering. This field is used for data buffers.
00 Reserved.
01 Power PC little endian.
1x Big endian.
5
6
—
Reserved, should be cleared during initialization.
DTB
Data buffer bus selection.
0 Data buffers reside on the 60x bus.
1 Data buffers reside on the local bus.
7
8
BIB
Bus selection for the BDs, interrupt queues and the free buffer pool.
0
1
Reside on the 60x bus.
Reside on the local bus.
AVCF
Auto VC off. Determines APC behavior when the last buffer associated
with this VC has been sent and no more buffers are in the VC’s TxBD
table,
0
The APC does not remove this VC from the schedule table and
continues to schedule it to transmit.
1
The APC removes this VC from the schedule table. To continue
transmission after the host adds buffers for transmission, a new ATM
TRANSMIT command is needed, which can be issued only after the CP
clears the VCON bit. (Bit 13)
9
PFM
ATT
0
1
Partially filled cells are not supported.
Partially filled cells are supported.
10-11
ATM traffic type
00 Peak cell-rate pacing (regular traffic). The host must initialize PCR
and PCR fraction. Other traffic parameters are not used.
01 Peak and sustain cell rate pacing (VBR traffic). The APC performs a
continuous-state leaky bucket algorithm (GCRA) to pace the
channel-sustain cell rate. The host must initialize PCR, PCR fraction,
SCR, SCR fraction, and BT (burst tolerance).
10 Peak and Minimum cell rate pacing. The host must initialize PCR, PCR
fraction, MCR, MCR fraction, and MDA.
11 Reserved.
12
13
ET
Enable Timer_CU.
0 Timer_CU operation in this channel is disabled.
1 Timer_CU operation in this channel is enabled.
VCON
Virtual channel is on
Should be set by the host before it issues an ATM TRANSMIT command.
When the host sets the STPT (stop transmit) bit, the CP deactivates this
channel and clears VCON. The host can issue another ATM TRANSMIT
command only when the CP clears VCON.
14–15
INTQ
Points to one of the four interrupt queues available.
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ATM AAL2
Table 32-1. AAL2 Protocol-Specific Transmit Connection Table (TCT)
Field Descriptions (continued)
1
Offset Bits
Name
Description
0x02
0-11
12
—
Reserved, should be cleared during initialization.
NoSTF
0 Normal AAL2 cell structure.
1 The cell does not include the STF byte. In this mode each cell starts with
a new packet and contains only whole packets (no split or partial).
13–15
AAL
AAL type
000 AAL0 —Segmentation with no adaptation layer
001 AAL1 —ATM adaptation layer 1 protocol
010 AAL5 —ATM adaptation layer 5 protocol
100 AAL2 —ATM adaptation layer 2 protocol
Service.”
All others reserved.
0x04
0x06
0x08
0x0A
—
—
—
—
—
Reserved, should be cleared during initialization.
Reserved, should be cleared during initialization.
Reserved, should be cleared during initialization.
—
—
FirstQueue
Points to the first queue to be serviced in the transmitter cycle. In
round-robin priority mode (TCT[Fix]=0), this pointer could point to any one
of the TxQDs related to this channel. In fixed priority mode (TCT[Fix]=1),
this pointer should point to the highest priority TxQD.
0x0C
0–7
8–15
—
Rate Remainder
PCR Fraction
PCR
Rate remainder. Used by the APC to hold the rate remainder after adding
the pace fraction to the additive channel rate. Should be cleared during
initialization by the user.
Peak cell rate fraction. Holds the peak cell rate fraction of this channel in
units of 1/256 slot. If this is an ABR channel, this field is automatically
updated by the CP.
0x0E
0x10
Peak cell rate. Holds the peak cell rate (in units of APC slots) permitted
for this channel according to the traffic contract. Note that for an ABR
channel, the CP automatically updates PCR to the ACR value.
—
Timer_CU_period
Timer_CU duration in units of APC slots. Assures that CPS-Packet
already packed in a cell wait at most the Timer_CU duration. The user
defines this field.
0x12
0x14
0x16
—
—
—
Timer_Period_Shadow This field must be initialized to the Timer_CU period in units of APC slots.
—
Reserved, should be cleared during initialization.
APCLC
APC linked channel. Used by the CP. Should be cleared during
initialization.
0x18
—
ATMCH
ATM cell header. Holds the full (4-byte) ATM cell header of the current
channel. The transmitter appends ATMCH to the cell payload during
transmission.
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ATM AAL2
Table 32-1. AAL2 Protocol-Specific Transmit Connection Table (TCT)
Field Descriptions (continued)
1
Offset Bits
Name
Description
0x1C
0–1
2–7
—
Reserved, should be cleared during initialization.
PMT
Performance monitoring table. Points to one of the available 64
performance monitoring tables. The starting address of the table is
PMT_BASE+PMT*32.
8–15
MaxStep
Holds the number of TX Queues visited for each cell being prepared for
transmission. In fixed priority mode (TCT[Fix]=1), MaxStep should be set
to the total number of TX queues in the channel. See Section 32.3.2,
0x1E
0-1
—
Reserved, should be cleared during initialization.
2–7
PFT
Partial fill threshold. Used for partially filled cells only; see Section 32.3.3,
allowed in a CPS PDU. The range 1–48 are valid values.
If PFT=48 in partial fill mode, performance is adversely affected. When
not in partial fill mode, PFT must be initialized to 47.
8-11
12
—
Reserved, should be cleared during initialization.
OneP
0 The transmitter reads as many packets as possible from each TX queue
before moving to the next queue.
1 The transmitter reads only one packet from each TX queue before
advancing to the next queue.
13
14
STPT
Fix
Stop transmit. Should be cleared during initialization. When the host sets
this bit, the CP removes this channel from the APC and clears
TCT[VCON] flag.
0 Round robin priority. The TX Queues related to this channel all share
the same priority.
1 Fixed priority. The TX Queues are ordered in a fixed priority ladder.
15
PM
Performance monitoring
0
No performance monitoring for this VC.
1 Performance is monitored for this VC. When a cell is sent for this VC,
the performance monitoring table indicated in PMT field is updated.
1
Boldfaced entries must be initialized by the user.
32.3.5.2 CPS Tx Queue Descriptor
TxQD contains the address of the next BD to be serviced, and other queue-specific parameters. The
NextQueue pointer is used to create a linked list of TxQDs, as described in Section 32.3.2, “Transmit
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ATM AAL2
0
7
8
9
10
11
12
13
15
Offset + 0x00
—
BNM SW HEC CPS TBM
—
Offset + 0x02
Offset + 0x04
Offset + 0x06
Offset + 0x08
Offset + 0x0A
Offset + 0x0C
Offset + 0x0E
TxBD Table Offset In (switched mode only)
TxBD Table Base
TxBD Table Offset Out
Number of Packets In Queue
NextQueue
—
Figure 32-7. CPS Tx Queue Descriptor (TxQD)
Table 32-2 describes the CPS TxQD fields.
.
Table 32-2. CPS TxQD Field Descriptions
1
Offset Bits
Name
Description
0x00
0-7
8
—
Reserved for internal use. (Used to save the BD status of the open BD.)
Buffer not-ready interrupt mask of the TxBD table.
BNM
0 The transmit buffer-not-ready event for this queue is masked. (The event is not sent
to the interrupt queue.)
1 The buffer-not-ready event for this queue is enabled.
9
SW
HEC
CPS
TBM
Switching queue.
0 Normal TX Queue.
1 This TxQD handles a switching queue. The receiver and transmitter share this queue.
10
11
12
HEC calculation.
0 Transmitter calculates the CPS header HEC.
1 The CPS header HEC is taken as is from the CPS buffer descriptor.
Sublayer type. For a CPS TxQD, this field must be set.
0 SSSAR or SSTED.
1 CPS packet.
Transmit buffer interrupt mask.
0
The transmit buffer event of this queue is masked. (The event is not sent to the
interrupt queue).
1
The transmit buffer event of this queue is enabled.
13-15
—
—
Reserved, should be cleared during initialization.
0x02
0x04
0x08
TxBD Table Used only when this queue is used for switching (SW=1). Should be cleared during
Offset In initialization.
—
—
TxBD Table This pointer points to the base address of the BD table.
Base
TxBD Table Holds the offset from the TxBD table base to the next BD to be opened by the
Offset Out transmitter. Should be cleared during initialization.
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ATM AAL2
Table 32-2. CPS TxQD Field Descriptions (continued)
1
Offset Bits
Name
Description
0x0A
—
Number of Counts the number of packets currently in the queue. If this queue is switched, the
Packets In receiver increments this counter with each new received packet and the transmitter
Queue
decrements it with each packet sent. For switching, the user should initialize this
counter to zero. When this queue is not switched, this counter counts down with every
packet sent. (This can have various purposes such as evaluating the packet rate that
is transmitted from this queue.).
0x0C
0x0E
—
—
—
Reserved, should be cleared during initialization.
1
Boldfaced entries must be initialized by the user.
32.3.5.3 CPS Buffer Structure
The CPS buffer structure consists of a BD table that points to data buffers. The BDs contain, apart from
the buffer pointer, also the packet header. The buffers contain the packet payload. See Figure 32-8.
BD memory space
Data memory space
TxBD table
of ch 1
Tx buffer 1 of
channel 1
TxBD_Table_Base
TxBD 1
TxBD 2
TxBD 3
TxBD 4
Pointers
from
CPS TxQD
Tx buffer 3 of
channel 1
TxBD_Table_Offset_Out
•
•
TxBD 5
Tx buffer 4 of
channel 1
TxBD 6
•
Tx buffer 1 of
channel 4
TxBD table
of ch 4
TxBD_Table_Base
TxBD 1
TxBD 2
TxBD 3
Tx buffer 2 of
channel 1
Pointers
from
another
Tx buffer 2 of
channel 4
TxBD 4
TxBD 5
TxBD 6
TxBD 7
TxBD 8
TxBD 9
•
•
•
CPS TxQD
Tx buffer 3 of
channel 4
TxBD_Table_Offset_Out
Tx buffer 8 of
channel 4
Figure 32-8. Buffer Structure Example for CPS Packets
Figure 32-9 shows a CPS TxBD.
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ATM AAL2
0
1
2
3
4
7
8
15
Offset + 0x00
R
CM
W
I
—
CPS Packet Header
Offset + 0x02
Offset + 0x04
Offset + 0x06
CPS Packet Header
Tx Data Buffer Pointer (TXDBPTR)
Figure 32-9. CPS TxBD
Table 32-3 describes the CPS TxBD fields.
.
Table 32-3. CPS TxBD Field Descriptions
1
Offset
Bits
Name
R
Description
0x00
0
1
2
3
Ready
0 The buffer associated with this BD is not ready for transmission. The user is free
to manipulate this BD or its associated buffer. The CP clears R after the buffer is
sent or after an error condition is encountered.
1 The user-prepared buffer has not been sent or is currently being sent. No fields of
this BD may be written by the user once R is set.
2
CM
Continuous mode
0 Normal operation.
1 The CP does not clear R after this BD is closed, allowing the associated buffer to
be retransmitted automatically when the CP next accesses this BD. However, the
R bit is cleared if an error occurs during transmission, regardless of the CM bit
setting.
W
Wrap (final BD in table)
0 This is not the last BD in the TxBD table.
1 This is the last BD in the TxBD table. After this buffer is used, the CP transmits
outgoing data for this channel from the first BD in the table (the BD pointed to by
the channel’s TxBD_table_Base in the TxQD). The number of TxBDs in this table
is determined only by the W bit.
I
Interrupt
0 No interrupt is generated after this buffer has been serviced.
1 A Tx Buffer event is sent to the interrupt queue after this buffer is serviced. The
GHIN/GLIN bit in the event register is set when the INT_CNT counter reaches
terminal count.
4-7
—
Reserved, should be cleared during initialization.
8-15
CPS Packet This field contains the beginning (MSB) of the 3-byte packet header. See
0x02
0x04
—
—
CPS Packet This field contains the rest of the packet header. If TxQD[HEC] = 0, the HEC part of
Header
the packet header is calculated by the CP, and the user may disregard the five
TXDBPTR Tx data buffer pointer. Points to the address of the associated buffer. There are no
byte-alignment requirements for the buffer, and it may reside in either internal or
external memory. This pointer is not modified by the CP.
1
2
Boldfaced entries must be initialized by the user.
Setting Continuous mode (TxBD[CM] = 1) is not allowed in CID switching mode.
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ATM AAL2
0
7
8
13
14
18
19
23
Channel identifier (CID)
Length indicator (LI)
User-to-user ID (UUI) Header error check (HEC)
Figure 32-10. CPS Packet Header Format
32.3.5.4 SSSAR Tx Queue Descriptor
A SSSAR TxBD table and its associated buffers are collectively called an SSSAR TX Queue. Each
base address of the BD table, the offset of the next BD to be serviced, the data buffer pointer, and other
queue-specific parameters. The NextQueue pointer is used to create a linked list of TxQDs, as described
a 32-byte aligned address.
0
7
8
9
10
11
12
13
14
15
Offset + 0x00
Offset + 0x02
Offset + 0x04
Offset + 0x06
Offset + 0x08
Offset + 0x0A
Offset + 0x0C
Offset + 0x0E
Offset + 0x10
Offset + 0x12
Offset + 0x14
Offset + 0x16
Offset + 0x18
Offset + 0x1a
Offset + 0x1C
Offset + 0x1E
—
BNM UUI INF CPS TBM SSSAR
—
Seg_Len
—
TxBD Table Base
TxBD Table Offset Out
—
NextQueue
—
Figure 32-11. SSSAR Tx Queue Descriptor
Table 32-4 describes the SSSAR TxQD fields.
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ATM AAL2
.
Table 32-4. SSSAR TxQD Field Descriptions
1
Offset Bits
Name
Description
0x00 0-7
8
—
Reserved, should be cleared during initialization.
BNM
Buffer-not-ready interrupt mask of the TxBD table.
0 The transmit buffer-not-ready event for this queue is masked. (The event is not
sent to the interrupt queue.)
1 The buffer-not-ready event for this queue is enabled.
9
UUI
INF
UUI insertion mode
0 UUI of last CPS packet is 0.
1 UUI of last CPS packet is taken from the next byte after the end of the buffer.
2
10
11
12
Indicates the current state of the frame.
0 The next packet will be the first of a new frame.
1 Currently in the middle of the frame.
CPS
TBM
Sublayer type. For an SSSAR TxQD, this field must be cleared.
0 SSSAR or SSTED.
1 CPS packet.
Transmit buffer interrupt mask for TxBD table.
0
The transmit buffer event of this queue is masked. (The event is not sent to the
interrupt queue.)
1
The transmit buffer event of this queue is enabled.
13
SSSAR
SSSAR bit
0 SSTED sublayer
1 SSSAR sublayer
14-15
0x02 0-7
—
Reserved, should be cleared during initialization.
Seg_Len
Specifies the maximum length in bytes of the SSSAR PDU (excluding the packet
header). Seg_Len is limited to 45 in NoSTF=1 mode. The CP always attempts to
segment the SSSAR SDU according to this length, but not more than it.
8-15
—
Reserved, should be cleared during initialization.
0x04
0x08
—
TxBD Table Base Must be initialized to the first TxBD by the user.
—
TxBD Table
Offset Out
Used to calculate the pointer to the next TxBD to be used for transmission.
Should be cleared during initialization.
0x0A
0x0C
—
—
—
Reserved, should be cleared during initialization.
NextQueue
Points to the next TxQD to be serviced after this one. See Section Section 32.3.2,
0x0E– —
0x1E
—
Reserved, should be cleared during initialization.
1
2
Boldfaced entries must be initialized by the user.
The 5-bit UUI field is inserted into the header of the last packet of an SSSAR SDU. The user must append the UUI
to the last buffer as an additional byte. This additional byte is then inserted into the UUI field of the last packet header
(note that, it is important that this additional byte—the byte after the last byte in the last data buffer of the SSSAR
frame—contains the 5 bits of the UUI). The 3 MSB bits of this extra byte should be cleared; refer to Figure 32-10.
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ATM AAL2
32.3.5.5 SSSAR Transmit Buffer Descriptor
The SSSAR buffer structure consists of a BD table that points to data buffers. The buffers may contain
SSSAR SDUs belonging to different CIDs. Each buffer may contain a whole SSSAR SDU or part of it.
0
1
2
3
4
5
7
8
15
Offset + 0x00
Offset + 0x02
Offset + 0x04
Offset + 0x06
R
CM
W
I
L
—
CID
Data Length (DL)
Tx Data Buffer Pointer (TXDBPTR)
Figure 32-12. SSSAR TxBD
.
Table 32-5. SSSAR TxBD Field Descriptions
1
Offset
Bits
Name
Description
0x00
0
1
2
R
Ready
0 The buffer associated with this BD is not ready for transmission. The user is free to
manipulate this BD or its associated buffer. The CP clears R after the buffer is sent
or after an error condition is encountered.
1 The user-prepared buffer has not been sent or is currently being sent. No fields of
this BD may be written by the user once R is set.
CM
W
Continuous mode
0 Normal operation.
1 The CP does not clear R after this BD is closed, allowing the associated buffer to
be retransmitted automatically when the CP next accesses this BD. However, the
R bit is cleared if an error occurs during transmission, regardless of the CM bit
setting.
Wrap (final BD in table)
0 This is not the last BD in the TxBD table.
1 This is the last BD in the TxBD table. After this buffer is used, the CP transmits
outgoing data for this channel from the first BD in the table (the BD pointed to by
the channel’s TxBD_table_Base in the TxQD). The number of TxBDs in this table
is determined only by the W bit.
3
4
I
Interrupt
0 No interrupt is generated after this buffer has been serviced.
1 A Tx Buffer event is sent to the interrupt queue after this buffer is serviced. The
GHIN/GLIN bit in the event register is set when the INT_CNT counter reaches
terminal count.
L
Last.
0 This is not the last buffer of the SSSAR SDU.
1 This is the last buffer of the SSSAR SDU.
5-7
—
Reserved, should be cleared during initialization.
8-15
CID
Contains the CID number of the SSSAR SDU pointed by this BD. This field should be
written to the first BD of an SSSAR SDU.
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Table 32-5. SSSAR TxBD Field Descriptions (continued)
1
Offset
0x02
Bits
Name
Description
—
Data
Length
Contains the length of the buffer associated with this BD. If this is the last buffer (L=1)
and the UUI bit in the SSSAR TxQD is set, the 5-bit UUI field is located at
(TXDBPTR+Data Length)[3:7] with bit [3] being the msb, that is, in the byte (right
justified) immediately following the last byte of the buffer. For best bandwidth utilization
and optimized partitioning of the SDU to packets of exactly Seglen size when an SDU
is spread over multiple BD’s, the application should set Data Length to be an integer
multiple of Seg_Len. (Data Length == n x Seg_Len). For an SDU on a single BD this
restriction does NOT apply.
0x04
—
TXDBPTR Tx data buffer pointer. Points to the address of the associated buffer. There are no
byte-alignment requirements for the buffer, and it may reside in either internal or
external memory. This value is not modified by the CP.
1
Boldfaced entries must be initialized by the user.
32.4 AAL2 Receiver
The following sections describe the AAL2 receiver.
32.4.1 Receiver Overview
The receiver cycle starts after the FCC receives a cell. If the cell header is successfully mapped to an ATM
channel number, the corresponding RCT is fetched and the AAL type is read. For AAL2 cells, the receiver
begins by checking if the last cell received in this channel (CID) has an uncompleted (split) packet. If so,
the receiver first finishes handling this packet.
The receiver then goes through a validation process. The receiver matches the OSF field in the STF with
the expected OSF based on the actual split packet (if the first packet is not split, the OSF should be zero).
If the two values do not match, an OSF error interrupt is issued and the receiver drops the last packet. Also,
if the STF parity check, the SN check or the OSF>47 check results in an error, the receiver issues an
interrupt and discards the whole cell. If any of the above errors has occurred and the cell has started with
the remainder of an uncompleted packet, the receiver does the following:
•
•
For a CPS sublayer CID, the packet’s RxBD[UP] (uncompleted packet) bit is set.
For an SSSAR sublayer CID, the buffer is closed with RxBD[RxError = US = 10] (uncompleted
SDU), and the rest of the frame is dropped.
The receiver now begins the process of extracting new CPS packets out of the cell with another round of
error checking. The receiver examines each CPS packet header for the following errors:
•
•
Incorrect packet HEC. The packet and rest of the cell are discarded.
Packet length (LI+1) is larger than CPS_Max_SDU_Length. The receiver discards the packet and
then continues to extract the next packet in the cell. However, if the packet belongs to an SSSAR
CID, the receiver closes the SSSAR buffer with RxBD[RxError = OS = 11] (oversized) and
discards the rest of the frame.
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The receiver issues an interrupt for each of the above errors.When a SSSAR buffer is closed with
RxBD[RxError = US or OS], indicating Uncompleted SDU or Oversized, then RxBD[L] is set, and if
RxQD[RFM]=1 then the receiver also issues an RXF interrupt.
Then, if no errors have occurred in the packet header, the packet CID is used to match the PHY | VP | VC
an RxQD pointer. The RxQD indicates the type of SAR operation to be performed on the PHY | VP | VC
| CID. Three SAR operation modes are supported:
•
•
•
For the CPS sublayer, each packet from the CID is stored, as is, in a one packet buffer.
For switching, the packet is stored directly into the transmit buffer, and the CID is translated.
For the SSSAR sublayer, all packets received from the CID are reassembled into an SSSAR SDU
similar to the BD and buffer structures used for AAL5 frames.
•
For the SSSAR sublayer, last packet UUI indication is stored in the last RxBD of the SDU.
For the SSSAR sublayer, two additional parameters are verified for each new packet received:
•
RAS_Timer expiration. The RAS_Timer_Duration defined in the AAL2 parameter RAM limits the
time (starting when the first packet is received) allowed to receive a complete SSSAR SDU. If this
time limit is exceeded, the receiver closes the current buffer with RxBD[RxError = TE = 01]
(Ras_Timer expired) and starts a new SSSAR frame with the next packet. When a buffer is closed
with RxBD[RxError = TE = 01], RxBD[L] is not set and the receiver does not issue an RXF
interrupt.
•
SSSAR_Max_SDU_Length. With each new packet the receiver checks whether the current
accumulated length of the SSSAR SDU exceeds the SSSAR_Max_SDU_Length. If so, the
receiver closes the current buffer with RxBD[RxError = OS = 11] (oversized), discards the rest of
the SSSAR SDU, RxBD[L] is set, and if RxQD[RFM]=1 issues an RXF interrupt.
NOTE
CIDs that have the same number but that are from different AAL2
connections cannot use the same RxQD, unless they never have split
packets.
32.4.2 Mapping of PHY | VP | VC | CID
The AAL2 mapping mechanism translates a PHY | VP | VC | CID combination into an RxQD. An RxQD
can be unique per PHY | VP | VC | CID.
•
Each ATM channel number (RCT) has its own CID mapping table. The mapping table can be
placed in internal or external memory (according to RCT[MAP]) and is pointed to by RCT[CID
Mapping Table Base]. The CID of the received packet is used as an index into the mapping table.
•
•
Each entry in the mapping table contains a 2-byte RxQD offset. This offset, multiplied by 4, is the
offset to an RxQD in either the internal or external RxQD table.
The two RxQD tables serve all the ATM channel numbers of an FCC. (RxQD_Base_Int and
RxQD_Base_Ext are defined in the FCC parameter RAM.)
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•
RxQD offsets from 8 through 511 point into the internal RxQD table located in dual-port RAM at
RxQD_Base_Int. Note that the first 32 bytes of the internal RxQD table are reserved (so offsets
0–7 are reserved).
•
•
RxQD offsets greater than 511 point into the external RxQD table located at RxQD_Base_Ext +
(512*4).
Because the three types of RxQDs are different sizes, some offset numbers may not be used.
ATM cell
Header
STF CID-PH CPS packet payload CID-PH CPS packet payload
AAL2 RCT
RxQD_Base_Int
(in FCC parameter RAM)
CID mapping table base
RxBD table Rx buffers
RxBD table Rx buffers
CID mapping table
RxQD table (internal)
CID0
CID1
0
RxQD offset
RxQD offset
Reserved
RxQD_Base_Int +
RxQD_Offset*4
32
SSSAR RxQD
•
•
•
64
CPS RxQD
72
Switch RxQD
CID255
RxQD offset
RxQD offset
2044
Half-word
Tx queue descriptor
RxQD table (external)
Tx buffers
RxQD_Base_Ext + 512*4
(in FCC parameter RAM)
2048
CPS RxQD
Switch RxQD
TxBD table
Figure 32-13. CID Mapping Process
32.4.3 AAL2 Switching
is unique for each Rx CID. The descriptor holds a translation CID number and a pointer to a CPS TxQD
into which this packet is saved and later sent by the transmitter. (The TxQD pointer is responsible for the
actual PHY | VP | VC switching.) The TxQD pointed to by the switch RxQD(s) should have TxQD[SW]
set and should not be modified by the host when the channel is active. The transmit scheduling of the
packet is done by the APC according to the programmed bit rate of the ATM channel that holds the
switched queue.
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ATM AAL2
ATM Rx VC
1
ATM Tx VC
CID mapping table
Offset
TxQD
SW=1
TxBD table
Tx buffers
Tx buffers
CID71
RxQD table
Switch RxQD
Switch RxQD
ATM Rx VC
2
TxQD
SW=1
TxBD table
CID mapping table
Offset
CID14
Figure 32-14. AAL2 Switching
A partial packet discard mode is provided for the AAL2 switched channels that perform end-to-end
SSSAR. When this mode is enabled (switch RxQD[PPD]=1), if no buffer is available to receive a packet
in the middle of a frame, the subsequent middle packets of the SSSAR SDU are discarded. When the last
packet of the SSSAR SDU arrives, the receiver attempts to re-open a buffer.
A number-of-packets-in-queue counter is available in the TxQD. The CP increments the counter for each
packet received and decrements it for each packet sent. The host can poll the counter periodically to verify
that the switching queues are not over-loaded.
On any open BD that is partially filled, the receiver sets the UP (Un-complete packet) bit. When the packet
is fully received during a normal error-free operation, the UP mark is removed, the Empty bit is set, and
operation continues. However, if an error is detected by the receiver, the Empty bit is set and the UP bit
remains set. In such a case, the transmitter skips this BD and proceeds to the next one. If for any reason
the receiver that was in the middle of the BD stopped receiving traffic, the UP bit remains set and the
Empty bit is cleared. Another receiver using the same BD ring monitors the UP bit in addition to the Empty
bit. If the UP bit is set, the other receiver does not proceed with the reception and gives a Busy interrupt.
The receiver that is in a “stuck” state marks the BD with the receiver channel code that received the partial
If the TBNR Time Out CNT mechanism is used, the transmitter advances after it tries to transmit the same
BD with UP set after a given amount of attempts. The BD will be freed up for use. Refer to the TBNR
32.4.4 AAL2 RX Data Structures
The following sections describe the receive conntection tables and the structures in which CPS packets and
SSSAR SDUs are stored in memory.
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ATM AAL2
32.4.4.1 AAL2 Protocol-Specific RCT
The receive connection table (RCT) is a VC-level table and is where the AAL type for the ATM channel
number is selected. The parameters related to the ATM channel number or to all the RX Queues of the
ATM channel are maintained here. The RCT also contains the pointer to the CID mapping table for the
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Offset + 0x00
Offset + 0x02
Offset + 0x04
Offset + 0x06
Offset + 0x08
Offset + 0x0A
Offset + 0x0c
Offset + 0x0e
Offset + 0x10
Offset + 0x12
Offset + 0x14
Offset + 0x16
Offset + 0x18
Offset + 0x1A
Offset + 0x1C
Offset + 0x1E
—
GBL
BO
—
DTB BIB
—
SEGF ENDF
—
MAP
INTQ
AAL
—
NoSTF
—
CID Mapping Table Base
—
PMT
Max_CPS_SDU_Deliver_length
TBNR Time OUT CNT
—
EM PM
Figure 32-15. AAL2 Protocol-Specific Receive Connection Table (RCT)
NOTE
For an active channel, the CP uses a burst cycle to fetch the 32-byte RCT
and writes back only the first 24 bytes.
Table 32-6 describes the AAL2 RCT fields.
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ATM AAL2
Table 32-6. AAL2 Protocol-Specific RCT Field Descriptions
1
Offset
Bits
0–1
Name
Description
0x00
—
Reserved, should be cleared during initialization.
2
GBL
Global. Setting GBL enables snooping of data buffers, BDs, interrupt queues and free
buffer pool.
3–4
BO
Byte ordering—used for data buffers.
00 Reserved
01 munged little endian
1x Big endian
5
6
—
Reserved, should be cleared during initialization.
DTB
Data buffer bus selection.
0 Reside on the 60x bus.
1 Reside on the local bus.
7
BIB
Bus selection for the BDs, interrupt queues, CID mapping table, RxQDs, and the free
buffer pool.
0 Reside on the 60x bus.
1 Reside on the local bus.
8-9
10
—
Reserved, should be cleared during initialization.
SEGF
OAM F5 segment filtering
0 Do not send cells with PTI=100 to the raw cell queue.
1 Send cells with PTI=100 to the raw cell queue.
11
ENDF
OAM F5 end-to-end filtering
0 Do not send cells with PTI=101 to the raw cell queue.
1 Send cells with PTI=101 to the raw cell queue.
12
13
—
Reserved, should be cleared during initialization.
MAP
CID mapping table memory location select
0 Resides in the dual-port RAM.
1 Resides in external memory.
14-15 INTQ
Assigns one of the four available interrupt queues to this ATM channel number.
Reserved, should be cleared during initialization.
0x02
0–11
12
—
NoSTF
No STF byte.
0 Normal AAL2 cell structure.
1 The cell does not include the STF byte. In this mode each cell starts with a packet
and contains only whole packets (no split or part).
13–15 AAL
AAL type
000 AAL0 —Reassembly with no adaptation layer
001 AAL1 —ATM adaptation layer 1 protocol
010 AAL5 —ATM adaptation layer 5 protocol
100 AAL2 —ATM adaptation layer 2 protocol
All others reserved.
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ATM AAL2
Table 32-6. AAL2 Protocol-Specific RCT Field Descriptions
1
Offset
Bits
Name
Description
0x04
0x06
0x08
0x0A
0x0C
0x0E
0x10
0x12
0x14
0x16
0x18
—
—
Reserved, should be cleared during initialization.
—
—
—
—
—
—
—
—
—
—
Table Base
If RCT[MAP] = 0, the pointer contains a dual-port RAM address and only the 16 lsb
(at 0x1A and 0x1B) are relevant. If MAP = 1, the pointer is a full 32-bit address in the
memory space.
0x1C
0–1
2–7
—
Reserved, should be cleared during initialization.
PMT
Performance monitoring table. Assigns one of the available 64 performance
monitoring tables to this VC. The table’s starting address is PMT_BASE+PMT*32.
8–15
TBNR Time The TBNR Time-Out CNT is a parameter that describes the amount of attempts the
Out CNT
transmitter tries to transmit a packet on a BD ring which is current marked as partially
filled, i.e. waiting for a receiver to finish reception of a packet.
This value will be used internally by the transmitter that is the destination for this
packet and decremeted by the CPM on each attempt. Upon reaching the value 1, the
transmitter will act as if the receiver is stuck in error condition and proceed to the next
BD in the BD ring. This parameter is valid in switch mode only and should be
programmed to a higher value than the ratio between the transmitter rate and the
lowest receiver rate in the BD ring. The 8 bit value is scaled by 4 (setting TBNR
Time-Out CNT =1 yields a value of 4 internally) so that the max number is 1K.
Clearing this field will disable this feature completely
0x1E
0–7
Max_CPS_S Indicates the maximum size CPS_SDU in bytes that is allowed to be transported on
DU_Deliver_ this channel. This value is compared to the length of each CPS_SDU before it is
Length
delivered, as specified in the ITU-T recommendation I.363.2.
8–13
14
—
Reserved, should be cleared during initialization.
EM
Receive error mask for AAL2 protocol-specific events. Note that buffer-not-ready, Rx
buffer and Rx frame events are not affected by this mask.
0 Disable AAL2 receive error events.
1 Enable AAL2 error events.
15
PM
Enable performance monitoring
0 No performance monitoring for this VC.
1 Perform performance monitoring for this VC. Whenever a cell is received by this
VC, the associated performance monitoring table is updated.
1
Boldfaced entries must be initialized by the user.
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ATM AAL2
32.4.4.2 CID Mapping Tables and RxQDs
Each PHY | VP | VC | CID combination is assigned an RxQD using a CID mapping table. To multiplex
several receive CIDs into a single common queue, map each multiplexed PHY | VP | VC | CID
combination to one RxQD.
The ATM channel’s RCT contains the base address of the associated CID mapping table. This base address
is external (32 bits) when RCT[MAP]=1; otherwise, the table resides in the dual-port RAM and the base
address is two bytes. The CID of the received packet is used as an index into the mapping table. The
mapping table entries are 2-byte RxQD offsets. If the CID mapping table is external, it must be on the same
bus as the BDs and interrupt queues as specified by RCT[BIB].
There are two RxQDs—one for internal RxQDs and one for external RxQDs. Offsets between 0–511
belong to the 2048-byte internal RxQD table. It is recommended to have as many RxQDs as possible in
the internal table. Note that the first 32 bytes of the internal RxQD table are reserved for internal use; that
is, RxQD offsets between 0–7 are reserved. The address of an internal RxQD is RxQD_Base_Int +
4*RxQD_Offset.
Offsets between 512–65535 belong to the external RxQD table. The address of an external RxQD is
RxQD_Base_Ext + 4*RxQD_Offset. The external RxQD table must be on the same bus as the BDs and
interrupt queues as specified by RCT[BIB].
Because the three kinds of RxQDs are each a different size (for example, an SSSAR RxQD is 32 bytes and
a CPS switch RxQD is only 4 bytes), some of the offset numbers are left unused.
32.4.4.3 CPS Rx Queue Descriptors
0
11
12
13
14
15
Offset + 0x00
Offset + 0x02
Offset + 0x04
Offset + 0x06
—
RBM
—
SubType
RxBD Table Offset
RxBD Table Base
Figure 32-16. CPS Rx Queue Descriptor
Table 32-7 describes the CPS RxQD fields.
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ATM AAL2
Table 32-7. CPS RxQD Field Descriptions
1
Offset
Bits
Name
Description
0x00
0–11
12
—
Reserved, should be cleared during initialization.
RBM
Receive buffer mask.
0 Disable receive buffer interrupt.
1 Enable receive buffer interrupt.
13
—
Reserved, should be cleared during initialization.
14-15 SubType
SubType. Sublayer type, should be 00 (CPS) for this descriptor.
00 CPS sublayer.
01 CPS switched.
10 SSSAR.
11 Reserved.
0x02
0x04
—
—
RxBD Table Holds the offset to the next BD to be opened by the receiver. Should be cleared
Offset during initialization.
RxBD Table Holds the pointer to the first BD in the BD table.
Base
1
Boldfaced entries must be initialized by the user.
32.4.4.4 CPS Receive Buffer Descriptor (RxBD)
The CPS RxBD structure consists of a BD table that points to data buffers. The RxBDs contain, apart from
the buffer pointer, the packet header, as shown in Figure 32-17. The buffers contain the packet payload.
0
1
2
3
4
6
7
8
15
Offset + 0x00
Offset + 0x02
Offset + 0x04
Offset + 0x06
E
CM
W
I
—
UP
CPS Packet Header
Packet Header
Rx Data Buffer Pointer (RXDBPTR)
Figure 32-17. CPS Receive Buffer Descriptor
Table 32-8 describes the CPS RxBD fields.
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ATM AAL2
.
Table 32-8. CPS RxBD Field Descriptions
1
Offset
Bits
Name
Description
0x00
0
E
Buffer empty bit
0 The CPS RX buffer is full or data reception was aborted due to an error. The core
can read or write any fields of this RxBD. The CP does not use this BD while E
remains zero.
1 The CPS RX buffer is empty or reception is in progress. This is controlled by the CP.
Once E is set, the core should not access any fields of this buffer.
1
2
CM
W
Continuous mode
0 Normal operation
1 The CP does not clear E after this BD is closed, allowing the associated buffer to
be reused automatically when the CP next accesses this BD. However, the E bit is
cleared if an error occurs while receiving, regardless of the CM bit setting.
Wrap (final BD in table)
0 This is not the last BD in the RxBD table.
1 This is the last BD in the RxBD table of this current channel. After this buffer has
been used, the CP receives incoming data for this channel into the first BD in the
table. The number of RxBDs in this table is programmable and is determined only
by the W bit. The current table cannot exceed 64 Kbytes.
3
I
Interrupt
0 The CP will not issue an interrupt after this buffer is serviced.
1 The CP will issue an interrupt after this buffer is serviced if the RBM bit in the RxQD
is set.
4-6
7
—
Reserved, should be cleared during initialization.
UP
Uncompleted packet
0 No error occurred in this packet
1 A receive error occurred that caused this packet to be uncompleted. The receive
error type is reported to the interrupt queue.
8-15
—
Header header format.
0x02
0x04
CPS Packet Contains the rest of the packet header. The CP checks the packet HEC and if
Header
appropriate, indicates a packet HEC error in an interrupt queue entry with CID = 0.
—
RXDBPTR Rx data buffer pointer. Points to the address of the associated buffer. There are no
byte-alignment requirements for the buffer, and it may reside in either internal or
external memory. This value is not modified by the CP.
1
Boldfaced entries must be initialized by the user.
32.4.4.5 CPS Switch Rx Queue Descriptor
PHY | VP | VC | CID to another PHY | VP | VC | CID . The RxQD contains the pointer to the
1
1
1
1
2
2
2
2
TxQD that controls the TxBD table through which the packet is transferred.
The switch RxQD also contains the translation CID that is saved with the packet in the transmit buffer. A
PPD mode enables the discarding of the rest of an SSSAR frame when a buffer is not available.
Note that the CPS switch RxQD must be unique for every Rx switched CID.
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ATM AAL2
0
7
8
11
12
13
14
15
Offset + 0x00
Offset + 0x02
TX CID
—
RBM
PPD SubType
TxQD Pointer
Figure 32-18. CPS Switch Rx Queue Descriptor
Table 32-9 describes the CPS switch RxQD fields.
Table 32-9. CPS Switch RxQD Field Descriptions
1
Offset
Bits
0-7
Name
TX CID
Description
0x00
Translation CID. The received CID is saved in a TX Queue with this new CID number.
Reserved, should be cleared during initialization.
8-11
12
—
RBM
Receive buffer mask
0 Disable receive buffer interrupt
1 Enable receive buffer interrupt
13
PPD
Partial packet discard
0 Normal mode
1 When a buffer-not-ready event causes a packet to be discarded, the remainder of the
SSSAR SDU is also discarded. This allows for better performance for switched
channels that implement SSSAR.
14-15 SubType
Sublayer type. Should be 01 (CPS switched) for this descriptor.
00 CPS sublayer
01 CPS switched
10 SSSAR
11 Reserved
0x02
—
TxQD
Points to the TxQD into which the packets of this CID are stored and later sent.
Pointer
1
Boldfaced entries must be initialized by the user.
32.4.4.6 SWITCH Receive/Transmit Buffer Descriptor (RxBD)
The switch buffer structure consists of a BD table that points to data buffers. The RxBDs contain, apart
from the buffer pointer, the packet header, as shown in Figure 32-19. The buffers contain the packet
payload. This BD is common to the receiver and the transmitter.
0
1
2
3
4
5
6
7
8
15
Offset + 0x00 E/R
0
W
I
—
UP
CPS Packet Header
Offset + 0x02
Offset + 0x04
Offset + 0x06
Packet Header (Receiver CC)
Rx Data Buffer Pointer (RXDBPTR)
Figure 32-19. Switch Receive/Transmit Buffer Descriptor
Table 3-11 describes the Switch RxBD fields.
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ATM AAL2
Table 32-10. Switch RxBD Field Descriptions
Description
1
Offset Bits
Name
0x00
0
E/R
Buffer Ready
Must be set to zero.
1
2
0
Not valid for switching mode, should be cleared to 0 upon initialization.
W
Wrap (final BD in table)
0 This is not the last BD in the RxBD table.
1 This is the last BD in the RxBD table of this current channel. After this buffer has been
used, the CP receives incoming data for this channel into the first BD in the table. The
number of RxBDs in this table is programmable and is determined only by the W bit.
The current table cannot exceed 64 Kbytes.
3
I
Interrupt.
0 The CP will not issue an interrupt after this buffer is serviced.
1 The CP will issue an interrupt after this buffer is serviced if the RBM bit in the RxQD is
set.
4–6
7
—
Reserved, should be cleared during initialization.
UP
Uncompleted packet.
0 No error occurred in this packet and the complete packet has been received.
1 if R/E=1 a receive error occurred that caused this packet to be uncompleted. The
receive error type is reported to the interrupt queue. The transmitter will skip this
BD when in this state and continue to the next BD in the ring.
If R/E=0 a receiver has received the first part of a packet and is waiting for the rest of
it to be received on the next ATM cell.
8–15 CPS Packet
Header
header format. (see remark in next row)
0x02
—
CPS Packet
Header
Contains the rest of the packet header. The CP checks the packet HEC and if
appropriate, indicates a packet HEC error in an interrupt queue entry with CID = 0. See
Figure 32-10 for the CPS packet header format.
(Receiver
CC)
In case of a “stuck” receiver in switch mode, where the BD ring in common to Tx and
Rx, this field indicates the last Receiver Channel Code number which has been
received. The terminology for “stuck” implies a receiver which started receiving a
packet and the rest of the packet hasn’t been received.When the receiver is in a “stuck”
state the entry: CPS Packet Header is not valid. If the Time-out mechanism is being
used this field is being used internally by the CPM.
0x04
—
RXBDPTR
Rx data buffer pointer. Points to the address of the associated buffer. There are no
byte-alignment requirements for the buffer, and it may reside in either internal or
external memory. This value is not modified by the CP.
1
Boldfaced entries must be initialized by the user.
32.4.4.7 SSSAR Rx Queue Descriptor
specific to the SSSAR sublayer. This descriptor can belong to only one PHY | VP | VC | CID.
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ATM AAL2
0
10
11
12
13
14
15
Offset + 0x00
—
RasT
RBM
RFM SubType
Offset + 0x02
Offset + 0x04
Offset + 0x06
Offset + 0x08
Offset + 0x0A
Offset + 0x0c
Offset + 0x0e
Offset + 0x10
Offset + 0x12
Offset + 0x14
Offset + 0x16
Offset + 0x18
Offset + 0x1A
Offset + 0x1C
Offset + 0x1E
RxBD Table Offset
RxBD Table Base
—
Time Stamp
—
—
MRBLR
Max_SSSAR_SDU_Length
—
Figure 32-20. SSSAR Rx Queue Descriptor
Table 32-11 describes the SSSAR RxQD fields.
.
Table 32-11. SSSAR RxQD Field Descriptions
1
Offset Bits
Name
Description
0x00
0–10
11
—
Reserved, should be cleared during initialization.
RasT
Ras Timer enable.
0 Ras Timer disabled (Time Stamp field is still valid)
1 Ras Timer enabled. The Ras Timer duration is set by the Ras Timer Duration
parameter in the parameter RAM. If the current SSSAR SDU is not completed
before the RasTimer expires, the BD is closed showing the Ras_Timer expired (TE)
(SSSAR RxBD[RxError] = 01) and the next packet starts a new SDU.
12
13
RBM
RFM
Receive buffer mask.
0 Disable receive buffer interrupt
1 Enable receive buffer interrupt
Receive frame mask.
0 Disable receive frame interrupt
1 Enable receive frame interrupt
14-15 SubType
Sublayer type. Should be 10 (SSSAR) for this descriptor.
00 CPS sublayer
01 CPS switched
10 SSSAR
11 Reserved
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Table 32-11. SSSAR RxQD Field Descriptions (continued)
1
Offset Bits
Name
Description
0x02
0x04
—
—
RxBD Table Points to the next BD to be handled by the CP. The user should initialize this pointer to
Offset zero.
RxBD Table Points to the beginning of the BD table.
Base
0x08
0x0A
0x0C
—
—
—
—
—
Reserved, should be cleared during initialization.
Reserved, should be cleared during initialization.
Time Stamp Used for reassembly timeout of the SSSAR SDU. Whenever the first packet of an
SSSAR SDU arrives the timestamp timer is sampled and stored here (regardless of
the RasT bit).
0x10
0x12
0x14
—
—
—
—
Reserved, should be cleared during initialization.
Reserved, should be cleared during initialization.
—
MRBLR
Maximum receive buffer length. Holds the maximum receive buffer length. The actual
buffer size can be less.
0x16
—
—
Max_SSSAR Holds the maximum SSSAR SDU length. Upon each new packet the accumulated
_SDU_
Length
frame size is compared with this value. If the limit is exceeded, the CP discards the rest
of the packets of the current frame.
0x18–
0x1E
—
Reserved, should be cleared during initialization.
1
Boldfaced entries must be initialized by the user.
32.4.4.8 SSSAR Receive Buffer Descriptor
The SSSAR SDU is stored in a BD-buffer structure similar to the structures used for AAL5 frames. The
buffer size is determined by SSSAR RxQD[MRBLR]; the actual buffer space used may be smaller. If the
received SSSAR SDU is greater than MRBLR, the SDU spans over multiple buffers.
0
1
2
3
4
5
6
7
10
11
15
Offset + 0x00
Offset + 0x02
Offset + 0x04
Offset + 0x06
E
CM
W
I
L
RxError
—
UUI
Data Length (DL)
Rx Data Buffer Pointer (RXDBPTR)
Figure 32-21. SSSAR Receive Buffer Descriptor
Table 32-12 describes the SSSAR RxBD fields.
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ATM AAL2
Table 32-12. SSSAR RxBD Field Descriptions
Description
1
Offset
Bits
Name
0x00
0
E
Empty
0 The buffer associated with this RxBD is full or data reception was aborted due to an
error. The core can read or write any fields of this RxBD. The CP does not use this
BD again while E remains zero.
1 The buffer associated with this RxBD is empty or reception is in progress. This RxBD
and its receive buffer are controlled by the CP. Once E is set, the core should not
write any fields of this RxBD.
1
2
CM
W
Continuous mode
0 Normal operation
1 The CP does not clear E after this BD is closed, allowing the associated buffer to
be reused automatically when the CP next accesses this BD. However, the E bit is
cleared if an error occurs while receiving, regardless of the CM bit setting.
Wrap (final BD in the table)
0 This is not the last BD in the RxBD table of the current channel.
1 This is the last BD in the RxBD table of this current channel. After this buffer has
been used, the CP receives incoming data for this channel into the first BD in the
table. The number of RxBDs in this table is programmable and is determined only
by the W bit. The current table cannot exceed 64 Kbytes.
3
4
I
Interrupt
0 No interrupt is generated after this buffer has been serviced.
1 An Rx buffer event is sent (provided that RxQD[RBM] is set) to the interrupt queue
after this buffer is serviced. The GHIN/GLIN bit in the event register is set when the
INT_CNT counter reaches terminal count.
L
Last. Set by the CP.
0 This is not the last buffer of the SSSAR SDU.
1 This is the last buffer of the SSSAR SDU.
5-6
RxError
Rx error occurred
00 No Rx error occurred
01 TE—Ras_Timer expired. The Ras Timer expired before this buffer could be
2
completed. The SSSAR SDU stored in this buffer is not completed.
10 US—Uncompleted SDU. A receive error caused a packet belonging to this
SSSAR SDU to be lost. The receiver discarded the rest of this SSSAR SDU.
11 OS—Oversized. The size of the SSSAR SDU has exceeded the
Max_SSSAR_SDU_Size parameter. The rest of the SDU was discarded.
7–10
—
Reserved, should be cleared during initialization.
11–15 UUI
Contains the UUI of the last packet in the received SDU. Valid only where the L bit is
set.
0x02
0x04
—
—
Data
Length
Contains the length of the buffer associated with this BD. If this is the last buffer (L=1)
of the SSSAR SDU, this field contains the total frame length.
RXDBPTR Rx data buffer pointer. Points to the address of the associated buffer. There are no
byte-alignment requirements for the buffer, and it may reside in either internal or
external memory. This value is not modified by the CP.
1
Boldfaced entries must be initialized by the user.
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ATM AAL2
When RAS timer expires the RxBD is closed with RAS timer expired indication, the Last (L) bit is not set, and RXF
2
interrupt is not issued. A new RxBD is opened for the next incoming AAL2 packet and the frame is processed as
normal and is treated as a new frame. When the next SSSAR end-of-frame indication is received, the RxBD at that
time is closed with an L indication, and if RxQD[RFM] = 1, the receiver issues an RXF interrupt.
32.5 AAL2 Parameter RAM
includes both the fields for general ATM operation and also the fields specific to AAL2 operation.
Note that some of the values must be initialized by the user, but values updated by the CP should not be
modified by the user.
Table 32-13. AAL2 Parameter RAM
Offset
Name
Width
Description
0x00–
0x3F
—
—
Reserved. Should be cleared during initialization.
0x40
0x42
0x44
RCELL_TMP_BASE
TCELL_TMP_BASE
UDC_TMP_BASE
Hword Rx cell temporary base address. Points to a total of 64 bytes reserved
dual-port RAM area used by the CP. Should be 64 byte aligned.
User-defined. (Recommended address space: 0x3000–0x4000 or
0xB000–0xC000.)
Hword Tx cell temporary base address. Points to total of 64 bytes reserved
dual-port RAM area used by the CP. Should be 64-byte aligned.
User-defined.
(Recommended address space: 0x3000–0x4000 or 0xB000–0xC000.)
Hword UDC mode only. Points to a total of 32 bytes reserved dual-port RAM
area used by the CP. Should be 64-byte aligned. User-defined.
(Recommended address space: 0x3000–0x4000 or 0xB000–0xC000.)
0x46
0x48
0x4A
0x4C
INT_RCT_BASE
INT_TCT_BASE
Hword Internal receive connection table base. User-defined.
Hword Internal transmit connection table base. User-defined.
Hword Internal transmit connection table extension base. User-defined.
INT_TCTE_BASE
RAS_Timer_Duration
Word Contains the RAS_Timer duration in microseconds for the SSSAR
sublayer. User-defined.
0x50
0x54
0x58
0x5C
EXT_RCT_BASE
EXT_TCT_BASE
EXT_TCTE_BASE
UEAD_OFFSET
Word
Word
Word
External receive connection table base. User-defined.
External transmit connection table base. User-defined.
External transmit connection table extension base. User-defined.
Hword User-defined cells mode only. The offset of the UEAD entry in the UDC
extra header. Should be an even address. If RCT[BO]=01
UEAD_OFFSET should be in little-endian format. For example if UEAD
entry is the first half word of the extra header in external memory,
UEAD_OFFSET should be set to 2 (second half word entry in internal
RAM).
0x5E
0x60
RxQD_Base_Int
PMT_BASE
Hword Points to the base address of the internal RxQD table. The pointer should
be 32-byte aligned. User-defined.
Hword Performance monitoring table base. User-defined.
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32-35
ATM AAL2
Table 32-13. AAL2 Parameter RAM (continued)
Width Description
Offset
Name
APCP_BASE
0x62
0x64
0x66
0x68
0x6A
0x6C
Hword APC parameters table base address. User-defined.
Hword Free buffer pool parameters table base. User-defined.
Hword Interrupt queue parameters table base. User-defined.
FBT_BASE
INTT_BASE
—
—
Reserved. Should be cleared during initialization.
UNI_STATT_BASE
BD_BASE_EXT
Hword UNI statistics table base. User-defined.
Word
Word
BD table base address extension. BD_BASE_EXT[0-7] hold the 8 most
significant bits of the RX/TxBD table base address.
BD_BASE_EXT[8-31] should be zero. User-defined.
0x70
VPT_BASE /
EXT_CAM_BASE
Base address of the address compression VP table/external CAM.
User-defined.
0x74
0x78
VCT_BASE
Word
Word
Base address of the address compression VC table. User-defined.
VPT1_BASE /
EXT_CAM1_BASE
Base address of the address compression VP1 table/EXT CAM1.
User-defined.
0x7C
0x80
0x82
VCT1_BASE
VP_MASK
Word
Base address of the address compression VC1 table. User-defined.
Hword VP mask for address compression lookup. User-defined.
VCI_Filtering
Hword VCI filtering enable bits. When cells with VCI = 3, 4, 6, 7-15 are received
and the associated VCI_Filtering bit = 1 the cell is sent to the raw cell
queue. VCI=3 is associated with VCI_Filtering[3], VCI=15 is associated
with VCI_Filtering[15]. VCI_Filtering[0–2, 5] should be zero. See
0x84
GMODE
(GMODE).”
0x86
0x88
0x8A
0x8C
0x90
0x94
0x98
COMM_INFO
Hword The information field associated with the last host command.
Hword
Hword
—
Word
Word
Word
Reserved. Should be cleared during initialization.
Preset for CRC32. Initialize to 0xFFFFFFFF.
CRC32_PRES
CRC32_MASK
AAL1_SNPT_BASE
Constant mask for CRC32. Initialize to 0xDEBB20E3.
Hword AAL1 SN protection look up table base address. (AAL1 only.) The
32-byte table resides in dual-port RAM and must be initialized by the user
0x9A
0x9C
—
Hword Reserved. Should be cleared during initialization.
SRTS_BASE
Word External SRTS logic base address. (AAL1 only.) Should be 16-byte
aligned.
0xA0
IDLE/UNASSIGN_BASE
IDLE/UNASSIGN_SIZE
Hword Idle/unassign cell base address. Points to dual-port RAM area contains
idle/unassign cell template (little-endian format). Should be 64-byte
aligned. User-defined. The ATM header should be 0x0000_0000 or
0x0100_0000 (CLP=1).
0xA2
Hword Idle/Unassign cell size. 52 in regular mode. 53–64 in UDC mode.
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ATM AAL2
Table 32-13. AAL2 Parameter RAM (continued)
Offset
Name
EPAYLOAD
Width
Description
0xA4
0xA8
Word
Word
Reserved payload. Initialize to 0x6A6A6A6A.
Trm
(ABR only) The upper bound on the time between F-RM cells for an
active source. TM 4.0 defines the Trm period as 100 msec. The Trm value
is defined by the system clock and the time stamp timer prescaler (See
RTSCR). For time stamp prescalar of 1µs, Trm should be set to 100
ms/1µs = 100,000.
0xAC
0xAE
0xB0
Nrm
Mrm
TCR
Hword (ABR only) Controls the maximum cells the source may send for each
F-RM cell. Set to 32 cells.
Hword (ABR only) Controls the bandwidth between F-RM, B-RM and user data
cell. Set to 2 cells.
Hword (ABR only) Tag cell rate. The minimum cell rate allowed for all ABR
channels. An ABR channel whose ACR is less than TCR sends only
out-of-rate F-RM cells at TCR. Should be set to 10 cells/sec as defined
in the TM 4.0. Uses the ATMF TM 4.0 floating-point format. Note that the
APC minimum cell rate should be at least TCR.
0xB2
0xB4
ABR_RX_TCTE
RxQD_Base_Ext
Hword (ABR only) Points to total of 16 bytes reserved dual-port RAM area used
by the CP. Should be 16-byte aligned. User-defined.
Word
Points to the base address of the external RxQD table. The actual
address of the first RxQD in the table is RxQD_Base_Ext + 512*4.
User-defined.
0xB8
0xBC
RX_UDC_Base
TX_UDC_Base
—
Word
Valid only for AAL2 VCs. Points to the base of the RX UDC header table
that contains the UDC headers of the AAL2 VCs. The pointer to a VC
UDC header is: RX_UDC_Base + 16*CH# (where CH# is the ATM
channel number)
Word
—
Valid only for AAL2 VCs. Points to the base of the TX UDC header table
that contains the UDC headers of the AAL2 VCs. The pointer to a VC
UDC header is: TX_UDC_Base + 16*CH# (where CH# is the ATM
channel number)
0xC0–
0xDF
Reserved. Should be cleared during initialization.
0xE0
TCELL_TMP_BASE_EXT Word
Transmit Cell Temporary base address. Points to a total of
64*last_AAL2_Ch# octets reserved in external memory for partially filled
cells. Note: TCELL_TMP_BASE_EXT must be on the same bus as the
all the AAL2 data buffers required for CPS, SSSAR and CID switching.
0xE4–
0xFB
—
—
Reserved. Should be cleared during initialization.
0xFC
PAD_TMP_BASE
—
Hword PAD template base address. Points to an internal memory area that
contains the zero cell template. Should be 64-byte aligned. User-defined.
0xFE
—
Reserved. Should be cleared during initialization.
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32-37
ATM AAL2
32.6 User-Defined Cells in AAL2
also applies to AAL2 operation. However, for AAL2 operation only, the UDC headers reside in a table in
external memory, not in the BDs.
For transmit channels in AAL2 UDC mode, initialize its UDC header entry in the TX UDC header table
before activating the channel. The header can be up to 12 bytes. The TX_UDC_Base parameter in the
The UDC header of a specific AAL2 transmit VC is located at the following address:
TX_UDC_Base + CH# *16 (where CH# is the ATM channel number)
For receive channels in AAL2 UDC mode, the receiver copies the UDC header from the first cell received
by the VC to the RX_UDC header table. The UDC headers of subsequent cells of that VC are discarded;
UDC extended address mode (UEAD) is not affected.
The UDC header of a specific AAL2 receive VC is located at the following address:
RX_UDC_Base + CH#*16 (where CH# is the ATM channel number)
UDC_Base
0
CH0 UDC header
CH1 UDC header
16
n*16
CHn UDC header
Figure 32-22. UDC Header Table
32.7 AAL2 Exceptions
For each VC, four circular interrupt queues are available. By programming RCT[INTQ] and TCT[INTQ]
for each VC, the user assigns an interrupt queue number.
When one of the CIDs generates an interrupt request, the CP writes a new entry to the interrupt queue
containing the ATM channel number, the CID and a description of the exception. Because CID = 0 is a
unique CID number, it is used to specify that the event is related to the VC rather than the CID. As with
all ATM exceptions, the valid (V) bit is then set and INTQ_PTR is incremented. When INTQ_PTR reaches
a location with the W bit set, it wraps to the first entry in the queue. More details can be found in
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ATM AAL2
0
1
2
3
10
11
12
13
14
15
Offset + 0x00
Offset + 0x02
V
—
W
CID
TBNR RXB BSY TXB RXF
Channel Code (CC)
Figure 32-23. AAL2 Interrupt Queue Entry CID ≠ 0
Table 32-14 describes the interrupt queue entry fields for a CID.
Table 32-14. AAL2 Interrupt Queue Entry CID ≠ 0 Field Descriptions
Offset
Bits
Name Description
0x00
0
V
Valid interrupt entry
0 This interrupt queue entry is free and can be used by the CP.
1 This interrupt queue entry is valid. The host should read this interrupt and clear this bit.
1
2
—
—
W
Wrap bit. When set, this is the last interrupt entry in the circular table. During initialization,
the host must clear all W bits in the table except the last one, which must be set.
3–10
11
CID
CID number. The exception occurred for this CID.
TBNR Tx buffer not ready interrupt. This interrupt is issued when the CP tries to open a TxBD,
which is not ready (R = 0). This interrupt is sent only if TxQD[BNM] = 1. The interrupt has
an associated channel code and CID.
Note: The CID number that is placed in the interrupt queue is the one currently located in
the last BD. Because the CID is not updated when the BD is not ready, the CID value
is the one extracted from this BD when it was last processed and transmitted. If the
BD is never processed and the BD was cleared, the CID value could be zero.
1
12
13
14
15
—
RXB
BSY
TXB
Rx buffer interrupt. This interrupt is issued when the I bit is set for an RxBD and the
RxQD[RBM] bit is set. This interrupt has an associated channel code and CID.
Busy condition. The RxBD table associated with this channel’s CID is busy. Packets were
discarded due to this condition.
Transmit buffer interrupt. This interrupt is issued when the TxBD[I] bit is set. This interrupt
is sent only if TxQD[TBM] is set. This interrupt has an associated channel code and CID.
1
RXF
Receive SSSAR SDU (frame). An SSSAR frame belonging to this channel’s CID has been
received. This interrupt is sent only if RxQD[RFM]=1.
0x02
CC
Channel code specifies the ATM channel number associated with this interrupt.
1
These interrupt queue fields are defined differently for other AAL types. Refer toTable 30-42 for more information.
.
0
1
2
3
10
11
12
15
Offset + 0x00
Offset + 0x02
V
—
W
0000_0000
Channel Code (CC)
Figure 32-24. AAL2 Interrupt Queue Entry CID = 0
Error_Code
Table 32-15 describes the interrupt queue entry fields for the VC. All the receive error events are enabled
by setting RCT[EM].
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32-39
ATM AAL2
Table 32-15. AAL2 Interrupt Queue Entry CID = 0 Field Descriptions
Name Description
Offset
0x00
Bits
0
V
Valid interrupt entry
0 This interrupt queue entry is free and can be used by the CP.
1 This interrupt queue entry is valid. The host should read this interrupt and clear this
bit.
1
2
—
—
W
Wrap bit. When set, this is the last interrupt circular table entry. During initialization,
the host must clear all W bits in the table except the last one, which must be set.
3–10
11
CID
—
CID number. Equals zero. This exception applies to the whole cell.
Reserved
12-15 Error_Code A receive error was detected.
0000 Parity error of the OSF.
0001 The STF sequence number is incorrect.
0010 The number of octets expected to overlap into this cell does not match the OSF.
0011 OSF is greater than 47.
0100 A packet HEC error was detected.
0101 The length of the CPS packet exceeds the Max_SDU_Length.
0111 A packet HEC error was detected in a split header packet.
0x02
—
CC
Channel code specifies the ATM channel number associated with this interrupt.
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Freescale Semiconductor
Chapter 33
Inverse Multiplexing for ATM (IMA)
NOTE
The functionality described in this chapter is available only on the
MPC8264 and the MPC8266.
Refer to www.freescale.com for the latest RAM microcode packages that
support enhancements.
This chapter provides specifications for the inverse multiplexing for ATM (IMA) microcode. In this
chapter, ‘IMA microcode’ and ‘microcode’ are synonymous.
33.1 Features
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
33-1
Inverse Multiplexing for ATM (IMA)
I
Table 33-1. IMA Sublayer in Layer Reference Model
User Plane
Functions
Layer Management
Functions
Plane Management
Functions
Layer
ATM
Sublayer
—
—
—
—
• ATM cell stream splitting
and reconstruction
• ICP Cell Insertion &
Removal
• IMA connectivity
• ICP cell errors (OIF)
• LIF/LODS/RDI-IMA defect • ATM cell rate change
processing
• RDI-IMA alarm generation
• Tx/Rx IMA link state report • IMA statistics
• IMA group configuration
• Link addition/removal
IMA Specific
• IMA group failure
notification
Transmission • Cell Rate decoupling
Convergence • IMA frame synch
• Stuffing
• Discarding bad-HEC cells
Physical
• No cell discarding
• No cell rate decoupling
Interface
—
—
• Cell delineation
Specific
• HEC error indication
• LCD-RDI alarm
Generation
• LCD failure notification
• TC statistics
• Cell scrambling &
Transmission
descrambling
Convergence
• Header error correction
• HEC generation &
verification
Physical
Medium
Dependent
• Bit timing
• Line coding
• Physical Medium
• Local alarm processing
• RDI alarm generation
• Link failure notification
• PMD state
The PowerQUICC II’s IMA microcode alone does not implement all of these functions. Software running
on the PowerQUICC II is responsible for managing the start-up procedure, handling changes in group
control, status, and maintaining the Link State Machine and Group State Machine. In general, the
PowerQUICC II IMA microcode implements most of the IMA sublayer user plane functions and provides
interrupts/statistics for the layer and plane management functions.
The key features of the IMA microcode are:
•
•
•
•
•
Supports any FCC with multi-PHY UTOPIA capability
Supports both IMA links and non-IMA links on the same FCC (on a per-PHY basis)
Supports up to 8 IMA groups with one FCC
Supports up to 8 links per IMA group using an internal TC layer hardware
Supports up to 31 links per IMA group using an external TC layer device. Note that a maximum
of 31 total links can be supported either on FCC1 or FCC2 but not concurrently on both FCCs)
•
Performs the following IMA User Plane functions
— ATM cell stream splitting and reconstruction
— ICP cell insertion/removal--communication of control and framing information
— Cell rate decoupling--insertion of ‘filler’ cells when ATM layer cells are unavailable
— IMA frame synchronization--finding IMA frame boundaries within links
— Stuffing--insertion of ‘stuff’ cells into fast links, in order to maintain an average data rate
between links of a group
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Freescale Semiconductor
Inverse Multiplexing for ATM (IMA)
— Discards cells with bad HECs (available on .25µm (HiP4) rev B silicon and forward)
•
•
•
•
•
Delay synchronization--correlating IMA frames among links of a group
Maximum differential delay supported is user-programmable
Optionally recovers IMA data clock rate (IDCR)
Provides interrupts on errors/state changes
Maintains low-level statistic counters
— Transmit stuff events
— Receive stuff events
— Receive ICP violations
— Receive Out-of-IMA Frame anomalies
33.1.1 References
The features provided by the IMA microcode are driven by The ATM Forum’s IMA specification. The
implementation of the IMA microcode is driven by the features, architecture, and resources available on
the PowerQUICC II. In addition to published PowerQUICC II device errata, users should be familiar with
the following (available at www.atmforum.com):
•
The ATM Forum Technical Committee. Inverse Multiplexing for ATM (IMA) Specification
Version 1.1 - AF-PHY-0086.001
•
The ATM Forum Technical Committee. Inverse Multiplexing for ATM (IMA) Specification
Version 1.0 - AF-PHY-0086.000
33.1.2 IMA Versions Supported
The IMA microcode supports IMA version 1.0 and version 1.1, with only minor configuration changes.
These include the following:
•
Programming the IMA version encoding in the OAM labels of the transmit ICP and Filler cell
templates.
•
Programming the validated OAM label field in the IMA group receive parameters.
33.1.3 PowerQUICC II Versions Supported
IMA support in ROM is available on the MPC8264 and the MPC8266. On these derivatives of the
PowerQUICC II family, integrated DS1/E1 transmission convergence (TC) layer hardware facilitates HEC
checking of received cells. (Refer to Chapter 34, “ATM Transmission Convergence Layer.”) So in these
PowerQUICC II devices, IMA support is available for either the integrated DS1/E1 TC layer or external
UTOPIA PHY devices connected via UTOPIA Level 2 multi-PHY.
33.1.4 PHY-Layer Devices Supported
The IMA microcode is primarily targeted at ATM’s primary application (i.e. IMA over multiple DS1/E1).
However, the IMA microcode supports any UTOPIA PHY device which (1) has a constant data rate and
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
33-3
Inverse Multiplexing for ATM (IMA)
(2) can be programmed not to screen out HEC-errorred cells. Most PHYs have this mode available for
IMA also.
33.1.5 ATM Features Not Supported
The following ATM features are not available for IMA links only, but are available for non-IMA links:
•
•
User-defined cells (UDC) (i.e. cells that are not 53 bytes and/or with customized headers)
Internal rate mode for APC scheduling
33.1.6 Additional Impact on PowerQUICC II Features
If the IDCR recovery feature is used, the following are true:
•
One of the IDMA channels are unavailable, and its resources are dedicated instead to the IDCR
master clock function. This can be any IDMA channel (1, 2, 3, or 4).
•
PowerQUICC II features sharing the IDMA channel’s parameter RAM page are unavailable.
33.2 IMA Protocol Overview
This section describes the IMA protocol, not the PowerQUICC II’s IMA microcode.
33.2.1 Introduction
Inverse Multiplexing over ATM (IMA) provides a cost effective solution to carry high speed connections,
for example, T3/E3 and OC-3c/STM-1 links, over already installed low speed connections, for example,
T1/E1 links, in a flexible way by dynamically adding/removing links as required, depending on the
bandwidth required.
IMA is defined as transmitting a stream of data over multiple low speed links and recombining the stream
in the correct order at the end. IMA involves inverse multiplexing and de-multiplexing of ATM cells in a
cyclical fashion among links grouped to form a higher bandwidth logical link whose rate is approximately
the sum of the link rates. This is referred to as an IMA group. Figure 33-1 provides a simple illustration of
ATM Inverse Multiplexing technique in one direction. This technique applies in the opposite direction.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
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Inverse Multiplexing for ATM (IMA)
IMA Group
IMA Group
TC
TC
Physical Link #1
Physical Link #2
+
PHY
+
PHY
Single ATM
Original ATM
Cell Stream to
ATM Layer
Cell Stream
from ATM
Layer
TC
+
PHY
TC
+
PHY
TC
+
PHY
TC Physical Link #3
+
PHY
TC
+
PHY
TC
+
PHY
Physical Link #4
Figure 33-1. Basic Concept of IMA
In the transmit direction (near-end), the ATM cell stream received from the ATM layer is distributed on a
cell by cell basis, across the multiple links within the IMA group. At the far-end, the receiving IMA unit
recombines the cells from each link, on a cell by cell basis, recreating the original ATM cell stream. The
aggregate cell stream is then passed to the ATM layer.The IMA protocol enables the
demultiplexing/deconstruction (transmit) of an ATM cell stream into multiple links. When receiving, the
IMA protocol multiplexes/reconstructs incoming cells from multiple links into the original ATM cell
stream. The IMA protocol must compensate for differences in clock rate and delay over the multiple links.
33.2.2 IMA Frame Overview
The IMA interface periodically transmits special cells that contain information that permit reconstruction
of the ATM cell stream at the receiving end of the IMA virtual link. The receiver end reconstructs the ATM
cell stream after accounting for the link differential delays, smoothing CDV introduced by the control
cells, etc. These cells, defined as IMA Control Protocol (ICP) cells, provide the definition of an IMA
frame. The transmitter must align the transmission of IMA frames on all links (shown in Figure 33-2). This
allows the receiver to adjust for differential link delays among the constituent physical links. Based on this
required behavior, the receiver can detect the defensible delays be measuring the arrival times of the IMA
frames on each link.
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33-5
Inverse Multiplexing for ATM (IMA)
IMA Frame Length = M cells
Link 0
ATM
ATM ATM
F
ICP2
F
ATM ATM
F
ICP1
F
F
ATM
F
ICP0
Link 1
2
M-1
3
1
0
F
F
ICP2 F ATM ATM
ATM ICP1
F
F
F
F
ICP0
F
ATM
Link 3
ATM
ICP2
F
F
ATM
F
ICP1 ATM
F
ATM
ATM
ATM
F
F
ICP0
ATM: ATM Layer Cell
ICPx: IMA Control Protocol Cell
Figure 33-2. Illustration of IMA Frames
F: Filler Cell
At the transmitting end, the cells are transmitted continuously. If there are no ATM layer cells to be sent
between ICP cells within an IMA frame, then the IMA transmitter sends filler cells to maintain a
continuous stream of cells at the physical layer. The insertion of Filler cells provides cell rate decoupling
at the IMA sublayer. The Filler cells should be discarded by the IMA receiver.
A new OAM cell is defined for use by the IMA protocol. The cell has codes that define it as an ICP or
Filler cell.
The data multiplexing performed by IMA is cell-based, where cells are distributed among the links in the
IMA group in a round-robin cycle. In order to compensate for different clock rates, IMA must periodically
insert ‘stuff’ cells into faster links in order to maintain a consistent average data rate over the links of the
group. Furthermore, IMA must compensate for potential differences in delay between the links of the
group. Per the IMA specification, the allowable delay differential for DS1/E1 links is 25ms, which at E1
rates is equivalent to approximately 118 cells. The IMA microcode allows the user to define the allowable
delay differential via a delay compensation buffer of programmable length.
IMA accomplishes these goals by the periodic insertion of special OAM cells, which (among other things)
define M-cell frame boundaries, provide frame sequence numbers, and provide stuffing information. This
framing information is used by the receiver to correlate the received cell streams and extract cells in-order
from the links of the IMA group, thereby reconstructing the original cell stream.
Figure 33-3. IMA Microcode Overview
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Inverse Multiplexing for ATM (IMA)
Link ID #1
Cell n+1
Cell 1
Phy 1
Cell n
Cell 3
Cell 2 Cell 1
Cell 4
Fast
IMA TX
Function
acting as a
Communication
ATM
TX
Cell 2
Controller
Phy 2
Virtual PHY
Function
Cell n
Link ID #N
Links 1 - N make up an IMA group
Phy n
Phy 1
Cell 1 Cell n+1
Cell 2 Cell 3 Cell 4
Cell 1
Cell n
Fast
IMA RX
Function
acting as a
Communication
ATM
RX
Cell 2
Cell n
Controller
Phy 2
Phy n
Virtual PHY
Function
33.2.3 Overview of IMA Cells
An IMA frame consists of M number of cells (M = 32, 64, 128, or 256 cells). Each frame consists of ATM
data cells and IMA control cells. Two types of IMA control cells are defined by and used by the IMA
protocol; IMA Control Protocol (ICP) cells and filler cells.
33.2.3.1 IMA Control Cells
There is at least one control cell (IMA Control Protocol) in each frame. An additional ICP cell may be
included in a frame to compensate for timing differences between the links in an IMA group (e.g., one link
is slightly faster than the other). The insertion of additional ICP cells to compensate for timing differences
between links is called a “stuff event”. The transmitter is responsible for inserting “stuff” ICP (SICP) cells
and the receiver will monitor for stuff indication and discard SICP cells. The location of the ICP cell in an
IMA frame is determined during the IMA start-up sequence.
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Link ID #1
Cell n+1
Cell 1
Phy 1
Phy 2
Cell n
Cell 3
Cell 2 Cell 1
Cell 4
Fast
Communication
IMA TX
Function
acting as a
ATM
TX
Cell 2
Controller
Virtual PHY
Function
Cell n
Link ID #N
Links 1 - N make up an IMA group
Phy n
Phy 1
Cell 1 Cell n+1
Cell 2 Cell 3 Cell 4
Cell 1
Cell n
Fast
IMA RX
Function
acting as a
Communication
ATM
RX
Cell 2
Cell n
Controller
Phy 2
Phy n
Virtual PHY
Function
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Link ID #1
Cell n+1
Cell 1
Phy 1
Cell n
Cell 3
Cell 2 Cell 1
Cell 4
Fast
IMA TX
Function
acting as a
Communication
ATM
TX
Cell 2
Controller
Phy 2
Virtual PHY
Function
Cell n
Link ID #N
Links 1 - N make up an IMA group
Phy n
Phy 1
Cell 1 Cell n+1
Cell 2 Cell 3 Cell 4
Cell 1
Cell n
Fast
IMA RX
Function
acting as a
Communication
ATM
RX
Cell 2
Cell n
Controller
Phy 2
Phy n
Virtual PHY
Function
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IMA Frame
.....
Cell n
ICP Cell
Cell 3
Cell 2 Cell 1
Cell 4
ICP Cell offset should be different for each link.
ICP cell offset is determined at start-up.
ICP Cell
7
9
6
8
18-49
11
50
X
12
14
17
1-5
Cell
10
Link
SI
15
51
13
16
52-53
CRC
IMA
FSN
ICP
cell
offset
Cell ID
TX
timing
info
end to
end
ch.
Grp.
Stat. &
Ctrl.
OAM
Stat. &
Ctrl CI
IMA
ID
RX
test
ptrn
TX
test
ptrn.
Link
info.
TX
test
ctrl
Label Link ID
Header
= b1011
PTI/CLP
0x64
HEC =
Link information for links 0-31
Figure 33-4. IMA Frame and ICP Cell Formats
The IMA protocol must compensate for potential differences in delay between the different links of the
IMA group. The allowable delay differential for DS1/E1 links is 25ms, which at E1 rates is equivalent to
approximately 118 cells.
33.2.3.2 IMA Filler Cells
At the transmitting end, cells are transmitted continuously. If there are no ATM layer cells to be sent
between ICP cells within an IMA frame, then the IMA transmitter sends filler cells to maintain a
continuous stream of cells at the physical layer. The insertion of Filler cells provides cell rate decoupling
at the IMA sublayer. The Filler cells should be discarded by the IMA receiver.
33.3 IMA Microcode Architecture
This chapter explains the architecture of the receive and transmit IMA microcode tasks.
33.3.1 IMA Function Partitioning
The IMA microcode performs only those functions with regular, critical real-time demands. The other
functions of IMA (e.g. control and management) are the responsibility of host software. As such, the IMA
microcode corresponds primarily to the user plane functions defined in the IMA specification, and
software must provide the layer management and plane management functionality. The IMA microcode
provides interrupts when interaction with layer management and plane management is required.
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33.3.1.1 User Plane Functions Performed by Microcode
•
•
•
•
•
•
ATM cell stream splitting and reconstruction
ICP cell insertion/removal
Cell rate decoupling (i.e. filler cell insertion/removal)
IMA frame synchronization
Stuffing
Discards cells with bad HECs (available on .25µm (HiP4) rev B silicon and forward)
33.3.1.2 Plane Management Functions Performed by Microcode
As stated above, most plane management functions must be performed in software. However, certain
statistics are intimately related to the lower-level user plane functions, and are thus best provided by the
microcode. These include the following:
•
•
•
ICP violations
Transmit stuff events
Receive stuff events
33.3.2 Transmit Architecture
This section discusses the behavior of the IMA microcode during transmission, focusing particularly on
the independent transmit clock (ITC) mode of IMA. Differences in behavior when common transmit clock
(CTC) mode is used are discussed at the end of this section.
Only one cell scheduler (known as the ATM pace controller or APC) is used per IMA group. This APC
schedules transmission for the IMA group as a single aggregate channel. The APC hands these cells off to
the IMA Tx microcode, which distributes these scheduled cells to each of the PHYs in the IMA group. To
compensate for clocking differences (jitter and average speed differential), the IMA Tx process distributes
ATM cells into N jitter buffers with a depth of 5 cells. The IMA PHYs take cells from these jitter buffers
and transmit them.
The cell scheduling is triggered by requests from the timing reference link (i.e. assertion of TxClav from
the TRL’s PHY). Requests from non-TRL PHYs only interact with the jitter buffer, and perform the
stuffing function as needed (when the jitter buffer becomes too shallow). Therefore, the microcode tasks
performed in response to TRL PHY requests and non-TRL PHY requests are different.
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APC
TRL Tx Task
N times
SAR
Tx Queue
Tx Queue
Tx Queue
Tx Queue
Jitter
Buffers
TRL Tx
non-TRL Tx
Task
UTOPIA Multi-PHY
Figure 33-5. IMA Transmit Task Interaction
33.3.2.1 TRL Operation
A request from the TRL PHY is used to trigger a complete round-robin process of cell scheduling and
distribution, distributing one cell for each of the transmit queues of the N links in the IMA group. For each
link, the microcode will:
1. Determine whether an ICP cell or a data/filler cell should be sent for the link:
— If data/filler, determine whether link is in ‘active’ or ‘filler-only’ mode
— If active, run the APC scheduling algorithm to find the next scheduled ATM channel
2. Distribute either:
— An ICP cell
— A filler cell (if ‘filler-only’ or ‘active’ with nothing scheduled in the APC)
— A data cell (if a channel is scheduled in the APC, performing the appropriate segmentation task
for the scheduled ATM channel, as determined by the channel’s AAL type)
The cells are distributed by writing the complete cells into circular transmit queues provided per link.
These transmit queues function as ‘jitter buffers’, as they are used to decouple the transmit rate of the TRL
PHY from the transmit rate of the non-TRL PHYs in the group to allow for clocking differences between
the PHYs.
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At startup, the non-TRL links will transmit filler cells until their transmit queues have reached a minimum
depth. In order to maintain less than the specified maximum +/-2.5 cell transmit timing differential (for
cells within an IMA frame), the TRL must exhibit the same behavior. Therefore, a 4-cell transmit buffer
is also maintained for the timing reference link. The timing reference link will only begin to pass ATM
layer cells to its PHY after it has 3 cells in its buffer. Prior to this, it will send filler cells. This behavior
will only be experienced at group start-up.
The TRL task will also implement the standard amount of stuffing on the TRL link by maintaining a
counter. When this task has scheduled (2048/ M) ICP cells for the TRL, a TRL stuff event will be flagged
and an indication of an upcoming stuff event will be signaled in the ICP LSI field. If a TRL stuff event is
flagged when the TRL task triggers, then a stuff cell will be sent to the TRL’s transmit queue, but no cells
will be sent to the transmit queues of the non-TRL PHYs. This forces a standard amount of stuffing on the
TRL, thereby reducing the effective data bit rate of the TRL to less than the minimum data clock rate
allowed by the clock rate tolerance of the physical-layer standard. Therefore by definition, this effective
data bit rate is achievable by the non-TRL links; the non-TRL links can either stuff less (if their data clock
rate is slower than the TRL), or stuff more (if their data clock rate is faster than the TRL).
33.3.2.1.1
TRL Service Latency
NOTE
The functionality described in this section is available only with the latest
RAM microcode package.
This optional feature allows the user to change the IMA APC behavior upon TRL request. When enabled
the TRL request will pass a programmable number of cells to the Tx queue of the links in an IMA group.
This can be used in order to suppress the TRL from consuming a large amount of bandwidth before another
cell is transmitted. The TRL request normally places a cell in a queue for N links where the group contains
N links; after this happens then a non_TRL link is free to pass a cell over the UTOPIA interface. The delay
for the TRL can be long and in some cases the TC layer FIFO can underrun. This feature can be used to
ensure that TRL and non-TRL requests are handled in the same manner - 1 cell in 1 cell out to the transmit
queues. The non-TRL requests will also trigger APC iterations when this feature is enabled. When using
this feature, the depth of the TRL transmit queue must equal the non-TRL queues.
33.3.2.2 Non-TRL Operation
A request from a non-TRL PHY does not trigger any scheduling task. The cells for non-TRL links will
already be supplied (by the TRL task) in its associated transmit queue. The TRL will simply read a cell out
of its transmit queue and update the queue pointers.
If the transmit queue becomes too shallow (because this link’s request rate is faster than the TRL), the link
will flag that a stuff event is imminent. The link will signal an upcoming stuff event in the LSI field of its
next ICP cell and will then flag that a stuff event is due. Having flagged this stuff event, the link will
continue sending cells from its queue as normal until it reaches its next ICP cell, upon which it indicates
a stuff event in the ICP cell and transmits it, but does not update the transmit queue pointers. When the link
next requests a cell, the previous ICP cell is repeated (since the queue pointers were not updated). This
process causes the transmit queue to deepen to the intended level.
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At group start-up, instead of accessing its transmit queue, the link will send filler cells. This is to allow the
transmit queues to reach their target steady-state depth. After the group start-up flag is cleared, normal
operation as described above will commence.
33.3.2.3 Transmit Queue Operation Examples (ITC mode)
The following diagrams demonstrate the different cases of queue operation, and consequently justify the
queue depth of 5 cells.
•
The extraction pointer points to the queue entry that is currently being supplied to the PHY. This
cell must be entirely ready when the PHY requests it.
•
The insertion pointer points to the queue entry which will be filled next by the TRL process.
In the figures, note that the pointers and filled queue locations are just shown with respect to the overall
queue depth available with the extraction pointer always shown at the bottom of the queue. This is done
only for the purpose of ease of illustration. In reality, the transmit queues are circular queues in which the
insertion and extraction pointers are continually rotating through the queue.
Tx Queue
Queue insertion pointer
(Filled by TRL task)
Floats between these
two positions
Normal ‘Wander zone’
Depth averages at 3.x
Queue extraction pointer
(Transmitted by non-TRL task)
Figure 33-6. Transmit Queue Normal Operating State
Tx Queue
TRL stuff event occurs
and this link is not given
a cell during a round
robin pass.
Normal ‘Wander zone’
Depth decreases to 2.x
“Imminent stuff” flagged
Queue extraction pointer
(Transmitted by non-TRL task)
Tx Queue
Queue insertion pointer
Normal ‘Wander zone’
Stuff event is performed
(ICP cell is left in queue
after transmission to be
sent one extra time.)
Depth increases back to 3.x
Queue extraction pointer
(Transmitted by non-TRL task)
Figure 33-7. Transmit Queue Behavior: Link Clock Rate Same as TRL
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Tx Queue
Queue insertion pointer
creeps up such that it
floats between these
two positions (wrapped)
Depth is 4.x
Normal ‘Wander zone’
Queue extraction pointer
(Transmitted by non-TRL task)
Tx Queue
Queue insertion pointer
Normal ‘Wander zone’
TRL stuff event happens,
so this link is not given a
cell during round robin.
Depth ratchets down to
normal operation of 3.x
Queue extraction pointer
(Transmitted by non-TRL task)
Figure 33-8. Transmit Queue Behavior: Link Clock Rate Slower than TRL
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Tx Queue
Tx Queue
Tx Queue
Tx Queue
TRL stuff event occurs
and this link is not given
a cell during a round
robin pass.
Depth decreases to 2.x
“imminent stuff” flagged
Normal ‘Wander zone’
Queue extraction pointer
(Transmitted by non-TRL task)
Normal ‘Wander zone’
Before stuff event can
happen, queue depth
creeps down below 2.x
threshold to 1.x
Queue extraction pointer
(Transmitted by non-TRL task)
Stuff event occurs,
bringing queue depth
back to 2.x
“imminent stuff’
remains flagged, but
is held off for minimum
5 frames.
Normal ‘Wander zone’
Queue extraction pointer
(Transmitted by non-TRL task)
Holdoff expires and
stuff event occurs,
bringing queue depth
back to normal depth
of 3.x
Normal ‘Wander zone’
Queue extraction pointer
(Transmitted by non-TRL task)
Figure 33-9. Transmit Queue Behavior: Link Clock Rate Faster than TRL, Worst-Case Event Sequence
33.3.2.4 Differences in CTC Operation
Overall, CTC operation is similar to ITC operation in task partitioning and overall structure. Differences
are as follows:
1. Transmit buffers are still maintained for the non-TRL links, but these buffers will not ‘jitter’, since
the transmit clocks are all the same. However, queue depths may vary slightly because PHY
requests, while synchronous, will not necessarily come in simultaneously (i.e. may have constant
offsets) and will definitely not be serviced simultaneously.
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2. The non-TRL tasks do not determine when to perform stuffing on the non-TRL links. When the
TRL flags ‘imminent stuff’ on its own link, it will flag ‘imminent stuff’ on all of the non-TRL links
as well. Thus, the non-TRL links will also stuff their links every 2048 cells.
3. The non-TRL queue depths are the same as the TRL’s queue (i.e. 4 cells).
33.3.3 Receive Architecture
The receive task consists of three parts. The first part is for cell reception from the link. The second part
provides the trigger for activating the cell processing task, including timing recovery if desired. The third
part performs the actual cell processing (i.e. passing cells to the ATM layer). The cell reception task
services requests from the links (via the UTOPIA multi-PHY interface and the FCC), maintains the link
state, and (if the link and group state dictates) writes the received cells into the link’s delay compensation
buffer in external memory. The cell processing activation function coordinates passing cells from the cell
reception task, on either an on-demand basis or at a rate determined by the reconstructed IDCR (IMA data
cell rate). The cell processing task extracts cells from the delay compensation buffers and passes them to
the ATM layer for processing.
Cell Processing
Task
Delay
Compensation
Buffers
Cell Processing Activation Function
Cell Reception
Task
UTOPIA Multi-PHY
Figure 33-10. IMA Receive Task Interaction
33.3.3.1 Cell Reception Task
In the cell reception task, received ICP cells in which an SCCI change is noted, except for the first ICP
received cell, are passed to a user-defined receive AAL0 channel to be processed by software. These
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received cells (and other event indications) are used by the software to initialize IMA links and groups,
and to manage transitions between link and group states.
The cell reception task centers around a four-state link state machine. Microcode tasks are performed
within each state, but transitions between states are managed by software. The processing of received cells
(both ICP cells and data cells) is determined by the state of the link.
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The states are described as follows:
•
Group Unassigned—This corresponds to a link which is known to be IMA, but for which no
information is known (e.g. IMA group number, IMA frame size). In this state, the receive task only
screens the incoming cells for ICP cells and discards all others. ICP cells in which an SCCI change
is noted are passed to a user-defined receive channel, where software must interpret their content
in order to initialize the link and add it to the group. The link transitions to the ‘Link IFSM
Unsynchronized’ state when the link’s ‘Group Assigned’ flag is set by software.
•
Link IFSM Unsynchronized—In this state, the link state machine has not yet found or validated
the frame boundary for this link. This state is initially entered after software defines the link’s M
value and expected ICP cell format, then sets the ‘Group Assigned’ flag. This state can be
subsequently re-entered as the result of a link defect. In this state, the link searches for an ICP cell,
then looks for ICP cells in the expected position of subsequent frames in order to validate frame
synchronization. Cells other than ICP cells are discarded. When the IFSM becomes synchronized,
an interrupt to the host is generated. The link transitions to the ‘Link Delay Unsynchronized’ state
when the link’s group and link synchronization flags are set appropriately by software.
•
•
Link Delay Unsynchronized—This state contains two separate operations, depending on the state
of the group to which the link belongs. If the link enters this state as the result of group start-up, it
performs the “new-group link delay synchronization algorithm”. If the link enters this state while
the group is already activated (per the link addition/slow recovery (LASR) procedure of the IMA
standard), it performs the “added-link delay synchronization algorithm”. As the result of either
algorithm, an interrupt will be generated to the host when delay synchronization is achieved.
No Link Defect—This is the state in which normal receive operation occurs after the link has been
established and the link-state has been communicated appropriately to the far end. If the link is not
inhibited at the group or link level, reception of ATM cells will occur. If the link or group is
inhibited, non-ICP received cells will be replaced with filler cells. In the “no link defect” state, cells
received (or their replacements) are written to the link’s delay compensation buffer. The link will
transition out of this state only as the result of an error or if reset by host software.
33.3.3.2 Cell Processing Activation Function
The cell processing activation function operates in two modes. The first, simplest mode is for on-demand
cell processing. The second mode is for cell processing as determined by the reconstructed IMA data cell
rate, as determined from the recovered receive data clock of the timing reference link (TRL) of the IMA
group.
33.3.3.2.1
On-Demand Cell Processing
In this mode, the cell processing activation function is null. The cell processing task is triggered directly
by the cell reception task if a cell is written to a delay compensation buffer.
This mode is strictly demand-driven; there is no attempt to reconstruct an IMA Data Cell Rate (IDCR)
from the IMA group at which to process incoming cells. Per the IMA specification, this is allowable under
the following conditions:
•
The IMA receiver is directly built into end equipment that directly terminates the ATM layer (i.e.
terminates all ATM connections), and
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•
The system is only capable of carrying services that either do not require CDV control (e.g. some
data services), or where the CDV is handled in some other way (e.g. absorbed in a play-out buffer
at the ATM layer connection termination).
The PowerQUICC II may qualify as such a system, if the PowerQUICC II terminates all ATM connections
that it receives. The buffer-descriptors and external memory serve as a play-out buffer.
Furthermore, a system which does not terminate cells, but instead passes cells port-to-port, can also use
this mode of operation if either of the following conditions are met:
•
All cell streams are switched at the VC level only, and the VC’s traffic type is one supported by the
PowerQUICC II’s APC. In this case, the APC of the PowerQUICC II can be programmed to
appropriately reshape the VC at the egress port, and therefore no cell delay variation (CDV) will
be introduced.
•
Some (or all) cell streams are switched at the VP level, but the switched VPs only carry traffic for
which cell delay variation (CDV) within the bounds of an IMA round-robin distribution is
tolerable. For example, if the IMA group consists of 8 DS1 links, then the maximum CDV
introduced by this method would be 8 cell times, or approximately 2.2ms
If the system meets the above qualifications, then this mode of operation is recommended, as it is the
simplest and will yield overall better system performance (i.e. this mode requires less CPM processing
power).
33.3.3.2.2
IDCR-Regulated Cell Processing
In this mode, cell processing is triggered at the recovered IMA data cell rate (IDCR). During group startup,
the microcode recovers the PHY clock rate of the TRL from the average period between requests from the
TRL PHY. It does this by averaging the difference of timestamps taken from the IDCR master timer
whenever the TRL’s PHY is serviced. As part of the group activation process, software calculates the
required IDCR request rate (scaling this rate by the number of links in the IMA group and by the
2048/2049 scale factor introduced by stuffing on the TRL), programs it in the IMA group’s associated
entry in the IDCR timer table, and enables the group’s IDCR timer table entry. Whenever a link is added
or removed from the group, software must update the IDCR timer table entry.
The IDCR timer table entries are maintained by the CPM according to the IDCR master timer. For each
IDCR master timer tick, the IDCR timer table entries are updated. When an IDCR timer table entry times
out, it triggers cell processing for one cell from the delay compensation buffers of its associated IMA
group. The timer table entry is then reset according to its IDCR request rate.
For this function to operate reliably and regularly, an adequate amount of CPM processing bandwidth must
be reserved for the microcode task that services the IDCR timers. If care is not taken with this aspect of
system design, then the IDCR task might miss the cell processing of incoming cells, resulting in the
eventual overflow of the delay compensation buffers. In order to ensure against this, it is recommended to
either (1) program the IDCR to run as a high-priority CPM task, or (2) leave an adequate margin of CPM
performance, on the order of 15%.
One additional benefit from IDCR-regulated cell processing is the microcode support for IMA group
service timeouts. If an active IMA group experiences 3 IDCR tick timeouts without having a data cell
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available in its delay compensation buffers, then the group is determined to have stalled and an error
interrupt is provided to software.
33.3.3.3 Cell Processing Task
The cell processing task is triggered by the cell processing activation function. When the cell processing
task is triggered, it will extract cells in-order from the delay compensation buffers. Cells extracted from
the delay compensation buffers are processed per the standard PowerQUICC II ATM operation (i.e.
mapped into ATM channels and processed per the appropriate AAL or OAM function).
If the on-demand cell processing activation function is used, then when the cell processing task is
triggered, it will extract cells in-order from the delay compensation buffers until either (1) no more are
available, or (2) four cells have been extracted. The purpose of limiting the cell processing task to a
maximum of four cells is to limit the maximum latency of servicing requests from the external PHYs. Note
that, on the average, the receive process will deliver one cell to the ATM layer per cell reception.
If the IDCR-regulated processing activation function is used, then one cell will be extracted from the delay
compensation buffers of a particular IMA group per timeout of that group’s IDCR timer.
33.4 IMA Programming Model
33.4.1 Data Structure Organization
Figure 33-12 shows the organization of IMA data structures.
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IMA Root Table
Filler Cell Template
IMA Data Structures
IMA Group Tx Table
Group 0
Transmit Queue Info
IMA Control Parameter
PHY Management
IMAEXTBASE
DCBs, TX Queue
.
.
.
External memory
(Local or 60x Bus)
must be aligned to
1MByte Boundary.
Group 7
IMA Group Rx Table
Group 0
.
.
.
IMAGRPT_TX
Group 7
IMAGRPT_RX
Link 0
IMALINKT_TX
.
.
.
IDCR Table
IMA Root Table
IMALINKT_RX
Link 31
IRLINKSTAT
IDCR param.
(Optional)
IMA Link Rx Table
Link 0
.
.
.
IMA Link Receive
Statistics Table
Link 31
IMA Link Tx Table
Internal DPRAM
Figure 33-12. IMA Root Table Data Structures
The IMA data structures are organized as follows:
•
Parameters at the FCC level determine common ATM parameters and location of the IMA Root
Table
•
•
IMA Root Table includes parameters that are used by all IMA links of this FCC
IMA Group Receive Table and IMA Group Transmit Table entries include parameters that define
the receive and transmit states and settings of the associated IMA group
•
•
IMA Link Receive Table and IMA Link Transmit Table entries include parameters that define the
receive and transmit states and settings of the associated IMA link
Optional IDCR Table that contains IDCR timers for the IMA groups
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33.4.2 IMA FCC Programming
33.4.2.1 FCC Registers
33.4.2.1.1
FPSMRx
IMA.
33.4.2.1.2
FTIRRx
For any PHY programmed in IMA mode (i.e. corresponding bit in IMAPHY is set), the corresponding
FTIRRx must be programmed to zero, for external rate mode. However, for PHYs 0-3, internal rate mode
may be selected for non-IMA PHYs. Refer to Section 30.13.4, “FCC Transmit Internal Rate Registers
33.4.2.2 FCC Parameters
33.4.2.2.1
TCELL_TMP_BASE and RCELL_TMP_BASE
The TCELL_TMP_BASE and RCELL_TMP_BASE have the same definitions as for a standard FCC, in
that they contain 64-byte aligned addresses of regions of DPRAM for temporary cell storage. However,
the 4 bytes leading and 4 bytes following the region indicated by TCELL_TMP_BASE must also be
reserved for use by the IMA microcode (thereby increasing its size to 60 bytes); and the 12 bytes following
the region indicated by RCELL_TMP_BASE must also be reserve for use by the IMA microcode (thereby
increasing its size to 64 bytes).
RCELL_TMP_BASE may be programmed to any 64-byte aligned address. TCELL_TMP_BASE must be
programmed to a 64-byte aligned address terminating with 0x40 (i.e. 0xnn40).
33.4.2.2.2
GMODE
IMA functionality in ROM is enabled using the GMODE register. Refer to Section 30.10.1.3, “Global
33.4.2.3 IMA-Specific FCC Parameters
The following parameter must be programmed in the FCC parameter RAM page in addition to the standard
FCC parameters for ATM.
Table 33-2. FCC Parameter RAM Additions
Offset
0xEE
Name
IMAROOT
Width
Description
Hword
Offset of IMA root table in DPRAM. Must be 128-byte aligned.
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Inverse Multiplexing for ATM (IMA)
NOTE
IMAROOT must be programmed to a 128-byte aligned address terminating
with 0x80 (i.e. 0xnn80).
33.4.3 IMA Root Table
1
Table 33-3. IMA Root Table
Offset
0x04
Name
Width
Description
2
IMAFILLERHD
4 Bytes Filler cell template. Used by microcode in transmission of filler cells. The
cell is formatted as byte-swapped, and additionally the header is
0x00–
0x2F
IMAFILLERPLD
48 Bytes
bitswapped. [This is due to hardware implementation, and does not imply
the order of the transmission of the cell. The transmission of the cell is per
the ATM standard.]
Content should be:
0xD0000000 (header)
0x6A6A0001 or 0x6A6A0003 (for IMA Version 1.0 or 1.1)
0x6A6A6A6A (padding)
0x6A6A6A6A (padding)
0x6A6A6A6A (padding)
0x6A6A6A6A (padding)
0x6A6A6A6A (padding)
0x6A6A6A6A (padding)
0x6A6A6A6A (padding)
0x6A6A6A6A (padding)
0x6A6A6A6A (padding)
0x6A6A6A6A (padding)
0xC6026A6A or 0xD9026A6A (for IMA Version 1.0 or 1.1)
0x30
0x31
FILLTAG
Byte
Byte
Tag indicating that the filler template is a filler cell. Program to zero.
TQ_SIZE
Transmit queue size. Recommended value is 0x18. Must be a multiple of 4.
0x32
0x33
TQ_TARGET
Byte
Transmit queue target level. Recommended value is 0x0C. Must be a
multiple of 4.
TQ_THRESHOLD Byte
Transmit queue stuff threshold. Recommended value is 0x0C. Must be a
multiple of 4.
0x34
0x36
RESERVED
Hword
Reserved.
IMACNTL
Byte
IMA control parameter. Controls functions shared by all IMA groups for this
FCC.
0x37
0x38
TMP_PCNT
Byte
Microcode managed parameter (pass count).
RXPHYEN
Word
Receive PHY enable. Bit array addressed by PHY address (e.g. bit 0
corresponds to PHY 0). Setting a bit enables reception for the
corresponding PHY. Must be used to enable/disable the corresponding
PHY regardless of whether or not the PHY is defined as IMA in IMAPHY.
All cells received by disabled PHYs are discarded. Note that the FCC must
also be enabled in GFMR[ENR] for reception to occur.
Bit 31 is reserved, and must be programmed to zero.
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1
Table 33-3. IMA Root Table (continued)
Width Description
Word
Offset
0x3C
Name
TXPHYEN
Transmit PHY enable. Bit array addressed by PHY address (e.g. bit 0
corresponds to PHY 0). Setting a bit enables transmission for the
corresponding PHY. Must be used to enable/disable the corresponding
PHY regardless of whether or not the PHY is defined as IMA in IMAPHY.
Only idle/unassigned cells are transmitted on disabled PHYs. Note that the
FCC must also be enabled in GFMR[ENT] for transmission to occur.
Bit 31 is reserved, and must be programmed to zero.
0x40
0x44
IMAPHY
Word
Word
Bit array addressed by PHY address (e.g. bit 0 corresponds to PHY 0).
Setting a bit defines the corresponding PHY to operate in IMA mode.
Clearing a bit defines the corresponding PHY to operate as a normal
(non-IMA) multi-PHY.
Bit 31 is reserved, and must be programmed to zero.
IMAEXTBASE
IMA external structure base pointer. Points to region in external memory
where external IMA data structures are located. Must be aligned to a 1MB
boundary (i.e. program bits 12-31 to zero).
0x48
0x4A
0x4C
0x4E
0x50
IMAGRPT_TX
IMAGRPT_RX
IMALINKT_TX
IMALINKT_RX
IRLINKSTAT
Hword
Hword
Hword
Hword
Hword
Offset of IMA group transmit table in DPRAM. Must be 16-byte aligned.
Offset of IMA group receive table in DPRAM. Must be 64-byte aligned.
Offset of IMA link transmit table in DPRAM. Must be 32-byte aligned.
Offset of IMA link receive table in DPRAM. Must be 32-byte aligned.
Offset of the optional IMA link receive statistics table in DPRAM. Must be
8-byte aligned.
0x52
0x54
0x56
0x58
0x5A
0X5C
0x5E
TMP_LPTR_RX
TMP_LPTR_TX
TMP_GPTR_TX
Hword
Hword
Hword
Microcode-managed parameter. Temporary storage of link table pointer.
Microcode-managed parameter. Temporary transmit table pointer.
Microcode-managed parameter. Temporary transmit group pointer.
Microcode-managed parameter. Temporary transmit group order pointer.
Microcode-managed parameter. Temporary receive group pointer.
Microcode-managed parameter. Temporary return pointer.
TMP_GPORD_TX Hword
TMP_GPTR_RX
TMP_RTRN_RX
Hword
Hword
TMP_GPTR2_RX Hword
Microcode-managed parameter. Temporary receive group pointer 2.
0x60–0x68 IDCR ROOT
—
PARAMETERS
0x68
0x6C
—
—
Reserved. Must be programmed to zero during initialization.
ITPGRPO
Hword
Required for optional TRL Service Latency enhancement only.
IMA Temp Group Order - Points to the base of a 2byte temp pointer storage
per group. Software initialized before FCC is enabled. Microcode managed
parameter.
0x6E–0x7
F
—
—
Reserved. Must be programmed to zero during initialization.
1
Boldfaced entries in the above table indicate parameters which must be initialized by the user. All other parameters
are managed by the microcode and should be initialized to zero unless otherwise stated.
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Inverse Multiplexing for ATM (IMA)
2
IMAFILLERHD is located at the word which immediately precedes the 128-byte aligned region defined by IMAROOT.
Thus it is located at offset - 0x04 from base of IMAROOT table.
33.4.3.1 IMA Control (IMACNTL)
0
1
2
3
4
5
6
7
Field
—
IRSE
IQB
DSB
—
INTQ
Figure 33-13. IMA Control (IMACNTL)
Table 33-4 describes the IMACNTL bit fields.
Table 33-4. IMACNTL Field Descriptions
Bits
0–1
Name
Description
—
Reserved
2
IRSE
IMA link receive statistics enable. If link receive statistics gathering is disabled, there is no
need to initialize IRLINKSTAT or reserve space for the receive statistics table.
0
1
Link receive statistics gathering is disabled.
Link receive statistics gathering is enabled.
3
4
IQB
Interrupt queue bus. Defines on which bus the IMA interrupt queue is located.
0
1
On the 60x bus.
On the local bus.
DSB
Data structure bus. Defines on which bus the IMA external structure memory area is
located.
0
1
On the 60x bus.
On the local bus.
5
—
Reserved.
6–7
INTQ
Number of the ATM interrupt queue dedicated to IMA events. Note that these do not include
ICP cell reception events; the handling of ICP cell reception events is programmed in the
RCT of the ICP channel defined by RICPCH.
33.4.4 IMA Group Tables
The IMA group tables consist of multiple IMA group structures indexed by group number, which ranges
from 0 to 7. The transmit and receive parameters are located in separate tables. The IMA group transmit
table entries are 16 bytes long. The IMA group receive table entries are 64 bytes long. However, there is
no need to reserve memory space in DPRAM for 8 receive IMA groups if less than 8 IMA groups are
required. To conserve memory space used by these tables, it is best to add groups starting from group
zero. Note also that group number is independent of the assignment of IMA ID.
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Inverse Multiplexing for ATM (IMA)
33.4.4.1 IMA Group Transmit Table Entry
1
Table 33-5. IMA Group Transmit Table Entry
Offset
0x00
Name
IGTCNTL
Width
Description
IMA group transmit control parameters.
Byte
Byte
0x01
IGTSTATE
IMA group transmit state. Microcode-managed parameter. Must be
initialized to zero at group start-up.
0x02
0x04
TGRPORDER
TVPHYNUM
Hword Offset of transmit group order table in DPRAM. Can be changed on the fly.
Byte
Transmit Virtual PHY number. Maps this IMA transmit group to a virtual
PHY number for the purpose of selecting an ATM pace controller (APC)
table number for this IMA group. Note that this parameter must be unique;
it must not conflict with the PHY number of any non-IMA PHYs or with the
TVPHYNUM of any other IMA group.
If there are any PHY numbers which will never be used in a system (i.e. the
actual PHY with the address does not exist), then TVPHYNUM should be
selected from one of these PHYs. If no such PHY numbers are available
(i.e. the multi-PHY interface consists of the full 31 PHYs), then select
TVPHYNUM from one of the PHY numbers of the PHYs within this IMA
group.
0x05
0x06
0x07
TIFSN
Byte
Byte
Byte
Transmit IMA Frame Sequence Number (IFSN). Microcode-managed
parameter. Increments each time an IMA frame is transmitted, cycling from
0 through 255. Should be initialized to zero at group start-up.
TMCTR
Transmit IMA M counter. Microcode-managed parameter. Tracks IMA frame
boundaries. Increments once per round-robin distribution of cells to the
transmit queues, cycling from 0 through M. Initialize to zero at group startup.
TRLSTFCNT
TRL stuff frame counter. Microcode-managed parameter. Controls required
stuffing on the TRL. Decrements each time an ICP cell is sent on the TRL,
cycling from TRLSTFN through 0. A TRL stuff event occurs when it reaches
zero. Initialize to the value of TRLSTFN at group start-up.
0x08
TICPPTR
Hword Offset of transmit ICP cell payload template area in DPRAM. Must be
64-byte aligned. This parameter and the associated template area may only
be changed when IGCNTL[ICPC]=IGTSTATE[ICPCA].
After changing TICPPTR, IGCNTL[ICPC] must be toggled.
0x0A
0x0B
TM
Byte
Byte
Transmit IMA frame size. Program to 31, 63, 127, or 255 for frame sizes (M)
of 32, 64, 128, or 256, respectively.
TRLSTFN
TRL stuff frame number. Defines the number of IMA frames sent between
TRL stuff events.
For ITC operation IGTCNT[CTC] = 0, program TRLSTFN = 2048/M. For
CTC operation IGTCNT[CTC] = 1, program TRLSTFN = (2048/M) – 1.
0x0C
0x0D
TNUMLINKS
Byte
Byte
Number of transmit links in the IMA group that are in the active state
(ILTCNTL[TXSC]=01). Used by the APC to scale the rescheduling
parameters appropriately when rescheduling channels.
RTSTPCNT
Real time-stamp subcounter. Microcode-managed parameter, used by the
APC. Initialize to zero at group start-up.
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Inverse Multiplexing for ATM (IMA)
1
Table 33-5. IMA Group Transmit Table Entry (continued)
Offset
0x0E
Name
IASNCCtr
Width
Description
Byte
Required for optional TRL Service Latency enhancement only.
IMA APC Scheduled Number of Cells Counter - Number of cells passed to
the groups links upon request. Initialize to IASNC.
0x0F
IASNC
Byte
Required for optional TRL Service Latency enhancement only.
IMA APC Scheduled Number of Cells - reset for IASNCtr. Number of cells
passed to the groups links upon request. Recommended value is 1.
1
Boldfaced entries must be initialized by the user. All other parameters initialize to zero.
33.4.4.1.1
IMA Group Transmit Control (IGTCNTL)
0
2
3
4
5
6
7
Field
—
TXSC
ISIE
CTC
ICPC
Figure 33-14. IMA Group Transmit Control (IGTCNTL)
Table 33-6 describes the IGTCNTL bit fields.
Table 33-6. IGTCNTL Field Descriptions
Bits
0–2
Name
Description
—
Reserved
Transmit status/control. Sets the transmit mode of the IMA group.
3-4
TXSC
00 Filler mode. The IMA group transmits only ICP and filler cells, no data cells.
01 Active mode. The IMA group is capable of sending data cells.
1XReserved.
5
ISIE
Required for optional TRL Service Latency enhancement only.
IMA Scheduler Split Iterations Enable
0 - APC is not split, TRL completes round robin distribution of cells.
1 - APC split, both TRL and non-TRL requests distribute cells to the transmit queues.
1
6
7
CTC
Transmit clock mode for this IMA group.
0 Independent transmit clock (ITC) mode.
1 Common transmit clock (CTC) mode.
ICPC
ICP change flag. Maintains at least the minimum 2-frame spacing of ICP cell control/status
changes. Initialize to zero at group start-up.
Must be toggled by software whenever TICPPTR is changed.
After two subsequent IMA frames are transmitted, the IGTSTATE[ICPCA] field will be changed
to match IGTCNTL[ICPC]. When IGTCNTL[ICPC] equals IGTSTATE[ICPCA], changes to
TICPPTR are allowed.
1
Ensure transmit clock mode is not changed during IMA group startup to avoid erratic behavior.
33.4.4.1.2
IMA Group Transmit State (IGTSTATE)
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33-31
Inverse Multiplexing for ATM (IMA)
0
1
2
3
4
5
6
7
Field
TSTF
TIMSTf
GTE
TRQS
ELX
—
ICH
ICPCA
Figure 33-15. IMA Group Transmit State (IGTSTATE)
Table 33-7. IGTSTATE Field Descriptions
Bits
Name
TSTF
Description
0
1
TRL stuff flag. Microcode-managed parameter. Indicates that the next ICP cell on the TRL will
be part of a stuff event. Initialize to zero at group startup.
TIMSTF
GTE
TRL imminent stuff flag. Microcode-managed parameter. Indicates that an upcoming stuff
event will be signalled in the next ICP of the TRL (via LSI=001). Initialize to zero at group
startup.
2
3
Go to end flag - TRL has requested 2 times before round robin distribution has completed or
link will underrun and is still due a cell from round robin distribution. Microcode managed
parameter initialize to 0. Used for optional TRL Service Latency enhancement only.
TRQS
TRL Request - TRL has requested therefore 1 round robin distribution of cells and is yet to be
completed. Microcode managed parameter initialize to 0. Used for optional TRL Service
Latency enhancement only.
4
5
6
7
ELX
—
Early exit flag. Microcode-managed parameter. Initialize to zero at group startup.
Reserved
ICH
ICP change holdoff. Microcode-managed parameter. Initialize to zero at group startup.
ICP change allowed flag. Microcode-managed parameter. See description of IGTCNTL[ICPC].
ICPCA
33.4.4.1.3
Transmit Group Order Table
The transmit group order table defines the order of the links in the round-robin distribution of cells to the
links of the IMA group. The table consists of an array of bytes ordered from first link to last link, with each
byte providing the PHY address of its associated link. The end of the table is indicated by an entry
programmed to 0x1F.
This table alone defines the order of cell distribution. It is the responsibility of software to program the
LID of the links in the IMA Link Table entries, and to program the group order table such that its order
corresponds to the order of increasing LIDs within the group.
0
2
3
7
Field
—
PHY ADDRESS
Figure 33-16. Transmit Group Order Table Entry
Table 33-8 describes the format of a transmit group order table entry.
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Inverse Multiplexing for ATM (IMA)
Table 33-8. Transmit Group Order Table Entry Field Descriptions
Name Description
Bits
0–2
—
Reserved
3–7
PHY
ADDRESS
PHY address (Up to 31 PHYs[0–30]) of the link transmitting in this position in the round-robin.
A value of 0x1F in this field indicates the end of the group order table.
33.4.4.1.4
ICP Cell Templates
The ICP cell templates are areas of memory provided by software to the microcode for construction of ICP
cells for transmission. Software prepares the fields which are common to the group (i.e. class B, C, D, and
E parameters). The other (class A) parameters will be written to the appropriate fields by the microcode.
The template is 53 bytes long and must be aligned on a 64-byte boundary.
Table 33-9 describes the format of a group order table entry. The ICP cell template is formatted as
byte-swapped, and additionally the ICP cell header is bitswapped. [This is due to hardware
implementation, and does not imply the order of transmission of the cell. The transmission of the cell is
per the ATM standard.] Reflecting this byte-swap, the offset column gives the offset in DPRAM from the
ICP template base.
1
Table 33-9. ICP Cell Template
Offset
0x00
Name
Width
Word
Description
ICP CELL HEADER
ICP cell header. Program to 0xD0000000.
0x04
0x05
0x06
0x07
ICP Cell Offset
Byte
Byte
Byte
Byte
Microcode-managed area. Microcode will program this field
dynamically.
IMA Frame Sequence
Number
Microcode-managed area. Microcode will program this field
dynamically.
Cell ID and Link ID
Microcode-managed area. Microcode will program this field
dynamically.
OAM LABEL
IMA Version value.
1
3
IMA Version 1.0
IMA Version 1.1
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33-33
Inverse Multiplexing for ATM (IMA)
1
Table 33-9. ICP Cell Template (continued)
Offset
0x08
Name
Width Description
GROUP STATUS AND Byte
CONTROL
Bits 7-4: Group State
0000 = Start-up,
0001 = Start-up-Ack,
0010 = Config-Aborted - Unsupported M,
0011 = Config-Aborted - Incompatible Group Symmetry,
0100 = Config-Aborted - Unsupported IMA Version,
0101, 0110 = Reserved for other Config-Aborted reasons in a future
version of the IMA specification,
0111 = Config-Aborted - Other reasons,
1000 = Insufficient-Links,
1001 = Blocked,
1010 = Operational,
Others: Reserved for later use in a future version of the IMA
specification.
Bits 3-2: Group Symmetry Mode
00 = Symmetrical configuration and operation,
01 = Symmetrical configuration and asymmetrical operation (optional),
10 = Asymmetrical configuration and asymmetrical operation
(optional),
11 = Reserved
Bits 1-0: IMA Frame Length (00: M=32, 01: M=64, 10: M=128, 11:
M=256)
0x09
0x0A
IMA ID
Byte
Byte
Bits 7-0: IMA ID
STATUS AND
CONTROL CHANGE
INDICATION (SCCI)
Software must increment this field in the new ICP template whenever a
new ICP template is created.
0x0B
Link Stuff Indication
Byte
Microcode-managed area. Microcode will program this field
dynamically.
0x0C
0x0D
0x0E
RX TEST PATTERN
TX TEST PATTERN
TX TEST CONTROL
Byte
Byte
Byte
Bits 7-0: Rx Test Pattern (value from 0 to 255)
Bits 7-0: Tx Test Pattern (value from 0 to 255)
Bits 7-6: Unused and set to 0
Bit 5: Test Link Command (0: inactive, l: active)
Bits 4-0: Tx LID of test link (0 to 31)
0x0F
TRANSMIT TIMING
INFORMATION
Byte
Bits 7-6: Unused and set to 0
Bit 5: Transmit Clock Mode: (0: ITC mode, 1: CTC mode)
Bits 4-0: Tx LID of the timing reference (0 to 31)
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
LINK 3 INFO
LINK 2 INFO
LINK 1 INFO
LINK 0 INFO
LINK 7 INFO
LINK 6 INFO
LINK 5 INFO
LINK 4 INFO
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Status and control of link with LID = 3
Status and control of link with LID = 2
Status and control of link with LID = 1
Status and control of link with LID = 0
Status and control of link with LID = 7
Status and control of link with LID = 6
Status and control of link with LID = 5
Status and control of link with LID = 4
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1
Table 33-9. ICP Cell Template (continued)
Offset
0x18
Name
Width
Byte
Description
LINK 11 INFO
LINK 10 INFO
LINK 9 INFO
LINK 8 INFO
LINK 15 INFO
LINK 14 INFO
LINK 13 INFO
LINK 12 INFO
LINK 19 INFO
LINK 18 INFO
LINK 17 INFO
LINK 16 INFO
LINK 23 INFO
LINK 22 INFO
LINK 21 INFO
LINK 20 INFO
LINK 27 INFO
LINK 26 INFO
LINK 25 INFO
LINK 24 INFO
LINK 31 INFO
LINK 30 INFO
LINK 29 INFO
LINK 28 INFO
CRC10
Status and control of link with LID = 11
Status and control of link with LID = 10
Status and control of link with LID = 9
Status and control of link with LID = 8
Status and control of link with LID = 15
Status and control of link with LID = 14
Status and control of link with LID = 13
Status and control of link with LID = 12
Status and control of link with LID = 19
Status and control of link with LID = 18
Status and control of link with LID = 17
Status and control of link with LID = 16
Status and control of link with LID = 23
Status and control of link with LID = 22
Status and control of link with LID = 21
Status and control of link with LID = 20
Status and control of link with LID = 27
Status and control of link with LID = 26
Status and control of link with LID = 25
Status and control of link with LID = 24
Program to 0x00.
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Hword
Status and control of link with LID = 30
Status and control of link with LID = 29
Status and control of link with LID = 28
Microcode-managed area. Microcode will program this field
dynamically.
0x32
END-TO-END
CHANNEL
Byte
Program to any value desired for end-to-end
implementation-dependent signalling, or program to 0x00 if unused.
0x33
0x34
UNUSED
TAG
Byte
Byte
Program to 0x6A.
Internally-used tag value indicating that this is an ICP cell. Program to
0x80.
1
Boldfaced entries in the above table indicate parameters which must be initialized by the user. All other
parameters are managed by the microcode and should be initialized to zero unless otherwise stated.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
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33-35
Inverse Multiplexing for ATM (IMA)
33.4.4.2 IMA Group Receive Table Entry
1
Table 33-10. IMA Group Receive Table Entry
Offset
0x00
Name
IGRCNTL
Width
Byte
Description
IMA group receive control parameters.
0x01
IGRSTATE
Byte
IMA group receive state. Microcode-managed parameter. Initialize to
zero at group startup.
0x02
0x03
RIMAID
IMAVER
Byte
Byte
Receive IMA ID. Program to the validated receive IMA ID value.
IMA version. Program to the validated IMA version value.
1 IMA Version 1.0
3 IMA Version 1.1
0x04
0x05
0x06
RM
Byte
Byte
Byte
Receive IMA frame size. Program to 31, 63, 127, or 255 for frame sizes
of 32, 64, 128, or 256, respectively.
RNUMLINKS
DCB_RM
Number of receive links in the IMA group that are in the active state
(ILRCNTL[RXSC]=01.
Current cell (x out of RM cells in a Frame) being processed by the
reconstruction routine. Microcode-managed parameter. Initialize to
zero at group startup.
0x07
0x08
RSCCI
Byte
Receive IMA SCCI field. Microcode-managed parameter. Holds the
SCCI value of the last ICP cell received by this group.
DCBLNK
Hword
Pointer to link entry in group order table currently in use.
Microcode-managed parameter. Initialize to value of RGRPORDER0 at
group startup.
0x0A
0x0C
DCBX
Hword
Byte
Delay-compensation buffer extraction pointer. Microcode-managed
parameter. Initialize to zero at group startup.
STALL_COUNT
Number of IDCR or On-demand requests made for which there were
no cells available in a link’s DCB. Microcode managed parameter.
Initialize to zero at group startup.
0x0D
0x0E
REF_IFSN
GFP
Byte
Identifies the IFSN of the frame being processed by the
“reconstruction” routine. Microcode managed parameter.
Hword
Pointer to the start of the current frame being processed by the
“reconstruction” routine. Microcode managed parameter. Initialize to
zero at group startup.
0x10
0x12
0x14
RGRPORDER0
RGRPORDER1
ALPHABETA
Hword
Hword
Byte
Offset of receive group order table 0 in DPRAM.
Offset of receive group order table 1 in DPRAM.
Alpha and beta parameters for IMA frame synchronization mechanism
(IFSM).
Bits 0-3: Alpha. Allowable range is 1-2; typical value is 2.
Bits 4-7: Beta. Allowable range is 1-5; typical value is 2.
0x15
GAMMA
Byte
Gamma parameter for IMA frame synchronization mechanism (IFSM).
Allowable range is 1-5; typical value is 1.
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1
Table 33-10. IMA Group Receive Table Entry (continued)
Offset
0x16
Name
Width
Description
TRLR
Hword
TRL rate. Used only when IDCR-regulated cell processing is used (i.e.
IGRCTNL[IDCR]=1). Calculated by microcode during group startup,
prior to group activation. Referenced by software in order to program
the IDCRREQ and IDCRREQF of the group’s IDCR table entry. Value
is valid after IGRSTATE[IDCR_DN] is set by the microcode.
0x18
0x1C
0x20
0x24
REF_LINK
LINK_ICP
LINK_DCB
LINK_LD
Word
Word
Word
Word
Bit array identifying which of the links (i.e., PHY) in this group are
enabled. Bit 0 corresponds to PHY 0, bit 30 corresponds to PHY 30.
Software must set the corresponding bits to 1 so that the delay
compensation process for the link(s) is started.
Bit array identifying which of the links in this group has received an ICP
cell. A “1” in the corresponding link’s bit position indicates that an ICP
cell has been received. Microcode-managed parameter. Initialize to
zero at group startup.
Bit array identifying which of the links in this group has started storing
cells to its corresponding DCB. A “1” in the corresponding link’s bit
position indicates that cells have been stored in the DCB.
Microcode-managed parameter. Initialize to zero at group startup.
Bit array identifying which of the “added” links in this group has a
Longer propagation Delay (LD) than any of the existing links. A “1” in
the corresponding link’s bit position indicates that it has a longer
propagation delay. Microcode-managed parameter. Initialize to zero at
group startup.
0x28
0x29
CELL_COUNT
Byte
Byte
Number of cells received on the TRL while in the Group Delay Sync.
stage. Used only when IDCR-regulated cell processing is used (i.e.
IGRCTNL[IDCR]=1). Used for determining TRLR. When
CELL_COUNT = 128, TRLR is calculated and can be used for
programming IDCR timer values. Microcode-managed parameter.
Initialize to zero at group startup.
RVPHYNUM
Receive Virtual PHY number. Maps this IMA receive group to a virtual
PHY number for the purpose of address mapping of received cells.
Note that this parameter must be unique; it must not conflict with the
PHY number of any non-IMA PHYs or with the RVPHYNUM of any
other IMA group.
If there are any PHY numbers which will never be used in a system (i.e.
the actual PHY with the address does not exist), then RVPHYNUM
should be selected from one of these PHYs. If no such PHY numbers
are available (i.e. the multi-PHY interface consists of the full 31 PHYs),
then select RVPHYNUM from one of the PHY numbers of the PHYs
within this IMA group.
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1
Table 33-10. IMA Group Receive Table Entry (continued)
Offset
0x2A
Name
Width
Byte
Description
STALL_THR
Stall threshold. Used to detect stalled links when performing
round-robin cell extraction from the delay compensation buffers (Dcbz).
This is the number of cells which may be received without advancing
the cell extraction pointer.
The value is application-dependent and must be tuned by the user to
the “expected worst case.” Its value depends on the depth of queues
and FIFOs in the complete transmit/receive path, and the ’burstiness’
of the behavior of the FIFOs. Assuming very bursty FIFOs, it is
approximately:
STALL_THR = 2 x RNUMLINKS x (3 + RX_FIFO)
where:
a) RNUMLINKS is the number of links in the receive group order
structure (regardless of link status).
b) RX_FIFO is the depth of the receive FIFOs of the TC layer.
c) 3 is the rounded value of the allowed transmit skew between links of
a group (2.5, per the IMA standard).
An optimal value for STALL_THR will be great enough to produce no
link stall events in normal operation, but low enough to detect a failed
link as quickly as possible.
0x2B
IRGFS
Byte
IMA Receive Group Frame Size
Bits 0-5: Reserved
Bits 6-7 - GSC_M: Value of received ICP cell Group Status Contl field
(Bits 1:0) which determine the IMA frame size. This field must be
programmed before links in the group are assigned
0x2C
0x30
—
Word
Word
Reserved. Must be initialized to zero at group startups.
LINK_DCBO
Link DCB overflow interrupt indication. Bit array identifying which links
have issued a link DCB overflow (DCBO) interrupt. This parameter
ensures that only one DCBO interrupt is generated per event.
Microcode managed parameter. Initialize to zero at group startup.
0x34–
0x3F
—
3 Words Reserved. Must be initialized to zero at group startups.
1
Boldfaced entries indicate parameters that must be initialized by the user. All other parameters are
managed by the microcode and should be initialized to zero unless otherwise stated.
33.4.4.2.1
IMA Group Receive Control (IGRCNTL)
0
1
2
3
4
5
6
7
Field
GOTP
—
RXSC
IDCR
—
Figure 33-17. IMA Group Receive Control (IGRCNTL)
Table 33-11 describes the IGRCNTL bit fields.
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Inverse Multiplexing for ATM (IMA)
Table 33-11. IGRCNTL Field Descriptions
Description
Bits
Name
GOTP
0
Group order table pointer. Defines which group order table pointer (RGRPORDER0 or
RGRPORDER1) will be used for the cell extraction round-robin. Initialize to zero at group
startup.
1–2
3-4
—
Reserved, initialize to zero.
RXSC
Receive status/control. Sets the receive mode of the IMA group.
00 Filler mode. The IMA group processes only ICP cells. Data cells are replaced with filler
cells.
01 Active mode. The IMA group is capable of receiving data cells.
1XReserved. Defaults to Filler Mode.
5
IDCR
—
IDCR recovery enable. Selects the mode of the receive process activation function.
0 On-demand cell processing
1 IDCR-regulated cell processing
6-7
Reserved, initialize to zero.
33.4.4.2.2
IMA Group Receive State (IGRSTATE)
0
1
2
3
7
Field IDCR_DN
GDSS
—
Figure 33-18. IMA Group Receive State (IGRSTATE)
Table 33-12. IGRSTATE Field Descriptions
Bits
Name
Description
0
IDCR_DN
IDCR Done. Microcode-managed parameter. When this bit is set by the microcode, the TRLR
value is valid and can be used to program the IDCR timer entry values for this group. Initialize
to zero at group startup.
1-2
GDSS
Group delay synchronization state. Initialize to zero at group startup. Must be changed by
software to 01 after sufficient links have achieved frame synchronization. Subsequently
managed by microcode.
00 Group delay synchronization process inhibited.
01 Group delay synchronization process enabled.
10 Group delay synchronization process in progress.
11 Group delay synchronized.
3-7
—
Reserved, initialize to zero.
33.4.4.2.3
IMA Receive Group Frame Size
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Inverse Multiplexing for ATM (IMA)
0
1
6
7
Field
0
—
GSC-M
Figure 33-19. IMA Receive Group Frame Size (IGRSTATE)
Table 33-13 describes the IRGFS bit fields.
Table 33-13. IRGFS Field Descriptions
Bits
Name
Description
0
0
Reserved, initialize to zero.
Reserved, initialize to zero.
1-5
6-7
—
GSC-M
IMA Receive Group Frame Size
Bits 0-5: Reserved
Bits 6-7 - GSC_M: Value of received ICP cell Group Status Contl field
(Bits 1:0) which determine the IMA frame size. This field must be
programmed before links in the group are assigned
33.4.4.2.4
Receive Group Order Tables
The receive group order tables define the order of the links in the round-robin extraction of cells to the
links of the IMA group. The table consists of an array of bytes ordered from first link to last link, with each
byte providing the PHY address of its associated link. The end of the table is indicated by an entry
programmed to 0x1F.
Two group order tables are used in order to allow for on-the-fly changes (i.e. to add or remove links), while
making certain that the changes only occur at the end of a round-robin cycle. IGRCNTL[GOTP] indicates
which group order table pointer (and therefore, group table) is currently in use. Changes should be made
to the group order table not in use, and then IGRCNTL[GOTP] should be toggled. When the current
round-robin cell extraction process completes, the next process will use the new table.
This table alone defines the order of cell extraction from the delay compensation buffers. It is the
responsibility of software to read the LIDs of the links in the group from the received ICP cells during
group startup, and to program the group order table such that its order corresponds to the order of
increasing LIDs within the group.
0
2
3
7
Field
—
PHY ADDRESS
Figure 33-20. Receive Group Order Table Entry
Table 33-14 describes the format of a receive group order table entry.
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Table 33-14. Receive Group Order Table Entry Field Descriptions
Name Description
Bits
0–2
3–7
—
Reserved, initialize to zero.
PHY
ADDRESS
PHY address (up to 31 PHYs[0–30]) of the link transmitting in this position in the round-robin.
A value of 0x1F in this field indicates the end of the group order table.
33.4.5 IMA Link Tables
The IMA link tables consist of multiple IMA group structures indexed by the PHY address of their
corresponding PHYs. The transmit and receive parameters are located in separate tables. The IMA group
transmit and receive table entries are each 32 bytes long.
Note that to conserve memory space consumed by these tables, it is best to group the addresses of the
PHYs that are assigned as IMA. [For example, if out of eight total links only four are IMA, then optimally
these would be links 0 through 3.]
33.4.5.1 IMA Link Transmit Table Entry
1
Table 33-15. IMA Link Transmit Table Entry
Offset
0x00
Name
ILTCNTL
Width
Byte
Description
IMA link transmit control parameters.
0x01
ILTSTATE
Byte
IMA link transmit state. Microcode-managed parameter. Initialize to
zero at link startup.
0x02
LICPOS
Byte
Link ICP offset. Determines the position of the ICP cell within the IMA
frame. Program in the range 0 to M-1. See the IMA specification for
recommended methods for programming this field.
0x03
ILID
Byte
IMA link ID. Formatted per the Cell ID and Link ID field of an ICP cell.
Bit 0: 1 (indicating ICP cell)
Bits 1-2: Not Used, set to zero
Bits 3-7: Program to software-assigned LID.
[Note: This value is only used by microcode to format ICP cells for this
link, it is not used to determine round-robin transmission order. That
function is performed by the group order table.]
0x04
0x08
0x0A
ITSEC
ITQSP
ITQEP
Word
IMA transmit stuff event counter. While ILTCNTL[SES]=0, increments
each time a stuff event is performed on this link. Initialize to zero at link
startup.
Hword
Hword
IMA link transmit queue start pointer. This parameter forms bits 12-27
of the pointer; bits 0-11 are from IMAEXTBASE, and bits 28-31 are
IMA link transmit queue end pointer. This parameter forms bits 12-27
of the pointer; bits 0-11 are from IMAEXTBASE, and bits 28-31 are
zero. Points to the last cell in the transmit queue. Program this
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1
Table 33-15. IMA Link Transmit Table Entry (continued)
Offset
0x0C
Name
Width
Description
ITQFP
ITQXP
Hword
IMA link transmit queue fill pointer. This parameter forms bits 12-27 of
the pointer; bits 0-11 are from IMAEXTBASE, and bits 28-31 are zero.
0x0E
0x10
Hword
Byte
IMA link transmit queue extract pointer. This parameter forms bits
12-27 of the pointer; bits 0-11 are from IMAEXTBASE, and bits 28-31
ITINTMSK
IMA transmit interrupt mask. Has the same format as the upper byte of
the IMA interrupt queue entry. Setting a bit enables the associated
interrupt; clearing a bit masks it.
For group-related events, only the mask register for the TRL is
referenced.
0x11
0x12
ITINTSTAT
LSHC
Byte
Byte
IMA transmit interrupt status. Indicates the status of transmit interrupt
events.
Stuff holdoff counter. Maintains the minimum five-frame spacing
between stuff events for non-TRL links. Must be initialized to zero. Set
to 4 by the microcode after a stuff event, and decrements after each
ICP cell is sent (saturating at zero). Signalling of ‘imminent stuff’ (and
subsequent stuff events) will not occur while this counter is non-zero.
1
Boldfaced entries indicate parameters that must be initialized by the user. All other parameters are
managed by the microcode and should be initialized to zero unless otherwise stated.
33.4.5.1.1
IMA Link Transmit Control (ILTCNTL)
0
1
2
3
4
5
7
field
TRL
SES
—
TXSC
IGNUM
Figure 33-21. IMA Link Transmit Control (ILTCNTL)
Table 33-16 describes the ILTCNTL bit fields.
Table 33-16. ILTCNTL Field Descriptions
Bits
Name
TRL
Description
0
Defines this link as the timing reference link (TRL) of the group.
0 This link is not the TRL.
1 This link is the TRL.
Note: One and only one link of the group must be programmed as the TRL. If zero or more than
one links are defined as TRL, erratic operation will occur.
1
2
SES
—
Severely errored seconds. Set by software when a severely errored second indication is
detected. When set, causes the transmit stuff event counter to stop counting.
Reserved, initialize to zero.
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Inverse Multiplexing for ATM (IMA)
Table 33-16. ILTCNTL Field Descriptions (continued)
Bits
3-4
Name
TXSC
Description
Transmit status/control. Sets the transmit mode of the IMA link.
00 Filler mode. The IMA link transmits only ICP and filler cells, no data cells.
01 Active mode. The IMA link is capable of sending data cells.
1XReserved.
5-7
IGNUM
Determines to which IMA group this link belongs. Contains the number of the link’s associated
IMA Group Table entry.
Note: This value need not be the same as the group’s IMA ID; the IMA ID is programmed
separately in the group’s ICP cell template.
33.4.5.1.2
IMA Link Transmit State (ILTSTATE)
0
1
2
3
4
5
7
Field
LSTF
LIMSTf
LSTFIP
LGSU
TQSU
LDC
—
Figure 33-22. IMA Link Transmit State (ILTSTATE)
Table 33-17 describes the ILTSTATE bit fields.
Table 33-17. ILTSTATE Field Descriptions
Bits
Name
LSTF
Description
0
1
2
3
Link stuff flag. Microcode-managed parameter. Indicates that the next ICP cell on this link will
be part of a stuff event. Initialize to zero at link startup.
LIMSTF
LSTFIP
LGSU
Link imminent stuff flag. Microcode-managed parameter. Indicates that an upcoming stuff
event will be signalled in the next ICP of this link (via LSI=001). Initialize to zero at link startup.
Link stuff-in-progress flag. Microcode-managed parameter. Indicates that the next cell on this
link will be the second cell of a stuff event. Initialize to zero at link startup.
Link/group startup flag. Microcode-managed parameter. Will be set by the microcode after the
link’s transmit queue has reached target average depth of 3 cells. While this bit is cleared, the
link will transmit only filler cells. Initialize to zero at link startup.
4
5
TQSU
LDC
—
Transmit queue startup flag. Microcode-managed parameter. Will be set by the microcode after
the first cell has been sent to the transmit queue. Initialize to zero at link startup.
Link Due Cell - Link is due cell from round robin distribution. Microcode managed parameter
initialize to 0. Used for optional TRL Service Latency enhancement only.
6-7
Reserved, initialize to zero.
33.4.5.1.3
IMA Transmit Interrupt Status (ITINTSTAT)
0
3
4
5
6
7
Field
—
PTQO
TQO
PTQU
TQU
Figure 33-23. IMA Transmit Interrupt Status (ITINTSTAT)
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Inverse Multiplexing for ATM (IMA)
Table 33-18. ITINTSTAT Field Descriptions
Bits
0-3
Name
Description
—
Reserved, initialize to zero.
4
PTQO
Persistent transmit queue overflow. Set when a transmit queue overflow occurs for two cells in
a row. Further transmit queue overflow events are masked when this bit is set, in order to avoid
a ’flood’ of interrupts. This bit can be used to distinguish a temporary overflow condition (which
could be caused by a rate differential between the TRL and non-TRL link which was out of
compensatable range), or a persistent overflow condition (which could be caused by a more
permanent condition, such as a failure of this link’s PHY device).
Initialize to zero at link startup.
5
6
TQO
Transmit queue overflow. Set when a transmit queue overflow occurs; cleared when a cell is
successfully transmitted. As this bit is set or cleared on a cell-by-cell basis, it may no longer be
set when software reads it if the overflow condition was only temporary. PTQO should be used
instead to distinguish between persistent or temporary underrun conditions.
PTQU
Persistent transmit queue underrun. Set when a transmit queue underrun occurs for two cells
in a row. Further transmit queue underrun events are masked when this bit is set, in order to
avoid a ’flood’ of interrupts. This bit can be used to distinguish a temporary underrun condition
(which could be caused by a rate differential between the TRL and non-TRL link which was out
of compensatable range), or a persistent underrun condition (which could be caused by a more
permanent condition, such as a TRL failure).
Initialize to zero at link startup.
7
TQU
Transmit queue underrun. Set when a transmit queue underrun occurs; cleared when a cell is
successfully transmitted. As this bit is set or cleared on a cell-by-cell basis, it may no longer be
set when software reads it if the underrun condition was only temporary. PTQU should be used
instead to distinguish between persistent or temporary underrun conditions.
Initialize to zero at link startup.
33.4.5.2 IMA Link Receive Table Entry
1
Table 33-19. IMA Link Receive Table Entry
Offset
0x00
Name
ILRCNTL
Width
Description
IMA link receive control parameters.
Hword
Hword
0x02
ILRSTATE
IMA link receive state. Microcode-managed parameter. Initialize to
0x0040 at link startup.
0x04
ILID
Byte
IMA link ID. Formatted per the Cell ID and Link ID field of an ICP cell.
Bit 0: 1 (indicating ICP cell)
Bits 1-2: Program to zero
Bits 3-7: Program to validated LID for this link
[Note: This value is only used by microcode to validate incoming ICP
cells for this link, it is not used to determine round-robin transmission
order. That function is performed by the group order table.]
0x05
0x06
RMCTR
LRIFSN
Byte
Byte
Receive M counter. Microcode-managed parameter.
Receive IFSN counter. Microcode-managed parameter.
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1
Table 33-19. IMA Link Receive Table Entry (continued)
Offset
0x07
Name
Width
Byte
Description
DFC
Number of frames to discard on a this link until it is caught up with the
other links in this group (long propagation delay). Microcode-managed
parameter.
0x08
0x0A
0x0C
0x0E
DCBSP
Hword
Hword
Hword
Hword
IMA link delay compensation buffer start pointer. This parameter forms
bits 12-27 of the pointer; bits 0-11 are from IMAEXTBASE, and bits
28-31 are zero. Refer to Section 33.4.6.2, “Delay Compensation
Buffers (DCB) for more details.
DCBEP
DCBFP
DCBRP
IMA link delay compensation buffer end pointer. This parameter forms
bits 12-27 of the pointer; bits 0-11 are from IMAEXTBASE, and bits
28-31 are zero. Refer to Section 33.4.6.2, “Delay Compensation
Buffers (DCB) for more details.
IMA link delay compensation buffer fill pointer. Microcode-managed
parameter. This parameter forms bits 12-27 of the pointer; bits 0-11 are
from IMAEXTBASE, and bits 28-31 are zero.
Initialize to DCBSP at link startup.
IMA link delay compensation buffer read pointer. Only used during
group delay synchronization and link addition. Microcode-managed
parameter. This parameter forms bits 12-27 of the pointer; bits 0-11 are
from IMAEXTBASE, and bits 28-31 are zero.
0x10
0x12
RICPCH
Hword
Byte
Receive ICP channel number. ATM receive channel number to which
received ICP cells are sent.
IRINTMSK
IMA receive interrupt mask. Has the same format as the IMA interrupt
queue entry.; however, only receive-related bits are relevant. Setting a
bit enables the associated interrupt; clearing a bit masks it.
For group-related events, only the mask register for the TRL is
referenced.
0x13
0x14
LICPOS
Byte
Link ICP offset. Program to the ICP offset validated for this link.
IRSEC
Word
IMA receive stuff event counter. Increments each time a stuff event is
received on this ink. Initialize to zero at link startup.
0x18
0x19
0x1A
0x1C
ANOMALY_CTR
ALPHABETA_CTR
GAMMA_CTR
Byte
Byte
Byte
Word
Anomaly counter. Microcode-managed parameter. Initialize to zero at
link startup.
Alpha/beta counter. Microcode-managed parameter. Initialize to zero at
link startup.
Gamma counter. Microcode-managed parameter. Initialize to zero at
link startup.
DEFECT_CTR
Defect counter. This counter is active while the link is in the
Loss-of-IMA-Frame (LIF) state and is used to ensure IFSD interrupts
are generated for every GAMMA+2 frames. Software can use the
period interrupt issued by this counter in order to determine if the link
is taking too long to synchronize. The DEFECT_CTR is active before
IFSM reaches SYNC. It starts counting from the first cell received and
will count from 0 to (GAMMA+2) x M. When it reaches (GAMMA+2) x M
an IFSD interrupt is generated and the counter is reset. Upon reception
of the next cell it starts to count again and subsequent interrupts are
generated. Microcode managed parameter. Initialize to zero at link
startup.
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1
Boldfaced entries indicate parameters that must be initialized by the user. All other parameters are
managed by the microcode and should be initialized to zero unless otherwise stated.
33.4.5.2.1
IMA Link Receive Control (ILRCNTL)
The fields of the ILRCNTL register are shown in Figure 33-24
0
1
2
3
4
5
7
Field
GA
SES
TRL
RXSC
IGNUM
8
9
10
15
Field Add_new MON_ICP
—
Figure 33-24. IMA Link Receive Control (ILRCNTL)
Table 33-20 describes the ILRCNTL bit fields.
Table 33-20. ILRCNTL Field Descriptions
Bits
Name
Description
0
1
2
GA
Group assigned flag. Set by software after group parameters have been validated.
0 Group unassigned.
1 Group assigned.
SES
Severely errored seconds. Set by software when a severely errored second indication is
detected. When set, causes the receive stuff event counter and ICP violation counter to stop
counting.
TRL
Identifies this link in the group as the Timing Reference Link (NOTE: Only one link per group
can be selected as the TRL).
3-4
RXSC
Receive status/control. Sets the receive mode of the IMA link.
00 Filler mode. The IMA link processes only ICP cells. Data cells are replaced with filler cells.
01 Active mode. The IMA link is capable of receiving data cells.
10 Dropped. Must be set by the user during the process of dropping the link. Dropped links are
treated filler mode until they are switched out of the receive round-robin (i.e. data cells are
replaced with filler cells).
11 Reserved.
5-7
8
IGNUM
Determines to which IMA group this link belongs. Contains the number of the link’s associated
IMA Group Table entry.
Note: This value need not be the same as the group’s IMA ID; the IMA ID is programmed
separately in the receive group’s RIMAID field.
ADD_NEW Identifies this link as a new/added link to a group. Software must flip (0 to 1 or 1 to 0) this bit
ONLY when adding a link to an existing group that is operational. If ADD_NEW =
ILRSTATE[ADD_NEW_M] = 0, set ADD_NEW to 1 to indicate this is an added link. If
ADD_NEW = ILRSTATE[ADD_NEW_M] = 1, set ADD_NEW to 0 to indicate this is an added
link. Initialize to zero.
9
MON_ICP
Setting this bit will allow changed ICP cells received on this link to be passed on to the ATM
layer (defined channel). The user must monitor at least one link in order for ICP cells to be
passed on to the ATM layer.
10 - 15 —
Reserved, initialize to zero.
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Inverse Multiplexing for ATM (IMA)
33.4.5.2.2
IMA Link Receive State (ILRSTATE)
0
1
9
2
3
4
5
6
7
Field ADD_NEW_M
IFSS
MASK_ERR
STFEX
SU
CHK_NXT DATA_ERR
8
10
11
12
13
14
15
Field
icp_cell
FSES
SYNC_DeFeCT
STFIP
DL
—
Figure 33-25. IMA Link Receive State (ILRSTATE)
Table 33-21. ILRSTATE Field Descriptions
Bits
Name
Description
0
ADD_NEW_M
New Link shadow bit. Microcode managed parameter. Initialize to zero at link startup.
1
1-2
IFSS
IMA frame synchronization state. Microcode-managed parameter. Initialize to zero at
link startup.
00 IMA hunt.
01 IMA presync.
1x IMA sync.
3
4
5
6
7
MASK_ERR
STFEX
Mask Error. Microcode managed parameter. Initialize to zero at link startup.
Stuff cell expected. Microcode-managed parameter. Initialize to zero at link startup.
Start Up. Microcode-managed parameter. Initialize to zero at link startup.
Check Next. Microcode-managed parameter. Initialize to zero at link startup.
SU
CHK_NXT
DATA_ERR
Data Error - Parity/CRC. Microcode-managed parameter. Initialize to zero at link
startup.
8
ICP_CELL
Current Cell is an ICP Cell. Microcode-managed parameter. Initialize to zero at link
startup.
1
9-10
FSES
Frame Synchronization Error State. Microcode-managed parameter. Initialize to 10 at
link startup.
00 IMA working.
01 Out-of-IMA frame anomaly.
1x Loss-of-IMA frame defect.
11
SYNC_DEFECT Synchronization Defect. Microcode-managed parameter. Initialize to zero at link
startup.
12
STFIP
DL
Stuff In-Progress flag. Microcode-managed parameter. Initialize to zero at link startup.
Dropped link. Microcode-managed parameter. Initialize to zero at link startup.
Reserved, initialize to zero.
13
14-15
—
1
Enable these parameters to their default values during IMA initialization to avoid spurious IMA exceptions in the IMA interrupt
queues.
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Inverse Multiplexing for ATM (IMA)
33.4.5.3 IMA Link Receive Statistics Table
The IMA link receive statistics table is optional. It is enabled globally for this FCC via IMACNTL[IRSE].
The base of this table is determined by IRLINKSTAT. Entries in the table are indexed by the link number
of the associated link. The format for the IMA link receive statistic table entries is shown in Table 33-22
Table 33-22. IMA Link Receive Statistics Table Entry
Offset
0x00
Name
ICPVIOL
Width
Word
Description
IMA receive ICP violation event counter. While ILRCNTL[SES]=0,
increments each time an errored, invalid, or missing ICP cell is received
on this link. Initialize to zero at link startup.
0x04
OIF
Word
Out-of-IMA frame counter. While ILRCNTL[SES]=0, increments each
time an Out-of-IMA Frame anomaly occurs on this link. Initialize to zero
at link startup.
33.4.6 Structures in External Memory
The IMA microcode requires supporting queue structures in external memory. These are used for the jitter
buffers (on transmission) and the delay compensation buffers (on reception). These structures reside in a
1 megabyte memory region defined by IMAEXTBASE, and may reside on either the 60x bus or the local
bus, as defined by IMACNTL[DSB].
33.4.6.1 Transmit Queues
Transmit queues are allocated on a per-link basis. They are circular queues of 64-byte buffers, defined by
their start and end pointers. For the transmit queue of the timing reference link (TRL), the queue must
consist of a minimum of four buffers (although it may consist of five buffers, if consistency of data
structures is desired). For the transmit queues of non-TRL links, the queues must consist of five buffers.
Queue fill and extract pointers must be initialized by software to the start of the queue; thereafter, these
pointers are managed by the microcode. The queue pointers must be on a 64-byte aligned boundary.
IMA External Structure Region
IMAEXTBASE
bits 0-11
bits 12-27
ITQSP
bits 28-31
0000
64-byte boundary
Transmit
Queue
IMAEXTBASE
ITQSP + TQ_SIZE - 4
IMAEXTBASE
ITQEP
0000
Figure 33-26. IMA Transmit Queue
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33.4.6.2 Delay Compensation Buffers (DCB)
Cells received on a link are initially stored in a delay compensation buffer (DCB). DCBs are allocated on
a per-link basis. They are of user-definable length, thereby providing a programmable maximum
synchronizable delay. Note that DCBs of links within a group must all have the same size.
DCBs consist of a circular queue of 64-byte cell buffers. These cell buffers contain the received cell
followed by 12 bytes of header/status information.
52 bytes RX CELL
64 bytes
12 bytes HEADER/STATUS
Figure 33-27. Cell Buffer in Delay Compensation Buffer
The length of a DCB is defined by the link’s DCBSP and DCBEP parameters. The length of the DCB
(defined by (DCBEP-DCBSP) x 16) must be an integer multiple of the IMA frame length in bytes, M x 64.
Furthermore, the DCBSP must be aligned on a M x 64-byte boundary. For example, if M = 64, then DCBSP
must be on a 4KB boundary. To ensure group delay synchronization, the minimum length of the DCB
should be 2(Mx64).
The DCB memory area must be initialized to zero at link startup.
IMA External Structure Region
IMAEXTBASE
bits 0-11
bits12-27
DCBSP
bits 28-31
0000
M x 64-byte boundary
DCB
IMAEXTBASE
(DCBEP - DCBSP) x 16
IMAEXTBASE
DCBEP
0000
Figure 33-28. IMA Delay Compensation Buffer
33.4.7 IMA Exceptions
One of the four ATM interrupt queues must be dedicated to IMA events. This enables minimum latency
in dealing with the IMA state machines, and ensures that the unique format for IMA exceptions are not
confused with other exceptions. The IMA interrupt queue is defined in the IMACNTL[INTQ] parameter.
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Inverse Multiplexing for ATM (IMA)
IMA events sent to this queue include only those described in this section. ICP receive events are treated
as normal receive events, and should therefore go to the interrupt queue allocated for receive events.
33.4.7.1 IMA Interrupt Queue Entry
The format for the IMA interrupt queue entries is shown in Figure 33-29
0
1
2
3
5
6
7
8
9
10
11
12
13
14
15
OFFSET + 0
V
—
W
—
TQU TQO
—
DSL LS DCBO LDS GDS IFSD IFSW
OFFSET + 2 L/G
NUM
Figure 33-29. IMA Interrupt Queue Entry
Table 33-23 describes the IMA interrupt queue entry bit fields.
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Table 33-23. IMA Interrupt Queue Entry Field Descriptions
Offset
Bits Name
Description
Offset + 0 0
V
Valid interrupt entry.
0 This interrupt queue entry is free and can be used by the CP.
1 This interrupt queue entry is valid. The host should read this interrupt and clear this bit.
1
2
—
W
Reserved.
Wrap bit.When set, this is the last interrupt circular table entry. During initialization, the
host must clear all W bits in the table except the last one, which must be set.
3–4
—
—
Reserved
Reserved
5
6
TQU Transmit queue underrun. Indicates that the corresponding PHY for this link requested a
cell for transmission, but the transmit queue was empty.
7
TQO Transmit queue overflow. Indicates that the TRL attempted to send a cell to this link’s
transmit queue, but no space was available.
8
9
—
Reserved
DSL
DCB synchronization lost. This interrupt is issued when a link in a group with
IGRSTATE[GDSS] = 11 loses synchronization, and the link enters HUNT state at the
IFSM.
10
LS
Link stalled. A link in the round-robin cell extraction process has excessively stalled and
been deactivated (i.e. switched to filler mode by the microcode).
11
12
13
14
15
DCBO Link out of delay synchronization. Set when the link’s DCB overflows, indicating that delay
synchronization for this link is not possible.
LDS
Link delay synchronized. Set when delay synchronization is achieved for a link that has
been added to an existing group.
GDS Group delay synchronized. Set when a group achieves delay synchronization as part of
the group startup procedure.
IFSD IMA frame synchronization status = defect. Set when the associated link goes into the
Loss of IMA Frame Defect state of the Error/Maintenance State Machine.
IFSW IMA frame synchronization status = working. Set when the associated link goes into the
IMA Working state of the Error/Maintenance State Machine.
Offset + 2 0
L/G
Link/group indicator. Indicates whether this interrupt is associated with a link or a group,
and thus if the NUM field is a link number or group number.
0 This interrupt is associated with a link.
1 This interrupt is associated with a group.
1–15 NUM Link or group number associated with this interrupt.
33.4.7.2 ICP Cell Reception Exceptions
ICP cells are received as AAL0 in the channel defined in RICPCH. Receive interrupts are provided for this
channel if enabled in its associated RCT.
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Inverse Multiplexing for ATM (IMA)
33.4.8 IDCR Timer Programming
Programming of the IDCR timer data structures is optional. It is only required if any of the IMA groups
use IDCR-regulated cell processing.
Only one IDCR master clock per FCC is supported; the IDCR timers for the individual groups are derived
from the IDCR master clock. Each IDCR timer has an associated IDCR table entry, indexed by the IMA
group number.
33.4.8.1 IDCR Master Clock
The signal normally used for DMA request for a selected IDMA channel is instead used to provide the
clock signal for the IDCR master clock. This signal must be provided on the external DREQx signal, either
by using an external clock source or by externally connecting one of the baud rate generator (BRG) outputs
to the signal.
The IDCR master clock is enabled by configuring the DREQx pin and supplying the external clock signal.
The IDCR master clock is disabled by either (1) turning the clock signal off, or (2) changing the
configuration of DREQx to be an alternate function or general-purpose I/O. The IDCR_Init command
must be issued before enabling the IDCR master clock.
A higher IDCR master clock frequency provides greater resolution in determining and reconstructing the
IDCR. However, an IDCR master clock frequency that is too high will consume too much CPM processing
power and will hinder the function of the PowerQUICC II. Therefore, the period of the IDCR master clock
should be no less than (number of IMA receive groups) x (500 CPM clocks).
The DONEx and DACKx signals of the IDMA channel are not used. Their I/O ports must be programmed
to an alternate function or to general-purpose I/O.
RCCR[DRxM] should be programmed to edge-sensitive for the DREQx signal functioning as the IDCR
master clock.
33.4.8.2 IDCR FCC Parameter Shadow
The FCC parameters (including IMAROOT) for the FCC associated with the IDCR master clock must be
copied onto the parameter RAM page for that IDCR master clock. For example, if DREQ1 serves as the
IDCR master clock signal for FCC2, then the FCC parameters for FCC2 (at offset 0x8500) must be copied
to parameter page 8 (at offset 0x8700).
33.4.8.2.1
PowerQUICC II Features Unavailable if IDCR is Used
Since their parameter RAM space is used as FCC parameter shadow space, other PowerQUICC II features
associated with this parameter RAM space will not be available. Selection of the IDCR clock signal must
be made with this in mind.
Table summarizes the PowerQUICC II features that share IDMA parameter space which will not be
available if DREQx is used as IDCR master clock,
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Table 33-24. Unavailable Features when DREQx used as IDCR Master Clock
IDCR Master Clock DPRAM Page
PowerQUICC II Features Not Available
MCC1, SMC1, and IDMA1 are unavailable.
DREQ1
DREQ2
DREQ3
DREQ4
8
9
MCC2, SMC2, and IDMA2
SPI and IDMA3
10
11
RISC Timers, Microcode Rev Num, Random Number Generator
function and IDMA4
33.4.8.2.2
Programming the FCC Parameter Shadow
All of the user-defined or user-initialized FCC parameters of the FCC should be copied from the FCC
parameter page to the shadow page. The following parameters are exceptions:
•
RCELL_TMP_BASE of the shadow page must differ from RCELL_TMP_BASE of the FCC
parameter page. This RCELL_TMP_BASE must point to a separate temporary cell storage area
similar to that reserved on the FCC parameter page.
•
Either:
— (1) INTT_BASE of the shadow page must differ from the INTT_BASE of the FCC parameter
page, and along with it separate interrupt parameters and queues.
— OR (2) INTT_BASE of the shadow page and FCC parameter page may be the same and
therefore share common structures, but (a) receive interrupts for the data channels associated
with non-IMA links, data channels associated with non-IDCR IMA links, and ICP channels for
group-unassigned IMA links must be directed to one dedicated interrupt queue, and (b) receive
interrupts for the data channels of group-assigned IMA links using IDCR must be directed to
another dedicated interrupt queue.
•
•
COMM_INFO on the shadow page is unused. ATM commands issued will use the COMM_INFO
fields on the FCC parameter page.
INT_RCT_BASE and EXT_RCT_BASE should be the same for both the shadow page and the
FCC parameter page. However, (a) received data from data channels associated with non-IMA
links, received data from data channels associated with non-IDCR IMA links, and received ICP
cells from group-unassigned IMA links, and (b) received data and ICP cells from group-assigned
IMA links using IDCR must never target the same receive queues. This would not normally be
done anyway; however, if it was done, it would result in erratic operation.
33.4.8.2.3
On-the-Fly Changes of FCC Parameters
In general, the FCC parameters should not require changes when the FCC is operating. In the event that
on-the-fly changes of FCC parameters is performed, those changes should be made one-by-one first in the
parameters of the shadow area, followed by the same change in the FCC parameter area.
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33.4.8.3 IDCR_Init Command
The IDCR_Init command is a host command issued to the CPCR (refer to Section 14.4.1, “CP Command
IDMA master clock. Any of the IDMA channels may be selected for this function.
The format of the command is as follows:
•
•
•
SBC = [per the selected IDMA channel]
OPCODE = 0x00
PAGE = [per the selected IDMA channel]
33.4.8.4 IDCR Root Parameters
The following IDCR parameters are added to the IMA root table only when IDCR is used.
1
Table 33-25. IDCR IMA Root Parameters
Offset
0x60
Name
Width
Description
IDCR_BASE
Hword
IDCR table base. Offset of the IDCR table in DPRAM. Must be 8-byte
aligned.
0x62
0x64
IDCRTICK
Hword
Byte
IDCR global tick counter. Initialize to zero.
IDCREN
IDCR enable array. Each bit (0-7) enables/disables the IDCR timer for
the associated IMA group. Initialize to zero at FCC initialization.
0 The IDCR for the associated group is disabled.
1 The IDCR for the associated group is enabled.
0x65
0x66
IDCR_LAST
Byte
Byte
Group number of last enabled IDCR timer.
IDCR_SVC
IDCR timer currently being serviced. Microcode-managed parameter.
Initialize to zero.
1
Boldfaced entries indicate parameters that must be initialized by the user. All other parameters are
managed by the microcode and should be initialized to zero unless otherwise stated.
33.4.8.5 IDCR Table Entry
A table entry of the format provided below must be provided for any IMA group for which IDCR recovery
is performed. Table entries in the IDCR table are indexed by the group number of the associated group.
The table entry must be initialized before the associated bit is set in IDCREN.
Table 33-26. IDCR Table Entry
Offset
0x00
Name
IDCRCNT
Width
Description
Hword
IDCR count. Holds the count of the IDCR timer for this IMA group.
Decremented once for each IDCR master clock tick.
Initialize to IDCRREQ.
0x02
IDCRCNTF
Hword
IDCR count fraction. Holds the fractional portion of the count of the
IDCR timer for this IMA group.
Initialize to IDCRREQF.
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Table 33-26. IDCR Table Entry
Width Description
Offset
0x04
Name
IDCRREQ
Hword
Hword
IDCR request rate. Program to [TRLR/(RNUMLINKS x 128)] x
(2048/2049).
0x06
IDCRREQF
IDCR request rate fraction. Holds the fractional portion of the IDCR
request rate, represented as (IDCRREQF / 65536).
33.4.8.6 IDCR Counter Algorithm
The IDCR count of each enabled IDCR timer is decremented each tick of the IDCR master clock. When
the IDCRCNT reaches zero, a cell is processed for the associated IMA group, and IDCRCNT and
IDCRCNTF are added with IDCRREQ and IDCRREQF, respectively. When IDCRCNTF overflows, the
’carry’ is added to IDCRCNT, such that the average rate of IDCRCNT timeouts equals the
integer-plus-fraction rate programmed into IDCRREQ and IDCRREQF.
For each tick of the IDCR master clock, the timer table is scanned from entry zero to the entry programmed
in IDCR_LAST. For greatest efficiency, the groups which use IDCR-regulated reception should therefore
be allocated the lowest group numbers, beginning from zero.
33.4.8.7 IDCR Events
For channels running on IMA links with IDCR mode enabled, events are reported and masked in the IDSR
and IDMR registers associated with the IDCR master clock. Furthermore, these events are signalled via
the associated IDMAx bit in the SIPNR_L register. The fields of the IDSR and IDMR registers are shown
in Figure 33-30
Note that INTO1/GRLI and INTO0/GBPB occupy the same bits in the register. Events of either type will
cause this bit to be set. It is therefore recommended that if the global buffer pool feature is used for
channels running on IMA links in IDCR mode, then the user should not use interrupt queues 1 and 0 for
receive or transmit events from these IMA links.
0
1
2
3
4
5
6
7
Field GINT3
GINT2
GINT1
GINT0
INTO3
INTO2
INTO1/GRLI INTO0/GBPB
Figure 33-30. IDMA Event/Mask Registers in IDCR Mode (IDSR/IDMR)
Table 33-27 describes the IDSR/IDMR bit fields.
Table 33-27. IDSR/IDMR Field Descriptions
Bits
Name
Description
0-3
4–5
GINTx
INTOx
Global Interrupt. Set when an event is sent to the corresponding interrupt queue.
Interrupt queue overflow. Set when an overflow condition occurs in the corresponding interrupt
queue. This occurs when the CP attempts to overwrite a valid interrupt entry..
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Inverse Multiplexing for ATM (IMA)
Table 33-27. IDSR/IDMR Field Descriptions (continued)
Bits
Name
INTO1/
Description
6
7
INTO1: Interrupt queue overflow 1. See INTOx above.
GRLI
GRLI: Global red-line interrupt. GRLI is set when a free buffer pool’s RLI flag is set. The RLI
flag is also set in the free buffer pool’s parameter table.
INTO0/
GBPB
INTO0: Interrupt queue overflow 1. See INTOx above.
GBPB: Global buffer pool busy interrupt. GBPB is set when a free buffer pool’s BUSY flag is
set. The BUSY flag is also set in the free buffer pool’s parameter table.
33.4.9 APC Programming for IMA
Dynamically adding and dropping links from a group changes the overall bandwidth of the group. The
bandwidth of a particular ATM channel is programmed as a percentage of the overall bandwidth, up to
100% in the case of APC pace of 1. In the case of IMA, it is desirable to allow for the dynamic addition
and deletion of links without changing the bandwidth of individual ATM channels, so that ATM traffic
contracts will not be violated. To do this without requiring updates of the APC parameters of all of the
ATM channels, the APC algorithm must be modified to consider the number of links in the group.
To accomplish this for channels which will be used with IMA groups, the APC parameters should be
programmed to define the bandwidth of a channel as a percentage of one link of the IMA group. As such,
the APC pace can be greater than 100%, in the case that a channel uses more bandwidth than a single link
can provide. The APC pace will be scaled automatically by the IMA group transmit parameter
TNUMLINKS. After scaling, if the pace required of the group is still greater than 100% of the group
bandwidth, the channel will be rescheduled at 100% of the group bandwidth. Refer to the examples in
Table 33-28. Examples of APC Programming for IMA
Example
Description
1
[The simplest case.] For an IMA group consisting of one 2Mbps link, with one CBR channel consuming the
full bandwidth of that link (i.e. 2Mbps), TNUMLINKS for the group should be programmed to 1 and the APC
pace of the channel should be programmed to 1 (PCR=1, PCR_Fraction=0).
2
3
Another 2Mbps link is added to the IMA group in Example 1. The overall bandwidth of the group is now
4Mbps. However, TNUMLINKS is now 2, and therefore the programmed PCR will be scaled by 2. [Note that
the scaling is done automatically internally; the PCR programmed into the channels transmit connection
table entry is not modified.] A scaled PCR of 2 indicates that the channel uses 50% of the bandwidth of the
group, or 2Mbps. Comparing to example 1 above, we see that the bandwidth of the channel has not
changed, even though the bandwidth of the group has changed.
Consider an IMA group consisting of five 2Mbps links, over which a 6Mbps CBR channel is to be sent.
6Mbps is 300% of what a single 2Mbps link can provide, so its pace should be programmed as 1/3 (PCR=0,
PCR_Fraction=85). Scaling the pace by TNUMLINKS results in 5/3 (PCR=1, PCR_Fraction=169), which
indicates that the channel will use 60% of the bandwidth of the group, or 6Mbps.
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Table 33-28. Examples of APC Programming for IMA
Description
Example
4
Assume that one link is dropped from the IMA group in Example 4. The overall bandwidth of the group is
now 8Mbps, and TNUMLINKS becomes 4. Therefore, the pace for the 6Mbps CBR channel described
above scales to 4/3 (PCR=1, PCR_Fraction=84), indicating that the channel will use 75% of the bandwidth
of the group, which is still 6Mbps.
5
Assume that two links more are dropped from the IMA group in Example 4. The overall bandwidth of the
group is now 4Mbps, and TNUMLINKS becomes 2. Therefore, the pace for the 6Mbps CBR channel
described above scales to 2/3 (PCR=0, PCR_Fraction=170). This is less than 1, which is not possible to
support, so it is rounded up to 1. The channel originally programmed for 6Mbps now consumes 100% of
the 4Mbps IMA group.
Per the above explanation and examples, it is seen that TNUMLINKS is the only parameter which needs
to be modified by software when a link is added or dropped from an IMA group. All other APC parameters
need not be modified. [Note, however, that if links are dropped such that the total scheduled bandwidth of
the ATM channels is greater than 100% of the IMA group bandwidth, this will result eventually in APC
overruns, and should therefore be corrected and/or avoided.
NOTE
Software should ensure that the length of the APC scheduling table is
increased if links are added to the IMA group. When incrementing the
number of links in an IMA group, the user might exceed the length of the
APC scheduling table; if this happens, the ATM channel is mapped outside
of the APC scheduling table and the channel stops.
33.4.9.1 Programming for CBR, UBR, VBR, and UBR+
All APC parameters for CBR, UBR, VBR, and UBR+ channels which will be transmitted over IMA
groups should be scaled by the intended steady-state value of TNUMLINKS. Their values should be
divided by TNUMLINKS, as they will be scaled by TNUMLINKS when the pacing algorithms are
performed. The parameters which must be scaled include: PCR, SCR, OOBR, BT, MCR, and MDA.
33.4.9.2 Programming for ABR
ABR channels are a special case, in that they are not programmed as a percentage of the physical line rate
as inferred from the period of requests from the PHY layer. Instead, the rate of an ABR channel is
programmed as a percentage of an explicitly-provided parameter, the LINE_RATE_ABR, which is
programmed in the APC parameter table for each APC. Therefore, when links are added or dropped from
an IMA group which carries ABR traffic, the parameter LINE_RATE_ABR must also be scaled to reflect
the change in bandwidth of the group. For example, if TNUMLINKS increases from three to four, then
LINE_RATE_ABR must also be multiplied by 4/3.
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Inverse Multiplexing for ATM (IMA)
33.4.10 Changing IMA Version
A new CPCR command has been added to the IMA microcode to change the IMA version on-the-fly
without software intervention. Use the following procedure:
1. Before issuing the command, the user should initialize the COMM_INFO fields in the parameter
m
0
8
9
11
12
15
0x86
0x88
0x8A
—
ITG
—
Filler CRC
—
IV
Figure 33-31. COMM_INFO Field
m
Table 33-29. COMM_INFO Field Descriptions
Offset
Bits
0–8
Name
Description
0x86
—
Reserved, should be cleared.
9–11 ITG
IMA transmit group. Program to the IMA group number [0–7] multiplied by 16 bytes. For
example, if the IMA group number = 3, program ITG to 0x30.
12–15 —
Reserved, should be cleared.
0x88
0x8A
0–15 Filler CRC Filler cell CRC. Set to 0xC602 (for IMA version 1.0) or 0xD902 (for IMA version 1.1)
0–13
—
Reserved, should be cleared.
14–15 IV
IMA version
00 Reserved
01 IMA version 1.0
10 Reserved
11 IMA version 1.1
3. Wait for the CPCR[FLG] to be cleared by the CPM before issuing a new CP command. Refer to
33.5 IMA Software Interface and Requirements
33.5.1 Software Model
The IMA microcode facilitates the implementation of the lower levels of an IMA system. Host software
(from here on, “host software” is code running on the G2 core) is responsible for initializing PowerQUICC
II IMA data structures, establishing and tearing down connections, handling of alarms, keeping statistics,
and controlling protocol state machines. The IMA microcode interfaces to the software-implemented
(Layer Management and Plane Management) functions by providing received ICP cells and by interrupts.
The software-implemented functions control the microcode and the system via the IMA root, group, and
link parameters and by providing an ICP cell template to the microcode for ICP cell transmission.
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Inverse Multiplexing for ATM (IMA)
Tx ICP Template
ICP Cells
Link 1
Interrupts
Layer
Management
IMA Tx
Microcode
Routine
IMA Parameters
Link n
Link 1
Host Software
Plane
Management
Interrupts
IMA Rx
Microcode
Routine
Rx ICP Channel
Link n
ICP Cells
Figure 33-32. IMA Microcode/Software Interaction
33.5.2 Initialization Procedure
1. Program FCC registers/parameters for ATM operation with UTOPIA multi-PHY (excluding APC
parameters for IMA PHYs).
2. Program IMA FCC and root parameters.
3. Enable FCC via GFMRx[ENR,ENT].
Aside from IMA state machine control and IMA-specific error events, subsequent interaction with the
ATM channels is the same as for non-IMA operation (e.g. host commands, RCT/TCT parameters, buffer
descriptors, interrupts).
33.5.3 Software Responsibilities
The following functions are the responsibility of the host software which must complement the IMA
microcode in order to provide a complete IMA solution.
33.5.3.1 System Definition
•
Definition of P(Rx) and P(Tx)—software variables which are used to determine “sufficient links”
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Inverse Multiplexing for ATM (IMA)
33.5.3.2 General Operation
•
React to received ICP cells. ICP cells are only received when their SCCI field changes, except the
first received ICP cell
•
Report any NE and FE timing mode mismatches (ITC vs. CTC) to the Unit Management
33.5.3.3 Receive Link State Machine Control
•
Set up unassigned links, awaiting ICP cells
— Define either as standard multi-PHY or as unassigned IMA link
— Set up receive channel for ICP OAM cells for this link only
Create and initialize delay compensation buffer
Respond to received ICP cells. Extract and validate link/group parameters
— IMA ID
•
•
— Link ID
— Link ICP offset
— IMA frame size (M)
•
•
After establishment of group, change receive channel for ICP OAM cells such that all links in the
group point to the same channel
Control link operation (via ILRCTNL[RXSC]) in coordination with link and group states
33.5.3.4 Receive Group State Machine Control
•
•
Coordinate receive links, using received ICP cells to identify a proposed group
Establish and validate group parameters in conjunction with the received link states and parameters
— IMA version
— IMA ID
— Group order table
•
•
•
Enable delay synchronization for the group, and react to its completion
Control group operation (via IGRCNTL[RXSC]) in coordination with group state
Signal receive group state via ICP cells of corresponding transmit group
33.5.3.5 Transmit Link State Machine Control
•
Define the IMA link
— Define link parameters (e.g. IMA ID, Link ID, IMA frame size (M)) in coordination with IMA
group definition
— Assign ICP offset
— Create and initialize transmit queue
•
Control link operation (via ILTCNTL[TXSC]) in coordination with link and group states
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33.5.3.6 Transmit Group State Machine Control
•
Define the IMA group(s)
— Assign IMA ID
— Assign Link IDs and the transmit group order table
— Assign TRL
— Assign IMA frame size (M)
— Signal group parameters via ICP cells
— Define ATM pace controller (APC) parameters for this transmit group
Signal transmit group state via ICP cells
•
•
•
•
•
Negotiate transmit group parameters with the far end
Check status of links in group to make ‘Sufficient Links’ determination
Control group operation (via IGTCNTL[TXSC]) in coordination with group state
Coordinate link state transitions with group state transitions during group startup and link addition
33.5.3.7 Group Symmetry Control
All types of group symmetry (operation and configuration) are supportable. This is facilitated by the ability
to independently enable/disable links (via RXPHYEN and TXPHYEN) and to control link and group
states (via independent link and group transmit and receive parameters).
33.5.3.8 ICP End-to-End Channel Transmission
•
•
Can send information on end-to-end channel by updating field in Tx ICP.
No Rx support is provided for end-to-end channel.
33.5.3.9 Link Addition and Slow Recovery (LASR) Procedure
Coordinate addition of links for both receive and transmit, including the following:
•
•
•
Establishing their parameters
Checking for defects
On-the-fly insertion into data structures
33.5.3.10 Failure Alarms
•
•
•
•
•
React to errors signalled in received ICP cells
React to physical layer errors
Monitor persistence of errors to determine alarm condition.
Report receive defects within 2M cells of entering defect state
Signal upper-layer software
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33.5.3.11 Test Pattern Control
•
Initiate transmit test patterns in the group’s transmit ICP cells (via TXTC and TXTP), and monitor
response in the receive ICP cells of the associated receive group
•
Respond to test patterns by:
— Recognizing test pattern activity in the received ICP cells
— Locating the Tx Test Pattern field in the ICP cell of the test link. (Because the SCCI field
changes as part of the test pattern generation by the far end, the cell will necessarily be among
the received ICP cells. Locate the latest ICP cell with a LID matching the Tx LID of the test
link).
— Signalling back via the transmit ICP cells of the associated transmit group, by modifying the
transmit ICP cell template appropriately
33.5.3.12 Performance Parameter Measurement and Reporting
•
Establish timers to correlate errors with time intervals (e.g. to determine severely errorred seconds
(SES) or unusable seconds (UUS))
•
•
Maintain statistics
Enable/disable receive and transmit event counters according to severely errorred seconds (SES)
condition via ILRCNTL[SES] and ILTCNTL[SES]
33.5.3.13 SNMP MIBs
Control interface and statistics information should be provided per the SNMP MIB definition for IMA.
33.5.4 IMA Software Procedures
The following procedures must be followed in order to assure the synchronization of changes between the
link state machines and the group state machine. Issues to be considered are order of changes to the ICP
cell and pointer, group order structure and pointer, IMA PHY assignment structure, and group/link Tx
control fields.
33.5.4.1 Transmit ICP Cell Signalling
1. Copy the transmit ICP cell template currently in use (as indicated by TICPPTR) to the ICP cell
template area not in use.
2. In the new template, change the ICP cell template fields as appropriate.
3. Verify that the IGTCNTL[ICPC] equals IGTSTATE[ICPCA]. If not, wait until it does.
4. Change TICPPTR to point to the “changed/altered” (see step 1) ICP cell template.
5. Toggle IGTCNTL[ICPC].
33.5.4.2 Receive Link Start-up Procedure
Before “activation” of links and group can take place, ICP cells must be received and processed by the
management software. Software must configure all IMA links to “group unassigned” mode. Reception
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of ICP cells requires that the corresponding PHYs (i.e., links) have been enabled and the corresponding
connection table entry/entries initialized (see RXPHYEN, IMAPHYEN, and RICPH). In “group
unassigned” mode, the first received ICP cell will always be reported to the corresponding channel’s buffer
(RICPCH) and subsequently every time there is a change in the SCCI (Status and Control Change
Indication) field of the ICP cell.
•
Set ILRCNTL[GA] to 0 (zero).
Setting GA to zero (group unassigned) allows only ICP cells to be processed, all other cells are dropped.
The management software will analyze the ICP cells and program the corresponding IMA Link Receive
Table parameters:
•
•
•
•
•
IMA Link ID (ILID)
Link ICP offset (LICPOS)
Select link as the Timing Reference Link (only one link can be TRL). ILRCNTL[TRL] = 1.
Assign the link to a group. ILRCNTL[IGNUM] = x.
Verify size of frame (M) is the expected value.
The software must have built in knowledge of the mapping between physical links and their corresponding
channel number (e.g., PHY 0 uses channel 2 (RICPH = 2)). Once a group has been established, the user
can have all links in a group report changed ICP cells to a single channel (either by changing RICPCH for
all the links to be the same or by clearing the MON_ICP bit):
•
ILRCNTL[MON_ICP] = 0. Note, at least 1 link in the group must have this bit set.
33.5.4.3 Group Start-up Procedure
The IMA Frame Synchronization Mechanism (IFSM) is initiated when a link is switched to “group
assigned.” However, before that happens, management software must have programmed the group
parameters based upon the received/negotiated values in ICP cells:
•
•
•
IMA ID (RIMAID)
IMA Version (IMAVER)
IMA Frame Size (RM)
There are other parameters that don’t depend on ICP information for programmability. Therefore, it is the
assumption that they have been initialized prior to the start of the IFSM. Start the IFSM by setting each
link in the group to “Group Assigned”:
•
Set ILRCNTL[GA] to 1 (one).
Management software must now wait until each link in the group has achieved IMA frame
synchronization. For each link in the group that was “group assigned” an IFSW (IMA Frame
Synchronization Working) event is generated. See section “IMA Exceptions.”
Having achieved frame synchronization, software can now enable the Group Delay Synchronization
(GDS) mechanism (i.e., finding link with shortest delay and buffering accordingly via DCB).
•
Configure group order table with the ascending link order (round robin distribution) to be used
when reconstructing the ATM stream.
•
Set the corresponding PHY bit in REF_LINK.
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•
Set IGRSTATE[GDSS] to 1 (one) to enable GDS.
Once group delay synchronization is achieved, a “GDS” exception is generated. At this point, ATM stream
reconstruction can take place. In order for stream reconstruction to be performed by the PowerQUICC II,
the user must switch all links and corresponding group (both directions) to “active” mode (i.e., capable of
receiving data cells). Set RX to “active” first, to avoid having the transmitter generate a data stream when
the opposite end is not ready:
•
•
•
•
Set ILRCNTL[RXSC] to 1 (one) to enable reception of data cells at the link level.
Set IGRCNTL[RXSC] to 1 (one) to enable reception of data cells at the group level.
Set ILTCNTL[TXSC] to 1 (one) to enable transmission of data cells at the link level.
Set IGTCNTL[TXSC] to 1 (one) to enable reception of data cells at the group level.
33.5.4.3.1
As Initiator (TX)
Most of the actions required when a system initiates the establishment of a group with X links involves the
exchange of ICP cells between the Near End (Initiator) and the Far End (Responder). In any case, both
ends must start with a group of X potential links configured to “filler mode”. One and only one of the links
in the group must be designated as TRL.
•
•
Set ILTCNTL[TXSC] to 0 (zero)—link is in filler mode.
Set IGTCNTL[TXSC] to 0 (zero)—group is in filler mode.
The actions at both ends mirror each other. That is, the Near End will initiate the establishment of a group
with X links by sending ICP cells to the FE and vise versa. The normal ICP state changes, driven by the
state machine software, are (on a per-link basis):
1. Not In Group
2. Unusable
3. Usable
4. Active
Refer to section “Transmit ICP Cell Signalling” for details on how to modify and transmit an updated ICP
cell.
It is the responsibility of the GSM/LSM (Group/Link State Machine software) to initialize the IMA ID (i.e.
group ID) in the ICP cell template and link ID in the corresponding TX IMA Link Transmit Table Entry
(ILTTE):
•
•
Set ILTTE[ILID] = corresponding Link ID.
Set IMA ID accordingly in the ICP Cell Template.
As an initiator, the NE (“end” is relative) must have established a group with X links provisioned.
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Tx ICP Template
TX
Tx ICP Template
TX
GSM/
LSM
GSM/
LSM
Near-end
PowerQUICC II
Far-end
PowerQUICC II
RX
RX
ICP buffer
ICP buffer
Figure 33-33. Near-End versus Far-End
33.5.4.3.2
As Responder (RX)
The IMA GSM/LSM software will receive ICP cells in the ICP buffer conveying the state of the FE’s
group and links. Once it has determined that the required minimum number of links are available, it can
proceed to enable the “group delay synchronization (GDS)” mechanism in which the all links in the
corresponding group are analyzed to find the one with the shortest propagation delay. The amount of delay
tolerated is programmable and is programmed via the setting of the beginning and ending addresses (size)
of the delay compensation buffers (DCB). Note that the size of all DCBs must be the same and must be
initialized before the GDS mechanism is activated. Activate GDS:
•
Set IGRSTATE[GDSS] to 1 (one) to enable GDS. Once GDS is enabled, the user must not alter
GDSS.
Once group delay synchronization is achieved, a “GDS” exception is generated. At this point, ATM stream
reconstruction can take place. In order for ATM stream reconstruction to be performed by the
PowerQUICC II, the user must switch all links in the group to “active” mode (i.e., capable of receiving
data cells), as specified earlier in this section. The initialization of the ATM TX and RX data structures
required to generate and receive the ATM stream is out of the scope of this document, however, it is
33.5.4.4 Link Addition Procedure
Adding a link to an existing group requires changes to both the group and link table entries. Aside from
the normal exchange of ICP cells by the state machines at the FE and NE, the following steps should be
followed. In general, a new link entry is appended to the existing list of link table entries and the required
parameters initialized. This has no impact until the corresponding link is enabled via the PHYEN fields in
the IMA root table.
33.5.4.4.1
Rx Steps
1. Reset all RX parameters in the new link table entry to zero.
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2. Assign corresponding group number for the new link: ILRCNTL[IGNUM] = x.
3. Assign channel number for ICP cell reception: RICPCH = x.
4. Enable desired interrupts: IRINTMSK = x
5. Allow for the reception of ICP cells during the IFSM stage: ILRCNTL[MON_ICP] = 1.
6. Indicate that this link has not yet been assigned to a group: ILRCNTL[GA] = 0.
7. Configure this link/PHY as an IMA link in the IMA Root Table by setting the corresponding bit in
8. Enable the corresponding link/PHY in the IMA Root Table by setting the corresponding bit in
9. Software receives and accepts ICP cell values (e.g. M, LID, etc.).
10. Program expected LID: ILID = x
11. Program the expected ICP offset: LICPOS = x
12. Initialize the DCB pointers accordingly: DCBEP, DCBSP, DCBFP. Note, it is recommended that
the DCB be initialized to zero.
13. Configure link to “Loss of IMA Frame” state: ILRSTATE[FSES] = 2.
14. Start the IMA Frame Synchronization Mechanism (IFSM) by assigning this link to the group:
ILRCNTL[GA] = 1.
15. Software must now wait for the IFSW (IMA Frame Synchronization Working) event/exception.
16. Now that we have a “frame” synchronized link, we can proceed to allow the link to be “delay”
synchronized. Indicate that this is a new link (GDS/reconstruction function) by inverting the
current “add-new” bit value: ILRCNTL[ADD_NEW] = x.
17. Formulate new group order table with the new link included (see Section 33.4.4.2.4, “Receive
18. Use the new group order table by inverting the current GOTP value: IGRCNTL[GOTP] = x.
19. The “Stall Threshold” needs to be recalculated. This parameter defines the acceptable tolerance to
an emptied DCB condition (stalled link, see LS exception). The recommended new value is:
Table Entry”: IGRTE[STALL_THR] = x.
20. Start the delay compensation process for this link (in IMA Root Table) by setting the corresponding
21. Software must now wait for the link delay synchronization process to complete. A LDS (Link
Delay Synchronized) exception will be generated by the PowerQUICC II as soon as this happens.
22. It is now safe for the link to receive data, set link to “active” mode: ILRCNTL[RXSC] = 1.
33.5.4.4.2
TX Parameters
1. Reset all TX parameters in the new link table entry to zero.
2. Assign corresponding group number for the new link: ILTCNTL[IGNUM] = x.
3. Enable desired interrupts: ITINTMSK = x.
4. Software formats content of ICP template accordingly (see section “Transmit ICP Cell
Signalling”).
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5. Program the Link’s ID (LID) in the IMA Link Transmit Table Entry (ILTTE): ILID = x.
6. Program the ICP offset (ILTTE): LICPOS = x.
7. Initialize the Transmit Queue pointers accordingly: ITQSP, ITQEP, ITQFP, and ITQXP.
8. Construct the new TX Group Order Table (includes the added/new link).
9. Point to new TX Group Order Table in the corresponding IMA Group Transmit Table Entry
(IGTTE): TGRPORDER = New Table Offset.
10. Configure this link/PHY as an IMA link in the IMA Root Table by setting the corresponding bit in
11. Enable the corresponding link/PHY in the IMA Root Table by setting the corresponding bit in
12. Software must now wait for the corresponding FE link to go to “active” state (See
mode”, capable of sending data cells. Prior to this point, only filler and ICP cells were transmitted.
ILTCNTL[TXSC] = 1.
13. Increment the number of links currently in the group (IGTTE): TNUMLINKS += 1.
33.5.4.5 Link Removal Procedure
Removing a link from an existing group requires changes to both the group and link table entries. Aside
from the normal exchange of ICP cells by the state machines at the FE and NE, the following steps should
be followed. In general, a link entry is removed from the existing list of link table entries and the required
parameters initialized. Note that if only one link is used in a group the software must monitor the TC layer
in order to detect that this link has stalled.
33.5.4.5.1
Rx Steps
2. The “Stall Threshold” needs to be recalculated. This parameter defines the acceptable tolerance to
an emptied DCB condition (stalled link; see LS exception). The recommended new value is:
STALL_THR = 2 x RNUMLINKS x (3 + RX_FIFO). See section “IMA Group Receive Table
Entry”: IGRTE[STALL_THR] = x.
3. Inhibit storing of cells in DCB for “dropped” link (in IMA Root Table): REF_LINK &= ~x (i.e.,
clear the corresponding link bit in the REF_LINK entry).
4. Indicate that the link should be dropped: ILRCNTL[RXSC] = 2.
5. Software should wait (poll) for the PowerQUICC II to remove the link from the DCB routine. The
corresponding bit in the group table’s LINK_DCB entry will be cleared by the PowerQUICC II
(IMA) (this means no more cells are being stored in the DCB), e.g.,: while (LINK_DCB !=
REF_LINK).
6. Use the new group order table by inverting the current GOTP value: IGRCNTL[GOTP] = x.
7. Indicate that this link is no longer assigned to a group: ILRCNTL[GA] = 0.
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8. Inhibit reception of cells over dropped link in the IMA Root Table: RXPHYEN &= ~x (i.e., clear
the corresponding link bit in the RXPHYEN entry). Note, you must reenable (set to 1) the
corresponding bit at a later point if you wish to use this link as a non-IMA link.
9. Software should wait (poll) for the PowerQUICC II to be using the new group order table. This
simply ensures that it is safe to modify/re-use the dropped link parameters (i.e., the
PowerQUICC II is no longer using the dropped link’s data structures). Do this by making sure the
group order pointer points to the new group order table (at this point, no more cells are extracted
out of the dropped link’s DCB), e.g.,: while (dcblink != new_pointer). DCBLINK is an entry in
the IGRTE.
10. Indicate that this link is no longer an IMA Link in the IMA Root Table: IMAPHY &= ~x (clear the
bit). Note, in a symmetrical operation, this step should be the last one performed (after both RX
and TX have been disabled). Setting this bit prematurely will halt transmission/reception on the
corresponding link.
33.5.4.5.2
TX Parameters
2. Point to new TX Group Order Table in the corresponding IMA Group Transmit Table Entry
(IGTTE): TGRPORDER = New Table Offset.
3. Decrement the number of links in the group (IGTTE): TNUMLINKS -= 1.
4. Inhibit transmission of cells over dropped link in the IMA Root Table: TXPHYEN &= ~x (i.e.,
clear the corresponding link bit in the TXPHYEN entry). Note, you must reenable (set to 1) the
corresponding bit at a later point if you wish to use this link as a non-IMA link.
5. Indicate that this link is no longer an IMA Link in the IMA Root Table: IMAPHY &= ~x (clear the
bit). Note, in symmetrical operation, this step should be the last one performed (after both RX and
TX have been disabled). Setting this bit prematurely will halt transmission/reception on the
corresponding link.
33.5.4.6 Link Receive Deactivation Procedure
The following procedure assumes that the link was part of the IMA group during the group delay
synchronization procedure and that an IFSW (IMA Frame Synchronization Working) event has already
been received for the link.
2. Decrement RNUMLINKS in the group receive table
3. The “Stall Threshold” needs to be recalculated. This parameter defines the acceptable tolerance to
an emptied DCB condition (stalled link, see LS exception). The recommended new value is:
Table Entry”: IGRTE[STALL_THR] = x.
4. Inhibit storing of cells in DCB for “dropped” link (in IMA Root Table): REF_LINK &= ~x (i.e.,
clear the corresponding link bit in the REF_LINK entry).
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5. Indicate that the link should be dropped: ILRCNTL[RXSC] = 2.
6. Software should wait (poll) for the PowerQUICC II to remove the link from the DCB routine. The
corresponding bit in the group table’s LINK_DCB entry will be cleared by the PowerQUICC II
(IMA) (this means no more cells are being stored in the DCB), e.g.,: while (LINK_DCB !=
REF_LINK).
7. Use the new group order table by inverting the current GOTP value: IGRCNTL[GOTP] = x.
8. Set the link to filler mode ILRCNTL[RXSC] = 0
9. Initialize the DCB pointers accordingly: DCBSP=DCBFP, DCBRP=Null.
10. Initialize link DCB in external memory to zero.
33.5.4.7 Link Receive Reactivation Procedure
The following procedure assumes that the link was part of the IMA group during the group delay
synchronization procedure and that an IFSW(IMA Frame Synchronization Working) event has already
been received for the link.
1. Indicate that this is a new link (GDS/reconstruction function) by inverting the current “add_new”
bit value: ILRCNTL[ADD_NEW] = x.
3. Use the new group order table by inverting the current GOTP value: IGRCNTL[GOTP] = x.
4. Increment RNUMLINKS in the group receive table.
5. The “Stall Threshold” needs to be recalculated. This parameter defines the acceptable tolerance to
an emptied DCB condition (stalled link, see LS exception). The recommended new value is:
6. Start the delay compensation process for this link (in IMA Root Table) by setting the corresponding
7. Software must now wait for the link delay synchronization process to complete. A LDS (Link
Delay Synchronized) exception will be generated by the PowerQUICC II as soon as this happens.
8. It is now safe for the link to receive data, set link to “active” mode: ILRCNTL[RXSC] = 01.
33.5.4.8 TRL On-the-Fly Change Procedure
Timing Reference Link (TRL) requests (CLAV) drive the distribution of cells to the corresponding link
transmit queues. To change the TRL, do the following:
1. Clear TRL bit for the existing TRL: ILTCNTL[TRL] = 0.
2. Set TRL bit for the new TRL: ILTCNTL[TRL] = 1.
Only one link must be selected as “TRL” in a group.
Note, when operating in IDCR mode (RX only), the timer value programmed was based on the TRL Rate
(TRLR) acquired when the group was brought up. It is necessary to restart the entire group if the RX TRL
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33.5.4.9 Transmit Event Response Procedures
The following TX events may take place when operating in IMA mode. It is recommended that all events
be handled via an “exception/interrupt service routine” (ISR) as the response time inherent with interrupt
driven events should diminish the negative impact/propagation of such events:
1. TQU (Transmit Queue Underrun)—Indicates that a transmit queue was emptied. This implies that
the offending link (PHY) is requesting cells at a faster rate relative to the TRL. If the TRL is out of
spec, then you will see multiple links reporting TQUs (because all links in the group will be faster
relative to the TRL). The offending link should be removed (see Section 33.5.4.5, “Link Removal
same), TNUMLINKS is equal (not less or greater) than the number of active links.
2. TQO (Transmit Queue Overflow)—Indicates that a transmit queue was not ready to receive a cell
(full). This implies that the offending link (PHY) is requesting cells at a slower rate relative to the
TRL. If the TRL is out of spec, then you will see multiple links reporting TQOs (because all links
in the group will be slower relative to the TRL). The offending link should be removed (see
should be the same as other queues), TNUMLINKS is equal (not less or greater) than the number
of active links.
33.5.4.10 Receive Event Response Procedures
The following RX events may take place when operating in IMA mode. It is recommended that all events
be handled via an “exception/interrupt service routine” (ISR) as the response time inherent with interrupt
driven events should diminish the negative impact/propagation of such events:
1. LS (Link Stalled)—The link’s DCB has emptied, either because the PHY is no longer functioning
or it is relatively slower than the other links. The offending link should be removed (see
Section 33.5.4.5, “Link Removal Procedure”). Make sure the DCB start and end pointers are not
the same. If only one link is used in a group the software must monitor the TC layer to detect that
this link has stalled. No LS event is reported in the IMA interrupt queue. To re-start an IMA group
properly after link(s) have recovered, the user must reset all the microcode-managed parameters in
the IMA receive group to zero.
2. DCBO (DCB Overflow)—Indicates that the Delay Compensation Buffer has no more space. The
source of the problem can be varied: 1) the offending PHY is sending at a faster rate (out of spec.),
2) the propagation delay of one of the other links in the group is greater than anticipated (need to
make DCB larger) or, 3) the size of the offending link was programmed incorrectly, i.e., smaller
(the size of all DCBs in the group should be the same). The offending link should be removed (see
of Delay Synchronization Defect) and should be reported to the FE (via the ICP cell, RxDefect =
LODS) of the problem. The PowerQUICC II will continue to report this exception if the condition
persists (unless the event is masked).
3. LDS (Link Delay Synchronized)—Indicates that the new/added link (to an existing group) has
achieved synchronization (link delay). The link is capable of receiving data at this point, (see
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4. GDS (Group Delay Synchronized)—Group delay synchronized achieved or group delay
synchronized not achieved. In some cases, it is not possible for the GDS to complete. GDS can not
complete if a link experiences problems during the GDS process - for example losing SYNC state
for the IFSM. If this occurs, it is not possible to determine the links true differential delay with
respect to other member links of the group. In order to determine if the GDS process completed
successfully, the ucode will set IGRSTATE[GDSS] to either of the following values after the GDS
interrupt has been generated:
— IGRSTATE[GDSS] = 00 - GDS process failed, a link lost IFSM SYNC during GDS process
— IGRSTATE[GDSS] = 11 - GDS process completed
Software can then read IGRSTATE[GDSS] and use this status information before deciding whether
to change the links to the active state or to try and resynchronize again at the group level. In
addition to the above status information, the ILRSTATE[ADD_NEW_M] bit of the link that caused
the failure of the GDS process will be flipped such that it is logically inverted with respect to the
ILRCNTL[ADD_NEW] bit. It is recommended however, that software, after GDS failure and
when restarting the GDS process, changes all of the links in the group to the group unassigned state
and then update the link and group parameters to their default values before starting the GDS
process again. Note that a link losing SYNC during the GDS process can cause DCBO interrupt
for other links in the group. If this situation occurs, the GDS process should be restarted as
described above.
5. IFSD (Link (IMA) Frame Synchronization Defect)—Indicates that the link has lost
synchronization (e.g., unexpected IFSN value for a number (GAMMA + 2) of consecutive frames).
If this condition persists, the link should be removed. The threshold that would trigger the removal
of the link is system specific. The IFSD event corresponds to the “Loss of IMA Frame” (LIF) state
and the software should react to this by informing the FE (via the ICP cell, RxDefect = LIF) of the
problem. If the condition persists, IFSD events will continue to be generated every GAMMA+2
frames. The PowerQUICC II maintains counters (if enabled) to track the overall “quality” of a
particular link: see OIF (Out of IMA Frame) and ICPVIOL (ICP Violation) in Section 33.4.5.3,
automatically perform Link Delay Synchronization and generate an LDS event upon achieving
synchronization. The software can use one of the PowerQUICC II timers as a time stamp when
handling IFSD events and check if the “persistence” time threshold has been crossed when
subsequent events take place. The LIF state time stamp should be reset when the IFSW event is
reported.
6. IFSW (Link (IMA) Frame Synchronization Working)—Indicates that the link is has achieved
frame synchronization. This event is reported when a link has been assigned to a group (start-up or
link addition) or it was previously assigned and working, but had a defect (see IFSD event). If
going from defect to working, the software should update the RxDefect field of the ICP. Again, a
time stamp (timer) can be used to measure the “persistence” time.
7. DSL (DCB Synchronisation Lost)—Indicates that a link in a group with IGRSTATE[GDSS] = 11
loses synchronization and enters the HUNT state at the IFSM. When this interrupt occurs, the link
should be removed by software, and the CPM will no longer perform the automatic LASR
procedure. Note that when the interrupt is generated, the ILRSTATE[DL] bit is set, and the
software should clear the IMA group and link receive state information as described above for the
GDS interrupt.
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33.5.4.11 Test Pattern Procedure
Test patterns are used verify “connectivity” of a link in a particular group. The NE will request, via an ICP
cell, that a test pattern be looped back to the FE over all links currently in the group. For this test, the FE
will look only at ICP cells received over the link being tested (LID = x) and upon receiving an ICP cell
“echo” the pattern back to the NE over all the links in the group. The major task of initiating and verifying
the pattern on all the links in the group falls on the software. The PowerQUICC II will simply transmit and
receive the modified/changed ICP cells. If the software detects that the pattern was “echoed” by the FE,
then connectivity is verified.
33.5.4.11.1 As Initiator (NE)
Alter the (unused) ICP cell template to the “Test Link” command to the FE:
1. Tx Test Control = Set to “Active” and select LID (link) to be tested.
2. Tx Pattern = X (0-255).
3. Increment SCCI.
5. Repeat steps 1-4 until expected pattern is received in any of the incoming ICP cells (alternate ICP
templates must be used).
After sending the request to perform the test (pattern) to the FE, the NE software must wait for the TX test
pattern to be echoed back/received in the RX Pattern field of the ICP cell (any of the active links in the
group can be monitored for the RX Pattern). After verifying connectivity, the test can be de-activated (set
Tx Test Control = “Inactive” and repeat steps 3 and 4 above).
33.5.4.11.2 As Responder (FE)
When the FE receives a request to perform the “pattern” test on any of the active links, it must monitor the
selected link (see Tx LID of Tx Test Control) for reception of an ICP cell. Upon receiving an ICP cell
(remember, the other end is incrementing the SCCI field), the software should copy the Tx Pattern to the
Rx Pattern field of the ICP Cell and transmit the ICP cell. Alter the ICP cell:
1. Rx Pattern = Tx Pattern (of received ICP Cell).
2. Increment SCCI
4. Repeat steps 1-3 until the test is inactive.
There are two ways to monitor the link under test. The first method is to simply look for the expected LID
in the received ICP cells (ICP cell buffer). For this to happen, all links in the group must have MON_ICP
bit set:
1. Monitor link for changes in SCCI: ILRCNTL[MON_ICP] = 1.
Now, since changed ICP cells are passed to the ICP buffer only when the SCCI field changes, then it may
take some time for the link under test to pass on an ICP cell. Again, ICP cells will be passed on to the buffer
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Inverse Multiplexing for ATM (IMA)
for the first link encountered in which a change (SCCI) is detected, it may or may not be the link under
test. An alternate method is to monitor only the link under test:
1. Don’t Monitor link for changes in SCCI for all links except link under test: ILRCNTL[MON_ICP]
= 0 (alter the corresponding Link Table Entries).
2. Monitor link under test for changes in SCCI: ILRCNTL[MON_ICP] = 1.
This will allow only changed ICP cells for the link under test to be passed on to the ICP Cell buffer.
33.5.4.12 IDCR Operation
The ATM stream reconstruction (RX) can be driven alternatively by another clock source (as opposed to
triggered by the arrival of cells/CLAV). The reconstruction rate (IMA Data Cell Rate (IDCR)) clock can
be generated by an external clock or by one of the PowerQUICC II’s baud rate generators (BRGs). Note
that the designated Rx TRL is used to record the TRLR (TRL Rate) and this is only captured once, when
a group’s GDS process is initialized. After, GDS is completed, the TRLR cannot be updated (unless the
group is re-initialized.
33.5.4.12.1 IDCR Start-up
There are some basic initialization steps that must be performed before any of the groups are activated and
make use of IDCR stream reconstruction. These steps should only be performed once:
1. Configure the base offset of the IDCR Table in the IMA Root table: IMAROOT[IDCR_BASE] = x.
2. Reset (to zero) the IDCR tick counter: IMAROOT[IDCRTICK] = 0.
3. Reset (to zero) the IDCR in Service field: IMAROOT[IDCR_SVC] = 0.
4. Reset (to zero) the IDCR_EN field: IMAROOT[IDCREN] = 0. Subsequently, any groups
operating in IDCR mode will require that this field be updated (ORed) to enable IDCR mode (e.g.
set bit for the corresponding group).
5. Since we have no active groups, configure IMAROOT[IDCR_LAST] to zero. As additional
groups are created/added, this field must also be modified accordingly with the group number
(groups are numbered 0-7).
6. Copy existing ATM parameter RAM contents to shadow RAM parameter space. For example, if
DREQ1 is used then page 8 (parameter RAM offset 0x8700) must be used as the shadow RAM. If
DREQ2 is used, then page 9 must be used, and so on. Note that the corresponding functionality
previously available and mapped to that page (e.g., MCC1, MCC2, etc.) will no longer be
available.
7. The shadow RAM must use a different address for the RCELL_TMP_BASE. Program a different
8. Program PIO registers: Indicate which pin is being used as the IDCR input (i.e., DREQx). The
port and pin selection is configurable and is driven by what other resources are being used on the
PowerQUICC II (e.g., Port C can be used of DREQ1 or DREQ2).
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Inverse Multiplexing for ATM (IMA)
is supplied by the PowerQUICC II. If an external source is used, this step can be skipped. An
external connection (physical) is required between the output of the BRG (TOUTx) and DREQx
(see step 7 above).
10. Enable IDMAx interrupts (refer to Section 19.8.4, “IDMA Event Register (IDSR) and Mask
11. Clear IDCR table entries (reset to zero).
point, the IDCR mechanism can be used.
33.5.4.12.2 Activating a Group in IDCR Mode
The following steps are required when activating a group in IDCR mode.
1. Configure the corresponding group to operate in IDCR mode: IGRCNTL[IDCR] = 1.
2. Indicate which is the last group that has IDCR enabled. Groups are numbered 0-7. As additional
groups are created/added or removed, this field must also be modified accordingly with the group
number of the last group (in the order of 0-7) that has IDCR enabled. For example, lets say groups
0 and 1 are active and group 2 is being added. Then IMAROOT[IDCR_LAST] = 2.
3. After GDS has been achieved, the software can now read the captured TRLR value (see
IGRTE[TRLR]). At this point, the group’s corresponding IDCR Table Entry can be programmed.
IDCRCNT and IDCRREQ are both initialized to the integer part of: ((TRLR/(num_links x 128)) x
(2048/2049)). IDCRCNTF and IDCRREQF are both initialized to the fraction value of the
previous equation times 65536. For example, lets say ((TRLR/(num_links x 128)) x (2048/2049))
yielded 10.45, then IDCRCNT and IDCRREQ would equal 10. IDCRCNTF and IDCRREQF
would then be set to (.45 x 65536) = 29491 (0x7333).
4. Once the IDCR Table has been programmed, IDCR driven stream reconstruction for this group can
start: IMAROOT[IDCREN] |= x. The corresponding bit must be cleared if this group is being
deactivated/removed from a multi-group configuration.
33.5.4.13 End-to-End Channel Signalling Procedure
33.5.4.13.1 Transmit
The end-to-end channel signalling field can be used by software to signal to the far end. Because the
end-to-end channel is not covered by the SCCI field and there are no standard requirements for the
minimum number of frames between changes of the end-to-end channel field, it is not necessary to follow
the procedure for ICP cell signalling in order to do this; instead, the end-to-end channel field of the ICP
template currently in use can be directly updated. However, if a minimum number of frames between
changes is desired, then the procedure for ICP cell signalling can be used, skipping the step in which the
SCCI is updated.
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Inverse Multiplexing for ATM (IMA)
33.5.4.13.2 Receive
No special facility is included for reception of the end-to-end channel. The end-to-end channel field is part
of the received ICP cells, so its information can be read by software from those cells. However, ICP cells
are only received when the SCCI field changes, so changes in the end-to-end channel will not be received
until the SCCI field also changes (when there is a change in the status and/or control of the far end).
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Chapter 34
ATM Transmission Convergence Layer
NOTE
The functionality described in this chapter is available only on the
MPC8264 and the MPC8266.
The PowerQUICC II can support applications which receive ATM traffic over the standard serial protocols
like E1, T1, and xDSL via its serial interface (SIx TDMx) ports because the ATM TC-layer functionality
is implemented internally. This allows the use of standard low-cost PHY devices in system applications
instead of PHYs that support UTOPIA bus devices.
A typical TC layer application requires the use of one SI TDM channel per TC block. As shown in
connected to a UTOPIA 16-bit MPHY bus which can be routed outside and operated independently of the
TC blocks.
UTOPIA level-2 8-/16-bit bus
FCC1
SIx
UTOPIA level-2 8-bit bus
FCC2
DPR
TDMx
TC
Blocks
FCC3
Figure 34-1. Serial ATM Using FCC2 and TC Blocks (Single Channel)
34.1 Features
Primary features of the TC layer include the following:
•
Eight TDM channels routed in hardware to eight TC layer blocks
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ATM Transmission Convergence Layer
— Protocol-specific overhead bits may be discarded or routed to other controllers by the SI
— Performing ATM TC layer functions (according to ITU-T I.432)
— Transmit (Tx) updates are as follows:
– Cell HEC generation
– Payload scrambling using self synchronizing scrambler (programmable by the user)
– Coset generation (programmable by the user)
– Cell rate by inserting idle cells
— Receive (Rx) updates are as follows:
– Cell delineation using bit by bit HEC checking and programmable ALPHA and DELTA
parameters for the delineation state machine
– Payload descrambling using self synchronizing scrambler (programmable by the user)
– Coset removing (programmable by the user)
– Filtering idle/unassigned cells (programmable by the user)
– Performing HEC error detection and single bit error correction (programmable by the user)
– Generating loss of cell delineation status/interrupt (LOC / LCD)
•
•
•
•
Operates with FCC2 (UTOPIA 8)
Serial loop back mode
Cell echo mode
Supports both FCC transmit modes:
— External rate mode—Idle cells are generated by the FCC (microcode) to control data rate
— Internal rate mode (sub-rate)—FCC transfers only the data cells using the required data rate.
The TC layer generates idle/unassigned cells to maintain the line bit rate
•
Supports the TC layer and PMD (physical medium dependent) WIRE interface (according to the
ATM-Forum af-phy-0063.000)
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ATM Transmission Convergence Layer
•
Cell counters for performance monitoring:
— 16-bit counters count:
– HEC errored cells
– HEC single bit errored and corrected cells
– Idle/unassigned cells filtered
– Idle/unassigned cells transmitted
– Transmitted ATM cells
– Received ATM cells
— Maskable interrupt sent to the host when a counter expires
•
•
Overrun (Rx cell FIFO) and underrun (Tx cell FIFO) condition produces maskable interrupt
May be operated at E1 and DS-1 rates. In addition, xDSL applications at bit rates up to 10 Mbps
are supported.
34.2 Functionality
The TC layer block is shown in Figure 34-2. The transmit and the receive parts are independent; the only
case in which they are synchronized is in cell echo mode.
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ATM Transmission Convergence Layer
60x Bus
PowerQUICC II
Registers
FCC2
Rx
M-PHY
UTOPIA
Rx I/F
Rx Cell
Functions
• cell delineation
• descrambling
• coset
Rx FIFO
Rx Serial I/F
• HEC error
detection and
correction
Rx UTOPIA I/F
(PHY)
Counters
Tx
M-PHY
UTOPIA
Tx I/F
Tx Cell
Functions
Tx FIFO
Tx Serial I/F
• HEC generation
• scrambling
• coset
• rate adaptation
Tx UTOPIA I/F
(PHY)
SI
PHY
one channel
TC Layer
Figure 34-2. TC Layer Block Diagram
34.2.1 Receive ATM Cell Functions
The ATM receive cell functions block (RCF) performs the receive functions of the TC block. It performs
cell delineation, cell payload descrambling, HEC verification and correction, and idle/unassigned cell
filtering.
Cell delineation is the process of framing data to ATM cell boundaries using the header error check (HEC)
received in the ATM cell header. The HEC is a CRC-8 calculation over the first four octets of the ATM
cell header. The cell delineation algorithm assumes that repetitive correct HEC calculations over
consecutive cells indicate valid ATM cell boundaries.
The RCF performs a sequential bit by bit hunt for a correct HEC sequence. While performing this hunt,
the cell delineation state machine is in HUNT state. When a correct HEC is found, the RCF locks on the
particular cell boundary and enters the PRESYNCH state, which indicates that the previously detected
HEC pattern is not a false indication. If a correct HEC pattern is false, an incorrect HEC is received within
the next DELTA cells. If an incorrect cell is detected, then a transition to the HUNT state is made. If an
incorrect HEC is not detected in the PRESYNCH state, a transition to the SYNCH state is made. In the
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ATM Transmission Convergence Layer
SYNCH state, the TC is assumed to be synchronized so that other functions can be applied to the received
cell. A transition back to the HUNT state is made only after ALPHA consecutive incorrect HEC patterns
are detected.
determine the robustness of the delineation method. ALPHA determines the robustness against false
misalignment due to bit errors. DELTA determines the robustness against false delineation in the
synchronization. Both parameters are programmable for each TC block and are provided to help tune the
system according to the line error characteristics of a specific application.
Bit-by-Bit
Correct HEC
HUNT
ALPHA
Consecutive
Incorrect HEC
Incorrect HEC
Cell-by-Cell
PRESYNCH
SYNCH
DELTA Consecutive
Correct HEC
Cell-by-Cell
Figure 34-3. TC Cell Delineation State Machine
The RCF descrambles (programmable) the cell payload using the self-synchronizing descrambler with a
43
polynomial of x + 1.
The HEC calculation is a CRC-8 calculation over the first four octets of the ATM cell header. The RCF
8
2
verifies the received HEC using the accumulation polynomial, x + x + x + 1. The coset polynomial
6
4
2
x + x + x + 1 is added (modulo 2) to the received HEC octet before comparison with the calculated
result (programmable).
The RCF can perform single bit error correction on the header. If multiple bit errors are found in the HEC,
the cell is discarded. If the single bit error correction mode is not enabled (TCMODE[SBC] = 1), the cell
is also discarded when a single bit error is found in the header.
When the cell delineation state machine is in the SYNCH state, the HEC verification state machine
(see Figure 34-4) implements the correction algorithm. This state machine makes sure that a single cell
header is corrected at a time. If consecutive cells are detected with single bit errors in their headers, only
the first cell error is corrected and the rest are discarded. This state machine reduces the probability of the
delivery of cells with errored headers under bursty error conditions.
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ATM Transmission Convergence Layer
Multi-bit error
detected
(Cell discarded)
No error detected
(No action)
No error detected
Error detected
(Cell discarded)
Correction
Mode
Detection
Mode
Single-bit error detected
(correction)
Figure 34-4. HEC: Receiver Modes of Operation
The RCF can also perform idle/unassigned cell filtering. Both features are programmable
(TCMODE[CF]). Cells that are detected to be idle/unassigned are discarded, that is, not forwarded to the
UTOPIA interface Rx FIFO.
34.2.1.1 Receive ATM 2-Cell FIFO
The receive FIFO provides FIFO management and an interface to the UTOPIA receive cell interface. The
receive FIFO can hold two ATM cells, thereby providing the cell rate decoupling function between the
transmission system physical layer and the ATM layer.
FIFO management includes filling the FIFO, indicating to the UTOPIA interface that it contains cells,
maintaining the FIFO read and write pointers, and detecting FIFO overrun (TCER[OR]) conditions.
34.2.2 Transmit ATM Cell Functions
The transmit ATM cell functions block (TCF) performs the ATM cell payload scrambling and is
responsible for the HEC generation and the idle cell generation.
The TCF scrambles (programmable by the user) the cell payload using the self-synchronizing scrambler
43
with polynomial x + 1.
8
2
6
4
2
The HEC is generated using the polynomial x + x + x + 1. The coset polynomial x + x + x + 1 is added
(modulo 2) (programmable by the user) to the calculated HEC octet. The result overwrites the HEC octet
on the transmitted cell. When the transmit FIFO is empty, the TCF inserts idle cells (counted in ICC).
The TCF accumulates the number of transmitted assigned cells in a counter (TCC).
34.2.2.1 Transmit ATM 2-Cell FIFO
The transmit FIFO provides FIFO management and an interface to the UTOPIA transmit interface. The
FIFO provides the cell rate decoupling between the transmission system physical layer and the ATM layer.
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ATM Transmission Convergence Layer
The FIFO management includes emptying cells from the transmit FIFO, indicating to the UTOPIA
interface that it is full, maintaining the FIFO read and write pointers, and detecting FIFO underrun
(TCER[UR]) conditions.
34.2.3 Receive UTOPIA Interface
This block performs the receive interface with the FCC via the UTOPIA bus. It implements the UTOPIA
level-2 (multi-PHY) 8-bit PMD side (slave) interface.
34.2.4 Transmit UTOPIA Interface
This block performs the transmit interface with the FCC via the UTOPIA bus. It implements the UTOPIA
level-2 (multi-PHY) 8-bit PMD side (slave) interface.
34.3 Signals
The TC layer is operated via an SI TDM port using a serial protocol. Synchronization signals are required
for some applications and must be supported. Table 34-1 describes the signals required for operating the
TC layer.
Table 34-1. TC Layer Signals
Signal
Txc
Direction
Description
Input
Output
Input
Input
Input
Input
Tx clock. Clocks Tx data out of the TC to external device.
Tx data from TC to external device.
Txd
Txsyn
Rxc
Tx synch. Synchronizes the transmit data to the beginning of a frame.
Rx clock. Clocks the data into the TC.
Rxd
Rx data. From external device to the TC.
Rxsyn
Rx synch. Synchronizes the received data.
34.4 TC Layer Programming Mode
This section describes the TC layer-specific registers and other programming model features. For a
34.4.1 TC Layer Registers
Each TC layer block is controlled by registers located in the block and accessed from the 60x bus.
34.4.1.1 TC Layer Mode Register [1–8] (TCMODEx)
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ATM Transmission Convergence Layer
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Field RXEN TXEN RPS TPS RC
TC SBC
CF
URE
LB
TBA IMA SM CM
Reset
R/W
0000_0000_0000_0000
R/W
Figure 34-5. TC Layer Mode Register (TCMODEx)
Table 34-2 describes TCMODE fields.
Table 34-2. TCMODEx Field Descriptions
Bits
Name
RXEN
Description
0
1
2
3
4
5
6
TC Layer Rx enable bit. Enables the TC Layer Rx block operation:
0 TC Layer Rx operation is disabled.
1 TC Layer Rx operation is enabled.
TXEN
RPS
TPS
RC
TC Layer Tx enable bit. Enables the TC Layer Tx block operation:
0 TC Layer Tx operation is disabled.
1 TC Layer Tx operation is enabled.
Rx Payload DeScrambling
0 Payload descrambling is performed on received payload data.
1 No payload descrambling is performed on received payload data.
Tx Payload Scrambling
0 Payload scrambling is performed on transmitted payload data.
1 No payload scrambling is performed on transmitted payload data.
Rx Coset Enable
0 XOR with 0xAA is done on received HEC.
1 No XOR with 0xAA is done on received HEC.
TC
Tx Coset Enable
0 XOR with 0xAA is done on transmitted HEC.
1 No XOR with 0xAA is done on transmitted HEC.
SBC
CF
Header Single Bit error Correction
0 Perform single bit error correction on the header according to HEC while in Synch mode.
1 Do not perform single bit error correction on the header.
7–8
Rx Idle/Unassigned Cells Filtering
00 No cell filtering is done on Rx cells.
01 Idle cell filtering is done - idle cells are discarded.
10 Unassigned cell filtering is done - unassigned cells are discarded.
11 Idle and unassigned cell filtering is done - both idle and unassigned cells are discarded.
The Header of idle cell (ITU-T I.361): b00000000_00000000_00000000_00000001
The Header of unassigned cell (ITU-T I.361): b00000000_00000000_00000000_0000xxx0
Note that physical layer cells bypass the TC layer; they are not filtered. Also note that the filter
works on the header only and ignores the HEC.
9
URE
Underrun interrupt (TCER[UR]) enable. Underrun interrupt may be set when Idle cell is
generated by the TC.
0 Underrun interrupt disabled.
1 Underrun interrupt enabled.
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Table 34-2. TCMODEx Field Descriptions (continued)
Description
Bits
Name
LB
10–11
Loopback/echo modes
00 Normal operation.
01 Cell echo mode operation. Received cells are transmitted and do not go out to the UTOPIA
bus.
10 Data loopback mode operation. Transmit data stream is connected to the receive data
stream.
11 Not used.
Note that for echo mode operation, TCMODE[SM] should be cleared, independent of the FCC
multi-PHY mode configuration.
12
13
14
15
TBA
IMA
SM
Tx Byte align
0 Tx data is transferred as soon as it is enabled.
1 Tx data is transferred byte aligned to the Txsyn signal.
IMA mode
0 Rx is not in IMA.
1 Rx is in IMA mode.
Single mode
0 TC is not the only PHY on UTOPIA
1 TC is the only PHY on UTOPIA
CM
Cell counters mode
0 Reading a cell counter clears the counter.
1 Reading a cell counter does not change the counter’s value.
34.4.1.2 Cell Delineation State Machine Register [1–8] (CDSMRx)
DELTA parameters of the cell delineation state machine.
0
4
5
9
10
15
Field
Reset
R/W
ALPHA
DELTA
—
0000_0000_0000_0000
R/W
Figure 34-6. Cell Delineation State Machine Register (CDSMRx)
Table 34-3 describes CDSMR fields.
Table 34-3. CDSMRx Field Descriptions
Bits
0-4
Name
Description
ALPHA
ALPHA consecutive received cells with incorrect HEC are counted by the cell delineation state
machine to pass from state SYNCH to state HUNT.
5-9
DELTA
—
DELTA consecutive received cells with correct HEC are counted by the cell delineation state
machine to pass from state PRESYNCH to state SYNCH.
10–15
Reserved
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ATM Transmission Convergence Layer
34.4.1.3 TC Layer Event Register [1–8] (TCERx)
The TC layer event registers (TCERx), as shown in Figure 34-7, records error events for each TC block.
TCER event bits are cleared by writing ones to them.
0
1
2
3
4
5
9
10
11
12
13
14
15
Field OR
UR CDT MS PARE
—
ROF TOF EOF COF IOF FOF
Reset
R/W
0000_0000_0000_0000
R/W
Figure 34-7. TC Layer Event Register (TCERx)
Table 34-4. TCERx Field Descriptions
Bits
Name
OR
Description
0
1
Overrun. Rx FIFO OverFlow.
Set when Rx FIFO is full and another complete cell is received. The cell is discarded.
UR
Underrun. No ATM cell to transmit.
Set when the Tx FIFO is empty and the transmission of a cell is completed. An idle cell
is sent.
This interrupt is enabled only if TCMODE[URE] is set.
The idle cell header is: 0x00000001 (I.432), whose HEC is: 0x52
The idle cell payload is:0x6A (I.432).
2
3
4
CDT
MS
Cell delineation toggled.
Set when the cell delineation bit (CD) in TCGSR has changed.
Misplaced Txsyn signal
Set when Txsyn is out of place. (The first Txsyn is by definition always in place.)
PARE
Parity event
Set when parity from UTOPIA to transmit is wrong.
5-9
10
—
Reserved
ROF
Received cell counter overflow
Set when the received cells counter passes its maximum value.
11
12
13
14
15
TOF
EOF
COF
IOF
Transmitted cell counter overflow
Set when the transmitted cells counter passes its maximum value.
Errored cells counter overflow
Set when the errored cells counter passes its maximum value.
Corrected cells counter overflow
Set when the corrected cells counter passes its maximum value.
Tx Idle cells counter overflow
Set when the Tx idle cells counter passes its maximum value.
FOF
Filtered cells counter overflow
Set when the filtered cells counter passes its maximum value.
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ATM Transmission Convergence Layer
34.4.1.4 TC Layer Mask Register (TCMRx)
This register’s field description is identical to that of TCER (refer to Section 34.4.1.3, “TC Layer Event
Register [1–8] (TCERx)”). Each bit that is set in TCMR enables an interrupt when the corresponding bit
in TCER is set.
34.4.2 TC Layer General Registers
The TC layer general registers are registers that are distributed to all of the TC blocks. Each TC block is
represented by specific bits. When accessing a general register each TC block is responsible for its specific
bits only.
34.4.2.1 TC Layer General Event Register (TCGER)
The TC layer general event register (TCGER), as shown in Figure 34-8, summarizes the events for all the
TC blocks. Each bit stands for an ORed event register of a TC block. Once a bit is set, it indicates that one
or more event bits are set in the corresponding TC block event register.
0
1
2
3
4
5
6
7
8
15
Field TC1 TC2 TC3 TC4 TC5 TC6 TC7 TC8
—
Reset
R/W
0000_0000_0000_0000
R/W
Figure 34-8. TC Layer General Event Register (TCGER)
Table 34-5 describes TCGER fields.
Table 34-5. TCGER Field Descriptions
Description
One bit or more is set in TC1 event register.
Bits
Name
0
1
2
3
4
5
6
7
TC1
TC2
TC3
TC4
TC5
TC6
TC7
TC8
One bit or more is set in TC2 event register.
One bit or more is set in TC3 event register.
One bit or more is set in TC4 event register.
One bit or more is set in TC5 event register.
One bit or more is set in TC6 event register.
One bit or more is set in TC7 event register.
One bit or more is set in TC8 event register.
34.4.2.2 TC Layer General Status Register (TCGSR)
Figure 34-9 shows the TC layer general status register (TCGSR), which records the cell delineation and
transmit FIFO status for all TC blocks.
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34-11
ATM Transmission Convergence Layer
0
1
2
3
4
5
6
7
8
15
Field CD1 CD2 CD3 CD4 CD5 CD6 CD7 CD8
—
Reset
R/W
0000_0000_0000_0000
R
Figure 34-9. TC Layer General Status Register (TCGSR)
Table 34-6 describes TCGSR fields.
f
Table 34-6. TCGSR Field Descriptions
Bits
Name
CDx
Description
0–7
Cell Delineation. The cell delineation state machine status of TCx.
0 Cell delineation state machine is in Hunt or Pre-Synch modes.
1 Cell delineation machine is in Synch mode.
8–15
—
Reserved
34.4.3 TC Layer Cell Counters
Each TC block maintains six memory-mapped 16-bit performance cell counters that are updated during
operation and can be read by the host. If a counter overflows, it wraps back to zero and generates a
maskable interrupt. These counters are automatically cleared when read if TCMODE[CM] = 0; see
34.4.3.1 Received Cell Counter [1–8] (TC_RCCx)
This cell counter is updated whenever a received cell without HEC errors is passed to the Rx UTOPIA
FIFO.
34.4.3.2 Transmitted Cell Counter [1–8] (TC_TCCx)
This cell counter is updated whenever the transmission of a cell is completed.
34.4.3.3 Errored Cell Counter [1–8] (TC_ECCx)
This cell counter is updated whenever a received errored cell (cell with header error) is discarded.
34.4.3.4 Corrected Cell Counter [1–8] (TC_CCCx)
This cell counter is updated whenever a received cell with a HEC single bit error is corrected. If header
single bit error correction is not enabled (TCMODE[SBC] is set), this counter is not updated. (All errored
cells are counted by the errored cell counter (ECC).)
34.4.3.5 Transmitted IDLE Cell Counter [1–8] (TC_ICCx)
This cell counter is updated whenever an idle cell is transmitted.
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ATM Transmission Convergence Layer
34.4.3.6 Filtered Cell Counter [1–8] (TC_FCCx)
This cell counter is updated whenever an idle/unassigned cell is filtered (discarded). If cell filters are not
enabled (TCMODE[CF] is cleared), this counter is not updated.
34.4.4 Programming FCC2
FCC2 is designed to work with the TC blocks. The TC blocks are located on fixed addresses on the
UTOPIA bus internally. FCC2 should be programmed to work with the TC blocks as if the TC blocks are
external PHYs located on the lowest eight (or fewer) addresses.
34.4.5 Programming and Operating the TC Layer
34.4.5.1 Receive
The TC layer receive operation is enabled by setting TCMODEx[RXEN].
The host software polls the CD bits of each enabled TC layer block to see that its receive cell delineation
state machines are synchronized. For each TC layer block that is synchronized, the host clears
TCERx[CDT]. Once all the enabled TC layer blocks are synchronized, the host terminates its initialization
routine, and the system starts normal operation.
Once a TC block gets out of synchronization, the corresponding TCGSR[CD] is cleared. This change then
causes a TCER[CDT] interrupt to the host (if enabled in the mask register—TCMRx).
On the receive path, the TC layer receives the bit stream via the SI and does the following:
1. Attempts to gain synchronization on the ATM cell boundaries by checking each byte against the
HEC calculated on the preceding 32 bits (ATM cell header candidate).
2. Once synchronized:
— Performs the descrambling function on the cell payload (if enabled)
— Performs the coset function on the HEC (if enabled)
— Checks for HEC errors and corrects single HEC errors when found (again, if enabled). Cells
containing multi-bit header errors (at least 2 errors) are discarded. Idle and unassigned cells are
filtered (discarded) when detected (if the filters are enabled).
Once an ATM cell’s processing is complete, it is passed to the TC layer receive FIFO and the internal TC
layer cell counters are updated. The cell is passed from the TC layer receive FIFO via the internal UTOPIA
interface to the FCC2 receive FIFO.
An overrun condition occurs when the TC layer receive FIFO is full and the FCC is unable to read a cell
from it (via the internal UTOPIA interface) before another valid cell is received. The incoming cell is
discarded and TCER[OR] interrupt is sent to the host (if enabled in the mask register—TCMRx).
34.4.5.2 Transmit
The TC layer transmit operation is enabled by setting TCMODEx[TXEN].
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34-13
ATM Transmission Convergence Layer
The TC layer requests ATM cells for transmission via the internal UTOPIA interface. Then, when the ATM
cell is passed to the TC layer transmit block, it is stored in the TC layer transmit FIFO. When the ATM cell
is to be transmitted, it is read and processed from the TC layer transmit FIFO.
The scrambling function is performed on the ATM cell payload if TCMODEx[TPS] = 1. The ATM cell
header HEC value is calculated and the coset function is performed on the HEC if TCMODEx[TC] = 1.
The ATM cell is then sent to the PHY via the SI. Once ATM cell transmission is complete, the relevant TC
layer cell counters are updated.
When a TC layer cell counter overflows, an interrupt (TCERx[TOF]) is set (if enabled in the corresponding
TCMRx[TOF]).
The TC layer is responsible for providing the data rate required by the physical medium device (PMD).
On PowerQUICC II there are two ATM transmit modes. Users should refer to Section 30.2.1.5, “Transmit
External Rate and Internal Rate Modes,” for more details. The following text and figures are specific to
TC layer operation.
•
External Rate—In general, the TC would never have its transmit FIFO empty, and thus would not
need to generate idle cells. However, if the CPM is busy and if the transmit FIFO is empty, the TC
layer generates an idle cell and an underrun condition will occur. If TCMODEx[URE] = 1, the
.
PowerQUICC II
Keep FCC FIFO full
Generate Idle Cells
CP
cell_req
2M Serial Rate
2M Cell Rate
UTOPIA
ATM Channels
BTM
TC
PHY
FCC
(External Rate)
DPR
Idle Cell
ATM Cell
Figure 34-10. TC Operation in FCC External Rate Mode
•
Internal Rate (Sub Rate)—The TC layer continues to request ATM cells and transmits idle cells.
TCERx[UR] interrupts can by disabled by clearing TCMODEx[URE] until a valid ATM cell is
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ATM Transmission Convergence Layer
PowerQUICC II
1M Sub Rate
Generate Cell Req
BRG
Write to FIFO
ATM Cells Only
CP
cell req
2M Serial Rate
1M Cell Sub Rate
UTOPIA
ATM Channels
BTM
TC
PHY
FCC
(Internal/Sub Rate)
Generate Idle Cells
DPR
Idle cell
ATM cell
Figure 34-11. TC Operation in FCC Internal Rate Mode (Sub Rate Mode)
Operation in byte-aligned mode (TCMODE[xTBA] = 1) is required for T1/E1 mainly. In this mode, once
the TC is enabled, it waits for the first Txsyn pulse to start transmit the first byte of the first cell. This
ensures that subsequent Txsyn pulses are byte-aligned to the cell boundaries.
34.5 Implementation Example
Figure 34-12 shows the PowerQUICC II connected to two PHY devices, each containing four T1 framers.
The eight T1 bit streams are connected to the eight PowerQUICC II SI TDMs and routed via the SI to the
eight TC layer blocks. The eight TC layer blocks, each with its own address, are connected internally to
FCC2 via the UTOPIA 8-bit bus. Another ATM stream is managed by FCC1 via the UTOPIA 16-bit bus
connected to a SONET 155-Mbps PHY.
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34-15
ATM Transmission Convergence Layer
PowerQUICC II
SONET
UTOPIA 16-bit bus
155 mbps
PHY
FCC1
FCC2
UTOPIA 8-bit bus
DPR
PHY
4*1.5 mbps
SI-1
8*1.5 mbps
TDMa
TDMb
TDMc
TDMd
4 channel
T1
Framer
TDMa
TDMb
TDMc
TDMd
4 channel
T1
Framer
TC
PHY
4*1.5 mbps
SI-2
Figure 34-12. Example of Serial ATM Application
34.5.1 Operating the TC Layer at Higher Frequencies
The operation of the TC layer requires a minimum frequency ratio of 1:2.5 between the serial clock and
the UTOPIA clock (in Rx and Tx separately). Using the TC for serial frequencies greater than 10 MHz
requires using higher UTOPIA frequencies to preserve that ratio.
34.5.2 Programming a T1 Application
This section describes the configurations necessary to implement a T1 application using a single TC layer
block. Note that using two or more TCs requires FCC2 to work in MPHY mode. Assuming that the
required ATM parameters and data structures have been setup and initialized, implementing a T1
application requires the following steps:
1. Program FCC2
2. Setup I/O Ports and Clocks
3. Enable Tx/Rx on FCC2
4. Program CPM MUX
5. Program the TC block
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ATM Transmission Convergence Layer
6. Program the Serial Interface (SI)
7. Enable TDM
Step 1
To setup and initialize FCC2, program the FPSMR and GFMR as shown in Table 14. This is for working
with one TC block operating in a single PHY environment. The transmitter and receiver should not be
enabled at this time. In this example, FCC2 does not discard idle cells.
Table 34-7. Programming GFMR and FPSMR to Setup the FCC2
Init Values
Description
FPSMR2 = 0x0080_0000 UTOPIA Rx and Tx in Master Mode, Idle cells are not discarded
GFMR2 = 0x0000_000A ATM Protocol Mode, Receiver and Transmitter are disabled
Step 2
Because the FCC2 UTOPIA bus is connected internally to the TC UTOPIA bus, program the parallel ports
and BRGs for the active TDM(s).
Step 3
To enable receiving and transmitting, FCC2 should be programmed as shown in Table 15.
Table 34-8. Enable FCC2
Init Values
Description
GFMR2 = 0x0000_003A
Enable Rx and Tx
Step 4
To define the connection of FCC2, the CPM MUX should be programmed as shown in Table 16.
Table 34-9. Programming the CPM MUX for a TI Application
Init Values
Description
CMXFCR = 0x0080_0000
CMXUAR = 0x0000
FCC2 is connected to the TC Layer
FCC2 as UTOPIA master
Step 5
The TCx layer block should be configured using the TCMODEx and CDSMR1 registers as shown in
Table 17. Note that the TC layer must be enabled after both FCC2 and CPM MUX have been programmed.
Table 34-10. Programming the TC Layer Block
Init Values
Description
TCMODE1 = 0xC202
Enable TC Layer Rx and Tx, no error correction on header, the TC is the only PHY on
UTOPIA
CDSMR1 = 0x3980
ALPHA = 7, DELTA = 6 (default values)
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ATM Transmission Convergence Layer
Step 6
Program the SI to retrieve the data bits (192 bits) out of the T1 frame (193 bits). The SI frame pattern is
programmed in the SI RAM (Rx or Tx), as shown in Table 18.
Table 34-11. Programming the SI RAM (Rx or Tx) for a T1 Application
Init Values
Description
SI_RAM[00]=0x0000
SI_RAM[02]=0x015E
SI_RAM[04]=0x015E
SI_RAM[06]=0x015F
1 bit is ignored.
Route 8 bytes to FCC2.
Route 8 bytes to FCC2.
Route 8 bytes to FCC2 and go back to the first entry in table.
Step 7
The last step in this example is to initialize the serial interface registers and enable TDM—in this case
TDMa on SI1 as shown in Table 19.
Table 34-12. Programming SI Registers to Enable TDM
Init Values
Description
Common Receive and Transmit Pins for TDMa
SI1AMR = 0x0040
SI1GMR = 01
Enable TDMa
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Chapter 35
Fast Ethernet Controller
The Ethernet IEEE 802.3 protocol is a widely-used LAN based on the carrier-sense multiple
access/collision detect (CSMA/CD) approach. Because Ethernet and IEEE 802.3 protocols are similar and
can coexist on the same LAN, both are referred to as Ethernet in this manual, unless otherwise noted.
Frame Length is 64–1,518 Bytes
Start Frame Destination
Source
Address
Type/
Length
Frame Check
Sequence
Preamble
7 Bytes
Data
Delimiter
Address
1 Byte
6 Bytes
6 Bytes
2 Bytes
46–1500 Bytes
4 Bytes
Note: The lsb of each octet is transmitted first.
Figure 35-1. Ethernet Frame Structure
The elements of an Ethernet frame are as follows:
•
•
•
•
7-byte preamble of alternating ones and zeros.
Start frame delimiter (SFD)—Signifies the beginning of the frame.
48-bit destination address.
48-bit source address. Original versions of the IEEE 802.3 specification allowed 16-bit addressing,
which has never been used widely.
•
Ethernet type field/IEEE 802.3 length field. The type field signifies the protocol used in the rest of
the frame, such as TCP/IP; the length field specifies the length of the data portion of the frame. For
Ethernet and IEEE 802.3 frames to exist on the same LAN, the length field must be unique from
any type fields used in Ethernet. This requirement limits the length of the data portion of the frame
to 1,500 bytes and, therefore, the total frame length to 1,518 bytes.
•
•
Data
Four-bytes frame-check sequence (FCS), which is the standard, 32-bit CCITT-CRC polynomial
used in many protocols.
When a station needs to transmit, it waits until the LAN becomes silent for a specified period (interframe
gap). When a station starts sending, it continually checks for collisions on the LAN. If a collision is
detected, the station forces a jam signal (all ones) on its frame and stops transmitting. Collisions usually
occur close to the beginning of a frame. The station then waits a random time period (backoff) before
attempting to send again. When the backoff completes, the station waits for silence on the LAN and then
begins retransmission on the LAN. This process is called a retry. If the frame is not successfully sent within
15 retries, an error is indicated.
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35-1
Fast Ethernet Controller
10-Mbps Ethernet basic timing specifications follow:
•
•
•
•
Transmits at 0.8 µs per byte
The preamble plus start frame delimiter is sent in 6.4 µs.
The minimum interframe gap is 9.6 µs.
The slot time is 51.2 µs.
100-Mbps Ethernet basic timing specifications follow:
•
•
•
•
Transmits at 0.08 µs per byte
The preamble plus start frame delimiter is sent in 0.64 µs.
The minimum interframe gap is 0.96 µs.
The slot time is 5.12 µs.
35.1 Fast Ethernet on the PowerQUICC II
When a general FCC mode register (GFMRx[MODE]) selects Ethernet protocol, that FCC performs the
full set of IEEE 802.3/Ethernet CSMA/CD media access control (MAC) and channel interface functions.
Figure 35-2 shows a block diagram of the FCC Ethernet control logic.
60x-Bus
Slot Time
And Defer
Counter
Control
Registers
RX_CLK
TX_CLK
Clock
Generator
Peripheral Bus
Internal Clocks
RX_ER
RX_DV
COL
TX_ER
TX_EN
COL
Receive
Data
FIFO
Transmit
Data
FIFO
Receiver
Control
UNIT
Transmitter
Control
Unit
CRS
CRS
TXD[3–0]
Shifter
Shifter
RXD[3–0]
Figure 35-2. Ethernet Block Diagram
35.2 Features
The following is a list of Fast Ethernet key features:
•
•
Support for Fast Ethernet through the MII (media-independent interface)
Performs MAC (media access control) layer functions of Fast Ethernet and IEEE 802.3x
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Freescale Semiconductor
Fast Ethernet Controller
•
•
Performs framing functions
— Preamble generation and stripping
— Destination address checking
— CRC generation and checking
— Automatic padding of short frames on transmit
— Framing error (dribbling bits) handling
Full collision support
— Enforces the collision (jamming and TX_ER assertion)
— Truncated binary exponential backoff algorithm for random wait
— Two nonaggressive backoff modes
— Automatic frame retransmission (until retry limit is reached)
— Automatic discard of incoming collided frames
— Delay transmission of new frames for specified interframe gap
Bit rates up to 100 Mbps
•
•
•
•
•
Receives back-to-back frames
Detection of receive frames that are too long
Multibuffer data structure
Supports 48-bit addresses in three modes
— Physical. One 48-bit address recognized or 64-bin hash table for physical addresses
— Logical. 64-bin group address hash table plus broadcast address checking
— Promiscuous. Receives all frames regardless of address (a CAM can be used for address
filtering)
•
•
•
External CAM support on system bus interfaces
Special RMON counters for monitoring network statistics
Transmitter network management and diagnostics
— Lost carrier sense
— Underrun
— Number of collisions exceeded the maximum allowed
— Number of retries per frame
— Deferred frame indication
— Late collision
•
Receiver network management and diagnostics
— CRC error indication
— Nonoctet alignment error
— Frame too short
— Frame too long
— Overrun
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Fast Ethernet Controller
— Busy (out of buffers)
Error counters
•
— Discarded frames (out of buffers or overrun occurred)
— CRC errors
— Alignment errors
•
•
•
•
•
Internal and external loopback mode
Supports Fast Ethernet in duplex mode
Supports pause flow control frames
Support of out-of-sequence transmit queue (for flow-control frames)
External buffer descriptors (BDs)
35.3 Connecting the PowerQUICC II to Fast Ethernet
Figure 35-3 shows the basic components of the media-independent interface (MII) and the signals required
to make the Fast Ethernet connection between the PowerQUICC II and a PHY.
Media-Independent Interface (MII)
Transmit Error (TX_ER)
Transmit Nibble Data 0–3 (TXD[0–3])
Transmit Enable (TX_EN)
Transmit Clock (TX_CLK)
Collision Detect (COL)
Receive Nibble Data (RXD[0–3])
Medium
Fast Ethernet
PowerQUICC II
Receive Error (RX_ER)
Receive Clock (RX_CLK)
PHY
Receive Data Valid (RX_DV)
Carrier Sense Output (CRS)
Management Data Clock1 (MDC)
Management Data I/O1 (MDIO)
1
The management signals (MDC and MDIO) can be common to all of the Fast Ethernet connections in
the system, assuming that each PHY has a different management address. Use parallel I/O port pins to
2
implement MDC and MDIO. (The I C controller cannot be used for this function.)
Figure 35-3. Connecting the PowerQUICC II to Ethernet
Each FCC has 18 signals, defined by the IEEE 802.3u standard, for connecting to an Ethernet PHY. The
two management signals (MDC and MDIO) required by the MII should be implemented separately using
the parallel I/O.
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Fast Ethernet Controller
The PowerQUICC II has additional signals for interfacing with an optional external content-addressable
The PowerQUICC II uses the SDMA channels to store every byte received after the start frame delimiter
into system memory. On transmit, the user provides the destination address, source address, type/length
field, and transmit data. To meet minimum frame requirements, PowerQUICC II automatically pads
frames with fewer than 64 bytes in the data field. The PowerQUICC II also appends the FCS to the frame.
35.4 Ethernet Channel Frame Transmission
The Ethernet transmitter requires almost no core intervention. When the core enables the transmitter, the
Ethernet controller polls the first TxBD in the FCC’s TxBD table every 256 serial clocks. If the user has a
frame ready to transmit, setting FTODR[TOD] eliminates waiting for the next poll. When there is a frame
to transmit, the Ethernet controller begins fetching the data from the data buffer and asserts TX_EN. The
preamble sequence, start frame delimiter, and frame information are sent in that order; see Figure 35-1. In
full-duplex mode, because collisions are ignored, frame transmission maintains only the interframe gap 28
serial clocks (112 bit time period) regardless of CRS assertion.
There is one internal buffer for out-of-sequence flow control frames (in full-duplex Fast Ethernet). When
the Fast Ethernet controller is between frames, this buffer is polled if flow control is enabled. This buffer
must contain the whole frame.
However, in half-duplex mode, the controller defers transmission if the line is busy (CRS asserted). Before
transmitting, the controller waits for carrier sense to become inactive, at which point the controller
determines if CRS remains negated for 16 serial clocks. If so, the transmission begins after an additional
8 serial clocks (96 bit-times after CRS originally became negated). In the fast ethernet transmitter, if CRS
is asserted and then negated within 10 clocks after TXEN is negated, the next frame is not deferred and a
defer indication is asserted.
If a collision occurs during the transmit frame, the Ethernet controller follows a specified backoff
procedure and tries to retransmit the frame until the retry limit is reached. The Ethernet controller stores
at least the first 64 bytes of data of the transmit frame in the FCC FIFO, so that the data does not have to
be retrieved from system memory in case of a collision. This improves bus usage and latency if the backoff
timer output requires an immediate retransmission.
When the end of the current buffer is reached and TxBD[L] = 1, the FCS (32-bit CRC) bytes are appended
(if TxBD[TC] = 1), and TX_EN is negated. This notifies the PHY of the need to generate the illegal
Manchester encoding that signifies the end of an Ethernet frame. Following the transmission of the FCS,
the Ethernet controller writes the frame status bits into the BD and clears TxBD[R]. When the end of the
current buffer is reached and TxBD[L] = 0 (a frame is comprised of multiple buffers), only TxBD[R] is
cleared.
For both half- and full-duplex modes, an interrupt can be issued depending on TxBD[I]. The Ethernet
controller then proceeds to the next TxBD in the table. In this way, the core can be interrupted after each
frame, after each buffer, or after a specific buffer is sent. If TxBD[PAD] = 1, the Ethernet controller pads
To rearrange the transmit queue before the CP finishes sending all frames, issue a GRACEFUL STOP
TRANSMIT command. This can be useful for transmitting expedited data ahead of previously linked buffers
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35-5
Fast Ethernet Controller
or for error situations. When the GRACEFUL STOP TRANSMIT command is issued, the Ethernet controller
stops immediately if no transmission is in progress or continues transmission until the current frame either
finishes or terminates with a collision. When the Ethernet controller is given the RESTART TRANSMIT
command, it resumes transmission. The Ethernet controller sends bytes least-significant nibble first.
35.5 Ethernet Channel Frame Reception
The Ethernet receiver is designed to work with almost no core intervention and can perform address
recognition, CRC checking, short frame checking, maximum DMA transfer checking, and maximum
frame-length checking.
When the core enables the Ethernet receiver, it enters hunt mode when RX_DV is asserted as long as COL
remains negated (full-duplex mode ignores COL). In hunt mode, as data is shifted into the receive shift
register four bits at a time, the contents of the register are compared to the contents of the SYN2 field in
the FCC’s data synchronization register (FDSR). When the registers match, the hunt mode is terminated
and character assembly begins.
When the receiver detects the first bytes of a frame, the Ethernet controller performs address recognition
physical (individual), group (multicast), and broadcast addresses. Because Ethernet receive frame data is
not written to memory until the internal address recognition algorithm is complete, bus usage is not wasted
on frames not addressed to this station. The receiver can also operate with an external CAM, in which case
frame reception continues normally, unless the CAM specifically signals the frame to be rejected. See
If an address is recognized, the Ethernet controller fetches the next RxBD and, if it is empty, starts
transferring the incoming frame to the RxBD’s associated data buffer.
In half-duplex mode, if a collision is detected during the frame, the RxBDs associated with this frame are
reused. Thus, no collision frames are presented to the user except late collisions, which indicate serious
LAN problems. When the buffer has been filled, the Ethernet controller clears RxBD[E] and generates an
interrupt if RxBD[I] is set. If the incoming frame is larger than the buffer, the Ethernet controller fetches
the next RxBD in the table; if it is empty, it continues receiving the rest of the frame.
The RxBD length is determined by MRBLR in the parameter RAM. The user should program MRBLR to
be at least 64 bytes. During reception, the Ethernet controller checks for frames that are too short or too
long. When the frame ends, the receive CRC field is checked and written to the data buffer. The data length
written to the last BD in the Ethernet frame is the length of the entire frame, which enables the software to
recognize a frame-too-long condition.
If an external CAM is used (FPSMRx[CAM] = 1), the Ethernet controller adds the two lower bytes of the
CAM output at the end of each frame. Note that the data length does not include these two bytes; that is,
the extra two bytes could push the buffer length past MRBLR.
When the receive frame is complete, the Ethernet controller sets RxBD[L], writes the other frame status
bits into the RxBD, and clears RxBD[E]. The Ethernet controller next generates a maskable interrupt,
indicating that a frame was received and is in memory. The Ethernet controller then waits for a new frame.
The Ethernet controller receives serial data least-significant nibble first.
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Fast Ethernet Controller
35.6 Flow Control
Because collisions cannot occur in full-duplex mode, Fast Ethernet can operate at the maximum rate.
When the rate becomes too fast for a station’s receiver, the station’s transmitter can send flow-control
frames to reduce the rate. Flow-control instructions are transferred by special frames of minimum frame
size. The length/type fields of these frames have a special value. Table 35-1 shows the flow-control frame
structure.
Table 35-1. Flow Control Frame Structure
Size [Octets]
Description
Preamble
Value
Comment
7
1
6
6
2
2
2
SFD
Start frame delimiter
01-80C2-00-00-01 Multicast address reserved for use in MAC frames
Destination address
Source address
Length/type
88-08
00-01
Control frame type
Pause command
MAC opcode
MAC parameter
up to
0xFFFE
Pause period measured in slot times, most-significant
octet first with a two time-slot resolution.
Note: Because the pause period has a resolution of two
time slots, the value programmed in this field is rounded
up to the nearest even number before being used, as
follows:
MAC Parameter ValuePause Period
0
none
1 or 2 2 x slot time
3 or 4 4 x slot time
… …
42
4
Reserved
FCS
—
Frame check sequence (CRC)
When flow-control mode is enabled (FPSMRx[FCE]) and the receiver identifies a pause-flow control
frame sent to individual or broadcast addresses, transmission stops for the time specified in the control
frame. During this pause, only the out-of-sequence frame is sent. Normal transmission resumes after the
pause timer stops counting. If another pause-control frame is received during the pause, the period changes
to the new value received.
35.7 CAM Interface
The PowerQUICC II internal address recognition logic can be used in combination with an external CAM.
The Ethernet controller writes two 32-bit accesses to the CAM and then reads the result in a 32-bit access.
If the high bit of the result is set, the frame is rejected; otherwise, the lower 16 bits are attached to the end
of the frame.
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35-7
Fast Ethernet Controller
When an external CAM is used for address filtering, users can choose to either discard rejected frames
(FPSMR[ECM] = 0) or receive rejected frames and signal the CAM miss in the RxBD (FPSMR[ECM] =
1).
NOTE
The bus atomicity mechanism for CAM accesses may not function correctly
when the CPM performs a DMA access to an external CAM device. This
only impacts systems in which multiple CPMs will access the CAM.
35.8 Ethernet Parameter RAM
Table 35-2. Ethernet-Specific Parameter RAM
1
Offset
Name
Width
Description
0x3C
0x40
STAT_BUF Word Buffer of internal usage
CAM_PTR Word CAM address. For FCC Fast Ethernet operation the CAM should be located on the
same bus as the data buffers.
0x44
0x48
0x4C
C_MASK
C_PRES
Word Constant MASK for CRC (initialize to 0xDEBB_20E3). For the 32-bit CRC-CCITT.
Word Preset CRC (initialize to 0xFFFF_FFFF). For the 32-bit CRC-CCITT.
2
CRCEC
Word CRC error counter. Counts each received frame with a CRC error. Does not count
frames not addressed to the station, frames received in the out-of-buffers condition,
frames with overrun errors, or frames with alignment errors.
2
0x50
0x54
0x58
ALEC
Word Alignment error counter. Counts frames received with dribbling bits. Does not count
frames not addressed to the station, frames received in the out-of-buffers condition, or
frames with overrun errors.
2
DISFC
Word Discard frame counter. Incremented for discarded frames because of an out-of-buffers
condition or overrun error. The CRC need not be correct for this counter to be
incremented.
RET_LIM Hword Retry limit (typically 15 decimal). Number of retries that should be made to send a
frame. If the frame is not sent after this limit is reached, an interrupt can be generated.
0x5A
0x5C
RET_CNT Hword Retry limit counter. Temporary decrementer used to count retries made.
P_PER
Hword Persistence. Allows the Ethernet controller to be less persistent after a collision.
Normally cleared, P_PER can be from 0 to 9 (9 = least persistent). The value is added
to the retry count in the backoff algorithm to reduce the chance of transmission on the
next time-slot. Using a less persistent backoff algorithm increases throughput in a
congested Ethernet LAN by reducing the chance of collisions. FPSMR[SBT] can also
reduce persistence of the Ethernet controller. The Ethernet/802.3 specifications
permit the use of P_PER.
0x5E BOFF_CNT Hword Backoff counter
0x60
0x64
GADDR_H Word Group address filters high and low are used in the hash table function of the group
addressing mode. The user may write zeros to these values after reset and before the
GADDR_L Word
Ethernet channel is enabled to disable all group hash address recognition functions.
The SET GROUP ADDRESS command is used to enable the hash table. See
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Table 35-2. Ethernet-Specific Parameter RAM (continued)
Width Description
1
Offset
Name
0x68
0x6A
0x6C
TFCSTAT Hword Out-of-sequence TxBD. Includes the status/control, data length, and buffer pointer
fields in the same format as a regular TxBD. Useful for sending flow control frames.
This area’s TxBD[R] is always checked between frames, regardless of FPSMRx[FCE].
TFCLEN Hword
If it is not ready, a regular frame is sent. The user must set TxBD[L] when preparing
this BD. If TxBD[I] is set, a TXC event is generated after frame transmission. This area
should be cleared when not in use.
TFCPTR
MFLR
Word
0x70
Hword Maximum frame length register (typically1518 decimal). If the Ethernet controller
detects an incoming frame exceeding MFLR, it sets RxBD[LG] (frame too long) in the
last RxBD, but does not discard the rest of the frame. The controller also reports the
frame status and length of the received frame in the last RxBD. MFLR includes all
in-frame bytes between the start frame delimiter and the end of the frame.
0x72 PADDR1_H Hword The 48-bit individual address of this station. PADDR1_L is the lowest order half-word,
and PADDR1_H is the highest order half-word.
0x74
PADDR1_ Hword
M
0x76
0x78
0x7A
PADDR1_L Hword
IBD_CNT Hword Internal BD counter
IBD_STAR Hword Internal BD start pointer
T
0x7C
0x7E
0x80
IBD_END Hword Internal BD end pointer
TX_LEN
Hword Tx frame length counter
IBD_BASE
32
Internal microcode usage
Bytes
0xA0
0xA4
IADDR_H Word Individual address filter high/low. Used in the hash table function of the individual
addressing mode. The user can write zeros to these values after reset and before the
IADDR_L Word
Ethernet channel is enabled to disable all individual hash address recognition
functions. Issuing a SET GROUP ADDRESS command enables the hash table. See
0xA8
MINFLR
Hword Minimum frame length register (typically 64 decimal). If the Ethernet receiver detects
an incoming frame shorter than MINFLR, it discards that frame unless FPSMR[RSH]
(receive short frames) is set, in which case RxBD[SH] (frame too short) is set in the
last RxBD. The Ethernet transmitter pads frames that are too short (according to
TxBD[PAD] and the PAD value in the parameter RAM). PADs are added to make the
transmit frame MINFLR bytes.
0xAA
0xAC
0xAE
0xB0
TADDR_H Hword Allows addition of addresses to the individual and group hashing tables. After an
address is placed in TADDR, issue a SET GROUP ADDRESS command. TADDR_L is the
lowest-order half-word; TADDR_H is the highest.
TADDR_M Hword
A zero in the I/G bit indicates an individual address; 1 indicates a group address.
TADDR_L Hword
PAD_PTR Hword Internal PAD pointer. This internal 32-byte aligned pointer points to a 32-byte buffer
filled with pad characters. The pads may be any value, but all the bytes should be the
same to assure padding with a specific character. If a specific padding character is not
needed, PAD_PTR should equal the internal temporary data pointer TIPTR; see
0xB2
—
Hword Reserved, should be cleared.
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Table 35-2. Ethernet-Specific Parameter RAM (continued)
Width Description
1
Offset
Name
0xB4
CF_RANG Hword Control frame range. Internal usage
E
0xB6
0xB8
MAX_B
Hword Maximum BD byte count. Internal usage
MAXD1
Hword Max DMA1 length register (typically 1520 decimal). Lets the user prevent system bus
writes after a frame exceeds a specified size. The MAXD1 value is valid only if an
address match is detected. If the Ethernet controller detects an incoming Ethernet
frame larger than the user-defined value in MAXD1, the rest of the frame is discarded.
The Ethernet controller waits for the end of the frame (or until MFLR bytes have been
received) and reports the frame status and length (including the discarded bytes) in
the last RxBD. This value must be greater than 32.
0xBA
MAXD2
Hword Max DMA2 length register (typically 1520 decimal). Lets the user prevent system bus
writes after a frame exceeds a specified size. The value of MAXD2 is valid in
promiscuous mode when no address match is detected. If the Ethernet controller
detects an incoming Ethernet frame larger than the value in MAXD2, the rest of the
frame is discarded. The Ethernet controller waits for the end of the frame (or until
MFLR bytes are received) and reports frame status and length (including the
discarded bytes) in the last RxBD. In a monitor station, MAXD2 can be much less than
MAXD1 to receive entire frames addressed to this station, but receive only the
headers of all other frames.This value must be less than MAXD1.
0xBC
0xBE
0xC0
MAXD
Hword Rx maximum DMA. Internal usage
DMA_CNT Hword Rx DMA counter. Temporary down-counter used to track the frame length.
2
OCTC
COLC
BROC
MULC
Word (RMON mode only) The total number of octets of data (including those in bad packets)
received on the network (excluding framing bits but including FCS octets).
2
2
2
0xC4
0xC8
0xCC
Word (RMON mode only) The best estimate of the total number of collisions on this Ethernet
segment.
Word (RMON mode only) The total number of good packets received that were directed to
the broadcast address. Note that this does not include multicast packets.
Word (RMON mode only) The total number of good packets received that were directed to
a multicast address. Note that this number does not include packets directed to the
broadcast address.
2
2
0xD0
0xD4
USPC
FRGC
Word (RMON mode only) The total number of packets received that were less than 64 octets
(excluding framing bits but including FCS octets) and were otherwise well-formed.
Word (RMON mode only) The total number of packets received that were less than 64 octets
long (excluding framing bits but including FCS octets) and had either a bad FCS with
an integral number of octets (FCS error) or a bad FCS with a non-integral number of
octets (alignment error). Note that it is entirely normal for etherStatsFragments to
increment because it counts both runts (which are normal occurrences due to
collisions) and noise hits.
2
0xD8
OSPC
Word (RMON mode only) The total number of packets received that were longer than 1518
octets (excluding framing bits but including FCS octets) and were otherwise
well-formed.
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Table 35-2. Ethernet-Specific Parameter RAM (continued)
Width Description
1
Offset
Name
2
0xDC
JBRC
Word (RMON mode only) The total number of packets received that were longer than 1518
octets (excluding framing bits but including FCS octets), and had either a bad FCS
with an integral number of octets (FCS error) or a bad FCS with a non-integral number
of octets (alignment error). Note that this definition of jabber is different than the
definition in IEEE-802.3 section 8.2.1.5 (10BASE5) and section 10.3.1.4 (10BASE2).
These documents define jabber as the condition where any packet exceeds 20 ms.
The allowed range to detect jabber is between 20 ms and 150 ms.
2
2
0xE0
0xE4
P64C
P65C
Word (RMON mode only) The total number of packets (including bad packets) received that
were 64 octets long (excluding framing bits but including FCS octets).
Word (RMON mode only) The total number of packets (including bad packets) received that
were between 65 and 127 octets long inclusive (excluding framing bits but including
FCS octets).
2
2
2
0xE8
0xEC
0xF0
0xF4
P128C
P256C
P512C
Word (RMON mode only) The total number of packets (including bad packets) received that
were between 128 and 255 octets long inclusive (excluding framing bits but including
FCS octets).
Word (RMON mode only) The total number of packets (including bad packets) received that
were between 256 and 511 octets long inclusive (excluding framing bits but including
FCS octets).
Word (RMON mode only) The total number of packets (including bad packets) received that
were between 512 and 1023 octets long inclusive (excluding framing bits but including
FCS octets).
2
P1024C
Word (RMON mode only) The total number of packets (including bad packets) received that
were between 1024 and 1518 octets long inclusive (excluding framing bits but
including FCS octets).
0xF8
0xFC
CAM_BUF Word Internal buffer for CAM result
Word Reserved, should be cleared.
—
1
2
Offset from FCC base: 0x8400 (FCC1), 0x8500 (FCC2) and 0x8600 (FCC3); see Section 14.5.2, “Parameter RAM.”
32-bit (modulo 232) counters maintained by the CP; cleared by the user while the channel is disabled.
35.9 Programming Model
The core configures an FCC to operate as an Ethernet controller using GFMR[MODE]. The receive errors
(collision, overrun, nonoctet-aligned frame, short frame, frame too long, and CRC error) are reported
through the RxBD. The transmit errors (underrun, heartbeat, late collision, retransmission limit, and carrier
sense lost) are reported through the TxBD.
The user should program the FDSR as described in Section 29.4, “FCC Data Synchronization Registers
35.10 Ethernet Command Set
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Fast Ethernet Controller
NOTE
Before resetting the CPM, configure TX_EN (RTS) to be an input.
Table 35-3. Transmit Commands
Command
Description
STOP
When used with the Ethernet controller, this command violates a specific behavior of an Ethernet/IEEE
802.3 station. It should not be used.
TRANSMIT
GRACEFUL
STOP
Used to smoothly stop transmission after the current frame finishes sending or undergoes a collision
(immediately if there is no frame being sent). FCCE[GRA] is set once transmission stops. Then the
Ethernet transmit parameters (including BDs) can be modified by the user. The TBPTR points to the
next TxBD in the table. Transmission begins when the R bit of the next BD is set and the RESTART
TRANSMIT command is issued. Note that if the GRACEFUL STOP TRANSMIT command is issued and the
current transmit frame ends in a collision, the TBPTR points to the beginning of the collided frame with
TxBD[R] still set (the frame looks as if it was never sent).
TRANSMIT
RESTART
TRANSMIT
Enables transmission of characters on the transmit channel. It is expected by the Ethernet controller
after a GRACEFUL STOP TRANSMIT command or transmitter error (underrun, retransmission limit reached,
or late collision). The Ethernet controller resumes transmission from the current TBPTR in the channel
TxBD table.
INIT TX
Initializes all the transmit parameters in this serial channel parameter RAM to their reset state. This
PARAMETERS command should be issued only when the transmitter is disabled. Note that the INIT TX AND RX
PARAMETERS command can also be used to reset the transmit and receive parameters.
Table 35-4. Receive Commands
Command
Description
ENTER HUNT
MODE
After the hardware or software is reset and the channel in the FCC mode register is enabled, the
channel is in the receive enable mode and uses the first BD in the table. This command is generally
used to force the Ethernet receiver to abort reception of the current frame and enter hunt mode. In hunt
mode, the Ethernet controller continually scans the input data stream for a transition of carrier sense
from inactive to active followed by a preamble sequence and the start frame delimiter. After receiving
the command, the current receive buffer is closed, the error status flags and length field are cleared,
RxBD[E] (the empty bit) is set, and the CRC calculation is reset. Further frame reception uses the
current RxBD.
Note that short frames pending in the internal FIFO may be lost.
INIT RX
Initializes all the receive parameters in this serial channel parameter RAM to their reset state and
PARAMETERS should only be issued when the receiver is disabled. Note that the INIT TX AND RX PARAMETERS
command can also be used to reset the receive and transmit parameters.
SET GROUP
ADDRESS
Used to set one of the 64 bits of the four individual/group address hash filter registers (GADDR[1–4]
or IADDR[1–4]). The individual or group address (48 bits) to be added to the hash table should be
written to TADDR_L, TADDR_M, and TADDR_H in the parameter RAM prior to executing this
command. The CP checks the I/G bit in the address stored in TADDR to determine whether to use the
individual hash table or the group hash table. A 0 in the I/G bit indicates an individual address; 1
indicates a group address. This command can be executed at any time, regardless of whether the
Ethernet channel is enabled.
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Fast Ethernet Controller
If an address from the hash table must be deleted, the Ethernet channel must be disabled, the hash table
registers must be cleared, and the SET GROUP ADDRESS command must be executed for the remaining
preferred addresses. This is required because the hash table might have mapped multiple addresses to the
same hash table bit.
35.11 RMON Support
The Fast Ethernet controller can automatically gather network statistics required for RMON without the
need to receive all addresses using promiscuous mode. Setting FPSMRx[MON] enables RMON support.
The RMON statistics and their corresponding counters in the parameter RAM are described in Table 35-5.
Table 35-5. RMON Statistics and Counters
Statistic
Description
Counter
etherStatsDropEvents
The total number of events in which packets were detected as
dropped by the probe due to lack of resources. Note that this may
not be the number of packets dropped; it is the number of times this
condition is detected.
DISFC
etherStatsOctets
etherStatsPkts
The total number of octets of data (including those in bad packets)
received on the network (excluding framing bits but including FCS
octets).
OCTC
The total number of packets (including bad packets, broadcast
packets, and multicast packets) received.
USPC +
OSPC +
FRGC +
JBRC +
P64C +
P65C +
P128C +
P256C +
P512C +
P1024C
etherStatsBroadcastPkts
etherStatsMulticastPkts
etherStatsCRCAlignErrors
The total number of good packets received that were directed to the
broadcast address. Note that this does not include multicast
packets.
BROC
The total number of good packets received that were directed to a
multicast address. Note that this number does not include packets
directed to the broadcast address.
MULC
The total number of packets received that had a length (excluding
framing bits but including FCS octets) of between 64 and 1518
octets, inclusive, but had either an integral number of octets (FCS
error) or a bad FCS with a non-integral number of octets (alignment
error).
CRCEC +
ALEC
-FRGC
-JBRC
etherStatsUndersizePkts
etherStatsOversizePkts
The total number of packets received that were less than 64 octets
long (excluding framing bits but including FCS octets) and were
otherwise well-formed.
USPC
OSPC
The total number of packets received that were longer than 1518
octets (excluding framing bits but including FCS octets) and were
otherwise well-formed.
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Fast Ethernet Controller
Table 35-5. RMON Statistics and Counters (continued)
Description
Statistic
Counter
etherStatsFragments
The total number of packets received that were less than 64 octets
long (excluding framing bits but including FCS octets) and had
either a bad FCS with an integral number of octets (FCS error) or a
bad FCS with a non-integral number of octets (alignment error).
Note that it is entirely normal for etherStatsFragments to increment,
because it counts both runts (which are normal occurrences due to
collisions) and noise hits.
FRGC
etherStatsJabbers
The total number of packets received that were longer than 1518
octets (excluding framing bits but including FCS octets) and had
either a bad FCS with an integral number of octets (FCS error) or a
bad FCS with a non-integral number of octets (alignment error).
Note that this definition of jabber is different than the definition in
IEEE-802.3 Section 8.2.1.5 (10BASE5) and Section 10.3.1.4
(10BASE2). These documents define jabber as the condition where
any packet exceeds 20 ms. The allowed range to detect jabber is
between 20 ms and 150 ms.
JBRC
etherStatsCollisions
The best estimate of the total number of collisions on this Ethernet
segment.
COLC
P64C
etherStatsPkts64Octets
The total number of packets (including bad packets) received that
were 64 octets long (excluding framing bits but including FCS
octets).
etherStatsPkts65to127Octets
etherStatsPkts128to255Octets
etherStatsPkts256to511Octets
etherStatsPkts512to1023Octets
The total number of packets (including bad packets) received that
were between 65 and 127 octets long inclusive (excluding framing
bits but including FCS octets).
P65C
P128C
P256C
P512C
P1024C
The total number of packets (including bad packets) received that
were between 128 and 255 octets long inclusive (excluding framing
bits but including FCS octets).
The total number of packets (including bad packets) received that
were between 256 and 511 octets long inclusive (excluding framing
bits but including FCS octets).
The total number of packets (including bad packets) received that
were between 512 and 1023 octets long inclusive (excluding
framing bits but including FCS octets).
etherStatsPkts1024to1518Octets The total number of packets (including bad packets) received that
were between 1024 and 1518 octets long inclusive (excluding
framing bits but including FCS octets).
35.12 Ethernet Address Recognition
The Ethernet controller can filter the received frames based on different addressing types—physical
(individual), group (multicast), broadcast (all-ones group address), and promiscuous. The difference
between an individual address and a group address is determined by the I/G bit in the destination address
field.
Figure 35-4 is a flowchart for address recognition on received frames.
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Fast Ethernet Controller
Check
Address
G
I
I/G Address
F
F
Individual
Addr Match?
Broadcast
Addr
T
Hash Search
Hash Search
T
Use Group
Table
Use Individual
Table
Broadcast
Enabled
T
T
Receive Frame
Match?
F
F
F
T
Promiscuous?
T
Use
CAM?
F
T
F
Rejected
by CAM?
Discard Frame
Start Receive
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Fast Ethernet Controller
Figure 35-4. Ethernet Address Recognition Flowchart
In the physical type of address recognition, the Ethernet controller compares the destination address field
of the received frame with the physical address that the user programs in the PADDR. If it fails, the
controller performs address recognition on multiple individual addresses using the IADDR_H/L hash
table. Since the controller always checks PADDR and the individual hash, for individual address the user
must write zeros to the hash in order to avoid a hash match and ones to PADDR in order to avoid individual
address match.
In the group type of address recognition, the Ethernet controller determines whether the group address is
a broadcast address. If it is a broadcast and broadcast addresses are enabled, the frame is accepted. If the
group address is not a broadcast address, the user can perform address recognition on multiple group
addresses using the GADDR_H/L hash table. In promiscuous mode, the Ethernet controller receives all of
the incoming frames regardless of their address when an external CAM is not used.
If an external CAM is used for address recognition (FPSMR[CAM] = 1), the user should select
promiscuous mode; the frame can be rejected if there is no match in the CAM. If the on-chip address
recognition functions detect a match, the external CAM is not accessed. Otherwise, the CPM issues a
match transaction to the CAM using the bus on which the data buffers reside. (The data buffer bus is
the CAM is placed on the local bus and the data buffers are on the 60x bus, match transactions are
eventually accessed correctly. That is, the CPM attempts to access the CAM on the 60x bus, but the
60x-to-local-bus bridge logic detects the 60x bus transaction and forwards it to the CAM on the local bus.
35.13 Hash Table Algorithm
The hash table process used in the individual and group hash filtering operates as follows. The Ethernet
controller maps any 48-bit address into one of 64 bins, which are represented by the 64 bits in
GADDR_H/L or IADDR_H/L. When the SET GROUP ADDRESS command is executed, the Ethernet
controller maps the selected 48-bit address in TADDR into one of the 64 bits. This is performed by passing
the 48-bit address through the on-chip 32-bit CRC generator and using 6 bits of the CRC-encoded result
to generate a number between 1 and 64. Bit 26 of the CRC result selects which address filter registers are
used in the hashing process—either GADDR_H/IADDR_H or GADDR_L/IADDR_L— and bits 27–31
of the CRC result select which bit is set.
The same process is used when the Ethernet controller receives a frame. If the CRC generator selects a bit
that is set in the group/individual hash table, the frame is accepted; otherwise, it is rejected. The result is
that if eight group addresses are stored in the hash table and random group addresses are received, the hash
table prevents roughly 56/64 (87.5%) of the group address frames from reaching memory. The core must
further filter those that reach memory to determine if they contain one of the eight preferred addresses.
Better performance is achieved by using the group and individual hash tables in combination. For instance,
if eight group and eight physical addresses are stored in their respective hash tables, 87.5% of all frames
(not just group address frames) are prevented from reaching memory.
The effectiveness of the hash table declines as the number of addresses increases. For instance, with 128
addresses stored in a 64-bin hash table, the vast majority of the hash table bits are set, preventing only a
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Fast Ethernet Controller
small fraction of frames from reaching memory. In such instances, an external CAM is advised if the extra
NOTE
The hash tables cannot be used to reject frames that match a set of selected
addresses because unintended addresses can map to the same bit in the hash
table. Thus, an external CAM must be used to implement this function.
35.14 Interpacket Gap Time
The minimum interpacket gap time for back-to-back transmission is 96 bit-times. The receiver receives
back-to-back frames with this minimum spacing. In addition, after the backoff algorithm, the transmitter
waits for carrier sense to be negated before retransmitting the frame. The retransmission begins 96 bit
times after carrier sense is negated if it stays negated for at least 64 bit times. So if there is no change in
the carrier sense indication during the first 64 bit-times (16 serial clocks), the retransmission begins 96
clocks after carrier sense is first negated
35.15 Handling Collisions
If a collision occurs during frame transmission, the Ethernet controller continues transmission for at least
32-bit times, transmitting a jam pattern of 32 ones. If the collision occurs during the preamble sequence,
the jam pattern is sent after the sequence ends.
If a collision occurs within 64 byte times, the process is retried. The transmitter waits a random number of
slot times. (A slot time is 512 bit times.) If a collision occurs after 64 byte times, no retransmission is
performed, FCCE[TXE] is set, and the buffer is closed with a late-collision error indication in TxBD[LC].
If a collision occurs during frame reception, reception is stopped. This error is reported only in the RxBD
if the frame is at least as long as the MINFLR or if FPSMR[RSH] = 1.
35.16 Internal and External Loopback
Both internal and external loopback are supported by the Ethernet controller. In loopback mode, both
receive and transmit FIFO buffers are used and the FCC operates in full-duplex. Both internal and external
loopback are configured using combinations of FPSMR[LPB] and GFMR[DIAG]. Because of the
full-duplex nature of the loopback operation, the performance of the other FCCs is degraded.
Internal loopback disconnects the FCC from the SI. The receive data is connected to the transmit data. The
transmitted data from the transmit FIFO is received immediately into the receive FIFO. There is no
heartbeat check in this mode.
In external loopback operation, the Ethernet controller listens for data received from the PHY while it is
sending.
35.17 Ethernet Error-Handling Procedure
The Ethernet controller reports frame reception and transmission error conditions using the channel BDs,
the error counters, and the FCC event register.
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Table 35-6. Transmission Errors
Error
Response
Transmitter
underrun
The controller sends 32 bits that ensure a CRC error, terminates buffer transmission, closes the
buffer, sets TxBD[UN] and FCCE[TXE]. The controller resumes transmission after receiving the
RESTART TRANSMIT command.
Carrier sense
If no collision is detected in the frame, the controller sets TxBD[CSL] and FCCE[TXE], and it
lostduringframe continues the buffer transmission normally. No retries are performed as a result of this error.
transmission
Retransmission The controller terminates buffer transmission, closes the buffer, sets TxBD[RL] and FCCE[TXE].
attempts limit
expired
Transmission resumes after receiving the RESTART TRANSMIT command.
Late collision
The controller terminates buffer transmission, closes the buffer, sets TxBD[LC] and FCCE[TXE].
The controller resumes transmission after receiving the RESTART TRANSMIT command. Note that late
collision parameters are defined in FPSMR[LCW].
Table 35-7. Reception Errors
Error
Description
Overrun error
The Ethernet controller maintains an internal FIFO buffer for receiving data. If a receiver FIFO buffer
overrun occurs, the controller writes the received data byte to the internal FIFO buffer over the
previously received byte. The previous data byte and frame status are lost. The controller closes the
buffer, sets RxBD[OV] and FCCE[RXF], and increments the discarded frame counter (DISFC). The
receiver then enters hunt mode.
Busy error
A frame is received and discarded due to a lack of buffers. The controller sets FCCE[BSY] and
increments the discarded frame counter (DISFC).
Non-octet error The Ethernet controller handles a nibble of dribbling bits when the receive frame terminates as
(dribbling bits)
nonoctet aligned and it checks the CRC of the frame on the last octet boundary. If there is a CRC
error, the frame nonoctet aligned (RxBD[NO]) error is reported, FCCE[RXF] is set, and the
alignment error counter (ALEC) in the parameter RAM is incremented. If there is no CRC error, no
error is reported.
CRC error
When a CRC error occurs, the controller closes the buffer, and sets RxBD[CR] and FCCE[RXF].
Also, the CRC error counter (CRCEC) in the parameter RAM is incremented. After receiving a frame
with a CRC error, the receiver enters hunt mode. CRC checking cannot be disabled, but the CRC
error can be ignored if checking is not required.
35.18 Fast Ethernet Registers
The following sections describe registers used for configuring and operating the Fast Ethernet controller.
35.18.1 FCC Ethernet Mode Register (FPSMR)
Ethernet mode register.
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Freescale Semiconductor
Fast Ethernet Controller
0
1
2
3
4
5
6
7
8
9
10
11
12
15
Field HBC FC SBT LPB LCW FDE MON
—
PRO FCE RSH
—
Reset
R/W
0000_0000_0000_0000
R/W
Addr
16
20
21
22
23
24
25
26
31
Field
Reset
R/W
—
CAM BRO ECM
CRC
—
0000_0000_0000_0000
R/W
Addr
0x11306 (FPSMR1), 0x11326 (FPSMR2), 0x11326 (FPSMR3)
Figure 35-5. FCC Ethernet Mode Registers (FPSMR)
Table 35-8 describes FPSMR fields.
Table 35-8. FPSMR Ethernet Field Descriptions
Bits
Name
Description
0
1
HBC
Heartbeat checking
0 Heartbeat checking is not performed. Do not wait for a collision after transmission.
1 Wait 40 transmit serial clocks for a collision asserted by the transceiver after transmission.
TxBD[HB] is set if the heartbeat is not heard within 40 transmit serial clocks.
FC
Force collision
0 Normal operation.
1 The controller forces a collision on transmission of every transmit frame. The PowerQUICC II
should be configured in loopback operation when using this feature, which allows the user to test
the PowerQUICC II collision logic. It causes the retry limit to be exceeded for each transmit frame.
2
3
SBT
Stop backoff timer
0 The backoff timer functions normally.
1 The backoff timer (for the random wait after a collision) is stopped whenever carrier sense is
active. In this method, the retransmission is less aggressive than the maximum allowed in the
IEEE 802.3 standard. The persistence (P_PER) feature in the parameter RAM can be used in
combination with the SBT bit (or in place of the SBT bit).
LPB
Local protect bit
0 Receiver is blocked when transmitter sends (default).
1 Receiver is not blocked when transmitter sends. Must be set for full-duplex operation. For
loopback operation, GFMR[DIAG] must be programmed also; see Section 29.2, “General FCC
4
5
6
LCW
FDE
MON
Late collision window
0 A late collision is any collision that occurs at least 64 bytes from the preamble.
1 A late collision is any collision that occurs at least 56 bytes from the preamble.
Full duplex Ethernet
0 Disable full-duplex.
1 Enable full-duplex. Must be set if FSMR[LPB] is set or external loopback is performed.
RMON mode
0 Disable RMON mode.
1 Enable RMON mode.
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35-19
Fast Ethernet Controller
Table 35-8. FPSMR Ethernet Field Descriptions (continued)
Bits
7–8
Name
Description
—
Reserved, should be cleared.
9
PRO
Promiscuous
0 Check the destination address of incoming frames.
1 Receive the frame regardless of its address. A CAM can be used for address filtering when
FSMR[CAM] is set.
10
11
FCE
RSH
Flow control enable
0 Flow control is not enabled.
1 Flow control is enabled.
Receive short frames
0 Discard short frames (frames smaller than the value specified in MINFLR).
1 Receive short frames.
12–20
21
—
Reserved, should be cleared.
CAM
CAM address matching
0 Normal operation.
1 Use the CAM for address matching; CAM result (16 bits) is added at the end of the frame.
22
23
BRO
ECM
Broadcast address
0 Receive all frames containing the broadcast address.
1 Reject all frames containing the broadcast address unless FSMR[PRO] = 1.
• Enable CAM miss. Valid only when the CAM is enabled. This bit interacts with RxBD[CMR].
0 Discard frames that miss in the CAM.
1 Receive frames that miss in the CAM.
24–25 CRC
CRC selection
0x Reserved.
10 32-bit CCITT-CRC (Ethernet). X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 +
X5 + X4 + X2 + X1 +1. Select this to comply with Ethernet specifications.
11 Reserved.
26–31
—
Reserved, should be cleared.
35.18.2 Ethernet Event Register (FCCE)/Mask Register (FCCM)
Ethernet controller. It generates interrupts and reports events recognized by the Ethernet channel. On
recognition of an event, the Ethernet controller sets the corresponding FCCE bit. Interrupts generated by
this register can be masked in the Ethernet mask register (FCCM).
The FCCM has the same bit format as FCCE. Setting an FCCM bit enables and clearing a bit masks the
corresponding interrupt in the FCCE.
The FCCE can be read at any time. Bits are cleared by writing ones; writing zeros does not affect bit values.
Unmasked FCCE bits must be cleared before the CP clears the internal interrupt request.
Figure 35-6. Ethernet Event Register (FCCE)/Mask Register (FCCM)
0
7
8
9
10
11
12
13
14
15
Field
—
GRA RXC TXC TXE RXF BSY TXB RXB
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Fast Ethernet Controller
Figure 35-6. Ethernet Event Register (FCCE)/Mask Register (FCCM)
Reset
0000_0000_0000_0000
R/W
R/W
Addr
16
31
Field
Reset
R/W
—
0000_0000_0000_0000
R/W
Addr
0x11312 (FCCE1), 0x11332 (FCCE2), 0x11352 (FCCE3)/
0x11316 (FCCM1), 0x11336 (FCCM2), 0x11356 (FCCM3)
Table 35-9 describes FCCE/FCCM fields.
Table 35-9. FCCE/FCCM Field Descriptions
Bits
Name
Description
0–7
8
—
Reserved, should be cleared.
GRA Graceful stop complete. A graceful stop, initiated by the GRACEFUL STOP TRANSMIT command, is
complete. When the command is issued, GRA is set as soon the transmitter finishes sending a
frame in progress. If no frame is in progress, GRA is set immediately.
9
RXC RX control. A control frame has been received (FSMR[FCE] must be set). As soon as the transmitter
finishes sending the current frame, a pause operation is performed.
10
11
TXC TX control. An out-of-sequence frame was sent.
TXE Tx error. An error occurred on the transmitter channel.
12
RXF Rx frame. Set when a complete frame is received on the Ethernet channel.
BSY Busy condition. Set when a frame is received and discarded due to a lack of buffers.
TXB Tx buffer. Set when a buffer has been sent on the Ethernet channel.
RXB Rx buffer. A buffer that was not a complete frame is received on the Ethernet channel.
13
14
15
16–31
—
Reserved, should be cleared.
Figure 35-7 shows interrupts that can be generated in the Ethernet protocol.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
35-21
Fast Ethernet Controller
Frame
Received in Ethernet
Stored in Rx Buffer
P SFD DA SA T/L
Time
D
CR
RXD
Line Idle
Line Idle
RX_DV
Ethernet FCCE
Events
RXB
RXF
Notes:
1. RXB event assumes receive buffers are 64 bytes each.
2. The RXF interrupt may occur later than RX_DV due to receive FIFO latency.
Frame
Transmitted by Ethernet
Stored in Tx Buffer
P SFD DA SA T/L
D
CR
TXD
TX_EN
COL
Line Idle
Line Idle
Ethernet FCCE
Events
TXB
TXB, GRA
Notes:
1. TXB events assume the frame required two transmit buffers.
2. The GRA event assumes a graceful stop transmit command was issued during frame transmission.
Legend:
P = Preamble, SFD = Start frame delimiter, DA and SA = Destination/Source address,
T/L = Type/Length, D = Data, CR = CRC bytes
Figure 35-7. Ethernet Interrupt Events Example
NOTE
The FCC status register is not valid for the Ethernet protocol. The current
state of the MII signals can be read through the parallel ports.
35.19 Ethernet RxBDs
The Ethernet controller uses the RxBD to report information about the received data for each buffer.
Figure 35-8 shows the FCC Ethernet RxBD format.
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Fast Ethernet Controller
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Offset + 0
Offset + 2
Offset + 4
Offset + 6
E
—
W
I
L
F
CMR
M
BC MC
LG
NO
SH
CR
OV
CL
Data Length
Rx Data Buffer Pointer
Figure 35-8. Fast Ethernet Receive Buffer (RxBD)
Table 35-10 describes Ethernet RxBD fields.
Table 35-10. RxBD Field Descriptions
Bits
Name
E
Description
0
Empty
0 The buffer associated with this RxBD is full or reception terminated due to an error. The core can
examine or read to any fields of this RxBD. The CP does not use this BD as long as E = 0.
1 The associated buffer is empty. The RxBD and buffer are owned by the CP. Once E = 1, the core
should not write any fields of this RxBD.
1
2
—
Reserved, should be cleared.
W
Wrap (final BD in RxBD table)
0 Not the last BD in the table.
1 Last BD in the table. After this buffer is used, the CP receives incoming data into the first BD that
RBASE points to in the table. The number of RxBDs in this table is programmable and determined
only by the W bit.
The RxBD table must contain more than one BD in Ethernet mode.
3
4
I
Interrupt
0 No interrupt is generated after this buffer is used.
1 FCCE[RXB] or FCCE[RXF] are set when this buffer is used by the Ethernet controller. These two
bits can cause interrupts if they are enabled.
L
Last in frame. Set by the Ethernet controller when this buffer is the last in a frame. This implies the
end of the frame or a reception error, in which case one or more of the CL, OV, CR, SH, NO, and LG
bits are set. The Ethernet controller writes the number of frame octets to the data length field.
0 Not the last buffer in a frame.
1 Last buffer in a frame.
5
6
F
First in frame. Set by the Ethernet controller when this buffer is the first in a frame.
0 Not the first buffer in a frame.
1 First buffer in a frame.
CMR CAM match result for the frame. Set by the Ethernet controller when using a CAM for address
matching and FPSMR[ECM] = 1. Valid only if the L bit is set.
0 A hit in the CAM.
1 A miss in the CAM.
7
M
Miss. Set by the Ethernet controller for frames that are accepted in promiscuous mode, but are
flagged as a miss by the internal address recognition. Thus, while using promiscuous mode, the
user uses the miss bit to determine quickly whether the frame is destined for this station. Valid only
if RxBD[I] is set.
0 The frame is received because the address is recognized.
1 The frame is received because of promiscuous mode (address is not recognized).
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Fast Ethernet Controller
Table 35-10. RxBD Field Descriptions (continued)
Description
Bits
Name
8
BC
Broadcast address. Valid only for the last buffer in a frame (RxBD[L] = 1). The received frame
address is the broadcast address.
9
MC
LG
NO
SH
Multicast address. Valid only for the last buffer in a frame (RxBD[L] = 1). The received frame address
is a multicast address other than a broadcast address.
10
11
12
Rx frame length violation. A frame length greater than the MFLR (maximum frame length) defined
for this FCC is recognized.
Rx nonoctet aligned frame. A frame that contained a number of bits not divisible by eight is received
and the CRC check at the preceding byte boundary generated an error.
Short frame. A frame length less than the MINFLR (minimum frame length) defined for this channel
is recognized. This indication is possible only if the FPSMR[RSH] = 1.
13
14
15
CR
OV
CL
Rx CRC error. This frame contains a CRC error.
Overrun. A receiver overrun occurred during frame reception.
Collision. This frame is closed because a collision occurred during frame reception. Set only if a late
collision occurs or if FPSMR[RSH] is set. The late collision definition is determined by the setting of
FPSMR[LCW].
Data length is the number of octets the CP writes into this BD data buffer. It is written by the CP as the
buffer is closed. When this BD is the last BD in the frame (RxBD[L] = 1), the data length contains the total
number of frame octets (including four bytes for CRC). Note that at least as much memory should be
allocated for each receive buffer as the size specified in MRBLR. MRBLR should be divisible by 32 and
not less than 64.
The receive buffer pointer, which points to the first location of the associated data buffer, can reside in
external memory. This value must be divisible by 16.
When a received frame’s data length is an exact multiple of MRBLR, the last BD contains only the status
and total frame length.
NOTE
At least two BDs must be prepared before beginning reception.
Figure 35-9 shows how RxBDs are used during Ethernet reception.
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Fast Ethernet Controller
MRBLR = 64 Bytes for this FCC
Receive BD 0
Buffer
E
0
L
F
Destination Address
(6)
Status
Length
0
1
0x0040
Source Address (6)
Type/Length (2)
Buffer Full
Pointer
32-Bit Buffer Pointer
64 Bytes
Data Bytes (50)
Receive BD 1
Buffer
CRC Bytes (4)
Tag Byte (1)
Empty
E
0
L
F
Status
Length
1
0
0x0045
Pointer
32-Bit Buffer Pointer
64 Bytes
Buffer Closed
after CRC Received.
Optional Tag Byte
Appended
Receive BD 2
Buffer
E
1
Status
Length
Old Data from
Collided Frame Will
be Overwritten
XXXX
64 Bytes
Collision
Causes Buffer
Pointer
32-Bit Buffer Pointer
to be Reused
Empty
Buffer
Receive BD 3
E
1
Status
Length
XXXX
64 Bytes
Empty
Buffer
Still Empty
Pointer
32-Bit Buffer Pointer
Non-Collided Ethernet Frame 1
Line Idle
Frame 2
Two Frames
Received in Ethernet
Collision Present
Time
Time
Figure 35-9. Ethernet Receiving Using RxBDs
35.20 Ethernet TxBDs
Data is sent to the Ethernet controller for transmission on an FCC channel by arranging it in buffers
referenced by the channel’s TxBD table. The Ethernet controller uses TxBDs to confirm transmission or
indicate errors so the core knows when buffers have been serviced. Figure 35-10 shows the FCC Ethernet
TxBD format.
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Fast Ethernet Controller
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Offset + 0
Offset + 2
Offset + 4
Offset + 6
R
PAD
W
I
L
TC DEF HB
LC
RL
RC
UN CSL
Data length
Tx data Buffer Pointer
Figure 35-10. Fast Ethernet Transmit Buffer (TxBD)
Table 35-11 describes Ethernet TxBD fields.
Table 35-11. Ethernet TxBD Field Definitions
Field Name
Description
0
R
Ready
0 The buffer associated with this BD is not ready for transmission; the user can manipulate this BD
or its associated buffer. The CP clears R after the buffer has been sent or after an error.
1 The buffer is ready to be sent. The buffer is either waiting or in the process of being sent. The
user cannot change fields in this BD or its associated buffer once R = 1.
1
2
PAD Short frame padding. Valid only when L = 1; otherwise, it is ignored.
0 Do not add PADs to short frames.
1 Add PADs to short frames. PAD bytes are inserted until the length of the transmitted frame equals
the MINFLR. The PAD bytes are stored in a buffer pointed to by PAD_PTR in the parameter RAM.
W
Wrap (final BD in table)
0 Not the last BD in the TxBD table.
1 Last BD in the TxBD table. After this buffer is used, the CP receives incoming data into the first
BD that TBASE points to in the table. The number of TxBDs in this table is programmable and
determined only by the W bit.
The TxBD table must contain more than one BD in Ethernet mode.
3
I
Interrupt
0 No interrupt is generated after this buffer is serviced.
1 FCCE[TXB] or FCCE[TXE] is set after this buffer is serviced. These bits can cause interrupts if
they are enabled.
4
5
L
Last
0 Not the last buffer in the transmit frame.
1 Last buffer in the current transmit frame.
TC
Tx CRC. Valid only when the L bit is set; otherwise, it is ignored.
0 End transmission immediately after the last data byte.
1 Transmit the CRC sequence after the last data byte.
6
7
DEF Defer indication. This frame did not have a collision before it was sent but it was sent late because
of deferring.
HB
Heartbeat. The collision input is not asserted within 40 transmit serial clocks following completion of
transmission. This bit cannot be set unless FPSMR[HBC] = 1. Written by the Ethernet controller
after sending the associated buffer.
8
9
LC
RL
Late collision. A collision occurred after the number of bytes defined in FPSMR[LCW] (56 or 64) are
sent. The Ethernet controller terminates the transmission and updates LC after sending the buffer.
Retransmission limit. The transmitter failed (RET_LIM + 1) attempts to successfully send a message
due to repeated collisions. The Ethernet controller updates RL after sending the buffer.
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Fast Ethernet Controller
Table 35-11. Ethernet TxBD Field Definitions (continued)
Description
Field Name
10–13
RC
Retry count. Indicates the number of retries required for this frame to be successfully sent. If RC =
0, the frame is sent correctly the first time. If RC = 15 and RET_LIM = 15 in the parameter RAM, 15
retries were needed. If RC = 15 and RET_LIM > 15, 15 or more retries were needed. The Ethernet
controller updates RC after sending the buffer.
14
15
UN
Underrun. The Ethernet controller encountered a transmitter underrun condition while sending the
associated buffer. The Ethernet controller updates UN after sending the buffer.
CSL Carrier sense lost. Carrier sense is lost during frame transmission. The Ethernet controller updates
CSL after sending the buffer.
Data length is the number of octets the Ethernet controller should transmit from this BD data buffer. This
value should be greater than zero. The CP never modifies the data length in a TxBD.
Tx data buffer pointer, which contains the address of the associated data buffer, can be even or odd. The
buffer can reside in external memory. The CP never modifies the buffer pointer.
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Fast Ethernet Controller
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Chapter 36
FCC HDLC Controller
Layer 2 of the seven-layer OSI model is the data link layer (DLL), in which HDLC is one of the most
insertion/deletion process (commonly known as bit stuffing) to ensure that the bit pattern of the delimiter
flag does not occur in the fields between flags. The HDLC frame is synchronous and therefore relies on
the physical layer for a method of clocking and of synchronizing the transmitter/receiver.
Because the layer 2 frame can be transmitted over a point-to-point link, a broadcast network, or a
packet-and-circuit switched system, an address field is needed for the frame's destination address. The
length of this field is commonly 0, 8, or 16 bits, depending on the data link layer protocol. For instance,
SDLC and LAPB use an 8-bit address and SS#7 has no address field because it is used always in
point-to-point signaling links. LAPD further divides its 16-bit address into different fields to specify
various access points within one device. It also defines a broadcast address. Some HDLC-type protocols
also permit extended addressing beyond 16 bits.
The 8- or 16-bit control field provides a flow-control number and defines the frame type (control or data).
The exact use and structure of this field depends upon the protocol using the frame. Data is transmitted in
the data field, which can vary in length depending upon the protocol using the frame. Layer 3 frames are
carried in this data field.
Error control is implemented by appending a cyclic redundancy check (CRC) to the frame, which in most
protocols is 16-bits long but can be as long as 32-bits. In HDLC, the lsb of each octet is transmitted first
and the msb of the CRC is transmitted first.
When GFMR[MODE] selects HDLC mode, that FCC functions as an HDLC controller. When an FCC in
HDLC mode is used with a nonmultiplexed modem interface, the FCC outputs are connected directly to
the external pins. Modem signals can be supported through the appropriate port pins. The receive and
transmit clocks can be supplied either externally or from the bank of baud-rate generators. The HDLC
controller can also be connected to one of the TDM channels of the serial interface and used with the TSA.
The HDLC controller consists of separate transmit and receive sections whose operations are
asynchronous with the core and can either be synchronous or asynchronous with other FCCs. The user can
allocate external buffer descriptors (BDs) for receive and transmit tasks so many frames can be sent or
received without core intervention.
36.1 Key Features
Key features of the HDLC include the following:
•
•
•
Flexible data buffers with multiple buffers per frame
Separate interrupts for frames and buffers (receive and transmit)
Received frames threshold to reduce interrupt overhead
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36-1
FCC HDLC Controller
•
•
•
•
•
•
•
•
•
•
•
•
Four address comparison registers with masks
Maintenance of four 16-bit error counters
Flag/abort/idle generation and detection
Zero insertion/deletion
16- or 32-bit CRC-CCITT generation/checking
Detection of nonoctet-aligned frames
Detection of frames that are too long
Programmable flags (0–15) between successive frames
External BD table
Up to T3 rate
Support of time stamp mode for Rx frames
Support of nibble mode HDLC (4 bits per clocks)
36.2 HDLC Channel Frame Transmission Processing
The HDLC transmitter is designed to work with almost no core intervention. When the core enables a
transmitter, it starts sending flags or idles as programmed in the HDLC mode register (FPSMR). The
HDLC controller polls the first BD in the transmit channel BD table. When there is a frame to transmit,
the HDLC controller fetches the data (address, control, and information) from the first buffer and begins
sending the frame after first inserting the user-specified minimum number of flags between frames. When
the end of the current buffer is reached and TxBD[L] (last buffer in frame) is set, the FCC appends the
CRC (if selected) and closing flag. In HDLC, the lsb of each octet and the msb of the CRC are sent first.
Figure 36-1 shows a typical HDLC frame.
Opening Flag
Address
Control
Information (Optional)
CRC
Closing Flag
8 Bits
16 Bits
8 Bits
8n Bits
16 Bits
8 Bits
Figure 36-1. HDLC Framing Structure
After the closing flag is sent, the HDLC controller writes the frame status bits into the BD and clears the
R bit. When the end of the current BD is reached and the L (last) bit is not set (working in multibuffer
mode), only the R bit is cleared. In either mode, an interrupt can be issued if the I bit in the TxBD is set.
The HDLC controller then proceeds to the next TxBD in the table. In this way, the core can be interrupted
after each buffer, after a specific buffer, after each frame, or after a number of frames.
To rearrange the transmit queue before the CP has sent all buffers, issue the STOP TRANSMIT command.
This can be useful for sending expedited data before previously linked buffers or for error situations. When
receiving the STOP TRANSMIT command, the HDLC controller aborts the current frame transmission and
starts transmitting idles or flags. When the HDLC controller is given the RESTART TRANSMIT command, it
resumes transmission. To insert a high-priority frame without aborting the current frame, the GRACEFUL
STOP TRANSMIT command can be issued. A special interrupt (GRA) can be generated in the event register
when the current frame is complete.
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FCC HDLC Controller
36.3 HDLC Channel Frame Reception Processing
The HDLC receiver is designed to work with almost no core intervention and can perform address
recognition, CRC checking, and maximum frame length checking. The received frame is available for any
HDLC-based protocol. When the core enables a receiver, the receiver waits for an opening flag character.
When it detects the first byte of the frame, the HDLC controller compares the frame address against the
user-programmable addresses. The user has four 16-bit address registers and an address mask available for
address matching. The HDLC controller compares the received address field to the user-defined values
after masking with the address mask. The HDLC controller can also detect broadcast (all ones) address
frames if one address register is written with all ones.
If a match is detected, the HDLC controller checks the prefetched BD; if it is empty, it starts transferring
the incoming frame to the BD’s associated buffer. When the buffer is full, the HDLC controller clears
BD[E] and generates an interrupt if BD[I] = 1. If the incoming frame is larger than the buffer, the HDLC
controller fetches the next BD in the table and, if it is empty, continues transferring the frame to the
associated buffer.
During this process, the HDLC controller checks for frames that are too long. When the frame ends, the
CRC field is checked against the recalculated value and written to the buffer. The data length written to
the last BD in the HDLC frame is the length of the entire frame. This enables HDLC protocols that lose
frames to correctly recognize a frame-too-long condition.
The HDLC controller then sets the last buffer in frame bit, writes the frame status bits into the BD, and
clears the E bit and fetches the next BD. The HDLC controller then generates a maskable interrupt,
indicating that a frame was received and is in memory. The HDLC controller then waits for a new frame.
Back-to-back frames can be received separated only by a single shared flag.
The user can configure the HDLC controller not to interrupt the core until a specified number of frames
have been received. This is configured in the received frames threshold (RFTHR) location of the parameter
RAM. This function can be combined with a timer to implement a time-out if fewer than the threshold
number of frames are received.
36.4 HDLC Parameter RAM
When an FCC operates in HDLC mode, the protocol-specific area of the FCC parameter RAM is mapped
Table 36-1. FCC HDLC-Specific Parameter RAM Memory Map
1
Offset
Name
Width
Description
0x3C
0x44
—
2 Words Reserved
C_MASK
Word CRC constant. For the 16-bit CRC-CCITT, initialize C_MASK to 0x0000_F0B8. For
the 32-bit CRC-CCITT, initialize C_MASK to 0xDEBB_20E3.
0x48
0x4C
C_PRES
Word CRC preset. For the 16-bit CRC-CCITT, initialize C_PRES to 0x0000_FFFF. For the
32-bit CRC-CCITT, initialize C_PRES to 0xFFFF_FFFF.
2
DISFC
Hword Discard frame counter. Counts error-free frames discarded due to lack of buffers.
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36-3
FCC HDLC Controller
Table 36-1. FCC HDLC-Specific Parameter RAM Memory Map (continued)
Name Width Description
1
Offset
2
0x4E
CRCEC
Hword CRC error counter. Counts frames not addressed to the user or frames received in
the BSY condition, but does not include overrun, CD lost, or abort errors.
2
0x50
0x52
ABTSC
Hword Abort sequence counter
2
NMARC
Hword Nonmatching address Rx counter. Counts nonmatching addresses received
(error-free frames only). See the HMASK and HADDR[1–4] parameter description.
0x54 MAX_CNT Word Max_length counter. Temporary decrementing counter that tracks frame length.
0x58
MFLR
Hword Max frame length register. If the HDLC controller detects an incoming HDLC frame
that exceeds the user-defined value in MFLR, the rest of the frame is discarded and
the LG (Rx frame too long) bit is set in the last BD belonging to that frame. The HDLC
controller waits for the end of the frame and then reports the frame status and length
in the last RxBD. MFLR includes all in-frame bytes between the opening and closing
flags (address, control, data, and CRC).
0x5A
0x5C
RFTHR
Hword Received frames threshold. Used to reduce the interrupt overhead that might
otherwise occur when a series of short HDLC frames arrives, each causing an RXF
interrupt. By programming RFTHR, the user lowers the frequency of RXF interrupts,
which occur only when the RFTHR value is reached. Note that the user should
provide enough empty RxBDs to receive the number of frames specified in RFTHR.
RFCNT
HMASK
Hword Received frames count. A decrementing counter used to implement this feature.
Initialize this counter with RFTHR.
0x5E
0x60
0x62
0x64
0x66
Hword HMASK and HADDR[1–4]. The HDLC controller reads the frame address from the
HDLC receiver, checks it against the four address register values, and masks the
HADDR1 Hword
HADDR2 Hword
HADDR3 Hword
HADDR4 Hword
result with HMASK. In HMASK, a 1 represents a bit position for which address
comparison should occur; 0 represents a masked bit position. When addresses
match, the address and subsequent data are written into the buffers. When
addresses do not match and the frame is error-free, the nonmatching address
received counter (NMARC) is incremented.
Note that for 8-bit addresses, mask out (clear) the eight high-order bits in HMASK.
The eight low-order bits and HADDRx should contain the address byte that
immediately follows the opening flag. For example, to recognize a frame that begins
0x7E (flag), 0x68, 0xAA, using 16-bit address recognition, HADDRx should contain
0x68
0x6A
TS_TMP
Hword Temporary storage
TMP_MB Hword Temporary storage
1
2
Offset from FCC base: 0x8400 (FCC1), 0x8500 (FCC2) and 0x8600 (FCC3); see Section 14.5.2, “Parameter RAM.”
DISFC, CRCEC, ABTSC, and NMARC—These 16-bit (modulo 216) counters are maintained by the CP. The user can
initialize them while the channel is disabled.
Figure 36-2 shows an example of using HMASK and HADDR[1–4].
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Freescale Semiconductor
FCC HDLC Controller
16-Bit Address Recognition
8-Bit Address Recognition
Flag
0x7E
Address
Address
0xAA
Control
0x44
Flag
0x7E
Address
0x55
Control
0x44
etc.
etc.
0x68
HMASK
HADDR1
HADDR2
HADDR3
HADDR4
0xFFFF
HMASK
0x00FF
0xXX55
0xXX55
0xXX55
0xXX55
0xAA68
0xFFFF
0xAA68
0xAA68
HADDR1
HADDR2
HADDR3
HADDR4
Recognizes one 16-bit address (HADDR1) and
the 16-bit broadcast address (HADDR2)
Recognizes one 8-bit address (HADDR1)
Figure 36-2. HDLC Address Recognition Example
36.5 Programming Model
The core configures each FCC to operate in the protocol specified in GFMR[MODE]. The HDLC
controller uses the same data structure as other modes. This data structure supports multibuffer operation
and address comparisons.
36.5.1 HDLC Command Set
Table 36-2 describes the transmit commands that apply to the HDLC controller.
Table 36-2. Transmit Commands
Command
Description
STOP TRANSMIT
After the hardware or software is reset and the channel is enabled in the FCC mode register, the
channel is in transmit enable mode and starts polling the first BD in the table every 256 transmit
clocks (immediately if FTODR[TOD] = 1). STOP TRANSMIT command disables the transmission of
frames on the transmit channel. If this command is received by the HDLC controller during frame
transmission, transmission is aborted after a maximum of 64 additional bits are sent and the transmit
FIFO buffer is flushed. The TBPTR is not advanced, no new BD is accessed, and no new frames
are sent for this channel. The transmitter sends an abort sequence consisting of 0x7F (if the
command was given during frame transmission) and begins sending flags or idles, as indicated by
the HDLC mode register. Note that if FPSMR[MFF] = 1, one or more small frames can be flushed
from the transmit FIFO buffer. The GRACEFUL STOP TRANSMIT command can be used to avoid this.
GRACEFUL STOP Used to stop transmission smoothly rather than abruptly, as performed by the regular STOP TRANSMIT
TRANSMIT
command. It stops transmission after the current frame finishes sending or immediately if no frame
is being sent. FCCE[GRA] is set once transmission has stopped. Then the HDLC transmit
parameters (including BDs) can be modified. The TBPTR points to the next TxBD in the table.
Transmission begins once the R bit of the next BD is set and the RESTART TRANSMIT command is
issued.
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Freescale Semiconductor
36-5
FCC HDLC Controller
Command
Table 36-2. Transmit Commands (continued)
Description
RESTART
TRANSMIT
Enables character transmission on the transmit channel. This command is expected by the HDLC
controller after a STOP TRANSMIT command, after a STOP TRANSMIT command is issued and the
channel in its FCC mode register is disabled, after a GRACEFUL STOP TRANSMIT command, or after a
transmitter error (underrun or CTS lost with no automatic frame retransmission). The HDLC
controller resumes sending from the current TBPTR in the channel TxBD table.
INIT TX
Initializes all transmit parameters in this serial channel parameter RAM to their reset state. This
command should only be issued when the transmitter is disabled. Notice that the INIT TX AND RX
PARAMETERS command can also be used to reset the transmit and receive parameters.
PARAMETERS
Table 36-3 describes the receive commands that apply to the HDLC controller.
Table 36-3. Receive Commands
Command
Description
ENTER HUNT
MODE
After the hardware or software is reset and the channel is enabled in the FCC mode register, the
channel is in receive enable mode and uses the first BD in the table. The ENTER HUNT MODE
command is generally used to force the HDLC receiver to abort reception of the current frame and
enter the hunt mode. In hunt mode, the HDLC controller continually scans the input data stream for
the flag sequence. After receiving the command, the current receive buffer is closed, the error status
flags and length field are cleared, RxBD[E] (the empty bit) is set, and the CRC calculation is reset.
Further frame reception uses the current RxBD.
INIT RX
Initializes all the receive parameters in this serial channel parameter RAM to their reset state and
should be issued only when the receiver is disabled. Notice that the INIT TX AND RX PARAMETERS
command resets both receive and transmit parameters.
PARAMETERS
36.5.2 HDLC Error Handling
The HDLC controller reports frame reception and transmission error conditions using the channel BDs,
error counters, and HDLC event register (FCCE). Table 36-4 describes HDLC transmission errors, which
are reported through the TxBD.
Table 36-4. HDLC Transmission Errors
Error
Description
Transmitter
Underrun
When this error occurs, the channel terminates buffer transmission, transmit an ABORT sequence
(a sequence which will generate CRC error on the frame), closes the buffer, sets the underrun (U)
bit in the BD, and generates the TXE interrupt if it is enabled. The channel resumes transmission
after receiving the RESTART TRANSMIT command.
CTS Lost during When this error occurs, the channel terminates buffer transmission, closes the buffer, sets
Frame
Transmission
TxBD[CT], and generates a TXE interrupt (if it is enabled). The channel resumes transmission after
receiving the RESTART TRANSMIT command.
Table 36-5 describes HDLC reception errors, which are reported through the RxBD.
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FCC HDLC Controller
Table 36-5. HDLC Reception Errors
Description
Error
Overrun Error
The HDLC controller maintains an internal FIFO buffer for receiving data. The CP begins
programming the SDMA channel and updating the CRC whenever data is received in the FIFO
buffer. When a receive FIFO overrun occurs, the channel writes the received data byte to the internal
FIFO buffer over the previously received byte. The previous byte and the frame status are lost. The
channel closes the buffer with RxBD[OV] set and generates the RXF interrupt if it is enabled. The
receiver then enters hunt mode. Even if the overrun occurs during a frame whose address is not
matched in the address recognition logic, an RxBD with data length two is opened to report the
overrun and the RXF interrupt is generated if it is enabled.
CD Lost During When this error occurs, the channel terminates frame reception, closes the buffer, sets RxBD[CD],
Frame
Reception
and generates the RXF interrupt if it is enabled. This error has highest priority. The rest of the frame
is lost and other errors are not checked in that frame. At this point, the receiver enters hunt mode. If
CD is Lost during the first 8 serial bits it will not be reported as CD Lost error and there will be no
indication of error.
Abort Sequence The HDLC controller detects an abort sequence when seven or more consecutive ones are
received. When this error occurs and the HDLC controller receives a frame, the channel closes the
buffer by setting RxBD[AB] and generates the RXF interrupt (if enabled). The channel also
increments the abort sequence counter. The CRC and nonoctet error status conditions are not
checked on aborted frames. The receiver then enters hunt mode. When an abort sequence is
received, the user is given no indication that an HDLC controller is not currently receiving a frame.
Nonoctet
Aligned Frame
When this error occurs, the channel writes the received data to the data buffer, closes the buffer,
sets the Rx nonoctet aligned frame bit RxBD[NO], and generates the RXF interrupt (if it is enabled).
The CRC error status should be disregarded on nonoctet frames. After a nonoctet aligned frame is
received, the receiver enters hunt mode. An immediate back-to-back frame is still received. The
nonoctet data portion may be derived from the last byte in the buffer by finding the least-significant
set bit, which marks the end of valid data as follows:
msb
lsb
0
Valid data
1
0
0
CRC Error
When this error occurs, the channel writes the received CRC to the data buffer, closes the buffer,
sets RxBD[CR], and generates the RXF interrupt (if it is enabled). The channel also increments the
CRC error counter. After receiving a frame with a CRC error, the receiver enters hunt mode. An
immediate back-to-back frame is still received. CRC checking cannot be disabled, but the CRC error
can be ignored if checking is not required.
36.6 HDLC Mode Register (FPSMR)
When an FCC is configured for HDLC mode, the FPSMR is used as the HDLC mode register, shown in
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
36-7
FCC HDLC Controller
0
3
4
5
6
8
9
10
15
Field
NOF
FSE MFF
—
TS
—
Reset
R/W
0000_0000_0000_0000
R/W
Addr
16
17
23
24
25
26
31
Field NBL
—
CRC
—
Reset
R/W
0000_0000_0000_0000
R/W
Addr
0x11306 (FPSMR1), 0x11326 (FPSMR2), 0x11326 (FPSMR3)
Figure 36-3. HDLC Mode Register (FPSMR)
1
Table 36-6. FPSMR Field Descriptions
Bits
Name
Description
0–3
NOF Number of flags. Minimum number of flags between or before frames (0–15 flags). If NOF = 0000,
no flags are inserted between the frames. Thus, for back-to-back frames, the closing flag of one
frame is immediately followed by the opening flag of the next frame.
4
5
FSE Flag sharing enable. This bit is valid only if GFMR[RTSM] is set.
0 Normal operation
1 If NOF = 0000, a single shared flag is transmitted between back-to-back frames. Other values of
NOF are decremented by 1 when FSE is set. This is useful in signaling system #7 applications.
MFF Multiple frames in FIFO. Setting MFF applies only when in RTS mode (GFMRx[RTSM] = 1).
0 Normal operation. The transmit FIFO buffer must never contain more than one HDLC frame. The
CTS lost status is reported accurately on a per-frame basis. The receiver is not affected by this
bit.
1 The transmit FIFO buffer can contain multiple frames, but lost CTS is not guaranteed to be
reported on the exact buffer/frame it occurred on. This option, however, can improve the
performance of HDLC transmissions for small back-to-back frames or if the user prefers to
strongly limit the number of flags sent between frames. MFF does not affect the receiver.
Refer to note 1 at the end of this table.
7–8
9
—
Reserved, should be cleared.
TS
Time stamp
0 Normal operation.
1 A 32-bit time stamp is added at the beginning of the receive BD data buffer, thus the buffer pointer
must be (32-byte aligned - 4). The BD’s data length does not include the time stamp. See
10–15
—
Reserved, should be cleared.
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FCC HDLC Controller
1
Table 36-6. FPSMR Field Descriptions (continued)
Description
Bits
Name
16
NBL Nibble mode enable
0 Nibble mode disabled (1 bit of data per clock). Note that at the end of the frame (after the closing
flag), RTS negates immediately after the active edge of TCLK.
1 Nibble mode enabled (4 bits of data per clock). The negation of of the RTS output signal is not
synchronized to the serial clock. The RTS is negated after the last nibble of the data and always
before the next edge of the serial clock. Note that at the end of the frame (after the closing flag),
RTS negates a maximum of 5 CPM clocks after the active edge of TCLK.
17–23
24-25
—
Reserved, should be cleared.
CRC CRC selection
00 16-bit CCITT-CRC (HDLC). X16 + X12 + X5 + 1
01 Reserved
10 32-bit CCITT-CRC (Ethernet and HDLC). X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 +
X8 + X7 + X5 + X4 + X2 + X1 +1
11 Reserved
26–31
—
Reserved, should be cleared.
1
When operating an FCC in HDLC nibble mode with the multiframe per FIFO bit off (FPSMR[MFF] = 0), the CPM might
lose synchronization with the FCC HDLC controller. As a result the HDLC controller will become stuck and stop
transmission. Therefore in HDLC nibble mode, FPSMR[MFF] must be set or the FCC must alternatively operate in
HDLC bit mode.
36.7 HDLC Receive Buffer Descriptor (RxBD)
example of the RxBD process.
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Freescale Semiconductor
36-9
FCC HDLC Controller
MRBLR = 32 Bytes for this FCC
Buffer
RxBD 0
E
0
L
F
Status
0
1
Address 1
Address 2
Length
Pointer
0x0020
Buffer Full
32-Bit Buffer Pointer
32 Bytes
Control Byte
29
Information
(I-Field) Bytes
RxBD 1
Buffer
E
0
L
F
Status
Length
1
0
Last I-Field Byte
CRC Byte 1
CRC Byte 2
0x0023
Buffer Closed
When Closing Flag
Received
Pointer
32-Bit Buffer Pointer
32 Bytes
Empty
RxBD 2
Buffer
E
0
L
1
F
1
AB
1
Status
Length
Address 1
Address 2
Control Byte
0x0003
32 Bytes
Abort was
Received after
Control Byte
Pointer
32-Bit Buffer Pointer
RxBD 3
Empty
Buffer
E
1
Status
Length
XXXX
32 Bytes
Empty
Buffer
Still Empty
Pointer
32-Bit Buffer Pointer
Stored in Rx Buffer
Stored in Rx Buffer
. . .
F
A
A
C
I
I
I
CR CR F
Line Idle
F
A
A
C
Abort/Idle
Two Frames
Received in HDLC
Unexpected Abort Present
Time
Occurs before
Closing Flag
Time
Legend:
F = Flag
A = Address Byte
C = Control Byte
I = Information Byte
CR = CRC Byte
Figure 36-4. FCC HDLC Receiving Using RxBDs
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Freescale Semiconductor
FCC HDLC Controller
Figure 36-5 shows the FCC HDLC RxBD.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Offset + 0
Offset + 2
Offset + 4
Offset + 6
E
—
W
I
L
F
CM
—
LG
NO
AB
CR
OV
CD
Data Length
Rx Data Buffer Pointer
Figure 36-5. FCC HDLC Receive Buffer Descriptor (RxBD)
Table 36-7 describes RxBD fields.
Table 36-7. RxBD field Descriptions
Description
Bits
Name
E
0
Empty
0 The buffer is full with received data or data reception stopped because of an error. The core can
read or write to any fields of this RxBD. The CP does not use this BD while E = 0.
1 The buffer associated with this BD is empty. This RxBD and its associated receive buffer are
owned by the CP. Once E is set, the core should not write any fields of this RxBD.
1
2
—
Reserved, should be cleared.
W
Wrap (final BD in table)
0 Not the last BD in the RxBD table.
1 Last BD in the RxBD table. After this buffer is used, the CP receives incoming data into the first
BD that RBASE points to in the table. The number of RxBDs in this table is programmable and is
determined only by the W bit and the overall space constraints of the dual-port RAM.
The RxBD table must contain more than one BD in HDLC mode.
3
4
I
Interrupt
0 The RXB bit is not set after this buffer is used, but RXF operation remains unaffected.
1 FCCE[RXB] or FCCE[RXF] is set when the HDLC controller uses this buffer. These two bits can
cause interrupts if they are enabled.
L
Last in frame. Set by the HDLC controller when this buffer is the last one in a frame. This implies the
reception of a closing flag or reception of an error, in which case one or more of the CD, OV, AB, and
LG bits are set. The HDLC controller writes the number of frame octets to the data length field.
0 Not the last buffer in a frame.
1 Last buffer in a frame.
5
6
F
First in frame. Set by the HDLC controller when this buffer is the first in a frame.
0 Not the first buffer in a frame.
1 First buffer in a frame.
CM
Continuous mode
0 Normal operation.
1 The E bit is not cleared by the CP after this BD is closed, allowing the associated data buffer to
be automatically overwritten the next time the CP accesses this BD. However, the E bit is cleared
if an error occurs during reception, regardless of the CM bit.
7–9
10
—
Reserved, should be cleared.
LG
Rx frame length violation. A frame length greater than the maximum defined for this channel is
recognized, and only the maximum-allowed number of bytes (MFLR) is written to the data buffer.
This event is not reported until the RxBD is closed, the RXF bit is set, and the closing flag is received.
The number of bytes received between flags is written to the data length field of this BD.
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Freescale Semiconductor
36-11
FCC HDLC Controller
Table 36-7. RxBD field Descriptions (continued)
Description
Bits
Name
11
NO
Rx nonoctet-aligned frame. Set when a received frame contains a number of bits not divisible by
eight.
12
13
AB
CR
Rx abort sequence. At least seven consecutive 1s are received during frame reception.
Rx CRC error. This frame contains a CRC error. Received CRC bytes are written to the receive
buffer.
14
15
OV
CD
Overrun. A receiver overrun occurs during frame reception.
Carrier detect lost. CD has negated during frame reception. This bit is valid only for NMSI mode.
The RxBD status bits are written by the HDLC controller after receiving the associated data buffer.
The remaining RxBD parameters are as follows:
•
Data length is the number of octets the CP writes into this BD’s data buffer. It is written by the CP
once the BD is closed. When this is the last BD in the frame (L = 1), this field contains the total
number of frame octets, including 2 or 4 bytes for CRC. The memory allocated for this buffer
should be no smaller than the MRBLR value.
•
Rx data buffer pointer. The receive buffer pointer, which always points to the first location of the
associated data buffer, resides in internal or external memory and must be divisible by 32 unless
36.8 HDLC Transmit Buffer Descriptor (TxBD)
Data is presented to the HDLC controller for transmission on an FCC channel by arranging it in buffers
referenced by the channel TxBD table. The HDLC controller confirms transmission (or indicates errors)
using the BDs to inform the core that the buffers have been serviced. Figure 36-6 shows the FCC HDLC
TxBD.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Offset + 0
Offset + 2
Offset + 4
Offset + 6
R
—
W
I
L
TC
CM
—
UN
CT
Data Length
Tx Data Buffer Pointer
Figure 36-6. FCC HDLC Transmit Buffer Descriptor (TxBD)
Table 36-8 describes HDLC TxBD fields.
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FCC HDLC Controller
Table 36-8. HDLC TxBD Field Descriptions
Description
Bits
Name
R
0
Ready
0 The buffer associated with this BD is not ready for transmission. The user can manipulate this BD
or its associated buffer. The CP clears R after the buffer has been sent or an error occurs.
1 The buffer is ready to be sent. The transmission may have begun, but it has not completed. The
user cannot set fields in this BD once R is set.
1
2
—
Reserved, should be cleared.
W
Wrap (final BD in table)
0 Not the last BD in the TxBD table.
1 Last BD in the TxBD table. After this buffer has been used, the CP sends data from the first BD
that TBASE points to in the table. The number of TxBDs in this table is determined only by the W
bit and the overall space constraints of the dual-port RAM.
3
I
Interrupt
0 No interrupt is generated after this buffer is serviced.
1 Either FCCE[TXB] or FCCE[TXE] is set when this buffer is serviced by the HDLC controller.
These bits can cause interrupts if they are enabled.
4
5
L
Last
0 Not the last buffer in the frame.
1 Last buffer in the current frame.
TC
Tx CRC.Valid only when the L bit is set. Otherwise, it is ignored.
0 Transmit the closing flag after the last data byte. This setting can be used to send a bad CRC after
the data for testing purposes.
1 Transmit the CRC sequence after the last data byte.
6
CM
Continuous mode
0 Normal operation.
1 The R bit is not cleared by the CP after this BD is closed, allowing the buffer to be retransmitted
automatically the next time the CP accesses this BD. However, the R bit is cleared if an error
occurs during transmission, regardless of the CM bit.
7–13
14
—
Reserved, should be cleared.
UN
Underrun. The HDLC controller encounters a transmitter underrun condition while sending the
buffer. The HDLC controller writes UN after sending the buffer.
15
CT
CTS lost. Set when CTS is lost during frame transmission in NMSI mode. If data from more than
one buffer is in the FIFO buffer when this error occurs, CT is set in the currently open TxBD. The
HDLC controller writes CT after sending the buffer.
The TxBD status bits are written by the HDLC controller after sending the associated data buffer.
The remaining TxBD parameters are as follows:
•
Data length is the number of bytes the HDLC controller should transmit from this data buffer; it is
never modified by the CP. The value of this field should be greater than zero.
•
Tx data buffer pointer. The transmit buffer pointer, which contains the address of the associated
data buffer, can be even or odd. The buffer can reside in internal or external memory. This value is
never modified by the CP.
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Freescale Semiconductor
36-13
FCC HDLC Controller
36.9 HDLC Event Register (FCCE)/Mask Register (FCCM)
The FCCE is used as the HDLC event register when the FCC operates as an HDLC controller. The FCCE
reports events recognized by the HDLC channel and generates interrupts. On recognition of an event, the
HDLC controller sets the corresponding FCCE bit. FCCE bits are cleared by writing ones; writing zeros
does not affect bit values. All unmasked bits must be cleared before the CP clears the internal interrupt
request.
Interrupts generated by the FCCE can be masked in the HDLC mask register (FCCM), which has the same
bit format as FCCE. If an FCCM bit = 1, the corresponding interrupt in the event register is enabled. If the
bit is 0, the interrupt is masked.
Figure 36-7 represents the FCC/FCCM.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Field
Reset
R/W
—
GRA
—
TXE
RXF
BSY
TXB
RXB
0000_0000_0000_0000
R/W
Addr
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Field
Reset
R/W
—
FLG IDL
—
0000_0000_0000_0000
R/W
Addr
0x11312 (FCCE1), 0x11332 (FCCE2), 0x11352 (FCCE3)/
0x11316 (FCCM1), 0x11336 (FCCM2), 0x11356 (FCCM3)
Figure 36-7. HDLC Event Register (FCCE)/Mask Register (FCCM)
Table 36-9 describes FCCE/FCCM fields.
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FCC HDLC Controller
Table 36-9. FCCE/FCCM Field Descriptions
Description
Bits
Name
0–7
8
—
Reserved, should be cleared.
GRA Graceful stop complete. A graceful stop, which was initiated by the GRACEFUL STOP TRANSMIT
command, is now complete. GRA is set as soon as the transmitter finishes transmitting any frame
that is in progress when the command was issued. It is set immediately if no frame is in progress
when the command is issued.
9–10
11
—
Reserved, should be cleared.
TXE Tx error. An error (CTS lost or underrun) occurs on the transmitter channel.
12
RXF Rx frame. A complete frame is received on the HDLC channel. This bit is set no sooner than two
clocks after receipt of the last bit of the closing flag.
13
14
BSY Busy condition. A frame is received and discarded due to a lack of buffers.
TXB Transmit buffer. Enabled by setting TxBD[I]. A buffer is sent on the HDLC channel. TXB is set no
sooner than when the last bit of the closing flag begins its transmission if the buffer is the last one
in the frame. Otherwise, TXB is set after the last byte of the buffer is written to the transmit FIFO
buffer.
15
RXB Receive buffer. When RXB = 1, a buffer for which the I bit is set in the corresponding BD was filled,
regardless if the end of a frame was completed in it.
16–21
22
—
Reserved, should be cleared.
FLG Flag status changed. The HDLC controller stops or starts receiving HDLC flags. The real-time status
23
IDL
Idle sequence status changed. A change in the status of the serial line is detected on the HDLC line.
24–31
—
Reserved, should be cleared.
Figure 36-8 shows interrupts that can be generated in the HDLC protocol.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
36-15
FCC HDLC Controller
Frame
Received by HDLC
Stored in Rx Buffer
CR CR F
Time
F
F
A
A
C
I
I
I
RXD
CD
Line Idle
Line Idle
HDLC FCCE
Events
CD
IDL FLG FLG
RXB
RXFFLG IDL
FLG
CD
Notes:
1. RXB event assumes receive buffers are 6 bytes each.
2. The second IDL event occurs after 15 ones are received in a row.
3. The FLG interrupts show the beginning and end of flag reception.
4. The FLG interrupt at the end of the frame may precede the RXF interrupt due to receive FIFO latency.
5. The CD event must be programmed in the parallel I/O port, not in the FCC itself.
6. F = flag, A = address byte, C = control byte, I = information byte, and CR = CRC byte
Stored in Tx Buffer
Frame
Transmitted by HDLC
TXD
RTS
CTS
Line Idle
F
F
A
A
C CR CR F
Line Idle
HDLC FCCE
Events
CT
TXB
CT
Notes:
1. TXB event shown assumes all three bytes were put into a single buffer.
2. Example shows one additional opening flag. This is programmable.
3. The CT event must be programmed in the parallel I/O port, not in the FCC itself.
Figure 36-8. HDLC Interrupt Event Example
36.10 FCC Status Register (FCCS)
The FCCS register, shown in Figure 36-9, allows the user to monitor real-time status conditions on the
RXD line. The real-time status of the CTS and CD signals are part of the parallel I/O port; see Chapter 40,
0
1
2
3
4
5
6
7
Field
Reset
R/W
—
FG
—
ID
0000_0000
R
Addr
Figure 36-9. FCC Status Register (FCCS)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
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Freescale Semiconductor
FCC HDLC Controller
Table 36-10 describes FCCS bits.
Table 36-10. FCCS Register Field Descriptions
Bits
Name
Description
0–4
5
—
Reserved, should be cleared.
FG
Flags. While FG is cleared, each time a new bit is received the most recently received 8 bits are
examined to see if a flag is present. FG is set as soon as an HDLC flag (0x7E) is received on the
line. Once FG is set, it remains set at least 8 bit times while the next 8 bits of input data are
examined. If another flag occurs, FG stays set for at least another eight bits. Otherwise, FG is
cleared and the search begins again.
• 0HDLC flags are not currently being received.
• 1HDLC flags are currently being received.
6
7
—
ID
Reserved, should be cleared.
Idle status. ID is set when the RXD signal is a logic one for 15 or more consecutive bit times; it is
cleared after a logic zero is received.
• 0The line is busy.
• 1The line is idle.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
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36-17
FCC HDLC Controller
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
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Freescale Semiconductor
Chapter 37
FCC Transparent Controller
The FCC transparent controller functions as a high-speed serial-to-parallel and parallel-to-serial converter.
Transparent mode provides a clear channel on which the FCC performs no bit-level
manipulation—implementing higher-level protocols would require software. Transparent mode is also
referred to as a totally transparent or promiscuous operation.
Basic applications for an FCC in transparent mode include the following:
•
•
For data, such as voice, moving serially without the need for protocol processing
For board-level applications, such as chip-to-chip communications, requiring a serial-to-parallel
and parallel-to-serial conversion
•
For applications requiring the switching of data paths without altering the protocol encoding itself,
such as a multiplexer in which data from a high-speed TDM serial stream is divided into multiple
low-speed data streams
An FCC transmitter and receiver can be programmed in transparent mode independently. Setting
GFMRx[TTx] enables the transparent transmitter; setting GFMRx[TRx] enables the transparent receiver.
Both bits must be set for full-duplex transparent operation. If only one bit is set, the other half of the FCC
operates with the protocol programmed in GFMRx[MODE]. This allows loopback modes to transfer data
from one memory location to another (using DMA) while the data is converted to a specific serial format.
However, the Ethernet and ATM controllers cannot be split in this way. See Section 29.2, “General FCC
The FCC in transparent mode can work with the TSA or NMSI and support modem lines using the
general-purpose I/O signals. The data can be transmitted and received with msb or lsb first in each octet.
The FCC consists of separate transmit and receive sections whose operations are asynchronous with the
core and can either be synchronous or asynchronous with respect to the other FCCs. Each clock can be
supplied from the internal BRG bank or external signals.
37.1 Features
The following is a list of the transparent controller’s important features:
•
•
Flexible data buffers
Automatic SYNC detection on receive
— 16-bit pattern
— 8-bit pattern
— Automatic sync (always synchronized)
— External sync signal support
CRCs can optionally be transmitted and received
•
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
37-1
FCC Transparent Controller
•
•
Reverse data mode
Another protocol can be performed on the FCC’s other half (transmitter or receiver) during
transparent mode
•
External BD table
37.2 Transparent Channel Operation
The transparent transmitter and receiver operates in the same way as the HDLC controller of the FCC (see
1. The FPSMR does not affect the transparent controller, only the GFMR does.
operation of the transparent receiver.
3. Transmitter synchronization has to be achieved using CTS before the transmitter begins sending;
37.3 Achieving Synchronization in Transparent Mode
Once the FCC transmitter is enabled for transparent operation in the GFMR, the TxBD is prepared for the
FCC, and the transmit FIFO is preloaded by the SDMA channel, transmit synchronization must be
established before data can be sent.
Similarly, once the FCC receiver is enabled for transparent operation in the GFMR and the RxBD is made
empty for the FCC, receive synchronization must occur before data can be received. The synchronization
process gives the user bit-level control of when the transmission and reception begins. The methods for
this are as follows:
•
•
•
An in-line synchronization pattern
External synchronization signals
Automatic sync
37.3.1 In-Line Synchronization Pattern
The transparent channel can be programmed to transmit and receive a synchronization pattern if
0
7
8
15
Field
Field
8-Bit Sync Pattern
—
16-Bit Sync Pattern
(Second Byte)
(First Byte)
Figure 37-1. In-Line Synchronization Pattern
The receiver synchronizes on the synchronization pattern located in the FDSR. For instance, if an 8-bit
SYNC is selected, reception begins as soon as these eight bits are received, beginning with the first bit
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
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Freescale Semiconductor
FCC Transparent Controller
following the 8-bit SYNC. This effectively links the transmitter synchronization to the receiver
synchronization.
37.3.2 External Synchronization Signals
If GFMR[SYNL] = 00, an external signal is used to begin the sequence. CTS is used for the transmitter
and CD is used for the receiver; these signals share the following sampling options.
•
The pulse/envelope option determines whether CD or CTS need to be asserted only once to begin
reception/transmission or whether they must be asserted and stay that way for the duration of the
transparent frame. This option is controlled by the CDP and CTSP bits of the GFMR. If the user
expects a continuous stream of data without interruption, the pulse option should be used.
However, if the user needs to identify frames of transparent data, the envelope mode of the these
signals should be used. Note that the first bit of a frame is transmitted as zero every time RTS is
asserted before CTS is asserted (GFMR[CTSS] = 1); subsequent data bits are sent accurately.
Similarly, if CTS is in pulse mode (GFMR[CTSP] = 1), only the first frame is affected. If CTS is
not in pulse mode (GFMR[CTSP] = 0), every frame is affected separately. Note that if NRZI
encoding is used (GFMR[TENC]=01), RTS must be asserted before CTS, or else the first bit of the
frame might be corrupted.
•
The sampling option determines the delay between CD and CTS being asserted and the resulting
action by the FCC. These signals can be assumed to be asynchronous to the data and then internally
synchronized by the FCC, or they can be assumed to be synchronous to the data giving faster
operation. This option allows the RTS of one FCC to be connected to the CD of another FCC (on
another PowerQUICC II) and to have the data synchronized and bit aligned. It is also an option to
link the transmitter synchronization to the receiver synchronization.
When working with the FCC receiver in envelope mode, RTS should be asserted for at least 3 clock cycles
between frames. Otherwise, the receiver cannot recognize the start of a new frame. Diagrams for the
37.3.3 Transparent Synchronization Example
Figure 37-2 shows an example of synchronization using external signals.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
37-3
FCC Transparent Controller
PowerQUICC II (A)
PowerQUICC II (B)
TXD
RTS
RXD
CD
BRGOx
RXD
CLKx
TXD
CD
RTS
CLKx
BRGOx
BRGOx
(Output is CLKx Input)
TXD
(Output is RXD Input)
Last Bit of Frame Data
First Bit of Frame Data
RTS
or CRC
(Output is CD Input)
TxBD[L] = 1 Causes Negation of RTS
CD Lost Condition Terminates Reception of Frame
Notes:
1
Each PowerQUICC II generates its own transmit clocks. If the transmit and receive clocks are the same, one can
generate transmit and receive clocks for the other PowerQUICC II. For example, CLKx on PowerQUICC II (B) could
be used to clock the transmitter and receiver
2
3
CTS should be configured as always asserted in the parallel I/O port or connected to ground externally.
The required GSMR configurations are DIAG= 00, CTSS=1, CTSP is a don’t care, CDS=1, CDP=0, TTX=1, and
TRX=1. REVD and TCRC are application-dependent.
4
The transparent frame contains a CRC if TxBD[TC] is set.
Figure 37-2. Sending Transparent Frames between PowerQUICC IIs
PowerQUICC II(A) and PowerQUICC II(B) exchange transparent frames and synchronize each other
using RTS and CD. However, CTS is not required because transmission begins at any time. Thus, RTS is
connected directly to the other PowerQUICC II’s CD. GFMR[SYNL] is not used and transmission and
reception from each PowerQUICC II are independent.
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Freescale Semiconductor
Chapter 38
Serial Peripheral Interface (SPI)
The serial peripheral interface (SPI) allows the PowerQUICC II to exchange data between other
PowerQUICC II chips, the MPC860, the MC68360, the MC68302, the M68HC11 and M68HC05
microcontroller families, and peripheral devices such as EEPROMs, real-time clocks, A/D converters, and
ISDN devices.
The SPI is a full-duplex, synchronous, character-oriented channel that supports a four-wire interface
(receive, transmit, clock and slave select). The SPI block consists of transmitter and receiver sections, an
independent baud-rate generator, and a control unit. The transmitter and receiver sections use the same
clock, which is derived from the SPI baud rate generator in master mode and generated externally in slave
mode. During an SPI transfer, data is sent and received simultaneously.
Because the SPI receiver and transmitter are double-buffered, as shown in Figure 38-1, the effective FIFO
size (latency) is 2 characters. The SPI’s msb is shifted out first. When the SPI is disabled in the SPI mode
register (SPMODE[EN] = 0), it consumes little power.
60x Bus
Peripheral Bus
SPI Mode Register
Transmit_Register
Receive_Register
Counter
Shift_Register
TxD
RxD
IN_CLK
Pins Interface
SPIBRG
BRGCLK
SPISEL
SPIMOSI
SPIMISO
SPICLK
Figure 38-1. SPI Block Diagram
38.1 Features
The following is a list of the SPI’s main features:
•
Four-signal interface (SPIMOSI, SPIMISO, SPICLK, and SPISEL) multiplexed with port D
signals
•
Full-duplex operation
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
38-1
Serial Peripheral Interface (SPI)
•
•
•
•
•
•
Works with data characters from 4 to 16 bits long
Supports back-to-back character transmission and reception
Master or slave SPI modes supported
Multimaster environment support
Continuous transfer mode for automatic scanning of a peripheral
Supports maximum clock rates of 25 in master mode and 50 MHz in slave mode, assuming a
100-MHz system clock
•
•
•
•
Independent programmable baud rate generator
Programmable clock phase and polarity
Open-drain outputs support multimaster configuration
Local loopback capability for testing
38.2 SPI Clocking and Signal Functions
The SPI can be configured as a slave or as a master in single- or multiple-master environments. The master
SPI generates the transfer clock SPICLK using the SPI baud rate generator (BRG). The SPI BRG takes its
input from BRGCLK, which is generated in the PowerQUICC II clock synthesizer.
SPICLK is a gated clock, active only during data transfers. Four combinations of SPICLK phase and
polarity can be configured with SPMODE[CI, CP]. SPI signals can also be configured as open-drain to
support a multimaster configuration in which a shared SPI signal is driven by the PowerQUICC II or an
external SPI device.
The SPI master-in slave-out SPIMISO signal acts as an input for master devices and as an output for slave
devices. Conversely, the master-out slave-in SPIMOSI signal is an output for master devices and an input
for slave devices. The dual functionality of these signals allows the SPIs in a multimaster environment to
communicate with one another using a common hardware configuration.
•
When the SPI is a master, SPICLK is the clock output signal that shifts received data in from
SPIMISO and transmitted data out to SPIMOSI. SPI masters must output a slave select signal to
enable SPI slave devices by using a separate general-purpose I/O signal. Assertion of an SPI’s
SPISEL while it is master causes an error.
•
When the SPI is a slave, SPICLK is the clock input that shifts received data in from SPIMOSI and
transmitted data out through SPIMISO. SPISEL is the enable input to the SPI slave. In a
multimaster environment, SPISEL (always an input) is used to detect an error when more than one
master is operating.
multiplexed with port D[16–19] signals, respectively. They are configured as SPI signals through the port
D signal assignment register (PDPAR) and the port D data direction register (PDDIR), specifically by
setting PDPAR[DDn] and PDDIR[DRn].
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Freescale Semiconductor
Serial Peripheral Interface (SPI)
38.3 Configuring the SPI Controller
The SPI can be programmed to work in a single- or multiple-master environment. This section describes
SPI master and slave operation in a single-master configuration and then discusses the multi-master
environment.
38.3.1 The SPI as a Master Device
In master mode, the SPI sends a message to the slave peripheral, which sends back a simultaneous reply.
A single master PowerQUICC II with multiple slaves can use general-purpose parallel I/O signals to
selectively enable slaves, as shown in Figure 38-2. To eliminate the multimaster error in a single-master
environment, the master’s SPISEL input can be forced inactive by selecting port D[19] for general-purpose
I/O (PDPAR[DD19] = 0).
PowerQUICC II
Slave 0
SPIMOSI
SPIMISO
SPICLK
SPIMOSI
SPIMISO
SPICLK
SPISEL
Master SPI
Slave 1
SPIMOSI
SPIMISO
SPICLK
SPISEL
The SPISEL
decoder can be
either internal or
external logic.
Slave 2
SPIMOSI
SPIMISO
SPICLK
SPISEL
Figure 38-2. Single-Master/Multi-Slave Configuration
To start exchanging data, the core writes the data to be sent into a buffer, configures a TxBD with TxBD[R]
set, and configures one or more RxBDs. The core then sets SPCOM[STR] in the SPI command register to
start sending data, which starts once the SDMA channel loads the Tx FIFO with data.
The SPI then generates programmable clock pulses on SPICLK for each character and simultaneously
shifts Tx data out on SPIMOSI and Rx data in on SPIMISO. Received data is written into a Rx buffer using
the next available RxBD. The SPI keeps sending and receiving characters until the whole buffer is sent or
an error occurs. The CP then clears TxBD[R] and RxBD[E] and issues a maskable interrupt to the interrupt
controller in the SIU.
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38-3
Serial Peripheral Interface (SPI)
When multiple TxBDs are ready, TxBD[L] determines whether the SPI keeps transmitting without
SPCOM[STR] being set again. If the current TxBD[L] is cleared, the next TxBD is processed after data
from the current buffer is sent. Typically there is no delay on SPIMOSI between buffers. If the current
TxBD[L] is set, sending stops after the current buffer is sent. In addition, the RxBD is closed after
transmission stops, even if the Rx buffer is not full; therefore, Rx buffers need not be the same length as
Tx buffers.
38.3.2 The SPI as a Slave Device
In slave mode, the SPI receives messages from an SPI master and sends a simultaneous reply. The slave’s
SPISEL must be asserted before Rx clocks are recognized; once SPISEL is asserted, SPICLK becomes an
input from the master to the slave. SPICLK can be any frequency from DC to BRGCLK/2 (12.5 MHz for
a 25-MHz system).
To prepare for data transfers, the slave’s core writes data to be sent into a buffer, configures a TxBD with
TxBD[R] set, and configures one or more RxBDs. The core then sets SPCOM[STR] to activate the SPI.
Once SPISEL is asserted, the slave shifts data out from SPIMISO and in through SPIMOSI. A maskable
interrupt is issued when a full buffer finishes receiving and sending or after an error. The SPI uses
successive RxBDs in the table to continue reception until it runs out of Rx buffers or SPISEL is negated.
Transmission continues until no more data is available or SPISEL is negated. If it is negated before all data
is sent, it stops but the TxBD stays open. Transmission continues once SPISEL is reasserted and SPICLK
begins toggling. After the characters in the buffer are sent, the SPI sends ones as long as SPISEL remains
asserted.
38.3.3 The SPI in Multimaster Operation
The SPI can operate in a multimaster environment in which SPI devices are connected to the same bus. In
this configuration, the SPIMOSI, SPIMISO, and SPICLK signals of all SPIs are shared; the SPISEL inputs
are connected separately, as shown in Figure 38-3. Only one SPI device can act as master at a time—all
others must be slaves. When an SPI is configured as a master and its SPISEL input is asserted, a
multimaster error occurs because more than one SPI device is a bus master. The SPI sets SPIE[MME] in
the SPI event register and a maskable interrupt is issued to the core. It also disables SPI operation and the
output drivers of SPI signals. The core must clear SPMODE[EN] before the SPI is used again. After
correcting the problems, clear SPIE[MME] and reenable the SPI.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
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Freescale Semiconductor
Serial Peripheral Interface (SPI)
PowerQUICC II
SPI #0
SPIMOSI
SPIMISO
SPICLK
SPISEL
SELOUT1
SELOUT2
SELOUT3
PowerQUICC II
SPI #1
SPIMOSI
SPIMISO
SPICLK
SPISEL
SELOUT0
SELOUT2
SELOUT3
PowerQUICC II
SPI #2
SPIMOSI
SPIMISO
SPICLK
SPISEL
SELOUT0
SELOUT1
SELOUT3
PowerQUICC II
SPI #3
SPIMOSI
SPIMISO
SPICLK
SPISEL
SELOUT0
SELOUT1
SELOUT2
Notes:
• All signals are open-drain
• For a system with more than two masters, SPISEL and SPIE[MME] do not detect all possible conflicts
• It is the responsibility of software to arbitrate for the SPI bus (with token passing, for example)
• SELOUTx signals are implemented in software with general-purpose I/O signals
Figure 38-3. Multimaster Configuration
The maximum sustained data rate that the SPI supports is SYSTEMCLK/50. However, the SPI can transfer
a single character at much higher rates—SYSTEMCLK/4 in master mode and SYSTEMCLK/2 in slave
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38-5
Serial Peripheral Interface (SPI)
mode. Gaps should be inserted between multiple characters to keep from exceeding the maximum
sustained data rate.
38.4 Programming the SPI Registers
The following sections describe the registers used in configuring and operating the SPI.
38.4.1 SPI Mode Register (SPMODE)
The SPI mode register (SPMODE), shown in Figure 38-4, controls both the SPI operation mode and clock
source.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Field
Reset
R/W
—
LOOP CI
CP DIV16 REV M/S EN
LEN
PM
0000_00
—
0_0000_0000
R/W
Figure 38-4. SPMODE—SPI Mode Register
Addr
Table 38-1 describes the SPMODE fields.
Table 38-1. SPMODE Field Descriptions
Bits Name
Description
0
1
—
Reserved, should be cleared.
LOOP Loop mode. Enables local loopback operation.
0 Normal operation.
1 Loopback mode. The transmitter output is internally connected to the receiver input. The receiver
and transmitter operate normally, except that received data is ignored.
2
3
4
CI
0 The inactive state of SPICLK is low.
1 The inactive state of SPICLK is high.
0 SPICLK starts toggling at the middle of the data transfer.
1 SPICLK starts toggling at the beginning of the data transfer.
DIV16 Divide by 16. Selects the clock source for the SPI baud rate generator when configured as an SPI
master. In slave mode, SPICLK is the clock source.
0 BRGCLK is the input to the SPI BRG.
1 BRGCLK/16 is the input to the SPI BRG.
5
6
REV Reverse data. Determines the receive and transmit character bit order.
0 Reverse data—lsb of the character sent and received first.
1 Normal operation—msb of the character sent and received first.
M/S Master/slave. Selects master or slave mode.
0 The SPI is a slave.
1 The SPI is a master.
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Serial Peripheral Interface (SPI)
Table 38-1. SPMODE Field Descriptions (continued)
Description
Bits Name
7
EN Enable SPI. Do not change other SPMODE bits when EN is set.
0 The SPI is disabled. The SPI is in a reset state and consumes minimal power. The SPI BRG is not
functioning and the input clock is disabled.
1 The SPI is enabled. Configure SPIMOSI, SPIMISO, SPICLK, and SPISEL to connect to the SPI as
8–11 LEN Character length in bits per character. If the character length is not greater than a byte, every byte in
memory holds (LEN+1) valid bits. If the character length is greater than a byte, every half-word holds
0000–0010 Reserved, causes erratic behavior.
0011 4-bit characters
…
1111 16-bit characters
12–15 PM Prescale modulus select. Specifies the divide ratio of the prescale divider in the SPI clock generator.
BRGCLK is divided by 4 * ([PM0–PM3] + 1), a range from 4 to 64. The clock has a 50% duty cycle.
SPICLK
SPICLK
(CI = 0)
(CI = 1)
SPIMOSI
(From Master)
msb
lsb
lsb
SPIMISO
(From Slave)
msb
Q
SPISEL
NOTE: Q = Undefined Signal.
Figure 38-5. SPI Transfer Format with SPMODE[CP] = 0
Figure 38-6 shows the SPI transfer format in which SPICLK starts toggling at the beginning of the transfer
(SPMODE[CP] = 1).
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38-7
Serial Peripheral Interface (SPI)
SPICLK
SPICLK
(CI = 0)
(CI = 1)
SPIMOSI
(From Master)
msb
msb
lsb
SPIMISO
(From Slave)
Q
lsb
SPISEL
NOTE: Q = Undefined Signal.
Figure 38-6. SPI Transfer Format with SPMODE[CP] = 1
38.4.1.1 SPI Examples with Different SPMODE[LEN] Values
The examples below show how SPMODE[LEN] is used to determine character length. To help map the
Table 38-2. Example Conventions
Convention
Description
g–v
x
Binary symbols
Deleted bit
1
__
Original byte boundary
Original 4-bit boundary.
1
_
1
Both __ and _ are used to aid readability.
Once the data string image is determined, it is always transmitted byte by byte with the lsb of the
most-significant byte sent first. For all examples below, assume the memory contains the following binary
image:
msb
ghij_klmn__opqr_stuv
lsb
Example 1
with LEN=4 (data size=5), the following data is selected:
msb
with REV=0, the data string image is:
msb j_klmn__r_stuv
xxxj_klmn__xxxr_stuv
lsb
lsb
the order of the string appearing on the line, a byte at a time is:
first nmlk_j__vuts_r last
with REV=1,the string has each byte reversed, and the data string image is:
msb nmlk_j__vuts_r lsb
the order of the string appearing on the line, one byte at a time is:
first j_klmn__r_stuv last
Example 2
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Freescale Semiconductor
Serial Peripheral Interface (SPI)
with LEN=7 (data size=8), the following data is selected:
msb
the data string is selected:
msb ghij_klmn__opqr_stuv
ghij_klmn__opqr_stuv
lsb
lsb
with REV=0, the string transmitted, a byte at a time with lsb first is:
first nmlk_jihg__vuts_rqpo last
with REV=1, the string is byte reversed and transmitted, a byte at a time, with lsb
first:
first
ghij_klmn__opqr_stuv
last
Example 3
with LEN=0xC (data size=13), the following data is selected:
msb
the data string selected is:
msb r_stuv__ghij_klmn
ghij_klmn__xxxr_stuv
lsb
lsb
with REV=0, the string transmitted, a byte at a time with lsb first is:
first nmlk_jihg__vuts_r last
with REV=1, the string is half-word reversed:
msb nmlk_jihg__vuts_r lsb
and transmitted a byte at a time with lsb first:
first r_stuv_ghij_klmn last
38.4.2 SPI Event/Mask Registers (SPIE/SPIM)
The SPI event register (SPIE) generates interrupts and reports events recognized by the SPI. When an
event is recognized, the SPI sets the corresponding SPIE bit. Clear SPIE bits by writing a 1—writing 0 has
no effect. Setting a bit in the SPI mask register (SPIM) enables and clearing a bit masks the corresponding
interrupt. Unmasked SPIE bits must be cleared before the CP clears internal interrupt requests. Figure 38-7
shows both registers.
0
1
2
3
4
5
6
7
Field
Reset
R/W
—
MME
TXE
—
BSY
TXB
RXB
0000_0000
R/W
Figure 38-7. SPIE/SPIM—SPI Event/Mask Registers
Addr
Table 38-3 describes the SPIE/SPIM fields.
Table 38-3. SPIE/SPIM Field Descriptions
Bits
Name
Description
0–1
2
—
Reserved, should be cleared.
MME Multimaster error. Set when SPISEL is asserted externally while the SPI is in master mode.
TXE Tx error. Set when an error occurs during transmission.
3
4
—
Reserved, should be cleared.
5
BSY Busy. Set after the first character is received but discarded because no Rx buffer is available.
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Serial Peripheral Interface (SPI)
Table 38-3. SPIE/SPIM Field Descriptions
Description
Bits
Name
6
TXB Tx buffer. Set when the Tx data of the last character in the buffer is written to the Tx FIFO. Wait two
character times to be sure data is completely sent over the transmit signal.
7
RXB Rx buffer. Set after the last character is written to the Rx buffer and the BD is closed.
38.4.3 SPI Command Register (SPCOM)
0
1
7
Field
Reset
R/W
STR
—
0000_0000
Write Only
Addr
Figure 38-8. SPCOM—SPI Command Register
Table 38-4 describes the SPCOM fields.
Table 38-4. SPCOM Field Descriptions
Bits
Name
Description
0
STR Start transmit. For an SPI master, setting STR causes the SPI to start transferring data to and from
the Tx/Rx buffers if they are prepared. For a slave, setting STR when the SPI is idle causes it to load
the Tx data register from the SPI Tx buffer and start sending with the next SPICLK after SPISEL is
asserted. STR is cleared automatically after one system clock cycle.
1–7
—
Reserved and should be cleared.
38.5 SPI Parameter RAM
The SPI parameter RAM area is similar to the SCC general-purpose parameter RAM. The CP accesses the
SPI parameter table using a user-programmed pointer (SPI_BASE) located in the parameter RAM; see
Section 14.5.2, “Parameter RAM.” The SPI parameter table can be placed at any 64-byte aligned address
in the dual-port RAM’s general-purpose area (banks 1–8, 11 and 12). Some parameter values must be
user-initialized before the SPI is enabled; the CP initializes the others. Once initialized, parameter RAM
values do not usually need to be accessed. They should be changed only when the SPI is inactive.
Table 38-5 shows the memory map of the SPI parameter RAM.
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Serial Peripheral Interface (SPI)
Table 38-5. SPI Parameter RAM Memory Map
Description
1
Offset
Name Width
0x00
0x02
RBASE Hword Rx/Tx BD table base address. Indicate where the BD tables begin in the dual-port RAM.
Setting Rx/TxBD[W] in the last BD in each BD table determines how many BDs are
TBASE Hword
allocated for the Tx and Rx sections of the SPI. Initialize RBASE/TBASE before enabling
the SPI. Furthermore, do not configure BD tables of the SPI to overlap any other active
controller’s parameter RAM.
RBASE and TBASE should be divisible by eight.
0x04
0x05
RFCR
TFCR
Byte Rx/Tx function code registers. The function code registers contain the transaction
specification associated with SDMA channel accesses to external memory. See
Byte
0x06
MRBLR Hword Maximum receive buffer length. The SPI has one MRBLR entry to define the maximum
number of bytes the PowerQUICC II writes to a Rx buffer before moving to the next buffer.
The PowerQUICC II can write fewer bytes than MRBLR if an error or end-of-frame
occurs, but never exceeds the MRBLR value. User-supplied buffers should be no smaller
than MRBLR.
Tx buffers are unaffected by MRBLR and can have varying lengths; the number of bytes
to be sent is programmed in TxBD[Data Length].
MRBLR is not intended to be changed while the SPI is operating. However it can be
changed in a single bus cycle with one 16-bit move (not two 8-bit bus cycles
back-to-back). The change takes effect when the CP moves control to the next RxBD.
To guarantee the exact RxBD on which the change occurs, change MRBLR only while
the SPI receiver is disabled. MRBLR should be greater than zero; it should be an even
number if the character length of the data exceeds 8 bits.
2
0x08 RSTATE Word Rx internal state. Reserved for CP use.
2
0x0C
—
Word The Rx internal data pointer is updated by the SDMA channels to show the next
address in the buffer to be accessed.
0x10
RBPTR Hword RxBD pointer. Points to the current Rx BD being processed or to the next BD to be
serviced when idle. After a reset or when the end of the BD table is reached, the CP
initializes RBPTR to the RBASE value. Most applications should not modify RBPTR, but
it can be updated when the receiver is disabled or when no Rx buffer is in use.
2
0x12
—
Hword The Rx internal byte count is a down-count value that is initialized with the MRBLR
value and decremented with every byte the SDMA channels write.
2
0x14
0x18
0x1C
—
Word Rx temp. Reserved for CP use.
2
TSTATE Word Tx internal state. Reserved for CP use.
2
—
Word The Tx internal data pointer is updated by the SDMA channels to show the next address
in the buffer to be accessed.
0x20
TBPTR Hword TxBD pointer. Points to the current Tx BD during frame transmission or the next BD to be
processed when idle. After reset or when the end of the Tx BD table is reached, the CP
initializes TBPTR to the TBASE value. Most applications do not need to modify TBPTR,
but it can be updated when the transmitter is disabled or when no Tx buffer is in use.
2
0x22
—
Hword The Tx internal byte count is a down-count value initialized with TxBD[Data Length] and
decremented with every byte read by the SDMA channels.
2
0x24
0x34
—
—
Word Tx temp. Reserved for CP use.
Word SDMA temp.
1
From the pointer value programmed in SPI_BASE at IMMR + 0x89FC.
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Serial Peripheral Interface (SPI)
2
Normally, these parameters need not be accessed. They are listed to help experienced users in debugging.
38.5.1 Receive/Transmit Function Code Registers (RFCR/TFCR)
Figure 38-9 shows the fields in the receive/transmit function code registers (RFCR/TFCR).
0
1
2
3
4
5
6
7
Field
Reset
R/W
—
GBL
BO
0000_0000
R/W
TC2
DTB
—
Addr
SPI Base + 04 (RFCR)/SPI Base + 05 (TFCR)
Figure 38-9. RFCR/TFCR—Function Code Registers
Table 38-6 describes the RFCR/TFCR fields.
Table 38-6. RFCR/TFCR Field Descriptions
Bits
Name
—
Description
0–1
2
Reserved, should be cleared.
GBL Global access bit
0 Disable memory snooping
1 Enable memory snooping
3–4
BO
Byte ordering. Set BO to select the required byte ordering for the buffer. If BO is changed on-the-fly,
it takes effect at the beginning of the next frame or BD.
00 True little-endian. Note this mode can only be used with 32-bit port size memory.
01 Munged little-endian
1x Big-endian
5
6
TC2 Transfer code 2. Contains the transfer code value of TC[2], used during this SDMA channel memory
access. TC[0–1] is driven with a 0b11 to identify this SDMA channel access as a DMA-type access.
DTB Data bus indicator.
0 Use 60x bus for SDMA operation.
1 Use local bus for SDMA operation.
7
—
Reserved, should be cleared.
38.6 SPI Commands
Table 38-7 lists transmit/receive commands sent to the CP command register (CPCR).
Table 38-7. SPI Commands
Command
Description
INIT TX
PARAMETERS
Initializes all transmit parameters in the parameter RAM to their reset state and should be issued
only when the transmitter is disabled. The INIT TX AND RX PARAMETERS command can also be used
to reset both the Tx and Rx parameters.
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Serial Peripheral Interface (SPI)
Table 38-7. SPI Commands (continued)
Description
Command
CLOSE RXBD
Forces the SPI controller to close the current RxBD and use the next BD for subsequently received
data. If the controller is not receiving data, no action is taken. Use this command to extract data from
a partially full buffer.
INIT RX
Initializes all receive parameters in the parameter RAM to their reset state. Should be issued only
when the receiver is disabled. The INIT TX AND RX PARAMETERS command can also be used to reset
both the Tx and Rx parameters.
PARAMETERS
38.7 The SPI Buffer Descriptor (BD) Table
The tables have the same basic configuration as for the SCCs and SMCs and form circular queues that
determine the order buffers are transferred. The CP uses BDs to confirm reception and transmission or to
indicate error conditions so that the core knows buffers have been serviced. The buffers themselves can be
placed in external memory or in any unused parameter area of the dual-port RAM.
Dual-Port RAM
External Memory
TxBD Table
Frame Status
Tx Buffer
Data Length
Tx Buffer
Rx Buffer
Buffer Pointer
Pointer to SPI
TxBD Table
RxBD Table
Pointer to SPI
RxBD Table
Frame Status
Data Length
Buffer Pointer
Figure 38-10. SPI Memory Structure
38.7.1 SPI Buffer Descriptors (BDs)
Receive and transmit BDs report information about each buffer transferred and whether a maskable
interrupt should be generated. Each 64-bit BD, shown in Figure 38-11 and Figure 38-12, has the following
structure:
•
The half word at offset + 0 contains status and control bits. The CP updates the status bits after the
buffer is sent or received.
•
The half word at offset + 2 contains the data length (in bytes) that is sent or received.
— For an RxBD, this is the number of octets the CP writes into this RxBD’s buffer once the BD
closes. The CP updates this field after the received data is placed into the buffer. Memory
allocated for this buffer should be no smaller than MRBLR.
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Serial Peripheral Interface (SPI)
— For a TxBD, this is the number of octets the CP should transmit from its buffer. Normally, this
value should be greater than zero. If the character length is more than 8 bits, the data length
should be even. For example, to send three characters of 8-bit data, 1 start, and 1 stop, the data
length field should be initialized to 3. However, to send three characters of 9-bit data, the data
length field should be initialized to 6 since the three 9-bit data fields occupy three half-words
in memory. The CP never modifies this field.
•
The word at offset + 4 points to the beginning of the buffer.
— For an RxBD, the pointer must be even and can point to internal or external memory.
— For a TxBD, the pointer can be even or odd, unless the character exceeds 8 bits, for which it
must be even. The buffer can be in internal or external memory.
38.7.1.1 SPI Receive BD (RxBD)
The CP uses RxBDs to report on each received buffer. It closes the current buffer, generates a maskable
interrupt, and starts receiving data in the next buffer once the current buffer is full. The CP also closes the
buffer when the SPI is configured as a slave and SPISEL is negated, indicating that reception stopped. The
core should write RxBD bits before the SPI is enabled. The format of an RxBD is shown in Figure 38-11.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Offset + 0
Offset + 2
Offset + 4
Offset + 6
E
—
W
I
L
—
CM
—
OV
ME
Data Length
Rx Buffer Pointer
Figure 38-11. SPI RxBD
Table 38-8 describes the RxBD status and control fields.
Table 38-8. SPI RxBD Status and Control Field Descriptions
Bits
Name
Description
0
E
Empty.
0 The buffer is full or stopped receiving because of an error. The core can examine or write to any
fields of this RxBD, but the CP does not use this BD while E = 0.
1 The buffer is empty or reception is in progress. The CP owns this RxBD and its buffer. Once E is
set, the core should not write any fields of this RxBD.
1
2
—
Reserved, should be cleared.
W
Wrap (last BD in table).
0 Not the last BD in the RxBD table.
1 Last BD in the RxBD table. After this buffer is used, the CP receives incoming data using the BD
pointed to by RBASE (top of the table). The number of BDs in this table is determined only by the
W bit and overall space constraints of the dual-port RAM.
3
I
Interrupt.
0 No interrupt is generated after this buffer is filled.
1 SPIE[RXB] is set when this buffer is full, indicating the need for the core to process the buffer.
SPIE[RXB] causes an interrupt if not masked.
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Table 38-8. SPI RxBD Status and Control Field Descriptions (continued)
Bits
Name
Description
4
L
Last. Updated by the SPI when the buffer is closed because SPISEL was negated (slave mode
only). Otherwise, RxBD[ME] is set. The SPI updates L after received data is placed in the buffer.
0 This buffer does not contain the last character of the message.
1 This buffer contains the last character of the message.
5
6
—
Reserved, should be cleared.
CM
Continuous mode. Master mode only; in slave mode, CM should be cleared.
0 Normal operation.
1 The CP does not clear RxBD[E] after this BD is closed; the buffer is overwritten when the CP next
accesses this BD. This allows continuous reception from an SPI slave into one buffer for
autoscanning of a serial A/D peripheral with no core overhead.
7–13
14
—
Reserved, should be cleared.
OV
Overrun. Set when a receiver overrun occurs during reception (slave mode only). The SPI updates
OV after the received data is placed in the buffer.
15
ME
Multimaster error. Set when this buffer is closed because SPISEL was asserted when the SPI was
in master mode. Indicates a synchronization problem between multiple masters on the SPI bus. The
SPI updates ME after the received data is placed in the buffer.
38.7.1.2 SPI Transmit BD (TxBD)
Data to be sent with the SPI is sent to the CP by arranging it in buffers referenced by TxBDs in the TxBD
table. TxBD fields should be prepared before data is sent. The format of an TxBD is shown in
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Offset + 0
Offset + 2
Offset + 4
Offset + 6
R
—
W
I
L
—
CM
—
UN ME
Data Length
Tx Buffer Pointer
Figure 38-12. SPI TxBD
Table 38-9 describes the TxBD status and control fields.
Table 38-9. SPI TxBD Status and Control Field Descriptions
Bits
Name
R
Description
0
Ready.
0 The buffer is not ready to be sent. This BD or its buffer can be modified. The CP clears R (unless
RxBD[CM] is set) after the buffer is sent (unless RxBD[CM] is set) or an error occurs.
1 The buffer is ready for transmission or is being sent. The BD cannot be modified once R is set.
1
—
Reserved, should be cleared.
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Serial Peripheral Interface (SPI)
Table 38-9. SPI TxBD Status and Control Field Descriptions (continued)
Description
Bits
Name
W
2
Wrap (last BD in TxBD table).
0 Not the last BD in the table.
1 Last BD in the table. After this buffer is used, the CP receives incoming data using the BD pointed
to by TBASE (top of the table). The number of BDs in this table is determined only by the W bit
and overall space constraints of the dual-port RAM.
3
4
I
Interrupt.
0 No interrupt is generated after this buffer is processed.
1 SPIE[TXB] or SPIE[TXE] are set when this buffer is processed and causes interrupts if not
masked.
L
Last.
0 This buffer does not contain the last character of the message.
1 This buffer contains the last character of the message.
5
6
—
Reserved, should be cleared.
CM
Continuous mode. Valid only when the SPI is in master mode. In slave mode, it should be cleared.
0 Normal operation.
1 The CP does not clear TxBD[R] after this BD is closed, allowing the buffer to be resent
automatically when the CP next accesses this BD.
7–13
14
—
Reserved, should be cleared.
UN
Underrun. Indicates that the SPI encountered a transmitter underrun condition while sending the
buffer. This error occurs only when the SPI is in slave mode. The SPI updates UN after it sends the
buffer.
15
ME
Multimaster error. Indicates that this buffer is closed because SPISEL was asserted when the SPI
was in master mode. A synchronization problem occurred between devices on the SPI bus. The SPI
updates ME after sending the buffer.
38.8 SPI Master Programming Example
The following sequence initializes the SPI to run at a high speed in master mode:
1. Configure port D to enable SPIMISO, SPIMOSI, SPICLK and SPISEL.
2. Configure a parallel I/O signal to operate as the SPI select output signal if needed.
3. In address 0x89FC, assign a pointer to the SPI parameter RAM.
4. Write RBASE and TBASE in the SPI parameter RAM to point to the RxBD and TxBD tables in
the dual-port RAM. Assuming one RxBD followed by one TxBD at the beginning of the dual-port
RAM, write RBASE with 0x0000 and TBASE with 0x0008.
5. Write RFCR and TFCR with 0x10 for normal operation.
6. Write MRBLR with the maximum number of bytes per Rx buffer. For this case, assume 16 bytes,
so MRBLR = 0x0010.
7. Initialize the RxBD. Assume the Rx buffer is at 0x0000_1000 in main memory. Write 0xB000 to
RxBD[Status and Control], 0x0000 to RxBD[Data Length] (optional), and 0x0000_1000 to
RxBD[Buffer Pointer].
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Serial Peripheral Interface (SPI)
8. Initialize the TxBD. Assume the Tx buffer is at 0x0000_2000 in main memory and contains five
8-bit characters. Write 0xB800 to TxBD[Status and Control], 0x0005 to TxBD[Data Length], and
0x0000_2000 to TxBD[Buffer Pointer].
9. Execute the INIT RX AND TX PARAMETERS command by writing 0x2541_0000 to CPCR.
10. Write 0xFF to SPIE to clear any previous events.
11. Write 0x37 to SPIM to enable all possible SPI interrupts.
12. Write 0x0370 to SPMODE to enable normal operation (not loopback), master mode, SPI enabled,
8-bit characters, and the fastest speed possible.
13. Set SPCOM[STR] to start the transfer.
After 5 bytes are sent, the TxBD is closed. Additionally, the Rx buffer is closed after 5 bytes are received
because TxBD[L] is set.
38.9 SPI Slave Programming Example
The following is an example initialization sequence to follow when the SPI is in slave mode. It is very
similar to the SPI master example, except that SPISEL is used instead of a general-purpose I/O signal (as
1. Enable SPIMISO, SPIMOSI, SPICLK, and SPISEL.
2. In address 0x89FC, assign a pointer to the SPI parameter RAM.
3. Assuming one RxBD at the beginning of the dual-port RAM followed by one TxBD, write RBASE
with 0x0000 and TBASE with 0x0008 in the SPI parameter RAM.
4. Write RFCR and TFCR with 0x10 for normal operation.
5. Program MRBLR = 0x0010 for 16 bytes, the maximum number of bytes per buffer.
6. Initialize the RxBD. Assume the Rx buffer is at 0x0000_1000 in main memory. Write 0xB000 to
RxBD[Status and Control], 0x0000 to RxBD[Data Length] (optional), and 0x0000_1000 to
RxBD[Buffer Pointer].
7. Initialize the TxBD. Assume the Tx buffer is at 0x0000_2000 in main memory and contains five
8-bit characters. Write 0xB800 to TxBD[Status and Control], 0x0005 to TxBD[Data Length], and
0x0000_2000 to TxBD[Buffer Pointer].
8. Execute the INIT RX AND TX PARAMETERS command by writing 0x2541_0000 to CPCR.
9. Write 0xFF to SPIE to clear any previous events.
10. Write 0x37 to SPIM to enable all SPI interrupts.
11. Set SPMODE to 0x0170 to enable normal operation (not loopback), slave mode, SPI enabled, and
8-bit characters. BRG speed is ignored in slave mode.
12. Set SPCOM[STR] to enable the SPI to be ready once the master begins the transfer.
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Serial Peripheral Interface (SPI)
NOTE
If the master sends 3 bytes and negates SPISEL, the RxBD is closed but the
TxBD remains open. If the master sends 5 or more bytes, the TxBD is closed
after the fifth byte. If the master sends 16 bytes and negates SPISEL, the
RxBD is closed without triggering an out-of-buffers error. If the master
sends more than 16 bytes, the RxBD is closed (full) and an out-of-buffers
error occurs after the 17th byte is received.
38.10 Handling Interrupts in the SPI
The following sequence should be followed to handle interrupts in the SPI:
1. Once an interrupt occurs, read SPIE to determine the interrupt source. Normally, SPIE bits should
be cleared at this time.
2. Process the TxBD to reuse it and the RxBD to extract the data from it. To transmit another buffer,
simply set TxBD[R], RxBD[E], and SPCOM[STR].
3. Execute an rfi instruction.
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Chapter 39
2
I C Controller
The inter-integrated circuit (I2C®) controller lets the PowerQUICC II exchange data with other I2C
devices, such as microcontrollers, EEPROMs, real-time clock devices, A/D converters, and LCD displays.
The I2C controller uses a synchronous, multimaster bus that can connect several integrated circuits on a
board. It uses two signals—serial data (SDA) and serial clock (SCL)—to carry information between the
integrated circuits connected to it.
As shown in Figure 39-1, the I2C controller consists of transmit and receive sections, an independent
baud-rate generator (BRG), and a control unit. The transmit and receive sections use the same clock, which
is derived from the I2C BRG when in master mode and generated externally when in slave mode. Wait
states are inserted during a data transfer if SCL is held low by a slave device. In the middle of a data
transfer, the master I2C controller recognizes the need for wait states by monitoring SCL. However, the
I2C controller has no automatic time-out mechanism if the slave device does not release SCL; therefore,
software should monitor how long SCL stays low to generate bus timeouts.
Peripheral Bus
60x Bus
Rx Data Register
Tx Data Register
Shift Register
Mode Register
Shift Register
SDA
Control
Baud-Rate Generator
SCL
2
Figure 39-1. I C Controller Block Diagram
The I2C receiver and transmitter are double-buffered, which corresponds to an effective two-character
FIFO latency. In normal operation, the transmitter shifts the msb (bit 0) out first. When the I2C is not
enabled in the I2C mode register (I2MOD[EN] = 0), it consumes little power.
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I2C Controller
39.1 Features
The following is a list of the I2C controller’s main features:
•
•
•
•
•
Two-signal interface (SDA and SCL)
Support for master and slave I2C operation
Multiple-master environment support
Continuous transfer mode for automatic scanning of a peripheral
Supports a maximum clock rate of 2,080 KHz (with a CPM utilization of 25%), assuming a
100-MHz system clock.
•
•
•
•
Independent, programmable baud-rate generator
Supports 7-bit I2C addressing
Open-drain output signals allow multiple master configuration
Local loopback capability for testing
39.2 I2C Controller Clocking and Signal Functions
The I2C controller can be configured as a master or slave for the serial channel. As a master, the controller’s
BRG provides the transfer clock. The I2C BRG takes its input from the BRG clock (BRGCLK), which is
SDA and SCL are bidirectional signals connected to a positive supply voltage through an external pull-up
resistor. When the bus is free, both signals are pulled high. The general I2C master/slave configuration is
DD
V
Master
Slave
SCL
SDA
SCL
SDA
(EEPROM, for example)
DD
V
2
Figure 39-2. I C Master/Slave General Configuration
When the I2C controller is master, the SCL clock output, taken directly from the I2C BRG, shifts receive
data in and transmit data out through SDA. The transmitter arbitrates for the bus during transmission and
aborts if it loses arbitration. When the I2C controller is a slave, the SCL clock input shifts data in and out
through SDA. The SCL frequency can range from DC to BRGCLK/48.
39.3 I2C Controller Transfers
To initiate a transfer, the master I2C controller sends a message specifying a read or write request to an I2C
slave. The first byte of the message consists of a 7-bit slave port address and a R/W request bit. Note that
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I2C Controller
because the R/W request follows the slave port address in the I2C bus specification, the R/W request bit
must be placed in the lsb (bit 7) unless operating in reverse data mode; see Section 39.4.1, “I C Mode
To write to a slave, the master sends a write request (R/W = 0) along with either the target slave’s address
or a general call (broadcast) address of all zeros, followed by the data to be written. To read from a slave,
the master sends a read request (R/W = 1) and the target slave’s address. When the target slave
acknowledges the read request, the transfer direction is reversed, and the master receives the slave’s
transmit buffer(s). If the receiver (master or slave) does not acknowledge each byte transfer in the ninth
bit frame, the transmitter signals a transmission error event (I2ER[TXE]). An I2C transfer timing diagram
Start Condition
Stop Condition
SCL
SDA
1
2
3
4
5
6
7
8
9
A
C
K
Data Byte
2
Figure 39-3. I C Transfer Timing
Select master or slave mode for the controller using the I2C command register (I2COM[M/S]). Set the
master’s start bit, I2COM[STR], to begin a transfer; setting a slave’s I2COM[STR] activates the slave to
wait for a transfer request from a master.
If a master or slave transmitter’s current TxBD[L] is set, transmission stops once the buffer is sent; that is,
I2COM[STR] must be set again to reactivate transfers. If TxBD[L] is zero, once the current buffer is sent,
the controller begins processing the next TxBD without waiting for I2COM[STR] to be set again.
The following sections further detail the transfer process.
39.3.1 I2C Master Write (Slave Read)
If the PowerQUICC II is the master, prepare the transmit buffers and BDs before initiating a write.
Initialize the first transmit data byte with the slave address and write request (R/W = 0).
If the PowerQUICC II is the slave target of the write, prepare receive buffers and BDs to await the master’s
S
S
T
O
P
T
A
R
T
A
C
W K
A
C
K
Data Byte
SDA
Device Address
Note: Data and ACK are repeated n times.
2
Figure 39-4. I C Master Write Timing
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I2C Controller
A master write occurs as follows:
1. The master core sets I2COM[STR]. The transfer starts when the SDMA channel loads the Tx FIFO
with data and the I2C bus is not busy.
2. The I2C master generates a start condition—a high-to-low transition on SDA while SCL is
high—and the transfer clock SCL pulses for each bit shifted out on SDA. If the master transmitter
detects a multiple-master collision (by sensing a ‘0’ on SDA while sending a ‘1’), transmission
stops and the channel reverts to slave mode. A maskable interrupt is sent to the master’s core so
software can try to retransmit later.
3. The slave acknowledges each byte and writes to its current receive buffer until a new start or stop
condition is detected.
4. After sending each byte, the master monitors the acknowledge indication. If the slave receiver fails
to acknowledge a byte, transmission stops and the master generates a stop condition—a
low-to-high transition on SDA while SCL is high.
39.3.2 I2C Loopback Testing
When in master mode, an I2C controller supports loopback operation for master write requests. The master
I2C controller simply issues a write request directed to its own address (programmed in I2ADD). The
master’s receiver monitors the transmission and reads the transmitted data into its receive buffer. Loopback
operation requires no special register programming.
39.3.3 I2C Master Read (Slave Write)
Before initiating a master read with the PowerQUICC II, prepare a transmit buffer of sizen+1 bytes, where
n is the number of bytes to be read from the slave. The first transmit byte should be initialized to the slave
address with R/W = 1. The next n transmit bytes are used strictly for timing and can be left uninitialized.
Configure suitable receive buffers and BDs to receive the slave’s transmission.
If the PowerQUICC II is the slave target of the read, prepare the I2C transmit buffers and BDs and activate
N
O
S
T
A
R
T
S
T
O
P
A
C
K
A
C
K
R
SDA
Device Address
Data Byte
Note: After the nth data byte, the master does not acknowledge the slave.
2
Figure 39-5. I C Master Read Timing
A master read occurs as follows:
1. Set the master’s I2COM[STR] to initiate the read. The transfer starts when the SDMA channel
loads the transmit FIFO with data and the I2C bus is not busy.
2. The slave detects a start condition on SDA and SCL.
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I2C Controller
3. After the first byte is shifted in, the slave compares the received data to its slave address. If the slave
is an PowerQUICC II, the address is programmed in its I2C address register (I2ADD).
— If a match is found, the slave acknowledges the received byte and begins transmitting on the
clock pulse immediately following the acknowledge.
— If a match is found but the slave is not ready, the read request is not acknowledged and the
transaction is aborted. If the slave is an PowerQUICC II, a maskable transmission error
interrupt is triggered to allow software to prepare data for transmission on the next try.
— If a mismatch occurs, the slave ignores the message and searches for a new start condition.
4. The master acknowledges each byte sent as long as an overrun does not occur. If the master
receiver fails to acknowledge a byte, the slave aborts transmission. For a slave PowerQUICC II,
the abort generates a maskable interrupt. A maskable interrupt is also issued after a complete buffer
is sent or after an error. If an underrun occurs, the PowerQUICC II slave sends ones until a stop
condition is detected.
39.3.4 I2C Multi-Master Considerations
The I2C controller supports a multi-master configuration, in which the I2C controller must alternate
between master and slave modes. The I2C controller supports this by implementing I2C master arbitration
in hardware. However, due to the nature of the I2C bus and the implementation of the I2C controller, certain
software considerations must be made.
A PowerQUICC II I2C controller attempting a master read request could simultaneously be targeted for an
external master write (slave read). Both operations trigger the controller’s I2CER[RXB] event, but only
one operation wins the bus arbitration. To determine which operation caused the interrupt, software must
verify that its transmit operation actually completed before assuming that the received data is the result of
its read operation.
Problems could also arise if the PowerQUICC II's I2C controller master sets up a transmit buffer and BD
for a write request, but then is the target of a read request from another master. Without software
precautions, the I2C controller responds to the other master with the transmit buffer originally intended for
its own write request. To avoid this situation, a higher-level handshake protocol must be used. For
example, a master, before reading a slave, writes the slave with a description of the requested data (which
register should be read, for example). This operation is typical with many I2C devices.
In addition, it is not recommended to enable the PowerQUICC II’s I2C controller while another I2C master
is executing transactions on the bus. The PowerQUICC II’s I2C controller should wait for the bus to
become idle.
The PowerQUICC II’s I2C controller assumes that other I2C devices on the bus closely conform to the I2C
specification. Unexpected behavior can occur if the PowerQUICC II I2C controller is connected with
devices which operate outside the specification. For example, a slave device which acknowledges a master
write with two SCL pulses instead of one (total of 10 SCL pulses), can cause wrong behavior of the
PowerQUICC I2C controller on its next transaction.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
39-5
I2C Controller
39.4 I2C Registers
2
The following sections describe the I C registers.
39.4.1 I2C Mode Register (I2MOD)
2
0
1
2
3
4
5
6
7
Field
Reset
R/W
—
REVD
GCD
FLT
PDIV
EN
0000_0000
R/W
Addr
2
Figure 39-6. I C Mode Register (I2MOD)
Table 39-1 describes I2MOD bit functions.
Table 39-1. II2MOD Field Descriptions
Bits
Name
Description
0–1
2
—
Reserved and should be cleared.
REVD Reverse data. Determines the Rx and Tx character bit order.
0 Normal operation. The msb (bit 0) of a character is transferred first.
1 Reverse data. the lsb (bit 7) of a character is transferred first.
Note: Clearing REVD is strongly recommended to ensure consistent bit ordering across devices.
3
4
GCD General call disable. Determines whether the receiver acknowledges a general call address.
0 General call address is enabled.
1 General call address is disabled.
2
FLT
Clock filter. Determines if the I C input clock SCL is filtered to prevent spikes in a noisy environment.
0 SCL is not filtered.
1 SCL is filtered by a digital filter.
2
5–6
PDIV Predivider. Selects the clock division factor before it is input into the I C BRG. The clock source for
2
00 BRGCLK/32
01 BRGCLK/16
10 BRGCLK/8
11 BRGCLK/4
Note: To both save power and reduce noise susceptibility, select the PDIV with the largest division
factor (slowest clock) that still meets performance requirements.
2
7
EN
Enable I C operation.
2
2
0 I C is disabled. The I C is in a reset state and consumes minimal power.
1 I C is enabled. Do not change other I2MOD bits when EN is set.
2
39.4.2 I2C Address Register (I2ADD)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
39-6
Freescale Semiconductor
I2C Controller
0
6
7
Field
Reset
R/W
SAD
Undefined
—
R/W
Addr
2
Figure 39-7. I C Address Register (I2ADD)
Table 39-2 describes I2ADD fields.
Table 39-2. I2ADD Field Descriptions
Bits
Name
Description
2
0–6
7
SAD Slave address 0–6. Holds the slave address for the I C port.
—
Reserved and should be cleared.
39.4.3 I2C Baud Rate Generator Register (I2BRG)
0
7
Field
Reset
R/W
DIV
1111_1111
R/W
Addr
2
Figure 39-8. I C Baud Rate Generator Register (I2BRG)
Table 39-3 describes I2BRG fields.
Table 39-3. I2BRG Field Descriptions
Bits
Name
Description
2
0–7
DIV
Division ratio 0–7. Specifies the divide ratio of the BRG divider in the I C clock generator. The output
of the prescaler is divided by 2 * ([DIV0–DIV7] + 3 + (2 * I2MOD[FLT])) and the clock has a 50% duty
cycle. DIV must be programmed to a minimum value of 3 if the digital filter is disabled
(I2MOD[FLT] = 0) and 6 if it is enabled (I2MOD[FLT] = 1) .
39.4.4 I2C Event/Mask Registers (I2CER/I2CMR)
The I2C event register (I2CER) is used to generate interrupts and report events. When an event is
recognized, the I2C controller sets the corresponding I2CER bit. I2CER bits are cleared by writing ones;
writing zeros has no effect. Setting a bit in the I2C mask register (I2CMR) enables and clearing a bit masks
the corresponding interrupt. Unmasked I2CER bits must be cleared before the CP clears internal interrupt
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
39-7
I2C Controller
0
2
3
4
5
6
7
Field
Reset
R/W
—
TXE
—
BSY
TXB
RXB
0000_0000
R/W
Addr
2
Figure 39-9. I C Event/Mask Registers (I2CER/I2CMR)
Table 39-4 describes the I2CER/I2CMR fields.
Table 39-4. I2CER/I2CMR Field Descriptions
Bits
Name
Description
0–2
3
—
Reserved and should be cleared.
TXE Tx error. Set when an error occurs during transmission.
Reserved and should be cleared.
4
—
5
BSY Busy. Set after the first character is received but discarded because no Rx buffer is available.
6
TXB Tx buffer. Set when the Tx data of the last character in the buffer is written to the Tx FIFO. Two
character times must elapse to guarantee that all data has been sent.
7
RXB Rx buffer. Set after the last character is written to the Rx buffer and the RxBD is closed.
39.4.5 I2C Command Register (I2COM)
The I2C command register, shown in Figure 39-10, is used to start I2C transfers and to select master or
slave mode.
0
1
2
3
4
5
6
7
Field
Reset
R/W
STR
—
M/S
0000_0000
R/W
Addr
2
Figure 39-10. I C Command Register (I2COM)
Table 39-5 describes I2COM fields.
Table 39-5. I2COM Field Descriptions
Bits
Name
Description
2
0
STR Start transmit. In master mode, setting STR causes the I C controller to start sending data from the
2
2
I C Tx buffers if they are ready. In slave mode, setting STR when the I C controller is idle causes it
to load the Tx data register from the I C Tx buffer and start sending when it receives an address
2
byte that matches the slave address with R/W = 1. STR is always read as a 0.
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Freescale Semiconductor
I2C Controller
Table 39-5. I2COM Field Descriptions
Description
Bits
Name
1–6
7
—
Reserved and should be cleared.
2
M/S Master/slave. Configures the I C controller to operate as a master or a slave.
2
0 I C is a slave.
2
1 I C is a master.
39.5 I2C Parameter RAM
The I2C controller parameter table is used for the general I2C parameters and is similar to the SCC
general-purpose parameter RAM. The CP accesses the I2C parameter table using a user-programmed
parameter table can be placed at any 64-byte aligned address in the dual-port RAM’s general-purpose area
(banks 1–8, 11 and 12). The user must initialize certain parameter RAM values before the I2C is enabled;
the CP initializes the other values. Software usually does not access parameter RAM entries once they are
initialized; they should be changed only when the I2C is inactive.
2
Table 39-6 shows the I C parameter memory map.
2
Table 39-6. I C Parameter RAM Memory Map
1
Offset
Name
Width
Description
0x00
0x02
RBASE Hword Rx/TxBD table base address. Indicate where the BD tables begin in the dual-port RAM.
Setting Rx/TxBD[W] in the last BD in each BD table determines how many BDs are
TBASE
Hword
2
allocated for the Tx and Rx sections of the I C. Initialize RBASE/TBASE before
2
2
enabling the I C. Furthermore, do not configure BD tables of the I C to overlap any
other active controller’s parameter RAM. RBASE and TBASE should be divisible by
eight.
0x04
0x05
RFCR
TFCR
Byte Rx/Tx function code registers. The function code registers contain the transaction
specification associated with SDMA channel accesses to external memory. See
Byte
0x06
MRBLR Hword Maximum receive buffer length. Defines the maximum number of bytes the
PowerQUICC II writes to a Rx buffer before moving to the next buffer. The
PowerQUICC II writes fewer bytes to the buffer than the MRBLR value if an error or
end-of-frame occurs. Buffers should not be smaller than MRBLR.
Tx buffers are unaffected by MRBLR and can vary in length; the number of bytes to be
sent is specified in TxBD[Data Length].
2
MRBLR is not intended to be changed while the I C is operating. However it can be
changed in a single bus cycle with one 16-bit move (not two 8-bit bus cycles
back-to-back). The change takes effect when the CP moves control to the next RxBD.
To guarantee the exact RxBD on which the change occurs, change MRBLR only while
2
the I C receiver is disabled. MRBLR should be greater than zero; it should be an even
number if the character length of the data exceeds 8 bits.
2
0x08
0x0C
RSTATE
RPTR
Word Rx internal state. Reserved for CP use.
2
Word Rx internal data pointer is updated by the SDMA channels to show the next address
in the buffer to be accessed.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
39-9
I2C Controller
2
Table 39-6. I C Parameter RAM Memory Map (continued)
1
Offset
Name
Width Description
0x10
RBPTR Hword RxBD pointer. Points to the next descriptor the receiver transfers data to when it is in
2
an idle state or to the current descriptor during frame processing for each I C channel.
After a reset or when the end of the descriptor table is reached, the CP initializes
RBPTR to the value in RBASE. Most applications should not write RBPTR, but it can
be modified when the receiver is disabled or when no receive buffer is used.
2
0x12
RCOUNT Hword Rx internal byte count is a down-count value that is initialized with the MRBLR value
and decremented with every byte the SDMA channels write.
2
0x14
0x18
0x1C
RTEMP
TSTATE
TPTR
Word Rx temp. Reserved for CP use.
2
Word Tx internal state. Reserved for CP use.
2
Word Tx internal data pointer is updated by the SDMA channels to show the next address
in the buffer to be accessed.
0x20
TBPTR
Hword TxBD pointer. Points to the next descriptor that the transmitter transfers data from when
it is in an idle state or to the current descriptor during frame transmission. After a reset
or when the end of the descriptor table is reached, the CP initializes TBPTR to the value
in TBASE.Most applications should not write TBPTR, but it can be modified when the
transmitter is disabled or when no transmit buffer is used.
2
0x22
TCOUNT Hword Tx internal byte count is a down-count value initialized with TxBD[Data Length] and
decremented with every byte read by the SDMA channels.
2
0x24
0x34
TTEMP
Word Tx temp. Reserved for CP use.
2
SDMATMP Word SDMA temp. Reserved for CP use.
1
From the pointer value programmed in I2C_BASE at IMMR + 0x8AFC.
Normally, these parameters need not be accessed.
2
Figure 39-11 shows the RFCR/TFCR bit fields.
0
1
2
3
4
5
6
7
Field
Reset
R/W
GBL
BO
0000_0000
R/W
TC2
DTB
—
Addr
I2C_BASE + 04 (RFCR)/I2C_BASE + 05 (TFCR)
2
Figure 39-11. I C Function Code Registers (RFCR/TFCR)
Table 39-7 describes the RFCR/TFCR bit fields.
Table 39-7. RFCR/TFCR Field Descriptions
Bits
Name
Description
0–1
2
—
Reserved, should be cleared.
GBL Global access bit
0 Disable memory snooping
0 Enable memory snooping
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Freescale Semiconductor
I2C Controller
Table 39-7. RFCR/TFCR Field Descriptions
Description
Bits
Name
BO
3–4
Byte ordering. Selects the required byte ordering for the buffer. If BO is changed on-the-fly, it takes
effect at the beginning of the next frame or BD.
00 True little-endian. Note this mode can only be used with 32-bit port size memory.
01 Big-endian
1x Munged little-endian
5
6
TC2 Transfer code 2. Contains the transfer code value of TC[2], used during this SDMA channel memory
access. TC[0–1] is driven with a 0b11 to identify this SDMA channel access as a DMA-type access.
DTB Data bus indicator.
0 Use 60x bus for SDMA operation.
1 Use local bus for SDMA operation.
7
—
Reserved, should be cleared.
39.6 I2C Commands
2
(CPCR).
2
Table 39-8. I C Transmit/Receive Commands
Command
Description
INIT TX
Initializes all transmit parameters in the parameter RAM to their reset state. Should be issued only when
PARAMETERS the transmitter is disabled. The INIT TX AND RX PARAMETERS command can also be used to reset both
the Tx and Rx parameters.
2
CLOSE RXBD Forces the I C controller to close the current Rx BD and use the next BD for subsequently received
data. If the controller is not receiving data, no action is taken. Use this command to extract data from a
partially full buffer.
INIT RX
Initializes all receive parameters in the parameter RAM to their reset state. Should be issued only when
PARAMETERS the receiver is disabled. The INIT TX AND RX PARAMETERS command can also be used to reset both the
Tx and Rx parameters.
39.7 The I2C Buffer Descriptor (BD) Table
in dual-port RAM. The tables have the same basic configuration as for the SCCs and SMCs and form
circular queues that determine the order buffers are transferred. The CP uses BDs to confirm reception and
transmission or to indicate error conditions so that the core knows buffers have been serviced. The buffers
themselves can be placed in external memory or in any unused parameter area of the dual-port RAM.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
39-11
I2C Controller
Dual-Port RAM
Tx Buffer
External Memory
TxBD Table
Status and Control
Data Length
Tx Buffer
Rx Buffer
Buffer Pointer
I2C TxBD Table
I2C RxBD Table
RxBD Table
Status and Control
Data Length
I2C RxBD Table Pointer
(RBASE)
Buffer Pointer
I2C TxBD Table Pointer
(TBASE)
2
Figure 39-12. I C Memory Structure
39.7.1 I2C Buffer Descriptors (BDs)
Receive and transmit buffer descriptors report information about each buffer transferred and whether a
maskable interrupt should be generated. Each 64-bit BD, shown in Figure 39-13 and Figure 39-14, has the
following structure:
•
The half word at offset + 0 contains status and control bits. The CP updates the status bits after the
buffer is sent or received.
•
The half word at offset + 2 contains the data length (in bytes) that is sent or received.
— For an RxBD, this is the number of octets the CP writes into this RxBD’s buffer once the
descriptor closes. The CP updates this field after the received data is placed into the associated
buffer. Memory allocated for this buffer should be no smaller than MRBLR.
— For a TxBD, this is the number of octets the CP should transmit from its buffer. Normally, this
value should be greater than zero. The CP never modifies this field.
•
The word at offset + 4 points to the beginning of the buffer.
— For an RxBD, the pointer must be even and can point to internal or external memory.
— For a TxBD, the pointer can be even or odd. The buffer can reside in internal or external
memory.
39.7.1.1 I2C Receive Buffer Descriptor (RxBD)
Using RxBDs, the CP reports on each buffer received, closes the current buffer, generates a maskable
interrupt, and starts receiving data in the next buffer when the current one is full. It closes the buffer when
a stop or start condition is found on the I2C bus or when an overrun error occurs. The core should write
RxBD bits before the I2C controller is enabled.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
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Freescale Semiconductor
I2C Controller
0
1
2
3
4
5
13
14
15
Offset + 0
Offset + 2
Offset + 4
Offset + 6
E
—
W
I
L
—
OV
—
Data Length
RX Buffer Pointer
2
Figure 39-13. I C RxBD
2
2
Table 39-9. I C RxBD Status and Control Bits
Bits
Name
E
Description
0
Empty.
0 The buffer is full or stopped receiving because of an error. The core can examine or write to any
fields of this RxBD, but the CP does not use this BD while E = 0.
1 The buffer is empty or reception is in progress. The CP owns this RxBD and its buffer. Once E is
set, the core should not write any fields of this RxBD.
1
2
—
Reserved and should be cleared.
W
Wrap (last BD in table).
0 Not the last BD in the RxBD table.
1 Last BD in the RxBD table. After this buffer is used, the CP receives incoming data using the BD
pointed to by RBASE (top of the table). The number of BDs in this table is determined only by the
W bit and overall space constraints of the dual-port RAM.
3
4
I
Interrupt.
0 No interrupt is generated after this buffer is full.
1 The I2CER[RXB] is set when the CP fills this buffer, indicating that the core needs to process the
buffer. The RXB bit can cause an interrupt if it is enabled.
2
L
Last. The I C controller sets L.
0 This buffer does not contain the last character of the message.
2
1 This buffer holds the last character of the message. The I C controller sets L after all received
data is placed into the associated buffer, or because of a stop or start condition or an overrun.
5–13
14
—
Reserved and should be cleared.
2
OV
Overrun. Set when a receiver overrun occurs during reception. The I C controller updates this bit
after the received data is placed into the associated buffer.
15
—
Reserved and should be cleared.
39.7.1.2 I2C Transmit Buffer Descriptor (TxBD)
Transmit data is arranged in buffers referenced by TxBDs in the TxBD table. The first word of the TxBD,
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
39-13
I2C Controller
0
1
2
3
4
5
6
12
13
14
15
Offset + 0
Offset + 2
Offset + 4
Offset + 6
R
—
W
I
L
S
—
NAK UN
CL
Data Length
Tx Buffer Pointer
2
Figure 39-14. I C TxBD
2
2
Table 39-10. I C TxBD Status and Control Bits
Bits
Name
R
Description
0
Ready.
0 The buffer is not ready to be sent. This BD or its buffer can be modified. The CP clears R after
the buffer is sent or an error occurs.
1 The buffer is ready for transmission or is being sent. The BD cannot be modified once R is set.
1
2
—
Reserved and should be cleared.
W
Wrap (last BD in TxBD table).
0 Not the last BD in the table.
1 Last BD in the table. After this buffer is used, the CP transmits data using the BD pointed to by
TBASE (top of the table). The number of BDs in this table is determined only by the W bit and
overall space constraints of the dual-port RAM.
3
4
I
Interrupt.
0 No interrupt is generated after this buffer is serviced.
1 I2CER[TXB] or I2CER[TXE] is set when the buffer is serviced. If enabled, an interrupt occurs.
L
Last.
0 This buffer does not contain the last character of the message.
2
1 This buffer contains the last character of the message. The I C controller generates a stop
condition after sending this buffer.
5
S
Generate start condition. Provides ability to send back-to-back frames with one I2COM[STR] trigger.
0 Do not send a start condition before the first byte of the buffer.
1 Send a start condition before the first byte of the buffer. (Used to separate frames.)
Note: If this BD is the first one in the frame when I2COM[STR] is triggered, a start condition is sent
regardless of the value of TxBD[S].
6–12
13
—
Reserved and should be cleared.
NAK No acknowledge. Indicates that the transmission was aborted because the last byte sent was not
2
acknowledged. The I C controller updates NAK after the buffer is sent.
2
14
15
UN
CL
Underrun. Indicates that the I C controller encountered a transmitter underrun condition while
2
sending the associated buffer. The I C controller updates UN after the buffer is sent.
Collision. Indicates that transmission terminated because the transmitter was lost while arbitrating
for the bus. The I C controller updates CL after the buffer is sent.
2
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Freescale Semiconductor
Chapter 40
Parallel I/O Ports
The CPM supports four general-purpose I/O ports—ports A, B, C, and D. Each pin in the I/O ports can be
configured as a general-purpose I/O signal or as a dedicated peripheral interface signal. Port C is unique
in that 16 of its pins can generate interrupts to the interrupt controller.
Each pin can be configured as an input or output and has a latch for data output, read or written at any time,
and configured as general-purpose I/O or a dedicated peripheral pin. Part of the pins can be configured as
open-drain (the pin can be configured in a wired-OR configuration on the board). The pin drives a zero
voltage but three-states when driving a high voltage.
Note that port pins do not have internal pull-up resistors. Due to the CPM’s significant flexibility, many
dedicated peripheral functions are multiplexed onto the ports. The functions are grouped to maximize the
pins’ usefulness in the greatest number of PowerQUICC II applications. The reader may not obtain a full
understanding of the pin assignment capability described in this chapter without understanding the CPM
peripherals.
40.1 Features
The following is a list of the parallel I/O ports’ important features:
•
•
•
•
•
•
•
•
•
•
Port A is 32 bits
Port B is 28 bits
Port C is 32 bits
Port D is 28 bits
All ports are bidirectional
All ports have alternate on-chip peripheral functions
All ports are three-stated at system reset
All pin values can be read while the pin is connected to an on-chip peripheral
Open-drain capability on some pins
Port C offers 16 interrupt input pins
40.2 Port Registers
Each port has four memory-mapped, read/write, 32-bit control registers.
40.2.1 Port Open-Drain Registers (PODRA–PODRD)
The port open-drain register (PODR), shown in Figure 40-1, indicates a normal or wired-OR configuration
of the port pins.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
40-1
Parallel I/O Ports
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
1
1
1
Field OD0 OD1 OD2 OD3 OD4 OD5 OD6 OD7 OD8 OD9 OD10 OD11 OD12 OD13 OD14 OD15
Reset
R/W
0000_0000_0000_0000
R/W
Addr
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Field OD16 OD17 OD18 OD19 OD20 OD21 OD22 OD23 OD24 OD25 OD26 OD27 OD28 OD29 OD30 OD31
Reset
R/W
0000_0000_0000_0000
R/W
Addr
0x10D0E (PODRA), 0x10D2E (PODRB), 0x10D4E (PODRC), 0x10D6E (PODRD)
1
These bits are valid for PODRA and PODRC only
Figure 40-1. Port Open-Drain Registers (PODRA–PODRD)
Table 40-1 describes PODR fields.
Table 40-1. PODRx Field Descriptions
Bits
Name
Description
0–31
ODx Open-drain configuration. Determines whether the corresponding pin is actively driven as an output
or is an open-drain driver. Note that bits OD0–OD3 are valid for PODRA and PODRC only.
0 The I/O pin is actively driven as an output.
1 The I/O pin is an open-drain driver. As an output, the pin is driven active-low, otherwise it is
three-stated.
40.2.2 Port Data Registers (PDATA–PDATD)
A read of a port data register (PDATx), shown in Figure 40-2, returns the data at the pin, independent of
whether the pin is defined as an input or output. This allows detection of output conflicts at the pin by
comparing the written data with the data on the pin.
A write to the PDATx is latched and if the equivalent PDIR bit is configured as an output, the value latched
for that bit is driven onto its respective pin. PDATx can be read or written at any time and is not initialized.
If a port pin is selected as a general-purpose I/O pin, it can be accessed through the port data register
(PDATx). Data written to the PDATx is stored in an output latch. If a port pin is configured as an output,
the output latch data is gated onto the port pin. In this case, when PDATx is read, the port pin itself is read.
If a port pin is configured as an input, data written to PDATx is still stored in the output latch, but is
prevented from reaching the port pin. In this case, when PDATx is read, the state of the port pin is read.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
40-2
Freescale Semiconductor
Parallel I/O Ports
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
1
1
1
Field D0
D1
D2
D3
D4
D5
D6
D7
D8
D9 D10 D11 D12 D13 D14 D15
Reset
R/W
—
R/W
Addr
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Field D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31
Reset
R/W
—
R/W
Addr
0x10D12 (PDATA), 0x10D32 (PDATB), 0x10D52 (PDATC), 0x10D72 (PDATD)
1
These bits are valid for PDATA and PDATC only
Figure 40-2. Port Data Registers (PDATA–PDATD)
40.2.3 Port Data Direction Registers (PDIRA–PDIRD)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
1
1
1
Field DR0 DR1 DR2 DR3 DR4 DR5 DR6 DR7 DR8 DR9 DR10 DR11 DR12 DR13 DR14 DR15
Reset
R/W
0000_0000_0000_0000
R/W
Addr
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Field DR16 DR17 DR18 DR19 DR20 DR21 DR22 DR23 DR24 DR25 DR26 DR27 DR28 DR29 DR30 DR31
Reset
R/W
0000_0000_0000_0000
R/W
Addr
0x10D02 (PDIRA), 0x10D22 (PDIRB), 0x10D42 (PDIRC), 0x10D62 (PDIRD)
1
These bits are valid for PDIRA and PDIRC only
Figure 40-3. Port Data Direction Register (PDIR)
Table 40-2 describes PDIR fields.
Table 40-2. PDIR Field Descriptions
Description
Bits Name
0–31 DRx Direction. Indicates whether a pin is used as an input or an output. Note that bits DR0–DR3 are valid
for PDIRA and PDIRC only.
0 The corresponding pin is an input or is bidirectional.
1 The corresponding pin is an output.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
40-3
Parallel I/O Ports
40.2.4 Port Pin Assignment Register (PPAR)
The port pin assignment register (PPAR) is cleared at system reset.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
1
1
1
Field DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15
Reset
R/W
0000_0000_0000_0000
R/W
Addr
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Field DD16 DD17 DD18 DD19 DD20 DD21 DD22 DD23 DD24 DD25 DD26 DD27 DD28 DD29 DD30 DD31
Reset
R/W
0000_0000_0000_0000
R/W
Addr
0x10D06 (PPARA), 0x10D26 (PPARB), 0x10D46 (PPARC), 0x10D66 (PPARD)
1
These bits are valid for PPARA and PPARC only
Figure 40-4. Port Pin Assignment Register (PPARA–PPARD)
Table 40-3. PPAR Field Descriptions
Bits
Name
Description
0–31
DDx Dedicated enable. Indicates whether a pin is a general-purpose I/O or a dedicated peripheral pin.
Note: Bits DD0–DD3 are valid for PPARA and PPARC only.
0 General-purpose I/O. The peripheral functions of the pin are not used.
1 Dedicated peripheral function. The pin is used by the internal module. The on-chip peripheral
function to which it is dedicated can be determined by other bits such as those is the PDIR.
40.2.5 Port Special Options Registers A–D (PSORA–PSORD)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
40-4
Freescale Semiconductor
Parallel I/O Ports
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
1
1
1
Field SO0 SO1 SO2 SO3 SO4 SO5 SO6 SO7 SO8 SO9 SO10 SO11 SO12 SO13 SO14 SO15
Reset
R/W
0000_0000_0000_0000
R/W
Addr
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Field SO16 SO17 SO18 SO19 SO20 SO21 SO22 SO23 SO24 SO25 SO26 SO27 SO28 SO29 SO30 SO31
Reset
R/W
0000_0000_0000_0000
R/W
Addr
0x10D0A (PSORA), 0x10D2A (PSORB), 0x10D4A (PSORC), 0x10D6A (PSORD)
1
These bits are valid for PSORA and PSORC only
Figure 40-5. Special Options Registers (PSORA–POSRD)
PSOR bits are effective only if the corresponding PPARx[DDx] = 1 (a dedicated peripheral function).
Table 40-4. PSORx Field Descriptions
Bits
Name
Description
0–31
SOx Special-option. Determines whether a pin configured for a dedicated function (PPARx[DDx] = 1)
uses option 1 or option 2. Note that bits SO0–SO3 are valid for PSORA and PSORC only. Options
0 Dedicated peripheral function. Option 1.
1 Dedicated peripheral function. Option 2.
NOTE
If the corresponding PPARx[DDx] = 1 (configured as a general-purpose pin)
before programming a PSORx or PDIRx bit, a pin might function for a short
period as an unwanted dedicated function and cause unknown behavior.
40.3 Port Block Diagram
Figure 40-6 shows the functional block diagram.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
40-5
Parallel I/O Ports
Read
To/from internal bus
PDATx Write
PDATx Read
0
PDATx
Latch
Open
Drain
Control
0
1
From DED OUT1
From DED OUT2
EN
1
Pin
PDIR
PODR
PPAR
PSOR
Default
0
Input IN1
To DED IN1
1
PPAR & PSOR & PDIR
Default
0
1
Input IN2
To DED IN2
PPAR & PSOR & PDIR
Register Name
0
1
Description
PPARx
PSORx
PDIRx
PODRx
PDATx
General purpose
Dedicated 1
Input
Dedicated
Dedicated 2
Output
Port pin assignment
Special operation
1
Direction
Regular
0
Open drain
1
Data
1
Bidirectional signals must be programmed as inputs (PDIR = 0).
Figure 40-6. Port Functional Operation
40.4 Port Pins Functions
Each pin can operate as a general purpose I/O pin or as a dedicated input or output pin.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
40-6
Freescale Semiconductor
Parallel I/O Ports
40.4.1 General Purpose I/O Pins
Each one of the port pins is independently configured as a general-purpose I/O pin if the corresponding
port pin assignment register (PPAR) bit is cleared. Each pin is configured as a dedicated on-chip peripheral
pin if the corresponding PPAR bit is set.When the port pin is configured as a general-purpose I/O pin, the
signal direction for that pin is determined by the corresponding control bit in the port data direction register
(PDIR). The port I/O pin is configured as an input if the corresponding PDIR bit is cleared; it is configured
as an output if the corresponding PDIR bit is set. All PPAR and PDIR bits are cleared on total system reset,
configuring all port pins as general-purpose input pins.
If a port pin is selected as a general-purpose I/O pin, it can be accessed through the port data register
(PDATx). Data written to the PDATx is stored in an output latch. If a port pin is configured as an output,
the output latch data is gated onto the port pin. In this case, when PDATx is read, the port pin itself is read.
If a port pin is configured as an input, data written to PDATx is still stored in the output latch, but is
prevented from reaching the port pin. In this case, when PDATx is read, the state of the port pin is read.
40.4.2 Dedicated Pins
When a port pin is not configured as a general-purpose I/O pin, it has a dedicated functionality, as
described in the following tables. Note that if an input to a peripheral is not supplied from a pin, a default
value is supplied to the on-chip peripheral as listed in the right-most column.
NOTE
Some output functions can be output on 2 different pins. For example, the
output for BRG1 can come out on both PC31 and PD19. The user can freely
configure such functions to be output on two pins at once. However, there
is typically no advantage in doing so unless there is a large fanout where it
is advantageous to share the load between two pins.
Many input functions can also come from two different pins; see
40.5 Ports Tables
Table 40-5 through Table 40-8 describe the ports functionality according to the configuration of the port
registers (PPARx, PSORx, and PDIRx). Each pin can function as a general purpose I/O, one of two
dedicated outputs, or one of two dedicated inputs.
As shown in Figure 40-7, some input functions can come from two different pins for flexibility. Secondary
option programming is relevant only if primary option is programmed to the default value.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
40-7
Parallel I/O Ports
PD4
PA8
Secondary option
for SMC2 RxD
Primary option
for SMC2 RxD
GND
0
1
0
to SMC2 RxD
Pin PD4
1
Pin PA8
PPARA[8] == 1 &
PPARD[4] == 1 &
PSORD[4] == 1 &
PDIRD[4] == 0
PSORA[8] == 0 &
PDIRA[8] == 0
Figure 40-7. Primary and Secondary Option Programming
In the tables below, the default value for a primary option is simply a reference to the secondary option. In
the secondary option, the programming is relevant only if the primary option is not used for the function.
Table 40-5 shows the port A pin assignments.
Table 40-5. Port A—Dedicated Pin Assignment (PPARA = 1)
Pin Function
PSORA = 0
PSORA = 1
Pin
Defaul
t Input
PDIRA = 0 (Input, or Defaul
Inout if Specified) t Input
PDIRA = 1 (Output) PDIRA = 0 (Input)
PDIRA = 1 (Output)
FCC1: RTS
1
1
PA31
PA30
FCC1: TxEnb
FCC1: TxEnb
UTOPIA slave
GND
FCC1: COL
GND
UTOPIA master
MII
1
1
FCC1: TxClav
FCC1: TxClav
GND
FCC1: CRS
GND
UTOPIA slave
UTOPIA master
MII
1
FCC1: TxClav0
MPHY, master, direct
polling
1
PA29
PA28
PA27
PA26
FCC1: TxSOC
FCC1: TX_ER
UTOPIA
MII
1
1
FCC1: RxEnb
FCC1: RxEnb
GND
GND
GND
FCC1: TX_EN
UTOPIA master
UTOPIA slave
MII
1
FCC1: RxSOC
FCC1: RX_DV
GND
GND
UTOPIA
MII
1
1
FCC1: RxClav
FCC1: RxClav
FCC1: RX_ER
UTOPIA slave
UTOPIA master
FCC1: RxClav0
MII
1
MPHY, master, direct
polling
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
40-8
Freescale Semiconductor
Parallel I/O Ports
Table 40-5. Port A—Dedicated Pin Assignment (PPARA = 1) (continued)
Pin Function
PSORA = 0
PSORA = 1
Pin
Defaul
t Input
PDIRA = 0 (Input, or Defaul
Inout if Specified) t Input
PDIRA = 1 (Output) PDIRA = 0 (Input)
PDIRA = 1 (Output)
1
2
PA25
FCC1: TxD[0]
MSNUM[0]
UTOPIA 8
FCC1: TxD[8]
1
UTOPIA 16
1
2
PA24
PA23
PA22
PA21
FCC1: TxD[1]
MSNUM[1]
UTOPIA 8
1
FCC1: TxD[9]
UTOPIA 16
1
FCC1: TxD[2]
UTOPIA 8
1
FCC1: TxD[10]
UTOPIA 16
1
FCC1: TxD[3]
UTOPIA 8
1
FCC1: TxD[11]
UTOPIA 16
1
FCC1: TxD[4]
UTOPIA 8
FCC1: TxD[12]
1
UTOPIA 16
FCC1: TxD[3]
MII/HDLC nibble
1
PA20
PA19
PA18
FCC1: TxD[5]
UTOPIA 8
1
FCC1: TxD[13]
UTOPIA 16
FCC1: TxD[2]
MII/HDLC nibble
FCC1: TxD[6]
UTOPIA 8
FCC1: TxD[14]
UTOPIA 16
FCC1: TxD[1]
MII/HDLC nibble
1
FCC1: TxD[7]
UTOPIA 8
FCC1: TxD[15]
1
UTOPIA 16
FCC1: TxD[0]
MII/HDLC nibble
FCC1: TxD
HDLC/transp
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
40-9
Parallel I/O Ports
Table 40-5. Port A—Dedicated Pin Assignment (PPARA = 1) (continued)
Pin Function
PSORA = 0
PSORA = 1
Pin
Defaul
t Input
PDIRA = 0 (Input, or Defaul
Inout if Specified) t Input
PDIRA = 1 (Output) PDIRA = 0 (Input)
PDIRA = 1 (Output)
1
PA17
FCC1: RxD[7]
GND
UTOPIA 8
FCC1: RxD[15]
1
UTOPIA 16
FCC1: RxD[0]
MII/HDLC nibble
FCC1: RxD
HDLC/transp.
1
PA16
PA15
PA14
FCC1: RxD[6]
GND
GND
GND
UTOPIA 8
1
FCC1: RxD[14]
UTOPIA 16
FCC1: RxD[1]
MII/HDLC nibble
1
FCC1: RxD[5]
UTOPIA 8
1
FCC1: RxD[13]
UTOPIA 16
FCC1: RxD[2]
MII/HDLC nibble
1
FCC1: RxD[4]
UTOPIA 8
FCC1: RxD[12]
1
UTOPIA 16
FCC1: RxD[3]
MII/HDLC nibble
1
2
PA13
PA12
PA11
PA10
FCC1: RxD[3]
GND
GND
GND
GND
MSNUM[2]
UTOPIA 8
1
FCC1: RxD[11]
UTOPIA 16
1
2
FCC1: RxD[2]
MSNUM[3]
UTOPIA 8
1
FCC1: RxD[10]
UTOPIA 16
1
2
FCC1: RxD[1]
MSNUM[4]
UTOPIA 8
FCC1: RxD[9]
UTOPIA 16
1
1
2
FCC1: RxD[0]
MSNUM[5]
UTOPIA 8
FCC1: RxD[8]
1
UTOPIA 16
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
40-10
Freescale Semiconductor
Parallel I/O Ports
Table 40-5. Port A—Dedicated Pin Assignment (PPARA = 1) (continued)
Pin Function
PSORA = 0
PSORA = 1
Pin
Defaul
t Input
PDIRA = 0 (Input, or Defaul
Inout if Specified) t Input
PDIRA = 1 (Output) PDIRA = 0 (Input)
SMC2: SMTXD
PDIRA = 1 (Output)
PA9
PA8
TDM_A1: L1TXD[0]
TDM_A1: L1TXD
GND
Output, nibble
Inout, serial
SMC2: SMRXD
(primary option)
by PD4
TDM_A1: L1RXD[0] GND
Input, nibble
TDM_A1: L1RXD
Inout, serial
PA7
SMC2: SMSYN
(primary option)
by PC0
GND
TDM_A1:
L1TSYNC/GRANT
GND
PA6
PA5
TDM_A1: L1RSYNC GND
1,3
1
SCC2: RSTRT
FCC1: RxPrty
UTOPIA
FCC2: RxAddr[2]
IDMA4: DREQ
GND
MPHY master
(secondary option)
1
1
PA4
PA3
PA2
PA1
PA0
FCC2: RxAddr[1]
SCC2: REJECT
VDD
GND
GND
VDD
IDMA4: DONE
VDD
MPHY master
Inout
FCC2: RxAddr[0]
CLK19
IDMA4: DACK
IDMA3: DACK
TDM_A2: L1RXD[1] GND
MPHY master
Nibble
1
FCC2: TxAddr[0]
MPHY master
CLK20
1
FCC2: TxAddr[1]
MPHY master
SCC1: REJECT
IDMA3: DONE
VDD
GND
Inout
1
SCC1: RSTRT
FCC2: TxAddr[2]
IDMA3: DREQ
MPHY master
1
2
Not available on the MPC8250.
MSNUM[0–4] is the sub-block code of the peripheral controller using SDMA; MSNUM[5] indicates which section,
transmit or receive, is active during the transfer. See Section 19.2.4, “SDMA Transfer Error MSNUM Registers
3
.25µm (HiP4) devices only: available only when the primary option for this function is not used.
Table 40-6 shows the port B pin assignments.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
40-11
Parallel I/O Ports
Table 40-6. Port B Dedicated Pin Assignment (PPARB = 1)
Pin Function
PSORB = 0
PSORB = 1
Pin
Defaul
t Input
PDIRB = 0 (Input or Defaul
Inout if Specified) t Input
PDIRB = 1 (Output) PDIRB = 0 (Input)
PDIRB = 1 (Output)
1
PB31
PB30
PB29
PB28
PB27
PB26
PB25
FCC2: TX_ER
FCC2: RxSOC
GND
GND
GND
GND
GND
GND
TDM_B2: L1TXD
GND
MII
UTOPIA
Inout
1
FCC2: TxSOC
FCC2: RX_DV
TDM_B2: L1RXD
GND
UTOPIA
MII
Inout
1
1
FCC2: RxClav
FCC2: RxClav
FCC2: TX_EN
TDM_B2: L1RSYNC GND
UTOPIA slave
UTOPIA master
MII
FCC2: RTS
FCC2: RX_ER
SCC1: TXD
TDM_B2:
L1TSYNC/GRANT
GND
GND
GND
GND
MII
1
FCC2: TxD[0]
FCC2: COL
TDM_C2: L1TXD
UTOPIA 8
MII
Inout
1
FCC2: TxD[1]
FCC2: CRS
TDM_C2: L1RXD
UTOPIA 8
MII
Inout
1
FCC2: TxD[4]
TDM_A1: L1TXD[3]
TDM_C2:
UTOPIA 8
Nibble
L1TSYNC/GRANT
FCC2: TxD[3]
MII/HDLC nibble
1
PB24
PB23
PB22
FCC2: TxD[5]
TDM_A1:L1RXD[3]
GND
TDM_C2: L1RSYNC GND
UTOPIA 8
Nibble
FCC2: TxD[2]
MII/HDLC nibble
1
FCC2: TxD[6]
TDM_A1: L1RXD[2] GND
TDM_D2: L1TXD
GND
GND
UTOPIA
Nibble
Inout
FCC2: TxD[1]
MII/HDLC nibble
1
FCC2: TxD[7]
TDM_A1: L1RXD[1] GND
TDM_D2: L1RXD
UTOPIA
FCC2: TxD[0]
MII/HDLC nibble
FCC2: TxD
Nibble
Inout
HDLC/transp. serial
PB21
PB20
FCC2: RxD[7]
UTOPIA 8
FCC2: RxD[0]
MII/HDLC nibble
FCC2: RxD
GND TDM_A1: L1TXD[2]
TDM_D2:
L1TSYNC/GRANT
GND
Nibble
HDLC/transp. serial
FCC2: RxD[6]
UTOPIA 8
GND
TDM_A1-L1TXD[1] TDM_D2: L1RSYNC GND
Nibble
FCC2: RxD[1]
MII/HDLC nibble
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
40-12
Freescale Semiconductor
Parallel I/O Ports
Table 40-6. Port B Dedicated Pin Assignment (PPARB = 1) (continued)
Pin Function
PSORB = 0
PSORB = 1
Pin
Defaul
t Input
PDIRB = 0 (Input or Defaul
Inout if Specified) t Input
PDIRB = 1 (Output) PDIRB = 0 (Input)
PDIRB = 1 (Output)
TDM_D2: L1RQ
1
PB19
FCC2: RxD[5]
GND
TDM_A2: L1RXD[3] GND
UTOPIA 8
Nibble
FCC2: RxD[2]
MII/HDLC nibble
PB18
FCC2: RxD[4]
UTOPIA 8
GND
TDM_D2: L1CLKO TDM A2: L1RXD[2]
GND
Nibble
FCC2: RxD[3]
MII/HDLC nibble
PB17
PB16
PB15
TDM_A1: L1RQ
FCC3: RX_DV
GND
GND
CLK17
CLK18
GND
GND
MII
TDM_A1: L1CLKO
FCC3: RX_ER
MII
FCC3: TX_ER
SCC2: RXD
(primary option)
by
PD28
TDM_C1: L1TXD
Inout
by
PD28
MII
(primary option)
PB14
PB13
FCC3: TX_EN
SCC3: RXD
(primary option)
by
PD25
TDM_C1: L1RXD
Inout
(primary option)
by
PD27
MII
TDM_B1: L1RQ
FCC3: COL
GND TDM_A2:L1TXD[1]
TDM_C1:
by
MII
Nibble
L1TSYNC/GRANT
(primary option)
PD16
PB12
PB11
TDM_B1: L1CLKO
FCC3: CRS
GND
GND
SCC2: TXD
TDM_C1: L1RSYNC
by
PD26
MII
(primary option)
1
FCC2: TxD[0]
FCC3: RxD[3]
MII/HDLC nibble
TDM_D1: L1TXD
Inout
by
PD25
UTOPIA 8
(primary option)
1
PB10
PB9
PB8
FCC2: TxD[1]
FCC3: RxD[2]
MII/HDLC nibble
GND
TDM_D1: L1RXD
Inout
(primary option)
by
PD24
UTOPIA 8
1
FCC2: TxD[2]
FCC3: RxD[1]
MII/HDLC nibble
GND TDM_A2:L1TXD[2]
TDM_D1:
L1TSYNC/GRANT
(primary option)
by PD4
UTOPIA 8
Nibble
1
FCC2: TxD[3]
FCC3: RxD[0]
MII/HDLC nibble
FCC3: RxD
GND
SCC3: TXD
TDM_D1: L1RSYNC
by
PD23
UTOPIA 8
(primary option)
HDLC/transp. serial
1
PB7
FCC3: TXD[0]
MII/HDLC nibble
FCC3: TXD
FCC2: RxD[3]
by
PC10
TDM_A2: L1TXD[0]
TDM_A2: L1TXD
Inout, serial
(primary option)
by
PD22
UTOPIA 8
Output, nibble
(primary option)
HDLC/transp. serial
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
40-13
Parallel I/O Ports
Table 40-6. Port B Dedicated Pin Assignment (PPARB = 1) (continued)
Pin Function
PSORB = 0
PSORB = 1
Pin
Defaul
t Input
PDIRB = 0 (Input or Defaul
Inout if Specified) t Input
PDIRB = 1 (Output) PDIRB = 0 (Input)
PDIRB = 1 (Output)
1
PB6
FCC3: TXD[1]
MII/HDLC nibble
FCC2: RxD[2]
UTOPIA 8
by
PC11
TDM_A2: L1RXD
Inout, serial
by
PD21
(primary option)
TDM_A2: L1RXD[0]
Input, nibble
(primary option)
1
PB5
PB4
FCC3: TXD[2]
MII/HDLC nibble
FCC2: RxD[1]
by
PD10
TDM_A2:
L1TSYNC/GRANT
(primary option)
by PC9
UTOPIA 8
(primary option)
1
FCC3: TXD[3]
FCC2: RxD[0]
by
FCC3: RTSN
TDM_A2: L1RSYNC
by
MII/HDLC nibble
UTOPIA 8
PD11
(primary option)
PD20
(primary option)
1
Not available on the MPC8250.
Table 40-7 shows the port C pin assignments.
Table 40-7. Port C Dedicated Pin Assignment (PPARC = 1)
Pin Function
PSORC = 0
PSORC = 1
PIN
Defaul
t Input
PDIRC = 0 (Input or Defaul
Inout if Specified) t Input
PDIRC = 1 (Output) PDIRC = 0 (Input)
PDIRC = 1 (Output)
Timer1:TOUT
PC31
PC30
BRG1: BRGO
CLK1
CLK2
CLK5
CLK6
1
FCC2: TxD[3]
UTOPIA 8
2
PC29
PC28
PC27
PC26
BRG2: BRGO
Timer2: TOUT
CLK3/TIN2
CLK4/TIN1
CLK5
CLK7
CLK8
GND
GND
SCC1: CTS
SCC1: CLSN
Ethernet
GND
GND
2
(secondary option)
2
SCC2: CTS
2
SCC2: CLSN
Ethernet
(secondary option)
FCC3: TxD
HDLC/transp. serial
FCC3: TxD[0]
BRG3: BRGO
MII/HDLC nibble
Timer3: TOUT
CLK6
TMCLK
BRGO
1
real-time counter
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
40-14
Freescale Semiconductor
Parallel I/O Ports
Table 40-7. Port C Dedicated Pin Assignment (PPARC = 1) (continued)
Pin Function
PSORC = 0
PSORC = 1
PIN
Defaul
t Input
PDIRC = 0 (Input or Defaul
Inout if Specified) t Input
PDIRC = 1 (Output) PDIRC = 0 (Input)
PDIRC = 1 (Output)
BRG4: BRGO
1
PC25
PC24
PC23
PC22
FCC2: TxD[2]
CLK7
CLK8
CLK9
CLK10
GND
GND
UTOPIA 8
1
FCC2: TxD[3]
Timer4: TOUT
IDMA1: DACK
UTOPIA 8
BRG5: BRGO
CLK13
CLK14
1
FCC1: TxPrty
UTOPIA
IDMA1: DONE
Inout
by PD5
2
(secondary option)
(primary option)
PC21
BRG6: BRGO
CLK11
CLK15
PC20
PC19
CLK12
CLK13
CLK16
GND
timer1/2: TGATE1
GND
GND
3
BRG7: BRGO
SPI: SPICLK
Inout
(secondary option)
PC18
PC17
PC16
PC15
CLK14
GND
GND
GND
timer3/4: TGATE2
BRG8: BRGO
SMC2: SMTXD
CLK15/TIN3
CLK16/TIN4
1
1,3
SCC1: CTS
SCC1: CLSN
Ethernet
by
PC29
FCC1: TxAddr[0]
MPHY, master
FCC1:TxAddr[0]
GND
GND
GND
GND
GND
MPHY, slave
FCC2: TxAddr[4]
MPHY, slave
(primary option)
1
1,3
PC14
PC13
PC12
SCC1: CD
SCC1: RENA
Ethernet
GND
FCC1: RxAddr[0]
FCC1: RxAddr[0]
MPHY, master
MPHY, slave
FCC2: RxAddr[4]
1
MPHY, slave
1
1,3
TDM_D1: L1RQ
SI1: L1ST3
SCC2: CTS
SCC2: CLSN
Ethernet
by
PC28
FCC1: TxAddr[1]
FCC1: TxAddr[1]
MPHY, master
MPHY, slave
FCC2: TxAddr[3]
1
(primary option)
MPHY, slave
1
1,3
SCC2: CD
SCC2: RENA
Ethernet
GND
FCC1: RxAddr[1]
FCC1:RxAddr[1]
MPHY, master
MPHY, slave
FCC2: RxAddr[3]
1
MPHY, slave
1, 3
PC11 TDM_D1: L1CLKO
SCC3: CTS
SCC3: CLSN
Ethernet
by PC8 TDM_A2:L1TXD[3]
FCC2: RxD[2]
Nibble
UTOPIA 8
(secondary option)
(primary option)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
40-15
Parallel I/O Ports
Table 40-7. Port C Dedicated Pin Assignment (PPARC = 1) (continued)
Pin Function
PSORC = 0
PSORC = 1
PIN
Defaul
t Input
PDIRC = 0 (Input or Defaul
Inout if Specified) t Input
PDIRC = 1 (Output) PDIRC = 0 (Input)
PDIRC = 1 (Output)
1
1,3
PC10
PC9
FCC1: TxD[2]
UTOPIA 16
SCC3: CD
SCC3: RENA
Ethernet
GND
SI1: L1ST4
FCC2: RxD[3]
UTOPIA
GND
strobe
(secondary option)
1
FCC1: TxD[1]
SCC4: CTS
SCC4: CLSN
Ethernet
by PC3
SI2: L1ST1
TDM_A2:
GND
UTOPIA 16
strobe
L1TSYNC/GRANT
(secondary option)
(primary option)
1
PC8
PC7
FCC1: TxD[0]
UTOPIA 16
SCC4: CD
SCC4: RENA
Ethernet
GND
GND
SI2: L1ST2
Strobe
SCC3: CTS
SCC3:CLSN
(secondary option)
GND
GND
2
1
1,3
TDM_C1: L1RQ
FCC1: CTS
FCC1: TxAddr[2]
FCC1:TxAddr[2]
MPHY master,
MPHY, slave,
multiplexed: polling
multiplexed polling
FCC1: TxClav1
1,3
MPHY, master, direct
polling
1
FCC2: TxAddr[2]
MPHY, slave,
multiplexed polling
1
1,3
PC6
TDM_C1: L1CLKO
FCC1: CD
GND
FCC1: RxAddr[2]
FCC1:RxAddr[2]
GND
MPHY, master,
MPHY, slave,
multiplexed polling
multiplexed polling)
FCC1: RxClav1
1,3
MPHY, master, direct
polling
1
FCC2: RxAddr[2]
MPHY, slave,
multiplexed polling
1
1
PC5
PC4
PC3
FCC2: TxClav
FCC2: TxClav
GND
GND
GND
SI2: L1ST3
Strobe
FCC2: CTS
FCC2: CD
SCC4: CTS
GND
GND
GND
UTOPIA, slave
UTOPIA, master
1
1
FCC2: RxEnb
FCC2: RxEnb
SI2: L1ST4
Strobe
UTOPIA, master
UTOPIA, slave
1
FCC2: TxD[2]
FCC3: CTS
IDMA2: DACK
2
UTOPIA 8
SCC4: CLSN
(secondary option)
1
PC2
PC1
FCC2: TxD[3]
FCC3: CD
GND
GND
IDMA2: DONE
V
DD
UTOPIA 8
Inout
2
BRG6: BRGO
IDMA2: DREQ
TDM_A2: L1RQ
SPI: SPISEL
Inout
(secondary option)
PC0
BRG7: BRGO
IDMA1: DREQ
GND
TDM_A2: L1CLKO
SMC2: SMSYN
GND
(secondary option)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
40-16
Freescale Semiconductor
Parallel I/O Ports
1
2
3
Not available on the MPC8250.
.25µm (HiP4) devices only: available only when the primary option for this function is not used.
MPHY Address pins 3,4 (master mode) can come from FCC2, depending on CMXUAR programming. (See
Table 40-8 shows the port D pin assignments.
Table 40-8. Port D Dedicated Pin Assignment (PPARD = 1)
Pin Function
PSORD = 0
PDIRD = 0 (Input)
PSORD = 1
Pin
Defaul
t Input
PDIRD = 0 (Input, or Defaul
PDIRD = 1 (Output)
PDIRD = 1 (Output)
Inout if Specified) t Input
PD31
PD30
SCC1: RXD
GND
GND
1
1
FCC2: TxEnb
FCC2: TxEnb
SCC1: TXD
UTOPIA master
UTOPIA slave
1,2
1,3
PD29
SCC1: RTS
SCC1: TENA
Ethernet
FCC1: RxAddr[3]
MPHY, master,
FCC1: RxAddr[3]
GND
MPHY, slave,
multiplexed polling
multiplexed polling
1
1, 3
FCC2: RxAddr[4]
MPHY, master,
FCC1: RxClav2
MPHY, master, direct
polling
multiplexed polling
1
FCC2: RxAddr[1]
MPHY, slave,
multiplexed polling
1
4
4
PD28
PD27
PD26
PD25
PD24
PD23
PD22
FCC1: TxD[7]
SCC2: RXD
GND
GND
GND
GND
GND
GND
GND
TDM_C1: L1TXD
GND
GND
GND
GND
GND
GND
GND
UTOPIA 16 bit
(secondary option)
Inout
(secondary option)
1
4
SCC2: TXD
FCC1: RxD[7]
UTOPIA 16
TDM_C1: L1RXD
Inout
(secondary option)
1
SCC2: RTS
SCC2: TENA
Ethernet
FCC1: RxD[6]
UTOPIA 16
TDM_C1:
4
L1RSYNC
(secondary option)
1
4
4
FCC1: TxD[6]
UTOPIA 16
SCC3: RXD
TDM_D1: L1TXD
(secondary option)
Inout
(secondary option)
1
4
SCC3: TXD
FCC1: RxD[5]
UTOPIA 16
TDM_D1: L1RXD
Inout
(secondary option)
1
SCC3: RTS
SCC3: TENA
Ethernet
FCC1: RxD[4]
UTOPIA 16
TDM_D1:
4
L1RSYNC
(secondary option)
1
4
FCC1: TxD[5]
UTOPIA 16
SCC4: RXD
TDM_A2:
L1TXD[0]
TDM_A2: L1TXD
4
Inout, serial
Output, nibble
(secondary option)
(secondary option)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
40-17
Parallel I/O Ports
Table 40-8. Port D Dedicated Pin Assignment (PPARD = 1) (continued)
Pin Function
PSORD = 0
PDIRD = 0 (Input)
PSORD = 1
Pin
Defaul
t Input
PDIRD = 0 (Input, or Defaul
PDIRD = 1 (Output)
PDIRD = 1 (Output)
Inout if Specified) t Input
1
4
PD21
SCC4: TXD
FCC1: RxD[3]
UTOPIA 16
GND
TDM_A2: L1RXD
Inout, serial
GND
TDM_A2:
4
L1RXD[0]
Input, nibble
(secondary option)
1
PD20
SCC4: RTS
SCC4: TENA
Ethernet
FCC1: RxD[2]
UTOPIA 16
GND
GND
TDM_A2:
L1RSYNC
(secondary option)
GND
4
1,
1,3
PD19 FCC1: TxAddr[4]
FCC1: TxAddr[4] 1
BRG1: BRGO
SPI: SPISEL
(primary option)
V
DD
2
5
MPHY, slave,
MPHY, master,
multiplexed polling
FCC2: TxAddr[3]
MPHY, master,
multiplexed polling
multiplexed polling
FCC1: TxClav3
1,3
1
MPHY, master, direct
polling
1
FCC2: TxAddr[0]
MPHY, slave,
multiplexed polling
1,2
1,3
PD18 FCC1: RxAddr[4]
MPHY, master,
FCC1: RxAddr[4]
GND
SPI: SPICLK
Inout
(primary option)
GND
MPHY, slave,
5
multiplexed polling
multiplexed polling
1
1,3
FCC2: RxAddr[3]
MPHY, master,
FCC1: RxClav3
MPHY, master, direct
polling
multiplexed polling
1
FCC2: RxAddr[0]
MPHY, slave,
multiplexed polling
PD17
PD16
PD15
BRG2: BRGO
FCC1: RxPrty
UTOPIA
(primary option)
GND
GND
SPI: SPIMOSI
V
DD
Inout
5
1
FCC1: TxPrty
TDM_C1:
L1TSYNC/GRANT
(secondary option)
SPI: SPIMISO
SPIMO
SI
4
UTOPIA
(primary option)
Inout
5
1
TDM_C2: L1RQ
FCC1: RxD[1]
GND
GND
I2C: I2CSDA
V
DD
UTOPIA 16
Inout
1
PD14 TDM_C2: L1CLKO
FCC1: RxD[0]
I2C: I2CSCL
GND
GND
GND
UTOPIA 16
Inout
PD13
PD12
SI1: L1ST1
SI1: L1ST2
TDM_B1: L1TXD
Inout
TDM_B1: L1RXD
Inout
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
40-18
Freescale Semiconductor
Parallel I/O Ports
Table 40-8. Port D Dedicated Pin Assignment (PPARD = 1) (continued)
Pin Function
PSORD = 0
PDIRD = 0 (Input)
PSORD = 1
Pin
Defaul
t Input
PDIRD = 0 (Input, or Defaul
Inout if Specified) t Input
PDIRD = 1 (Output)
TDMB2: L1RQ
PDIRD = 1 (Output)
1,4
PD11
PD10
FCC2: RxD[0]
GND
TDM_B1:
L1TSYNC/GRANT
GND
UTOPIA 8
(secondary option)
1,4
TDMB2: L1CLKO
SMC1: SMTXD
FCC2: RxD[1]
GND
BRG4: BRGO
BRG3: BRGO
TDM_B1:L1RSYNC GND
UTOPIA 8
(secondary option)
1
PD9
PD8
PD7
FCC2: RxPrty
GND
GND
UTOPIA
1
FCC2: TxPrty
SMC1: SMRXD
SMC1: SMSYN
GND
BRG5: BRGO
UTOPIA
1,2
1,3
GND FCC1: TxAddr[3]
MPHY, master,
FCC1: TxAddr[3]
MPHY, slave,
multiplexed polling
FCC2: TxAddr[4]
multiplexed polling
FCC1: TxClav2
1
1,3
MPHY, master,
multiplexed polling
MPHY, master, direct
polling
FCC2: TxAddr[1]
1
MPHY, slave,
multiplexed polling
1
PD6
PD5
FCC1: TxD[4]
UTOPIA 16
IDMA1: DACK
1
4
FCC1: TxD[3]
IDMA1: DONE
V
DD
UTOPIA 16
Inout
(secondary option)
4
PD4
BRG8: BRGO
TDM_D1:
L1TSYNC/GRANT
GND
FCC3: RTS
SMC2: SMRXD
GND
4
(secondary option)
(secondary option)
1
2
Not available on the MPC8250.
MPHY address pins 3 and 4 (master mode) can come from FCC2, depending on CMXUAR programming. (See
3
MPHY address pins 0–4 (slave mode) can come from FCC2, depending on CMXUAR programming. (See
4
5
Available only when the primary option for this function is not used.
.25µm (HiP4) devices only: primary option.
40.6 Interrupts from Port C
The port C lines associated with CDx and CTSx have a mode of operation where the pin can be internally
connected to the SCC/FCC but can also generate interrupts. Port C still detects changes on the CTS and
CD pins and asserts the corresponding interrupt request, but the SCC/FCC simultaneously uses CTS
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
40-19
Parallel I/O Ports
and/or CD to automatically control operation. This lets the user fully implement protocols V.24, X.21, and
X.21 bis (with the assistance of other general-purpose I/O lines).
To configure a port C pin as a CTS or CD pin that connects to the SCC/FCC and generates interrupts, these
steps should be followed:
1. Write the corresponding PPARC bit with a 1 and PSORC bit with 0.
2. Write the corresponding PDIRC bit with a zero.
3. Set the SIEXR bit (in the interrupt controller) to determine which edges cause interrupts.
4. Write the corresponding SIMR (mask register) bit with a 1 to allow interrupts to be generated to
the core.
5. The pin value can be read at any time using PDATC.
NOTE
After connecting CTS or CD to the SCC/FCC, the user must also choose the
normal operation mode in GSMR[DIAG] to enable and disable SCC/FCC
transmission and reception with these pins.
The IDMA-DREQ signals on port C can assert an external request to the CP instead of asserting an
interrupt to the core. Each line can be programmed to assert an interrupt request upon a high-to-low change
or any change as configured in SIEXR.
NOTE
Do not program the IDMAx-DREQ pins to assert external requests to the
IDMA, unless the IDMA is used. Otherwise, erratic operation occurs.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
40-20
Freescale Semiconductor
Appendix A
Register Quick Reference Guide
A0
This section provides a brief guide to the core registers.
A.1
PowerPC Registers—User Registers
The implements the user-level registers defined by the PowerPC architecture except those required for
supporting floating-point operations (the floating-point register file (FPRs) and the floating-point status
Table A-2 lists user-level special-purpose registers (SPRs).
Table A-1. User-Level PowerPC Registers (non-SPRs)
Description
Name
Comments
Access Level Serialize Access
General-purpose
registers
GPRs The thirty-two 32-bit (GPRs) are used for source
and destination operands.
User
User
—
Condition register
CR
See the Programming Environments Manual
Only mtcrf
Table A-2 lists SPRs defined by the PowerPC architecture implemented on the MPC8260.
Table A-2. User-Level PowerPC SPRs
SPR Number
Name
Comments
Serialize Access
Decimal SPR [5–9] SPR [0–4]
1
8
9
00000
00000
00000
00001
01000
01001
XER
LR
See the Programming Write: Full sync
Environments Manual Read: Sync relative to load/store operations
See the Programming No
Environments Manual
CTR
See the Programming No
Environments Manual
1
2
268
269
01000
01000
01100
01101
TBL read
TBU read
See the Programming Write (as a store)
Environments Manual
1
2
Extended opcode for mftb, 371 rather than 339.
Any write (mtspr) to this address causes an implementation-dependent software emulation exception.
A.2
PowerPC Registers—Supervisor Registers
All supervisor-level registers implemented on the MPC8260 are SPRs, except for the machine state
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
A-1
Register Quick Reference Guide
Description
Table A-3. Supervisor-Level PowerPC Registers
Name Comments
Serialize Access
Machine state register MSR See the Programming Environments Manual and Write fetch sync
MPC603e RISC Microprocessor User’s Manual
Table A-4 lists supervisor-level SPRs defined by the PowerPC architecture.
Table A-4. Supervisor-Level PowerPC SPRs
SPR Number
Name
Comments
Serialize Access
Decimal SPR[5–9] SPR[0–4]
18
00000
10010
DSISR
See the Programming Environments
Manual
Write: Full sync
Read: Sync relative to
load/store operations
19
00000
10011
DAR
See the Programming Environments
Manual
Write: Full sync
Read: Sync relative to load/
store operations
22
26
27
00000
00000
00000
10110
11010
11011
DEC
See the Programming Environments
Manual
Write
Write
Write
Write
SRR0
SRR1
See the Programming Environments
Manual
See the Programming Environments
Manual
272
273
274
275
284
285
287
01000
01000
01000
01000
01000
01000
01000
10000
10001
10010
10011
11100
11101
11111
SPRG0
SPRG1
SPRG2
SPRG3
See the Programming Environments
Manual
1
TBL write See the Programming Environments
Write (as a store)
Manual
1
TBU write
PVR
1
Any read (mftb) to this address causes an implementation-dependent software emulation exception.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
A-2
Freescale Semiconductor
Register Quick Reference Guide
A.3
MPC8260-Specific SPRs
Table A-2 and Table A-5 list SPRs specific to the MPC8260. Supervisor-level registers are described in
Table A-5. MPC8260-Specific Supervisor-Level SPRs
SPR Number
Name
Comments
Serialize Access
Decimal SPR[5–9] SPR[0–4]
976
977
978
979
980
981
982
1008
11110
11110
11110
11110
11110
11110
11110
11111
10000
10001
10010
10011
10100
10101
10110
10000
DMISS
See the MPC603e RISC
Microprocessor User’s Manual
DCMP
HASH1
HASH2
IMISS
ICMP
RPA
See the MPC603e RISC
Microprocessor User’s Manual
See the MPC603e RISC
Microprocessor User’s Manual
See the MPC603e RISC
Microprocessor User’s Manual
See the MPC603e RISC
Microprocessor User’s Manual
See the MPC603e RISC
Microprocessor User’s Manual
See the MPC603e RISC
Microprocessor User’s Manual
HID0
Section 2.3.1.2.1, “Hardware
(HID0).”
1009
11111
10001
HID1
Section 2.3.1.2.2, “Hardware
(HID1).”
1010
1011
11111
11111
10010
10011
IABR
HID2
See the MPC603e RISC
Microprocessor User’s Manual
Section 2.3.1.2.3, “Hardware
(HID2).”
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
A-3
Register Quick Reference Guide
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
A-4
Freescale Semiconductor
Appendix B
Reference Manual (Rev 1) Errata
This appendix lists errata to revision 1 of the MPC8260 PowerQUICC II™ User’s Manual. It is intended
solely as a quick reference for users who are familiar with revision 1. These errata have been incorporated
into the current manual. Therefore, the following information is redundant.
This appendix contains the last published version of the errata document (rev 2.1, 04/2004).
NOTE
All numbering corresponds to revision 1 of the MPC8260 PowerQUICC
II™ User’s Manual. This includes section and page numbers of each
erratum (provided on the left-hand margin) as well as table and figure
numbers.
B.1
Document Errata
The following list includes the document errata:
Section/Page
Changes
4.3.1.1, 4-19
In Table 4-4, the reserved field should be bits 8–13 (as shown in Figure 4-10) and
not 8–14. Bit 14 is GSIU (group SIU).
4.3.1.3, 4-21
4.3.1.3, 4-22
In Table 4-6, descriptions for bits 3–31 should appear as follows:
3–11
XC2P–XC4P Same as XC1P, but for XCC2–XCC4
Reserved, should be cleared.
12–15
—
16–27 XC5P–XC8P Same as XC1P, but for XCC5–XCC8
28–31 Reserved, should be cleared.
—
In Table 4-7, descriptions for bits 3–31 should appear as follows:
3–11 YC2P–YC8P Same as YC1P, but for YCC2–YCC8
12–15
16–27 YC5P–YC8P Same as YC1P, but for YCC5–YCC8
28–31 Reserved, should be cleared.
—
Reserved, should be cleared.
—
4.3.2.1, 4-28
In Figure 4-21, the note on reset (“Depends on reset configuration sequence...”)
should only apply to bits 0 and 27 [EBM, ISPS]. All other BCR bits are cleared at
reset.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
B-1
Reference Manual (Rev 1) Errata
4.3.2.1, 4-28
The bit definitions should be reversed for BCR[DAM] in Table 4-9. They should
appear as follows:
10 DAM Delay all masters. Applies to all the masters on the bus (CPU, EXT, CPM).
This bit is similar to BCR[EXDD] but with opposite polarity.
0 The memory controller asserts CS on the cycle following the assertion of
TS when accessing an address space controlled by the memory
controller.
1 The memory controller inserts one wait state between the assertion of TS
and the assertion of CS when accessing an address space controlled by
the memory controller.
4.3.2.2, 4-31
In Table 4-10, the description of PRKM = 0010 contains an incorrect
cross-reference. It should state, “See Section 29.7.1, “FCC Function Code
Registers (FCRx).”
4.3.2.8, 4-38
5.3, 5-6
In Table 4-14 the reserved field should be bits 26–28 (as shown in Figure 4-30),
not 26–29. Bit 29 is SWE (software watchdog enable).
In Table 5-4, add the following to the description of CSRE:
Note: When the core is disabled, CSRE must be cleared.
In Table 5-7, add the following to the description of CS10PC:
5.4.1, 5-10
Note: During the reset configuration sequence, the BCTL1/CS10 pin toggles like
POE of the 60x bus GPCM, regardless of the configuration of the reset
configuration word. After the reset configuration sequence, the BCTL1/CS10 pin
behaves according to the configuration of SIUMCR[CS10PC].
7.2.8.1.1, 7-17
Replace the description of TA input assertion with the following:
Timing Comments
Assertion depends on whether or not the PCI controller can initiate 60x bus global
transactions when the address retry mechanism is in use:
PCI controller is not used or cannot initiate global transactions—Assertion must
occur at least one cycle following AACK for the current transaction; otherwise,
assertion may occur at any time during the assertion of DBB. The system can
withhold assertion of TA to indicate that the PowerQUICC II should insert wait
states to extend the duration of the data beat.
PCI controller can initiate global transactions—Assertion must occur at least one
clock cycle following AACK for the current transaction and at least one clock
cycle after ARTRY can be asserted.
7.2.8.1.2, 7-17
Replace the description of TA output assertion with the following:
Timing Comments
Assertion depends on whether or not the PCI controller can initiate 60x bus global
transactions when the address retry mechanism is in use:
PCI controller is not used or cannot initiate global transactions—Assertion must
occur at least one cycle following AACK for the current transaction; occurs on the
clock in which the current data transfer can be completed.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
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Reference Manual (Rev 1) Errata
PCI controller can initiate global transactions—Assertion must occur at least one
clock cycle following AACK for the current transaction and at least one clock
cycle after ARTRY can be asserted.
8.4.4.1. 8-24
8.4.4.1. 8-24
Replace the third sentence of the paragraph that follows Figure 8-7 with the
following (changes appear in boldface):
If the assertion of ARTRY is received up to or on the bus cycle as the first (or only)
assertion of TA for the data tenure, the PowerQUICC II ignores the first data beat.
Replace the first sentence of the paragraph that begins, “Note that the system...”
with the following:
Note that the system must ensure that ARTRYis never asserted later than the cycle
of the first or only assertion of TA. (If the PCI controller can initiate global
transactions, the system must ensure that ARTRY is never asserted on the same
cycle or later then the first or only assertion of TA.)
9.11, 9-30
Replace the second paragraph with the following:
Both the PCI configuration and memory-mapped internal registers of the PCI
bridge are intrinsically little endian and are described using classic bit-numbering;
that is, the lowest memory address contains the least-significant byte of the
register, and bit 0 is the least-significant bit of the register.
9.11.1.11, 9-42
9.11.1.14, 9-45
The second sentence should read as follows (changes appear in boldface):
The IOU asserts an interrupt or machine check only if the mask bit for the error
condition (refer to Table 9-14) is set.
In Table 9-15, the descriptions of Transaction size, Error source, and Valid
information should appear as follows (changes or additions appear in boldface):
21–20 Transaction
size
This is the size of the transaction in doublewords (4 bytes) (the
PCI bridge as master only)
00 4 doublewords
01 1 doubleword
10 2 doublewords
11 3 doublewords
19–16 Error source The source of the PCI transaction.
0000 External master
0001 60x master
0101 DMA
All others are reserved.
0
Valid info
When this bit is set, the PCI bus error capture registers
(PCI_EACR, PCI_EDCR, and PCI_ECCR) contain valid
information.
Writing ‘0’ to this bit enables the capture of a new error in
the PCI bus error capture registers (PCI_EACR,
PCI_EDCR, and PCI_ECCR).
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
B-3
Reference Manual (Rev 1) Errata
9.11.2.22, 9-62
10.8, 10-8
In Figure 9-54, the reset value row has a misplaced set bit. It currently shows bit
4 as reset to 1 (0000_0000_0001_0000). It should show bit 5—CFG_LOCK—as
reset to 1 (0000_0000_0010_0000).
In Figure 10-5, the access of SCCR[PCI_MODE, PCI_MODCK] (bits 23 and 24)
should be shown as read/write (R/W). Bits 25–28 (PCIDF) are the only read-only
bits in SCCR.
10.8, 10-9
In Table 10-2, add the following to the description of CLPD:
Note: When the core is disabled, CLPD must be cleared.
10.10, 10-11
Replace 2.5 V references. Replace the second and fourth sentences of the
paragraph with the following:
Internal logic can be fed by a lower voltage source; this considerably reduces
power consumption....The VCCSYN value is equal to the internal supply. For
more information, refer to Section 1.2, “Electrical and Thermal Characteristics,”
in the hardware specifications document available at wwww.freescale.com.
11.3.1, 11-16
In Table 11-4, add the following to the description of BRx[V]:
Note: If BRx has been selected as the SDRAM controller and the valid bit has been
set (BRx[31] = 1), the SDRAM controller must be invalidated by doing the
following:
1. Disable the SDRAM refresh service by clearing PSDMR/LSDMR[RFEN].
2. Wait at least 100 60x-bus clock cycles.
3. Clear BRx[V].
11.3.3, 11-23
11.3.3, 11-24
11.6.4.2, 11-81
In Table 11-8, the description of PSDMR[RFEN] should state the following
(changes appear in boldface):
Indicates that the SDRAM needs refresh services.
In Table 11-8, add the following to the description of PSDMR[LDOROPRE]:
Note: A value of 0b00 (0 clock cycles) gives the longest time while a value of
0b10 (–2 clock cycles) gives the least.
Add the following below “Note that on the local bus...”:
Also, note that for the UPM address multiplexing to work, if the UPM is on the
60x bus, PSDMR[PBI] needs to be zero. If the UPM is on the local bus,
LSDMR[PBI] needs to be zero. This means that UPM address multiplexing does
not work when the SDRAM controller is on the same bus and PBI is set to one.
14.3.5, 14-7
Table 14-2 incorrectly lists IDMA CPM priority levels. IDMA option 1 should
appear immediately before the emergency priority (not after as shown) and IDMA
option 2 should appear immediately after the emergency priority (not as priority
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
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Freescale Semiconductor
Reference Manual (Rev 1) Errata
#24 as shown). IDMA option 3 is shown correctly as the last request in
prioritization of CPM peripherals. The table should appear as follows:
Priority
Request
1-3
4
Unchanged
IDMA[1–4] emulation (default—option 1)
1
5
Emergency (from FCCs, MCCs, and SCCs)
1
6
IDMA[1–4] emulation (option 2)
7-33
34
Same relative priority
1
IDMA[1–4] emulation (option 3)
1
The priority of each IDMA channel is programmed independently. See the
RCCR[DRxQP] description in Section 14.3.7, “RISC Controller Configuration Register
(RCCR).”
14.3.7, 14-10
In Table 14-3, the description for RCCR[ERAM] pertaining to HiP4 devices
(ERAM = 16–19), the starting offset for all of the additional 8 Kbytes of dual-port
RAM should be 0x4000 (not 0x0000). Also, it should read “RAM microcode
execution...”. The description should appear as follows (changes in boldface):
ERAM .25-µm (HiP4) devices: ERAM[16-19]. Enable RAM microcode. Configure as instructed in the
download process of a Freescale-supplied RAM microcode package.
0000 Disable microcode program execution from the dual-port RAM. (That is, microcode
execution starts at ROM address 0x0000 after reset.)
In the following configurations, RAM microcode execution starts at address 0x0000 after reset:
0010 Microcode uses the first 2 Kbytes of the dual-port RAM + 8 Kbytes starting from 0x4000.
0100 Microcode uses the first 4 Kbytes of the dual-port RAM + 8 Kbytes starting from 0x4000.
0110 Microcode uses the first 6 Kbytes of the dual-port RAM + 8 Kbytes starting from 0x4000.
1000 Microcode uses the first 8 Kbytes of the dual-port RAM + 8 Kbytes starting from 0x4000.
1010 Microcode uses the first 10 Kbytes of the dual-port RAM + 8 Kbytes starting from 0x4000.
1100 Microcode uses the first 12 Kbytes of the dual-port RAM + 8 Kbytes starting from 0x4000.
In the following configurations, microcode execution starts at RAM address 0x4000 after reset:
0011 Microcode uses 2 Kbytes starting from dual-port RAM address 0x4000.
0101 Microcode uses 4 Kbytes starting from dual-port RAM address 0x4000.
0111 Microcode uses 6 Kbytes starting from dual-port RAM address 0x4000.
1001 Microcode uses 8 Kbytes starting from dual-port RAM address 0x4000.
Note: All other configurations not listed are reserved.
14.3.10, 14-12
Replace the current paragraph with the following.
Associated with each version of CPM microcode is a number (REV_NUM) that
uniquely identifies that specific microcode. This number is hard-coded into the
microcode which is stored in the CPM’s internal ROM. At power-up, the
communication processor (CP) reads this number and proceeds to store it into the
miscellaneous parameter RAM portion of the CPM's internal dual-port RAM
(DPR). The user can then access this location in DPR to determine which version
of CPM microcode is contained in that device. Table 14-5 describes which
microcode version numbers are associated with each silicon revision.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
B-5
Reference Manual (Rev 1) Errata
Also, replace the description of REV_NUM in Table 14-15 with the following
(changes or additions appear in boldface):
RAM Base + 0x8AF0 REV_NUM Hword
Microcode revision number. If working with newer silicon than what is
shown below, consult the product page on the web.
For .29-µm (HiP3) devices: Rev A.1—0x0001
Rev B.2—0x003B
Rev C.2—0x007B
For .25-µm (HiP4) devices: Rev A.0—0x000D
Rev B.1—0x002D
Rev C.0—0x002D
15.4.5, 15-15
15.5.2, 15-19
In the first and third items under the ‘Static routing’ bullet, it should state TDM
rather than TSA.
In Table 15-5, add the following to the definition of configuration 00 for
RFSDx (SIxMR[6–7]) and TFSDx (SIxMR[14–15]):
If frame sync delay is not used and if a frame sync is issued early during the last
bit of the previous frame, data corruption can occur on all subsequent frames. To
avoid this problem, program a 1-, 2-, or 3-bit sync delay.
19.7.1, 19-15
Under ‘Note,’ replace “do one of the following” with “do the following.” Then
replace the two bulleted items with the following:
First, initialize all registers, parameter RAM, and buffer descriptors ready
(TxBD[R]=1) for an IDMA. Then, write an IDMA START command to CPCR
and wait for CPCR[FLG] to be cleared. Then, wait an additional 50 CPM clocks.
At this point, it is safe to program the parallel port registers for the IDMA.
19.7.1.1, 19-16
Add the following:
When an IDMA is in external request mode and its DREQ is set to level-sensitive
mode, the IDMA requests service by the CPM whenever its DREQ signal is
active. This is true regardless of whether or not an IDMA is in progress. Therefore,
whenever the IDMA's DREQ is active, all CPM peripherals with a priority lower
than the IDMA do not receive service. The IDMA priority can be configured via
RCCR[DRxQP] and, because DREQ may be active for long periods, systems that
configure DREQ to be level-sensitive must select priority option 3 for DRxQP to
avoid starving other CPM peripherals (see Table 14-2 and Table 14-3). If more
than one IDMA is given the same priority, the lower-numbered IDMA has priority
over a higher numbered IDMA. For example, if both IDMA3 and IDMA4 are
given priority option 3, then IDMA3 will have priority over IDMA4.
In addition to the issue described in the previous paragraph, there is another issue
to consider when an IDMA is in external request mode and its DREQ is set to
level-sensitive mode. When these are true and the external peripheral device is
controlled by one of the memory controllers of PowerQUICC II, such as the UPM
or GPCM controller, DREQ must be negated before t
to prevent DREQ
max
negation from triggering an extra IDMA transfer cycle. Refer to the following
figure. Note that T = 2 x CPM_CLK. In the example shown, CPM_CLK = 133
MHz, with an approximate clock cycle of 7.5 ns. Therefore, T = 15 ns and DREQ
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
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Freescale Semiconductor
Reference Manual (Rev 1) Errata
must be negated no later than 15 ns after the first rising edge of the bus clock after
CS negation for the peripheral.
19.7.2, 19-17
19.8.2, 19-19
Add the following note:
When DREQ is level-sensitive and DONE is an input to the PowerQUICC II, the
system design must ensure that DONE is not asserted while DREQ is also
asserted. In other words, the system must not request IDMA service and
termination at the same time.
In Table 19-4, the following parameters must be initialized by the user. Their
names should appear in boldface, as do other user-initialized parameters
elsewhere in the manual: IBASE, DCM, IBDPTR, DPR_BUF, SS_MAX, STS,
DTS, ISTATE.
Change the description of ISTATE in Table 19-4 to, “Internal use. Must be cleared
before every START_IDMA command.”
19.8.5, 19-25
20.3.6, 20-22
Add the following note after the first paragraph:
The CPM always clears the valid (V) bit in an IDMA buffer descriptor before
setting the bits in IDSR that may cause an interrupt to the core.
In the previous version of this document it was incorrectly stated that, in the lower
left corner of Figure20-13, “DPLL Receiver Block Diagram,” the label
“RENC π NRZI” should be replaced by “RENC = NRZI.” This is incorrect.
The correct change is as follows: it should state “RENC ≠ NRZI” and not
“RENC π NRZI.”
29.5, 29-8
Note that the previous version of this document incorrectly stated that TxBD[R]
must be set twice. Instead, it is TOD that must be set twice, as stated below:
Replace the first paragraph with the following (changes or additions appear in
boldface):
If no frame is being sent by the FCC, the CP periodically polls the R bit of the next
TxBD to see if the user has requested a new frame/buffer to be sent. Polling
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
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Reference Manual (Rev 1) Errata
occurs every 256 serial transmit clocks. The polling algorithm depends on the
FCC configuration, as shown in the following equations:
Fast Ethernet:
10BaseT:
256 clocks / 25 MHz = 10 µs
256 clocks / 2.5 MHz = 100 µs
The user, however, can request that the CP begin processing the new frame/buffer
without waiting the normal polling time. For immediate processing, after setting
TxBD[R], set the transmit-on-demand (TOD) bit in the transmit-on-demand
register (FTODR) twice to activate. If TOD is set only once, the new
frame/buffer will not be transmitted until the next periodic polling request.
29.10.1.1, 29-16
30.2.2, 30-7
In step 3 of the re-initialization procedure, the command issued from CPCR must
be a RESTART_TX, not INIT_TX_PARAMS.
In the second paragraph, replace the sentence that begins, “The cell includes...,”
with the following (changes appear in boldface):
The cell includes: 4 bytes ATM cell header, 1 byte HEC, which can be checked
by setting FPSMR[HECC] (refer to Table 30-47), and 48 bytes payload.
[Note that the description of HECC referred to above is also contained in this
document as an errata for Section 30.13.2. The description is not shown in the
manual]
30.10.1.3, 30-43
Add GBL at bit 2 in Figure 30-23 and Table 30-14 as shown in the following:
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
Field
0
0
GBL
0
0
0
ALB CTB REM
0
IMA_EN UEAD CUAB EVPT
0
ALM
1
MPC8264 and MPC8266 only.
2
GBL Global. Asserting GBL enables snooping of connection tables. GBL should not be asserted if any of
the related DMAs will access the local bus.
30.10.5.3, 30-74
30.10.5.4, 30-76
In Table 30-34, the alignment column for AAL1 and ALL5 receive buffers should
state “Burst-aligned (recommended).”
In Table 30-35, the description for RXDBPTR at offset 0x04 should state the
following (change appears in boldface):
Rx data buffer pointer. Points to the first location of the associated buffer; may
reside in internal or external memory. It is recommended that the pointer be
burst-aligned.
30.10.5.5, 30-77
In Table 30-35, the description for RXDBPTR at offset 0x04 should state the
following (change appears in boldface):
Rx data buffer pointer. Points to the first location of the associated buffer; may
reside in internal or external memory. It is recommended that the pointer be
burst-aligned.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
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Freescale Semiconductor
Reference Manual (Rev 1) Errata
30.10.7, 30-84
In Table 30-41, change the description of UTOPIAE to the following:
0x00
UTOPIAE
Hword Counts cells dropped as a result of UTOPIA/ATM protocol violations.
Violations include the following:
1. Parity error
2. HEC error
3. Invalid timing of RxSOC.
If RxClav is asserted for the selected PHY, RxSOC should be asserted the
cycle immediately following the assertion of RXENB. A violation occurs if
RxSOC is not asserted at that time (that is, it is late or is missing).
30.12.1, 30-87
Add the following at the beginning of the section:
Cell transfer on an ATM device (with single or multiple PHYs) uses cell-level
handshaking as defined in the UTOPIA standards. The FCC does not pause cell
transmission by the PHY and does not stop receiving cells from the PHY.
30.12.1, 30-87
30.12.1, 30-87
In Figure 30-57, “UTOPIA Master Mode Signals,” replace “TxCLAV[3–0]” with
“TxCLAV[3–0]/TxClav” and “RxCLAV[3–0]” with “RxCLAV[3–0]/RxClav.”
In Table 30-44, make the following additions:
Add “/TxClav” to “TXCLAV[3-0]”
Add “/RxClav” to “RXCLAV[3-0]”
Add a cross-reference to Section 30.10.7, “UNI Statistics Table,” at the end of
RxPRTY’s description.
30.12.1.1, 30-88
30.12.1.1, 30-88
The first bulleted item should read “Direct polling uses CLAV[3–0] with PHY
selection using ADD[1–0]...”
Replace the first sentence of the second bulleted item with the following:
Single CLAV polling uses Clav and ADD[4–0].
30.12.2, 30-89
30.12.2, 30-89
Add a cross-reference to Section 30.10.7, “UNI Statistics Table,” to the end of
RxPRTY’s description.
Add the following to the beginning of the section:
In UTOPIA slave mode (single or multiple PHY), cells are transferred using
cell-level and octet-level handshakes as defined by the UTOPIA L2 standard. The
FCC allows cell transfer to be halted or paused. If the master negates TXENB, the
cell that the FCC is transmitting is halted. If the master negates RXENB, the cell
that the FCC is receiving is paused. Note the following restriction on halting a cell
transfer: there cannot be a halt immediately before the transfer of the last data
word. There is no restriction on pausing a cell transfer.
30.13.2, 30-91
In Figure 30-59, the address row should appear as follows:
0
3
4
7
8
9
10
11
15
31
Addr
0x11304 (FPSMR1), 0x11324 (FPSMR2), 0x11344(FPSMR3)
16 17
18
19
20
21
22
23
24
25
26
27
28
29
30
Addr
0x11306 (FPSMR1), 0x11326 (FPSMR2), 0x11346 (FPSMR3)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
B-9
Reference Manual (Rev 1) Errata
30.13.2, 30-92
In Table 30-47, replace the description of TPRI, TUDC, RUDC, and UPLM with
the following (changes appear in boldface):
18
TPRI
Transmitter priority. Used to adjust the default priority of the FCC transmitter. It is strongly
recommended to set TPRI when in multi-PHY mode, or in single-PHY mode if the maximal
bit rate (either internal or external rate) is higher than that of the other FCCs; for other
modes, it should remain cleared.
0 Default operation
1 Prevents elevation to emergency mode
Refer to Table 14-2.
19
20
27
TUDC Transmit user-defined cells
1
0 Regular 53-byte cells (Disable this mode for IMA support )
1 User-defined cells
RUDC Receive user-defined cells
1
0 Regular 53-byte cells (Disable this mode for IMA support )
1 User-defined cells
UPLM UTOPIA polling mode.
0 Single Clav polling. Polling is done using Add[4–0] and Clav. Selection is done using
Add[4–0]. Up to 31 PHYs can be polled.
1 Direct polling. Polling is done using Clav[3–0]. Selection is done using Add[1–0]. Up to 4
PHYs can be polled.
30
HECC Receive HEC check
0 Do not check Rx HEC
1 Check Rx HEC. HEC errors are reported in UTOPIAE counter (see Section 30.10.7, “UNI
Statistics Table”). This option can be used only in UTIPIA 8-bit data bus size.
30.13.3. 30-94
In Table 30-48, replace the description of TIRU with the following:
5
TIRU Transmit internal rate underrun. A cumulative lag of seven cells has formed between the
programmable rate and the actual rate for a specific PHY. A transmit internal rate counter expired
and a cell was not sent, either because of slow CPM performance or slow PHY performance. TIRU
may be set only when using transmit internal rate mode; see Section 30.13.4, “FCC Transmit
Internal Rate Registers (FTIRRx) (FCC1 and FCC2 Only).”
30.13.4, 30-94
30.13.4, 30-94
Add the following note at the beginning of this section:
The source clock of the internal rate timers is the BRG clock, which is configured
in CMXUAR (refer to Section 16.4.1, “CMX UTOPIA Address Register”). The
frequency of this clock must be less than one half of the FCC Tx clock of the
UTOPIA interface.
Replace the first paragraph with the following (updated portion in boldface):
The first four PHY devices (address 00– 03) on FCC1 and FCC2 have their own
transmit internal rate registers (FTIRRx_PHY0–FTIRRx_PHY3) for use in
transmit internal rate mode. In this mode, the total transmission rate is determined
by FCC internal rate timers. As a master, the controller only polls the PHY’s
Clav status at the rate determined by the internal rate. As a slave, the
controller attempts to insert cells into the FIFO at the internal rate. The
controller can handle a lag of up to seven cells per PHY between the
programmable and actual bus rate. When the cell count mismatch reaches
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
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seven, TIRU event is reported, see Section 30.13.3, “ATM Event Register
(FCCE)/Mask Register (FCCM)”. Note that a mismatch occurs if the PHY
rate or the CPM performance are lower then the internal rate. FTIRRx,
shown in Figure 30-61, includes the initial value of the internal rate timer. The
source clock of the internal rate timers is supplied by one of four baud-rate
generators selected in CMXUAR; see Section 16.4.1, “CMX UTOPIA Address
Register (CMXUAR)”. Note that in slave mode, FTIRRx_PHY0 is used
regardless of the slave PHY address.
30.13.4, 30-95, -96
Under “Example” replace the second sentence and the equation with the following
(changes appear in boldface):
If the CPM clock is 133 MHz and the BRG CLK is 66 MHz, the BRG should
be programmed to divide the CPM clock by 181 to generate cell transmit requests
every 362 system clocks:
(66MHz × (53 × 8))
--------------------------------------------------
= 181
155.52Mbps
33.3.2.1, 33-13
After the last paragraph of Section 33.3.2.1, add the following new section:
33.3.2.1.1 TRL Service Latency
NOTE
The functionality described in this section is available only with the latest
RAM microcode package.
This optional feature allows the user to change the IMA APC behavior upon TRL request. When
enabled the TRL request will pass a programmable number of cells to the Tx queue of the links in
an IMA group. This can be used in order to suppress the TRL from consuming a large amount of
bandwidth before another cell is transmitted. The TRL request normally places a cell in a queue for
N links where the group contains N links; after this happens then a non_TRL link is free to pass a
cell over the UTOPIA interface. The delay for the TRL can be long and in some cases the TC layer
FIFO can underrun. This feature can be used to ensure that TRL and non-TRL requests are handled
in the same manner—one cell in one cell out to the transmit queues. The non-TRL requests will
also trigger APC iterations when this feature is enabled. When using this feature, the depth of the
TRL transmit queue must equal the non-TRL queues.
33.4.3, 33-26,-27
Delete the last row in Table 33-3 and add the following rows at the bottom:
0x68
0x6C
—
—
Reserved. Must be programmed to zero during initialization.
ITPGRPO
Hword
Required for optional TRL Service Latency enhancement only.
IMA Temp Group Order - Points to the base of a 2byte temp pointer storage
per group. Software initialized before FCC is enabled. Microcode managed
parameter.
0x6E–0x7F —
—
Reserved. Must be programmed to zero during initialization.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
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33.4.1.1, 33-29
Add the following two rows to the bottom of Table 33-5:
0x0E
IASNCCTR
Byte
Required for optional TRL Service Latency enhancement only.
IMA APC Scheduled Number of Cells Counter - Number of cells passed to
the groups links upon request. Initialize to IASNC.
0x0F
IASNC
Byte
Required for optional TRL Service Latency enhancement only.
IMA APC Scheduled Number of Cells - reset for IASNCtr. Number of cells
passed to the groups links upon request. Recommended value is 1.
33.4.4.1.1, 33-29
Add ISIE to Figure 33-14 and Table 33-6, as shown in the following:
0
2
3
4
5
6
7
Field
—
TXSC
ISIE
CTC
ICPC
5
ISIE
Required for optional TRL Service Latency enhancement only.
IMA Scheduler Split Iterations Enable
0 - APC is not split, TRL completes round robin distribution of cells.
1 - APC split, both TRL and non-TRL requests distribute cells to the transmit queues.
33.4.4.1.2, 33-30
Add GTE and TRQS to Figure 33-15 and Table 33-7, as shown in the following:
0
1
2
3
4
5
6
7
Field
TSTF
TIMSTF
GTE
TRQS
ELX
—
ICH
ICPCA
2
3
GTE
Go to end flag - TRL has requested 2 times before round robin distribution has completed or
link will underrun and is still due a cell from round robin distribution. Microcode managed
parameter initialize to 0. Used for optional TRL Service Latency enhancement only.
TRQS
TRL Request - TRL has requested therefore 1 round robin distribution of cells and is yet to be
completed. Microcode managed parameter initialize to 0. Used for optional TRL Service
Latency enhancement only.
33.4.4.2, 33-35
In Table 33-10 replace the descriptions of offsets 0x2C and 0x30 with the
following:
0x2C
0x30
—
LINK_DCBO
Word
Word
Reserved. Must be initialized to zero at group startups.
Link DCB overflow interrupt indication. Bit array identifying which links
have issued a link DCB overflow (DCBO) interrupt. This parameter
ensures that only one DCBO interrupt is generated per event.
Microcode managed parameter. Initialize to zero at group startup.
33.4.5.1.2, 33-40
Add LDC to Figure 33-22 and Table 33-17, as shown in the following:
0
1
2
3
4
5
6
7
Field
LSTF
LIMSTF
LSTLFIP
LGSU
TQSU
LDC
—
5
LDC
Link Due Cell. Link is due cell from round robin distribution. Microcode managed parameter
initialize to 0. Used for optional TRL Service Latency enhancement only.
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Reference Manual (Rev 1) Errata
33.4.7.1, 33- 47
Add DSL to Offset + 0 in Figure 33-29 and Table 33-23, as shown in the
following:
0
1
2
3
5
6
7
8
9
10
11
12
13
14
15
OFFSET + 0
V
—
W
—
TQU TQO
—
DSL LS DCBO LDS GDS IFSD IFSW
OFFSET + 2 L/G
NUM
9
DSL
DCB synchronization lost. This interrupt is issued when a link in a group with IGRSTATE[GDSS] = 11
loses synchronization, and the link enters HUNT state at the IFSM.
33.4.10, 33-54
Add the following new section:
33.4.10 Changing IMA Version
A new CPCR command has been added to the IMA microcode to change the IMA version
on-the-fly without software intervention. Use the following procedure:
1. Before issuing the command, the user should initialize the COMM_INFO fields in the
parameter RAM as described in Figure Table 33-13..
2. To issue this FCC command, refer to Section 20.4, “Command Set.” Use opcode 1101 (0xD).
0
8
9
11
12
15
0x86
0x88
0x8A
—
ITG
—
Filler CRC
—
IV
Table 33-13. COMM_INFO Field
m
Offset
Bits
Name
Description
0x86
0–8
—
Reserved, should be cleared.
9–11 ITG
IMA transmit group. Program to the IMA group number [0–7] multiplied by 16 bytes.
For example, if the IMA group number = 3, program ITG to 0x30.
12–15 —
Reserved, should be cleared.
0x88
0x8A
0–15 Filler CRC Filler cell CRC. Set to 0xC602 (for IMA version 1.0) or 0xD902 (for IMA version 1.1)
0–13
—
Reserved, should be cleared.
14–15 IV
IMA version
00 Reserved
01 IMA version 1.0
10 Reserved
11 IMA version 1.1
3. Wait for the CPCR[FLG] to be cleared by the CPM before issuing a new CP command. Refer
to Section 20.4, “Command Set.”
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33.5.4.5.1, 33-65
The order of steps is incorrect. Current step #2 (“Use the new group order table...”)
should immediately follow current step # 6 (“Software should wait...”). Therefore,
current step # 6 becomes the new step #5 and current step #2 becomes the new step
#6.
33.5.4.10, 33-70
Replace #4 and #7 with the following:
4. GDS (Group Delay Synchronized)—Group delay synchronized achieved or group delay
synchronized not achieved. In some cases, it is not possible for the GDS to complete. GDS can not
complete if a link experiences problems during the GDS process - for example losing SYNC state
for the IFSM. If this occurs, it is not possible to determine the links true differential delay with
respect to other member links of the group. In order to determine if the GDS process completed
successfully, the microcode will set IGRSTATE[GDSS] to either of the following values after the
GDS interrupt has been generated:
— IGRSTATE[GDSS] = 00 - GDS process failed, a link lost IFSM SYNC during GDS process
— IGRSTATE[GDSS] = 11 - GDS process completed
Software can then read IGRSTATE[GDSS] and use this status information before deciding whether
to change the links to the active state or to try and resynchronize again at the group level. In
addition to the above status information, the ILRSTATE[ADD_NEW_M] bit of the link that caused
the failure of the GDS process will be flipped such that it is logically inverted with respect to the
ILRCNTL[ADD_NEW] bit. It is recommended however, that software, after GDS failure and
when restarting the GDS process, changes all of the links in the group to the group unassigned state
and then update the link and group parameters to their default values before starting the GDS
process again. Note that a link losing SYNC during the GDS process can cause DCBO interrupt
for other links in the group. If this situation occurs, the GDS process should be restarted as
described above.
7. DSL (DCB Synchronization Lost)—Indicates that a link in a group with IGRSTATE[GDSS] = 11
loses synchronization and enters the HUNT state at the IFSM. When this interrupt occurs, the link
should be removed by software, and the CPM will no longer perform the automatic LASR
procedure. Note that when the interrupt is generated, the ILRSTATE[DL] bit is set, and the
software should clear the IMA group and link receive state information as described above for the
GDS interrupt.
34.2, 34-4
In the top center of Figure 34-2 “DBB bus” should be replaced with “60x bus.”
Replace the second paragraph after Table 35-10 with the following:
35.19, 35-27
The receive buffer pointer, which points to the first location of the associated data
buffer, can reside in external memory. This value must be divisible by 16.
38.4.1.1, 38-10
In Example 3, the representation of data transmitted when REV = 0 and REV = 1
should appear as follows (changes appear in boldface):
with REV=0, the string transmitted, a byte at a time with lsb first is:
first nmlk_jihg__vuts_r last
with REV=1, the string is half-word reversed:
msb nmlk_jihg__vuts_r lsb
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Reference Manual (Rev 1) Errata
and transmitted a byte at a time with lsb first:
first r_stuv_ghij_klmn last
39.4.3, 39-8
In Table 39-3, the description of DIV should read as follows (changes appear in
boldface):
2
0–7
DIV Division ratio 0–7. Specifies the divide ratio of the BRG divider in the I C clock generator. The output
of the prescaler is divided by 2 * ([DIV0–DIV7] + 3 + (2 * I2MOD[FLT])) and the clock has a 50% duty
cycle. DIV must be programmed to a minimum value of 3 if the digital filter is disabled
(I2MOD[FLT] = 0) and 6 if it is enabled (I2MOD[FLT] = 1).
40-5, 40-10
In Table 40-5, add TDM_A1:L1TXD to PA9 in the column for PSORA = 1 and
PDIRA = 0, as shown below:
Pin Function
PSORA = 0
PSORA = 1
Pin
Default
Input
PDIRA = 0 (Input, or Default
In/out if Specified) Input
PDIRA = 1 (Output) PDIRA = 0 (Input)
SMC2: SMTXD
PDIRA = 1 (Output)
PA9
TDM_A1: L1TXD[0]
TDM_A1: L1TXD
GND
Output, nibble
Inout, serial
40-5, 40-16
In Table 40-7, the note attached to SPI: SPISEL at PC1 is incorrect. It should refer
to note 2 (“available only when the primary option for this function is not used”)
and not note 3.
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Glossary of Terms and Abbreviations
The glossary contains an alphabetical list of terms, phrases, and abbreviations used in this book.
Some of the terms and definitions included in the glossary are reprinted from IEEE Std. 754-1985,
IEEE Standard for Binary Floating-Point Arithmetic, copyright ©1985 by the Institute of
Electrical and Electronics Engineers, Inc. with the permission of the IEEE.
Note that some terms are defined in the context of how they are used in this book.
A
Architecture. A detailed specification of requirements for a processor or computer
system. It does not specify details of how the processor or computer
system must be implemented; instead it provides a template for a family of
compatible implementations.
Asynchronous exception. Exceptions that are caused by events external to the
processor’s execution. In this document, the term ‘asynchronous
exception’ is used interchangeably with the word interrupt.
Atomic access. A bus access that attempts to be part of a read-write operation to the
same address uninterrupted by any other access to that address (the term
refers to the fact that the transactions are indivisible). The PowerPC
architecture implements atomic accesses through the lwarx/stwcx.
instruction pair.
Autobaud. The process of determining a serial data rate by timing the width of a
single bit.
B
Big-endian. A byte-ordering method in memory where the address n of a word
corresponds to the most-significant byte. In an addressed memory word,
the bytes are ordered (left to right) 0, 1, 2, 3, with 0 being the
most-significant byte. See Little-endian.
Blockage. A pipeline stall that occurs when an instruction occupies an execution
unit and prevents a subsequent instruction from being dispatched.
Boundedly undefined. A characteristic of results of certain operations that are not
rigidly prescribed by the PowerPC architecture. Boundedly- undefined
results for a given operation may vary among implementations, and
between execution attempts in the same implementation.
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Glossary-1
Although the architecture does not prescribe the exact behavior for when results
are allowed to be boundedly undefined, the results of executing instructions in
contexts where results are allowed to be boundedly undefined are constrained to
ones that could have been achieved by executing an arbitrary sequence of defined
instructions, in valid form, starting in the state the machine was in before
attempting to execute the given instruction.
Breakpoint. A programmable event that forces the core to take a breakpoint exception.
Burst. A bus transfer whose data phase consists of a sequence of transfers. For example,
on a 64-bit bus, a four-beat burst can transfer four, 64-bit double words.
Bus parking. A feature that optimizes the use of the bus by allowing a device to retain bus
mastership without having to rearbitrate.
C
Cache. High-speed memory component containing recently-accessed data and/or
instructions (subset of main memory).
Cache coherency. An attribute in which an accurate and common view of memory is
provided to all devices that share the a memory system. Caches are coherent if a
processor performing a read from its cache is supplied with data corresponding to
the most recent value written to memory or to another processor’s cache.
Cache flush. An operation that removes from a cache any data from a specified address
range. This operation ensures that any modified data within the specified address
range is written back to main memory. This operation is generated typically by a
Data Cache Block Flush (dcbf) instruction.
Caching-inhibited. A memory update policy in which the cache is bypassed and the load
or store is performed to or from main memory.
Cast-outs. Cache blocks that must be written to memory when a cache miss causes a cache
block to be replaced.
Changed bit. One of two page history bits found in each page table entry (PTE). The
processor sets the changed bit if any store is performed into the page. See also
Page access history bits and Referenced bit.
Clear. To cause a bit or bit field to register a value of zero. The opposite of set.
Context synchronization. An operation that ensures that all instructions in execution
complete past the point where they can produce an exception, that all instructions
in execution complete in the context in which they began execution, and that all
subsequent instructions are fetched and executed in the new context. Context
synchronization may result from executing specific instructions (such as isync or
rfi) or when certain events occur (such as an exception).
Copy-back. An operation in which modified data in a cache block is copied back to
memory.
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Critical-data first. An aspect of burst accesses that allow the requested data (typically a
word or double word) in a cache block to be transferred first.
D
Denormalized number. A nonzero floating-point number whose exponent has a reserved
value, usually the format's minimum, and whose explicit or implicit leading
significand bit is zero.
Direct-mapped cache. A cache in which each main memory address can appear in only
one location within the cache, operates more quickly when the memory request is
a cache hit.
Direct-store. Interface available on processors that implement the PowerPC architecture
only to support direct-store devices from the POWER architecture. When the T bit
of a segment descriptor is set, the descriptor defines the region of memory that is
to be used as a direct-store segment. Note that this facility is being phased out of
the architecture and will not likely be supported in future devices. Therefore,
software should not depend on it and new software should not use it.
E
Effective address (EA). The 32- or 64-bit address specified for a load, store, or an
instruction fetch. This address is then submitted to the MMU for translation to
either a physical memory address or an I/O address.
Exception. A condition encountered by the processor that requires special, supervisor-level
processing.
Exception handler. A software routine that executes when an exception is taken.
Normally, the exception handler corrects the condition that caused the exception,
or performs some other meaningful task (that may include aborting the program
that caused the exception). The address for each exception handler is identified by
an exception vector offset defined by the architecture and a prefix selected via the
MSR.
Extended opcode. A secondary opcode field generally located in instruction bits 21–30,
that further defines the instruction type. All PowerPC instructions are one word in
length. The most significant 6 bits of the instruction are the primary opcode,
identifying the type of instruction. See also Primary opcode.
Execution synchronization. A mechanism by which all instructions in execution are
architecturally complete before beginning execution (appearing to begin
execution) of the next instruction. Similar to context synchronization but doesn't
force the contents of the instruction buffers to be deleted and refetched.
Exponent. In the binary representation of a floating-point number, the exponent is the
component that normally signifies the integer power to which the value two is
raised in determining the value of the represented number. See also Biased
exponent.
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Glossary-3
F
Fetch. Retrieving instructions from either the cache or main memory and placing them into
the instruction queue.
Fully-associative. Addressing scheme where every cache location (every byte) can have
any possible address.
G
General-purpose register (GPR). Any of the 32 registers in the general-purpose register
file. These registers provide the source operands and destination results for all
integer data manipulation instructions. Integer load instructions move data from
memory to GPRs and store instructions move data from GPRs to memory.
H
I
Harvard architecture. An architectural model featuring separate caches for instruction
and data.
IEEE 754. A standard written by the Institute of Electrical and Electronics Engineers that
defines operations and representations of binary floating-point arithmetic.
Illegal instructions. A class of instructions that are not implemented for a particular
processor that implement the PowerPC architecture. These include instructions
not defined by the PowerPC architecture. In addition, for 32-bit implementations,
instructions that are defined only for 64-bit implementations are considered to be
illegal instructions. For 64-bit implementations instructions that are defined only
for 32-bit implementations are considered to be illegal instructions.
Implementation. A particular processor that conforms to the PowerPC architecture, but
may differ from other architecture-compliant implementations for example in
design, feature set, and implementation of optional features. The PowerPC
architecture has many different implementations.
Implementation-dependent. An aspect of a feature in a processor’s design that is defined
by a processor’s design specifications rather than by the PowerPC architecture.
Implementation-specific. An aspect of a feature in a processor’s design that is not required
by the PowerPC architecture, but for which the PowerPC architecture may provide
concessions to ensure that processors that implement the feature do so
consistently.
Imprecise exception. A type of synchronous exception that is allowed not to adhere to the
precise exception model (see Precise exception). The PowerPC architecture
allows only floating-point exceptions to be handled imprecisely.
Internal bus. The bus connecting the core and system interface unit (SIU).
Instruction latency. The total number of clock cycles necessary to execute an instruction
and make ready the results of that instruction.
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Interrupt. An asynchronous exception. On PowerPC processors, interrupts are a special
case of exceptions. See also asynchronous exception.
L
Latency. The time an operation requires. For example, execution latency is the number of
processor clocks an instruction takes to execute. Memory latency is the number of
bus clocks needed to perform a memory operation.
Least-significant bit (lsb). The bit of least value in an address, register, data element, or
instruction encoding.
Least-significant byte (LSB). The byte of least value in an address, register, data element,
or instruction encoding.
Little-endian. A byte-ordering method in memory where the address n of a word
corresponds to the least-significant byte. In an addressed memory word, the bytes
are ordered (left to right) 3, 2, 1, 0, with 3 being the most-significant byte. See
Big-endian.
M
Master. The name given to a bus device that has been granted control, or mastership, of the
bus.
Memory access ordering. The specific order in which the processor performs load and
store memory accesses and the order in which those accesses complete.
Memory controller. A unit whose primary function is to control the external bus memories
and I/O devices.
Memory coherency. An aspect of caching in which it is ensured that an accurate view of
memory is provided to all devices that share system memory.
Memory consistency. Refers to agreement of levels of memory with respect to a single
processor and system memory (for example, on-chip cache, secondary cache, and
system memory).
Memory management unit (MMU). The functional unit that is capable of translating an
effective (logical) address to a physical address, providing protection
mechanisms, and defining caching methods.
Microarchitecture. The hardware details of a microprocessor’s design. Such details are
not defined by the PowerPC architecture.
Mnemonic. The abbreviated name of an instruction used for coding.
Modified state. When a cache block is in the modified state, it has been modified by the
processor since it was copied from memory. See MESI.
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Glossary-5
Munging. A modification performed on an effective address that allows it to appear to the
processor that individual aligned scalars are stored as little-endian values, when
in fact it is stored in big-endian order, but at different byte addresses within double
words. Note that munging affects only the effective address and not the byte order.
Note also that this term is not used by the PowerPC architecture.
Most-significant bit (msb). The highest-order bit in an address, registers, data element, or
instruction encoding.
Most-significant byte (MSB). The highest-order byte in an address, registers, data
element, or instruction encoding.
N
O
No-op. No-operation. A single-cycle operation that does not affect registers or generate
bus activity.
OEA (operating environment architecture). The level of the architecture that describes
PowerPC memory management model, supervisor-level registers,
synchronization requirements, and the exception model. It also defines the
time-base feature from a supervisor-level perspective. Implementations that
conform to the PowerPC OEA also conform to the PowerPC UISA and VEA.
Optional. A feature, such as an instruction, a register, or an exception, that is defined by
the PowerPC architecture but not required to be implemented.
Out-of-order. An aspect of an operation that allows it to be performed ahead of one that
may have preceded it in the sequential model, for example, speculative operations.
An operation is said to be performed out-of-order if, at the time that it is
performed, it is not known to be required by the sequential execution model. See
In-order.
Out-of-order execution. A technique that allows instructions to be issued and completed
in an order that differs from their sequence in the instruction stream.
Overflow. An error condition that occurs during arithmetic operations when the result
cannot be stored accurately in the destination register(s). For example, if two
32-bit numbers are multiplied, the result may not be representable in 32 bits.
P
Pace control. Controls the rate of the data flow between a master and slave.
Page. A region in memory. The OEA defines a page as a 4-Kbyte area of memory, aligned
on a 4-Kbyte boundary.
Page fault. A page fault is a condition that occurs when the processor attempts to access a
memory location that does not reside within a page not currently resident in
physical memory. On processors that implement the PowerPC architecture, a page
fault exception condition occurs when a matching, valid page table entry (PTE[V]
= 1) cannot be located.
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Physical memory. The actual memory that can be accessed through the system’s memory
bus.
Pipelining. A technique that breaks operations, such as instruction processing or bus
transactions, into smaller distinct stages or tenures (respectively) so that a
subsequent operation can begin before the previous one has completed.
Precise exceptions. A category of exception for which the pipeline can be stopped so
instructions that preceded the faulting instruction can complete, and subsequent
instructions can be flushed and redispatched after exception handling has
completed. See Imprecise exceptions.
Primary opcode. The most-significant 6 bits (bits 0–5) of the instruction encoding that
identifies the type of instruction. See Secondary opcode.
Protection boundary. A boundary between protection domains.
Protection domain. A protection domain is a segment, a virtual page, a BAT area, or a
range of unmapped effective addresses. It is defined only when the appropriate
relocate bit in the MSR (IR or DR) is 1.
Q
R
Quad word. A group of 16 contiguous locations starting at an address divisible by 16.
rA. The rA instruction field is used to specify a GPR to be used as a source or destination.
rB. The rB instruction field is used to specify a GPR to be used as a source.
rD. The rD instruction field is used to specify a GPR to be used as a destination.
rS. The rS instruction field is used to specify a GPR to be used as a source.
Real address mode. An MMU mode when no address translation is performed and the
effective address specified is the same as the physical address. The processor’s
MMU is operating in real address mode if its ability to perform address translation
has been disabled through the MSR registers IR and/or DR bits.
Record bit. Bit 31 (or the Rc bit) in the instruction encoding. When it is set, updates the
condition register (CR) to reflect the result of the operation.
Register indirect addressing. A form of addressing that specifies one GPR that contains
the address for the load or store.
Register indirect with immediate index addressing. A form of addressing that specifies
an immediate value to be added to the contents of a specified GPR to form the
target address for the load or store.
Register indirect with index addressing. A form of addressing that specifies that the
contents of two GPRs be added together to yield the target address for the load or
store.
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Glossary-7
Reservation. The processor establishes a reservation on a cache block of memory space
when it executes an lwarx instruction to read a memory semaphore into a GPR.
Reserved field. In a register, a reserved field is one that is not assigned a function. A
reserved field may be a single bit. The handling of reserved bits is
implementation-dependent. Software is permitted to write any value to such a bit.
A subsequent reading of the bit returns 0 if the value last written to the bit was 0
and returns an undefined value (0 or 1) otherwise.
RISC (reduced instruction set computing). An architecture characterized by
fixed-length instructions with nonoverlapping functionality and by a separate set
of load and store instructions that perform memory accesses.
S
Scalability. The capability of an architecture to generate implementations specific for a
wide range of purposes, and in particular implementations of significantly greater
performance and/or functionality than at present, while maintaining compatibility
with current implementations.
Scan chain. The peripheral buffers of a device, linked in JTAG test mode, that are
addressed in a shift-register fashion.
Set (v). To write a nonzero value to a bit or bit field; the opposite of clear. The term ‘set’
may also be used to generally describe the updating of a bit or bit field.
Set (n). A subdivision of a cache. Cacheable data can be stored in a given location in any
one of the sets, typically corresponding to its lower-order address bits. Because
several memory locations can map to the same location, cached data is typically
placed in the set whose cache block corresponding to that address was used least
recently. See Set-associative.
Set-associative. Aspect of cache organization in which the cache space is divided into
sections, called sets. The cache controller associates a particular main memory
address with the contents of a particular set, or region, within the cache.
Significand. The component of a binary floating-point number that consists of an explicit
or implicit leading bit to the left of its implied binary point and a fraction field to
the right.
Slave. A device that responds to the master’s address. A slave receives data on a write cycle
and gives data to the master on a read cycle.
Static branch prediction. Mechanism by which software (for example, compilers) can
give a hint to the machine hardware about the direction a branch is likely to take.
Sticky bit. A bit that when set must be cleared explicitly.
Superscalar machine. A machine that can issue multiple instructions concurrently from a
conventional linear instruction stream.
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Glossary-8
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Supervisor mode. The privileged operation state of a processor. In supervisor mode,
software, typically the operating system, can access all control registers and can
access the supervisor memory space, among other privileged operations.
Synchronization. A process to ensure that operations occur strictly in order. See Context
synchronization and Execution synchronization.
Synchronous exception. An exception that is generated by the execution of a particular
instruction or instruction sequence. There are two types of synchronous
exceptions, precise and imprecise.
System memory. The physical memory available to a processor.
T
U
Time-division multiplex (TDM). A single serial channel used by several channels taking
turns.
TLB (translation lookaside buffer) A cache that holds recently-used page table entries.
Throughput. The measure of the number of instructions that are processed per clock cycle.
UISA (user instruction set architecture). The level of the architecture to which user-level
software should conform. The UISA defines the base user-level instruction set,
user-level registers, data types, floating-point memory conventions and exception
model as seen by user programs, and the memory and programming models.
User mode. The unprivileged operating state of a processor used typically by application
software. In user mode, software can only access certain control registers and can
access only user memory space. No privileged operations can be performed. Also
referred to as problem state.
V
VEA (virtual environment architecture). The level of the architecture that describes the
memory model for an environment in which multiple devices can access memory,
defines aspects of the cache model, defines cache control instructions, and defines
the time-base facility from a user-level perspective. Implementations that conform
to the PowerPC VEA also adhere to the UISA, but may not necessarily adhere to
the OEA.
Virtual address. An intermediate address used in the translation of an effective address to
a physical address.
Virtual memory. The address space created using the memory management facilities of
the processor. Program access to virtual memory is possible only when it
coincides with physical memory.
W
Watchpoint. An event that is reported, but does not change the timing of the machine.
Word. A 32-bit data element. Note that on other processors a word may be a different size.
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Glossary-9
Write-back. A cache memory update policy in which processor write cycles are directly
written only to the cache. External memory is updated only indirectly, for
example, when a modified cache block is cast out to make room for newer data.
Write-through. A cache memory update policy in which all processor write cycles are
written to both the cache and memory.
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Index
Numerics
603e
60x bus
60x-compatible mode
TBST signal, 8-12
TLBISYNC input, 8-32
address
bus protocol
data
asserting TEA, 8-29
effect of ARTRY assertion, 8-27
A
data transfers
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Index-1
A–A
Index
interworking functions
mapping
AppleTalk mode
ATM controller
ATM pace control (APC) unit
SWITCH receive/transmit buffer descriptor (RxBD),
ATM TRANSMIT command, 30-93
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Index
B–B
BISYNC mode
receive connection table (RCT)
Block diagrams
transmit connection table (TCT)
transmit connection table extension (TCTE)
2
system interface unit (SIU)
user-defined cells (UDC)
Buffer descriptors
ATM controller
B
Baud-rate generator (BRG)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
Index-3
C–C
Index
Clocks
fast communications controllers (FCCs)
Fast Ethernet mode
HDLC mode
overview
GCI mode
I C controller
2
IDMA emulation
multi-channel controllers (MCCs)
serial peripheral interface (SPI)
Commands
ATM TRANSMIT command, 30-93
fast communications controllers (FCCs)
Ethernet mode
transparent mode
HDLC mode
UART mode
2
Buffers
Bus interface
communication processor module
Communications processor (CP)
C
Chip-select
Communications processor module (CPM)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Index-4
Freescale Semiconductor
Index
C–C
ATM controller
ATM pace control (APC) unit
transmit connection table (TCT)
transmit connection table extension (TCTE)
user-defined cells (UDC)
ATM TRANSMIT command, 30-93
command set
communications processor (CP)
receive connection table (RCT)
CPM multiplexing logic (CMX)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
Index-5
C–C
Index
dual-port RAM
overview
fast communications controllers (FCCs)
Fast Ethernet mode
transparent mode
2
I C controller
HDLC mode
IDMA emulation
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Index-6
Freescale Semiconductor
Index
C–C
parallel I/O ports
RISC timer tables
SET TIMER command, 14-25
interrupt controller
multi-channel controllers (MCCs)
CHAMR
SDMA channels
serial peripheral interface (SPI)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
Index-7
D–D
Index
programming example
system interface unit (SIU)
time counter (TMCNT)
timers
Conventions
CPM multiplexing logic (CMX)
see also Serial interface (SI)
D
DSR (data synchronization register)
Dual-port RAM
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Index-8
Freescale Semiconductor
Index
E–F
HDLC mode
E
Ethernet mode
fast communications controller (FCC)
Exceptions
overview
F
Fast communications controllers (FCCs)
Fast Ethernet mode
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
Index-9
G–H
Index
transparent mode
synchronization
serial management controllers (SMCs)
FCCE register
Floating-point unit
FPSMR register
FCCM register
Features list
G
GCI
General-purpose chip-select machine (GPCM)
implementation differences with UPMs and SDRAM
Features lists
fast communications controllers (FCCs)
GSMR (general SCC mode register)
2
memory controller
serial communications controllers (SCCs)
H
HDLC mode
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Index-10
Freescale Semiconductor
Index
I–I
delayed RTS mode, 22-20
fast communications controllers (FCCs)
2
2
2
2
I2MOD (I C mode) register, 39-6
IDMA emulation
HID0 register
I
2
I C controller
2
2
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
Index-11
I–I
Index
IEEE 1149.1 test access port
FCC programming
FCC programming
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Index-12
Freescale Semiconductor
Index
J–M
L
L_TESCR1 (local bus transfer error status and control
L_TESCR2 (local bus transfer error status and control
LDTEA (SDMA local bus transfer error address register),
LDTEM (SDMA local bus transfer error MSNUM register),
LSRT (local bus-assigned SDRAM refresh timer) register,
M
performance parameter measurement and reporting,
Memory controller
controlling the timing of GPL1, GPL2, and CSx, 11-69
Interrupts
RISC timer tables
general-purpose chip-select machine (GPCM)
Inverse Multiplexing for ATM (IMA)
J
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
Index-13
M–M
Index
TEA generation, 11-8
UPMs (user-programmable machines)
implementation differences with SDRAM machine and
SDRAM machine (synchronous DRAM machine)
Memory management unit
memory map
parameters
Memory maps
serial communications controllers (SCCs)
serial management controllers (SMCs)
Modes
60x bus mode
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Index-14
Freescale Semiconductor
Index
N–P
ATM controller
N
NMSI (non-multiplexed serial interface)
synchronization in NMSI mode, transparent operation,
IDMA emulation
O
Operations
serial interface (SI)
serial peripheral interace (SPI)
transparent mode
UART mode
Multi-channel controllers (MCCs)
CHAMR
P
Parallel I/O ports
Parameter RAM
fast communications controllers (FCCs)
2
serial communications controllers (SCCs)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
Index-15
P–P
Index
serial management controllers (SMCs)
PCI bus internal memory-mapped registers base
PCI configuration register access in Big-Endian mode,
PCI outbound comparison mask registers (POCMRx),
current descriptor address registers (DMACDARx),
next descriptor address registers (DMANDARx),
PCI outbound translation address registers (POTARx),
general purpose local access base address registers
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Index-16
Freescale Semiconductor
Index
P–P
inbound message interrupt status register (IMISR),
outbound message interrupt mask register
outbound message interrupt status register
inbound FIFOs
bus transactions
PDTEM (SDMA 60x bus transfer error MSNUM register),
Power consumption
Programming examples
inbound message interrupt mask register (IMIMR),
serial communications controllers (SCCs)
GSMR (general SCC mode register)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
Index-17
R–R
Index
PSMR (protocol-specific mode register)
parallel I/O ports
TODR (transmit-on-demand register)
transparent mode
CPM multiplexing
DSR
PSMR (protocol-specific mode register)
fast communications controller (FCC)
PSRT (60x bus-assigned SDRAM refresh timer) register,
fast communications controllers (FCCs)
Fast Ethernet mode
HDLC mode
R
Registers
overview
AppleTalk mode
ATM controller
BISYNC mode
GSMR
HDLC mode
2
I C controller
communications processor (CP)
communications processor module (CPM)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Index-18
Freescale Semiconductor
Index
R–R
IDMA emulation
PCI bridge
IEEE 1149.1 test access port
IMA
group tables
DMA registers
link tables
memory controller
DMA current descriptor address registers
DMA destination address registers (DMADARx),
DMA next descriptor address registers
GPCM mode
SDRAM mode
UPM mode
general purpose local access base address registers
multi-channel controllers (MCCs)
I20 unit
I2O registers
inbound message interrupt mask register (IMIMR),
inbound FIFOs
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
Index-19
R–R
Index
I2O unit
I2O registers
RISC timer tables
SCCE
SCCM
SCCS
SDMA channels
inbound message interrupt status register (IMISR),
outbound message interrupt mask register
outbound message interrupt status register
inbound FIFOs
outbound FIFOs
PCI bus internal memory-mapped registers bass address
serial interface (SI)
serial management controllers
GCI mode
PCI-bridge
I2O unit
outbound FIFOs
PowerPC
transparent mode
supervisor-level
user-level
UART mode
PSMR
serial management controllers (SMCs)
GCI mode
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Index-20
Freescale Semiconductor
Index
R–R
serial management controllers(SMCs)
GCI mode
serial peripheral interface (SPI)
TODR
transparent mode
system interface unit (SIU)
UART mode
registers
Reset
RFCR (Rx buffer function code register)
RISC timer tables
SET TIMER command, 14-25
timers
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
Index-21
S–S
Index
BISYNC mode
Ethernet mode
S
SCCE (SCC event) register
SCCE register
SCCM (SCC mask) register
SCCM register
SCCS (SCC status) register
SDMA channels
HDLC mode
delayed RTS mode, 22-20
Serial communications controllers (SCCs)
AppleTalk mode
overview
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Index-22
Freescale Semiconductor
Index
S–S
transparent mode
see also CPM multiplexing logic (CMX)
Serial management controllers (SMCs)
GCI mode
C/I channel
monitor channel
UART mode
parameter RAM
transparent mode
Serial interface (SI)
IDL bus implementation
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
Index-23
S–S
Index
UART mode
IDMA emulation
memory controller
Serial mode
Serial peripheral interface (SPI)
programming example
signals, external
description
SMCE (SMC event) register
SMCM (SMC mask) register
Signals
60x bus
System interface unit (SIU)
TBST, 8-12
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Index-24
Freescale Semiconductor
Index
T–T
time counter (TMCNT)
T
TC layer
ATM cell functions
UTOPIA interface
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
Index-25
U–U
Index
TFCR (Tx buffer function code register)
Timers
Time-slot assigner
U
Time-slot assigner (TSA)
Timing
TODR (transmit-on-demand register)
UART mode
serial management controllers
Transparent mode
fast communications controllers (FCCs)
synchronization
UPMs (user-programmable machines)
serial management controllers (SMCs)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Index-26
Freescale Semiconductor
Index
U–U
implementation differences with SDRAM machine and
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
Index-27
U–U
Index
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Index-28
Freescale Semiconductor
Part I—Overview
I
1
2
3
Part II—Configuration and Reset
II
4
5
Part III—The Hardware Interface
III
6
7
8
9
10
11
12
13
IV
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
I
Part I—Overview
1
2
3
II
Part II—Configuration and Reset
4
5
III
Part III—The Hardware Interface
6
7
8
9
10
11
12
13
IV
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
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