Endura RADISYS KP915GV User Manual
Endura KP915GV  
Product Manual  
www.radisys.com  
007-01542-0001 December 2005  
KP915GV Product Manual  
Preface  
Revision History  
Revision history  
Description  
No.  
1.0  
2.0  
Date  
September 2005  
December 2005  
•
•
First Release  
Updates to clarify jumper default positioning, non-support  
for S/PDIF In and Out on board, BIOS update to P28 version,  
and editorial changes to some tables. Added details to OEM  
Features section. No functional changes.  
Notational Conventions  
This manual uses the following conventions:  
Screen text and syntax strings appear in this font.  
All numbers are decimal unless otherwise stated.  
•
•
Notes indicate important information  
about the product.  
Cautions indicate potentially hazardous  
situations which, if not avoided, may result  
in minor or moderate injury or damage to  
data or hardware. It may also alert you  
about unsafe practices.  
Tips indicate alternate techniques or  
procedures that you can use to save  
time or better understand the product.  
The globe indicates a World Wide  
Web address.  
Warnings indicate potentially hazardous  
situations which, if not avoided, can result  
in death or serious injury.  
The book indicates a book or file.  
Danger indicates imminently hazardous  
situations which, if not avoided, will result  
in death or serious injury.  
ESD cautions indicate situations that  
may cause damage to hardware via  
electro-static discharge (ESD).  
Installation Notes  
When installing this motherboard into a suitable chassis, refer to the following notes:  
•
Read and save all instructions.  
•
Always disconnect Cord/Plug before installation or upgrade. Parts of the motherboard can  
remain powered even when the power supply is switched off unless the cord is disconnected.  
Pay attention to the safety warnings included in this document.  
When installing expansion cards, pay attention to the maximum loads detailed in this  
document. Use only UL approved peripheral cards.  
•
•
•
•
Route wiring away from sharp edges, heat sources and cooling fans.  
Pay attention to the thermal issues described in this document. The motherboard requires  
suitable airflow to maintain an ambient temperature within its operating range.  
3
KP915GV Product Manual  
Safety and Approval Notices  
Safety and approval notices  
Item  
Description  
Battery  
This product contains a lithium cell.  
•
•
When removing or replacing the lithium cell, do not use a  
conductive instrument as a short-circuit may cause the cell  
to explode. Always replace the cell with one of the same  
type. This product uses a CR2032 cell. Dispose of a spent  
cell promptly – do not recharge, disassemble or incinerate.  
Keep cells away from children.  
CAUTION! Danger of explosion if battery is incorrectly  
replaced. Replace only with the same or equivalent type  
recommended by the manufacturer. Dispose of batteries  
according to the manufacturer's instructions.  
LAN (Local Area  
Network) Connector  
This product may include an RJ45 LAN connector (see  
product options). Do not connect to anything other than an  
Ethernet LAN.  
Thermal Interface  
Material  
This product may contain thermal interface material between  
devices and heatsinks. This can cause irritation and can stain  
clothing. Avoid prolonged or repeated contact with the skin  
and wash thoroughly with soap and water after handling. Avoid  
contact with eyes and inhalation of fumes. Do not ingest.  
Anti-static  
Precautions  
This product contains static-sensitive components and should  
be handled with care. It is recommended that the product be  
handled in a Special Handling Area (SHA) as defined in  
EN100015-1:1992. Such an area has working surfaces, floor  
coverings and chairs connected to a common earth reference  
point. An earthed wrist strap should be worn whilst handling.  
Other examples of static-sensitive devices are the memory  
modules and the processor. Failure to employ adequate anti-  
static measures can cause irreparable damage to components  
on the motherboard.  
Electromagnetic  
Compatibility  
This product is designed to meet the following EMC standards  
when installed in a suitable chassis.  
•
FCC Class B (Title 47 of Code of Federal Regulations,  
parts 2 & 15, subpart B)  
•
•
EN55022 Class B  
EN55024  
Safety  
This product complies with the American Safety Standard  
UL60950 when installed in a suitable chassis.  
Legal Directives  
This product complies with the relevant clauses of the  
following European Directives.  
Low Voltage Directive  
EMC Directive  
73/23/EEC  
89/336/EEC  
4
KP915GV Product Manual  
Contents  
1
1.1  
1.2  
1.3  
1.4  
OVERVIEW ................................................................................................................10  
Accessories ………………………………………………………………………………………….. 11  
Motherboard Layout................................................................................................................12  
Block Diagram.........................................................................................................................14  
Configuration ………………………………………………………………………………………….15  
1.4.1 Operation Mode Selection Jumper (JP3) ................................................................................15  
1.4.2 BIOS Boot Block Write Protection Jumper (JP2).....................................................................16  
1.4.3 Clear CMOS Jumper (JP1) .....................................................................................................16  
1.4.4 Front Panel Connections.........................................................................................................16  
1.4.5 Alternate Power LED...............................................................................................................17  
1.5  
Installation of CPU ..................................................................................................................17  
2
2.1  
2.2  
2.3  
2.4  
2.5  
2.6  
2.7  
2.8  
2.9  
MOTHERBOARD DESCRIPTION.............................................................................24  
Processor Support ..................................................................................................................24  
System Clocks ........................................................................................................................24  
On board Clocking Block Diagram ..........................................................................................25  
Mechanical ……………………………………………………………………………………………25  
Expansion Slot Types .............................................................................................................25  
915GV Chipset Feature ..........................................................................................................26  
Video .………………………………………………………………………………………………….27  
Disks …………………………………………………………………………………………………..28  
Audio …………………………………………………………………………………………………..28  
2.10 Network ……………………………………………………………………………………………….29  
2.11 I/O ……………………………………………………………………………………………………...30  
2.12 Power Management................................................................................................................30  
2.13 System management ..............................................................................................................30  
2.14 Security ………………………………………………………………………………………………..30  
2.15 Programmable Controller (PLD)..............................................................................................31  
2.16 CMOS RAM and RTC.............................................................................................................31  
2.17 Configuration ………………………………………………………………………………………….31  
2.18 BIOS …………………………………………………………………………………………………..31  
2.19 Operating Systems Support....................................................................................................32  
2.20 Power Supplies .......................................................................................................................32  
2.21 Reliability and Environmental..................................................................................................33  
2.22 Regulatory Compliance...........................................................................................................34  
3
3.1  
3.2  
SPECIFICATIONS .....................................................................................................35  
Product Basis …………………………………………………………………………………………35  
Non-Core Integrated Sub-systems..........................................................................................35  
3.2.1 I/O Controller Hub 6 (ICH6).....................................................................................................35  
3.2.2 Flash BIOS..............................................................................................................................38  
3.3  
Major Sub-systems .................................................................................................................39  
3.3.1 Audio Interface........................................................................................................................39  
3.3.2 Hardware Management Interface............................................................................................41  
3.3.3 Ethernet Interface....................................................................................................................42  
3.3.4 Super I/O Interface..................................................................................................................43  
3.4  
Motherboard Power Consumption...........................................................................................48  
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KP915GV Product Manual  
4
4.1  
4.2  
MOTHERBOARD BIOS.............................................................................................51  
BIOS Features ........................................................................................................................51  
Post and Boot ………………………………………………………………………………………..51  
4.2.1 Hotkeys...................................................................................................................................52  
4.3 Setup Utility ………………………………………………………………………………………….. 52  
4.3.1 Enter Setup.............................................................................................................................52  
4.3.2 Configuration Reset ................................................................................................................52  
4.3.3 Keyboard Command ...............................................................................................................52  
4.3.4 Setup Configuration ................................................................................................................53  
4.4  
4.4.1 ACPI Wake-up Support...........................................................................................................93  
4.5 Hardware Monitor and Auto Fan Control.................................................................................93  
Power Management................................................................................................................93  
4.5.1 Hardware Monitor....................................................................................................................93  
4.5.2 Automatic Fan Control ............................................................................................................93  
4.6  
4.7  
Power LED ……………………………………………………………………………………………93  
CPLD …………………………………………………………………………………………………. 94  
4.7.1 POST Code Display................................................................................................................94  
4.7.2 BIOS Protection ......................................................................................................................94  
4.7.3 LAN Controller.........................................................................................................................94  
4.8  
4.9  
TPM ……………………………………………………………………………………………………94  
Normal, Configure and Recovery Mode..................................................................................94  
4.9.1 Normal Mode ..........................................................................................................................95  
4.9.2 Configure Mode.......................................................................................................................95  
4.9.3 Recovery Mode.......................................................................................................................95  
4.10 Update and Recovery Diskette ...............................................................................................95  
4.10.1 Update Diskette.......................................................................................................................95  
4.10.2 Recovery Diskette...................................................................................................................95  
4.11 Tamper Detection....................................................................................................................95  
4.12 OEM Features.........................................................................................................................95  
4.12.1 POST Logo Change................................................................................................................95  
4.12.2 CMOS Default Change ...........................................................................................................96  
4.13 PXE ……………………………………………………………………………………………………96  
4.14 BIOS Flash Usage Map ..........................................................................................................97  
4.15 Processor Microcode Support.................................................................................................97  
4.16 SMBIOS ……………………………………………………………………………………………… 97  
4.17 Post Code Technical Description ..........................................................................................102  
4.18 POST Beep ………………………………………………………………………………………….104  
4.19 SMBus Device Configuration ................................................................................................104  
5
CUSTOMER SUPPORT...........................................................................................105  
TECHNICAL REFERENCE......................................................................................106  
A
A.1 I/O Map ………………………………………………………………………………………………106  
A.2 PCI Interrupt Allocation .........................................................................................................107  
A.3 PCI Device Assignments.......................................................................................................108  
A.4 SMBus Resource Allocation..................................................................................................108  
A.5 ISA Interrupt Allocation .........................................................................................................109  
A.6 ISA DMA Channel Allocation ................................................................................................109  
A.7 BIOS Organization ................................................................................................................110  
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KP915GV Product Manual  
B
CONTROL REGISTERS..........................................................................................111  
B.1 Index Register.......................................................................................................................111  
B.2 Watchdog Control .................................................................................................................111  
B.3 Watchdog Kick ......................................................................................................................112  
B.4 Watchdog Status...................................................................................................................112  
B.5 Watchdog Timeout Period.....................................................................................................113  
B.6 General Purpose I/O Port 1...................................................................................................113  
B.7 General Purpose I/O Port 2 and Control ...............................................................................113  
B.8 PWM Control ………………………………………………………………………………………..114  
B.9 Processor Identification.........................................................................................................114  
B.10 Controller Part Number .........................................................................................................115  
C
CONNECTOR DESCRIPTIONS ..............................................................................116  
C.1 Connector Part Numbers ......................................................................................................116  
C.2 PCI-E Expansion Slot (ADD2 card mode).............................................................................117  
C.3 PCI Expansion Slot ...............................................................................................................118  
C.4 PCI Express x1 Slot ..............................................................................................................119  
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KP915GV Product Manual  
Figures  
Figure 1.  
Figure 2.  
Figure 3.  
Figure 4.  
Figure 5.  
Figure 6.  
Figure 7.  
Figure 8.  
Figure 9.  
Figure 10.  
Figure 11.  
KP915GV Board Layout.............................................................................................12  
KP915GV Block diagram ...........................................................................................14  
Jumpers .....................................................................................................................15  
Clocking Block Diagram.............................................................................................25  
KP915GV Board Slot Layout......................................................................................28  
Audio Jack Socket and ATAPI Connectors................................................................29  
SST 49LF004B Functional Block Diagram.................................................................38  
SigmaTel STAC9200 High Definition Block Diagram.................................................40  
NS LM96000CIM Block Diagram ...............................................................................41  
PC8374K Block Diagram ...........................................................................................43  
BIOS ROM Addresses .............................................................................................110  
Tables  
Revision history .................................................................................................................................3  
Safety and approval notices ..............................................................................................................4  
Product Specification Overview.......................................................................................................10  
Table 1. KP915GV Motherboard ...................................................................................................26  
Table 3. ACPI Power States..........................................................................................................30  
Table 4. Power Supply Connector.................................................................................................32  
Table 5. Environmental Specifications...........................................................................................33  
Table 6. Regulatory Testing* .........................................................................................................34  
Table 7. References ....................................................................................................................105  
Table 8. I/O Map..........................................................................................................................106  
Table 9. PCI Interrupt Allocation..................................................................................................107  
Table 10. PCI Device Assignments .............................................................................................108  
Table 11. SMBus Resource Allocation ........................................................................................108  
Table 12. ISA Interrupt Allocation................................................................................................109  
Table 13. ISA DMA Channel Allocation.......................................................................................109  
Table 14. Connector part numbers..............................................................................................116  
Table 15. ADD2 Expansion Slot ..................................................................................................117  
Table 16. PCI Expansion Slot......................................................................................................118  
Table 17. PCI Express x1 Slot (PCI-E x1) ...................................................................................119  
Table 18. P/S2 Mouse and P/S2 Keyboard.................................................................................119  
Table 20. Serial Port....................................................................................................................120  
Table 21. VGA Port .....................................................................................................................120  
Table 22. 2 x Dual Stack USB Ports............................................................................................120  
Table 24. 3 x Audio Jack .............................................................................................................121  
Table 25. 1394 Header................................................................................................................121  
Table 26. Front Panel Header .....................................................................................................121  
Table 27. General Purpose I/O Headers ......................................................................................122  
Table 28. Power Supply Connector.............................................................................................122  
Table 29. Floppy Disk Connector ................................................................................................122  
Table 30. ATA/100 Hard Drive Disk Connector ...........................................................................123  
Table 32. 3X Internal Audio Headers...........................................................................................123  
Table 33. TPM Header ...............................................................................................................124  
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KP915GV Product Manual  
Table 34. Complex Programmable Logic Device (CPLD) JTAG Header....................................124  
Table 35. Serial Port 2 Header ...................................................................................................124  
Table 36. 4 X Internal USB Headers ...........................................................................................124  
Table 37. Remote Thermal Sensor..............................................................................................125  
Table 38. 3 X Fan Connector.......................................................................................................125  
Table 39. SMBus Connector........................................................................................................125  
Table 40. PS/2 Keyboard Header................................................................................................125  
Table 41. PS/2 Mouse Header ....................................................................................................125  
9
KP915GV Product Manual  
1
Overview  
Target applications are transaction terminals, medical, test & measurement, gaming, industrial  
automation applications and other enterprise systems. This motherboard is part of the RadiSys  
Endura product line, which is specifically targeted at embedded applications with a lifetime of 5  
years. Products are fully revision controlled and any change to form, fit or function will be notified to  
customers in advance via a Product Change Notification procedure.  
Product Specification Overview  
Item  
Description  
Form Factor  
Processor  
ATX  
12” x 9.6”, 6 expansion slots  
Support for an Intel® Pentium® 4 or Celeron D processor in a LGA775 socket  
with an 800MHz or 533MHz FSB  
Embedded processor requirements:  
Intel® Pentium® 4 Processor 551 (3.4GHz 800MHz FSB 1MB L2)  
Intel® Celeron™ D Processor 341 (2.93GHz 533MHz FSB 256KB L2)  
Intel 915GV GMCH and Intel ICH6 I/O hub  
Chipset  
Memory  
Video  
Four DIMM sockets for DDR2 400/533 modules  
Intel® GMA900 video controller integrated within chipset  
Audio  
Two channel stereo audio using the Sigmatel STAC9200 audio controller with  
Intel HD Audio interface operation option  
Two plug and play jacks on I/O panel (default MIC, line-out)  
Three ATAPI connectors – line input, line output, and microphone input  
On-board PC speaker (beep)  
Expansion  
915GV ATX  
Three PCI, two x1 PCI-E, one ADD2 slots  
Capabilities  
(No PCI riser extension connector)  
Power  
ACPI 2.0 supporting states S0, S3, S4, S5, and C0, C1, C2, C3  
Management  
System  
Management  
Voltage, temperature and fan monitoring (3 fans)  
Lithium cell voltage monitoring  
Automatic fan speed control (3 fans)  
Programmable watchdog timer  
SMBus header  
Security  
BIOS  
Header for TPM 1.1 compliant module  
Phoenix Award BIOS for the Intel 915G/GV chipset  
Includes video BIOS and network boot  
4Mbit Firmware Hub  
Build option for socketed BIOS with write-protect jumper (enabled by the PLD  
logic)  
User defined BIOS default settings  
I/O  
Eight USB 2.0 ports - four on I/O panel and four on locking headers  
General purpose I/O lines (13) with LCD character display support  
Firewire  
Available with IEEE 1394b function with single port via an on-board header  
connector (based on TI TSB82AA2 controller and TSB81BA3 transceiver)  
10  
 
KP915GV Product Manual  
Product Specification Overview  
Item  
Description  
Network  
Intel 82573V (or ‘L) PCI-E Gbit Ethernet controller, co-lay with Intel 82562GZ  
10/100 PHY (using the integrated MAC)  
Available with second Intel 82573V (or ‘L) Gbit Ethernet controller  
Four SATA ports with locking headers  
Disks  
Single Ultra ATA/100 interface supporting hard disks and ATAPI drives  
One FDD interface  
Super I/O &  
H/W Monitor  
Nat Semiconductor PC8374K Super I/O and Nat Semiconductor LM9600  
hardware monitoring device  
Automatic fan speed control based on thermal monitoring (note that the BIOS  
Setup is used for configuration and status information)  
Header  
Connectors  
GPIO  
2 x 10 pin with housing  
1 x 4 pin with housing  
2 x 5 pin with housing  
1 x 4 pin with housing  
1 x 2 pin with housing  
1 x FDD connector  
SMbus  
COM2  
Kbd/Mouse  
Remote thermal sensor  
FDD  
1394b  
2 x 5 pin connector  
I/O Panel  
PS/2 keyboard and mouse  
Analog VGA  
Bi-directional/EPP/ECP parallel port  
COM1 RS232  
One or two dual USB + RJ45 stacks  
Audio jack stack (2 jacks)  
RadiSys PLD  
Lattice LC4128ZC-75TN100C PLD for watchdog, GPIO, BIOS write-protect  
support  
1.1  
Accessories  
There are two I/O shields, one for the single Ethernet configuration and one for the dual Ethernet  
configuration, and an available fan heat sink for the processor. These are separately orderable  
product codes.  
ATX-L KP IOSHLD  
ATX I/O Shield for KP915GV  
11  
KP915GV Product Manual  
1.2  
Motherboard Layout  
Figure 1 shows the layout of the KP915GV motherboard with the major components identified.  
Figure 1.  
KP915GV Board Layout  
59  
58  
57  
56 55 54 53 52 51 50 49 48 47  
46  
45  
1
2
3
44  
43  
4
42  
41  
5
6
40  
39  
7
8
9
38  
37  
36  
35  
10  
11  
34  
33  
32  
12  
(Optional)  
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30  
31  
12  
KP915GV Product Manual  
Component Identification  
Description  
Description  
Description  
Ethernet port 1  
(option)  
1
Super IO  
21  
41 USB port 2 header  
2
3
4
5
Memory sockets  
22  
23  
24  
25  
I/O panel USB port 7  
I/O panel USB port 8  
Microphone input jack  
Audio line output jack  
42 USB port 3 header  
43 USB port 4 header  
44 SMBus header  
Serial port 2 header  
Remote thermal sensor  
CPU FAN power  
connector  
45 BIOS ROM write-  
protect jumper  
6
7
Chipset GMCH  
26  
27  
Ethernet controller 1  
(option)  
46 Clear CMOS Jumper  
775-pin socket for  
processor  
ADD2 slot  
47 GPIO header  
8
9
Clock generator  
28  
29  
Ethernet controller 2  
PCI Express x1 slot  
48 BIOS ROM (FWH)  
System fan power  
connector  
49 CPLD control logic  
10 PS/2 mouse header  
30  
31  
PCI slot 2.3  
50 JTAG header  
11 PS/2 keyboard header  
HD Audio CODEC  
51 I/O controller hub  
(ICH6)  
12 12V power connector  
32  
33  
Stereo audio (CD) line  
input header  
52 Operation Mode  
Jumper  
13 PS/2 mouse (green)  
Stereo audio  
(microphone) input  
header  
53 Front panel header  
14 PS/2 keyboard (purple)  
34  
Stereo audio line  
output header  
54 SATA connectors  
15 Serial port  
35  
36  
Buzzer  
55 Chassis fan power  
connector  
16 Parallel port  
1394 controller  
RTC battery  
56 Primary power supply  
connector  
17 VGA monitor  
37  
38  
57 IDE connector  
18 Ethernet port 2  
1394 PHY  
58 TPM header  
(TSB81BA3I)  
19 I/O panel USB port 5  
39  
40  
1394 header  
59 FDD connector  
20 I/O panel USB port 6  
USB port 1 header  
13  
KP915GV Product Manual  
1.3  
Block Diagram  
Figure 2 shows the block diagram of the KP915GV motherboard.  
Figure 2.  
KP915GV Block diagram  
Prescott, Tejas  
Pentium 4 EE  
LGA775 processor  
Socket T  
VRD 10.1  
4 Phase PWM  
CK-410 Clock  
800/533 FSB  
CRT  
Channel A DDR-2  
DIMM1  
400/533MHz  
400/533MHz  
VGA  
Channel A DDR-2  
DIMM2  
PCIEx16 Port  
GMCH  
Intel SDVO Card  
Channel B DDR-2  
DIMM3  
Grantsdale  
I/O Panel  
Channel B DDR-2  
DIMM4  
USB2.0 Port5  
USB2.0 Port6  
USB2.0 Port7  
USB2.0 Port8  
4 Lanes  
Direct Media Interface (DMI)  
PCI-E Slot 1  
PCIE x1 Interface  
PCIE x1 Interface  
PCI-E Slot 2  
USB2.0  
Header  
USB2.0 Port1  
USB2.0 Port2  
USB2.0 Port3  
Intel 82573E  
LAN-Link  
Intel 82562GZ  
USB2.0  
ATA  
USB2.0 Port4  
PCI Interface  
ATX Form Factor  
PCI Slot 1,2&3  
ATA100  
IDE CONN 1  
1394  
TSB82AA2I  
PCI Interface  
SATA  
Keyboard  
Mouse  
Serial ATA  
Port 1  
LPC  
ICH6  
SUPER I/O  
NS PC8374K  
SATA  
Serial ATA  
Port 2  
SATA  
Serial Port1  
Serial ATA  
Port 3  
Serial Port2  
SATA  
Serial ATA  
Port 4  
High Definition Audio  
Azalia Codec  
STAC9200  
Parallel  
FWH Flash  
BIOS  
4Mb  
Floppy  
14  
KP915GV Product Manual  
1.4  
Configuration  
The majority of the configuration of the motherboard is done through the Setup utility built into the  
BIOS – discussed later in this document. There are, however, a number of jumpers that control the  
operation of the motherboard as described below. Some jumpers are not fitted to certain products.  
Figure 3.  
Jumpers  
1 (No jumper = Recover) JP3  
(No jumper = Protected)  
Normal  
CPLD Write Enable  
JP2  
Configure  
CPLD Write  
Protected  
BIOS Unlock  
BIOS Lock  
1
(No jumper = Unlock)  
1
JP1  
Clear CMOS  
Normal  
(No jumper = Normal)  
1.4.1  
Operation Mode Selection Jumper (JP3)  
This jumper selects one of the following operating modes for the motherboard (pins 1, 3, 5) and  
controls write capability for the CPLD content (pins 2, 4, 6).  
Normal Mode  
(Jumper between pins 1 & 3) This is the factory default position the jumper  
should be in for normal operation of the motherboard.  
Configure Mode (Jumper between pins 3 & 5) With the jumper in this position the motherboard  
automatically runs the BIOS Setup utility regardless of the state of the Setup  
disable flag that can be set in the BIOS defaults. In this mode, the CMOS RAM  
contents are ignored and the defaults are used to configure the motherboard.  
15  
KP915GV Product Manual  
Recover Mode (No jumper) With no jumper installed on pins 1, 3, and 5 recovery mode is entered.  
The motherboard does not boot and waits until a valid recovery diskette is  
detected and then copies new BIOS into the ROM. The motherboard must be  
powered down and then re-powered with the jumper in the normal position before  
normal operation can resume.  
CPLD Write Enabled (Jumper between pins 2 & 4) In this position the contents of the CPLD can  
be reprogrammed.  
CPLD Write Protected (Jumper between pins 4 & 6) This is the factory default position. In this  
position, or with no jumper on pins 2, 4, and 6, the contents of the CPLD are  
protected from reprogramming.  
1.4.2  
BIOS Boot Block Write Protection Jumper (JP2)  
(Jumper between pins 1 & 2) This is the factory default position. A jumper installed in this position.  
or no jumper installed, enables changes to contents of BIOS ROM boot block (unlocked position).  
Some motherboard applications may want to have boot block write-protected BIOS. This can be  
provided via the BIOS boot block write protection jumper. If a jumper is installed between pins 2 &  
3 (locked position), the contents of BIOS ROM boot block cannot be changed in any way.  
1.4.3  
1.4.4  
Clear CMOS Jumper (JP1)  
(Jumper between pins 2 & 3) This is the factory default position. Either this position or no jumper  
installed, is the normal operating configuration. Installing a jumper between pins 1 & 2 clears  
(resets) the CMOS.  
Front Panel Connections  
The primary controls and indicators for the motherboard are connected via the front panel  
connector using either a single ribbon cable to a ‘front panel’ assembly, or using a number of small  
PC-standard connectors. The functions are described below. See appendix B for the connector pin-  
out information.  
Power LED  
Connects either a single-color LED (usually green) or a two-terminal bi-color LED (usually  
green/yellow) to indicate the powered status of the motherboard. In both cases, the ‘green’ anode  
should be attached to pin 2 of the front panel connector. Refer to the Enhanced Power  
Management LED portion in section 3.3.4.4 of this document for further information.  
Power Switch  
If the motherboard is used with a soft-switch power supply, a momentary switch should be  
connected between pins 6 and 8 of the power switch connections on the front panel connector. If  
the switch is closed for greater than approximately 4 seconds, the motherboard powers off  
immediately, regardless of the state of the operating system, losing any system context information.  
This input is redundant when using a hard-switch power supply.  
Reset Switch  
If used, a momentary switch connected between pins 5 and 7 will cause the motherboard to restart  
when closed.  
Hard Disk LED  
To indicate hard disk activity on either of the two ATA channels, a single color LED should be  
connected between pins 1 (anode) and 3.  
Speaker  
Connect an external speaker between pins 10 and 12 or 10 and 16. This is used only for the PC  
‘beep’ functions. The speaker should typically be 8Ω.  
16  
KP915GV Product Manual  
Tamper Switch  
To make use of the tamper detection logic of the motherboard, connect a momentary switch  
between pins 18 and 20. The switch should be open when the chassis is closed.  
1.4.5  
Alternate Power LED  
The power LED function on the front panel connector is duplicated on the Alternate Power LED  
connector for use with LEDs cabled to a 3-pin connector. Do not use both the primary (front panel)  
and alternate connectors simultaneously.  
1.5  
Installation of CPU  
1.5.1  
Installation of CPU  
Below is the CPU socket illustration. Follow these procedures to install a CPU.  
Load lever  
Load plate  
Load cap  
Load Stiffener  
1. Use thumb & forefinger to hold the lifted tab of the cap.  
Lifted tab  
2. Lift the cap up and pick to upload the cap completely from the socket.  
17  
KP915GV Product Manual  
3. Use thumb & forefinger to hold the hook of the load lever and pull the lever sideways to unlock it.  
Correct  
Wrong  
Warning:  
DO NOT use finger to lift the locking lever, as injury could occur to the finger and the SKT could be  
damaged.  
4.  
Lift up the lever. Use thumb to open the load plate. Be careful not to touch the contacts.  
5.  
Hold the CPU and tilt it to some degree since the contacts are designed to be hooked, and  
then match the triangle marker to Pin 1 position as shown below. Carefully insert the CPU  
into the socket until it fits in place.  
18  
KP915GV Product Manual  
Alignment key  
Pin 1 indicator  
19  
KP915GV Product Manual  
6.  
Close the load plate, and slightly push down the tongue side.  
Slightly push down  
the tongue side  
7. Lower the lever and lock it to the load plate, then the CPU is locked in place.  
CAUTION  
Excessive temperatures will severely damage the CPU and system. Therefore, you should install  
CPU cooling fan and make sure that the cooling fan works normally at all times in order to prevent  
overheating and damaging to the CPU. Please refer to your CPU fan user guide to install it  
properly.  
1.5.2  
Installation of Memory  
This motherboard includes four 240-pin slots with 1.8V for DDR2. You must install at least one  
memory bank to ensure normal operation.  
Installation of DDR2 Memory  
1. There is only one gap in the middle of the DIMM slot, and the memory module can be fixed in  
one direction only. Unlock a DIMM slot by pressing the module clips outward.  
2. Align the memory module to the DIMM slot, and insert the module vertically into the DIMM slot.  
20  
KP915GV Product Manual  
DDR2 Memory bank  
128 Pins  
112 Pins  
3. The plastic clips at both sides of the DIMM slot will lock automatically.  
CAUTION  
Be sure to unplug the AC power supply before adding or removing expansion cards or other  
system peripherals, especially the memory devices, otherwise the motherboard or the system  
memory might be seriously damaged.  
21  
KP915GV Product Manual  
1.5.3  
Power Supply  
In order to avoid damaging any devices, make sure that they have been installed properly prior to  
connecting the power supply.  
It is recommended that the board be used with a power supply that supports a minimum  
current load of 0.3A or less on the 5V supply rail and 2A or less on the 3.3V supply rail.  
This board with CPU and memory may draw as little as 400mA of 5V and 2A of 3.3V during  
start-up (increases depend on installed devices). The power supply under consideration must  
be verified as compatible with the projected total system start-up loads for these supply rails.  
If the power supply minimum current level requirements are not at or below the level of  
current loads that are actually drawn, unpredictable start-up operation may result, such as the  
power supply latching off. If this occurs, the AC input to the power supply must be removed  
and re-attached or the power supply switch cycled off and on, in order to turn the system  
back on.  
4-pin ATX 12V Power Connector:  
The ATX power supply connects here and provides power to the CPU.  
GND GND  
3
4
1
2
12V 12V  
4-pin ATX 12V power connector  
22  
KP915GV Product Manual  
KP915GV 20-pin ATX power connector:  
Below is the ATX power supply connector. Make sure that the power supply cable and pins are  
properly aligned with the connector on the motherboard. Firmly plug the power supply cable into  
the connector and make sure it is secure.  
GND  
-5V  
PS-ON  
GND  
5V  
GND GND  
3.3V  
-12V  
5V  
5V +5V  
GND  
3.3V  
3.3V  
12V  
5VSB  
Pw-OK  
GND  
GND  
20-pin ATX power connector  
23  
KP915GV Product Manual  
2
Motherboard Description  
2.1  
Processor Support  
•
•
•
•
Single processor support  
Intel® Pentium® 4 Processor 550/551 (3.4GHz 800MHz FSB 1MB L2)  
Intel® Celeron™ D Processor 340/341 (2.93GHz 533MHz FSB 256Kb L2)  
Follow the Design Guide in the Intel(R) Pentium(R) 4 Processor in the 775-land Package on 90  
nm Process EMTS REV. NO. 1.1 and Grantsdale Chipset (915-GV) Platform Design Guide  
REV NO. 1.2  
•
Supports Pentium® 4 Processor Front Side Bus (FSB) at 533MHz (133MHz bus clock) and  
800MHz (200MHz bus clock)  
•
•
Supports Hyper-Threading Technology and FSB Dynamic Bus Inversion (DBI)  
Supports 32-bit host bus addressing, allowing the CPU to access the entire 4 GB of the  
GMCH’s memory address space  
2.2  
System Clocks  
All clocks must comply with CK410 specifications. System clocks include as below:  
•
•
•
•
•
•
•
•
•
•
•
•
Host system (FSB 533/800MHz)  
DMI (Direct Media Interface)  
Memory system DDR2 SDRAM  
CPU/MCH/ITP CONNECTOR  
MCH/ICH6/LAN/SATA/PCI-E slot  
DOTCLK  
PCI slot/SIO/FWH/ICH6/TPM/CPLD  
USB/ICH6  
HD Audio  
133/200MHz  
100 MHz  
400/533MHz  
200MHz  
100MHz  
96 MHz  
33 MHz  
48 MHz  
24.576 MHz  
14 MHz  
32.768 KHz  
25 MHz  
ICH6/SIO  
RTC (OSC)  
LAN (OSC)  
24  
KP915GV Product Manual  
2.3  
On board Clocking Block Diagram  
14.318MHz  
CPU  
CPU 133/200 MHz Diff Pair  
MCH 133/200 MHz Diff Pair  
DDR 4 Slots 12 Diff Pair CLKs  
PCI Express 100 MHz Diff Pair  
DOT 96 MHz Diff Pair  
PCI Express x16 SDVO  
Channel A DDR2  
DIMM1  
GMCH  
DIMM2  
PCI Express/DMI 100 MHz Diff Pair  
Grantsdale  
Channel B DDR2  
DIMM1  
PCI Express/DMI 100 MHz Diff Pair  
USB/SIO 48 MHz  
DIMM2  
ICH 33 MHz  
REF 14 MHz  
FWH 33 MHz  
PCI 33 MHz  
Azalia  
24.576MHz  
FWH  
ICH6  
PCI Slot  
1,2&3  
Azalia Bit Clock  
PCI Express 100 MHz Diff Pair  
PCI Express 100 MHz Diff Pair  
PCI-E SLOT  
1,2  
LAN  
1394 33 MHz  
32.768KHz  
Super I/O  
1394  
SATA 100 MHz Diff Pair  
SIO 33 MHz  
Figure 4.  
Clocking Block Diagram  
2.4  
2.5  
Mechanical  
•
•
•
•
Compliant with the ATX 2.03 specification  
Lead-free design  
4-layer PCB, components top side only, immersion silver surface finish  
Screen printing includes RadiSys product code, RadiSys part number, RadiSys branding,  
selected component reference designators, and UL and WEEE directive logos.  
Expansion Slot Types  
25  
KP915GV Product Manual  
Table 1. KP915GV Motherboard  
Form  
Factor  
PCI-E x16  
or ADD2  
PCI-E  
x1  
PCI Riser  
Extension  
Chipset  
PCI  
915GV  
ATX  
1
2
3
N/A  
•
•
See Figure 5 for slot configurations  
ADD2 will be a green connector  
2.6  
915GV Chipset Feature  
The 915GV is a Memory Controller Hub (MCH) designed for use with the Prescott processors in  
desktop platforms. The role of a MCH is a system is to manage the flow of information between its  
four interfaces: the CPU interface (FSB), the DDR/DDR2 System Memory interface (DRAM  
controller), the External Graphics interface (PCI Express-G), and the I/O Controller through Direct  
Media Interface (DMI). It’s 1210 Flip Chip Ball Grid Array (FCBGA) package.  
Processor/Host interface (FSB)  
•
•
Supports a single Pentium 4 processor with 1-MB L2 cache in the 90 nm process, in an  
LGA775 package.  
The primary enhancements over the Compatible Mode P6 bus protocol are:  
1- Source synchronous double-pumped (2x) Address  
2- Source synchronous quad-pumped (4x) Data  
•
•
Supports Pentium 4 processor FSB interrupt delivery.  
Supports Pentium 4 processor Front Side Bus (FSB) at the following Frequency Ranges:  
533/800MT/s (133/200MHz)  
•
•
•
Supports Hyper-Threading Technology (HT Technology)  
Supports FSB Dynamic Bus Inversion (DBI)  
Supports 36-bit host bus addressing, allowing the CPU to access the entire 4GB of the MCH’s  
memory address space.  
•
12-deep In-Order Queue to support up to twelve outstanding pipelined address requests on  
the host bus.  
•
•
•
•
1-deep Defer Queue.  
Utilizes GTL+ bus driver with integrated GTL termination resistors.  
Supports a Cache Line Size of 64 bytes.  
At 133/200MHz bus clock the address signals run at 266/400MT/s, the data is quad pumped  
and an entire 64B cache line can be transferred in two bus clocks. At 133/200MHz bus clock  
the data signals run at 533/800MT/s for a maximum bandwidth of 4.3GB/s.  
System Memory Controller  
•
The MCH System Memory Controller directly supports dual channel of memory (each channel  
consisting of 64 data lines)  
1- The memory channels are asymmetric: “Stacked” channels are assigned address serially.  
Channel B addresses are assigned after all Channel A addresses.  
2- The memory channels are interleaved: Addresses are ping-ponged between the channels  
after each cache line (64-B boundary).  
•
Supports DDR2 memory DIMM frequencies of 400 and 533MHz. The speed used in all  
channels is the speed of the slowest DIMM in the system.  
26  
KP915GV Product Manual  
•
Support for non-ECC memory, unbuffered DIMMs only, in 256MB, 512MB, 1GB, and 2GB  
sizes, which may be installed as single DIMMs if desired. If a total of 4GB of DIMMs is  
installed, the maximum available memory will be approximately 3.24GB, with the balance of  
the address space being consumed by other resources in the system.  
•
•
•
I/O Voltage of 1.8V for DDR2.  
Directly support only two channels of non-ECC DDR2 DIMMs.  
Supports maximum memory bandwidth of 4.2GB/s in single-channel or dual channel  
asymmetric mode, or 8.5GB/s in dual-channel interleaved mode assuming DDR2 533MHz.  
•
For dual interleaved mode, DIMMs must be installed in matched pairs, installed in DIMM  
sockets with identical color (e.g. locations DIMM1 and DIMM3, then DIMM2 and DIMM4).  
•
•
Supports 256Mb, 512Mb, and 1Gb technologies for x8 and x16 non-ECC DDR2 devices.  
Supports four banks for all DDR2 devices up to 512Mb densities. Supports eight banks for 1Gb  
DDR2 devices.  
•
•
•
Maximum DRAM address decode space of 4GB. (Assuming 32-bit addressing)  
Supports opportunistic refresh scheme.  
Supports page sizes of 4KB, 8KB, 16KB and 32 KB. Note 32KB is for dual-channel operation  
only.  
•
•
•
•
•
Supports up to 16 simultaneous open pages per channel  
Serial Presence Detect (SPD) scheme for DIMM detection support.  
Dual channel DDR2 for 4 X 240 pin DIMM connectors  
Support for Serial Presence Detect (SPD)  
Support for Suspend to RAM (STR) using CKE, S3 ACPI state  
PCI Express Graphics Interface  
•
One, 16-lane PCI Express port intended for Graphics Attach, fully compliant to the PCI  
Express Base Specification revision 1.0a  
•
•
A base PCI Express frequency of 2.5Gb/s only.  
Raw bit-rate on the data pins of 2.5Gb/s, resulting in the real bandwidth per pair of 250MB/s  
given the 8b/10b encoding used to transmit data across this interface.  
•
•
Maximum theoretical realized bandwidth on the interface of 4GB/s in each direction  
simultaneously, for an aggregate of 8GB/s when x16.  
PCI Express Enhanced Addressing Mechanism. Accessing the device configuration space in  
the flat memory mapped fashion.  
•
•
Automatic discovery, negotiation, and training of link out of reset.  
Supports traditional PCI style traffic (asynchronous snooped, PCI ordering).  
DMI  
•
•
•
•
A chip-to-chip connection interface to Intel ICH6.  
2GB/s point-to-point DMI to ICH6 (1GB/s each direction).  
100MHz reference clock (shared with PCI Express Graphics Attach).  
32-bit downstream addressing.  
2.7  
Video  
•
Integrated Intel® GMA900 video controller  
1. Intel Infrastructure Processor Division (IPD) group Embedded Graphics or Graphics Media  
Accelerator (GMA) (Extreme) drivers and video BIOS  
•
Analog RGB output with DDC2B  
1. Graphics resolution up to 2048 x 1536 pixels with 32-bit color support at 75Hz  
2. 15-pin D-sub connector  
27  
KP915GV Product Manual  
Processor  
x1  
PCI-E  
ADD2  
x1  
PCI-E  
PCI  
PCI  
PCI  
Figure 5.  
KP915GV Board Slot Layout  
2.8  
Disks  
•
•
•
•
•
•
Four 150MB/s SATA ports with locking headers  
One Ultra ATA/100 interface via on-board 40-way boxed header  
40/80-pin cable host-side detection or forced in BIOS  
Support for hard disks and ATAPI drives  
BIOS support for 48-bit LBA (ATA drives >137GB)  
Support for USB drives including boot  
2.9  
Audio  
SigmaTel STAC9200 audio controller with Intel High Definition Audio (HDA) compatible mode  
•
On-board ATAPI connectors  
•
•
•
ATAPI 1: Line input connector (black)  
ATAPI 2: Stereo AUX/MIC input connector (white)  
ATAPI 3: Stereo Line output connector (yellow)  
•
•
Two I/O panel 3.5mm plug and play audio jacks – default connections:  
•
•
Stereo microphone input (with support for microphone bias)  
Stereo line output with headphone drive capability  
(Note: an option exists for a three jack connector – refer to Table 2 and comments below.)  
On-board PC beeper  
28  
KP915GV Product Manual  
External  
Internal  
Optional*  
Line in  
ATAPI 1  
Line out  
MIC in  
ATAPI 3  
ATAPI 2  
Line out  
MIC in  
Figure 6.  
Audio Jack Socket and ATAPI Connectors  
Table 2: Audio Channel Allocation  
I/O panel jack  
Internal header  
I/O panel jack color  
ATAPI header color  
Nominal function  
Pink  
Lime  
Blue*  
Black*  
Line In*  
X
White  
Yellow  
Microphone  
X
Line Out  
Microphone  
Line Out  
Line In capability  
Line Out capability  
Microphone capability  
Headphone Out Capability  
X
X
X
X
X
* If a 3 jack external connector is needed, an option could be made available, for which the  
added blue jack would be Line In, displacing the Line In black internal header (deleted) on  
the standard configuration.  
2.10  
Network  
•
•
•
•
•
•
•
•
•
•
One Ethernet controller configured as either 10/100 or 10/100/Gbit at build-time  
Available with a second Ethernet controller configured as 10/100/Gbit  
10/100Mbps Ethernet solution IEEE 802.3 10Base-T and 100Base-TX compatible  
MAC integrated into ICH with Intel 82562GZ transceiver  
Remote boot, PXE and Wake-On-LAN support  
Gbit Ethernet solutions IEEE 802.3 10Base-T, 100Base-TX, 1000Base-T compatible  
Intel 82573V (or ‘L) PCI Express Ethernet controller connected via I/O hub x1 lane  
Full line-speed operation  
Remote boot, PXE and Wake-On-LAN support  
On-board RJ45 connector (RJ45 over dual USB connector) with two integral LEDs showing  
combined link integrity and activity (yellow) plus line speed (green/amber)  
•
Available with a second RJ45 over dual USB connector  
29  
KP915GV Product Manual  
2.11  
I/O  
•
•
•
Four USB 2.0 ports on I/O panel via two dual stacked USB over RJ45 connectors  
Four USB 2.0 ports on internal locking headers  
Available with IEEE 1394b controller with support for 1394a  
•
•
Single port via a header connector  
Based on Texas Instruments TSB82AA2 controller and TSB81BA3 transceiver  
2.12  
Power Management  
•
•
Supports ACPI 2.0 with power states S0, S3, S4 (not S4BIOS), S5 and C0, C1, C2, C3  
Supports PCI PME and PCI Express power management event signaling  
Table 3. ACPI Power States  
G0/S0/C0  
Full on  
G0/S0/C1  
G0/S0/C2  
G0/S0/C3  
G1/S3  
Processor is halted  
Processor stops internal clocks  
Processor clocks are disabled and processor in sleep state  
System context is saved to RAM and power removed from all circuits  
except that required to maintain system RAM and resume  
G1/S4  
G2/S5  
System context is saved to disk and power removed from all circuits  
except that required to resume  
Soft off, only resume logic and RTC remain powered  
2.13  
System management  
•
•
•
•
•
•
•
•
•
•
•
System monitoring of voltage, temperature, fans  
Temperature monitoring of processor die, board and remote sensor  
Direct monitoring of lithium cell voltage  
Automatic fan control for 3 fans - CPU, System 1, System 2  
Fan configuration held in BIOS customization block  
Fans can be assigned to any of three thermal zones for automatic control - each zone  
monitored by one of the three thermal sensors  
450mA drive capability for each system fan, 2.2A for the CPU fan  
Anti-tamper security (trigger for chassis intrusion detect)  
Programmable watchdog timer with range of 1 second to 1 hour  
Access to SMBus via 4-pin 2mm header  
2.14  
Security  
•
•
Header for Trusted Platform Module (TPM)  
TCG 1.1 compliant  
30  
KP915GV Product Manual  
2.15  
Programmable Controller (PLD)  
•
Programmable logic device to support configurable system functions  
•
•
•
Supports software-based updates (including field updates)  
Supports customizable logic (by RadiSys, not user customizable)  
Option of 128 or 256 macrocell device (256 for enhanced controller)  
•
•
Controls product write-protect features for BIOS ROM  
•
•
Allows write-protection via software or permanent protection via controller logic  
Supports write-protect jumper covering update of controller logic (override via ICT)  
Total of 13 General purpose I/O lines  
•
10 signals that can be programmed as inputs and outputs  
Direction control in three groups with 2, 3 and 5 bits (20:21, 15:17, 10:14)  
•
•
•
•
Two signals that are input-only  
One signal that is output-only  
Support for character-based LCD panel to display BIOS POST messages and other  
information. Displays have an 8-bit parallel interface. Displayed text is the BIOS Port 80  
codes in the format: “BIOS Code xx”  
2.16  
2.17  
CMOS RAM and RTC  
•
•
256 bytes of CMOS RAM  
Lithium cell with >5 years operating life  
Configuration  
•
Majority of configuration is jumper-less and done through BIOS settings  
Customer can specify BIOS defaults at manufacture  
•
•
•
Operating mode jumper selects normal, configure and recovery modes  
Power supply jumper configures the product to operate with a hard-switched power supply that  
must be used when the PSU does not provide 5V on the 5V standby pin  
•
Target: jumper-less operation for power supply type  
2.18  
BIOS  
•
•
Based on Phoenix Award BIOS  
4Mbit firmware hub BIOS ROM  
•
•
•
•
System and (Intel) video BIOS  
Intel Ethernet remote boot and PXE code  
Fully customizable including video BIOS  
ROM can be optionally socketed with write-protect support  
•
Silent boot (boot message hiding, logo visible), headless operation support  
31  
KP915GV Product Manual  
•
•
All configuration is automatic - no stopping on configuration change  
Resources freed when unused  
2.19  
Operating Systems Support  
•
•
•
•
•
•
Windows XP Professional SP2  
Embedded Windows XP Server SP2  
Red Hat Enterprise Linux 4.0 AS  
Knoppix Linux 3.7 (selected drivers only)  
Windows 2000 Server SP4  
SUSE Linux Enterprise Server 9.0 (selected drivers only)  
2.20  
Power Supplies  
•
•
•
Support for ATX12V power supplies (see Note below)  
Supports hard- and soft-switched power supplies with jumper-less configuration  
See table 4 for required power supply connector.  
Table 4. Power Supply Connector  
Board  
KP915GV  
Connector Type  
2 x 10 pin  
It is recommended that the board be used with a power supply that supports a  
minimum current load of 0.3A or less on the 5V supply rail and 2A or less on the  
3.3V supply rail (see note below).  
Note: This board with CPU and memory may draw as little as 400mA of 5V and 2A  
of 3.3V during start-up (increases depend on installed devices). The power supply  
under consideration must be verified as compatible with the projected total system  
start-up loads for these supply rails. If the power supply minimum current level  
requirements are not at or below the level of current loads that are actually drawn,  
unpredictable start-up operation may result, such as the power supply latching off.  
If this occurs, the AC input to the power supply must be removed and re-attached  
or the power supply switch cycled off and on, in order to turn the system back on.  
32  
KP915GV Product Manual  
2.21  
Reliability and Environmental  
Table 5. Environmental Specifications  
State Value  
Characteristic  
Temperature  
(ambient)  
Operating  
0oC to +55oC  
Operation above +30° C reduces the maximum operational  
relative humidity.  
Operating  
gradient  
±5°C per minute  
-40oC to +85oC, 5°C per minute maximum excursion  
gradient.  
Storage  
Relative  
humidity  
Operating  
10% to 85% RH non-condensing at +30oC, linearly  
decreasing to 5% to 15.5% RH non-condensing at +65oC.  
Storage  
5% to 90% RH non-condensing at +40o C.  
Random 5Hz to 2kHz, 7.7grms, 10 mins in each of 3 axes  
5Hz to 20Hz: 0.004g2/Hz ramping up to 0.04g2/Hz;  
20Hz to 1000Hz: 0.04g2/Hz;  
Vibration  
Operating  
1000Hz to 2000Hz: 0.04g2/Hz ramping down to  
0.01g2/Hz  
Packaged  
Random 5Hz to 2kHz, 9.7grms, 10 min. in each of 3 axes  
5Hz to 20Hz: 0.006g2/Hz ramping up to 0.06g2/Hz;  
20Hz to 1000Hz: 0.06g2/Hz;  
1000Hz to 2000Hz: 0.06g2/Hz ramping down to  
0.02g2/Hz  
Sine 5Hz to 500Hz, 0.15 octave/min up and back, 10 min.  
dwell at 3 resonances in each of 3 axes  
5 to 50Hz swept – 0.1g; 50 to 500Hz swept – 0.25g  
30g 11ms, half-sine  
Shock  
Non-  
operating  
Packaged  
Drop test, 10-up bulk packaging, 30 inches free-fall, 152  
inches/s velocity change  
Altitude  
MTBF  
Operating  
Storage  
To 15000 ft. (4500m)  
To 40000 ft. (12000m)  
The table below summarizes the MTBF (hr) predictions for  
the listed products, without the main processor, memory, or  
battery installed.  
SKU  
35°C  
55°C  
298,735  
295,736  
280,528  
141,946  
156,014  
147,801  
KPGV1W00  
KPGV1G00  
KPGVFG00  
Airflow  
Fuses  
Base on standard Intel guidelines  
Self-resetting PTC fuse (fuses automatically reset without  
user intervention once the load had been removed)  
33  
KP915GV Product Manual  
2.22  
Regulatory Compliance  
Table 6. Regulatory Testing*  
Characteristic  
State  
Value  
ESD  
Operating  
Designed and tested to pass (not certified):  
To IEC 1000-4-2 / EN61000-4-2: 1995  
4kV direct contact, performance criteria B  
6kV direct contact, performance criteria C  
4kV air discharge, performance criteria B  
8kV air discharge, performance criteria C  
Fast transient/burst Operating  
Designed and tested to pass (not certified):  
IEC 1000-4-4/EN61000-4-4: 1995, performance criteria B  
Designed and tested to pass (not certified):  
IEC 1000-4-5 / EN61000-4-5: 1995, performance criteria B  
Designed and tested to pass (not certified):  
IEC 1000-4-6 / EN61000-4-6: 1995, performance criteria B  
Designed and tested to pass (not certified):  
CISPR 22: 1998, Class B  
Surge voltages  
Conducted  
Operating  
Operating  
Radiated emissions Operating  
EN55022, EN55024  
FCC Class B  
Radiated immunity  
Operating  
Operating  
EN61000-4-3, performance criteria A  
Conducted  
immunity  
EN61000-4-6, performance criteria A  
AC power dips and Operating  
interrupts  
EN61000-4-11performance criteria B and C  
Safety  
UL60950-1, CSA60950-1, EN60950-1, IEC60950-1  
CB report to IEC60950-1  
Recognized component to UL60950-1  
UL60950-1 approval will become accessory listing in Q405  
* EMC and immunity testing performed in an example standard desktop chassis.  
34  
KP915GV Product Manual  
3
Specifications  
3.1  
Product Basis  
This product based on the Intel® 915GV Express chipset, designed for the Intel® Pentium® 4  
processor with Hyper-Threading (HT) Technology in the LGA775 package, and is flexible for  
specific customer needs.  
3.2  
Non-Core Integrated Sub-systems  
3.2.1  
I/O Controller Hub 6 (ICH6)  
The sixth generation I/O Controller Hub (Intel ICH6) component provides data buffering and  
interface arbitration required to ensure that system interfaces operate efficiently and provides the  
bandwidth necessary to enable the system to obtain peak performance. The ICH6 supports  
connection to the MCH via the Direct Media Interface. The ICH6 provides up to 4 PCI Express root  
ports, which are compliant to the PCI Express Base Specification revision 1.0a. The ICH6 is  
capable of supporting four SATA ports at generation 1 speeds, eight USB2.0 ports, and up to IDE  
devices. The ICH6 additionally features an integrated High Definition Audio controller to support  
extreme multimedia applications and differentiation through the use of a variety of third party audio  
codecs. The ICH6 features on the KP915GV board include:  
•
Direct Media Interface  
•
•
10Gb/s each direction, full duplex  
Transparent to software  
•
PCI Express  
•
•
•
•
4 PCI Express root ports  
Fully PCI Express 1.0a compliant  
Ports 1-4 can be statically configured as 4x1, or 1x4 (Enterprise applications only)  
Support for full 2.5Gb/s bandwidth in each direction per x1 lane  
•
•
•
•
PCI Bus Interface  
•
•
•
Supports PCI-X Rev 2.2 Specification at 66 MHz  
Seven available PCI REQ/GNT pairs  
Support for 64-bit addressing on PCI using DAC protocol  
Integrated Serial ATA Host Controllers  
•
•
•
Two ports on board  
Data transfer rates up to 1.5Gb/s (150 MB/s)  
Integrated AHCI controller (ICH6R/ICH6RW Only)  
Integrated IDE Controller  
•
•
•
Independent timing of up to two drives  
Ultra ATA/100/66/33, BMIDE and PIO modes  
Tri-state modes to enable swap bay  
Intel High Definition Audio Interface  
35  
KP915GV Product Manual  
•
•
PCI Express endpoint  
Independent Bus Master logic for eight general purpose streams: Four input and four  
output  
•
•
•
•
•
•
•
Support three external Codecs  
Supports variable length stream slots  
Supports multimedia channel, 32-bit sample depth, 192kHz sample rate output  
Provides Mic array support  
Supports memory-based command/response transport  
Allows for non-48kHz sampling output  
Support for ACPI Devices States  
•
•
AC-Link for Audio and Telephony codecs  
•
•
Support for three AC’97 2.3 codecs.  
Independent bus master logic for 8 channels (PCM In/Out, PCM2 In, Mic 1 Input, Mic 2  
Input, Modem In/Out, S/PDIF Out)  
•
•
Support for up to six channels of PCM audio output (full AC3 decode)  
Supports wake-up events  
USB 2.0  
•
•
•
•
•
•
Includes four UHCI Host Controllers, supporting eight external ports  
Includes one EHCI Host Controller that supports all eight ports  
Includes one USB2.0 High-Speed Debug Port  
Supports wake-up from sleeping states S1-S5  
Supports legacy Keyboard/Mouse software  
Maximum total current for all USB devices is 3A  
•
•
Integrated LAN Controller  
•
•
•
•
Integrated ASF Management Controller  
WfM2.0 and IEEE802.3 Compliant  
LAN Connect Interface (LCI)  
10/100Mb/s Ethernet Support  
Power Management Logic  
•
•
•
•
•
•
ACPI 2.0 compliant  
ACPI-defined power states (C1, S1, S3-S5 for Desktop)  
ACPI Power Management Timer  
PCI CLKRUN# and PME# support  
SMI# generation  
All registers readable/restorable for proper resume from 0V suspend states  
36  
KP915GV Product Manual  
•
Support for APM-based legacy power management for non-ACPID Desktop  
implementation  
•
•
•
External Glue Integration  
•
•
Integrated Pull-op, Pull down and Series Termination resistors on IDE, processor I/F  
Integrated Pull-down and Series resistors on USB  
Enhanced DMA Controller  
•
•
Two cascaded 8237 DMA controller  
Supports LPC DMA  
SMBus  
•
•
•
•
•
•
Flexible SMBus/SMLink architecture to optimize for ASF  
Provides independent manageability bus through SMLink interface  
Supports SMBus 2.0 Specification  
Host interface allows processor to communicate via SMBus  
Compatible with most two-wire components that are also I2C compatible  
Slave interface allows an internal or external Microcontroller to access system  
resources  
•
•
•
High Precision Event Timers  
•
Advanced operation system interrupt scheduling  
Timers Based on 82C54  
•
System timer, Refresh request, Speaker tone output  
Real-Time Clock  
•
•
•
256-byte battery-backed CMOS RAM  
Integrated oscillator components  
Lower Power DC/DC Converter implementation  
•
•
System TCO Reduction Circuits  
•
•
•
•
Timers to generate SMI# and Reset upon detection of system hang  
Timer to detect improper processor reset  
Integrated processor frequency strap logic  
Supports ability to disable external devices  
Interrupt Controller  
•
•
•
•
•
Supports up to eight interrupt pins  
Supports PCI 2.3 Message Signaled Interrupts  
Two cascaded 82C59 with 15 interrupts  
Integrated I/O APIC capability with 24 interrupts  
Supports Processor System Bus interrupt delivery  
•
1.5V operation with 3.3V I/O  
37  
KP915GV Product Manual  
•
5V tolerant buffers on IDE, PCI, and Legacy signals  
•
•
•
Integrated 1.5V Voltage Regulator (INTVR) for the Suspend and LAN wells  
Firmware Hub I/F supports BIOS Memory size up to 8 MBytes  
Low Pin Count (LPC) I/F  
•
•
Supports two Master/DMA devices  
Support for Security Device (Trusted Platform Module) connected to LPC  
•
•
GPIO, TTL, Open-Drain, Inversion  
Package 31x31 mm 609 pin mBGA  
3.2.2  
Flash BIOS  
The SST 49LF004B (512K x 8) 4Mb Flash EEPROM, This flash memory device is designed to  
interface with host controllers (chipsets) that support a Low Pin Count (LPC) interface for BIOS  
applications. The SST49LF004B devices comply with Intel’s LPC Interface Specification 1.1,  
supporting single-byte Firmware Memory and LPC Memory cycle types. It as a flash BIOS and it  
will be implemented via the NS PC8374K Super I/O.  
Superflash  
Memory  
LAD[3:0]  
X-Decoder  
INIT#  
WP#  
TBL#  
FWH/LPC  
Interface  
Address Buffers & Latches  
LCLK  
LFRAME#  
ID[3:0]  
GPI[4:0]  
Y-Decoder  
MODE  
R/C#  
A[10:0]  
DQ[7:0]  
QE#  
Control Logic  
Programmer  
I/O Buffers and Data Latche  
Interface  
RST#  
WE#  
FUNCTIONAL BLOCK DIAGRAM  
Figure 7.  
Conforms to Intel LPC Interface Specification 1.1  
Supports Single-Byte LPC Memory and Firmware Memory Cycle Types  
Flexible Erase Capability  
SST 49LF004B Functional Block Diagram  
•
•
•
•
•
Uniform 64 KByte overlay blocks for SST49LF004B  
Chip-Erase for PP Mode Only  
•
•
Single 3.0-3.6V Read and Write Operations  
Superior Reliability  
•
Endurance: 100,000 Cycles (typical)  
38  
KP915GV Product Manual  
•
Greater than 100 years Data Retention  
•
•
Low Power Consumption  
•
•
Active Read Current: 6 mA (typical)  
Standby Current: 10 µA (typical)  
Fast Sector-Erase/Byte-Program Operation  
•
•
•
•
•
•
•
Sector-Erase Time: 18 ms (typical)  
Block-Erase Time: 18 ms (typical)  
Chip-Erase Time: 70 ms (typical)  
Byte-Program Time: 14 µs (typical)  
Chip Rewrite Time: SST49LF004B: 8 seconds (typical)  
Single-pulse Program or Erase  
Internal timing generation  
•
•
Two Operational Modes  
•
•
Low Pin Count (LPC) interface mode for in-system operation  
Parallel Programming (PP) mode for fast production programming  
LPC Interface Mode  
•
•
•
LPC bus interface supporting byte Read and Write  
33 MHz clock frequency operation  
WP# and TBL# pins provide hardware write protect for entire chip and/or top Boot  
Block  
•
•
•
•
•
Block Locking Registers for individual block write-lock and lock-down protection  
JEDEC Standard SDP Command Set  
Data# Polling and Toggle Bit for End-of-Write detection  
5 GPI pins for system design flexibility  
4 ID pins for multi-chip selection  
•
•
Parallel Programming (PP) Mode  
•
•
11-pin multiplexed address and 8-pin data I/O interface  
Supports fast In-System or PROM programming for manufacturing  
Packages 32 pin lead PLCC (10mm x 20mm)  
3.3  
Major Sub-systems  
3.3.1  
Audio Interface  
The motherboard includes High Definition integrated audio function support, using the ICH6  
integrated audio controller and a SigmaTel STAC9200. The STAC9200 is a high quality, 2-channel  
audio codec compatible with the Intel High Definition (HD) Audio Interface. The STAC9200 provides  
Stereo 24-Bit resolution with sample rates up to 192kHz. The STAC9200 incorporates SigmaTel's  
proprietary SD technology to achieve an estimated DAC SNR in excess of 100dB. See Figure 8.  
39  
KP915GV Product Manual  
STAC9200 Block Diagram  
SPDIF  
Receiver  
SPDIF INPin47  
PCM to  
SPDIF  
OUT  
SPDIF Pin48  
MUX  
Stream/  
Stream/  
Channel  
Select  
Channel  
Select  
-6dB  
MONO_OUT  
Pin 37  
Digital  
PC Beep  
vol  
mute  
+0dB  
Pin5  
SD0  
Stream/  
Channel  
Select  
Stream/  
Channel  
Select  
BIT_CLK  
Pin6  
Port A  
Pin Complex  
Pins 39/41  
HP  
Out  
Single Bit Loopback (Loop 3)  
Pin8  
SDI  
Pin10  
SYNC  
Stream/  
Channel  
Select  
Port B  
Pin Complex  
Pins 35/36  
Reset#Pin11  
HP  
Out  
Stream/  
Channel  
Select  
vol  
mute  
Digital Analog  
MUX  
Stream/  
Channel  
Select  
DAC BYPASS MODE  
Loop 1  
Port C  
Pin Complex  
Pins 23/24  
Line  
Out  
Stream/  
Channel  
Select  
Port D  
Pin Complex  
Pins 21/22  
Analog  
PC Beep  
Line  
Out  
vol  
mute  
MIC  
Boost  
STEREO  
ADC  
+22dB  
MIC In  
Pin Complex  
Pins 18/20  
Figure 8.  
SigmaTel STAC9200 High Definition Block Diagram  
The audio Codec includes:  
•
•
•
•
•
•
High performance Σ∆ technology  
100dB DAC SNR  
Intel HD Audio Interface  
Two Channel DACs and ADCs with 24-bit resolution Sample rates up to 192kHz  
Mixer-less design  
Low-latency Karaoke Mode Supported  
•
Integrated Headphone Amps  
•
Stereo Microphone  
•
•
•
•
•
•
•
Supports Stereo Mic  
Microphone Boost 0, 10, 20, 30, 40dB  
Direct CDROM Recording Mixerless Design  
Universal Jacks (TM) Functionality for jack retasking  
Adjustable VREF Out  
Digital PC Beep to all outputs • +3.3V and +5V analog power supply options  
32-pad QFN (5mm x 5mm) and 48-pin LQFP package options  
40  
KP915GV Product Manual  
•
Package 48-pin Lead Free LQFP  
3.3.2  
Hardware Management Interface  
The LM96000, hardware monitor, has a two wire digital interface compatible with SMBus 2.0. Using  
an 8-bit Σ∆ ADC, the LM96000 measures:  
•
•
The temperature of two remote diode connected transistors as well as its own die  
The VCCP, 2.5V, 3.3VSBY, 5.0V, and 12V supply (internal scaling resistors).  
VID[4:0]  
REGISTER  
SMBDAT  
SMBCLK  
SERIAL BUS  
INTERFACE  
VOLTAGE. FAN  
SPEED.  
TEMPREATURE. AND  
LIMIT VALUE  
FA N SPEED  
COUNTER  
TACH[4:1]  
REGISTERS  
PWM1  
PWM2  
PWM3/  
LIMIT  
COMPARATORS  
3.3SBY  
5VIN  
INPUT  
12VIN  
ATTENUATORS  
E XTERNA L  
DIODE SIGNAL  
CONDITIONING  
AND  
2.5VIN  
VCCP_IN  
FAN PWM CONTROL  
&PWM VALUE  
REGISTERS  
8- BIT  
ADC  
ANALOG  
MUTIPLEXER  
REMOTE1+  
REMOTE1 -  
ADDRESS  
ENA BLE  
INTERNAL  
TEMP  
SENSOR  
REMOTE2+  
REMOTE2 -  
Figure 9.  
NS LM96000CIM Block Diagram  
•
•
•
•
•
•
•
•
•
•
•
2-wire, SMBus 2.0 compliant, serial digital interface  
8-bit Σ∆ ADC  
Monitors VCCP, VRTC battery, 3.3 VSBY, 5.0V, and 12V motherboard/processor supplies  
Monitors 2 remote thermal diodes  
Programmable autonomous fan control based on temperature readings  
Noise filtering of temperature reading for fan control  
1.0°C digital temperature sensor resolution  
3 PWM fan speed control outputs  
Provides high and low PWM frequency ranges  
4 fan tachometer inputs  
Monitors 5 Voltage Identification (VID) control lines  
41  
KP915GV Product Manual  
•
•
XOR-tree test mode  
Package 24-pin Lead TSSOP  
3.3.3  
Ethernet Interface  
Either one or two IEEE 802.3 compatible Ethernet ports are available as build options that are  
based around Intel controllers (82562GZ and 82573V or ‘L) to provide 10/100Mbps and/or  
10/100/1000Mbps configuration. Connection to the network is achieved through two RJ45  
connectors, available on the I/O (Input/Output) panel, which have integral LED’s to provide Link  
status information.  
•
Intel 82562GZ 10/100BASE-TX Fast Ethernet Controller  
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
IEEE 802.3 10BASE-T/100BASE-TX compliant physical layer interface  
IEEE 802.3u Auto-Negotiation support  
Digital Adaptive Equalization control  
Link status interrupt capability  
XOR tree mode support  
3-port LED support (speed, link and activity)  
10BASE-T auto-polarity correction  
LAN Connect interface  
Alert on LAN Functionality, ASF 1.0 alerting  
Diagnostic loop-back mode  
1:1 transmit transformer ratio support  
Low power (less than 300 mW in active transmit mode)  
Reduced power in “unplugged mode” (less than 50 mW)  
Automatic detection of “unplugged mode”  
3.3 V device  
Package 15x15 mm 196 pin BGA  
•
Intel 82573V (or ‘L) 10/100/1000BASE-T Gigabit Ethernet Controller  
•
•
•
•
•
Uses x1 PCI-E on ICH6  
Peak bandwidth 2Gb/s per direction  
PCI-E power management  
Optimized transmit and receive queues  
IEEE802.x compliant flow control support with software controllable pause times and  
threshold values  
•
•
Integrated PHY for 10/100/1000 Mbps full and half duplex operation  
DSP architecture implements digital adaptive equalization, echo cancellation, and cross-  
talk cancellation  
•
•
Advanced packet filtering  
Intel Active Management Technology  
42  
KP915GV Product Manual  
•
•
•
•
•
•
•
Support ASF1.0 and 2.0 alerting  
Support Wake On LAN (WOL) and ACPI  
Programmable LED functionality  
On-chip power control circuitry  
Loop-back capabilities  
IEEE 802.3ab Auto-Negotiation support and PHY compliance with compatibility  
Package 15x15 mm 196 pin TF-BGA  
3.3.4  
Super I/O Interface  
The motherboard is designed to support the NS PC8374K controller. The Super I/O provides  
support that includes floppy, PS/2, serial port, and parallel port to rest of platform through the ICH6  
via the Low Pin Count (LPC) interface.  
Power Management  
South Bridge  
System  
BIOS  
LPC Bus  
FLOCK  
Serial Interfaces  
Parallel Port Interface  
Floppy Drive Interface  
PS/2 Interfaces  
KBC Ports  
PC8374K  
SMBus I/F  
SMI  
Infrared Interface  
GPIO Ports  
Vbat  
Tacho  
PWM  
LEDS  
Power  
Supply  
Reset  
Logic  
Drv(3)  
FAN(3)  
Figure 10.  
PC8374K Block Diagram  
3.3.4.1 System Health Support  
Fan Monitor and Control  
•
•
•
•
Three PWM-based fan controls  
Four 16-bit resolution tachometer inputs  
Software or local temperature feedback control  
43  
KP915GV Product Manual  
•
•
Heceta6-compatible register set accessible via the LPC interface and SMBus  
•
Supports the following combinations of LMxx devices:  
•
•
•
LM41 and optional LM30  
LM32  
LM40  
•
Simultaneous read support via LPC interface and SMBus  
Generates SMI on critical temperature event  
3.3.4.2 Glue Functions  
•
•
•
Flash Write Protect control (using GPIO) with optional SMI generation when  
cleared  
Floppy Disk Drive Write Protect (WGATE) lockable control (cleared only by  
hardware reset)  
Generates the power-related signals:  
•
•
Main Power good  
Power distribution control (for switching between Main and Standby  
regulators)  
•
•
Resume reset (Master Reset) according to the 5V standby supply status  
Main power supply turn on (PS_ON)  
•
•
Voltage translation between 2.5V or 3.3V levels (DDC) and 5V levels (VGA) for  
the SMBus serial clock and data signals  
•
•
•
Isolation circuitry for the SMBus serial clock and data signals  
Buffers PCI_RESET to generate three reset output signals  
Buffers PWRGD_PS to generate IDE reset output.  
Generates “highest active supply” reference voltage  
•
•
Based on 3.3V and 5V Main supplies  
Based on 3.3V and 5V Standby supplies  
•
•
High-current LED driver control for Hard Disk Drive activity indication  
Software selectable alternative functionality, through pin multiplexing  
3.3.4.3 General-Purpose I/O (GPIO) Ports  
•
•
•
All 16 GPIO ports powered by Voltage Standby 3V (VSB3)  
Each pin individually configured as input or output  
Programmable features for each output pin:  
•
•
Drive type (open-drain, push-pull or TRI-STATE)  
TRI-STATE on detection of falling VDD3 for VSB3-powered pins driving  
VDD-supplied devices  
•
Programmable option for internal pull-up resistor on each input pin (some with  
internal pull-down resistor option)  
44  
KP915GV Product Manual  
•
•
Lock option for the configuration and data of each output pin  
15 GPIO ports generate IRQ/SMI/SIOPME# for wake-up events; each GPIO has  
separate:  
•
•
•
•
•
Enable control of event status routing to IRQ  
Enable control of event status routing to SMI  
Enable control of event status routing to SIOPME# (via SWC)  
Polarity and edge/level selection  
Programmable de-bouncing  
3.3.4.4 Power Management  
•
•
Supports ACPI Specification Revision 2.0b, July 27, 2000  
System Wake-Up Control (SWC)  
•
Optional routing of events to generate SCI (SIOPME#) on detection of:  
•
•
•
•
•
Keyboard or Mouse events  
Ring Indication RI on each of the two serial ports  
General-Purpose Input Events from 15 GPIO pins  
IRQs of the Keyboard and Mouse Controller  
IRQs of the other internal modules  
•
•
Optional routing of the SCI (SIO PME#) to generate IRQ (SERIRQ)  
Implements the GPE1_BLK of the ACPI General Purpose (Generic)  
Register blocks with child” events  
•
VSB3-powered event detection and event-logic configuration  
•
Enhanced Power Management (PM), including:  
•
•
•
•
•
Special configuration registers for power down  
Low-leakage pins  
Low-power CMOS technology  
Ability to disable all modules  
High-current LED drivers control (two LEDs) for power status indication  
with:  
•
•
Standard blinking, controlled by software  
Advanced blinking, controlled by power supply status, sleep state or  
software  
•
•
Special blinking, controlled by power supply status, sleep state and  
software bit  
VBAT-powered indication of the Main power supply state before an AC  
power failure  
•
Keyboard Events  
Wake-up on any key  
•
45  
KP915GV Product Manual  
•
•
•
Supports programmable 8-byte sequence “Password” or “Special Keys”  
for Power Management  
Simultaneous recognition of three programmable keys (sequences):  
“Power”, “Sleep” and “Resume”  
Wake-up on mouse movement and/or button click  
3.3.4.5 Bus Interface  
•
LPC Bus Interface  
•
•
•
•
•
Based on Intel’s LPC Interface Specification Revision 1.1, August 2002  
I/O, Memory and 8-bit Firmware Memory read and write cycles  
Up to four 8-bit DMA channels  
Serial IRQ (SERIRQ)  
Supports registers memory and I/O mapping  
•
Configuration Control  
•
•
•
PnP Configuration Register structure  
PC01 Specification Revision 1.0, 1999-2000 compliant  
Base Address strap (BADDR) to setup the address of the Index-Data  
register pair (defaults to 2Eh/2Fh)  
•
Flexible resource allocation for all logical devices:  
•
•
•
Re-locatable base address  
15 IRQ routing options to serial IRQ  
Up to four optional 8-bit DMA channels  
•
Configurable feature sets:  
•
•
Software selectable  
VSB3-powered pin multiplexing  
3.3.4.6 Legacy Modules  
Serial Ports 1 and 2  
•
•
•
•
Software-compatible with the NS16550A and NS16450  
Support shadow register for write-only bit monitoring  
Data rates up to 1.5 Mbaud  
•
Serial Infrared Port (SIR)  
•
•
•
•
•
Software compatible with the 16550A and the 16450  
Shadow register support for write-only bit monitoring  
HP-SIR  
ASK-IR option of SHARP-IR  
DASK-IR option of SHARP-IR  
46  
KP915GV Product Manual  
•
Consumer Remote Control supports RC-5, RC-6, NEC, RCA and RECS  
80  
•
IEEE 1284-compliant Parallel Port  
•
•
•
•
•
•
ECP, with Level 2 (14 mA sink and source output buffers)  
Software or hardware control  
Enhanced Parallel Port (EPP) compatible with EPP 1.7 and EPP 1.9  
Supports EPP as mode 4 of the Extended Control Register (ECR)  
Selection of internal pull-up or pull-down resistor for Paper End (PE) pin  
Supports a demand DMA mode mechanism and a DMA fairness  
mechanism for improved bus utilization  
•
Protection circuit that prevents damage to the parallel port when a printer  
connected to it is powered up or is operated at high voltages (in both  
cases, even if the PC8374K is in power-down state)  
•
Floppy Disk Controller (FDC)  
•
Software compatible with the PC8477 (the PC8477 contains a superset of  
the FDC functions in the μDP8473, NEC μPD765A/B and N82077  
devices)  
•
•
•
•
Error-free handling of data overrun and underrun  
Programmable write protect  
Supports FM and MFM modes  
Supports Enhanced mode command for three-mode Floppy Disk Drive  
(FDD)  
•
•
•
Perpendicular recording drive support for 2.88 MBytes  
Burst (16-byte FIFO) and Non-Burst modes  
Full support for IBM Tape Drive Register (TDR) implementation of AT and  
PS/2 drive types  
•
•
High-performance digital separator  
Supports fast tape drives (2 Mbps) and standard tape drives (1 Mbps, 500  
Kbps and 250 Kbps)  
•
Keyboard and Mouse Controller (KBC)  
•
•
•
•
8-bit microcontroller, software compatible with 8042AH and PC87911  
Standard interface (60h, 64h, IRQ1 and IRQ12)  
Supports two external swappable PS/2 interfaces for keyboard and mouse  
Programmable, dedicated quasi-bidirectional I/O lines (GA20/P21,  
KBRST/P20)  
3.3.4.7 Clocking, Supply, and Package Information  
•
Clocks  
•
LPC (PCI) clock input (up to 33 MHz)  
47  
KP915GV Product Manual  
•
On-chip Clock Generator:  
•
•
•
•
Generates 48 MHz clock  
Generates 32.768 KHz internal clock  
VSB3 powered  
Based on the 14.31818 MHz clock input  
•
•
•
Protection  
•
•
•
•
All pins are 5V tolerant and back-drive protected (except LPC bus pins)  
High ESD protection of all the pins  
Pin multiplexing selection lock  
Configuration register lock  
Testability  
•
XOR tree structure  
•
•
Includes all the pins (except supply and analog pins)  
Selected at power-up by strap input (TEST)  
•
TRI-STATE pins, selected at power-up by strap input (TRIS)  
Power Supply  
•
•
•
•
•
3.3V supply operation  
Separate pin pairs for main (VDD3) and standby (VSB3) power supplies  
Backup battery input (VBAT) for SWC indications  
Low standby power consumption  
Very low power consumption from backup battery (less than 0.5 μA)  
•
Package 128-pin PQFP  
3.4  
Motherboard Power Consumption  
The motherboard power consumption is highly dependent on the processor, memory and devices  
attached and also on the software that is running and the power state that the board is in. The  
figures given below are a guide to the power requirements to expect under selected conditions.  
They should not be interpreted as maximum requirements. The figures are based on  
measurements of a real system configured as shown in the following table.  
It is recommended that the board be used with a power supply that supports a minimum  
current load of 0.3A or less on the 5V supply rail and 2A or less on the 3.3V supply rail.  
This board with CPU and memory may draw as little as 400mA of 5V and 2A of 3.3V during  
start-up (increases depend on installed devices). The power supply under consideration  
must be verified as compatible with the projected total system start-up loads for these  
supply rails. If the power supply minimum current level requirements are not at or below the  
level of current loads that are actually drawn, unpredictable start-up operation may result,  
such as the power supply latching off. If this occurs, the AC input to the power supply must  
be removed and re-attached or the power supply switch cycled off and on, in order to turn  
the system back on.  
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KP915GV  
Item  
Description  
Power Supply  
Current Meter  
Drives  
FSP350-60PLN/350W  
PROVA CM-01 AC/DC Clamp Meter  
Powered independently  
Hard Drive Disk  
Network  
WD Caviar SE 1200/120GB Serial ATA Disk  
On-board (single LAN, not operating)  
Configuration 1 : Heavy Load  
Item  
Description  
Memory  
Video  
Apacer ELPIDA chip DDR2-400 1GB X4 (P/N: 78.01066.420)  
On-board (8MB shared Memory)  
Network  
On-board (single 10/100 LAN, not operating)  
Intel Pentium 4 at 3.4GHz with 800MHz Processor Bus  
Motherboard Current (A)  
Power  
Mode  
+3.3V +5V +12V +12V(CPU) -12V +5Vsby Total (W)  
MS-DOS Prompt  
without power management  
3.22 1.46 0.32  
6.82  
0.02  
0.05  
104.10  
Windows XP desktop idle  
Windows XP hibernate (S4)  
Windows XP shutdown  
3.25 1.46 0.32  
0.00 0.00 0.00  
0.00 0.00 0.00  
2.70 1.36 0.30  
0.00 0.00 0.00  
3.13  
0.00  
0.00  
3.06  
0.00  
0.02  
0.00  
0.00  
0.05  
0.00  
0.04  
0.41  
0.37  
0.02  
0.43  
59.87  
2.05  
1.85  
Windows XP standby (S1)  
Windows XP standby (S3)  
56.73  
2.15  
Windows XP stress test  
(3DMark03)  
Windows XP stress test  
(PCMark04)  
Windows XP stress test  
(Intel Maxpower v1.4.2)  
4.29 2.16 0.52  
3.58 1.77 0.52  
3.50 1.67 0.51  
8.43  
8.77  
0.02  
0.02  
0.03  
0.05  
0.04  
0.05  
132.85  
132.58  
156.11  
10.79  
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Configuration 2 : Light Load  
Item  
Memory  
Video  
Description  
Micron MT8HF3264AY-40EB3 256MB DDR2-400 CL3 X1  
On-board (8MB shared Memory)  
Network  
On-board (single LAN, not operating)  
Intel Celeron 4 at 2.93GHz with 533MHz Processor Bus  
Motherboard Current (A)  
Mode  
Power  
+3.3V +5V +12V +12V(CPU) -12V +5Vsby Total (W)  
MS-DOS Prompt  
without power management  
2.96 0.74 0.32  
3.06 0.75 0.35  
0.00 0.00 0.00  
0.00 0.00 0.00  
2.52 0.65 0.33  
0.00 0.00 0.00  
3.89 1.09 0.35  
4.14  
4.08  
0.00  
0.00  
1.75  
0.00  
4.91  
0.02  
0.02  
0.00  
0.00  
0.02  
0.00  
0.02  
0.05  
0.05  
0.41  
0.38  
0.05  
0.41  
0.05  
67.48  
67.50  
2.05  
Windows XP desktop idle  
Windows XP hibernate (S4)  
Windows XP shutdown  
1.90  
Windows XP standby (S1)  
Windows XP standby (S3)  
37.02  
2.05  
Windows XP stress test  
(3DMark03)  
81.90  
Windows XP stress test  
(PCMark04)  
Windows XP stress test  
(Intel Maxpower v1.4.2)  
3.17 0.84 0.34  
3.09 0.77 0.34  
5.00  
6.48  
0.02  
0.02  
0.05  
0.05  
79.23  
96.38  
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4
Motherboard BIOS  
4.1  
BIOS Features  
•
•
Phoenix Award BIOS  
Intel® Pentium® 4 "Prescott" processor in an LGA775 socket with an 800MHz or 533MHz  
FSB and microcode patch  
•
•
Intel 915GV chipset initialization modules and Intel memory sizing reference code  
Dual channel DDR2 400/533 MHz  
•
•
4 DDR2 DIMMs with 4GB Maximum capacity  
Mixed speed DIMM configuration will default to the slowest speed DIMM installed  
•
NS PC8374K initialization module (supports swappable PS/2 interfaces for keyboard and  
mouse)  
•
•
•
•
•
•
•
•
•
•
•
NS LM96000 CIM initialization module and healthy monitor module  
4MB FWH flash ROM in PLCC package  
PC2001 compliant  
PCI bus specification v.2.2 compliant  
PCI Express specification Rev. 1.0a compliant  
SMBus 2.0 compliant  
Plug and play specification version 1.0A compliant  
APM 1.2 compliant  
ACPI 2.0 compliant  
SMBIOS 2.3 compliant  
UHCI and EHCI support  
•
•
Fully USB legacy boot  
USB keyboard/mouse support  
•
•
360K, 720K, 1.2M, 1.44M, 2.88M FDD, LS-120, 120Mbyte floptical drive support  
Enhanced IDE HDD  
•
•
•
•
Auto-detect HDD type & access mode (LBA / CHS / Large)  
Auto detect & Up to PIO mode 4 support  
Ultra DMA 33/66/100 support  
INT13 extension support  
•
BIOS Boot Specification 1.0x compliant  
•
•
•
•
•
Boot from CD-ROM drive (FDD or HDD image - el Torito)  
Boot from any one of 4 hard drives (C, D, E, F)  
Boot from SCSI (need SCSI option ROM)  
Boot from LS-120, IOMEGA ATAPI ZIP drive  
Boot from network (int18)  
•
•
SATA interface support for Legacy IDE, Native IDE, and Enhanced non-AHCI modes  
Setup utility  
4.2  
Post and Boot  
After power-up or reset, the BIOS perform a self-test, POST, that attempts to determine if further  
operation is possible and that the detected configuration is expected. This process can complete  
normally or result in a warning or an error. The boot process does not stop after a warning but  
displays a message on the primary display device. If an error is detected, the boot process is  
halted. If possible, a message is displayed but failures early on in the test can only be indicated by  
POST codes.  
Once the initial part of the self-test process is completed, the display device is initialized and boot  
messages can then be sent to the display. By default, the display is in Quietboot mode in which the  
customizable logo is visible on screen. If the Quietboot mode is disabled (BIOS Setup) then sign-on  
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and test progress messages are visible. Pressing the 'TAB' key on the keyboard during a Quietboot  
switches the display to text mode - providing the progress messages.  
The BIOS will then search for boot devices in the order configured by the BIOS Setup and load an  
operating system from the first boot device found. Control is then passed to the operating system  
and the motherboard BIOS plays no further part in the boot except to provide run-time services.  
4.2.1  
Hotkeys  
Key  
DEL  
TAB  
Function  
Enter BIOS Setup  
Switch Quietboot to disable  
Availability  
POST  
POST in Quietboot Mode  
4.3  
Setup Utility  
The BIOS Setup utility is provided to perform system configuration changes and to display current  
settings and environment information. The BIOS Setup utility stores configuration settings in  
system non-volatile storage. Changes affected by BIOS Setup will not take effect until the system is  
rebooted.  
4.3.1  
4.3.2  
4.3.3  
Enter Setup  
During the boot, pressing the 'DEL' key on the keyboard requests the Setup utility be launched  
once the self-test is complete and before searching for a boot device.  
Configuration Reset  
Activating the Clear CMOS jumper produces a "reset system configuration" request and the BIOS  
loads the default system configuration values during the next POST.  
Keyboard Command  
The Keyboard Command Bar supports the following keys:  
Key  
Option  
Description  
The Enter key is used to activate sub-menus, pick lists, or to  
select a sub-field. If a pick list is displayed, the Enter key will  
select the pick list highlighted item, and pass that selection in the  
parent menu.  
Enter  
Execute  
The ESC key provides a mechanism for backing out of any field.  
This key will undo the pressing of the Enter key. When the ESC  
key is pressed in any major menu, the exit confirmation window is  
displayed and the user is asked whether changes can be  
discarded.  
ESC  
Exit  
Select Item  
Used to move between the items.  
↑ ↓ ↔  
+ - PU  
PD  
Change Value  
Used to change options or increase/decrease value.  
F1  
General Help  
Show the help message box.  
F5  
F7  
Previous Values  
Default settings  
Used to return to previous value  
Used to load defaults to Setup items  
Pressing F10 causes a message to appear:  
If “Yes” is selected and the Enter key is pressed, all changes are  
saved and setup is exited. If “No” is selected and the Enter key is  
pressed, or the ESC key is pressed, the user is returned to where  
they were before F10 was pressed without affecting any existing  
values.  
Save Changes  
and Exit  
F10  
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4.3.4  
4.3.4.1  
Setup Configuration  
Standard CMOS Features  
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Note: The Main BIOS level in the figure above is an example only and doesn’t necessarily reflect  
the latest BIOS on delivered products or available for downloading.  
4.3.4.2  
Advanced BIOS Features  
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4.3.4.3  
Advanced Chipset Features  
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4.3.4.4  
Integrated Peripherals  
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4.3.4.5  
Power Management Setup  
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4.3.4.6  
PnP/PCI Configurations  
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4.3.4.7  
PC Health Status  
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4.3.4.8  
Load Default Settings  
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4.3.4.9  
Set Supervisor Password  
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4.3.4.10  
Set User Password  
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4.3.4.11  
Save & Exit Setup  
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4.3.4.12  
Exit Without Saving  
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4.4  
Power Management  
Supports APM and ACPI 2.0 with power states S0, S3, S4 (not S4BIOS), S5 and C0, C1, C2, C3.  
4.4.1  
ACPI Wake-up Support  
The next table indicates which events can cause an ACPI wake-up and from which sleep states.  
Event  
Power Switch  
S1  
v
S3  
v
S4  
v
S5  
v
RTC alarm  
PS2 Mouse/Keyboard  
USB Device  
PME  
v
v
v
v
v
v
v
v
v
v
v
v
v
v
WOL  
v
4.5  
Hardware Monitor and Auto Fan Control  
The hardware monitoring values and auto fan control configure was in 'Setup menu -> System  
Monitor' item.  
4.5.1  
Hardware Monitor  
The LM96000 measures:  
•
•
•
•
Temperature of two remote diodes and its own die.  
VCCP, 3.3VSBY, 5.0V, and 12V.  
3 fan tachometer inputs.  
Lithium Cell Battery Voltage  
4.5.2  
Automatic Fan Control  
In Auto Fan Mode, the LM96000 will automatically adjust the PWM duty cycle of the PWM outputs.  
PWM outputs are assigned to a thermal zone based on the fan configuration registers. It is possible  
to have more than one PWM output assigned to a thermal zone. For example, PWM outputs 2 and  
3, connected to two chassis fans, may both be controlled by thermal zone 2. At any time, the  
temperature of a zone exceeds its absolute limit, all PWM outputs will go to 100% duty cycle to  
provide maximum cooling to the system.  
4.6  
Power LED  
LED  
State  
OFF  
Indicates  
The motherboard is powered down or in one of the  
ACPI sleep states (including S1).  
Single color  
ON  
The motherboard is fully powered up (S0).  
The motherboard is fully powered up (S0) with a  
message waiting (as determined by ACPI TAPI).  
The motherboard is powered down or in ACPI sleep  
states S4 or S5 (no +5V supply available)  
The motherboard is fully powered up (S0).  
The motherboard is in sleep state S1.  
Blinking  
Dual Color  
(Green /Yellow)  
OFF  
Green  
Yellow  
Blinking  
green  
The motherboard is fully powered up (S0) with a  
message waiting (as determined by ACPI TAPI).  
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LED  
State  
Blinking  
yellow  
Indicates  
The motherboard is in sleep state S1 with a message  
waiting (as determined by ACPI TAPI).  
4.7  
CPLD  
4.7.1  
POST Code Display  
Support for character-based LCD panel to display BIOS POST messages and other information.  
Displays have an 8-bit parallel interface. Text for display is the BIOS Port 80 codes in the format:  
"BIOS Code xx".  
This section describes how the LCD character display support is implemented. With the exception  
of the backlight power pins, the display connector is wired directly to the motherboard port GPIO  
pins.  
The logic in the CPLD is driven purely by software; there is no automatic generation of the interface  
control signals. In this way, the use of the display is controlled exclusively by software (or BIOS).  
The PWM signal from the CPLD requires an inverting low-pass filter in order to correctly drive the  
contrast voltage to the display.  
GPIO Header  
4.7.2  
4.7.3  
BIOS Protection  
Support 2 GPIO pins to control the FWH pins TBL# (Top Block Lock) and WP# (Write Protect) to  
protect the BIOS code.  
LAN Controller  
Support 2 GPIO pins to Enable/Disable on-board LAN1/LAN2 controller.  
4.8  
4.9  
TPM  
Pr-allocate 16 byte size I/O from 4700h for TPM module.  
Normal, Configure and Recovery Mode  
The motherboard can operate in one of three modes - Normal, Recovery and Configure by jumper  
setting. Refer to section 1.4 (Configuration) for further information.  
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4.9.1  
4.9.2  
Normal Mode  
This is the factory default position the jumper should be in for normal operation of the motherboard.  
Configure Mode  
The Configure mode forces the BIOS into Setup with the manufacturer defaults loaded. The mode  
should be returned to normal before re-starting.  
4.9.3  
Recovery Mode  
The Recovery mode expects a recovery disk in floppy disk drive A and will wait until one is found  
before performing the recovery operation.  
4.10  
Update and Recovery Diskette  
4.10.1  
Update Diskette  
The upgrade process requires two files:  
•
•
The new BIOS file (e.g., newbios.bin)  
The upgrade utility (awdflash.exe).  
Although it may be possible to use different media for the files, this manual assumes that you are  
using a floppy disk. Prepare for the upgrade process as follows:  
•
•
•
Create a bootable floppy disk.  
Transfer the two Award files listed above onto the diskette.  
Check and configure the BIOS write-protection jumper.  
You are now ready to start the upgrade process.  
CAUTION  
Do not interrupt the upgrade program while it is running! Interrupting the program leaves the  
system without BIOS and renders the system unusable. If the power goes off during the few  
seconds that the program is running, the system will be left without a working BIOS and it will be  
necessary to install a correctly programmed flash EPROM.  
4.10.2  
Recovery Diskette  
The recovery diskette should be used to recover a system BIOS when the motherboard no longer  
operates after a failed BIOS update operation. The process is described below.  
•
•
•
Create a bootable floppy disk as the Update section.  
Create a AUTOEXEC.BAT and following command included ‘AWDFLASH ****.BIN /py/sn/wb/r’  
Check and configure the operation mode jumper to recovery mode.  
4.11  
4.12  
Tamper Detection  
When detecting the tamper signal low, BIOS can be configured to display a warning message or to  
require a password at the next boot. Since the lithium cell powers the logic, the tamper detection  
continues to operate even if the board is un-powered.  
OEM Features  
4.12.1  
POST Logo Change  
CBROM.exe is the Award BIOS ROM combination utility. CBROM runs at a DOS prompt. Use the  
following command to change a full-screen logo to your BIOS bin file.  
Cbrom AAA.bin /logo test.bmp  
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NOTE  
The full-screen logo file must be 640X464 pixels with 16 colors BMP format.  
4.12.2  
CMOS Default Change  
The MODBIN6.EXE is the utility that runs at a DOS prompt for binary code manipulation. It allows  
selection of customized default CMOS (BIOS setup) settings.The process is described below:  
Execute the MODBIN6.exe  
•
•
•
Load the BIOS bin file by the ‘File’ option.  
Change the ‘Edit Setup Screen’ to change the default settings.  
Save the modified BIOS file by ‘File’ option.  
4.13  
PXE  
BIOS locate and configure all PXE-capable boot devices (UNDI Option ROMs) in the system follow  
the BIOS Boot Specification (BBS) v1.01or later to support network adapters as boot devices.  
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4.14  
BIOS Flash Usage Map  
4.15  
Processor Microcode Support  
IA32 processors have the capability of correcting specific errata through the loading of an Intel-  
supplied data block (i.e. microcode update). Below table list the microcode that BIOS store in flash,  
and will load it into each processor during POST.  
Name  
Revision  
CPUID  
F43  
F41  
F37  
F34  
Stepping  
N-0  
M9DF4304  
M9DF4112  
M0DF3702  
M1DF3414  
M0DF320A  
M10F252C  
04  
12  
02  
14  
0A  
2C  
E-0  
C-1  
D-0  
B-1  
F32  
F25  
M-0  
4.16  
SMBIOS  
The BIOS provides support for the SMBIOS specification to create a standardized interface for  
manageable attributes that are expected to be supported by DMI-enabled computer systems. The  
BIOS provides this interface via data structures through which the system attributes are reported.  
Using SMBIOS, a system administrator can obtain the types, capabilities, operational status,  
installation date and other information about the system components.  
The following table describes the types of SMBIOS structures supported by the system BIOS.  
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Item  
SMBIOS Data  
BIOS Vendor  
Expected Result  
Phoenix Technologies, LTD  
BIOS Version  
Starting Addr Seg  
BIOS Release Date  
BIOS ROM Size  
Manufacturer  
4C7R2BXX  
Type 00: BIOS  
Information  
1
E000h  
MM/DD/YYYY  
512K  
‘RadiSys‘  
Product Name  
Version  
‘Endura KP915GV‘  
‘ ‘  
‘ ‘  
Type 01: System  
Information  
2
Serial Number  
FFFFFFFF-FFFFFFFF  
FFFFFFFF-FFFFFFFF  
UUID  
Manufacturer  
Product  
‘Foxconn‘  
Type 02:  
Baseboard  
Information  
‘Endura KP915GV‘  
‘ ‘  
3
4
Version  
Serial Number  
Manufacturer  
Type  
‘50bbcccddddd‘  
‘RadiSys‘  
Desktop  
Type 03: System  
Enclosure  
Version  
‘ ‘  
Serial Number  
Asset Tag Number  
Socket Designation  
Processor Type  
Processor Family  
Processor Manufacturer  
Processor ID  
‘ ‘  
‘ ‘  
LGA 775  
Central Processor  
Other  
Intel  
Depend on CPU  
Depend on CPU  
Depend on CPU  
Depend on CPU  
Depend on CPU  
Depend on CPU  
Depend on CPU  
Other  
Type 04:  
Processor  
Information  
Processor Version  
Voltage  
5
External Clock  
Max Speed  
Current Speed  
Status  
Processor Upgrade  
Socket Designation  
Cache Configuration  
Maximum Cache Size  
Type 07: Cache  
Information  
6
L1-Cache  
Depend on CPU  
Depend on CPU  
Installed Size  
Depend on CPU  
Depend on CPU  
Supported SRAM Type  
Current SRAM Type  
Depend on CPU  
Cache Speed  
Depend on CPU  
03h(None)  
Error Correction Type  
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Item  
SMBIOS Data  
Expected Result  
System Cache Type  
Associativity  
Data  
Depend on CPU  
L2-Cache  
Socket Designation  
Cache Configuration  
Maximum Cache Size  
Depend on CPU  
Depend on CPU  
Installed Size  
Depend on CPU  
Depend on CPU  
Depend on CPU  
Depend on CPU  
Supported SRAM Type  
Current SRAM Type  
Cache Speed  
Type 07: Cache  
Information  
7
Error Correction Type  
System Cache Type  
Associativity  
03h(None)  
Unified  
Depend on CPU  
PCI0  
Slot Designation  
Slot Type:  
PCI  
Slot Data Bus Width:  
Current Usage:  
Slot Length:  
32Bit  
Available  
Short Length  
001  
Type 09: System  
Slots  
8
Slot ID:  
Slot Characteristics:  
Slot Characteristics 2:  
Slot Designation  
Slot Type:  
Provides 3.3V  
PME enable  
PCI1  
PCI  
Slot Data Bus Width:  
Current Usage:  
Slot Length:  
32Bit  
Available  
Short Length  
002  
Type 09: System  
Slots  
9
Slot ID:  
Slot Characteristics:  
Slot Characteristics 2:  
Slot Designation  
Slot Type:  
Provides 3.3V  
PME enable  
PCI-E-0  
Other  
Slot Data Bus Width:  
Current Usage:  
Slot Length:  
Other  
Available  
Other  
Type 09: System  
Slots  
10  
11  
Slot ID:  
0003  
Slot Characteristics:  
Slot Characteristics 2:  
Slot Designation  
Slot Type:  
Provides 3.3V  
PME enable  
PCI-E-1  
Other  
Type 09: System  
Slots  
Slot Data Bus Width:  
Current Usage:  
Other  
Available  
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Item  
SMBIOS Data  
Slot Length:  
Expected Result  
Other  
0004  
Slot ID:  
Slot Characteristics:  
Slot Characteristics 2:  
Provides 3.3V  
PME enable  
Location  
03h(System board or motherboard)  
Use  
03h(System Memory)  
03h(None)  
Memory Error Correction  
Memory Capacity  
Type 16 Physical  
Memory Array  
12  
Depend on MEM  
Memory Error Information Handle  
Unknown  
Number of Memory Devices  
0002  
Memory Error Information Handle  
Unknown  
Total Width  
Data Width  
Size  
Depend on MEM  
Depend on MEM  
Depend on MEM  
09h(DIMM)  
00  
Type 17 Memory  
Device  
Form Factor  
Device Set  
Device Locator  
Bank Locator  
Memory Type  
Type Detail  
13  
A0  
Bank 0/1  
0Fh(SDRAM)  
0080h(Synchronous)  
Memory Error Information Handle  
Unknown  
Total Width  
Depend on MEM  
Depend on MEM  
Depend on MEM  
09h(DIMM)  
00  
Data Width  
Size  
Type 17 Memory  
Device  
Form Factor  
Device Set  
14  
Device Locator  
Bank Locator  
Memory Type  
Type Detail  
B0  
Bank 2/3  
0Fh(SDRAM)  
0080h(Synchronous)  
Unknown  
Memory Error Information Handle  
Total Width  
Type 17 Memory  
Device  
15  
Depend on MEM  
Depend on MEM  
Depend on MEM  
09h(DIMM)  
00  
Data Width  
Size  
Form Factor  
Device Set  
Device Locator  
A1  
100  
KP915GV Product Manual  
Item  
SMBIOS Data  
Bank Locator  
Memory Type  
Type Detail  
Expected Result  
Bank 4/5  
0Fh(SDRAM)  
0080h(Synchronous)  
Unknown  
Memory Error Information Handle  
Total Width  
Depend on MEM  
Depend on MEM  
Depend on MEM  
09h(DIMM)  
Data Width  
Size  
Form Factor  
Type 17 Memory  
16  
Device  
Device Set  
00  
Device Locator  
Bank Locator  
Memory Type  
Type Detail  
B1  
Bank 6/7  
0Fh(SDRAM)  
0080h(Synchronous)  
Starting Address  
Ending Address  
Depend on MEM  
Depend on MEM  
Type 19 Memory  
Array Mapped  
Address  
17  
18  
Partition Width  
Depend on MEM  
Depend on MEM  
Depend on MEM  
Depend on MEM  
Depend on MEM  
Depend on MEM  
Depend on MEM  
Depend on MEM  
Depend on MEM  
Depend on MEM  
Depend on MEM  
Depend on MEM  
Depend on MEM  
Depend on MEM  
Depend on MEM  
Depend on MEM  
Depend on MEM  
Depend on MEM  
Depend on MEM  
Depend on MEM  
Depend on MEM  
Starting Address  
Ending Address  
Type 20 Memory  
Device Mapped  
Address  
Partition Row Position  
Interleave Position  
Interleaved Data Depth  
Starting Address  
Ending Address  
Type 20 Memory  
Device Mapped  
Address  
19  
Partition Row Position  
Interleave Position  
Interleaved Data Depth  
Starting Address  
Ending Address  
Type 20 Memory  
Device Mapped  
Address  
20  
21  
Partition Row Position  
Interleave Position  
Interleaved Data Depth  
Starting Address  
Type 20 Memory  
Device Mapped  
Address  
Ending Address  
Partition Row Position  
Interleave Position  
Interleaved Data Depth  
Type 32 System  
Boot Information  
22  
Boot status  
00  
101  
KP915GV Product Manual  
Item  
SMBIOS Data  
Expected Result  
Type 127: End-of-  
Table  
23  
4.17  
Post Code Technical Description  
POST Code  
Description  
CFh  
Test CMOS R/W functionality.  
Early chipset initialization:  
-Disable shadow RAM  
C0h  
-Disable L2 cache (socket 7 or below)  
-Program basic chipset registers  
Detect memory  
C1h  
-Auto-detection of DRAM size, type and ECC.  
-Auto-detection of L2 cache (socket 7 or below)  
C3h  
C5h  
01h  
03h  
Expand compressed BIOS code to DRAM  
Call chipset hook to copy BIOS back to E000 & F000 shadow RAM.  
Expand the Xgroup codes locating in physical address 1000:0  
Initial Superio_Early_Init switch.  
1. Blank out screen  
2. Clear CMOS error flag  
05h  
07h  
08h  
1. Clear 8042 interface  
2. Initialize 8042 self-test  
Enable keyboard interface.  
Auto detect ports for keyboard & mouse followed by a port & interface swap  
(optional).  
0Ah  
Test F000h segment shadow to see whether it is R/W-able or not. If test fails,  
keep beeping the speaker.  
0Eh  
10h  
12h  
Auto detect flash type to load appropriate flash R/W codes into the run time  
area in F000 for ESCD & DMI support.  
Use walking 1’s algorithm to check out interface in CMOS circuitry. Also set  
real-time clock power status, and then check for override.  
14h  
16h  
18h  
Program chipset default values into chipset.  
Initial Early_Init_Onboard_Generator switch.  
Detect CPU information including brand, SMI type and CPU level.  
Initial interrupts vector table. If no special specified, all H/W interrupts are  
directed to SPURIOUS_INT_HDLR & S/W interrupts to  
SPURIOUS_soft_HDLR.  
1Bh  
1Dh  
1Fh  
21h  
Initial EARLY_PM_INIT switch.  
Load keyboard matrix (notebook platform)  
HPM initialization (notebook platform)  
102  
KP915GV Product Manual  
POST Code  
Description  
Check validity of RTC value: e.g. a value of 5Ah is an invalid value for RTC  
minute.  
Load CMOS settings into BIOS stack. If CMOS checksum fails, use default  
value instead.  
Prepare BIOS resource map for PCI & PnP use. If ESCD is valid, take into  
consideration of the ESCD’s legacy information.  
Onboard clock generator initialization.  
23h  
Disable respective clock resource to empty PCI & DIMM slots.  
Early PCI initialization:  
-Enumerate PCI bus number  
-Assign memory & I/O resource  
-Search for a valid VGA device & VGA BIOS, and put it into C000:0.  
27h  
29h  
Initialize INT 09 buffer  
Program CPU internal MTRR (P6 & PII) for 0-640K memory address. Initialize  
the APIC for Pentium class CPU. Program early chipset according to CMOS  
setup. Example: onboard IDE controller. Measure CPU speed. Invoke video  
BIOS.  
Initialize multi-language Put information on screen display, including Award  
title, CPU type, CPU speed  
2Dh  
3Ch  
3Eh  
40h  
43h  
47h  
Test 8254  
Test 8259 interrupt mask bits for channel 1.  
Test 8259 interrupt mask bits for channel 2.  
Test 8259 functionality.  
Initialize EISA slot  
Calculate total memory by testing the last double word of each 64K page.  
Program writes allocation for AMD K5 CPU.  
49h  
Program MTRR of M1 CPU Initialize L2 cache for P6 class CPU & program  
CPU with proper cacheable range. Initialize the APIC for P6 class CPU. On MP  
platform, adjust the cacheable range to smaller one in case the cacheable  
ranges between each CPU are not identical.  
4Eh  
50h  
52h  
55h  
Initialize USB  
Test all memory (clear all extended memory to 0)  
Display number of processors (multi-processor platform)  
Display PnP logo Early ISA PnP initialization -Assign CSN to every ISA PnP  
device.  
Initialize the combined Trend Anti-Virus code.  
(Optional Feature) Show message for entering AWDFLASH.EXE from FDD  
(optional)  
57h  
59h  
5Bh  
Initialize Init_Onboard_Super_IO switch.  
Initialize Init_Onboard_AUDIO switch.  
5Dh  
60h  
Okay to enter Setup utility; i.e. not until this POST stage can users enter the  
CMOS setup utility.  
65h  
67h  
69h  
Initialize PS/2 Mouse  
Prepare memory size information for function call: INT 15h ax=E820h  
Turn on L2 cache  
Program chipset registers according to items described in Setup & Auto-  
configuration table.  
6Bh  
6Dh  
6Fh  
Assign resources to all ISA PnP devices.  
Initialize floppy controller  
103  
KP915GV Product Manual  
POST Code  
Description  
Detect & install all IDE devices: HDD, LS120, ZIP, CDROM…  
Detect serial ports & parallel ports.  
75h  
77h  
7Ah  
Detect & install co-processor  
7Fh  
Switch back to text mode if full screen logo is supported.  
82h  
Call chipset power management hook. If password is set, ask for password.  
83h  
84h  
Save all data in stack back to CMOS  
Initialize ISA PnP boot devices  
85h  
93h  
USB final Initialization.  
Read HDD boot sector information for Trend Anti-Virus code  
Enable L2 cache Program boot up speed Chipset final initialization. Power  
management final initialization Clear screen & display summary table.  
94h  
95h  
96h  
FFh  
Program daylight saving Update keyboard LED & typematic rate  
Build MP table Build & update ESCD Set CMOS century to 20h or 19h Load  
CMOS time into DOS timer tick Build MSIRQ routing table.  
Boot attempt (INT 19h)  
4.18  
4.19  
POST Beep  
•
A single long beep followed by two short beeps. It indicates that a video error has occurred  
and the BIOS cannot initialize the video screen to display any additional information.  
•
A single long beep repeatedly. This indicates that a DRAM error has occurred.  
SMBus Device Configuration  
Device Name  
Address  
Description  
Channel A DIMM1  
Channel A DIMM2  
Channel B DIMM1  
Channel B DIMM2  
ICS 954101AFT  
NS LM96000  
A0  
DDR2 Memory  
DDR2 Memory  
DDR2 Memory  
DDR2 Memory  
CK410E  
A8  
A4  
AC  
D2 & D3  
5C  
Hardware Monitor  
104  
KP915GV Product Manual  
5
Customer Support  
RadiSys Online Support can be found at www.radisys.com and includes device drivers, BIOS  
updates, support software and documentation. See the Manuals, Drivers & BIOS section.  
The next table displays online specifications and reference material:  
Table 7. References  
Specification  
Description  
Location  
www.acpi.info  
ACPI  
Advanced Configuration and  
Power Interface specification  
www.agpforum.org  
AGP  
Advanced Graphics Port Interface  
Specification  
www.microsoft.com/hwdev/archive/B  
USBIOS/amp_12.asp  
APM  
Advanced Power Management  
specification  
http://developer.intel.com/design/chip  
sets/915g/index.htm  
Intel 915G Chipset  
Intel 915G chipset datasheet  
http://developer.intel.com/design/chip  
sets/915gv/index.htm  
Intel 915GV Chipset Intel 915GV chipset datasheet  
http://developer.intel.com/design/cele  
ron  
Intel Celeron  
processor  
Intel Celeron processor datasheet  
http://developer.intel.com/design/pent  
ium4  
Intel Pentium 4  
processor  
Intel Pentium 4 processor  
datasheet  
www.formfactors.org  
www.pcisig.com  
ATX, microATX  
PCI  
Form factor specifications  
PCI local bus specification  
Memory module specifications  
http://developer.intel.com/technology/  
memory/  
DDR SDRAM  
DIMMs  
http://www.jedec.org/  
www.smbus.org  
SMBus  
USB  
System management bus  
www.usb.org/developers  
www.vesa.org  
Universal Serial Bus specification  
VESA  
Video Electronics Standards  
Association  
105  
KP915GV Product Manual  
A
Technical Reference  
A.1  
I/O Map  
Table 8. I/O Map  
Description  
Address (hex)*  
0000 – 000F  
0020 – 0021  
002E – 002F  
0040 – 0043  
0060 – 0064  
0062, 0066  
DMA controller 1  
Interrupt controller 1  
SIO control registers  
Timer counter  
Keyboard and mouse controller  
Motherboard control registers  
RTC and CMOS RAM  
0070 – 0071  
0080 – 008F  
0092  
DMA controller page registers (for channels 1 and 2)  
PC compatible Port 92 (fast A20 and PIC)  
Interrupt controller 2  
00A0 – 00A1  
00B2 – 00B3  
00C0 – 00DF  
00F0  
Advanced power management (APM) control registers  
DMA controller 2  
Floating point error control  
Secondary IDE controller  
Primary IDE controller  
0170 – 0177  
01F0 – 01F7  
0278 –027F  
02E8 – 02EF  
02F8 – 02FF  
0374 – 0376  
0378 –037F  
x3B0 – x3BB  
x3C0 – x3CF  
x3D4 – x3DA  
03F0 – 03F5  
03F6 – 03F7  
03E8 – 03EF  
03F8 – 03FF  
04D0 – 04D1  
0678 – 067A  
0778 – 077A  
0CF8 – 0CFF  
1000 – 105F  
1060 – 107F  
1200 – 12FF  
Parallel port, LPT2  
COM4 serial port  
COM2 serial port  
Secondary IDE controller  
Parallel port, LPT1  
VGA controller  
EGA controller registers  
CGA controller registers  
Flexible diskette controller  
Primary IDE controller  
COM3 serial port  
COM1 serial port  
Interrupt controller  
ECP registers for parallel port LPT2  
ECP registers for parallel port LPT1  
PCI configuration address and data registers  
ACPI registers  
TCO controller  
AC97 audio mixer  
106  
KP915GV Product Manual  
Table 8. I/O Map  
Description  
Address (hex)*  
1300 – 133F  
AC97 audio master  
1800 – 182F  
SIO GPIO and control logic  
FFA0 – FFA7  
Primary IDE bus master registers  
FFA8 – FFAF  
Secondary IDE bus master registers  
Dynamically assigned  
Dynamically assigned  
Dynamically assigned  
USB controller (four) (32 locations on 32-byte boundary)  
SMBus controller (16 locations on 16-byte boundary)  
LAN controllers (two) (4096 locations on a 4096-byte boundary)  
* An ‘x’ prefix for the address indicates that only the low-order 10 address bits are decoded.  
A.2  
PCI Interrupt Allocation  
In order to share PCI interrupts efficiently, the routing of the PCI interrupts INTA - INTD to the  
motherboard PCI interrupts PIRQE – PIRQH are rotated for each slot. Thus the PCI card INTA  
signals for the PCI slots are spread across these four motherboard inputs. Interrupt routing for the  
riser slots is determined by the riser design.  
Table 9. PCI Interrupt Allocation  
Device  
PIRQA PIRQB PIRQC PIRQD PIRQE PIRQF PIRQG PIRQH  
Slot 1 (AGP4X)  
INTA  
INTB  
–
–
–
–
–
–
Slot 2 (PCI 2.2)  
–
–
–
–
INTA  
INTB  
INTC  
INTD  
Slot 3 (PCI 2.2)  
–
–
–
–
INTD  
INTA  
INTB  
INTC  
Slot 4 (PCI 2.2)  
–
–
–
–
INTC  
INTD  
INTA  
INTB  
VGA controller  
INTA  
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Ethernet controller 1  
Ethernet controller 2  
USB UHCI controller 1  
USB UHCI controller 2  
USB UHCI controller 3  
USB EHCI controller  
SMBus controller  
AC97 controller  
INTA  
–
–
–
–
–
INTA  
–
–
–
INTA  
–
–
–
–
–
–
–
–
–
–
–
INTB  
–
–
INTC  
–
–
–
–
–
–
–
–
–
INTD  
INTB  
INTB  
–
–
Example. From the previous table, the INTA interrupt from a card plugged into slot 2 would be  
routed to the motherboard PIRQE.  
107  
KP915GV Product Manual  
A.3  
PCI Device Assignments  
Table 10. PCI Device Assignments  
Bus  
Device  
Device  
Number  
Function  
Number  
IDSEL  
Number  
Chipset host bridge and memory  
controller  
–
0
0
0
AGP bridge  
–
–
–
–
0
0
0
0
1
0
0
0
0
Graphics controller  
PCI bridge  
2
30  
31  
LPC bridge  
(Includes DMA, timers, PIC, APIC, RTC,  
power & system management, GPIO)  
IDE controller  
–
0
0
0
0
0
0
0
2
2
2
2
2
2
2
2
31  
31  
31  
29  
29  
29  
29  
0
1
3
5
0
1
2
7
–
–
–
–
–
–
0
0
SMBus controller  
–
AC97 audio controller  
USB UHCI controller 1  
USB UHCI controller 2  
USB UHCI controller 3  
USB EHCI controller  
Slot 1 (AGP4X)  
–
–
–
–
–
AD16  
AD17  
AD18  
AD19  
AD20  
AD21  
AD23  
AD24  
Slot 2 (PCI 2.2)  
1
Slot 3 (PCI 2.2)  
2
Slot 4 (PCI 2.2)  
3
Slot 5 (PCI 2.2, via riser only)  
Slot 6 (PCI 2.2, via riser only)  
Ethernet controller 1  
Ethernet controller 2  
4
5
7
8
The PCI slots and the Ethernet controller are behind a virtual bridge to PCI bus 2 implemented by  
the chipset ICH4. An AGP card, when present, resides on PCI bus 1.  
A.4  
SMBus Resource Allocation  
Table 11. SMBus Resource Allocation  
Address  
Description  
0101 110X  
1010 000X  
1010 001X  
1101 001X  
System management controller (LM85)  
Memory module 1  
Memory module 2  
Clock synthesizer  
108  
KP915GV Product Manual  
A.5  
ISA Interrupt Allocation  
While the motherboard does not include an ISA bus, it includes an ISA-compatible interrupt  
controller (PIC) in order to be compatible with AT standard architecture. The interrupts are  
allocated as described in the next table.  
Table 12. ISA Interrupt Allocation  
Interrupt  
IRQ0  
Description  
System Timer  
IRQ1  
Keyboard Controller  
IRQ2  
Cascade interrupt  
IRQ3  
COM2, COM1 or unassigned  
COM1, COM2 or unassigned  
Parallel port or unassigned  
Floppy  
IRQ4  
IRQ5  
IRQ6  
IRQ7  
Printer port or unassigned  
Real time clock/CMOS RAM  
ACPI SCI (when configured for ACPI operating system)  
Unassigned  
IRQ8  
IRQ9  
IRQ10  
IRQ11  
IRQ12  
IRQ13  
IRQ14  
IRQ15  
NMI  
Unassigned  
PS/2 mouse or unassigned  
Floating point unit  
Primary IDE or unassigned  
Secondary IDE or unassigned  
PCI PERR and SERR signals  
A.6  
ISA DMA Channel Allocation  
While the motherboard does not support an ISA bus, it includes an ISA-compatible DMA controller  
in order to be compatible with AT standard architecture. The DMA channels are allocated as  
described in the next table.  
Table 13. ISA DMA Channel Allocation  
DMA Channel  
Channel 0  
Channel 1  
Channel 2  
Channel 3  
Channel 4  
Channel 5  
Channel 6  
Channel 7  
Description  
Unassigned 8-bit channel  
Unassigned 8-bit channel  
Floppy controller or unassigned 8-bit channel  
ECP parallel port or unassigned 8-bit channel  
Cascade channel  
Unassigned 16-bit channel  
Unassigned 16-bit channel  
Unassigned 16-bit channel  
109  
KP915GV Product Manual  
A.7  
BIOS Organization  
The BIOS ROM is a 4or 8Mbit device containing eight or sixteen symmetrical 64KB blocks. The next  
figure shows how the ROM stores code and control information. The addresses shown refer to the  
ROM image at the top of the 4GB-address space. Note that the system BIOS segment is  
compressed in this image. When the BIOS runs, the code is uncompressed in real-time and the  
resulting code and data image is found at physical address 0E0000h through 0FFFFFh.  
Figure 11. BIOS ROM Addresses  
110  
KP915GV Product Manual  
B
Control Registers  
Notes  
•
The following abbreviations are used in register descriptions:  
R=Read RO=Read only R/W=Read/Write W=Write only  
The MSB (Most Significant Bit) is listed first.  
•
B.1  
Index Register  
7
6
5
4
3
2
1
0
Version  
Index  
RO  
RO  
RO  
RO  
R/W  
R/W  
R/W  
R/W  
I/O location:  
Default:  
062h  
vvvv1010b  
Version  
0001  
0010  
Index  
0000  
0000  
0000  
0001  
0010  
0011  
1000  
1001  
1010  
1011  
A read-only field containing the software version number for the logic.  
Version 1  
Version 2  
Value description.  
Watchdog Control  
Watchdog Kick  
Watchdog Status  
Watchdog Timeout Period  
General Purpose I/O Port 1  
General Purpose I/O Port 2 and Control  
PWM Control  
Part Number, low digits  
Processor Identification  
Part Number, high digits  
B.2  
Watchdog Control  
7
6
5
4
3
RES  
W
2
1
WEN  
W
0
0
Prescale  
SMI  
W
W
W
W
W
W
I/O location:  
Index:  
066h  
0
Default:  
00000000b  
111  
KP915GV Product Manual  
Prescale  
4-bit value to set the watchdog counter period  
16..1s period (a value of 1010b gives a period of 6 seconds)  
Description  
0..15  
1
RES  
Reset after second timeout:  
No reset  
0
1
Force system reset after second watchdog timeout  
Generate SMI after first timeout:8  
No SMI  
SMI  
0
1
Generate SMI after first watchdog timeout  
Watchdog enable:  
WEN  
0
1
Disable watchdog timer  
Enable and start watchdog timer  
8 Use of this feature normally requires a custom BIOS – contact RadiSys for more information. The  
standard BIOS does not route the SMI and thus ignores the event – causing a system reset after  
the second timeout unless the timer is restarted.  
B.3  
Watchdog Kick  
7
6
5
4
Don’t care  
W
3
2
1
0
1
W
W
W
W
W
W
W
I/O location:  
Index  
066h  
0
Default:  
00000000b  
B.4  
Watchdog Status  
7
6
5
4
3
2
1
0
0
Prescale  
TO2  
RO  
TO1  
RO  
WEN  
RO  
RO  
RO  
RO  
RO  
RO  
I/O location:  
Index:  
066h  
0
Default:  
N/A  
Prescale  
TOC1  
4-bit value to set counter period (copy of data written)  
First timeout:  
0
First timeout has not occurred  
Timer has expired at least once  
1
TOC2  
Second timeout:  
0
Second timeout has not occurred  
Timer has expired at least once  
1
WEN  
0
Timer enable:  
Timer is disabled  
112  
KP915GV Product Manual  
1
Timer is enabled and counting  
B.5  
Watchdog Timeout Period  
7
6
5
4
3
2
1
0
Watchdog timeout period  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
I/O location:  
Index  
066h  
1
Default:  
11111111b  
Timeout period  
0
Do not use (causes immediate timeout)  
Timeout period in units of 1 x prescale value seconds  
1–255  
B.6  
General Purpose I/O Port 1  
7
6
5
4
3
2
1
0
PI7  
R/W  
PI6  
R/W  
PI5  
R/W  
PI4  
R/W  
PI3  
R/W  
PI2  
R/W  
PI1  
R/W  
PI0  
R/W  
I/O location:  
Index:  
066h  
2
Default:  
00000000b  
P17–P10, GPIO Port 1 data:  
When programmed as an output, the GPIO port 1 bit follows the value written into this register and  
reads reflect the value written.  
When programmed as inputs, writes are ignored and a read follows the state of the GPIO port 1  
signal. Direction control is via the GPIO port 2 and control register.  
B.7  
General Purpose I/O Port 2 and Control  
7
6
5
4
3
2
1
0
D201  
R/W  
D157  
R/W  
D104  
P24  
R/W  
P23  
R/W  
P22  
R/W  
P21  
R/W  
P20  
R/W  
R/W 9  
9 Controller versions up to and including 2 do not support reading this bit  
I/O location:  
Index:  
066h  
3
Default:  
00000000b  
P21 – P20, GPIO Port 2 data:  
When programmed as an output, the GPIO port 2 bit follows the value written into this register and  
reads reflect the value written. When programmed as inputs, writes are ignored and a read follows  
the state of the GPIO port 2 signal. Direction control is via the D201 control.  
P22, GPIO Port 2 data:  
This bit is output only. GPIO port 2 bit 2 follows the value written into this register and reads reflect  
the value written.  
P24 - P23, GPIO Port 2 data:  
113  
KP915GV Product Manual  
These bits are input only. Writes to these bits have no effect; reads reflect the state of the GPIO  
port 2 bits 4 and 3 respectively.  
D104, GPIO Port 1 bits 0 – 4 direction control:  
GPIO bits 10 – 14 are inputs  
GPIO bits 10 – 14 are outputs  
D157, GPIO Port 1 bits 5 – 7 direction control:  
GPIO bits 15 – 17 are inputs  
GPIO bits 15 – 17 are outputs  
D201, GPIO Port 2 bits 0 – 1 direction control:  
GPIO bits 20 – 21 are inputs  
GPIO bits 20 – 21 are outputs  
B.8  
PWM Control  
7
6
5
4
3
2
1
0
Reserved  
R/W  
PWM control  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
I/O location:  
Index:  
066h  
8
Default:  
00000000b  
PWM Control  
Determines the pulse width of the PWM output.  
B.9  
Processor Identification  
7
6
5
4
3
2
1
0
CPU mode  
P4M  
RO  
Voltage ID, VID4–VID0  
RO  
RO  
RO  
RO  
RO  
RO  
RO  
I/O location:  
Index:  
066h  
10  
Default:  
N/A  
CPU Mode  
Returns the state of the processor type selection jumper:  
Pentium 4 or Celeron  
01  
10  
11  
P4M  
0
Pentium 4-M  
Auto select  
Pentium 4-M detected:  
Pentium 4-M  
1
Pentium 4 or Celeron  
VID  
Processor voltage ID (selected by processor):  
Returns the voltage identification value presented by the processor.  
114  
KP915GV Product Manual  
B.10  
Controller Part Number  
The controller part number format is 97-xxyy-0v where v is version number (top 4 bits of index  
register), xx is the byte 2 value and yy is the byte 1 value. BCD encoding is used for all digits.  
Byte 1 is 36h  
Byte 2 is 42h.  
The programmed part number is 97-4236-0v for production motherboards.  
Controller Part Number, low digits  
7
6
5
4
3
2
1
0
Part number, byte 1  
RO  
RO  
RO  
RO  
RO  
RO  
RO  
RO  
I/O location:  
Index:  
066h  
9
Default:  
N/A  
Controller Part Number, high digits  
7
6
5
4
3
2
1
0
Part number, byte 2  
RO  
RO  
RO  
RO  
RO  
RO  
RO  
RO  
I/O location:  
Index:  
066h  
11  
Default:  
N/A  
115  
KP915GV Product Manual  
C
Connector Descriptions  
Note 1: Connector views in the following sections are shown from the motherboard side.  
Note 2: In all tables below the # sign indicates “active low.”  
C.1  
Connector Part Numbers  
The various motherboard connectors are listed in the next table along with the part number of one  
of the approved vendors. The list is intended to assist in the selection of mating connectors.  
Table 14. Connector part numbers  
Connector  
I/O panel dual USB  
Part Number  
Foxconn UB1112C-8MD1  
Type  
Dual vertically stacked USB  
RJ45 with LEDs and  
transformer over dual USB,  
10/100  
RJ45 with LEDs and  
transformer over dual USB,  
Gbit  
I/O panel 10/100 RJ45 over  
dual USB  
Foxconn FM25U1B-21U5  
Foxconn FM38U1B-21U5  
I/O panel Gbit RJ45 over  
dual USB  
I/O panel PS/2 keyboard  
and mouse  
I/O panel VGA monitor (D-  
SUB 3 IN 1)  
I/O panel Serial port (D-  
SUB 3 IN 1)  
I/O panel Parallel port (D-  
SUB 3 IN 1)  
I/O panel double stack  
audio jacks  
ATAPI CD-ROM Audio  
Line-In Header  
Keyboard and Mouse  
headers  
Foxconn MH11067-F7D2  
Foxconn DM11352-H5V3  
Foxconn DM11352-H5V3  
Foxconn DM11352-H5V3  
Foxconn JA2333L-HA6Q  
NIKETECH 271S04-A01A  
Foxconn HF5504E  
Stacked 6-way mini-DIN  
15-way high-density female D-  
sub  
9-way male D-sub  
25-way female D-sub  
Double vertically stacked  
3.5mm  
4-way header with latch, black  
4-pin 2mm headers  
ATAPI Audio Line-Out  
Header  
ATX12V Power Connector  
ATAPI Audio Microphone-In  
Header  
Processor Fan, System  
FAN1 and FAN2 Header  
Processor Socket  
SMBUS Header  
4-way header with latch,  
yellow  
2 by 2-way ATX power header  
NIKETECH 271S04-A08A  
Foxconn HM3502E-P1  
NIKETECH 271S04-A07A  
4-way header with latch, white  
4-way with locking ramp  
Foxconn HF0804E-M2  
Foxconn PE077527-1041  
Foxconn HF5504E  
775-pin FC-LGA4  
4-pin 2mm header  
1 Lane differential pairs  
signaling  
3.5V/5V signaling  
8 Lane differential pairs  
signaling  
x1 PCI-E Slot  
PCI Slot  
Foxconn 2EG0181V-D2D  
Foxconn EH0600V-DAW  
Foxconn 2EG0821V-D2G  
ADD2 Slot (Green)  
5-pin locking ATAPI-style,  
black  
USB Port 5,6,7,8 headers  
NIKETECH 271S05-A01A  
Foxconn HF5502E-N  
Remote Thermal Sensor  
Header  
2-pin 2mm header  
Lithium cell holder  
DIMM Sockets  
DIMM Sockets  
LOTES KB6666BP5L  
Foxconn AT2400V-H3B  
Foxconn AT2400V-H3W  
Top loading, CR2032  
240-pin, 1.8V DDR2 SDRAM  
240-pin, 1.8V DDR2 SDRAM  
116  
KP915GV Product Manual  
Table 14. Connector part numbers  
Part Number  
Connector  
Type  
Front Panel Header  
RS232 Serial Port2 Header  
SATA Port 1 and Port 2  
Header  
Foxconn HC11101-L6  
Foxconn HL20051-D1  
2 by 10-way header  
2 by 5-way shrouded header  
Foxconn LD1807V-S51B  
Foxconn HL20101-P0  
Foxconn HM3510E-P1  
2 differential pairs signaling  
TPM Header  
2 by 10-way header  
2 by 10/12-way ATX power  
header  
ATX Power Connector  
GPIO Header  
Diskette Connector  
Primary IDE Connector  
Foxconn HL20101-L7  
Foxconn HL20171-P4  
Foxconn HL20201-UD2  
2 by 10-way shrouded header  
34-pin shrouded header  
40-pin shrouded header  
C.2  
PCI-E Expansion Slot (ADD2 card mode)  
The PCI-E/ADD2 slot only supports 1.5V signaling.  
Table 15. ADD2 Expansion Slot  
Signal Pin Signal  
Not Used  
A34 VDDQ1.5  
Pin  
A1  
A2  
A3  
A4  
Signal  
+12V  
Pin  
B1  
B2  
B3  
B4  
Pin  
Signal  
B34 VDDQ1.5  
B35 DVOCD2  
B36 DVOCD0  
B37 GND  
Not Used  
Not Used  
Not Used  
+5V  
A35 DVOCD3  
A36 DVOCD1  
A37 GND  
+5V  
Not Used  
DVOCBLANK  
#
A5  
GND  
B5  
GND  
A38  
B38 DVOCHSYNC  
A6  
A7  
A8  
A9  
Not Used  
Not Used  
Not Used  
+3.3V  
B6  
B7  
B8  
B9  
Not Used  
Not Used  
Not Used  
+3.3V  
A39 DVOCVSYNC B39 Not Used  
A40 VDDQ1.5  
A41 MDVIDATA  
A42 KEY  
B40 VDDQ1.5  
B41 MI2CCLK  
B42 KEY  
A10 Not Used  
A11 Not Used  
A12 Not Used  
A13 GND  
B10 Not Used  
B11 Not Used  
B12 Not Used  
B13 GND  
A43 KEY  
B43 KEY  
A44 KEY  
B44 KEY  
A45 KEY  
B45 KEY  
A46 MDVICLK  
A47 MDDCDATA  
A48 Not Used  
A49 GND  
B46 MI2CDATA  
B47 VDDQ1.5  
B48 Not Used  
B49 GND  
A14 Not Used  
A15 ADDID1  
A16 +3.3V  
B14 Not Used  
B15 ADDID0  
B16 +3.3V  
A17 ADDID3  
A18 Not Used  
A19 GND  
B17 ADDID2  
B18 Not Used  
B19 GND  
A50 ADDDETECT#  
A51 MDDCCLK  
A52 VDDQ1.5  
B50 Not Used  
B51 DVOBBLANK#  
B52 VDDQ1.5  
A20 ADDID5  
A21 ADDID7  
A22 Not Used  
A23 GND  
B20 ADDID4  
B21 ADDID6  
B22 Not Used  
B23 GND  
A53 DVOBCLKINT# B53 DVOBFLDSTL  
A54 DVOBD11  
A55 GND  
B54 DVOBD10  
B55 GND  
A56 DVOBD9  
A57 DVOBD7  
A58 VDDQ1.5  
A59 DVOBCLK#  
B56 DVOBD8  
B57 DVOBD6  
B58 VDDQ1.5  
B59 DVOBCLK  
A24 Not Used  
A25 +3.3V  
B24 +3.3VAUX  
B25 +3.3V  
A26 DVOBCINTR#  
B26 DVOCFLDSTL  
117  
KP915GV Product Manual  
Table 15. ADD2 Expansion Slot  
Signal Pin Signal  
Pin  
Signal  
Pin  
Pin  
Signal  
A27 DVOCD11  
A28 +3.3V  
B27 DVOCD10  
B28 +3.3V  
A60 DVOBD5  
A61 GND  
B60 DVOBD4  
B61 GND  
A29 DVOCD9  
A30 DVOCD7  
A31 GND  
B29 DVOCD8  
B30 DVOCD6  
B31 GND  
A62 DVOBD3  
A63 DVOBD1  
A64 VDDQ1.5  
B62 DVOBD2  
B63 DVOBD0  
B64 VDDQ1.5  
A32 DVOCCLK#  
A33 DVOCD5  
B32 DVOCCLK  
B33 DVOCD4  
A65 DVOBHSYNC B65 DVOBVSYNC  
A66 VREFGC  
B66 VREFGC  
C.3  
PCI Expansion Slot12  
Table 16. PCI Expansion Slot  
Pin  
A1  
Signal  
TRST#13  
+12V  
Pin  
B1  
Signal  
Pin  
A32  
A33  
A34  
A35  
A36  
A37  
A38  
A39  
A40  
A41  
A42  
A43  
A44  
A45  
A46  
A47  
A48  
A49  
A50  
A51  
A52  
A53  
A54  
A55  
A56  
A57  
A58  
A59  
A60  
A61  
A62  
Signal  
AD16  
Pin  
B32  
B33  
B34  
B35  
B36  
B37  
B38  
B39  
B40  
B41  
B42  
B43  
B44  
B45  
B46  
B47  
B48  
B49  
B50  
B51  
B52  
B53  
B54  
B55  
B56  
B57  
B58  
B59  
B60  
B61  
B62  
Signal  
-12V  
AD17  
C/BE2#  
GND  
A2  
B2  
TCK13  
GND  
+3.3V  
FRAME#  
GND  
A3  
TMS14  
TDI14  
B3  
A4  
B4  
TDO15  
+5V  
IRDY#  
+3.3V  
DEVSEL#  
GND  
A5  
+5V  
B5  
TRDY#  
GND  
A6  
INTA#  
INTC#  
+5V  
CLKRUN#15  
+5V  
B6  
+5V  
A7  
B7  
INTB#  
INTD#  
PRSNT1#  
Reserved  
PRSNT2#  
GND  
STOP#  
+3.3V  
Not Used  
Not Used  
GND  
A8  
B8  
LOCK#  
PERR#  
+3.3V  
SERR#  
+3.3V  
C/BE1#  
AD14  
GND  
A9  
B9  
A10  
A11  
A12  
A13  
A14  
A15  
A16  
A17  
A18  
A19  
A20  
A21  
A22  
A23  
A24  
A25  
A26  
A27  
A28  
A29  
A30  
A31  
B10  
B11  
B12  
B13  
B14  
B15  
B16  
B17  
B18  
B19  
B20  
B21  
B22  
B23  
B24  
B25  
B26  
B27  
B28  
B29  
B30  
B31  
Reserved  
GND  
PAR  
GND  
GND  
AD15  
+3.3V  
AD13  
AD11  
GND  
+3.3V AUX  
RST#  
+5V  
Reserved  
GND  
CLK  
AD12  
AD10  
GND  
GNT#  
GND  
GND  
REQ#  
+5V  
AD9  
PME#  
AD30  
KEY  
KEY  
AD31  
AD29  
GND  
KEY  
KEY  
+3.3V  
AD28  
C/BE0#  
+3.3V  
AD6  
AD8  
AD7  
AD26  
AD27  
AD25  
+3.3V  
C/BE3#  
AD23  
GND  
+3.3V  
AD5  
GND  
AD4  
AD24  
GND  
AD3  
IDSEL  
+3.3V  
AD22  
AD2  
GND  
AD0  
AD1  
+5V  
+5V  
AD20  
AD21  
AD19  
+3.3V  
REQ64#  
+5V  
ACK64#  
+5V  
GND  
AD18  
+5V  
+5V  
12 For ATX riser extension and slot 3 & 4 pin-out deviations, see following sections.  
118  
KP915GV Product Manual  
13 Not used but pulled low  
14 Not used but pulled high to +5V  
15 Not connected  
C.4  
PCI Express x1 Slot  
Table 17. PCI Express x1 Slot (PCI-E x1)  
Pin  
A1  
Signal  
PRSNT1# 16  
12V  
Pin  
B1  
Signal  
12V  
Pin  
A10  
A11  
A12  
A13  
A14  
A15  
A16  
A17  
A18  
Signal  
3.3V  
Pin  
B10  
B11  
B12  
B13  
B14  
B15  
B16  
B17  
B18  
Signal  
3.3VAUX  
WAKE#  
RSVD 16  
GND  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
A9  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
B9  
12V  
PWRGD  
GND  
12V  
RSVD  
GND  
GND  
REFCLK+  
REFCLK-  
GND  
JTAG2 16  
JTAG3 16  
JTAG4 16  
JTAG5 16  
3.3V  
SMCLK  
SMDAT  
GND  
HSOP0  
HSON0  
GND  
PRSNT2# 16  
GND  
HSIP0  
HSIN0  
GND  
3.3V  
JTAG1 16  
16 Not connected  
Table 18. P/S2 Mouse and P/S2 Keyboard  
Pin SIGNAL  
1
2
3
4
5
6
Mouse DATA / Keyboard DATA  
NC  
GND  
VCC  
Mouse Clock / Keyboard Clock  
NC  
Table 19. Parallel Port  
Pin SIGNAL  
Pin  
14  
SIGNAL  
AUTO  
FEED#  
ERR#  
INIT#  
SLIN#  
GND  
1
STROBE#  
2
DATA0  
DATA1  
DATA2  
DATA3  
DATA4  
DATA5  
DATA6  
DATA7  
ACK#  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
3
4
5
6
GND  
7
GND  
8
GND  
9
GND  
10  
11  
12  
13  
GND  
BUSY  
GND  
PE  
GND  
SELECT  
119  
KP915GV Product Manual  
Table 20. Serial Port  
Pin SIGNAL  
Pin  
SIGNAL  
1
2
3
4
DCD  
SIN  
6
DSR  
RTS  
CTS  
RI  
7
8
9
SOUT  
DTR  
5
GND  
Table 21. VGA Port  
Pin  
SIGNAL  
RED  
Pin  
SIGNAL  
1
2
3
4
5
6
7
8
9
+5V  
GREEN  
BLUE  
NC  
10  
11  
12  
13  
14  
15  
GND  
NC  
SDA  
GND  
GND  
GND  
GND  
Horizontal Sync  
Vertical Sync  
SCL  
Table 22. 2 x Dual Stack USB Ports  
Pin  
SIGNAL  
VCC  
Pin  
SIGNAL  
1
2
3
4
5
6
7
8
VCC  
DATA0-  
DATA0+  
GND  
DATA1-  
DATA1+  
GND  
Table 23. LAN Jack  
For 10/100Mbps  
Pin SIGNAL  
Pin  
SIGNAL  
1
2
3
4
TxD+  
5
6
7
8
75R Terminator  
RxD-  
TxD-  
RxD+  
75R Terminator  
75R Terminator  
75R Terminator  
For 10/100/1000Mbps  
Pin SIGNAL  
Pin  
SIGNAL  
1
2
3
4
A+  
A-  
5
6
7
8
C-  
B-  
B+  
C+  
D+  
D-  
120  
KP915GV Product Manual  
Table 24. 3 x Audio Jack  
Pin  
SIGNAL  
Tip  
Left Audio  
Ring  
Right Audio  
GND  
Sleeve  
Remark  
L- Line (Line In, Line Out)  
Table 25. 1394 Header  
Pin  
SIGNAL  
Pin  
SIGNAL  
1
2
3
4
5
TA1+  
TA1-  
GND  
GND  
TB1+  
6
TB1-  
7
Power  
Power  
KEY  
8
9
10  
GND  
Table 26. Front Panel Header  
Pin  
SIGNAL  
Pin  
SIGNAL  
GREEN LED+  
and/or  
YELLOW LED-  
HDLED+  
(Anode)  
1
2
4
GREEN LED-  
and/or  
YELLOW LED+  
HDLED-  
(Cathode)  
3
PWRSW#  
(Reference to GND)  
5
7
9
GND  
6
RESET#  
(Reference to  
GND)  
+5V  
(Fused)  
8
GND  
+5V(fused, speaker  
power)  
10  
SPKR#  
(Speaker return)  
KEY (no pin fitted)  
11  
13  
Not Used  
12  
14  
GND  
GREEN LED+  
and/or  
YELLOW LED-  
(same as pin 2)  
SPKR#  
(Speaker return)  
15  
17  
19  
16  
18  
20  
TAMPER#  
(Reference to GND)  
Not Used  
GREEN LED-  
and/or  
YELLOW LED+  
(same as pin 4)  
GND  
121  
KP915GV Product Manual  
Table 27. General Purpose I/O Headers  
Pin  
1
SIGNAL  
GND  
Pin  
2
SIGNAL  
+5V (fused)  
GPIO20  
3
PWM  
4
5
GPIO21  
GPIO10  
GPIO12  
GPIO14  
GPIO16  
Reserved  
6
GPIO22  
7
8
GPIO11  
9
10  
12  
14  
16  
GPIO13  
11  
13  
15  
GPIO15  
GPIO17  
KEY (no pin fitted)  
17  
19  
GND  
GND  
18  
20  
GPI23  
GPI24  
Table 28. Power Supply Connector  
Pin  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
SIGNAL  
+3.3V  
Pin  
SIGNAL  
+3.3V  
+3.3V  
GND  
1
2
3
4
5
6
7
8
9
-12V  
GND  
PSON#  
GND  
+5V  
GND  
GND  
+5V  
GND  
GND  
Not Used  
+5V  
PWROK  
+5VSB  
+12V  
+5V  
10  
Table 29. Floppy Disk Connector  
Pin SIGNAL  
Pin  
SIGNAL  
DRVDEN0  
NC  
1
GND  
2
4
3
NC  
5
7
9
KEY (no pin)  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
6
8
NC  
INDEX#  
MOA#  
DSB#  
DSA#  
MOB#  
DIP#  
STEP#  
WD#  
WE#  
TRAK0#  
WP#  
RDATA#  
HEAD#  
DSKCHG  
10  
12  
14  
16  
18  
20  
22  
24  
26  
28  
30  
32  
34  
11  
13  
15  
17  
19  
21  
23  
25  
27  
29  
31  
33  
122  
KP915GV Product Manual  
Table 30. ATA/100 Hard Drive Disk Connector  
Pin  
1
SIGNAL  
HDRST#  
Pin  
2
SIGNAL  
GND  
3
5
7
9
11  
13  
15  
17  
19  
21  
23  
25  
Device data 7  
Device data 6  
Device data 5  
Device data 4  
Device data 3  
Device data 2  
Device data 1  
Device data 0  
GND  
4
6
8
Device data 8  
Device data 9  
Device data 10  
Device data 11  
Device data 12  
Device data 13  
Device data 14  
Device data 15  
KEY (no pin)  
GND  
10  
12  
14  
16  
18  
20  
22  
24  
26  
IDE REQ  
I/O WRITE  
I/O READ  
GND  
GND  
Pull down for  
always master  
GND  
NC  
NC  
Device address 2  
Device chip  
select S3  
27  
I/O RDY  
28  
29  
31  
33  
35  
IDE ACK  
IRQ14  
Device address 1  
Device address 0  
Device chip  
select S1  
30  
32  
34  
36  
37  
39  
38  
40  
HDDLED  
GND  
Table 31. SATA Disk Connector  
Pin  
SIGNAL  
1
2
3
GND  
A+ transmit  
A- transmit  
GND  
4
5
6
7
B-receive  
B+ receive  
GND  
Table 32. 3X Internal Audio Headers  
Pin  
SIGNAL  
1
LEFT  
GND  
2
3
4
GND  
RIGHT  
123  
KP915GV Product Manual  
Table 33.  
TPM Header  
SIGNAL  
Pin  
1
Pin  
SIGNAL  
GND  
LCLK  
2
4
6
8
3
LFRAME#  
LRESET#  
LAD3  
KEY PIN  
NC3  
5
7
LAD2  
9
VDD  
10  
12  
14  
16  
18  
20  
LAD1  
11  
13  
15  
17  
19  
LAD0  
GND  
NC1  
NC4  
NC2  
SERIRQ  
CLKRUNin  
NC5  
GND  
LPCPDn  
Table 34.  
Complex Programmable Logic Device (CPLD) JTAG Header  
Pin  
SIGNAL  
1
2
3
4
5
6
7
8
VCC_STBY  
CPLD_TDO  
CPLD_TDI  
NC  
KEY PIN  
CPLD_TMS  
GND  
CPLD_TCK  
Table 35.  
Serial Port 2 Header  
Pin  
SIGNAL  
DCD  
Pin  
SIGNAL  
DSR  
1
2
RxD  
3
5
4
6
RTS  
CTS  
TxD  
7
9
DTR  
GND  
8
RING  
KEY  
10  
Table 36. 4 X Internal USB Headers  
Pin  
SIGNAL  
1
2
3
4
5
+5V (fused)  
DATA-  
DATA+  
GND  
GND  
124  
KP915GV Product Manual  
Table 37. Remote Thermal Sensor  
Pin SIGNAL  
1
DIODE+  
DIODE-  
2
Table 38. 3 X Fan Connector  
Pin  
SIGNAL  
1
2
GND  
+12V  
3
4
TACHO  
PWM  
Table 39. SMBus Connector  
Pin  
SIGNAL  
1
2
3
4
+3.3V  
DATA  
CLOCK  
GND  
Table 40. PS/2 Keyboard Header  
Pin  
SIGNAL  
1
2
3
4
+5V (fused)  
DATA  
GND  
CLOCK  
Table 41. PS/2 Mouse Header  
Pin  
SIGNAL  
1
2
+5V (fused)  
DATA  
3
4
GND  
CLOCK  
125  

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