Cypress CY7C1411JV18 User Manual

CY7C1411JV18, CY7C1426JV18  
CY7C1413JV18, CY7C1415JV18  
36-Mbit QDR™-II SRAM 4-Word  
Burst Architecture  
Features  
Configurations  
Separate independent read and write data ports  
Supports concurrent transactions  
CY7C1411JV18 – 4M x 8  
CY7C1426JV18 – 4M x 9  
CY7C1413JV18 – 2M x 18  
CY7C1415JV18 – 1M x 36  
300 MHz clock for high bandwidth  
4-word burst for reducing address bus frequency  
DoubleDataRate(DDR)interfacesonbothreadandwriteports  
(data transferred at 600 MHz) at 300 MHz  
Functional Description  
The CY7C1411JV18, CY7C1426JV18, CY7C1413JV18, and  
CY7C1415JV18 are 1.8V Synchronous Pipelined SRAMs,  
equipped with QDR™-II architecture. QDR-II architecture  
consists of two separate ports to access the memory array. The  
read port has dedicated data outputs to support the read opera-  
tions and the write port has dedicated data inputs to support the  
write operations. QDR-II architecture has separate data inputs  
and data outputs to completely eliminate the need to “turn  
around” the data bus required with common IO devices. Access  
to each port is through a common address bus. Addresses for  
read and write addresses are latched on alternate rising edges  
of the input (K) clock. Accesses to the QDR-II read and write  
ports are completely independent of one another. To maximize  
data throughput, read and write ports are equipped with DDR  
interfaces. Each address location is associated with four 8-bit  
words (CY7C1411JV18), 9-bit words (CY7C1426JV18), 18-bit  
words (CY7C1413JV18), or 36-bit words (CY7C1415JV18) that  
burst sequentially into or out of the device. Because data can be  
transferred into and out of the device on every rising edge of both  
input clocks (K and K and C and C), memory bandwidth is  
maximized while simplifying system design by eliminating bus  
“turn arounds”.  
Two input clocks (K and K) for precise DDR timing  
SRAM uses rising edges only  
Two input clocks for output data (C and C) to minimize clock  
skew and flight time mismatches  
Echo clocks (CQ and CQ) simplify data capture in high speed  
systems  
Single multiplexed address input bus latches address inputs  
for both read and write ports  
Separate port selects for depth expansion  
Synchronous internally self-timed writes  
QDR-II operates with 1.5 cycle read latency when DLL is  
enabled  
Operates similar to a QDR-I device with 1 cycle read latency  
in DLL off mode  
Available in x 8, x 9, x 18, and x 36 configurations  
Full data coherency, providing most current data  
Core V = 1.8 (±0.1V); IO V  
= 1.4V to V  
DD  
DD  
DDQ  
Available in 165-ball FBGA package (15 x 17 x 1.4 mm)  
Offered in both Pb-free and non Pb-free packages  
Variable drive HSTL output buffers  
Depth expansion is accomplished with port selects, which  
enables each port to operate independently.  
All synchronous inputs pass through input registers controlled by  
the K or K input clocks. All data outputs pass through output  
registers controlled by the C or C (or K or K in a single clock  
domain) input clocks. Writes are conducted with on chip  
synchronous self-timed write circuitry.  
JTAG 1149.1 compatible test access port  
Delay Lock Loop (DLL) for accurate data placement  
Selection Guide  
300 MHz  
250 MHz  
250  
200 MHz  
200  
Unit  
MHz  
mA  
Maximum Operating Frequency  
Maximum Operating Current  
300  
965  
x8  
x9  
745  
620  
970  
760  
620  
x18  
x36  
1010  
1130  
790  
655  
870  
715  
Cypress Semiconductor Corporation  
Document Number: 001-12557 Rev. *C  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised June 25, 2008  
CY7C1411JV18, CY7C1426JV18  
CY7C1413JV18, CY7C1415JV18  
Logic Block Diagram (CY7C1413JV18)  
18  
D
[17:0]  
Write Write Write Write  
19  
Address  
Register  
A
Reg  
Reg  
Reg  
Reg  
(18:0)  
19  
Address  
Register  
A
(18:0)  
RPS  
K
Control  
Logic  
CLK  
Gen.  
K
C
C
DOFF  
Read Data Reg.  
CQ  
CQ  
72  
36  
V
REF  
18  
18  
18  
18  
Reg.  
Reg.  
Reg.  
Control  
Logic  
WPS  
BWS  
18  
36  
Q
[17:0]  
[1:0]  
Logic Block Diagram (CY7C1415JV18)  
36  
D
[35:0]  
Write Write Write Write  
18  
Address  
Register  
A
Reg  
Reg  
Reg  
Reg  
(17:0)  
18  
Address  
Register  
A
(17:0)  
RPS  
K
Control  
Logic  
CLK  
Gen.  
K
C
C
DOFF  
Read Data Reg.  
CQ  
CQ  
144  
72  
V
REF  
36  
36  
36  
36  
Reg.  
Reg.  
Reg.  
Control  
Logic  
WPS  
BWS  
36  
72  
Q
[35:0]  
[3:0]  
Document Number: 001-12557 Rev. *C  
Page 3 of 28  
CY7C1411JV18, CY7C1426JV18  
CY7C1413JV18, CY7C1415JV18  
Pin Configuration  
The pin configuration for CY7C1411JV18, CY7C1413JV18, and CY7C1415JV18 follows.  
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout  
CY7C1411JV18 (4M x 8)  
1
CQ  
NC  
NC  
NC  
NC  
NC  
NC  
DOFF  
NC  
NC  
NC  
NC  
NC  
NC  
TDO  
2
NC/72M  
NC  
3
4
WPS  
A
5
6
K
7
8
RPS  
A
9
10  
A
11  
CQ  
Q3  
D3  
NC  
Q2  
NC  
NC  
ZQ  
D1  
NC  
Q0  
D0  
NC  
NC  
TDI  
A
B
C
D
E
F
A
NWS  
NC/144M  
A
1
NC  
NC  
NC  
Q4  
NC  
Q5  
NC/288M  
A
K
NWS  
A
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
D2  
NC  
NC  
0
NC  
V
V
NC  
V
V
SS  
SS  
SS  
SS  
D4  
V
V
V
V
V
V
V
V
V
V
V
V
V
SS  
SS  
DD  
DD  
DD  
DD  
DD  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
DD  
DD  
DD  
DD  
DD  
NC  
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
NC  
V
V
V
V
V
V
V
V
V
V
G
H
J
D5  
V
V
V
V
REF  
REF  
DDQ  
DDQ  
NC  
NC  
Q6  
NC  
NC  
Q1  
K
L
NC  
D6  
NC  
NC  
Q7  
A
NC  
NC  
NC  
NC  
NC  
A
NC  
NC  
V
V
V
V
SS  
SS  
SS  
SS  
M
N
P
R
NC  
D7  
V
V
NC  
SS  
SS  
SS  
V
A
A
A
A
C
C
A
A
A
V
NC  
SS  
NC  
TCK  
A
A
A
A
NC  
TMS  
CY7C1426JV18 (4M x 9)  
1
CQ  
NC  
NC  
NC  
NC  
NC  
NC  
DOFF  
NC  
NC  
NC  
NC  
NC  
NC  
TDO  
2
NC/72M  
NC  
3
4
5
NC  
6
K
7
8
9
10  
A
11  
CQ  
Q4  
D4  
NC  
Q3  
NC  
NC  
ZQ  
D2  
NC  
Q1  
D1  
NC  
Q0  
TDI  
A
B
C
D
E
F
A
WPS  
A
NC/144M  
RPS  
A
A
NC  
NC  
NC  
Q5  
NC  
Q6  
NC/288M  
A
K
BWS  
A
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
D3  
NC  
NC  
0
NC  
V
V
NC  
V
V
SS  
SS  
SS  
SS  
D5  
V
V
V
V
V
V
V
V
V
V
V
V
V
SS  
SS  
DD  
DD  
DD  
DD  
DD  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
DD  
DD  
DD  
DD  
DD  
NC  
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
NC  
V
V
V
V
V
V
V
V
V
V
G
H
J
D6  
V
V
V
V
REF  
REF  
DDQ  
DDQ  
NC  
NC  
Q7  
NC  
NC  
Q2  
NC  
NC  
NC  
NC  
D0  
K
L
NC  
D7  
NC  
NC  
Q8  
A
NC  
NC  
NC  
NC  
NC  
A
V
V
SS  
SS  
SS  
SS  
M
N
P
R
NC  
D8  
V
V
V
V
SS  
SS  
SS  
V
A
A
A
A
C
C
A
A
A
V
SS  
NC  
TCK  
A
A
A
A
TMS  
Note  
1. NC/72M, NC/144M, and NC/288M are not connected to the die and can be tied to any voltage level.  
Document Number: 001-12557 Rev. *C  
Page 4 of 28  
 
CY7C1411JV18, CY7C1426JV18  
CY7C1413JV18, CY7C1415JV18  
Pin Configuration  
[1]  
The pin configuration for CY7C1411JV18, CY7C1413JV18, and CY7C1415JV18 follows.  
(continued)  
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout  
CY7C1413JV18 (2M x 18)  
1
CQ  
NC  
NC  
NC  
NC  
NC  
NC  
DOFF  
NC  
NC  
NC  
NC  
NC  
NC  
TDO  
2
NC/144M  
Q9  
3
4
WPS  
A
5
BWS  
NC  
A
6
K
7
8
RPS  
A
9
10  
NC/72M  
NC  
11  
CQ  
Q8  
D8  
D7  
Q6  
Q5  
D5  
ZQ  
D4  
Q3  
Q2  
D2  
D1  
Q0  
TDI  
A
B
C
D
E
F
A
NC/288M  
A
1
D9  
K
BWS  
A
NC  
NC  
NC  
NC  
NC  
NC  
0
NC  
D10  
Q10  
Q11  
D12  
Q13  
V
V
NC  
V
V
Q7  
SS  
SS  
SS  
SS  
D11  
V
V
V
V
V
V
V
V
V
V
V
V
V
NC  
SS  
SS  
DD  
DD  
DD  
DD  
DD  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
DD  
DD  
DD  
DD  
DD  
NC  
V
V
V
V
V
V
V
V
V
V
V
V
V
V
D6  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
Q12  
D13  
V
V
V
V
V
V
V
V
V
V
NC  
G
H
J
NC  
V
V
V
V
REF  
REF  
DDQ  
DDQ  
NC  
NC  
D14  
NC  
Q4  
D3  
K
L
Q14  
D15  
D16  
Q16  
Q17  
A
NC  
NC  
NC  
NC  
NC  
A
Q15  
NC  
V
V
V
V
NC  
Q1  
SS  
SS  
SS  
SS  
M
N
P
R
V
V
SS  
SS  
SS  
D17  
NC  
V
A
A
A
A
C
C
A
A
A
V
NC  
D0  
SS  
A
A
A
A
TCK  
TMS  
CY7C1415JV18 (1M x 36)  
1
2
3
4
5
BWS  
BWS  
A
6
K
7
BWS  
BWS  
A
8
9
10  
NC/144M  
Q17  
11  
CQ  
Q8  
D8  
D7  
Q6  
Q5  
D5  
ZQ  
D4  
Q3  
Q2  
D2  
D1  
Q0  
TDI  
A
B
C
D
E
F
CQ  
NC/288M NC/72M  
WPS  
A
RPS  
A
A
2
3
1
0
Q27  
D27  
D28  
Q29  
Q30  
D30  
DOFF  
D31  
Q32  
Q33  
D33  
D34  
Q35  
TDO  
Q18  
Q28  
D20  
D29  
Q21  
D22  
D18  
D19  
Q19  
Q20  
D21  
Q22  
K
D17  
D16  
Q16  
Q15  
D14  
Q13  
V
V
NC  
V
V
Q7  
SS  
SS  
SS  
SS  
V
V
V
V
V
V
V
V
V
V
V
V
V
D15  
SS  
SS  
DD  
DD  
DD  
DD  
DD  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
DD  
DD  
DD  
DD  
DD  
V
V
V
V
V
V
V
V
V
V
V
V
V
V
D6  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
V
V
V
V
V
V
V
V
V
V
Q14  
G
H
J
D13  
V
V
V
V
REF  
REF  
DDQ  
DDQ  
Q31  
D23  
D12  
Q4  
D3  
K
L
D32  
Q24  
Q34  
D26  
D35  
TCK  
Q23  
D24  
D25  
Q25  
Q26  
A
Q12  
D11  
D10  
Q10  
Q9  
V
V
Q11  
Q1  
SS  
SS  
SS  
SS  
M
N
P
R
V
V
V
V
SS  
SS  
SS  
V
A
A
A
A
C
C
A
A
A
V
D9  
SS  
A
A
A
A
D0  
A
TMS  
Document Number: 001-12557 Rev. *C  
Page 5 of 28  
CY7C1411JV18, CY7C1426JV18  
CY7C1413JV18, CY7C1415JV18  
Pin Definitions  
Pin Name  
IO  
Pin Description  
Data Input Signals. Sampled on the rising edge of K and K clocks when valid write operations are active.  
D
Input-  
[x:0]  
Synchronous CY7C1411JV18 D  
[7:0]  
CY7C1426JV18 D  
[8:0]  
CY7C1413JV18 D  
CY7C1415JV18 D  
[17:0]  
[35:0]  
WPS  
Input-  
Write Port Select Active LOW. Sampled on the rising edge of the K clock. When asserted active, a  
Synchronous write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D  
.
[x:0]  
NWS ,  
Input-  
Nibble Write Select 0, 1 Active LOW (CY7C1411JV18 Only). Sampled on the rising edge of the K  
. Used to select which nibble is written into the device  
during  
0
Synchronous and K clocks  
NWS ,  
when write operations are active  
NWS controls D  
1
and NWS controls D .  
the current portion of the write operations.  
All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write Select  
ignores the corresponding nibble of data and it is not written into the device  
0
[3:0]  
1
[7:4]  
.
BWS ,  
Input-  
Byte Write Select 0, 1, 2 and 3 Active LOW. Sampled on the rising edge of the K and K clocks when  
0
BWS ,  
Synchronous write operations are active. Used to select which byte is written into the device during the current portion  
of the write operations. Bytes not written remain unaltered.  
1
BWS ,  
2
BWS  
CY7C1426JV18 BWS controls D  
3
0
[8:0]  
[8:0]  
CY7C1413JV18 BWS controls D  
and BWS controls D  
[17:9].  
0
1
CY7C1415JV18 BWS controls D  
[35:27].  
, BWS controls D  
, BWS controls D  
and BWS controls  
0
[8:0]  
1
[17:9]  
2
[26:18]  
3
D
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select  
ignores the corresponding byte of data and it is not written into the device  
.
A
Input-  
Address Inputs. Sampled on the rising edge of the K clock during active read and write operations. These  
Synchronous address inputs are multiplexed for both read and write operations. Internally, the device is organized as  
4M x 8 (4 arrays each of 1M x 8) for CY7C1411JV18, 4M x 9 (4 arrays each of 1M x 9) for CY7C1426JV18,  
2M x 18 (4 arrays each of 512K x 18) for CY7C1413JV18 and 1M x 36 (4 arrays each of 256K x 36) for  
CY7C1415JV18. Therefore, only 20 address inputs are needed to access the entire memory array of  
CY7C1411JV18 and CY7C1426JV18, 19 address inputs for CY7C1413JV18 and 18 address inputs for  
CY7C1415JV18. These inputs are ignored when the appropriate port is deselected.  
Q
Outputs-  
Data Output Signals. These pins drive out the requested data when the read operation is active. Valid  
[x:0]  
Synchronous data is driven out on the rising edge of the C and C clocks during read operations or K and K, when in  
single clock mode. On deselecting the read port, Q  
are automatically tri-stated.  
[x:0]  
CY7C1411JV18 Q  
[7:0]  
CY7C1426JV18 Q  
[8:0]  
CY7C1413JV18 Q  
CY7C1415JV18 Q  
[17:0]  
[35:0]  
RPS  
C
Input-  
Read Port Select Active LOW. Sampled on the rising edge of positive input clock (K). When active, a  
Synchronous read operation is initiated. Deasserting deselects the read port. When deselected, the pending access is  
allowed to complete and the output drivers are automatically tri-stated following the next rising edge of  
the C clock. Each read access consists of a burst of four sequential transfers.  
Input Clock Positive Input Clock for Output Data. C is used in conjunction with C to clock out the read data from  
the device. C and C can be used together to deskew the flight times of various devices on the board back  
to the controller. See application example for further details.  
Input Clock Negative Input Clock for Output Data. C is used in conjunction with C to clock out the read data from  
the device. C and C can be used together to deskew the flight times of various devices on the board back  
to the controller. See application example for further details.  
C
K
K
Input Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device  
and to drive out data through Q  
when in single clock mode. All accesses are initiated on the rising  
[x:0]  
edge of K.  
Input Clock Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and  
to drive out data through Q when in single clock mode.  
[x:0]  
Document Number: 001-12557 Rev. *C  
Page 6 of 28  
CY7C1411JV18, CY7C1426JV18  
CY7C1413JV18, CY7C1415JV18  
Pin Definitions (continued)  
Pin Name  
IO  
Pin Description  
CQ  
Echo Clock CQ is Referenced With Respect to C. This is a free running clock and is synchronized to the input clock  
for output data (C) of the QDR-II. In the single clock mode, CQ is generated with respect to K. The timings  
for the echo clocks are shown in the AC timing table.  
CQ  
ZQ  
Echo Clock CQ is Referenced With Respect to C. This is a free running clock and is synchronized to the input clock  
for output data (C) of the QDR-II. In the single clock mode, CQ is generated with respect to K. The timings  
for the echo clocks are shown in the AC timing table.  
Input  
Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus  
impedance. CQ, CQ, and Q output impedance are set to 0.2 x RQ, where RQ is a resistor connected  
[x:0]  
between ZQ and ground. Alternatively, this pin can be connected directly to V  
, which enables the  
DDQ  
minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.  
DOFF  
Input  
DLL Turn Off Active LOW. Connecting this pin to ground turns off the DLL inside the device. The  
timings in the DLL turned off operation differs from those listed in this data sheet. For normal operation,  
this pin can be connected to a pull up through a 10 KΩ or less pull up resistor. The device behaves in  
QDR-I mode when the DLL is turned off. In this mode, the device can be operated at a frequency of up  
to 167 MHz with QDR-I timing.  
TDO  
Output  
Input  
Input  
Input  
N/A  
TDO for JTAG.  
TCK  
TCK Pin for JTAG.  
TDI  
TDI Pin for JTAG.  
TMS  
TMS Pin for JTAG.  
NC  
Not Connected to the Die. Can be tied to any voltage level.  
Not Connected to the Die. Can be tied to any voltage level.  
Not Connected to the Die. Can be tied to any voltage level.  
Not Connected to the Die. Can be tied to any voltage level.  
Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC  
NC/72M  
NC/144M  
NC/288M  
N/A  
N/A  
N/A  
V
Input-  
REF  
Reference measurement points.  
V
V
V
Power Supply Power Supply Inputs to the Core of the Device.  
DD  
Ground  
Ground for the Device.  
SS  
Power Supply Power Supply Inputs for the Outputs of the Device.  
DDQ  
Document Number: 001-12557 Rev. *C  
Page 7 of 28  
CY7C1411JV18, CY7C1426JV18  
CY7C1413JV18, CY7C1415JV18  
rising edge of the output clocks (C and C, or K and K when in  
single clock mode).  
Functional Overview  
The CY7C1411JV18, CY7C1426JV18, CY7C1413JV18, and  
CY7C1415JV18 are synchronous pipelined burst SRAMs with a  
read port and a write port. The read port is dedicated to read  
operations and the write port is dedicated to write operations.  
Data flows into the SRAM through the write port and flows out  
through the read port. These devices multiplex the address  
inputs to minimize the number of address pins required. By  
having separate read and write ports, the QDR-II completely  
eliminates the need to “turn around” the data bus and avoids any  
possible data contention, thereby simplifying system design.  
Each access consists of four 8-bit data transfers in the case of  
CY7C1411JV18, four 9-bit data transfers in the case of  
CY7C1426JV18, four 18-bit data transfers in the case of  
CY7C1413JV18, and four 36-bit transfers data in the case of  
CY7C1415JV18 in two clock cycles.  
When the read port is deselected, the CY7C1413JV18 first  
completes the pending read transactions. Synchronous internal  
circuitry automatically tri-states the outputs following the next  
rising edge of the positive output clock (C). This enables a  
transition between devices without the insertion of wait states in  
a depth expanded memory.  
Write Operations  
Write operations are initiated by asserting WPS active at the  
rising edge of the positive input clock (K). On the following K  
clock rise the data presented to D  
the lower 18-bit write data register, provided BWS  
is latched and stored into  
[17:0]  
are both  
[1:0]  
asserted active. On the subsequent rising edge of the negative  
input clock (K), the information presented to D is also stored  
[17:0]  
are both asserted  
into the write data register, provided BWS  
[1:0]  
This device operates with a read latency of one and half cycles  
when DOFF pin is tied HIGH. When DOFF pin is set LOW or  
active. This process continues for one more cycle until four 18-bit  
words (a total of 72 bits) of data are stored in the SRAM. The 72  
bits of data are then written into the memory array at the specified  
location. Therefore, write accesses to the device cannot be  
initiated on two consecutive K clock rises. The internal logic of  
the device ignores the second write request. Initiate write access  
on every other rising edge of the positive input clock (K). Doing  
so pipelines the data flow such that 18 bits of data transfers into  
the device on every rising edge of the input clocks (K and K).  
connected to V then device behaves in QDR-I mode with a  
SS  
read latency of one clock cycle.  
Accesses for both ports are initiated on the positive input clock  
(K). All synchronous input timing is referenced from the rising  
edge of the input clocks (K and K) and all output timing is refer-  
enced to the output clocks (C and C or K and K when in single  
clock mode).  
When deselected, the write port ignores all inputs after the  
pending write operations have been completed.  
All synchronous data inputs (D  
controlled by the input clocks (K and K). All synchronous data  
) pass through input registers  
[x:0]  
outputs (Q ) pass through output registers controlled by the  
rising edge of the output clocks (C and C or K and K when in  
single clock mode).  
[x:0]  
Byte Write Operations  
Byte write operations are supported by the CY7C1413JV18. A  
write operation is initiated as described in the Write Operations  
section. The bytes that are written are determined by BWS and  
All synchronous control (RPS, WPS, BWS  
) inputs pass  
[x:0]  
0
through input registers controlled by the rising edge of the input  
clocks (K and K).  
BWS , which are sampled with each set of 18-bit data words.  
1
Asserting the byte write select input during the data portion of a  
write latches the data being presented and writes it into the  
device. Deasserting the byte write select input during the data  
portion of a write enables the data stored in the device for that  
byte to remain unaltered. This feature can be used to simplify  
read, modify, or write operations to a byte write operation.  
CY7C1413JV18 is described in the following sections. The same  
basic descriptions apply to CY7C1411JV18, CY7C1426JV18,  
and CY7C1415JV18.  
Read Operations  
The CY7C1413JV18 is organized internally as four arrays of  
512K x 18. Accesses are completed in a burst of four sequential  
18-bit data words. Read operations are initiated by asserting  
RPS active at the rising edge of the positive input clock (K). The  
address presented to address inputs are stored in the read  
address register. Following the next K clock rise, the corre-  
sponding lowest order 18-bit word of data is driven onto the  
Single Clock Mode  
The CY7C1411JV18 can be used with a single clock that controls  
both the input and output registers. In this mode the device  
recognizes only a single pair of input clock (K and K) that control  
both the input and output registers. This operation is identical to  
the operation if the device had zero skew between the K/K and  
C/C clocks. All timing parameters remains the same in this mode.  
To use this mode of operation, the user must tie C and C HIGH  
at power on. This function is a strap option and not alterable  
during device operation.  
Q
using C as the output timing reference. On the subse-  
[17:0]  
quent rising edge of C, the next 18-bit data word is driven onto  
the Q . This process continues until all four 18-bit data words  
[17:0]  
have been driven out onto Q  
. The requested data is valid  
[17:0]  
0.45 ns from the rising edge of the output clock (C or C, or K or  
K when in single clock mode). To maintain the internal logic, each  
read access must be allowed to complete. Each read access  
consists of four 18-bit data words and takes two clock cycles to  
complete. Therefore, read accesses to the device can not be  
initiated on two consecutive K clock rises. The internal logic of  
the device ignores the second read request. Read accesses can  
be initiated on every other K clock rise. Doing so pipelines the  
data flow such that data is transferred out of the device on every  
Concurrent Transactions  
The read and write ports on the CY7C1413JV18 operates  
independently of one another. As each port latches the address  
inputs on different clock edges, the user can read or write to any  
location, regardless of the transaction on the other port. If the  
ports access the same location when a read follows a write in  
successive clock cycles, the SRAM delivers the most recent  
information associated with the specified address location. This  
Document Number: 001-12557 Rev. *C  
Page 8 of 28  
 
CY7C1411JV18, CY7C1426JV18  
CY7C1413JV18, CY7C1415JV18  
includes forwarding data from a write cycle that was initiated on  
the previous K clock rise.  
of ±15% is between 175Ω and 350Ω, with V  
= 1.5V. The  
DDQ  
output impedance is adjusted every 1024 cycles upon power up  
to account for drifts in supply voltage and temperature.  
Read accesses and write access must be scheduled such that  
one transaction is initiated on any clock cycle. If both ports are  
selected on the same K clock rise, the arbitration depends on the  
previous state of the SRAM. If both ports were deselected, the  
read port takes priority. If a read was initiated on the previous  
cycle, the write port takes priority (as read operations can not be  
initiated on consecutive cycles). If a write was initiated on the  
previous cycle, the read port takes priority (as write operations  
can not be initiated on consecutive cycles). Therefore, asserting  
both port selects active from a deselected state results in alter-  
nating read or write operations being initiated, with the first  
access being a read.  
Echo Clocks  
Echo clocks are provided on the QDR-II to simplify data capture  
on high speed systems. Two echo clocks are generated by the  
QDR-II. CQ is referenced with respect to C and CQ is referenced  
with respect to C. These are free running clocks and are synchro-  
nized to the output clock of the QDR-II. In the single clock mode,  
CQ is generated with respect to K and CQ is generated with  
respect to K. The timings for the echo clocks are shown in the  
DLL  
Depth Expansion  
These chips use a Delay Lock Loop (DLL) that is designed to  
function between 120 MHz and the specified maximum clock  
frequency. During power up, when the DOFF is tied HIGH, the  
DLL gets locked after 1024 cycles of stable clock. The DLL can  
also be reset by slowing or stopping the input clock K and K for  
a minimum of 30 ns. However, it is not necessary to reset the  
DLL to lock to the desired frequency. The DLL automatically  
locks 1024 clock cycles after a stable clock is presented. The  
DLL may be disabled by applying ground to the DOFF pin. When  
the DLL is turned off, the device behaves in QDR-I mode (with  
one cycle latency and a longer access time). For information  
refer to the application note “DLL Considerations in  
QDRII/DDRII”.  
The CY7C1413JV18 has a port select input for each port. This  
enables for easy depth expansion. Both port selects are sampled  
on the rising edge of the positive input clock only (K). Each port  
select input can deselect the specified port. Deselecting a port  
does not affect the other port. All pending transactions (read and  
write) completes prior to the device being deselected.  
Programmable Impedance  
An external resistor, RQ, must be connected between the ZQ pin  
on the SRAM and V to allow the SRAM to adjust its output  
driver impedance. The value of RQ must be 5X the value of the  
intended line impedance driven by the SRAM. The allowable  
range of RQ to guarantee impedance matching with a tolerance  
SS  
Application Example  
Figure 1 shows four QDR-II used in an application.  
Figure 1. Application Example  
SRAM #1  
R = 250ohms  
SRAM #4  
R = 250ohms  
ZQ  
CQ/CQ#  
Q
ZQ  
CQ/CQ#  
Q
R
P
S
#
R W  
B
W
P
B
W
S
Vt  
P
S
#
P
S
#
W
S
#
D
A
D
A
S
R
C
C#  
K
K#  
C
C#  
K
K#  
#
#
DATA IN  
DATA OUT  
Address  
Vt  
Vt  
R
RPS#  
BUS  
MASTER  
(CPU  
or  
WPS#  
BWS#  
CLKIN/CLKIN#  
Source K  
Source K#  
ASIC)  
Delayed K  
Delayed K#  
R
R = 50ohms  
Vt = Vddq/2  
Document Number: 001-12557 Rev. *C  
Page 9 of 28  
 
CY7C1411JV18, CY7C1426JV18  
CY7C1413JV18, CY7C1415JV18  
Truth Table  
The truth table for CY7C1411JV18, CY7C1426JV18, CY7C1413JV18, and CY7C1415JV18 follows.  
Operation  
Write Cycle:  
K
RPS WPS  
DQ  
DQ  
DQ  
DQ  
[8]  
L-H  
H
L
D(A) at K(t + 1)D(A + 1) at K(t + 1)D(A + 2) at K(t + 2)D(A + 3) at K(t + 2)↑  
Load address on the rising  
edge of K; input write data  
on two consecutive K and  
K rising edges.  
Read Cycle:  
L-H  
L-H  
L
X
Q(A) at C(t + 1)Q(A + 1) at C(t + 2)Q(A + 2) at C(t + 2)Q(A + 3) at C(t + 3)↑  
Load address on the rising  
edge of K; wait one and a  
half cycle; read data on  
two consecutive C and C  
rising edges.  
NOP: No Operation  
H
H
X
D = X  
Q = High-Z  
D = X  
Q = High-Z  
D = X  
Q = High-Z  
D = X  
Q = High-Z  
Standby: Clock Stopped Stopped  
X
Previous State  
Previous State  
Previous State  
Previous State  
Write Cycle Descriptions  
The write cycle description table for CY7C1411JV18 and CY7C1413JV18 follows.  
BWS / BWS /  
0
1
K
Comments  
K
NWS  
NWS  
1
0
L
L
L–H  
During the data portion of a write sequence :  
CY7C1411JV18 both nibbles (D  
) are written into the device,  
[7:0]  
CY7C1413JV18 both bytes (D  
) are written into the device.  
[17:0]  
L
L
L–H  
L-H During the data portion of a write sequence :  
CY7C1411JV18 both nibbles (D  
) are written into the device,  
[7:0]  
CY7C1413JV18 both bytes (D  
) are written into the device.  
[17:0]  
L
H
H
L
During the data portion of a write sequence :  
CY7C1411JV18 only the lower nibble (D  
) is written into the device, D  
) is written into the device, D  
remains unaltered.  
remains unaltered.  
[3:0]  
[7:4]  
[17:9]  
CY7C1413JV18 only the lower byte (D  
[8:0]  
L
L–H During the data portion of a write sequence :  
CY7C1411JV18 only the lower nibble (D  
) is written into the device, D  
remains unaltered.  
remains unaltered.  
[3:0]  
[7:4]  
CY7C1413JV18 only the lower byte (D  
) is written into the device, D  
[8:0]  
[17:9]  
H
H
L–H  
During the data portion of a write sequence :  
CY7C1411JV18 only the upper nibble (D  
) is written into the device, D  
) is written into the device, D  
remains unaltered.  
[3:0]  
[7:4]  
CY7C1413JV18 only the upper byte (D  
remains unaltered.  
[17:9]  
[8:0]  
L
L–H During the data portion of a write sequence :  
CY7C1411JV18 only the upper nibble (D  
) is written into the device, D  
) is written into the device, D  
remains unaltered.  
remains unaltered.  
[7:4]  
[3:0]  
[8:0]  
CY7C1413JV18 only the upper byte (D  
[17:9]  
H
H
H
H
L–H  
No data is written into the devices during this portion of a write operation.  
L–H No data is written into the devices during this portion of a write operation.  
Notes  
2. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, represents rising edge.  
3. Device powers up deselected with the outputs in a tri-state condition.  
4. “A” represents address location latched by the devices when transaction was initiated. A + 1, A + 2, and A +3 represents the address sequence in the burst.  
5. “t” represents the cycle at which a read/write operation is started. t + 1, t + 2, and t + 3 are the first, second and third clock cycles respectively succeeding the “t” clock cycle.  
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.  
7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging  
symmetrically.  
8. If this signal was LOW to initiate the previous cycle, this signal becomes a “Don’t Care” for this operation.  
9. This signal was HIGH on previous K clock rise. Initiating consecutive read or write operations on consecutive K clock rises is not permitted. The device ignores the  
second read or write request.  
10. Is based on a write cycle that was initiated in accordance with the Write Cycle Descriptions table. NWS , NWS , BWS , BWS , BWS , and BWS can be altered on  
0
1
0
1
2
3
different portions of a write cycle, as long as the setup and hold requirements are achieved.  
Document Number: 001-12557 Rev. *C  
Page 10 of 28  
                   
CY7C1411JV18, CY7C1426JV18  
CY7C1413JV18, CY7C1415JV18  
Write Cycle Descriptions  
The write cycle description table for CY7C1426JV18 follows.  
BWS  
K
L–H  
K
0
L
L
During the data portion of a write sequence, the single byte (D  
) is written into the device.  
) is written into the device.  
[8:0]  
L–H During the data portion of a write sequence, the single byte (D  
[8:0]  
H
H
L–H  
No data is written into the device during this portion of a write operation.  
L–H No data is written into the device during this portion of a write operation.  
Write Cycle Descriptions  
The write cycle description table for CY7C1415JV18 follows.  
[2, 10]  
BWS  
BWS  
BWS  
BWS  
3
K
K
Comments  
0
1
2
L
L
L
L
L–H  
During the data portion of a write sequence, all four bytes (D  
the device.  
) are written into  
) are written into  
[35:0]  
L
L
L
H
H
L
L
H
H
H
H
L
L
H
H
H
H
H
H
L
L–H  
L–H During the data portion of a write sequence, all four bytes (D  
the device.  
[35:0]  
During the data portion of a write sequence, only the lower byte (D  
) is written  
) is written  
[8:0]  
[8:0]  
into the device. D  
remains unaltered.  
[35:9]  
L
L–H During the data portion of a write sequence, only the lower byte (D  
into the device. D remains unaltered.  
[35:9]  
H
H
H
H
H
H
L–H  
During the data portion of a write sequence, only the byte (D  
) is written into  
[17:9]  
the device. D  
and D  
remains unaltered.  
[8:0]  
[35:18]  
L
L–H During the data portion of a write sequence, only the byte (D  
the device. D and D remains unaltered.  
) is written into  
[17:9]  
[8:0]  
[35:18]  
H
H
H
H
L–H  
During the data portion of a write sequence, only the byte (D  
) is written into  
) is written into  
) is written into  
) is written into  
[26:18]  
[26:18]  
[35:27]  
[35:27]  
the device. D  
and D  
remains unaltered.  
[17:0]  
[35:27]  
L
L–H During the data portion of a write sequence, only the byte (D  
the device. D and D remains unaltered.  
[17:0]  
[35:27]  
H
H
L–H  
During the data portion of a write sequence, only the byte (D  
the device. D remains unaltered.  
[26:0]  
L
L–H During the data portion of a write sequence, only the byte (D  
the device. D remains unaltered.  
[26:0]  
H
H
H
H
H
H
H
H
L–H  
No data is written into the device during this portion of a write operation.  
L–H No data is written into the device during this portion of a write operation.  
Document Number: 001-12557 Rev. *C  
Page 11 of 28  
CY7C1411JV18, CY7C1426JV18  
CY7C1413JV18, CY7C1415JV18  
Instruction Register  
IEEE 1149.1 Serial Boundary Scan (JTAG)  
Three-bit instructions can be serially loaded into the instruction  
register. This register is loaded when it is placed between the TDI  
and TDO pins, as shown in TAP Controller Block Diagram on  
page 15. Upon power up, the instruction register is loaded with  
the IDCODE instruction. It is also loaded with the IDCODE  
instruction if the controller is placed in a reset state, as described  
in the previous section.  
These SRAMs incorporate a serial boundary scan Test Access  
Port (TAP) in the FBGA package. This part is fully compliant with  
IEEE Standard #1149.1-2001. The TAP operates using JEDEC  
standard 1.8V IO logic levels.  
Disabling the JTAG Feature  
It is possible to operate the SRAM without using the JTAG  
feature. To disable the TAP controller, TCK must be tied LOW  
When the TAP controller is in the Capture-IR state, the two least  
significant bits are loaded with a binary “01” pattern to allow for  
fault isolation of the board level serial test path.  
(V ) to prevent clocking of the device. TDI and TMS are inter-  
SS  
nally pulled up and may be unconnected. They may alternatively  
be connected to V through a pull up resistor. TDO must be left  
unconnected. Upon power up, the device comes up in a reset  
state, which does not interfere with the operation of the device.  
Bypass Register  
DD  
To save time when serially shifting data through registers, it is  
sometimes advantageous to skip certain chips. The bypass  
register is a single-bit register that can be placed between TDI  
and TDO pins. This enables shifting of data through the SRAM  
with minimal delay. The bypass register is set LOW (V ) when  
the BYPASS instruction is executed.  
Test Access Port—Test Clock  
The test clock is used only with the TAP controller. All inputs are  
captured on the rising edge of TCK. All outputs are driven from  
the falling edge of TCK.  
SS  
Boundary Scan Register  
Test Mode Select (TMS)  
The boundary scan register is connected to all of the input and  
output pins on the SRAM. Several No Connect (NC) pins are also  
included in the scan register to reserve pins for higher density  
devices.  
The TMS input is used to give commands to the TAP controller  
and is sampled on the rising edge of TCK. This pin may be left  
unconnected if the TAP is not used. The pin is pulled up inter-  
nally, resulting in a logic HIGH level.  
The boundary scan register is loaded with the contents of the  
RAM input and output ring when the TAP controller is in the  
Capture-DR state and is then placed between the TDI and TDO  
pins when the controller is moved to the Shift-DR state. The  
EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can  
be used to capture the contents of the input and output ring.  
Test Data-In (TDI)  
The TDI pin is used to serially input information into the registers  
and can be connected to the input of any of the registers. The  
register between TDI and TDO is chosen by the instruction that  
is loaded into the TAP instruction register. For information on  
loading the instruction register, see the TAP Controller State  
Diagram on page 14. TDI is internally pulled up and can be  
unconnected if the TAP is unused in an application. TDI is  
connected to the most significant bit (MSB) on any register.  
The Boundary Scan Order on page 18 shows the order in which  
the bits are connected. Each bit corresponds to one of the bumps  
on the SRAM package. The MSB of the register is connected to  
TDI, and the LSB is connected to TDO.  
Identification (ID) Register  
Test Data-Out (TDO)  
The ID register is loaded with a vendor-specific, 32-bit code  
during the Capture-DR state when the IDCODE command is  
loaded in the instruction register. The IDCODE is hardwired into  
the SRAM and can be shifted out when the TAP controller is in  
the Shift-DR state. The ID register has a vendor code and other  
The TDO output pin is used to serially clock data out from the  
registers. The output is active, depending upon the current state  
of the TAP state machine (see Instruction Codes on page 17).  
The output changes on the falling edge of TCK. TDO is  
connected to the least significant bit (LSB) of any register.  
Performing a TAP Reset  
A Reset is performed by forcing TMS HIGH (V ) for five rising  
TAP Instruction Set  
DD  
edges of TCK. This Reset does not affect the operation of the  
SRAM and can be performed while the SRAM is operating. At  
power up, the TAP is reset internally to ensure that TDO comes  
up in a high-Z state.  
Eight different instructions are possible with the three-bit  
instruction register. All combinations are listed in Instruction  
Codes on page 17. Three of these instructions are listed as  
RESERVED and must not be used. The other five instructions  
are described in this section in detail.  
TAP Registers  
Instructions are loaded into the TAP controller during the Shift-IR  
state when the instruction register is placed between TDI and  
TDO. During this state, instructions are shifted through the  
instruction register through the TDI and TDO pins. To execute  
the instruction after it is shifted in, the TAP controller must be  
moved into the Update-IR state.  
Registers are connected between the TDI and TDO pins to scan  
the data in and out of the SRAM test circuitry. Only one register  
can be selected at a time through the instruction registers. Data  
is serially loaded into the TDI pin on the rising edge of TCK. Data  
is output on the TDO pin on the falling edge of TCK.  
Document Number: 001-12557 Rev. *C  
Page 12 of 28  
CY7C1411JV18, CY7C1426JV18  
CY7C1413JV18, CY7C1415JV18  
IDCODE  
PRELOAD places an initial data pattern at the latched parallel  
outputs of the boundary scan register cells before the selection  
of another boundary scan test operation.  
The IDCODE instruction loads a vendor-specific, 32-bit code into  
the instruction register. It also places the instruction register  
between the TDI and TDO pins and shifts the IDCODE out of the  
device when the TAP controller enters the Shift-DR state. The  
IDCODE instruction is loaded into the instruction register at  
The shifting of data for the SAMPLE and PRELOAD phases can  
occur concurrently when required, that is, while the data  
captured is shifted out, the preloaded data can be shifted in.  
power up or whenever the TAP controller is given  
Test-Logic-Reset state.  
a
BYPASS  
When the BYPASS instruction is loaded in the instruction register  
and the TAP is placed in a Shift-DR state, the bypass register is  
placed between the TDI and TDO pins. The advantage of the  
BYPASS instruction is that it shortens the boundary scan path  
when multiple devices are connected together on a board.  
SAMPLE Z  
The SAMPLE Z instruction connects the boundary scan register  
between the TDI and TDO pins when the TAP controller is in a  
Shift-DR state. The SAMPLE Z command puts the output bus  
into a High-Z state until the next command is given during the  
Update IR state.  
EXTEST  
The EXTEST instruction drives the preloaded data out through  
the system output pins. This instruction also connects the  
boundary scan register for serial access between the TDI and  
TDO in the Shift-DR controller state.  
SAMPLE/PRELOAD  
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When  
the SAMPLE/PRELOAD instructions are loaded into the  
instruction register and the TAP controller is in the Capture-DR  
state, a snapshot of data on the input and output pins is captured  
in the boundary scan register.  
EXTEST OUTPUT BUS TRI-STATE  
IEEE Standard 1149.1 mandates that the TAP controller be able  
to put the output bus into a tri-state mode.  
The user must be aware that the TAP controller clock can only  
operate at a frequency up to 20 MHz, while the SRAM clock  
operates more than an order of magnitude faster. Because there  
is a large difference in the clock frequencies, it is possible that  
during the Capture-DR state, an input or output undergoes a  
transition. The TAP may then try to capture a signal while in  
transition (metastable state). This does not harm the device, but  
there is no guarantee as to the value that is captured.  
Repeatable results may not be possible.  
The boundary scan register has a special bit located at bit #108.  
When this scan cell, called the “extest output bus tri-state,” is  
latched into the preload register during the Update-DR state in  
the TAP controller, it directly controls the state of the output  
(Q-bus) pins, when the EXTEST is entered as the current  
instruction. When HIGH, it enables the output buffers to drive the  
output bus. When LOW, this bit places the output bus into a  
High-Z condition.  
To guarantee that the boundary scan register captures the  
correct value of a signal, the SRAM signal must be stabilized  
long enough to meet the TAP controller's capture setup plus hold  
times (t and t ). The SRAM clock input might not be captured  
correctly if there is no way in a design to stop (or slow) the clock  
during a SAMPLE/PRELOAD instruction. If this is an issue, it is  
still possible to capture all other signals and simply ignore the  
value of the CK and CK captured in the boundary scan register.  
This bit can be set by entering the SAMPLE/PRELOAD or  
EXTEST command, and then shifting the desired bit into that cell,  
during the Shift-DR state. During Update-DR, the value loaded  
into that shift-register cell latches into the preload register. When  
the EXTEST instruction is entered, this bit directly controls the  
output Q-bus pins. Note that this bit is preset HIGH to enable the  
output when the device is powered up, and also when the TAP  
controller is in the Test-Logic-Reset state.  
CS  
CH  
After the data is captured, it is possible to shift out the data by  
putting the TAP into the Shift-DR state. This places the boundary  
scan register between the TDI and TDO pins.  
Reserved  
These instructions are not implemented but are reserved for  
future use. Do not use these instructions.  
Document Number: 001-12557 Rev. *C  
Page 13 of 28  
CY7C1411JV18, CY7C1426JV18  
CY7C1413JV18, CY7C1415JV18  
TAP Controller State Diagram  
The state diagram for the TAP controller follows.  
TEST-LOGIC  
1
RESET  
0
1
1
1
SELECT  
TEST-LOGIC/  
SELECT  
0
IR-SCAN  
IDLE  
DR-SCAN  
0
0
1
1
CAPTURE-DR  
0
CAPTURE-IR  
0
0
1
0
1
SHIFT-DR  
1
SHIFT-IR  
1
EXIT1-DR  
0
EXIT1-IR  
0
0
0
PAUSE-DR  
1
PAUSE-IR  
1
0
0
EXIT2-DR  
1
EXIT2-IR  
1
UPDATE-IR  
0
UPDATE-DR  
1
1
0
Note  
11. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.  
Document Number: 001-12557 Rev. *C  
Page 14 of 28  
   
CY7C1411JV18, CY7C1426JV18  
CY7C1413JV18, CY7C1415JV18  
TAP Controller Block Diagram  
0
Bypass Register  
2
1
1
1
0
0
0
Selection  
TDI  
Selection  
Circuitry  
TDO  
Instruction Register  
Circuitry  
31 30  
29  
.
.
2
Identification Register  
.
108  
.
.
.
2
Boundary Scan Register  
TCK  
TMS  
TAP Controller  
TAP Electrical Characteristics  
Over the Operating Range  
Parameter  
Description  
Output HIGH Voltage  
Test Conditions  
= 2.0 mA  
Min  
1.4  
1.6  
Max  
Unit  
V
V
V
V
V
V
I
I
I
I
I
V
V
OH1  
OH2  
OL1  
OL2  
IH  
OH  
OH  
OL  
OL  
Output HIGH Voltage  
Output LOW Voltage  
Output LOW Voltage  
Input HIGH Voltage  
= 100 μA  
= 2.0 mA  
0.4  
0.2  
V
= 100 μA  
V
0.65V  
V
+ 0.3  
V
DD  
DD  
Input LOW Voltage  
–0.3  
–5  
0.35V  
5
V
IL  
DD  
Input and Output Load Current  
GND V V  
DD  
μA  
X
I
Notes  
12. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table.  
13. Overshoot: V (AC) < V + 0.85V (Pulse width less than t /2).  
/2), Undershoot: V (AC) > 1.5V (Pulse width less than t  
IH  
DDQ  
CYC  
IL  
CYC  
14. All Voltage referenced to Ground.  
Document Number: 001-12557 Rev. *C  
Page 15 of 28  
       
CY7C1411JV18, CY7C1426JV18  
CY7C1413JV18, CY7C1415JV18  
TAP AC Switching Characteristics  
Over the Operating Range  
Parameter  
Description  
Min  
Max  
Unit  
ns  
t
t
t
t
TCK Clock Cycle Time  
TCK Clock Frequency  
TCK Clock HIGH  
50  
TCYC  
TF  
20  
MHz  
ns  
20  
20  
TH  
TCK Clock LOW  
ns  
TL  
Setup Times  
t
t
t
TMS Setup to TCK Clock Rise  
TDI Setup to TCK Clock Rise  
Capture Setup to TCK Rise  
5
5
5
ns  
ns  
ns  
TMSS  
TDIS  
CS  
Hold Times  
t
t
t
TMS Hold after TCK Clock Rise  
TDI Hold after Clock Rise  
5
5
5
ns  
ns  
ns  
TMSH  
TDIH  
CH  
Capture Hold after Clock Rise  
Output Times  
t
t
TCK Clock LOW to TDO Valid  
TCK Clock LOW to TDO Invalid  
10  
ns  
ns  
TDOV  
TDOX  
0
TAP Timing and Test Conditions  
Figure 2 shows the TAP timing and test conditions.  
Figure 2. TAP Timing and Test Conditions  
0.9V  
ALL INPUT PULSES  
1.8V  
50Ω  
0.9V  
TDO  
0V  
Z = 50  
Ω
0
C = 20 pF  
L
t
t
TH  
TL  
GND  
(a)  
Test Clock  
TCK  
t
TCYC  
t
TMSH  
t
TMSS  
Test Mode Select  
TMS  
t
TDIS  
t
TDIH  
Test Data In  
TDI  
Test Data Out  
TDO  
t
TDOV  
t
TDOX  
Notes  
15. t and t refer to the setup and hold time requirements of latching data from the boundary scan register.  
CS  
CH  
16. Test conditions are specified using the load in TAP AC Test Conditions. t /t = 1 ns.  
R
F
Document Number: 001-12557 Rev. *C  
Page 16 of 28  
     
CY7C1411JV18, CY7C1426JV18  
CY7C1413JV18, CY7C1415JV18  
Identification Register Definitions  
Value  
Instruction Field  
Description  
CY7C1411JV18  
CY7C1426JV18  
000  
CY7C1413JV18  
000  
CY7C1415JV18  
Revision Number  
(31:29)  
000  
000  
Version number.  
Cypress Device ID 11010011011000111 11010011011001111 11010011011010111 11010011011100111 Defines the type of  
(28:12)  
SRAM.  
Cypress JEDEC ID  
(11:1)  
00000110100  
1
00000110100  
1
00000110100  
1
00000110100  
1
Allows unique  
identification of  
SRAM vendor.  
ID Register  
Presence (0)  
Indicates the  
presence of an ID  
register.  
Scan Register Sizes  
Register Name  
Bit Size  
Instruction  
Bypass  
3
1
ID  
32  
109  
Boundary Scan  
Instruction Codes  
Instruction  
EXTEST  
Code  
000  
Description  
Captures the input and output ring contents.  
IDCODE  
001  
Loads the ID register with the vendor ID code and places the register between TDI and TDO.  
This operation does not affect SRAM operation.  
SAMPLE Z  
010  
Captures the input and output contents. Places the boundary scan register between TDI and  
TDO. Forces all SRAM output drivers to a High-Z state.  
RESERVED  
011  
100  
Do Not Use: This instruction is reserved for future use.  
SAMPLE/PRELOAD  
Captures the input and output ring contents. Places the boundary scan register between TDI  
and TDO. Does not affect the SRAM operation.  
RESERVED  
RESERVED  
BYPASS  
101  
110  
111  
Do Not Use: This instruction is reserved for future use.  
Do Not Use: This instruction is reserved for future use.  
Places the bypass register between TDI and TDO. This operation does not affect SRAM  
operation.  
Document Number: 001-12557 Rev. *C  
Page 17 of 28  
   
CY7C1411JV18, CY7C1426JV18  
CY7C1413JV18, CY7C1415JV18  
Boundary Scan Order  
Bit #  
0
Bump ID  
6R  
Bit #  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
Bump ID  
10G  
9G  
Bit #  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
Bump ID  
6A  
5B  
5A  
4A  
5C  
4B  
3A  
2A  
1A  
2B  
3B  
1C  
1B  
3D  
3C  
1D  
2C  
3E  
2D  
2E  
1E  
2F  
Bit #  
84  
Bump ID  
1J  
1
6P  
85  
2J  
2
6N  
11F  
11G  
9F  
86  
3K  
3
7P  
87  
3J  
4
7N  
88  
2K  
5
7R  
10F  
11E  
10E  
10D  
9E  
89  
1K  
6
8R  
90  
2L  
7
8P  
91  
3L  
8
9R  
92  
1M  
1L  
9
11P  
10P  
10N  
9P  
93  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
10C  
11D  
9C  
94  
3N  
95  
3M  
1N  
96  
10M  
11N  
9M  
9D  
97  
2M  
3P  
11B  
11C  
9B  
98  
99  
2N  
9N  
100  
101  
102  
103  
104  
105  
106  
107  
108  
2P  
11L  
11M  
9L  
10B  
11A  
10A  
9A  
1P  
3R  
4R  
10L  
11K  
10K  
9J  
4P  
8B  
5P  
7C  
3F  
5N  
6C  
1G  
1F  
5R  
9K  
8A  
Internal  
10J  
11J  
11H  
7A  
3G  
2G  
1H  
7B  
6B  
Document Number: 001-12557 Rev. *C  
Page 18 of 28  
 
CY7C1411JV18, CY7C1426JV18  
CY7C1413JV18, CY7C1415JV18  
DLL Constraints  
Power Up Sequence in QDR-II SRAM  
DLL uses K clock as its synchronizing input. The input must  
have low phase jitter, which is specified as t  
QDR-II SRAMs must be powered up and initialized in a  
predefined manner to prevent undefined operations.  
.
KC Var  
The DLL functions at frequencies down to 120 MHz.  
Power Up Sequence  
If the input clock is unstable and the DLL is enabled, then the  
DLL may lock onto an incorrect frequency, causing unstable  
SRAM behavior. To avoid this, provide1024 cycles stable clock  
to relock to the desired clock frequency.  
Apply power and drive DOFF either HIGH or LOW (all other  
inputs can be HIGH or LOW).  
Apply V before V  
.
DD  
DDQ  
Apply V  
before V  
or at the same time as V  
.
DDQ  
REF  
REF  
Drive DOFF HIGH.  
Provide stable DOFF (HIGH), power and clock (K, K) for 1024  
cycles to lock the DLL.  
Figure 3. Power Up Waveforms  
K
K
Unstable Clock  
> 1024 Stable clock  
Stable)  
DDQ  
Start Normal  
Operation  
/
V
Clock Start (Clock Starts after V  
DD  
Stable (< +/- 0.1V DC per 50ns )  
/
/
V
VDDQ  
V
VDD  
DD  
DDQ  
Fix High (or tie to V  
)
DDQ  
DOFF  
Document Number: 001-12557 Rev. *C  
Page 19 of 28  
CY7C1411JV18, CY7C1426JV18  
CY7C1413JV18, CY7C1415JV18  
Current into Outputs (LOW) ........................................ 20 mA  
Static Discharge Voltage (MIL-STD-883, M. 3015).. > 2001V  
Latch Up Current................................................... > 200 mA  
Maximum Ratings  
Exceeding maximum ratings may impair the useful life of the  
device. These user guidelines are not tested.  
Storage Temperature ................................. –65°C to +150°C  
Ambient Temperature with Power Applied.. –55°C to +125°C  
Operating Range  
Ambient  
Range  
Commercial  
Industrial  
Temperature (T )  
V
V
DDQ  
Supply Voltage on V Relative to GND........–0.5V to +2.9V  
A
DD  
DD  
0°C to +70°C  
1.8 ± 0.1V  
1.4V to  
Supply Voltage on V  
Relative to GND.......–0.5V to +V  
DD  
DDQ  
V
DD  
–40°C to +85°C  
DC Applied to Outputs in High-Z ........ –0.5V to V  
+ 0.3V  
DDQ  
DC Input Voltage  
.............................. –0.5V to V + 0.3V  
DD  
Electrical Characteristics  
DC Electrical Characteristics  
Over the Operating Range  
Parameter  
Description  
Power Supply Voltage  
IO Supply Voltage  
Test Conditions  
Min  
1.7  
1.4  
Typ  
Max  
Unit  
V
1.8  
1.5  
1.9  
V
V
DD  
V
V
V
V
V
V
V
I
V
DD  
DDQ  
OH  
Output HIGH Voltage  
Output LOW Voltage  
Output HIGH Voltage  
Output LOW Voltage  
Input HIGH Voltage  
Input LOW Voltage  
Note 18  
Note 19  
V
V
/2 – 0.12  
/2 – 0.12  
– 0.2  
V
V
/2 + 0.12  
/2 + 0.12  
V
DDQ  
DDQ  
DDQ  
V
OL  
DDQ  
I
I
= 0.1 mA, Nominal Impedance  
V
V
V
OH(LOW)  
OL(LOW)  
IH  
OH  
OL  
DDQ  
DDQ  
= 0.1 mA, Nominal Impedance  
V
0.2  
V
SS  
V
+ 0.1  
V
+ 0.15  
V
REF  
DDQ  
–0.15  
V
– 0.1  
V
IL  
REF  
Input Leakage Current  
Output Leakage Current  
Input Reference Voltage  
GND V V  
2  
2  
2
μA  
μA  
V
X
I
DDQ  
I
GND V V  
Output Disabled  
2
OZ  
I
DDQ,  
V
Typical Value = 0.75V  
0.68  
0.75  
0.95  
965  
970  
1010  
1130  
745  
760  
790  
870  
620  
620  
655  
715  
REF  
I
V
Operating Supply  
V
= Max,  
300 MHz  
250 MHz  
200 MHz  
(x8)  
(x9)  
mA  
DD  
DD  
DD  
I
= 0 mA,  
OUT  
f = f  
= 1/t  
MAX  
CYC  
(x18)  
(x36)  
(x8)  
mA  
mA  
(x9)  
(x18)  
(x36)  
(x8)  
(x9)  
(x18)  
(x36)  
Notes  
17. Power up: Assumes a linear ramp from 0V to V (min) within 200 ms. During this time V < V and V  
< V .  
DD  
DD  
IH  
DD  
DDQ  
18. Output are impedance controlled. I = (V  
/2)/(RQ/5) for values of 175 ohms <= RQ <= 350 ohms.  
/2)/(RQ/5) for values of 175 ohms <= RQ <= 350 ohms.  
DDQ  
OH  
DDQ  
19. Output are impedance controlled. I = (V  
OL  
20. V  
(min) = 0.68V or 0.46V  
, whichever is larger, V  
(max) = 0.95V or 0.54V  
, whichever is smaller.  
REF  
DDQ  
REF  
DDQ  
21. The operation current is calculated with 50% read cycle and 50% write cycle.  
Document Number: 001-12557 Rev. *C  
Page 20 of 28  
           
CY7C1411JV18, CY7C1426JV18  
CY7C1413JV18, CY7C1415JV18  
Electrical Characteristics (continued)  
DC Electrical Characteristics  
[14]  
Over the Operating Range  
Parameter  
Description  
Test Conditions  
Min  
Typ  
Max  
350  
350  
355  
395  
355  
355  
355  
370  
300  
300  
300  
300  
Unit  
I
Automatic Power Down  
Current  
Max V  
,
300 MHz  
250 MHz  
200 MHz  
(x8)  
(x9)  
mA  
SB1  
DD  
Both Ports Deselected,  
V
V or V V  
IN  
IH  
= 1/t  
IN  
IL  
(x18)  
(x36)  
(x8)  
f = f  
, Inputs  
MAX  
CYC  
Static  
mA  
mA  
(x9)  
(x18)  
(x36)  
(x8)  
(x9)  
(x18)  
(x36)  
AC Electrical Characteristics  
Over the Operating Range  
Parameter  
Description  
Input HIGH Voltage  
Input LOW Voltage  
Test Conditions  
Min  
+ 0.2  
REF  
Typ  
Max  
Unit  
V
V
V
IH  
IL  
V
V
– 0.2  
V
REF  
Document Number: 001-12557 Rev. *C  
Page 21 of 28  
CY7C1411JV18, CY7C1426JV18  
CY7C1413JV18, CY7C1415JV18  
Capacitance  
Tested initially and after any design or process change that may affect these parameters.  
Parameter  
Description  
Input Capacitance  
Test Conditions  
Max  
Unit  
pF  
C
T = 25°C, f = 1 MHz, V = 1.8V, V = 1.5V  
DDQ  
5
4
6
IN  
A
DD  
C
C
Clock Input Capacitance  
Output Capacitance  
pF  
CLK  
O
pF  
Thermal Resistance  
Tested initially and after any design or process change that may affect these parameters.  
165 FBGA  
Package  
Parameter  
Description  
Test Conditions  
Unit  
Θ
Thermal Resistance  
(Junction to Ambient)  
Test conditions follow standard test methods and  
procedures for measuring thermal impedance, in  
accordance with EIA/JESD51.  
17.2  
°C/W  
JA  
Θ
Thermal Resistance  
(Junction to Case)  
3.2  
°C/W  
JC  
Figure 4. AC Test Loads and Waveforms  
V
REF = 0.75V  
0.75V  
VREF  
VREF  
0.75V  
R = 50Ω  
OUTPUT  
ALL INPUT PULSES  
1.25V  
Z = 50Ω  
0
OUTPUT  
Device  
Under  
Test  
R = 50Ω  
L
0.75V  
Device  
Under  
0.25V  
5 pF  
VREF = 0.75V  
Slew Rate = 2 V/ns  
ZQ  
Test  
ZQ  
RQ =  
RQ =  
250Ω  
250Ω  
INCLUDING  
JIG AND  
SCOPE  
(a)  
(b)  
Notes  
22. Unless otherwise noted, test conditions are based on signal transition time of 2V/ns, timing reference levels of 0.75V, Vref = 0.75V, RQ = 250Ω, V  
= 1.5V, input  
DDQ  
pulse levels of 0.25V to 1.25V, and output loading of the specified I /I and load capacitance shown in (a) of AC Test Loads and Waveforms.  
OL OH  
Document Number: 001-12557 Rev. *C  
Page 22 of 28  
   
CY7C1411JV18, CY7C1426JV18  
CY7C1413JV18, CY7C1415JV18  
Switching Characteristics  
Over the Operating Range  
300 MHz  
250 MHz  
200 MHz  
Cypress Consortium  
Parameter Parameter  
Description  
Unit  
Min Max Min Max Min Max  
t
t
t
t
t
V
(Typical) to the First Access  
1
1
1
ms  
ns  
ns  
ns  
ns  
POWER  
CYC  
KH  
DD  
t
t
t
t
K Clock and C Clock Cycle Time  
Input Clock (K/K; C/C) HIGH  
Input Clock (K/K; C/C) LOW  
3.3 8.4 4.0 8.4 5.0 8.4  
KHKH  
KHKL  
KLKH  
KHKH  
1.32  
1.32  
1.49  
1.6  
1.6  
1.8  
2.0  
2.0  
2.2  
KL  
K Clock Rise to K Clock Rise and C to C Rise  
(rising edge to rising edge)  
KHKH  
t
t
0
1.45  
0
1.8  
0
2.2  
ns  
K/K Clock Rise to C/C Clock Rise (rising edge to rising edge)  
KHCH  
KHCH  
Setup Times  
t
t
t
t
t
t
Address Setup to K Clock Rise  
0.4  
0.4  
0.3  
0.5  
0.5  
0.6  
0.6  
0.4  
ns  
ns  
ns  
SA  
AVKH  
IVKH  
IVKH  
Control Setup to Clock (K, K) Rise (RPS, WPS)  
Double Data Rate Control Setup to Clock (K, K) Rise  
SC  
0.35  
SCDDR  
(BWS , BWS , BWS , BWS )  
0
1
2
3
t
t
0.3  
0.35  
0.4  
ns  
D
Setup to Clock (K/K) Rise  
SD  
DVKH  
[X:0]  
Hold Times  
t
t
t
t
0.4  
0.4  
0.3  
0.5  
0.5  
0.6  
0.6  
0.4  
ns  
ns  
ns  
Address Hold after Clock (K/K) Rise  
Control Hold after Clock (K /K) Rise (RPS, WPS)  
Double Data Rate Control Hold after Clock (K/K) Rise  
HA  
KHAX  
KHIX  
KHIX  
t
t
HC  
0.35  
HCDDR  
(BWS , BWS , BWS , BWS )  
0
1
2
3
t
t
0.3  
0.35  
0.4  
ns  
D
Hold after Clock (K/K) Rise  
HD  
KHDX  
[X:0]  
Output Times  
t
t
t
t
0.45  
0.45  
0.45  
ns  
ns  
C/C Clock Rise (or K/K in single clock mode) to Data Valid  
CO  
CHQV  
CHQX  
–0.45  
–0.45  
–0.45  
Data Output Hold after Output C/C Clock Rise  
(Active to Active)  
DOH  
t
t
t
t
t
t
t
t
t
t
t
t
0.45  
0.45  
0.45  
ns  
ns  
ns  
ns  
ns  
ns  
C/C Clock Rise to Echo Clock Valid  
Echo Clock Hold after C/C Clock Rise  
Echo Clock High to Data Valid  
CCQO  
CQOH  
CQD  
CHCQV  
CHCQX  
CQHQV  
CQHQX  
CQHCQL  
CQHCQH  
–0.45  
–0.45  
–0.45  
0.27  
0.3  
0.35  
Echo Clock High to Data Invalid  
–0.27  
1.24  
1.24  
–0.3  
1.55  
1.55  
–0.35  
1.95  
1.95  
CQDOH  
CQH  
Output Clock (CQ/CQ) HIGH  
CQ Clock Rise to CQ Clock Rise  
CQHCQH  
(rising edge to rising edge)  
t
t
t
t
0.45  
0.45  
0.45  
ns  
ns  
Clock (C and C) Rise to High-Z (Active to High-Z)  
CHZ  
CLZ  
CHQZ  
–0.45  
–0.45  
–0.45  
Clock (C and C) Rise to Low-Z  
CHQX1  
DLL Timing  
t
t
t
t
t
t
Clock Phase Jitter  
0.20  
0.20  
0.20  
ns  
Cycles  
ns  
KC Var  
KC Var  
DLL Lock Time (K, C)  
K Static to DLL Reset  
1024  
30  
1024  
30  
1024  
30  
KC lock  
KC Reset  
KC lock  
KC Reset  
Notes  
23. This part has a voltage regulator internally; t  
is the time that the power must be supplied above V minimum initially before a read or write operation can be  
DD  
POWER  
initiated.  
24. These parameters are extrapolated from the input timing parameters (t  
- 250 ps, where 250 ps is the internal jitter. An input jitter of 200 ps (t  
) ia already  
KHKH  
KC Var  
included in the t  
). These parameters are only guaranteed by design and are not tested in production  
KHKH  
25. t  
, t  
, are specified with a load capacitance of 5 pF as in (b) of AC Test Loads and Waveforms. Transition is measured ± 100 mV from steady-state voltage.  
CHZ CLZ  
26. At any given voltage and temperature t  
is less than t  
and t  
less than t  
.
CO  
CHZ  
CLZ  
CHZ  
Document Number: 001-12557 Rev. *C  
Page 23 of 28  
         
CY7C1411JV18, CY7C1426JV18  
CY7C1413JV18, CY7C1415JV18  
Switching Waveforms  
Figure 5. Read/Write/Deselect Sequence  
NOP  
6
NOP  
1
WRITE  
3
READ  
4
WRITE  
5
READ  
2
7
K
t
t
t
t
t
KHKH  
KH  
KL  
SC  
CYC  
K
RPS  
t
HC  
t
t
SC  
HC  
WPS  
A
A0  
A1  
A2  
A3  
t
t
HD  
t
t
HD  
SA  
HA  
t
t
SD  
SD  
D13  
D30  
D31  
D12  
D32  
D33  
D10  
Q00  
D11  
D
Q
Q20  
CQDOH  
Q21  
Q22  
Q01  
Q02  
Q03  
Q23  
CHZ  
t
t
t
CO  
t
KHCH  
t
CLZ  
t
t
t
KHCH  
DOH  
CQD  
C
t
t
t
t
KHKH  
KH  
CYC  
KL  
C
CQ  
CQ  
t
CCQO  
t
CQOH  
t
CQH  
t
t
CCQO  
CQHCQH  
t
CQOH  
DON’T CARE  
UNDEFINED  
Notes  
27. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0+1.  
28. Outputs are disabled (High-Z) one clock cycle after a NOP.  
29. In this example, if address A2 = A1, then data Q20 = D10 and Q21 = D11. Write data is forwarded immediately as read results. This note applies to the whole diagram.  
Document Number: 001-12557 Rev. *C  
Page 24 of 28  
     
CY7C1411JV18, CY7C1426JV18  
CY7C1413JV18, CY7C1415JV18  
Ordering Information  
Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or  
visit www.cypress.com for actual products offered.  
Speed  
(MHz)  
Package  
Diagram  
Operating  
Range  
Ordering Code  
Package Type  
300 CY7C1411JV18-300BZC  
CY7C1426JV18-300BZC  
CY7C1413JV18-300BZC  
CY7C1415JV18-300BZC  
CY7C1411JV18-300BZXC  
CY7C1426JV18-300BZXC  
CY7C1413JV18-300BZXC  
CY7C1415JV18-300BZXC  
CY7C1411JV18-300BZI  
CY7C1426JV18-300BZI  
CY7C1413JV18-300BZI  
CY7C1415JV18-300BZI  
CY7C1411JV18-300BZXI  
CY7C1426JV18-300BZXI  
CY7C1413JV18-300BZXI  
CY7C1415JV18-300BZXI  
250 CY7C1411JV18-250BZC  
CY7C1426JV18-250BZC  
CY7C1413JV18-250BZC  
CY7C1415JV18-250BZC  
CY7C1411JV18-250BZXC  
CY7C1426JV18-250BZXC  
CY7C1413JV18-250BZXC  
CY7C1415JV18-250BZXC  
CY7C1411JV18-250BZI  
CY7C1426JV18-250BZI  
CY7C1413JV18-250BZI  
CY7C1415JV18-250BZI  
CY7C1411JV18-250BZXI  
CY7C1426JV18-250BZXI  
CY7C1413JV18-250BZXI  
CY7C1415JV18-250BZXI  
51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)  
51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free  
51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)  
51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free  
51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)  
51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free  
51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)  
51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free  
Commercial  
Industrial  
Commercial  
Industrial  
Document Number: 001-12557 Rev. *C  
Page 25 of 28  
CY7C1411JV18, CY7C1426JV18  
CY7C1413JV18, CY7C1415JV18  
Ordering Information (continued)  
Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or  
visit www.cypress.com for actual products offered.  
Speed  
(MHz)  
Package  
Diagram  
Operating  
Range  
Ordering Code  
Package Type  
200 CY7C1411JV18-200BZC  
CY7C1426JV18-200BZC  
CY7C1413JV18-200BZC  
CY7C1415JV18-200BZC  
CY7C1411JV18-200BZXC  
CY7C1426JV18-200BZXC  
CY7C1413JV18-200BZXC  
CY7C1415JV18-200BZXC  
CY7C1411JV18-200BZI  
CY7C1426JV18-200BZI  
CY7C1413JV18-200BZI  
CY7C1415JV18-200BZI  
CY7C1411JV18-200BZXI  
CY7C1426JV18-200BZXI  
CY7C1413JV18-200BZXI  
CY7C1415JV18-200BZXI  
51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)  
51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free  
51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)  
51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free  
Commercial  
Industrial  
Document Number: 001-12557 Rev. *C  
Page 26 of 28  
CY7C1411JV18, CY7C1426JV18  
CY7C1413JV18, CY7C1415JV18  
Package Diagram  
Figure 6. 165-Ball FBGA (15 x 17 x 1.40 mm), 51-85195  
"/44/- 6)%7  
4/0 6)%7  
0). ꢀ #/2.%2  
Œꢃꢂꢃꢄ - #  
Œꢃꢂꢇꢄ - # ! "  
ꢌꢃꢂꢀꢈ  
0). ꢀ #/2.%2  
Œꢃꢂꢄꢃ  
ꢅꢀꢆꢄ8  
ꢍꢃꢂꢃꢆ  
ꢀꢃ  
ꢀꢀ  
ꢀꢀ ꢀꢃ  
!
"
!
"
#
$
#
$
%
%
&
&
'
'
(
*
(
*
+
+
,
,
-
-
.
0
2
.
0
2
!
ꢀꢂꢃꢃ  
ꢄꢂꢃꢃ  
ꢀꢃꢂꢃꢃ  
"
ꢀꢄꢂꢃꢃ¼ꢃꢂꢀꢃ  
ꢃꢂꢀꢄꢅꢈ8  
./4%3 ꢎ  
3/,$%2 0!$ 490% ./. 3/,$%2 -!3+ $%&).%$ ꢅ.3-$  
0!#+!'% 7%)'(4 ꢂꢆꢄG  
*%$%# 2%&%2%.#% -/ꢍꢇꢀꢆ ꢏ $%3)'. ꢈꢂꢆ#  
0!#+!'% #/$% ""ꢃ!$  
3%!4).' 0,!.%  
#
51-85195-*A  
Document Number: 001-12557 Rev. *C  
Page 27 of 28  
CY7C1411JV18, CY7C1426JV18  
CY7C1413JV18, CY7C1415JV18  
Document History Page  
Document Title: CY7C1411JV18/CY7C1426JV18/CY7C1413JV18/CY7C1415JV18, 36-Mbit QDR™-II SRAM 4-Word  
Burst Architecture  
Document Number: 001-12557  
ISSUE  
DATE  
ORIG. OF  
CHANGE  
REV. ECN NO.  
DESCRIPTION OF CHANGE  
**  
808457 See ECN  
VKN  
New data sheet  
*A  
1462587 See ECN VKN/AESA Converted from preliminary to final  
Removed 250 MHz and 200 MHz speed bins  
Updated I /I specs  
DD SB  
Changed DLL minimum operating frequency from 80MHz to 120MHz  
Changed t  
max spec to 8.4ns  
CYC  
*B  
*C  
2189567 See ECN VKN/AESA Minor Change-Moved to the external web  
2521072 06/25/08 NXR/PYRS Updated Logic Block diagrams  
Updated power up sequence waveform and its description  
Changed Ambient Temperature with Power Applied from “–10°C to +85°C” to “–55°C  
to +125°C” in the “Maximum Ratings “ on page 20  
Added footnote #21 related to I  
DD  
Added 250 MHz and 200 MHz speed bin  
Changed JTAG ID code [31:29] form 001 to 000  
Sales, Solutions, and Legal Information  
Worldwide Sales and Design Support  
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office  
closest to you, visit us at cypress.com/sales.  
Products  
PSoC  
PSoC Solutions  
General  
Clocks & Buffers  
Wireless  
Low Power/Low Voltage  
Precision Analog  
LCD Drive  
Memories  
Image Sensors  
CAN 2.0b  
USB  
© Cypress Semiconductor Corporation, 2007-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used  
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use  
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support  
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),  
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,  
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress  
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without  
the express written permission of Cypress.  
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES  
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not  
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where  
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer  
assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Use may be limited by and subject to the applicable Cypress software license agreement.  
Document Number: 001-12557 Rev. *C  
Revised June 25, 2008  
Page 28 of 28  
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document  
are the trademarks of their respective holders.  

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