CY7C1339G
4-Mbit (128K x 32) Pipelined Sync SRAM
Features
Functional Description[1]
• Registered inputs and outputs for pipelined operation
• 128K × 32 common I/O architecture
The CY7C1339G SRAM integrates 128K x 32 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
• 3.3V core power supply (V
)
DD
• 2.5V/3.3V I/O power supply (V
• Fast clock-to-output times
)
DDQ
(CE ), depth-expansion Chip Enables (CE and CE ), Burst
1
2
3
— 2.6 ns (for 250-MHz device)
Control inputs (ADSC, ADSP,
ADV), Write Enables
). Asynchronous
GW
and
(BW
, and BWE), and Global Write (
[A:D]
• Provide high-performance 3-1-1-1 access rate
inputs include the Output Enable (OE) and the ZZ pin.
®
• User-selectable burst counter supporting Intel
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
®
Pentium interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to four bytes wide as
controlled by the byte write control inputs. GW when active
• Available in lead-free 100-Pin TQFP package, lead-free
and non-lead-free 119-Ball BGA package
• “ZZ” Sleep Mode Option
causes all bytes to be written.
LOW
The CY7C1339G operates from a +3.3V core power supply
while all outputs may operate with either a +2.5 or +3.3V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Logic Block Diagram
A0, A1,
A
ADDRESS
REGISTER
2
A
[1:0]
Q1
MODE
ADV
CLK
BURST
COUNTER
CLR AND Q0
LOGIC
ADSC
ADSP
DQD
BYTE
DQD
BYTE
BW
D
W RITE REGISTER
W RITE DRIVER
DQC
BYTE
DQC
BYTE
BW
C
OUTPUT
BUFFERS
W RITE DRIVER
OUTPUT
REGISTERS
W RITE REGISTER
MEMORY
ARRAY
SENSE
AMPS
D Q s
DQB
BYTE
W RITE DRIVER
E
DQB
BYTE
W RITE REGISTER
BW
BW
B
DQA
BYTE
W RITE DRIVER
DQA
BYTE
W RITE REGISTER
A
BW E
INPUT
REGISTERS
GW
ENABLE
REGISTER
PIPELINED
ENABLE
CE1
CE2
CE3
OE
SLEEP
CONTROL
ZZ
1
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05520 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 5, 2006
CY7C1339G
Pin Configurations (continued)
119-Ball BGA Pinout
1
2
A
3
A
A
A
4
5
A
A
A
6
7
A
V
A
V
DDQ
ADSP
ADSC
DDQ
NC/288M
NC/144M
CE
A
NC/9M NC/576M
B
C
2
V
A
NC/1G
DD
DQ
NC
V
NC
CE
V
NC
DQ
D
E
F
C
SS
SS
SS
SS
SS
SS
B
DQ
DQ
DQ
DQ
DQ
V
V
V
V
V
DQ
DQ
DQ
DQ
V
DQ
B
C
C
C
C
C
1
B
B
B
B
V
OE
ADV
GW
V
DDQ
DDQ
G
H
J
DQ
BW
V
BW
V
DQ
C
C
c
B
B
B
DQ
DQ
SS
SS
V
NC
V
NC
V
DDQ
DDQ
DD
DD
DD
K
DQ
DQ
V
CLK
NC
V
DQ
DQ
D
D
SS
SS
A
A
L
M
N
DQ
DQ
DQ
DQ
BW
V
BW
DQ
DQ
DQ
DQ
D
D
D
D
D
A
A
A
A
A
V
V
V
V
DDQ
BWE
A1
DDQ
SS
SS
DQ
V
DQ
D
SS
SS
A
P
R
T
DQ
NC
A
V
A0
V
NC
A
DQ
D
SS
SS
A
NC
NC
MODE
A
V
NC
A
NC
ZZ
DD
NC/72M
NC
A
NC/36M
NC
V
NC
NC
NC
V
DDQ
U
DDQ
Pin Definitions
Name
I/O
Description
A , A , A
Input-
Address Inputs used to select one of the 128K address locations. Sampled at the rising edge
0
1
Synchronous of the CLK if ADSP or ADSC is active LOW, and CE , CE , and CE are sampled active. A1, A0
1
2
3
are fed to the two-bit counter.
.
BW , BW
Input-
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.
A
B
BW , BW
Synchronous Sampled on the rising edge of CLK.
C
D
GW
Input-
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global
Synchronous write is conducted (ALL bytes are written, regardless of the values on BW
and BWE).
[A:D]
BWE
CLK
Input-
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be
Synchronous asserted LOW to conduct a byte write.
Input-
Clock
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the
burst counter when ADV is asserted LOW, during a burst operation.
CE
CE
CE
Input-
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
1
2
3
Synchronous CE and CE to select/deselect the device. ADSP is ignored if CE is HIGH. CE
is sampled only
2
3
1
1
when a new external address is loaded.
Input-
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE and CE to select/deselect the device.CE
is sampled only when a new external address is
1
3
2
loaded.
Input-
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE and CE to select/deselect the device. CE is sampled only when a new external address is
1
2
3
loaded. Not connected for BGA. Where referenced, CE is assumed active throughout this
3
document for BGA.
OE
Input-
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When
Asynchronous LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as
input data pins. OE is masked during the first clock of a read cycle when emerging from a
deselected state.
Document #: 38-05520 Rev. *F
Page 3 of 18
CY7C1339G
Pin Definitions (continued)
Name
ADV
I/O
Description
Advance Input signal, sampled on the rising edge of CLK, active LOW. When asserted, it
Input-
Synchronous automatically increments the address in a burst cycle.
ADSP
Input- Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When
Synchronous asserted LOW, addresses presented to the device are captured in the address registers. A1, A0
are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is
recognized. ASDP is ignored when CE is deasserted HIGH.
1
ADSC
Input-
Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When
Synchronous asserted LOW, addresses presented to the device are captured in the address registers. A1, A0
are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is
recognized.
ZZ
Input-
ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a non-time-critical
Asynchronous “sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW or
left floating. ZZ pin has an internal pull-down.
I/O-
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered
DQs
Synchronous by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by the addresses presented during the previous clock rise of the read cycle. The direction
of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When
HIGH, DQs are placed in a tri-state condition.
V
V
V
Power Supply Power supply inputs to the core of the device.
DD
Ground
Ground for the core of the device.
SS
I/O Power
Supply
Power supply for the I/O circuitry.
DDQ
V
I/O Ground
Ground for the I/O circuitry.
SSQ
MODE
Input-
Static
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to V or left
floating selects interleaved burst sequence. This is a strap pin and should remain static during
device operation. Mode Pin has an internal pull-up.
DD
NC,NC/9M,
NC/18M.
NC/72M,
NC/144M,
NC/288M,
NC/576M,
NC/1G
–
No Connects. Not internally connected to the die. NC/9M, NC/18M, NC/72M, NC/144M,
NC/288M, NC/576M and NC/1G are address expansion pins are not internally connected to the
die.
all four bytes. All writes are simplified with on-chip
synchronous self-timed Write circuitry.
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise (t ) is 2.6 ns
(250-MHz device).
Three synchronous Chip Selects (CE , CE , CE ) and an
1
2
3
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. ADSP is ignored if CE
is HIGH.
1
CO
Single Read Accesses
The CY7C1339G supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium and i486™
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is user
selectable, and is determined by sampling the MODE input.
Accesses can be initiated with either the Processor Address
Strobe (ADSP) or the Controller Address Strobe (ADSC).
Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
CE , CE , CE are all asserted active, and (3) the Write
1
2
3
signals (GW, BWE) are all deserted HIGH. ADSP is ignored if
CE is HIGH. The address presented to the address inputs (A)
1
is stored into the address advancement logic and the Address
Register while being presented to the memory array. The
corresponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within 2.6 ns (250-MHz device) if OE is active
LOW. The only exception occurs when the SRAM is emerging
from a deselected state to a selected state, its outputs are
always tri-stated during the first cycle of the access. After the
first cycle of the access, the outputs are controlled by the OE
Byte Write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW
) inputs. A Global Write
[A:D]
Enable (GW) overrides all Byte Write inputs and writes data to
Document #: 38-05520 Rev. *F
Page 4 of 18
CY7C1339G
signal. Consecutive single Read cycles are supported. Once
the SRAM is deselected at clock rise by the chip select and
either ADSP or ADSC signals, its output will tri-state immedi-
ately.
to the DQs inputs. Doing so will tri-state the output drivers. As
a safety precaution, DQs are automatically tri-stated whenever
a Write cycle is detected, regardless of the state of OE.
Burst Sequences
Single Write Accesses Initiated by ADSP
The CY7C1339G provides a two-bit wraparound counter, fed
by A1, A0, that implements either an interleaved or linear burst
sequence. The interleaved burst sequence is designed specif-
ically to support Intel Pentium applications. The linear burst
sequence is designed to support processors that follow a
linear burst sequence. The burst sequence is user selectable
through the MODE input.
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and
(2) CE , CE , CE are all asserted active. The address
1
2
3
presented to A is loaded into the address register and the
address advancement logic while being delivered to the
memory array. The Write signals (GW, BWE, and BW
) and
[A:D]
ADV inputs are ignored during this first cycle.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both Read and Write burst operations are supported.
ADSP-triggered Write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQs inputs is written into the corre-
sponding address location in the memory array. If GW is HIGH,
Sleep Mode
then the Write operation is controlled by BWE and BW
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
[A:D]
signals. The CY7C1339G provides Byte Write capability that
is described in the Write Cycle Descriptions table. Asserting
the Byte Write Enable input (BWE) with the selected Byte
Write (BW
) input, will selectively write to only the desired
[A:D]
bytes. Bytes not selected during a Byte Write operation will
remain unaltered. A synchronous self-timed Write mechanism
has been provided to simplify the Write operations.
the “sleep” mode. CE , CE , CE , ADSP, and ADSC must
1
2
3
remain inactive for the duration of t
returns LOW.
after the ZZ input
Because the CY7C1339G is a common I/O device, the Output
Enable (OE) must be deserted HIGH before presenting data
to the DQs inputs. Doing so will tri-state the output drivers. As
a safety precaution, DQs are automatically tri-stated whenever
a Write cycle is detected, regardless of the state of OE.
ZZREC
Interleaved Burst Address Table
(MODE = Floating or VDD
)
First
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
Single Write Accesses Initiated by ADSC
Address
A1, A0
ADSC Write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
deserted HIGH, (3) CE , CE , CE are all asserted active, and
1
2
3
(4) the appropriate combination of the Write inputs (GW, BWE,
and BW ) are asserted active to conduct a Write to the
[A:D]
desired byte(s). ADSC-triggered Write accesses require a
single clock cycle to complete. The address presented to A is
loaded into the address register and the address
advancement logic while being delivered to the memory array.
The ADV input is ignored during this cycle. If a global Write is
conducted, the data presented to the DQs is written into the
corresponding address location in the memory core. If a Byte
Write is conducted, only the selected bytes are written. Bytes
not selected during a Byte Write operation will remain
unaltered. A synchronous self-timed Write mechanism has
been provided to simplify the Write operations.
Linear Burst Address Table (MODE = GND)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Because the CY7C1339G is a common I/O device, the Output
Enable (OE) must be deserted HIGH before presenting data
ZZ Mode Electrical Characteristics
Parameter
Description
Snooze mode standby current
Device operation to ZZ
Test Conditions
ZZ > V – 0.2V
Min.
Max.
40
Unit
mA
ns
I
t
t
t
t
DDZZ
DD
ZZ > V – 0.2V
2t
ZZS
DD
CYC
ZZ recovery time
ZZ < 0.2V
2t
ns
ZZREC
ZZI
CYC
ZZ active to snooze current
ZZ Inactive to exit snooze current
This parameter is sampled
This parameter is sampled
2t
ns
CYC
0
ns
RZZI
Document #: 38-05520 Rev. *F
Page 5 of 18
CY7C1339G
Truth Table [2, 3, 4, 5, 6, 7]
Operation
Add. Used CE CE CE
3
ADSP ADSC ADV WRITE OE CLK
DQ
Tri-State
Tri-State
Tri-State
Tri-State
Tri-State
Tri-State
Q
ZZ
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
1
2
Deselect Cycle, Power-down
Deselect Cycle, Power-down
Deselect Cycle, Power-down
Deselect Cycle, Power-down
Deselect Cycle, Power-down
Snooze Mode, Power-down
READ Cycle, Begin Burst
READ Cycle, Begin Burst
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
None
None
H
L
X
L
X
X
H
X
H
X
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
L-H
L-H
L-H
L-H
L-H
X
None
L
X
L
L
None
L
H
H
X
L
None
L
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
None
X
L
X
X
X
L
External
External
External
External
External
Next
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L
L
L
H
X
L
Tri-State
D
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L
L
L
H
H
H
H
H
H
L
Q
L
L
L
H
L
Tri-State
Q
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Next
L
H
L
Tri-State
Q
Next
L
Next
L
H
X
X
L
Tri-State
D
Next
L
Next
L
L
D
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
L
Q
H
L
Tri-State
Q
H
X
X
Tri-State
D
L
D
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write enable signals (BW , BW , BW , BW ) and BWE = L or GW= L. WRITE = H when all Byte write enable signals
A
B
C
D
(BW , BW , BW , BW ), BWE, GW = H.
A
B
C
D
4. The DQ pins are controlled by the current cycle and the
signal.
is asynchronous and is not sampled with the clock.
OE
OE
5. CE , CE , and CE are available only in the TQFP package. BGA package has only 2 chip selects CE and CE .
1
2
3
1
2
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
. Writes may occur only on subsequent clocks
[A: D]
after the ADSP or with the assertion of ADSC. As a result,
don't care for the remainder of the write cycle.
must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a
OE
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document #: 38-05520 Rev. *F
Page 6 of 18
CY7C1339G
Partial Truth Table for Read/Write [2, 8]
Function
GW
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
BWE
H
L
BW
X
H
H
H
H
H
H
H
H
L
BW
X
H
H
H
H
L
BW
X
H
H
L
BW
A
D
C
B
Read
Read
X
H
L
Write Byte A – DQ
L
A
Write Byte B – DQ
Write Bytes B, A
L
H
L
B
L
L
Write Byte C– DQ
Write Bytes C, A
Write Bytes C, B
L
H
H
L
H
L
C
L
L
L
L
H
L
Write Bytes C, B, A
L
L
L
Write Byte D– DQ
Write Bytes D, A
Write Bytes D, B
L
H
H
H
H
L
H
H
L
H
L
D
L
L
L
L
H
L
Write Bytes D, B, A
Write Bytes D, C
Write Bytes D, C, A
Write Bytes D, C, B
Write All Bytes
L
L
L
L
L
H
H
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
Write All Bytes
X
X
X
X
X
Note:
8.Table only lists a partial listing of the byte write combinations. Any combination of BW is valid. Appropriate write will be done based on which byte write is active.
X
Document #: 38-05520 Rev. *F
Page 7 of 18
CY7C1339G
DC Input Voltage ................................... –0.5V to V + 0.5V
Maximum Ratings
DD
Current into Outputs (LOW)......................................... 20 mA
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Storage Temperature .................................–65°C to +150°C
Latch-up Current.................................................... > 200 mA
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Supply Voltage on V Relative to GND........ –0.5V to +4.6V
Ambient
DD
Range
Commercial
Industrial
Temperature
V
V
DDQ
DD
Supply Voltage on V
Relative to GND ......–0.5V to +V
DD
DDQ
0°C to +70°C
3.3V
–5%/+10%
2.5V –5%
DC Voltage Applied to Outputs
in tri-state ............................................ –0.5V to V
to V
DD
+ 0.5V
–40°C to +85°C
–40°C to +125°C
DDQ
Automotive
[9, 10]
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
Min.
3.135
2.375
2.4
Max.
3.6
Unit
V
V
V
V
Power Supply Voltage
I/O Supply Voltage
Output HIGH Voltage
DD
V
V
DDQ
OH
DD
for 3.3V I/O, I = –4.0 mA
V
OH
for 2.5V I/O, I = –1.0 mA
2.0
V
OH
V
V
V
I
Output LOW Voltage
for 3.3V I/O, I = 8.0 mA
0.4
0.4
V
OL
IH
IL
OL
for 2.5V I/O, I = 1.0 mA
V
OL
[9]
Input HIGH Voltage
for 3.3V I/O
for 2.5V I/O
for 3.3V I/O
for 2.5V I/O
2.0
1.7
V
V
+ 0.3V
+ 0.3V
V
DD
DD
V
[9]
Input LOW Voltage
–0.3
–0.3
–5
0.8
V
0.7
5
V
Input Leakage Current GND ≤ V ≤ V
except ZZ and MODE
µA
X
I
DDQ
Input Current of MODE Input = V
–30
–5
µA
µA
SS
Input = V
5
DD
Input Current of ZZ
Input = V
Input = V
µA
SS
DD
30
5
µA
I
I
Output Leakage Current GND ≤ V ≤ V
Output Disabled
–5
µA
OZ
I
DDQ,
V
Operating Supply
V
f = f
= Max., I
= 0 mA,
4-ns cycle, 250 MHz
5-ns cycle, 200 MHz
6-ns cycle, 166 MHz
7.5-ns cycle, 133 MHz
4-ns cycle, 250 MHz
5-ns cycle, 200 MHz
6-ns cycle, 166 MHz
325
265
240
225
120
110
100
90
mA
mA
mA
mA
mA
mA
mA
mA
DD
DD
DD
OUT
= 1/t
MAX CYC
Current
I
Automatic CE
Power-down
Current—TTL Inputs
V = Max, Device Deselected,
DD
SB1
V
≥ V or V ≤ V
IN
IH
IN
IL
f = f
= 1/t
MAX CYC
Industrial/ 7.5-ns cycle, 133 MHz
Commercial
Automotive 7.5-ns cycle, 133 MHz
115
40
mA
mA
I
Automatic CE
Power-down
Current—CMOS Inputs f = 0
V
= Max, Device Deselected,
DD
All speeds
SB2
V
≤ 0.3V or V > V – 0.3V,
IN
IN
DDQ
Notes:
9. Overshoot: V (AC) < V +1.5V (Pulse width less than t
/2), undershoot: V (AC) > –2V (Pulse width less than t /2).
CYC
IH
DD
CYC
IL
10. TPower-up: Assumes a linear ramp from 0V to V (min.) within 200 ms. During this time V < V and V
< V
.
DD
IH
DD
DDQ
DD
Document #: 38-05520 Rev. *F
Page 8 of 18
CY7C1339G
[9, 10]
Electrical Characteristics Over the Operating Range
(continued)
Parameter
Description
Automatic CE
Power-down
Test Conditions
Min.
Max.
105
95
Unit
mA
mA
mA
mA
mA
I
V
= Max, Device Deselected, or 4-ns cycle, 250 MHz
DD
SB3
V
≤ 0.3V or V > V
– 0.3V
IN
IN
DDQ
5-ns cycle, 200 MHz
6-ns cycle, 166 MHz
7.5-ns cycle, 133 MHz
All Speeds
Current—CMOS Inputs f = f
= 1/t
MAX
CYC
85
75
I
Automatic CE
Power-down
Current—TTL Inputs
V
V
= Max, Device Deselected,
45
SB4
DD
≥ V or V ≤ V , f = 0
IN
IH IN IL
Capacitance[11]
TQFP
BGA
Parameter
Description
Test Conditions
Package
Package
Unit
pF
C
Input Capacitance
T = 25°C, f = 1 MHz,
5
5
5
5
5
7
IN
A
V
= 3.3V.
DD
C
C
Clock Input Capacitance
Input/Output Capacitance
pF
CLK
I/O
V
= 3.3V
DDQ
pF
Thermal Resistance[11]
TQFP
Package
BGA
Package
Parameter
Description
Test Conditions
Unit
ΘJA
Thermal Resistance
(Junction to Ambient)
Test conditions follow standard test
methods and procedures for
measuring thermal impedance, per
EIA/JESD51
30.32
6.85
34.1
14.0
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
°C/W
AC Test Loads and Waveforms
3.3V I/O Test Load
R = 317Ω
3.3V
OUTPUT
ALL INPUT PULSES
90%
VDDQ
OUTPUT
90%
10%
Z = 50Ω
0
10%
R = 50Ω
L
GND
5 pF
INCLUDING
R = 351Ω
≤ 1 ns
≤ 1 ns
V = 1.5V
T
JIG AND
SCOPE
(c)
(a)
(b)
2.5V I/O Test Load
R = 1667Ω
2.5V
OUTPUT
R = 50Ω
OUTPUT
ALL INPUT PULSES
90%
VDDQ
GND
90%
10%
Z = 50Ω
0
10%
L
5 pF
R = 1538Ω
≤ 1 ns
≤ 1 ns
V = 1.25V
T
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
Note:
11. Tested initially and after any design or process change that may affect these parameters.
Document #: 38-05520 Rev. *F
Page 9 of 18
CY7C1339G
[12, 13, 14, 15, 16, 17]
Switching Characteristics Over the Operating Range
–250
–200
–166
–133
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Unit
[12]
t
V
(Typical) to the first Access
1
1
1
1
ms
POWER
DD
Clock
t
t
t
Clock Cycle Time
Clock HIGH
4.0
1.7
1.7
5.0
2.0
2.0
6.0
2.5
2.5
7.5
3.0
3.0
ns
ns
ns
CYC
CH
Clock LOW
CL
Output Times
t
t
t
t
t
t
t
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
2.6
2.8
3.5
4.0
ns
ns
ns
ns
ns
ns
ns
CO
1.0
0
1.0
0
1.5
0
1.5
0
DOH
CLZ
[13, 14, 15]
Clock to Low-Z
[13, 14, 15]
Clock to High-Z
2.6
2.6
2.8
2.8
3.5
3.5
4.0
4.0
CHZ
OEV
OELZ
OEHZ
OE LOW to Output Valid
[13, 14, 15]
OE LOW to Output Low-Z
0
0
0
0
[13, 14, 15]
OE HIGH to Output High-Z
2.6
2.8
3.5
4.0
Set-up Times
t
t
t
t
t
t
Address Set-up Before CLK Rise
ADSC, ADSP Set-up Before CLK Rise
ADV Set-up Before CLK Rise
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
ns
AS
ADS
ADVS
WES
DS
GW, BWE, BW Set-up Before CLK Rise
X
Data Input Set-up Before CLK Rise
Chip Enable Set-Up Before CLK Rise
CES
Hold Times
t
t
t
t
t
t
Address Hold After CLK Rise
ADSP, ADSC Hold After CLK Rise
ADV Hold After CLK Rise
0.3
0.3
0.3
0.3
0.3
0.3
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
AH
ADH
ADVH
WEH
DH
GW, BWE, BW Hold After CLK Rise
X
Data Input Hold After CLK Rise
Chip Enable Hold After CLK Rise
CEH
Notes:
12. This part has a voltage regulator internally; t
is the time that the power needs to be supplied above V (minimum) initially before a read or write operation
DD
POWER
can be initiated.
13. t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
CHZ CLZ OELZ
OEHZ
14. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
CLZ
OEHZ
OELZ
CHZ
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
15. This parameter is sampled and not 100% tested.
16. Timing reference level is 1.5V when V
= 3.3V and is 1.25V when V
= 2.5V.
DDQ
DDQ
17. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05520 Rev. *F
Page 10 of 18
CY7C1339G
Switching Waveforms
[18]
Read Cycle Timing
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
ADH
ADS
t
t
AH
AS
A1
A2
A3
ADDRESS
Burst continued with
new base address
t
t
WEH
WES
GW, BWE,
BW[A:D]
Deselect
cycle
t
t
CEH
CES
CE
t
t
ADVH
ADVS
ADV
OE
ADV
suspends
burst.
t
t
OEV
CO
t
t
OEHZ
t
t
CHZ
OELZ
DOH
t
CLZ
t
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A1)
Data Out (Q)
High-Z
CO
Burst wraps around
to its initial state
Single READ
BURST READ
DON’T CARE
UNDEFINED
Note:
18. On this diagram, when CE is LOW, CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH, CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
Document #: 38-05520 Rev. *F
Page 11 of 18
CY7C1339G
Switching Waveforms (continued)
[18, 19]
Write Cycle Timing
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC extends burst
t
t
ADH
ADS
t
t
ADH
ADS
ADSC
t
t
AH
AS
A1
A2
A3
ADDRESS
Byte write signals are
ignored for first cycle when
ADSP initiates burst
t
t
WEH
WES
BWE,
BW[A :D]
t
t
WEH
WES
GW
CE
t
t
CEH
CES
t
t
ADVH
ADVS
ADV
OE
ADV suspends burst
t
t
DH
DS
Data In (D)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
D(A1)
High-Z
t
OEHZ
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
Extended BURST WRITE
DON’T CARE
UNDEFINED
Note:
19.
Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW
LOW.
[A:D]
Document #: 38-05520 Rev. *F
Page 12 of 18
CY7C1339G
Switching Waveforms (continued)
[18, 20, 21]
Read/Write Cycle Timing
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
AH
AS
A1
A2
A3
A4
A5
A6
ADDRESS
t
t
WEH
WES
BWE,
BW[A:D]
t
t
CEH
CES
CE
ADV
OE
t
t
DH
t
CO
DS
t
OELZ
Data In (D)
High-Z
High-Z
D(A3)
D(A5)
D(A6)
t
t
OEHZ
CLZ
Data Out (Q)
Q(A1)
Q(A2)
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
Back-to-Back READs
Single WRITE
BURST READ
Back-to-Back
WRITEs
DON’T CARE
UNDEFINED
Notes:
20. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.
21.
GW is HIGH.
Document #: 38-05520 Rev. *F
Page 13 of 18
CY7C1339G
Switching Waveforms (continued)
[22, 23]
ZZ Mode Timing
CLK
t
t
ZZ
ZZREC
ZZ
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes:
22. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
23. DQs are in high-Z when exiting ZZ sleep mode.
Document #: 38-05520 Rev. *F
Page 14 of 18
CY7C1339G
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
Speed
(MHz)
Package
Diagram
Operating
Range
Ordering Code
CY7C1339G-133AXC
CY7C1339G-133BGC
CY7C1339G-133BGXC
CY7C1339G-133AXI
CY7C1339G-133BGI
CY7C1339G-133BGXI
CY7C1339G-133AXE
CY7C1339G-166AXC
CY7C1339G-166BGC
CY7C1339G-166BGXC
CY7C1339G-166AXI
CY7C1339G-166BGI
CY7C1339G-166BGXI
CY7C1339G-200AXC
CY7C1339G-200BGC
CY7C1339G-200BGXC
CY7C1339G-200AXI
CY7C1339G-200BGI
CY7C1339G-200BGXI
CY7C1339G-250AXC
CY7C1339G-250BGC
CY7C1339G-250BGXC
CY7C1339G-250AXI
CY7C1339G-250BGI
CY7C1339G-250BGXI
Package Type
133
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
Industrial
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Automotive
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
166
200
250
119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
Industrial
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
Industrial
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
Industrial
Document #: 38-05520 Rev. *F
Page 15 of 18
CY7C1339G
Package Diagrams
100-Pin TQFP (14 x 20 x 1.4 mm) (51-85050)
16.00 0.20
1.40 0.05
14.00 0.10
100
81
80
1
0.30 0.08
0.65
TYP.
12° 1°
(8X)
SEE DETAIL
A
30
51
31
50
0.20 MAX.
1.60 MAX.
R 0.08 MIN.
0.20 MAX.
0° MIN.
SEATING PLANE
STAND-OFF
0.05 MIN.
0.15 MAX.
NOTE:
0.25
1. JEDEC STD REF MS-026
GAUGE PLANE
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
R 0.08 MIN.
0.20 MAX.
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
0°-7°
0.60 0.15
0.20 MIN.
51-85050-*B
1.00 REF.
DETAIL
A
Document #: 38-05520 Rev. *F
Page 16 of 18
CY7C1339G
Package Diagrams (continued)
119-Ball BGA (14 x 22 x 2.4 mm) (51-85115)
Ø0.05 M C
Ø0.25 M C A B
A1 CORNER
Ø0.75 0.15(119X)
Ø1.00(3X) REF.
1
2
3
4
5
6
7
7
6
5
4
3
2
1
A
B
C
D
E
A
B
C
D
E
F
F
G
H
G
H
J
K
L
J
K
L
M
N
P
R
T
M
N
P
R
T
U
U
1.27
0.70 REF.
A
3.81
12.00
7.62
B
14.00 0.20
0.15(4X)
30° TYP.
51-85115-*B
SEATING PLANE
C
All products and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05520 Rev. *F
Page 17 of 18
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C1339G
Document History Page
Document Title: CY7C1339G 4-Mbit (128K x 32) Pipelined Sync SRAM
Document Number: 38-05520
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
224368
288909
See ECN
See ECN
RKF
VBL
New data sheet
*A
In Ordering Info section, Changed TQFP to PB-free TQFP
Added PB-free BG package
*B
332895
See ECN
SYT
Modified Address Expansion balls in the pinouts for 100 TQFP and 119 BGA
Package as per JEDEC standards and updated the Pin Definitions accordingly
Modified V
V
test conditions
OL, OH
Replaced TBDs for Θ and Θ to their respective values on the Thermal Resis-
JA
JC
tance table
Updated the Ordering Information by shading and unshading MPNs as per
availability
*C
*D
351194
366728
See ECN
See ECN
PCI
PCI
Updated Ordering Information Table
Added V /V
test conditions in DC Table
DD DDQ
Modified test condition in note# 10 from V < V to V
V
DD
<
IH
DD
IH
*E
420883
See ECN
RXU
Converted from Preliminary to Final
Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901
North First Street” to “198 Champion Court”
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the
Electrical Characteristics Table
Replaced Package Name column with Package Diagram in the Ordering Infor-
mation table
Replaced Package Diagram of 51-85050 from *A to *B
Added Automotive Range in Operating Range Table
Updated the Ordering Information
*F
480368
See ECN
VKN
Added the Maximum Rating for Supply Voltage on V
Updated the Ordering Information table.
Relative to GND.
DDQ
Document #: 38-05520 Rev. *F
Page 18 of 18
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