Cypress CY7C1303BV25 User Manual

CY7C1303BV25

CY7C1306BV25

18-Mbit Burst of 2 Pipelined SRAM with

QDR™ Architecture

Features

Functional Description

• Separate independent Read and Write data ports

— Supports concurrent transactions

• 167-MHz Clock for high bandwidth

— 2.5 ns Clock-to-Valid access time

• 2-Word Burst on all accesses

The CY7C1303BV25 and CY7C1306BV25 are 2.5V

Synchronous Pipelined SRAMs equipped with QDR™ archi-

tecture. QDR architecture consists of two separate ports to

access the memory array. The Read port has dedicated Data

Outputs to support Read operations and the Write Port has

dedicated Data inputs to support Write operations. Access to

each port is accomplished through a common address bus.

The Read address is latched on the rising edge of the K clock

and the Write address is latched on the rising edge of K clock.

QDR has separate data inputs and data outputs to completely

eliminate the need to “turn-around” the data bus required with

common I/O devices. Accesses to the CY7C1303BV25/

CY7C1306BV25 Read and Write ports are completely

independent of one another. All accesses are initiated

synchronously on the rising edge of the positive input clock

(K). In order to maximize data throughput, both Read and

Write ports are equipped with Double Data Rate (DDR) inter-

faces. Therefore, data can be transferred into the device on

every rising edge of both input clocks (K and K) and out of the

device on every rising edge of the output clock (C and C, or K

and K when in single clock mode) thereby maximizing perfor-

mance while simplifying system design. Each address location

is associated with two 18-bit words (CY7C1303BV25) or two

36-bit words (CY7C1306BV25) that burst sequentially into or

out of the device.

• Double Data Rate (DDR) interfaces on both Read and

Write Ports (data transferred at 333 MHz) @167 MHz

• Two input clocks (K and K) for precise DDR timing

— SRAM uses rising edges only

• Two input clocks for output data (C and C) to minimize

clock-skew and flight-time mismatches.

• Single multiplexed address input bus latches address

inputs for both Read and Write ports

• Separate Port Selects for depth expansion

• Synchronous internally self-timed writes

• 2.5V core power supply with HSTL Inputs and Outputs

• Available in 165-ball FBGA package (13 x 15 x 1.4 mm)

• Variable drive HSTL output buffers

• Expanded HSTL output voltage (1.4V–1.9V)

• JTAG Interface

Depth expansion is accomplished with a Port Select input for

each port. Each Port Selects allow each port to operate

independently.

• Variable Impedance HSTL

Configurations

All synchronous inputs pass through input registers controlled

by the K or K input clocks. All data outputs pass through output

registers controlled by the C or C input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

CY7C1303BV25 – 1M x 18

CY7C1306BV25 – 512K x 36

Cypress Semiconductor Corporation

Document #: 38-05627 Rev. *A

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised April 3, 2006

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CY7C1303BV25

CY7C1306BV25

Pin Configuration

165-ball FBGA (13 x 15 x 1.4 mm) Pinout

CY7C1303BV25 (1M x 18)

BWS

Gnd/ 72M

TDI

TDO

Gnd/ 144M NC/ 36M

WPS

RPS

D10

Q10

Q11

D12

Q13

VDDQ

D14

Q14

D15

D16

Q16

Q17

VDDQ

VSS

VDDQ

VSS

VDDQ

VSS

D11

VSS

VDD

VSS

VDD

VSS

Q12

D13

VREF

Q15

D17

TCK

TMS

CY7C1306BV25 (512K x 36)

BWS

TDI

Gnd/ 288M NC/72M

WPS

RPS

NC/36M Gnd/ 144M

Q27

D27

D28

Q29

Q30

D30

Q18

Q28

D20

D29

Q21

D22

VREF

Q31

D32

Q24

Q34

D26

D35

TCK

D18

D19

Q19

Q20

D21

Q22

VDDQ

D23

Q23

D24

D25

Q25

Q26

D17

D16

Q16

Q15

D14

Q13

VDDQ

D12

Q12

D11

D10

Q10

Q17

VSS

VDDQ

VSS

VDDQ

VSS

VDD

VSS

VDD

VSS

D15

Q14

D13

VREF

D31

Q32

Q33

D33

D34

Q35

TDO

Q11

TMS

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CY7C1303BV25

CY7C1306BV25

Pin Definitions

Name

I/O

Description

Data input signals, sampled on the rising edge of K and K clocks during valid write opera-

Input-

[x:0]

Synchronous tions.

CY7C1303BV25 – D

[17:0]

[35:0]

CY7C1306BV25 – D

WPS

Input-

Synchronous a Write operation is initiated. Deasserting will deselect the Write port. Deselecting the Write port

will cause D to be ignored.

Write Port Select, active LOW. Sampled on the rising edge of the K clock. When asserted active,

[x:0]

BWS , BWS ,

Input-

Byte Write Select 0, 1, 2 and 3 - active LOW. Sampled on the rising edge of the K and K clocks

BWS , BWS

Synchronous during Write operations. Used to select which byte is written into the device during the current

portion of the Write operations.

CY7C1303BV25 - BWS controls D

and BWS controls D

[8:0]

[17:9].

CY7C1306BV25 - BWS controls D

, BWS controls D

and BWS

[8:0]

[17:9]

[26:18] 3

controls D

[35:27]

Bytes not written remain unaltered. Deselecting a Byte Write Select will cause the corresponding

byte of data to be ignored and not written into the device.

Input-

Address Inputs. Sampled on the rising edge of the K clock during active Read operations and

Synchronous on the rising edge of K for Write operations. These address inputs are multiplexed for both Read

and Write operations. Internally, the device is organized as 1M x 18 (2 arrays each of 512K x 18)

for CY7C1303BV25 and 512K x 36 (2 arrays each of 256K x 36) for CY7C1306BV25. Therefore,

only 19 address inputs are needed to access the entire memory array of CY7C1303BV25 and

18 address inputs for CY7C1306BV25. These inputs are ignored when the appropriate port is

deselected.

Outputs-

Data Output signals. These pins drive out the requested data during a Read operation. Valid

[x:0]

Synchronous data is driven out on the rising edge of both the C and C clocks during Read operations or K and

K when in single clock mode. When the Read port is deselected, Q

three-stated.

are automatically

[x:0]

CY7C1303BV25 - Q

CY7C1306BV25 - Q

[17:0]

[35:0]

RPS

Input-

Read Port Select, active LOW. Sampled on the rising edge of positive input clock (K). When

Synchronous active, a Read operation is initiated. Deasserting will cause the Read port to be deselected. When

deselected, the pending access is allowed to complete and the output drivers are automatically

three-stated following the next rising edge of the K clock. Each read access consists of a burst

of two sequential 18-bit or 36-bit transfers.

Input-Clock Positive Input Clock for Output Data. C is used in conjunction with C to clock out the Read

data from the device. C and C can be used together to deskew the flight times of various devices

on the board back to the controller. See application example for further details.

Input-Clock Negative Input Clock for Output Data. C is used in conjunction with C to clock out the Read

data from the device. C and C can be used together to deskew the flight times of various devices

on the board back to the controller. See application example for further details.

Input-Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the

device and to drive out data through Q

when in single clock mode. All accesses are initiated

[x:0]

on the rising edge of K.

Input-Clock Negative Input Clock Input. K is used to capture synchronous inputs to the device and to drive

out data through Q when in single clock mode.

[x:0]

Input

Output Impedance Matching Input. This input is used to tune the device outputs to the system

data bus impedance. Q output impedance are set to 0.2 x RQ, where RQ is a resistor

[x:0]

connected between ZQ and ground. Alternately, this pin can be connected directly to V

, which

DDQ

enables the minimum impedance mode. This pin cannot be connected directly to GND or left

unconnected.

TDO

TCK

TDI

Output

Input

TDO pin for JTAG.

TCK pin for JTAG.

TDI pin for JTAG.

TMS pin for JTAG.

TMS

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CY7C1303BV25

CY7C1306BV25

Pin Definitions (continued)

Name

NC/36M

I/O

Description

N/A

Address expansion for 36M. This pin is not connected to the die and so can be tied to any

voltage level on CY7C1303BV25/CY7C1306BV25.

GND/72M

NC/72M

Input

N/A

Address expansion for 72M. This pin has to be tied to GND on CY7C1303BV25.

Address expansion for 72M. This pin can be tied to any voltage level on CY7C1306BV25.

GND/144M

Input

Address expansion for 144M. This pin has to be tied to GND on

CY7C1303BV25/CY7C1306BV25.

GND/288M

Input

N/A

Address expansion for 288M. This pin has to be tied to GND on CY7C1306BV25.

Not connected to the die. Can be tied to any voltage level.

Input-

Reference Voltage Input. Static input used to set the reference level for HSTL inputs and Outputs

REF

Reference as well as AC measurement points.

Power Supply Power supply inputs to the core of the device.

Ground

Ground for the device.

Power Supply Power supply inputs for the outputs of the device.

DDQ

the output timing reference. On the subsequent rising edge of

C the higher order data word is driven onto the Q . The

requested data will be valid 2.5 ns from the rising edge of the

output clock (C and C, or K and K when in single clock mode,

250-MHz device).

Introduction

[17:0]

Functional Overview

The CY7C1303BV25/CY7C1306BV25 are synchronous

pipelined Burst SRAM equipped with both a Read port and a

Write port. The Read port is dedicated to Read operations and

the Write port is dedicated to Write operations. Data flows into

the SRAM through the Write port and out through the Read

port. These devices multiplex the address inputs in order to

minimize the number of address pins required. By having

separate Read and Write ports, this architecture completely

eliminates the need to “turn-around” the data bus and avoids

any possible data contention, thereby simplifying system

design. 38-05627Each access consists of two 18-bit data

transfers in the case of CY7C1303BV25, and two 36-bit data

transfers in the case of CY7C1306BV25, in one clock cycle.

Synchronous internal circuitry will automatically three-state

the outputs following the next rising edge of the positive output

clock (C). This will allow for a seamless transition between

devices without the insertion of wait states in a depth

expanded memory.

Write Operations

Write operations are initiated by asserting WPS active at the

rising edge of the positive input clock (K). On the same K clock

rise the data presented to D

lower 18-bit Write Data register provided BWS

is latched and stored into the

[17:0]

are both

[1:0]

asserted active. On the subsequent rising edge of the negative

input clock (K), the address is latched and the information

Accesses for both ports are initiated on the rising edge of the

Positive Input Clock (K). All synchronous input timing is refer-

enced from the rising edge of the input clocks (K and K) and

all output timings are referenced to rising edge of output clocks

(C and C or K and K when in single clock mode).

presented to D

provided BWS

is stored into the Write Data register

are both asserted active. The 36 bits of data

[17:0]

[1:0]

are then written into the memory array at the specified

location.

All synchronous data inputs (D

) pass through input

[x:0]

When deselected, the Write port will ignore all inputs after the

pending Write operations have been completed.

registers controlled by the rising edge of the input clocks (K

and K). All synchronous data outputs (Q ) pass through

[x:0]

output registers controlled by the rising edge of the output

clocks (C and C, or K and K when in single clock mode).

Byte Write Operations

Byte Write operations are supported by the CY7C1303BV25.

A Write operation is initiated as described in the Write

Operation section above. The bytes that are written are deter-

All synchronous control (RPS, WPS, BWS

) inputs pass

[x:0]

through input registers controlled by the rising edge of input

clocks (K and K).

mined by BWS and BWS which are sampled with each set

The following descriptions take CY7C1303BV25 as an

example. The same basic descriptions apply to

CY7C1306BV25.

of 18-bit data word. Asserting the appropriate Byte Write

Select input during the data portion of a write will allow the data

being presented to be latched and written into the device.

Deasserting the Byte Write Select input during the data portion

of a write will allow the data stored in the device for that byte

to remain unaltered. This feature can be used to simplify

Read/Modify/Write operations to a Byte Write operation.

Read Operations

The CY7C1303BV25 is organized internally as 2 arrays of

512K x 18. Accesses are completed in a burst of two

sequential 18-bit data words. Read operations are initiated by

asserting RPS active at the rising edge of the positive input

clock (K). The address is latched on the rising edge of the K

clock. Following the next K clock rise the corresponding lower

Single Clock Mode

The CY7C1303BV25 can be used with a single clock mode. In

this mode the device will recognize only the pair of input clocks

(K and K) that control both the input and output registers. This

order 18-bit word of data is driven onto the Q

using C as

[17:0]

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CY7C1303BV25

CY7C1306BV25

operation is identical to the operation if the device had zero

skew between the K/K and C/C clocks. All timing parameters

remain the same in this mode. To use this mode of operation,

the user must tie C and C HIGH at power-up.This function is

a strap option and not alterable during device operation.

Depth Expansion

The CY7C1303BV25 has a Port Select input for each port.

This allows for easy depth expansion. Both Port Selects are

sampled on the rising edge of the Positive Input Clock only (K).

Each port select input can deselect the specified port.

Deselecting a port will not affect the other port. All pending

transactions (Read and Write) will be completed prior to the

device being deselected.

Concurrent Transactions

The Read and Write ports on the CY7C1303BV25 operate

completely independently of one another. Since each port

latches the address inputs on different clock edges, the user

can Read or Write to any location, regardless of the trans-

action on the other port. Also, reads and writes can be started

in the same clock cycle. If the ports access the same location

at the same time, the SRAM will deliver the most recent infor-

mation associated with the specified address location. This

includes forwarding data from a Write cycle that was initiated

on the previous K clock rise.

Programmable Impedance

An external resistor, RQ, must be connected between the ZQ

pin on the SRAM and V to allow the SRAM to adjust its

output driver impedance. The value of RQ must be 5X the

value of the intended line impedance driven by the SRAM, The

allowable range of RQ to guarantee impedance matching with

a tolerance of ±15% is between 175Ω and 350Ω, with

=1.5V. The output impedance is adjusted every 1024

DDQ

cycles to account for drifts in supply voltage and temperature.

Application Example^[1]

Truth Table^{[2, 3, 4, 5, 6, 7]}

Operation

RPS

WPS

Write Cycle:

L-H

D(A+0) at

K(t) ↑

D(A+1) at

K(t) ↑

Load address on the rising edge of K clock; input write

data on K and K rising edges.

Read Cycle:

L-H

Q(A+0) at

C(t+1)↑

Q(A+1) at

C(t+1) ↑

Load address on the rising edge of K clock; wait one

cycle; read data on 2 consecutive C and C rising edges.

NOP: No Operation

D = X

Q = High-Z Q = High-Z

Standby: Clock Stopped

Stopped

State

Notes:

1. The above application shows 4 QDR-I being used.

2. X = Don't Care, H = Logic HIGH, L = Logic LOW, ↑represents rising edge.

3. Device will power-up deselected and the outputs in a three-state condition.

4. “A” represents address location latched by the devices when transaction was initiated. A+0, A+1 represent the addresses sequence in the burst.

5. “t” represents the cycle at which a Read/Write operation is started. t+1 is the first clock cycle succeeding the “t” clock cycle.

6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.

7. It is recommended that K = K and C = C when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging

symmetrically.

Document #: 38-05627 Rev. *A

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CY7C1303BV25

CY7C1306BV25

Write Descriptions (CY7C1303BV25)^{[2, 8]}

BWS

L-H

Comments

During the Data portion of a Write sequence, both bytes (D

) are written into the device.

[17:0]

L-H During the Data portion of a Write sequence, both bytes (D

[17:0]

L-H

During the Data portion of a Write sequence, only the lower byte (D

) is written into the

[8:0]

device. D

remains unaltered.

[17:9]

L-H

L-H During the Data portion of a Write sequence, only the lower byte (D

device. D remains unaltered.

) is written into the

[8:0]

[17:9]

During the Data portion of a Write sequence, only the byte (D

) is written into the device.

[17:9]

remains unaltered.

[8:0]

L-H During the Data portion of a Write sequence, only the byte (D

remains unaltered.

) is written into the device.

[17:9]

[8:0]

L-H

No data is written into the device during this portion of a write operation.

L-H No data is written into the device during this portion of a write operation.

Write Descriptions (CY7C1306BV25)^{[2, 8]}

BWS

Comments

L-H

During the Data portion of a Write sequence, all four bytes (D

written into the device.

) are

[35:0]

L-H

L-H During the Data portion of a Write sequence, all four bytes (D

written into the device.

[35:0]

During the Data portion of a Write sequence, only the lower byte (D

)

[8:0]

is written into the device. D

will remain unaltered.

[35:9]

L-H During the Data portion of a Write sequence, only the lower byte (D

[8:0]

is written into the device. D

will remain unaltered.

[35:9]

L-H

During the Data portion of a Write sequence, only the byte (D

) is

[17:9]

written into the device. D

and D

will remain unaltered.

[8:0]

[35:18]

L-H During the Data portion of a Write sequence, only the byte (D

) is

[17:9]

written into the device. D

and D

will remain unaltered.

[8:0]

[35:18]

L-H

During the Data portion of a Write sequence, only the byte (D

) is

[26:18]

[35:27]

written into the device. D

and D

will remain unaltered.

[17:0]

[35:27]

L-H During the Data portion of a Write sequence, only the byte (D

written into the device. D and D

will remain unaltered.

[17:0]

[35:27]

L-H

During the Data portion of a Write sequence, only the byte (D

written into the device. D will remain unaltered.

[26:0]

L-H During the Data portion of a Write sequence, only the byte (D

written into the device. D will remain unaltered.

[26:0]

L-H

No data is written into the device during this portion of a Write operation.

L-H No data is written into the device during this portion of a Write operation.

Note:

8. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. BWS , BWS , in the case of CY7C1303BV25 and also BWS and BWS

in the case of CY7C1306BV25 can be altered on different portions of a write cycle, as long as the set-up and hold requirements are achieved. 38-05627

Document #: 38-05627 Rev. *A

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CY7C1303BV25

CY7C1306BV25

TDI and TDO pins as shown in TAP Controller Block Diagram.

Upon power-up, the instruction register is loaded with the

IDCODE instruction. It is also loaded with the IDCODE

instruction if the controller is placed in a reset state as

described in the previous section.

IEEE 1149.1 Serial Boundary Scan (JTAG)

These SRAMs incorporate a serial boundary scan test access

port (TAP) in the FBGA package. This part is fully compliant

with IEEE Standard #1149.1-1900. The TAP operates using

JEDEC standard 2.5V I/O logic levels.

When the TAP controller is in the Capture IR state, the two

least significant bits are loaded with a binary “01” pattern to

allow for fault isolation of the board level serial test path.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG

feature. To disable the TAP controller, TCK must be tied LOW

Bypass Register

(V ) to prevent clocking of the device. TDI and TMS are inter-

nally pulled up and may be unconnected. They may alternately

To save time when serially shifting data through registers, it is

sometimes advantageous to skip certain chips. The bypass

and TDO pins. This allows data to be shifted through the

SRAM with minimal delay. The bypass register is set LOW

be connected to V

through a pull-up resistor. TDO should

be left unconnected. Upon power-up, the device will come up

in a reset state which will not interfere with the operation of the

device.

(V ) when the BYPASS instruction is executed.

Test Access Port—Test Clock

Boundary Scan Register

The test clock is used only with the TAP controller. All inputs

are captured on the rising edge of TCK. All outputs are driven

from the falling edge of TCK.

The boundary scan register is connected to all of the input and

output pins on the SRAM. Several no connect (NC) pins are

also included in the scan register to reserve pins for higher

density devices.

Test Mode Select

The boundary scan register is loaded with the contents of the

RAM Input and Output ring when the TAP controller is in the

Capture-DR state and is then placed between the TDI and

TDO pins when the controller is moved to the Shift-DR state.

The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instruc-

tions can be used to capture the contents of the Input and

Output ring.

The TMS input is used to give commands to the TAP controller

and is sampled on the rising edge of TCK. It is allowable to

leave this pin unconnected if the TAP is not used. The pin is

pulled up internally, resulting in a logic HIGH level.

Test Data-In (TDI)

The TDI pin is used to serially input information into the

registers and can be connected to the input of any of the

registers. The register between TDI and TDO is chosen by the

instruction that is loaded into the TAP instruction register. For

information on loading the instruction register, see the TAP

Controller State Diagram. TDI is internally pulled up and can

be unconnected if the TAP is unused in an application. TDI is

connected to the most significant bit (MSB) on any register.

The Boundary Scan Order tables show the order in which the

bits are connected. Each bit corresponds to one of the bumps

on the SRAM package. The MSB of the register is connected

to TDI, and the LSB is connected to TDO.

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-bit code

during the Capture-DR state when the IDCODE command is

loaded in the instruction register. The IDCODE is hardwired

into the SRAM and can be shifted out when the TAP controller

is in the Shift-DR state. The ID register has a vendor code and

other information described in the Identification Register

Definitions table.

Test Data-Out (TDO)

The TDO output pin is used to serially clock data-out from the

registers. The output is active depending upon the current

state of the TAP state machine (see Instruction codes). The

output changes on the falling edge of TCK. TDO is connected

to the least significant bit (LSB) of any register.

TAP Instruction Set

Performing a TAP Reset

Eight different instructions are possible with the three-bit

instruction register. All combinations are listed in the

Instruction Code table. Three of these instructions are listed

as RESERVED and should not be used. The other five instruc-

tions are described in detail below.

A Reset is performed by forcing TMS HIGH (V ) for five rising

edges of TCK. This RESET does not affect the operation of

the SRAM and may be performed while the SRAM is

operating. At power-up, the TAP is reset internally to ensure

that TDO comes up in a high-Z state.

Instructions are loaded into the TAP controller during the

Shift-IR state when the instruction register is placed between

TDI and TDO. During this state, instructions are shifted

through the instruction register through the TDI and TDO pins.

To execute the instruction once it is shifted in, the TAP

controller needs to be moved into the Update-IR state.

TAP Registers

Registers are connected between the TDI and TDO pins and

allow data to be scanned into and out of the SRAM test

circuitry. Only one register can be selected at a time through

the instruction registers. Data is serially loaded into the TDI pin

on the rising edge of TCK. Data is output on the TDO pin on

the falling edge of TCK.

IDCODE

The IDCODE instruction causes a vendor-specific, 32-bit code

to be loaded into the instruction register. It also places the

instruction register between the TDI and TDO pins and allows

the IDCODE to be shifted out of the device when the TAP

controller enters the Shift-DR state. The IDCODE instruction

Instruction Register

Three-bit instructions can be serially loaded into the instruction

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CY7C1303BV25

CY7C1306BV25

is loaded into the instruction register upon power-up or

whenever the TAP controller is given a test logic reset state.

BYPASS

When the BYPASS instruction is loaded in the instruction

advantage of the BYPASS instruction is that it shortens the

boundary scan path when multiple devices are connected

together on a board.

SAMPLE Z

The SAMPLE Z instruction causes the boundary scan register

to be connected between the TDI and TDO pins when the TAP

controller is in a Shift-DR state. The SAMPLE Z command puts

the output bus into a High-Z state until the next command is

given during the “Update IR” state.

EXTEST

The EXTEST instruction enables the preloaded data to be

driven out through the system output pins. This instruction also

selects the boundary scan register to be connected for serial

access between the TDI and TDO in the shift-DR controller

state.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When

the SAMPLE/PRELOAD instructions are loaded into the

instruction register and the TAP controller is in the Capture-DR

state, a snapshot of data on the inputs and output pins is

captured in the boundary scan register.

EXTEST Output Bus Tri-state

The user must be aware that the TAP controller clock can only

operate at a frequency up to 10 MHz, while the SRAM clock

operates more than an order of magnitude faster. Because

there is a large difference in the clock frequencies, it is

possible that during the Capture-DR state, an input or output

will undergo a transition. The TAP may then try to capture a

signal while in transition (metastable state). This will not harm

the device, but there is no guarantee as to the value that will

be captured. Repeatable results may not be possible.

IEEE Standard 1149.1 mandates that the TAP controller be

able to put the output bus into a tri-state mode.

The boundary scan register has a special bit located at bit #47.

When this scan cell, called the “extest output bus tri-state”, is

latched into the preload register during the “Update-DR” state

in the TAP controller, it will directly control the state of the

output (Q-bus) pins, when the EXTEST is entered as the

current instruction. When HIGH, it will enable the output

buffers to drive the output bus. When LOW, this bit will place

the output bus into a High-Z condition.

To guarantee that the boundary scan register will capture the

correct value of a signal, the SRAM signal must be stabilized

long enough to meet the TAP controller's capture set-up plus

This bit can be set by entering the SAMPLE/PRELOAD or

EXTEST command, and then shifting the desired bit into that

cell, during the “Shift-DR” state. During “Update-DR”, the value

loaded into that shift-register cell will latch into the preload

directly control the output Q-bus pins. Note that this bit is

pre-set HIGH to enable the output when the device is

powered-up, and also when the TAP controller is in the

“Test-Logic-Reset” state.

hold times (t and t ). The SRAM clock input might not be

captured correctly if there is no way in a design to stop (or

slow) the clock during a SAMPLE/PRELOAD instruction. If this

is an issue, it is still possible to capture all other signals and

simply ignore the value of the CK and CK captured in the

boundary scan register.

Once the data is captured, it is possible to shift out the data by

putting the TAP into the Shift-DR state. This places the

boundary scan register between the TDI and TDO pins.

Reserved

These instructions are not implemented but are reserved for

future use. Do not use these instructions.

PRELOAD allows an initial data pattern to be placed at the

latched parallel outputs of the boundary scan register cells

prior to the selection of another boundary scan test operation.

The shifting of data for the SAMPLE and PRELOAD phases

can occur concurrently when required—that is, while data

captured is shifted out, the preloaded data can be shifted in.

Document #: 38-05627 Rev. *A

Page 9 of 19

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TAP Controller State Diagram^[9]

TEST-LOGIC

RESET

TEST-LOGIC/

IDLE

SELECT

DR-SCAN

SELECT

IR-SCAN

CAPTURE-DR

SHIFT-DR

SHIFT-IR

EXIT1-DR

EXIT1-IR

PAUSE-DR

PAUSE-IR

EXIT2-DR

EXIT2-IR

UPDATE-DR

UPDATE-IR

Note:

9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.

Document #: 38-05627 Rev. *A

Page 10 of 19

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TAP Controller Block Diagram

Bypass Register

Selection

TDI

Selection

TDO

Circuitry

Instruction Register

31 30

Identification Register

106 .

Boundary Scan Register

TCK

TMS

TAP Controller

[10, 14, 17]

TAP Electrical Characteristics Over the Operating Range

Parameter

Description

Output HIGH Voltage

Output LOW Voltage

Input HIGH Voltage

Test Conditions

= −2.0 mA

Min.

1.7

Max.

Unit

OH1

OH2

OL1

OL2

= −100 µA

= 2.0 mA

= 100 µA

2.1

0.7

0.2

1.7

–0.3

−5

+ 0.3

Input LOW Voltage

0.7

Input and Output Load Current

GND ≤ V ≤ V

DDQ

µA

[11, 12]

TAP AC Switching Characteristics Over the Operating Range

Parameter

Description

Min.

Max.

Unit

TCK Clock Cycle Time

TCK Clock Frequency

TCK Clock HIGH

MHz

TCYC

TCK Clock LOW

Set-up Times

TMS Set-up to TCK Clock Rise

TDI Set-up to TCK clock Rise

Capture Set-up to TCK Rise

TMSS

TDIS

Hold Times

TMS Hold after TCK Clock Rise

TDI Hold after Clock Rise

TMSH

TDIH

Capture Hold after Clock Rise

Notes:

10. These characteristic pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics table.

11. t and t refer to the set-up and hold time requirements of latching data from the boundary scan register.

12. Test conditions are specified using the load in TAP AC test conditions. t /t = 1 ns.

Document #: 38-05627 Rev. *A

Page 11 of 19

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[11, 12]

TAP AC Switching Characteristics Over the Operating Range

(continued)

Parameter

Description

Min.

Max.

Unit

Output Times

TCK Clock LOW to TDO Valid

TCK Clock LOW to TDO Invalid

TDOV

TDOX

TAP Timing and Test Conditions^[12]

1.25V

50Ω

ALL INPUT PULSES

1.25V

TDO

2.5V

Z = 50Ω

C = 20 pF

(a)

GND

t_TL

t_TH

Test Clock

TCK

t_TCYC

t_TMSS

t_TMSH

Test Mode Select

TMS

t_TDIS

t_TDIH

Test Data-In

TDI

Test Data-Out

TDO

t_TDOX

t_TDOV

Identification Register Definitions

Value

Instruction Field

Revision Number (31:29)

Cypress Device ID (28:12)

Cypress JEDEC ID (11:1)

ID Register Presence (0)

CY7C1303BV25

CY7C1306BV25

Description

Version number.

000

01011010010010101

00000110100

000

01011010010100101 Defines the type of SRAM.

00000110100

Allows unique identification of SRAM vendor.

Indicate the presence of an ID register.

Document #: 38-05627 Rev. *A

Page 12 of 19

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Scan Register Sizes

Instruction

Bit Size

Bypass

107

Boundary Scan

Instruction Codes

Instruction

EXTEST

Code

Description

000

001

Captures the Input/Output ring contents.

IDCODE

Loads the ID register with the vendor ID code and places the register

between TDI and TDO. This operation does not affect SRAM operation.

SAMPLE Z

010

Captures the Input/Output contents. Places the boundary scan register

between TDI and TDO. Forces all SRAM output drivers to a High-Z state.

RESERVED

011

100

Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD

Captures the Input/Output ring contents. Places the boundary scan register

between TDI and TDO. Does not affect the SRAM operation.

RESERVED

BYPASS

101

110

111

Do Not Use: This instruction is reserved for future use.

Places the bypass register between TDI and TDO. This operation does not

affect SRAM operation.

Document #: 38-05627 Rev. *A

Page 13 of 19

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Boundary Scan Order

Bit #

Bump ID

Bit #

Bump ID

11H

10G

Bit #

Bump ID

Bit #

Bump ID

11F

11G

10F

11E

10E

10D

11P

10P

10N

10C

11D

10M

11N

11B

11C

11L

11M

10B

11A

Internal

100

101

102

103

104

105

106

10L

11K

10K

10J

11J

Document #: 38-05627 Rev. *A

Page 14 of 19

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[17]

DC Input Voltage ............................... –0.5V to V + 0.5V

Maximum Ratings

Current into Outputs (LOW)......................................... 20 mA

(Above which the useful life may be impaired.)

Static Discharge Voltage.......................................... > 2001V

(per MIL-STD-883, Method 3015)

Storage Temperature ................................–65°C to + 150°C

Ambient Temperature with

Power Applied............................................–55°C to + 125°C

Latch-up Current.................................................... > 200 mA

Operating Range

Supply Voltage on V Relative to GND....... –0.5V to + 3.6V

Supply Voltage on V

Relative to GND .....–0.5V to + V

Ambient

DDQ

[13]

DDQ

Range Temperature (T )

DC Applied to Outputs in

Com’l

Ind’l

0°C to + 70°C

2.5 ± 0.1V

1.4V to 1.9V

High-Z State........................................ –0.5V to V

+ 0.5V

DDQ

–40°C to + 85°C

[14]

Electrical Characteristics Over the Operating Range

DC Electrical Characteristics Over the Operating Range

Parameter

Description

Power Supply Voltage

I/O Supply Voltage

Test Conditions

Min.

2.4

Typ.

Max.

Unit

2.5

1.5

2.6

1.4

1.9

DDQ

Output HIGH Voltage

Output LOW Voltage

Output HIGH Voltage

Output LOW Voltage

Note 15

Note 16

/2 – 0.12

/2 + 0.12

DDQ

= –0.1 mA, Nominal Impedance

= 0.1 mA, Nominal Impedance

– 0.2

DDQ

OH(LOW)

OL(LOW)

DDQ

0.2

+ 0.3

DDQ

[17]

Input HIGH Voltage

+ 0.1

REF

[17, 18]

Input LOW Voltage

–0.3

– 0.1

REF

[19]

Input Reference Voltage

Input Leakage Current

Output Leakage Current

Typical value = 0.75V

0.68

–5

0.75

0.95

REF

GND ≤ V ≤ V

µA

DDQ

GND ≤ V ≤ V

Output Disabled

–5

DDQ,

Operating Supply

= Max., I

= 0 mA,

500

OUT

= 1/t

CYC

f = f

MAX

Automatic

Power-Down

Current

Max. V , Both Ports Deselected,

240

SB1

≥ V or V ≤ V f = f

=1/t

MAX CYC,

Inputs Static

AC Input Requirements Over the Operating Range

Parameter

Description

Input HIGH Voltage

Input LOW Voltage

Test Conditions

Min.

Typ.

Max.

Unit

+ 0.2

REF

–

– 0.2

REF

Thermal Resistance^[20]

Parameter

Description

Test Conditions

165 FBGA Package

Unit

Thermal Resistance

(Junction to Ambient)

Testconditionsfollowstandardtestmethodsand

procedures for measuring thermal impedance,

per EIA/JESD51.

16.7

°C/W

Thermal Resistance

(Junction to Case)

6.5

°C/W

Notes:

13. Power-up: Assumes a linear ramp from 0V to V (min.) within 200 ms. During this time V < V and V

< V .

DDQ

14. All Voltage referenced to Ground.

15. Output are impedance controlled. I = –V

/2)/(RQ/5) for values of 175Ω <= RQ <= 350Ω.

DDQ

16. Output are impedance controlled. I = (V

/2)/(RQ/5) for values of 175Ω <= RQ <= 350Ω.

DDQ

17. Overshoot: V (AC) < V

+0.85V (Pulse width less than t

/2), Undershoot: V (AC) > –1.5V (Pulse width less than t

/2).

DDQ

CYC

18. This spec is for all inputs except C and C Clock. For C and C Clock, V (Max.) = V

– 0.2V.

REF

19. V

(Min.) = 0.68V or 0.46V

, whichever is larger, V

(Max.) = 0.95V or 0.54V

, whichever is smaller.

REF

DDQ

REF

DDQ

20. Tested initially and after any design or process change that may affect these parameters.

Document #: 38-05627 Rev. *A

Page 15 of 19

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CY7C1306BV25

Capacitance^[23]

Parameter

Description

Test Conditions

T = 25°C, f = 1 MHz,

Max.

Unit

Input Capacitance

= 2.5V.

Clock Input Capacitance

Output Capacitance

CLK

= 1.5V

DDQ

AC Test Loads and Waveforms

_REF= 0.75V

0.75V

V_REF

0.75V

R = 50Ω

OUTPUT

[21]

ALL INPUT PULSES

1.25V

Z = 50Ω

OUTPUT

Device

R = 50Ω

0.75V

Under

Device

Under

0.25V

Test

5 pF

V_REF= 0.75V

Slew Rate = 2 V/ns

Test

RQ =

250Ω

(a)

(b)

[21]

Switching Characteristics Over the Operating Range

167 MHz

Cypress Consortium

Parameter Parameter

Description

(typical) to the First Access Read or Write

Min.

Max.

Unit

[22]

µs

Power

Cycle Time

K Clock and C Clock Cycle Time

Input Clock (K/K and C/C) HIGH

Input Clock (K/K and C/C) LOW

6.0

2.4

2.7

CYC

KHKH

KHKL

KLKH

KHKH

K/K Clock Rise to K/K Clock Rise and C/C to C/C Rise

(rising edge to rising edge)

3.3

2.0

KHKH

K/K Clock Rise to C/C Clock Rise (rising edge to rising edge)

0.0

KHCH

Set-up Times

Address Set-up to Clock (K and K) Rise

0.7

Control Set-up to Clock (K and K) Rise (RPS, WPS, BWS , BWS )

Set-up to Clock (K and K) Rise

[x:0]

Hold Times

Address Hold after Clock (K and K) Rise

0.7

Control Signals Hold after Clock (K and K) Rise (RPS, WPS, BWS , BWS ) 0.7

Hold after Clock (K and K) Rise

0.7

[x:0]

Output Times

C/C Clock Rise (or K/K in single clock mode) to Data Valid

Data Output Hold after Output C/C Clock Rise (Active to Active)

2.5

CHQV

CHQX

CHZ

1.2

DOH

CHZ

CLZ

[23, 24]

Clock (C and C) rise to High-Z (Active to High-Z)

[23, 24]

Clock (C and C) rise to Low-Z

CLZ

Notes:

21. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V,Vref = 0.75V, RQ = 250Ω, V

= 1.5V, input

DDQ

pulse levels of 0.25V to 1.25V, and output loading of the specified I /I and load capacitance shown in (a) of AC test loads.

OL OH

22. This part has a voltage regulator that steps down the voltage internally; t

is the time power needs to be supplied above V minimum initially before a read

Power

or write operation can be initiated.

23. At any given voltage and temperature t

is less than t

and, t

less than t

CHZ

CLZ

CHZ

Document #: 38-05627 Rev. *A

Page 16 of 19

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Switching Waveforms^{[25, 26, 27]}

READ

WRITE

READ

WRITE

READ

WRITE

NOP

WRITE

NOP

CYC

KHKH

RPS

tSC

tHC

WPS

SA HA

D10

D11

D30

D31

D50

D51

D60

D61

Q00

Q01

Q20

Q21

Q40

Q41

CHZ

DOH

CLZ

KHCH

tCYC

KHKH

DON’T CARE

UNDEFINED

Notes:

24. t

, t

, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.

CHZ CLZ

25. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e., A0+1.

26. Outputs are disabled (High-Z) one clock cycle after a NOP.

27. In this example, if address A2 = A1 then data Q2 0= D10 and Q21 = D11. Write data is forwarded immediately as read results.This note applies to the whole diagram.

Document #: 38-05627 Rev. *A

Page 17 of 19

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CY7C1306BV25

Ordering Information

“Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

visit www.cypress.com for actual products offered”.

Speed

(MHz)

Package

Diagram

Operating

Range

Ordering Code

Package Type

167 CY7C1303BV25-167BZC 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)

CY7C1306BV25-167BZC

Commercial

CY7C1303BV25-167BZXC

CY7C1306BV25-167BZXC

CY7C1303BV25-167BZI

CY7C1306BV25-167BZI

CY7C1303BV25-167BZXI

CY7C1306BV25-167BZXI

165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead free

165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)

Industrial

165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead free

Package Diagram

165 FBGA 13 x 15 x 1.40 MM BB165D/BW165D

165-ball FBGA (13 x 15 x 1.4 mm) (51-85180)

BOTTOM VIEW

PIN 1 CORNER

BOTTOM VIEW

TOP VIEW

PIN 1 CORNER

Ø0.05 M C

Ø0.25 M C A B

PIN 1 CORNER

-0Ø.060.25 M C A B

Ø0.50 (165X)

+0.14

-0.06

Ø0.50₃

(165X)

11 10

+0.14

11 10

1.00

5.00

1.00

5.00

10.00

13.00 0.10

0.15(4X)

NOTES :

SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)

PACKAGE WEIGHT : 0.475g

SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)

JEDEC REFERENCE : MO-216 / DESIGN 4.6C

PACKAGE WEIGHT : 0.475g

PACKAJEGDEECCORDEEFE:RBEBN0ACEC: MO-216 / DESIGN 4.6C

PACKAGE CODE : BB0AC

SEATING PLANE

51-85180-*A

Quad Data Rate™ SRAM and QDR™ SRAM comprise a new family of products developed by Cypress, IDT, NEC, Renesas and

Samsung. All products and company names mentioned in this document may be the trademarks of their respective holders.

Document #: 38-05627 Rev. *A

Page 18 of 19

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

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Document History Page

Document Title: CY7C1303BV25/CY7C1306BV25 18-Mbit Burst of 2 Pipelined SRAM with QDR™ Architecture

Document Number: 38-05627

Orig. of

REV.

ECN NO.

253010

436864

Issue Date

See ECN

Change

Description of Change

SYT

New Data Sheet

NXR

Converted from Preliminary to Final.

Removed 133 MHz & 100 MHz from product offering.

Included the Industrial Operating Range.

Changed C/C Description in the Features Section & Pin Description Table.

Changed t

from 100 ns to 50 ns, changed t from 10 MHz to 20 MHz

TCYC

and changed t and t from 40 ns to 20 ns in TAP AC Switching

Characteristics table

Modified the ZQ pin definition as follows:

Alternately, this pin can be connected directly to V

minimum impedance mode

, which enables the

DDQ

Included Maximum Ratings for Supply Voltage on V

Relative to GND

DDQ

Changed the Maximum Ratings for DC Input Voltage from V

to V

DDQ

DD.

Modified the Description of I from Input Load current to Input Leakage

Current on page # 15.

Modified test condition in note# 13 from V

< V to V

≤ V

DDQ

DDQ DD

Updated the Ordering Information table and replaced the Package Name

Column with Package Diagram.

Document #: 38-05627 Rev. *A

Page 19 of 19

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