Silicon Image SiliconDrive CF SSD C08G(I) 3150 User Manual

DATA SHEET

SILICONDRIVE CF

SSD-CXXX(I)-3150

OVERVIEW

FEATURES

SiliconDrive

combines

all

the

high

• Integrated PowerArmor, SiSMART, and

SiSecure technologies

performance, high reliability, and multiyear

lifecycle benefits of the standard SiliconDrive

with a comprehensive suite of patented and

patent-pending technologies that provide

multiple security options to safeguard

application data and software IP in embedded

systems.

• Capacity range: 32MB to 8GB

• Supports both 8-bit and 16-bit data register

transfers

• Supports dual-voltage 3.3V or 5V interface

• Data reliability <1 error in 10 bits read

Applications requiring advanced levels of

security such as data recorders, wearable and

field computers, medical monitoring and

diagnostic equipment, POS systems, and

voting machines are able to activate security

options to protect application data and

software IP from theft, falling into the wrong

hands from deployments in high-risk areas,

corruption, and accidental or malicious

overwrites.

• MTBF 4,000,000 hours

• ATA-3 compliant

• Industry standard Type I CF form factor

• RoHS 5 of 6 compliant

• Supports PIO modes 0-4 and DMA modes

0-2

PowerArmor prevents data corruption and loss

from power disturbances by integrating

patented technology into every SiliconDrive.

8GB

SSD-C08G(I)-3150

SiSMART acts as an early warning system to

eliminate unscheduled downtime by constantly

monitoring and reporting the exact amount of

remaining storage system useful life.

SiSecure is a comprehensive suite of user-

selectable security technologies that solves

the critical need for robust storage security for

embedded systems applications that have a

small footprint and low-power requirement.

SISECURE

PowerArmor Eliminates drive corruption.

SiZone

Data zones with different

security parameters.

SiKey

Ties SiliconDrive to a specific

host and/or software IP.

SiProtect

Protection software for

password-required, read/write,

or read-only access.

SiSweep

SiPurge

Ultra-fast data erasure.

Non-recoverable data erasure.

Click here

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This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc.

All unauthorized use and/or reproduction is prohibited.

26840 ALISO VIEJO PARKWAY, ALISO VIEJO, CA 92656 • PHONE: 949.900.9400 • FAX: 949.900.9500 • http://www.siliconsystems.com

3150C-10DSR

FEBRUARY 2, 2009

TABLE OF CONTENTS

SSD-CXXX(I)-3150 DATA SHEET

TABLE OF CONTENTS

Overvie w.......................................................................................................................... i

SiSecure........................................................................................................................... i

Feature s........................................................................................................................... i

Revision History..............................................................................................................II

List of Figures ...............................................................................................................VII

List of Table s................................................................................................................VIII

Physical Specification s................................................................................................. 1

Physical Dimensions .................................................................................................... 1

Product Specification s.................................................................................................. 2

System Performance.................................................................................................... 2

System Power Requirements....................................................................................... 2

Reliabilit y ...................................................................................................................... 3

Projected Operational Life Span .................................................................................. 3

Product Capacity Specifications................................................................................... 4

Environmental Specifications ....................................................................................... 4

Electrical Specification.................................................................................................. 5

Pin Assignments........................................................................................................... 5

Signal Descriptions....................................................................................................... 6

Absolute Maximum Ratings........................................................................................ 14

Capacitance ............................................................................................................... 15

DC Characteristics ..................................................................................................... 15

AC Characteristics...................................................................................................... 16

Attribute and Common Memory Read Timin g ...................................................... 16

Attribute and Common Memory Write Timing ...................................................... 17

I/O Access Read Timing....................................................................................... 18

I/O Access Write Timing....................................................................................... 19

True IDE Read/Write Access Timing.................................................................... 20

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TABLE OF CONTENTS

SSD-CXXX(I)-3150 DATA SHEET

True IDE Multiword DMA Read/Write Access Timing .......................................... 21

Attribute Memory Description and Operatio n........................................................... 22

Attribute Memory Read Operations............................................................................ 22

Attribute Memory Write Operation s ............................................................................ 23

Attribute Memory Ma p ................................................................................................ 24

Card Information Structur e ......................................................................................... 25

Configuration Option Register (200h)......................................................................... 36

Configuration and Status Register (202h ).................................................................. 37

Pin Placement Register (204h) .................................................................................. 38

Socket and Copy Register (206h) .............................................................................. 39

Common Memory Description and Operation .......................................................... 40

Common Memory Read Operations........................................................................... 40

Common Memory Write Operations........................................................................... 40

I/O Space Description and Operation ........................................................................ 41

I/O Space Read Operations ....................................................................................... 41

I/O Space Write Operations ....................................................................................... 41

ATA and True IDE Register Decoding ........................................................................ 42

Memory-Mapped Register Decoding.......................................................................... 42

Independent I/O Mode Register Decodin g ................................................................. 43

Primary and Secondary I/O Mapped Register Decoding ........................................... 44

Task File Register Specificatio n ................................................................................. 45

ATA Registers............................................................................................................... 46

Data Register ............................................................................................................. 46

Error Registe r ............................................................................................................. 46

Feature Register......................................................................................................... 47

Sector Count Registe r ................................................................................................ 48

Sector Number Register............................................................................................. 49

Cylinder Low Register ................................................................................................ 50

Cylinder High Register ............................................................................................... 51

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TABLE OF CONTENTS

SSD-CXXX(I)-3150 DATA SHEET

Drive/Head Registe r ................................................................................................... 52

Status Register........................................................................................................... 53

Command Register .................................................................................................... 54

Alternate Status Register ........................................................................................... 55

Device Control Register ............................................................................................. 56

Device Address Register............................................................................................ 57

ATA Command Block and Set Descriptio n................................................................ 58

ATA Command Set .................................................................................................... 58

Check Power Mode — 98h, E5 h .......................................................................... 60

Executive Drive Diagnostic — 90 h ....................................................................... 61

Format Track — 50h ............................................................................................ 62

Identify Drive — ECh............................................................................................ 63

Identify Drive — Drive Attribute Data ............................................................. 64

Idle — 97h, E3h.................................................................................................... 67

Idle Immediate — 95h, E1h.................................................................................. 68

Initialize Drive Parameters — 91h........................................................................ 69

Recalibrate — 1Xh ............................................................................................... 70

Read Buffer — E4h .............................................................................................. 71

Read DMA — C8h................................................................................................ 72

Read Multiple — C4h ........................................................................................... 73

Read Sector — 20h, 21h...................................................................................... 74

Read Long Sector(s) — 22h, 23h......................................................................... 75

Read Verify Sector(s) — 40h, 41h ....................................................................... 76

Seek — 7Xh ......................................................................................................... 77

Set Features — EFh............................................................................................. 78

Set Multiple Mode — C6h .................................................................................... 79

Set Sleep Mode — 99h, E6h................................................................................ 80

Standby — 96h, E2h ............................................................................................ 81

Standby Immediate — 94h, E0h .......................................................................... 82

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TABLE OF CONTENTS

SSD-CXXX(I)-3150 DATA SHEET

Write Buffer — E8h .............................................................................................. 83

Write DMA — CAh ............................................................................................... 84

Write Multiple — C5h ........................................................................................... 85

Write Sector(s) — 30h, 31h.................................................................................. 86

Write Long Sector(s) — 32h, 33h......................................................................... 87

Erase Sector(s) — C0h ........................................................................................ 88

Request Sense — 03h ......................................................................................... 89

Translate Sector — 87h ....................................................................................... 90

Wear-Level — F5h ............................................................................................... 91

Write Multiple w/o Erase — CDh.......................................................................... 92

Write Sector(s) w/o Erase — 38h......................................................................... 93

Write Verify — 3Ch............................................................................................... 94

Sales and Support ....................................................................................................... 95

Part Numberin g............................................................................................................ 95

Nomenclatur e ............................................................................................................. 95

Part Numbers ............................................................................................................. 96

Sample Label ............................................................................................................. 96

Related Documentatio n............................................................................................... 97

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LIST OF FIGURES

SSD-CXXX(I)-3150 DATA SHEET

LIST OF FIGURES

Figure 1: Physical Dimensions......................................................................................... 1

Figure 2: Attribute and Common Memory Read Timing Diagram.................................. 16

Figure 3: Attribute and Common Memory Write Timing Diagra m.................................. 17

Figure 4: I/O Access Read Timing Diagram .................................................................. 18

Figure 5: I/O Access Write Timing Diagram................................................................... 19

Figure 6: True IDE Read/Write Access Timing Diagram ............................................... 20

Figure 7: True IDE Multiword DMA Read/Write Access Timing..................................... 21

Figure 8: Sample Label.................................................................................................. 96

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LIST OF TABLES

SSD-CXXX(I)-3150 DATA SHEET

LIST OF TABLES

Table 1: System Performance ......................................................................................... 2

Table 2: System Power Requirements ............................................................................ 2

Table 3: Reliability............................................................................................................ 3

Table 4: Operational Life Span ........................................................................................ 3

Table 5: Product Capacity Specifications ........................................................................ 4

Table 6: Environmental Specifications............................................................................. 4

Table 7: Pin Assignments ................................................................................................ 5

Table 8: Signal Descriptions ............................................................................................ 6

Table 9: Absolute Maximum Ratings ............................................................................. 14

Table 10: Capacitanc e................................................................................................... 15

Table 11: DC Characteristic s......................................................................................... 15

Table 12: Attribute and Common Memory Read Timing................................................ 16

Table 13: Attribute and Common Memory Write Timing................................................ 17

Table 14: I/O Access Read Timing ................................................................................ 18

Table 15: I/O Access Write Timing ................................................................................ 19

Table 16: True IDE Read/Write Access Timing ............................................................. 20

Table 17: True IDE Multiword DMA Read/Write Access Timing.................................... 21

Table 18: Attribute Memory Read Operations ............................................................... 22

Table 19: Attribute Memory Write Operations................................................................ 23

Table 20: Attribute Memory Map.................................................................................... 24

Table 21: Card Information Structure............................................................................. 25

Table 22: Configuration Option Register (200h) ............................................................ 36

Table 23: Configuration and Status Register (202h)...................................................... 37

Table 24: Pin Placement Register (204h )...................................................................... 38

Table 25: Socket and Copy Register (206h).................................................................. 39

Table 26: Common Memory Read Operations .............................................................. 40

Table 27: Common Memory Write Operations .............................................................. 40

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LIST OF TABLES

SSD-CXXX(I)-3150 DATA SHEET

Table 28: I/O Space Read Operations........................................................................... 41

Table 29: I/O Space Write Operation s........................................................................... 41

Table 30: Memory-Mapped Register Decoding ............................................................. 42

Table 31: Independent I/O Mode Register Decoding..................................................... 43

Table 32: Primary and Secondary I/O Mapped Register Decodin g............................... 44

Table 33: Task File Register Specification..................................................................... 45

Table 34: Error Register................................................................................................. 46

Table 35: Feature Register ............................................................................................ 47

Table 36: Sector Count Register.................................................................................... 48

Table 37: Sector Number Register ................................................................................ 49

Table 38: Cylinder Low Register.................................................................................... 50

Table 39: Cylinder High Registe r................................................................................... 51

Table 40: Drive/Head Register....................................................................................... 52

Table 41: Status Register .............................................................................................. 53

Table 42: Command Registe r........................................................................................ 54

Table 43: Alternate Status Registe r............................................................................... 55

Table 44: Device Control Registe r................................................................................. 56

Table 45: Device Address Register ............................................................................... 57

Table 46: ATA Command Block and Set Description .................................................... 58

Table 47: ATA Command Se t........................................................................................ 58

Table 48: Check Power Mode — 98h, E5h.................................................................... 60

Table 49: Executive Drive Diagnostic — 90h................................................................. 61

Table 50: Format Track — 50 h...................................................................................... 62

Table 51: Identify Drive — ECh ..................................................................................... 63

Table 52: Identify Drive — Drive Attribute Dat a............................................................. 64

Table 53: Idle — 97h, E3h ............................................................................................. 67

Table 54: Idle Immediate — 95h, E1h ........................................................................... 68

Table 55: Initialize Drive Parameters — 91h ................................................................. 69

Table 56: Recalibrate — 1Xh......................................................................................... 70

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LIST OF TABLES

SSD-CXXX(I)-3150 DATA SHEET

Table 57: Read Buffer — E4h........................................................................................ 71

Table 58: Read DMA — C8h ......................................................................................... 72

Table 59: Read Multiple — C4h..................................................................................... 73

Table 60: Read Sector — 20h, 21h ............................................................................... 74

Table 61: Read Long Sector(s) — 22h, 23h .................................................................. 75

Table 62: Read Verify Sector(s) — 40h, 41 h................................................................. 76

Table 63: Seek — 7Xh................................................................................................... 77

Table 64: Set Features — EFh ...................................................................................... 78

Table 65: Set Features’ Attributes ................................................................................. 78

Table 66: Set Multiple Mode — C6 h.............................................................................. 79

Table 67: Set Sleep Mode — 99h, E6h ......................................................................... 80

Table 68: Standby — 96h, E2h...................................................................................... 81

Table 69: Standby Immediate — 94h, E0 h.................................................................... 82

Table 70: Write Buffer — E8 h........................................................................................ 83

Table 71: Write DMA — CA h......................................................................................... 84

Table 72: Write Multiple — C5 h..................................................................................... 85

Table 73: Write Sector(s) — 30h, 31h ........................................................................... 86

Table 74: Write Long Sector(s) — 32h, 33h .................................................................. 87

Table 75: Erase Sector(s) — C0h.................................................................................. 88

Table 76: Request Sense — 03h................................................................................... 89

Table 77: Extended Error Codes ................................................................................... 89

Table 78: Translate Sector — 87 h................................................................................. 90

Table 79: Wear-Level — F5h......................................................................................... 91

Table 80: Write Multiple w/o Erase — CDh ................................................................... 92

Table 81: Write Sector(s) w/o Erase — 38h .................................................................. 93

Table 82: Write Verify — 3Ch ........................................................................................ 94

Table 83: Part Numbering Nomenclature ...................................................................... 95

Table 84: Part Numbers................................................................................................. 96

Table 85: Related Documentation ................................................................................. 97

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FEBRUARY 2, 2009

PHYSICAL SPECIFICATIONS

SSD-CXXX(I)-3150 DATA SHEET

PHYSICAL SPECIFICATIONS

The SiliconDrive CF products are offered in an industry-standard Type I form

factor. See "Part Numbering" on page 95 for details regarding CF capacities.

PHYSICAL DIMENSIONS

This section provides diagrams that describe the physical dimensions for the

CF.

Figure 1: Physical Dimensions

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PRODUCT SPECIFICATIONS

SSD-CXXX(I)-3150 DATA SHEET

PRODUCT SPECIFICATIONS

Note: All SiliconDrive CF values quoted are typical at 25°C and nominal

supply voltage.

SYSTEM PERFORMANCE

Table 1: System Performance

Reset to Ready Startup Time (Typical/Maximum) 200ms/400ms

Read Transfer Rate (Typical)

Write Transfer Rate (Typical)

Burst Transfer Rate

8MBps

6MBps

16.7MBps

2ms (maximum)

Controller Overhead (Command to DRQ)

SYSTEM POWER REQUIREMENTS

Table 2: System Power Requirements

DC Input Voltage

3.3 ± 10%

<0.5mA

5.0 ± 10%

Sleep (Standby Current)

Read (Typical/Peak)

Write (Typical/Peak)

<1.0mA

20mA/75mA

30mA/75mA

30mA/100mA

40mA/100mA

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PRODUCT SPECIFICATIONS

SSD-CXXX(I)-3150 DATA SHEET

RELIABILITY

Table 3: Reliability

4,000,000 hours

<1 non-recoverable error in 10 bits read

MTBF (@ 25ºC)

Bit Error Rate

PROJECTED OPERATIONAL LIFE SPAN

Table 4: Operational Life Span

Capacity Service Life*

8GB 324.3 Years

SiliconDrive Part#

GB Written per Day

@ 135.2GB

SSD-C08G-3150

SSD-C04G-3150

SSD-C02G-3150

SSD-C01G-3150

SSD-C51M-3150

SSD-C25M-3150

SSD-C12M-3150

SSD-C64M-3150

SSD-C32M-3150

4GB

162.2 Years

81.1 Years

40.5 Years

20.3 Years

10.1 Years

5.1 Years

2.5 Years

1.3 Years

@ 135.2GB

2GB

1GB

512MB

256MB

128MB

64MB

32MB

* There are unlimited read cycles. Service life is determined using

SiliconSystems’ LifeEst calculation at 100% duty cycle with 25% write cycles.

LifeEst is a comprehensive measurement that considers numerous factors to

determine the projected life span of a SiliconDrive. A white paper that

describes the benefits of LifeEst and how to calculate it can be found at http://

www.siliconsystems.com/resources/Documents/Whitepaper/

SiliconSystems_NAND_Evolution.pdf.

The actual life of a SiliconDrive is dependant on the customer usage model.

SiSMART is a patented technology of SiliconSystems that enables host

systems to monitor actual usage of a SiliconDrive in real time. SiSMART

measures and reports the remaining life of a SiliconDrive. For more

information on SiSMART, refer to the Eliminating Unscheduled Downtime by

Forecasting Useable Life white paper at http://www.siliconsystems.com/

technology/pdfs/SiliconDrive_SiSMAR T .pdf.

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PRODUCT SPECIFICATIONS

SSD-CXXX(I)-3150 DATA SHEET

PRODUCT CAPACITY SPECIFICATIONS

Table 5: Product Capacity Specifications

Numberof

Sectors/

Track

Product Capacity

Capacity (Bytes)

Number of Number of Number

Sectors

Cylinders of Heads

32MB

64MB

128MB

256MB

512MB

1GB

32,702,464

65,601,536

130,154,496

260,571,136

521,773,056

63,872

499

128,128

254,208

508,928

1,019,088

1001

993

994

1011

2030

4066

8186

1,047,674,880 2,046,240

2,098,446,336 4,098,528

4,224,761,856 8,251,488

2GB

4GB

8GB

8,455,200,768 16,514,064 16,383*

* = All IDE drives 8GB and larger use 16383 cylinders, 16 heads, and 63 sectors/track due to

interface restrictions.

ENVIRONMENTAL SPECIFICATIONS

Table 6: Environmental Specifications

Temperature

0ºC to 70ºC (Commercial)

-40ºC to 85ºC (Industrial)

8% to 95% non-condensing

Humidity

Vibration

16.3gRMS, MIL-STD-810F, Method 514.5, Procedure I,

Category 24

Shock

1000G, Half-sine, 0.5ms Duration

50g Pk, MIL-STD-810F, Method 516.5, Procedure I

80,000ft, MIL-STD-810F, Method 500.4, Procedure II

Altitude

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ELECTRICAL SPECIFICATION

SSD-CXXX(I)-3150 DATA SHEET

ELECTRICAL SPECIFICATION

PIN ASSIGNMENTS

The following table describes the SiliconDrive CF 50-pin IDE connector

signals.

Table 7: Pin Assignments

PC Card

Memory

Mode

PC Card

Memory

Mode

PC Card

I/O Mode Mode

IDE-ATA

PC Card

I/O Mode Mode

IDE-ATA

GND

26 CD1#

CD1#

D11¹

D12¹

D13¹

D14¹

CD1#

D11¹

D12¹

D13¹

D14¹

D11¹

D12¹

D13¹

D14¹

D15¹

CE1#

A10

CE1#

A10

OE#

CE1#

A10

32 CE2#

33 VS1#

34 IORD#

35 IOWR#

CE2#

VS1#

CE2#

VS1#

OE#

IORD#

IOWR#

IORD#

IOWR#

A9²

A8²

10 A9

11 A8

V_CC

36 WE#

WE#

A7 ²

V_CC

12 A7

13 V_CC

14 A6

15 A5

16 A4

17 A3

37 RDY/BSY IREQ

RDY/BSY

V_CC

38 V_CC

V_CC

A6²

A5²

A4²

39 CSEL#

40 VS2#

41 RESET#

42 WAIT#

CSEL#

VS2#

CSEL#

VS2#

RESET#

WAIT#

RESET#

WAIT#

A3²

18 A2

19 A1

20 A0

21 D0

22 D1

43 INPACK# INPACK# DMARQ

44 REG#

45 BVD2

46 BVD1

REG#

DMACK#

DASP#

SPKR#

STSCHG# PDIAG#

D8¹

D9¹

D8¹

D9¹

23 D2

D10¹

GND

D10¹

GND

24 WP

25 CD2#

-IOIS16

CD2#

-IOIS16

CD2#

50 GND

Notes:

1 = These signals are required only for 16-bit access, and not required when installed in

8-bit systems.

2 = Should be grounded by the host.

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ELECTRICAL SPECIFICATION

SSD-CXXX(I)-3150 DATA SHEET

SIGNAL DESCRIPTIONS

Table 8: Signal Descriptions

Signal Name

Type Description

I These address lines along with the

A10-A0

8, 10, 11,

12, 14, 15,

16, 17, 18,

19, 20

-REG signal are used to select the

following:

• The I/O port address registers

within the SiliconDrive CF

• The memory-mapped port address

registers within the SiliconDrive CF

• A byte in the card's information

structure and its configuration

control and status registers

A10-A0

This signal is the same as the PC

Card Memory Mode signal.

(PC Card I/O

mode)

A2-A0

18, 19, 20 I

In true IDE mode, only A[2:0] are used

to select the one of eight registers in

the Task File. The remaining address

lines should be grounded by the host.

(True IDE mode)

BVD1

I/O

This signal is asserted high, because

BVD1 is not supported.

(PC Card memory

mode)

-STSCHG

This signal is asserted low to alert the

host to changes in the RDY/-BSY and

Write Protect states while the I/O

interface is configured. This signal’s

use is controlled by the Card

(PC Card I/O

mode)

Configuration and Status register.

-PDIAG

In the true IDE mode, this input/output

is the Pass Diagnostic signal in the

Master/Slave handshake protocol.

(True IDE mode)

BVD2

I/O

This signal is asserted high, as BVD2

is not supported.

(PC Card memory

mode)

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ELECTRICAL SPECIFICATION

SSD-CXXX(I)-3150 DATA SHEET

Table 8: Signal Descriptions (Continued)

Signal Name

Type Description

-SPKR

This line is the Binary Audio output

from the card. If the Card does not

support the Binary Audio function, this

line should be held negated.

(PC Card I/O

mode)

-DASP

In the true IDE mode, this input/output

is the Disk Active/Slave Present

signal in the Master/Slave handshake

protocol.

(True IDE mode)

-CD1, -CD2

26, 25

These Card Detect pins are

connected to ground on the

(PC Card memory

mode)

SiliconDrive CF, and are used by the

host to determine that the SiliconDrive

CF is fully inserted into its socket.

-CD1, -CD2

This signal is the same for all modes.

(PC Card I/O

Mode)

-CD1, -CD2

This signal is the same for all modes.

(True IDE mode)

-CE1, -CE2

7, 32

These input signals are used both to

select the card and to indicate to the

card whether a byte or a word

(PC Card memory

mode)

operation is being performed.

Card Enable

• -CE2 always accesses the odd

byte of the word.

• -CE1 accesses the even byte or

the odd byte of the word depending

on A0 and -CE2.

A multiplexing scheme based on A0,

-CE1, and -CE2 allows 8-bit hosts to

access all data on D0-D7. See

"Attribute Memory Read Operations"

on page 22, "Attribute Memory Write

Operations" on page 23, "Common

Memory Read Operations" on page

40, and "Common Memory Write

Operations" on page 40.

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ELECTRICAL SPECIFICATION

SSD-CXXX(I)-3150 DATA SHEET

Table 8: Signal Descriptions (Continued)

Signal Name

Type Description

-CE1, -CE2

This signal is the same as the PC

Card Memory Mode signal. See "I/O

Space Read Operations" on page 41

and "I/O Space Write Operations" on

page 41.

(PC Card I/O

mode)

Card Enable

-CS0, -CS1

In the true IDE mode, -CS0 is the chip

select for the task file registers while

-CS1 is used to select the Alternate

Status register and the Device Control

(True IDE mode)

-CSEL

This signal is not used for this mode.

(PC Card memory

mode)

-CSEL

This signal is not used for this mode.

(PC Card I/O

mode)

-CSEL

This internally pulled-up signal is used

to configure this device as a master or

slave when configured in the true IDE

mode.

(True IDE mode)

When this pin is:

• Grounded, this device is configured

as a master.

• Open, this device is configured as

a slave.

-INPACK

This signal is not used in this mode.

(PC Card memory

mode)

-INPACK

This signal is asserted by the

SiliconDrive CF when the card is

selected and responding to an I/O

read cycle at the address that is on

the address bus. This signal is used

by the host to control the enabling of

any input data buffers between the

SiliconDrive CF and the CPU.

(PC Card I/O

mode)

Input Acknowledge

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ELECTRICAL SPECIFICATION

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Table 8: Signal Descriptions (Continued)

Signal Name

Type Description

DMARQ

In true IDE mode, this signal is used

for DMA transfers between the host

and device. DMARQ is asserted by

the device when the device is ready to

transfer data to/from the host. The

direction of data transfer is controlled

by -IORD and -IOWR. This signal is

used in a handshake manner with

-DMACK (i.e., the device waits until

the host asserts -DMACK before

negating DMARQ, and reasserts

DMARQ if there is more data to

transfer). The DMARQ/-DMACK

handshake is used to provide flow

control during the transfer.

(True IDE mode)

D15-D00

31, 30, 29, I/O

28, 27, 49,

48, 47, 6,

5, 4, 3, 2,

23, 22, 21

These lines carry the data,

commands, and status information

between the host and the controller.

(PC Card memory

mode)

• D00 is the LSB of the word’s even

byte.

• D08 is the LSB of the word’s odd

byte.

D15-D00

This signal is the same as the PC

Card Memory Mode signal.

(PC Card I/O

mode)

D15-D00

In true IDE mode, all Task File

operations occur in byte mode on the

low-order bus D00-D07, while all data

transfers are 16 bits using D00-D15.

(True IDE mode)

GND

1, 50

Ground.

(PC Card memory

mode)

GND

This signal is the same for all modes.

(PC Card I/O

mode)

GND

(True IDE mode)

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ELECTRICAL SPECIFICATION

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Table 8: Signal Descriptions (Continued)

Signal Name

Type Description

-IORD

This signal is not used in this mode.

(PC Card memory

mode)

-IORD

This is an I/O read strobe generated

by the host. This signal gates I/O data

onto the bus from the SiliconDrive CF

when the card is configured to use the

I/O interface.

(PC Card I/O

mode)

-IORD

In true IDE mode, this signal has the

same function as the PC Card I/O

mode.

(True IDE mode)

-IOWR

This signal is not used in this mode.

(PC Card memory

mode)

-IOWR

The I/O write strobe pulse is used to

clock I/O data on the Card data bus

into the SiliconDrive CF controller

registers when the SiliconDrive CF is

configured to use the I/O interface.

(PC Card I/O

mode)

The clocking occurs on the negative-

to-positive edge of the signal (the

trailing edge).

-IOWR

In true IDE mode, this signal has the

same function as the PC Card I/O

mode.

(True IDE mode)

-OE

This is an output enable strobe

generated by the host interface, which

is used to read:

(PC Card memory

mode)

• Data from the SiliconDrive CF in

memory mode.

• The CIS and configuration

registers.

-OE

In PC Card I/O mode, this signal is

used to read the CIS and

configuration registers.

(PC Card I/O

mode)

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ELECTRICAL SPECIFICATION

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Table 8: Signal Descriptions (Continued)

Signal Name

Type Description

-ATA SEL

To enable true IDE mode, this input

should be grounded by the host.

(True IDE mode)

-RDY/-BSY

In memory mode, this signal is:

(PC Card memory

mode)

• Set high when the SiliconDrive CF

is ready to accept a new data

transfer operation.

• Held low when the card is busy.

The host memory card socket must

provide a pull-up resistor.

At power-up and reset, the RDY/-BSY

signal is held low (busy) until the

SiliconDrive CF has completed its

power-up or reset function. No access

of any type should be made to the

SiliconDrive CF during this time. The

RDY/-BSY signal is held high

(disabled from being busy) whenever

the SiliconDrive CF has been

powered up with +RESET

continuously disconnected or

asserted.

-IREQ

I/O Operation. After the SiliconDrive

CF has been configured for I/O

operation, this signal is used as

-Interrupt Request. This line is strobed

low to generate a pulse mode

interrupt or held low for a level mode

interrupt.

(PC Card I/O

mode)

Input Acknowledge

-IREQ

In true IDE mode, this signal is the

active high Interrupt Request to the

host.

(True IDE mode)

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ELECTRICAL SPECIFICATION

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Table 8: Signal Descriptions (Continued)

Signal Name

Type Description

-REG

This signal is used during memory

cycles to distinguish between

common memory and register

(attribute) memory accesses. This

signal is set:

(PC Card memory

mode)

Attribute Memory

Select

• High for common memory.

• Low for attribute memory.

-REG

The signal must also be active (low)

during I/O cycles when the I/O

address is on the bus.

(PC Card I/O

mode)

-DMACK

In true IDE mode, this signal is used

by the host in response to DMARQ to

initiate DMA transfers. The DMARQ/

-DMACK handshake is used to

provide flow control during the

(True IDE mode)

transfer. When -DMACK is asserted,

-CS0 and -CS1 are not asserted and

transfers are 16-bits wide.

-RESET

When the pin is high, this signal

resets the SiliconDrive CF. The

SiliconDrive CF is reset only at power-

up if this pin is left high or open from

power-up. The SiliconDrive CF is also

reset when the Soft Reset bit in the

Card Configuration Option register is

set.

(PC Card memory

mode)

-RESET

This signal is the same as the PC

Card Memory Mode signal.

(PC Card I/O

mode)

-RESET

In the true IDE mode, this input pin is

the active low hardware reset from the

host.

(True IDE mode)

13, 38

+5V, +3.3V power.

(PC Card memory

mode)

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ELECTRICAL SPECIFICATION

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Table 8: Signal Descriptions (Continued)

Signal Name

Type Description

This signal is the same for all modes.

(PC Card I/O

mode)

This signal is the same for all modes.

(True IDE mode)

-VS1, -VS2

33, 40

Voltage Sense Signals.

• -VS1 is grounded so that the

SiliconDrive CF CIS can be read at

3.3V.

• -VS2 is reserved by PC Card for a

secondary voltage.

-VS1, -VS2

This signal is the same for all modes.

(PC Card I/O

mode)

-VS1, -VS2

(True IDE mode)

-WAIT

The -WAIT signal is driven low by the

SiliconDrive CF to signal the host to

delay completion of a memory or I/O

cycle that is in progress.

(PC Card memory

mode)

-WAIT

This signal is the same as the PC

Card Memory Mode signal.

(PC Card I/O

mode)

-IORDY

In true IDE mode, this output signal

may be used as IORDY.

(True IDE mode)

-WE

This is a signal driven by the host and

used for strobing memory write data

to the registers of the SiliconDrive CF

when the card is configured in the

memory interface mode. This signal is

also used for writing the configuration

registers.

(PC Card memory

mode)

-WE

In PC Card I/O mode, this signal is

used for writing the configuration

registers.

(PC Card I/O

mode)

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ELECTRICAL SPECIFICATION

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Table 8: Signal Descriptions (Continued)

Signal Name

Type Description

-WE

In true IDE mode, this input signal is

not used and should be connected to

(True IDE mode)

by the host.

Write Protect Memory Mode. The

SiliconDrive CF does not have a write

protect switch. This signal is held low

after the completion of the reset

initialization sequence.

(PC Card memory

mode)

-IOIS16

I/O Operation. When the SiliconDrive

CF is configured for I/O operation, pin

24 is used for the -I/O Selected, which

is a 16-bit port (-IOIS16) function. A

low signal indicates that a 16-bit or

odd byte only operation can be

(PC Card I/O

mode)

performed at the addressed port.

-IOIS16

In true IDE mode, this output signal is

asserted low when this device is

expecting a word data transfer cycle.

(True IDE mode)

ABSOLUTE MAXIMUM RATINGS

Table 9: Absolute Maximum Ratings

Parameter Minimum Maximum Units

Symbol

Storage Temperature

-55

125

°C

Operating Temperature

-40

with Respect to GND

-0.3

-0.5

-0.3

6.7

3.8

3.6

Input Voltage

Output Voltage

out

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ELECTRICAL SPECIFICATION

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CAPACITANCE

Table 10: Capacitance

Symbol

Parameter

Maximum

Units

Input Capacitance

Output Capacitance

Bidirectional Capacitance

out

I/O

DC CHARACTERISTICS

Table 11: DC Characteristics

3.3 V ±10%

Minimum Maximum Minimum Maximum

5V ±10%

Symbol Parameter

Units

Power Supply 3.0

Voltage

3.6

4.5

5.5

Input Leakage -

*(1) Current

μA

Output

μA

Leakage *(1)

Current

Read

CCR

CCW

CCS

Current

Write

Current

Standby

0.3

0.5

Current

Input Low

Voltage

-0.3

2.5

0.3 x V

-0.3

0.3 x V

Input High

Voltage

+ 0.3 2.5

V + 0.3 V

Output Low

Voltage

0.4

Output High

Voltage

2.4

*(1) Except the pulled-up/pulled-down pin.

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ELECTRICAL SPECIFICATION

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AC CHARACTERISTICS

Attribute and Common Memory Read Timing

tRC

tGHAX

tA(A)

____

A[10::0],REG

tA(CE)

tAXQX

tELWL

tAVWL

tGHEH

tA(OE)

tDIS(OE)

tEN(OE)

D[15::0]

Figure 2: Attribute and Common Memory Read Timing Diagram

Table 12: Attribute and Common Memory Read Timing

Symbol Parameter

Minimum Maximum Units

Read Cycle Time

100

t (A)

Address Access Time

Card Enable Access Time

Output Enable Access Time

100

t (CE)

100

t (OE)

(OE) Output Disable Time from OE

DIS

(OE) Output Enable Time from OE

Data Valid from Address Change

Address Setup Time

AXQX

AVWL

AXQX

ELWL

GHEH

Address Hold Time

Card Enable Setup Time before OE

Card Enable Hold Time following OE

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ELECTRICAL SPECIFICATION

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Attribute and Common Memory Write Timing

tWR

____

A[10::0],REG

tELWH

tELWL

tGHEH

tAVWH

tWLWH

tWHAX

tAVWL

___

tWHOL

tWLOL

tDVWH

tWHDX

D[15:0](Dout)

tWLQZ

tOHDX

tOLWH

tWHOX

D[15:0](Dout)

Figure 3: Attribute and Common Memory Write Timing Diagram

Table 13: Attribute and Common Memory Write Timing

Symbol Parameter

Minimum Maximum Units

Write Cycle Time

100

Write Pulse Width

WLWH

AVWL

AVWH

ELWH

WHDX

WHAX

WLQZ

OLWH

WHOX

OHDX

WLOL

WHOL

ELWL

GHEH

DVWH

Address Setup Time

Address Setup Time for WE

Card Enable Setup Time for WE

Data Hold Time

Write Recover Time

Output Disable Time from WE

Output Disable Time from OE

Output Enable Time from WE

Output Enable Time from OE

Output Enable Setup for WE

Output Enable Hold from WE

Card Enable Setup Time before WE

Card Enable Hold Time from WE

Data Setup Time

100

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ELECTRICAL SPECIFICATION

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I/O Access Read Timing

A[10::0]

tGHAX

tRLIGL

____

REG

tRHIGH

tCLIGL

tCHIGH

tIGLIGH

___

IORD

tIGHINH

tAVIGL

______

INPACK

tIGLINL

tAXISH

______

IOIS16

tAVISL

tIGHQX

tDVRL

D[15::0]

Figure 4: I/O Access Read Timing Diagram

Table 14: I/O Access Read Timing

Symbol Parameter

Minimum

Maximum Units

Data Delay after IORD

DVRL

Data Hold following IORD

IORD Pulse Width

IGHQX

IGLIGH

AVIGL

GHAX

CLIGL

CHIGH

RLIGL

RHIGH

IGLINL

IGHINH

AVISL

Address Setup before IORD

Address Hold following IORD

CE Setup before IORD

CE Hold following IORD

REG Setup before IORD

REG Hold following IORD

INPACK Delay falling from IORD

INPACK Delay Rising from IORD

IOIS16 Delay Falling from Address

IOIS16 Delay Rising from Address

(1)

AXISH

Note: (1) IOIS16 and INPACK are not supported.

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ELECTRICAL SPECIFICATION

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I/O Access Write Timing

A[10::0]

tAXIGH

tRHIGH

tRLIGL

____

REG

tCHIGH

tCLIGL

tIGLIGH

_____

IOWR

tAVIGL

tAXISH

______

IOIS16

tAVISL

tIGHQX

tIGHDX

D[15::0]

Figure 5: I/O Access Write Timing Diagram

Table 15: I/O Access Write Timing

Symbol

Parameter

Data Hold following IOWR

Minimum

Maximum Units

IGHDX

IGHQX

IGLIGH

AVIGL

AXIGH

CLIGL

CHIGH

RLIGL

RHIGH

AVISL

Data Setup before IOWR

IOWR Pulse Width

Address Setup before IOWR

Address Hold following IOWR

CE Setup before IOWR

CE Hold following IOWR

REG Setup before IOWR

REG Hold following IOWR

IOIS16 Delay Falling from Address

IOIS16 Delay Rising from Address

(1)

AXISH

Note: (1) IOIS16 and INPACK are not supported.

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ELECTRICAL SPECIFICATION

SSD-CXXX(I)-3150 DATA SHEET

True IDE Read/Write Access Timing

tICL

ADDRESS Valid

CS0, CS1, DA[2::0]

tAX16H

tAVRWL

tAXRWH

tRWPW

____ _____

DIOR,DIOW

tDVWL

WRITE

DD[15::00]

tDXWH

READ

DD[15::00]

tDVRL

tIOPW

tDXRH

tIOST

IORDY

______

IOIS16

tAV16L

Figure 6: True IDE Read/Write Access Timing Diagram

Table 16: True IDE Read/Write Access Timing

Symbol Parameter

Minimum Maximum Units

Cycle Time

Address Valid to DIOR,DIOW Setup Time 15

100

ICL

AVRWL

RWPW

DVWL

DXWH

DVRL

DXRH

AV16L

AX16H

AXRWH

IOST

DIOR, DIOW Pulse Width

DIOW Data Setup Time

DIOW Data Hold Time

DIOR Data Setup Time

DIOR Data Hold Time

Address Valid to IOCS16 Assertion

Address Valid to IOCS16 Negation

DIOW,DIOR to Address Valid Hold Time

IORDY Setup Time

(1)

IORDY Pulse Width

IOPW

Note: (1) IOIS16 and INPACK are not supported.

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ELECTRICAL SPECIFICATION

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True IDE Multiword DMA Read/Write Access Timing

This function does not apply to SiliconDrives that have DMA disabled.

Figure 7: True IDE Multiword DMA Read/Write Access Timing

Table 17: True IDE Multiword DMA Read/Write Access Timing

Symbol Parameter

Minimum

Maximum Units

Cycle Time (mode 2)

100

RWC

RWPW

RDA

DIOR/DIOW Pulse Width

DIOR Data Access

DIOR/DIOW Data Setup Time

DIOW Data Hold Time

RWSU

DIOR Data Hold Time

DMACK to DIOR/DIOW Setup Time

DIOR/DIOW to DMACK Hold Time

DIOR/DIOW negated Pulse Width

DIOR/DIOW to DMARQ Delay

CS(1:0) valid to DIOR/DIOW

CS(1:0) Hold Time

DMRW

RWDH

RWN

RWD

CSRW

CSH

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ATTRIBUTE MEMORY DESCRIPTION AND OPERATION

SSD-CXXX(I)-3150 DATA SHEET

ATTRIBUTE MEMORY DESCRIPTION AND OPERATION

The attribute memory plane can be read or written to by asserting the REG#

signal, qualified by the appropriate combination of CE1#, OE#, and WE#. An

attribute memory map describing the type and location of the information

maintained in the attribute memory plane is provided in "Attribute Memory

Map" on page 24.

With respect to SiliconDrive CF, attribute memory consists of two sections:

• Card Information Structure (CIS), which contains a description of the Card’s

capabilities and specifications.

• Function Configuration Registers (FCRs), which consists of four registers,

that can be read or written to by a host to configure the Card for specific

purposes.

ATTRIBUTE MEMORY READ OPERATIONS

Attribute memory read operations are enabled by asserting REG#, OE#, and

CE1# low. Odd byte read operations from the attribute memory plane are not

valid.

Table 18: Attribute Memory Read Operations

Function

Mode

REG# CE1# CE2# A0

OE# WE# D[15:8] D[7:0]

Standby

High-Z

Even

Byte Access

Not Valid

Word Access L

Not Valid Even

Odd Byte

Not Valid High-Z

Only Access

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ATTRIBUTE MEMORY DESCRIPTION AND OPERATION

SSD-CXXX(I)-3150 DATA SHEET

ATTRIBUTE MEMORY WRITE OPERATIONS

Attribute memory write operations are enabled by asserting REG#, WE#, and

CE1# low. Odd byte write operations from the attribute memory plane are not

valid.

Table 19: Attribute Memory Write Operations

Function

Mode

REG# CE1# CE2# A0

OE# WE# D[15:8] D[7:0]

Standby

High-Z

Even

Byte Access

Not Valid

Word Access L

Not Valid Even

Odd Byte

Not Valid High-Z

Only Access

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ATTRIBUTE MEMORY DESCRIPTION AND OPERATION

SSD-CXXX(I)-3150 DATA SHEET

ATTRIBUTE MEMORY MAP

As stated earlier, the Attribute Memory plane is comprised of two components,

the CIS and the FCRs. The following tables detail the type, location, and read/

write requirements for each of the four FCRs maintained in the attribute

memory plane.

Table 20: Attribute Memory Map

Operation Addr CE1# REG# WE# OE#

Card Information Structure Read

Write

Configuration Option

Read

Write

Read

200h 0

202h 0

Card Configuration and

Status

Write

Read

Write

Read

Write

202h 0

204h 0

206h 0

Pin Replacement

Socket and Copy

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ATTRIBUTE MEMORY DESCRIPTION AND OPERATION

SSD-CXXX(I)-3150 DATA SHEET

CARD INFORMATION STRUCTURE

The CIS is data that describes the SiliconDrive CF, and is described by the

CFA standard. This information can be used by the host system to determine a

number of things about the Card that has been inserted. For information

regarding the exact nature of this data and how to design the host software to

interpret it, refer to the PC Card Standard Metaformat Specification.

Table 21: Card Information Structure

Attribute

Offset

Data

Description of Contents

CIS Function

00h

02h

04h

01h

03h

D9h

CISTPL_DEVICE

Device information tuple

Link length is 3 bytes

Tuple code

Link to next tuple

Device Type

Code

Device

Speed

•

I/O device

No WP

Speed = 100ns

•

Device ID

WPS

Device speed

Dh = I/O

06h

08h

0Ah

0Ch

0Eh

01h

FFh

1Ch

04h

02h

2KB of address space

End of device

Device size

List End Marker

END marker

Tuple code

CISTPL_DEVICE_OC

TPL_LINK

Other conditions device in tuple code

Link length is 4 bytes

3V, wait is Not Used

Link to next tuple

EXT Reserved

MWAIT

Other conditions

information field

10h

D9h

Device Type

Device

Speed

•

Device type = DH: I/O

Device WPS = 1: No WP

Device speed = 1: 250ns

12h

14h

16h

18h

1Ah

01h

FFh

18h

02h

DFh

2K units

List End Marker

2KB of address space

End of device

Device size

End marker

Tuple code

CISTPL_JEDEC_C

TPL_LINK

JEDEC ID common memory

Link length is 2 bytes

Link to next tuple

PCMCIA Manufacturer’s JEDEC Manufacturer’s ID code

JEDEC ID

1Ch

1Eh

20h

22h

01h

20h

04h

PCMCIA JEDEC Device Code

CISTPL_MANFID

TPL_LINK

Second byte of JEDEC ID

Manufacturer’s ID code

Tuple code

00h Low Byte of PCMCIA Manufacturer’s JEDEC manufacturer’s ID

Code

Low byte of

manufacturer’s

code

24h

00h

High Byte of PCMCIA

Manufacturer’s Code

Code of 0, because the other byte is the High byte of the

JEDEC 1 byte manufacturer’s ID

manufacturer’s

code

26h

28h

00h

Low Byte of Product Code

High Byte of Product Code

Manufacturer’s code for SiliconDrive CF Low byte of the

product code

Manufacturer’s code for SiliconDrive CF High byte of the

product code

2Ah

2Ch

21h

02h

CISTPL_FUNCID

TPL_LINK

Function ID tuple

Tuple code

Link length is 2 bytes

Link to next tuple

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ATTRIBUTE MEMORY DESCRIPTION AND OPERATION

SSD-CXXX(I)-3150 DATA SHEET

Table 21: Card Information Structure (Continued)

Attribute

Offset

Data

Description of Contents

CIS Function

2Eh

04h

TPLFID_FUNCTION = 04H

Reserved

Disk function, which may be silicon or

removable

PC Card function

code

30h

01h

•

R = 0: No BIOS ROM

P = 1: Configure card at power-on byte

System initialization

32h

34h

36h

22h

02h

CISTPL_FUNCE

TPL_LINK

Function extension tuple

Link length is 2 bytes

Tuple code

Link to next tuple

01h Disk Function Extension Tuple Type Disk interface type

Extension tuple type

for disk

38h

3Ah

3Ch

3Eh

01h

22h

03h

Disk Interface Type

CISTPL_FUNCE

TPL_LINK

PC Card interface type

Function extension tuple

Link length is 3 bytes

Interface type

Tuple code

Link to next tuple

02h Disk Function Extension Tuple Type Basic PCMCIA-ATA extension tuple

Extension tuple type

for disk

40h

04h

Reserved

No Vpp, silicon, single drive

Basic ATA option

parameters byte 1

•

V = 0: No Vpp required

S = 0: Silicon

U = 1: Unique serial number

D = 0: Single drive on Card

42h

07h

P3 P2 P1 P0 • P0: Sleep mode supported

Basic ATA option

parameters byte 2

•

P1: Standby mode supported

P2: Idle mode supported

P3: Drive auto power control

N: Some configuration excludes 3X7

E: Index bit is emulated

I: Twin IOIS16# data register only

R: Reserved

44h

46h

48h

1Ah

05h

01h

CISTPL_CONFIG

TPL_LINK

Configuration tuple

Tuple code

Link length is 5 bytes

Link to next tuple

RAS

RMS

RAS

•

RFS: Reserved

Size of fields byte

TPCC_SZ

RMS: TPCC RMSK size -1 = 0

RAS: TPCC_RADR size -1 = 1

1-byte register mask

2-byte configuration base address

4Ah

4Ch

07h

00h

TPCC_LAST

Entry with configuration index of 7 is final Last entry of

entry in table

configuration

registers

TPCC_RADR (LSB)

TPCC_RADR (MSB)

Configuration registers are located at

200H in REG space

Location of

configuration

registers

4Eh

50h

02h

0Fh

Reserved

•

I: Configuration index

C: Configuration and status

P: Pin replacement

Configuration

registers present

mask

S: Socket and copy

TPCC_RMSK

52h

54h

1Bh

0Bh

CISTPL_TABLE_ENTRY

TPL_LINK

Configuration table entry tuple

Link length is 11 bytes

Tuple code

Link to next tuple

SILICONSYSTEMS PROPRIETARY

This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc.

All unauthorized use and/or reproduction is prohibited.

3150C-10DSR

PAGE 26

FEBRUARY 2, 2009

ATTRIBUTE MEMORY DESCRIPTION AND OPERATION

SSD-CXXX(I)-3150 DATA SHEET

Table 21: Card Information Structure (Continued)

Attribute

Offset

Data

Description of Contents

CIS Function

56h

C0h

Configuration index

Memory-mapped I/O configuration

Configuration table

index byte

TPCE_INDX

•

I = 1: Interface byte follows

D = 1: Default entry

Configuration index = 0

58h

C0h

A1h

Interface Type

•

W = 0: Wait not used

R = 1: Ready active

P = 0: WP used

B = 0: BVD1 and BVD2 not used

IF type = 0: Memory interface

Interface description

field TPCE_IF

5Ah

MS IR IO

•

M = 1: Miscellaneous information

present

MS = 01: Memory space information

single 2-byte length

IR = 0: No interrupt information

present

IO = 0: No I/O port information

present

Feature selection

byte TPCE_FS

•

T = 0: No timing information present

P = 1: V only information

5Ch

27h

DI PI AI SI HV LV NV Nominal voltage only follows

Power parameters

for V

•

R: Reserved

DI: Powerdown current information

PI: Peak current information

AI: Average current information

SI: Static current information

HV: Maximum voltage information

LV: Minimum voltage information

NV: Nominal voltage information

5Eh

60h

62h

64h

55h

4Dh

5Dh

75h

Mantissa

Exponent Nominal voltage = 5V

nominal value

minimum value

maximum value

Exponent

nominal 4.5V

nominal 5.5V

Mantissa

Maximum average current over 10ms is Maximum average

80mA

current

66h

68h

6Ah

08h

00h

21h

Length in 256 bytes pages (LSB) Length of memory space is 2KB

Length in 256 bytes pages (MSB) Length of memory space is 2KB

Memory space

description

structures

(TPCE_MS)

Memory space

description

structures

(TPCE_MS)

•

X = 0: No more miscellaneous fields Miscellaneous

R: Reserved

features field

TPCE_MI

P = 1: Powerdown supported

RO = 0: Not read only mode

A = 0: Audio not supported

T = 0: Single drive

6Ch

6Eh

1Bh

06h

CISTPL_TABLE_ENTRY

TPL_LINK

Configuration table entry tuple

Link length is 6 bytes

Tuple code

Link to next tuple

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All unauthorized use and/or reproduction is prohibited.

3150C-10DSR

PAGE 27

FEBRUARY 2, 2009

ATTRIBUTE MEMORY DESCRIPTION AND OPERATION

SSD-CXXX(I)-3150 DATA SHEET

Table 21: Card Information Structure (Continued)

Attribute

Offset

Data

Description of Contents

CIS Function

70h

00h

IR IQ

Memory-mapped I/O configuration

Configuration table

index byte

TPCE_INDX

•

I = 0: No interface byte

D = 0: No default entry

Configuration index = 0

72h

01h

MS IR IO

•

M = 0: No miscellaneous information Feature selection

MS = 00: No memory space

information

byte

TPCE_FS

•

IR = 0: No interrupt information

present

IO = 0: No I/O port information

present

•

T = 0: No timing information present

P = 1: V only information

74h

21h

DI PI AI SI HV/LV/NV Nominal voltage only follows

Power parameters

for V

•

R: Reserved

DI: Powerdown current information

PI: Peak current information

AI: Average current information

SI: Static current information

HV: Maximum voltage information

LV: Minimum voltage information

NV: Nominal voltage information

76h

B5h

Mantissa

Extension

Mantissa

Exponent

Nominal voltage = 3.0 V

+0.3 V

nominal value

78h

7Ah

1Eh

4Dh

Extension byte

Exponent

Maximum average current over 10ms is Maximum average

45 mA

current

7Ch

7Eh

80h

1Bh

0Dh

C1h

CISTPL_TABLE_ENTRY

TPL_LINK

Configuration table entry tuple

Link length is 10 bytes

Tuple code

Link to next tuple

Configuration

INDEX

Contiguous I/O mapped ATA registers

configuration

Configuration table

index byte

TPCE_INDX

•

I = 1: Interface byte follows

D = 1: Default entry

Configuration index = 1

82h

84h

41h

99h

Interface Type

•

W = 0: Wait not used

R = 1: Ready active

P = 0: WP not used

B = 0: BVS1 and BVD2 not used

IF type = 1: I/O interface

Interface description

field TPCE_IF

MS IR IO

•

M = 1: Miscellaneous information

present

Feature selection

byte TPCE_FS

•

MS = 00: No memory space

information

•

IR = 1: Interrupt information present

IO = 1: I/O port information present

T = 0: No timing information present

P = 1: V only information

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FEBRUARY 2, 2009

ATTRIBUTE MEMORY DESCRIPTION AND OPERATION

SSD-CXXX(I)-3150 DATA SHEET

Table 21: Card Information Structure (Continued)

Attribute

Offset

Data

Description of Contents

CIS Function

86h

27h

DI PI AI SI HV LV NV Nominal voltage only follows

Power parameters

for V

•

R: Reserved

DI: Powerdown current information

PI: Peak current information

AI: Average current information

SI: Static current information

HV: Maximum voltage information

LV: Minimum voltage information

NV: Nominal voltage information

88h

8Ah

8Ch

8Eh

55h

4Dh

5Dh

75h

Mantissa

Exponent

Nominal voltage = 5V

nominal value

minimum value

maximum value

nominal 4.5V

nominal 5.5V

Maximum average current over 10ms is Maximum average

80mA

current

90h

92h

64h

F0h

AddrLine

•

S = 1: 16-bit hosts supported

E = 1: 8-bit hosts supported

IO AddrLine: 4 lines decoded

I/O space

description field

TPCE_IO

•

S = 1: Share logic active

P = 1: Pulse mode IRQ supported

L = 1: Level mode IRQ supported

M = 1: Bit mask of IRQs present

V = 0: No vender unique IRQ

B = 0: No bus error IRQ

Interrupt request

description structure

TPCE_IR

I = 0: No IO check IRQ

N = 0: No NMI

94h

96h

98h

FFh IR IR IR IR IR IR IR IR SiliconSystems recommends the IRQ

level to be routed 0 to 15

Mask extension

byte 1 TPCE_IR

FFh IR IR IR IR IR IR IR IR SiliconSystems recommends routing to Mask extension

any normal, maskable IRQ.

byte 2 TPCE_IR

15 14 13 12 11 10

21h

•

X = 0: No more miscellaneous fields Miscellaneous

R: Reserved

P = 1: Powerdown supported

RO = 0: Not read only mode

A = 0: Audio not supported

T = 0: Single drive

features field

TPCE_MI

9Ah

9Ch

9Eh

1Bh

06h

01h

CISTPL__TABLE_ENTRY

TPL_LINK

Configuration table entry tuple

Link length is 6 bytes

Tuple code

Link to next tuple

Configuration Index

Contiguous I/O mapped ATA registers

configuration

Configuration table

index

Byte TPCE_INDX

•

I = 0: No Interface byte

D = 0: No Default entry

Configuration index = 1

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ATTRIBUTE MEMORY DESCRIPTION AND OPERATION

SSD-CXXX(I)-3150 DATA SHEET

Table 21: Card Information Structure (Continued)

Attribute

Offset

Data

Description of Contents

CIS Function

A0h

01h

MS IR IO

•

M = 0: No miscellaneous information Feature selection

MS = 00: No memory space

information

byte TPCE_FS

•

IR = 0: No interrupt information

present

IO = 0: No I/O port information

present

•

T = 0: No timing information present

P = 1: V only information

A2h

21h

DI PI AI SI HV LV NV Nominal voltage only follows

Power parameters

for V

•

R: Reserved

DI: Powerdown current information

PI: Peak current information

AI: Average current information

SI: Static current information

HV: Maximum voltage information

LV: Minimum voltage information

NV: Nominal voltage information

A4h

B5h

Mantissa

Exponent

Nominal voltage = 3.0V

+0.3V

nominal value

A6h

A8h

1Eh

4Dh

Mantissa

Exponent

Extension byte

Maximum average current over 10ms is Maximum average

45mA

current

AAh

ACh

AEh

1Bh

12h

C2h

CISTPL_TABLE_ENTRY

TPL_LINK

Configuration table entry tuple

Link length is 18 bytes

Extension byte

Link to next tuple

Configuration Index

ATA primary I/O mapped configuration Configuration table

index byte

•

I = 1: Interface byte follows

D = 1: default entry follows

Configuration index = 2

TPCE_INDX

B0h

B2h

41h

99h

Interface Type

•

W = 0: Wait not used

R = 1: Ready active

P = 0: WP not used

B = 0: BVS1 and BVD2 not used

IF type = 1: I/O interface

Interface description

field TPCE_IF

MS IR IO

•

M = 1: Miscellaneous information

present

Feature selection

byte TPCE_FS

•

MS = 00: No memory space

information

•

IR = 1: Interrupt information present

IO = 1: I/O port information present

T = 0: No timing information present

P = 1: V only information

B4h

27h

DI PI AI SI HV LV NV Nominal voltage only follows

Power parameters

for V

•

R: Reserved

DI: Powerdown current information

PI: Peak current information

AI: Average current information

SI: Static current information

HV: Maximum voltage information

LV: Minimum voltage information

NV: Nominal voltage information

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ATTRIBUTE MEMORY DESCRIPTION AND OPERATION

SSD-CXXX(I)-3150 DATA SHEET

Table 21: Card Information Structure (Continued)

Attribute

Offset

Data

Description of Contents

Nominal voltage = 5V

CIS Function

B6h

B8h

BAh

BCh

55h

4Dh

5Dh

75h

Mantissa

Exponent

nominal value

minimum value

maximum value

nominal 4.5V

nominal 5.5V

Maximum average current over 10ms is Maximum average

80mA

current

BEh

EAh

AddrLine

•

R = 1: Range follows

I/O space

description field

TPCE_IO

S = 1: 16-bit hosts supported

E = 1: 8-bit hosts supported

IO AddrLines: 10 lines decoded

C0h

C2h

61h LS AS

N Range

•

LS = 1: Size of lengths is 1 byte

AS = 2: Size of address is 2 bytes

N Range = 1: Address Range-1

I/O range format

description

F0h

First I/0 Base Address

First I/O base address (LSB)

First I/O range

address

C4h

C6h

01h

07h

First I/0 Base Address

First I/O base address (MSB)

First I/O length -1

First I/O range

length

C8h

F6h

Second I/O Base Address

Second I/O base address (LSB)

Second I/O range

address

CAh

CCh

03h

01h

Second I/O Base Address

Second I/O Range Length

Second I/O base address (MSB)

Second I/O length -1

Second I/O range

length

CEh

EEh

IRQ

Level

•

S = 1: Share logic active

Interrupt request

description structure

TPCE_IR

P = 1: Pulse mode IRQ supported

L = 1: Level mode IRQ supported

M = 0: Bit mask of IRQs present —

IRQ level is IRQ14

D0h

21h

•

X = 0: No more miscellaneous fields Miscellaneous

R: Reserved

P = 1: Powerdown supported

RO = 0: Not read only mode

A = 0: Audio not supported

T = 0: Single drive

features field

TPCE_MI

D2h

D4h

D6h

1Bh

06h

02h

CISTPL_TABLE_ENTRY

TPL_LINK

Configuration table entry tuple

Link length is 6 bytes

Tuple code

Link to next tuple

Configuration Index

ATA primary I/O mapped configuration Configuration table

index byte

•

I = 0: No Interface byte

D = 0: No Default entry

Configuration index = 2

TPCE_INDX

D8h

01h

Configuration Index

Contiguous I/O mapped ATA registers

configuration

Configuration table

index byte

TPCE_INDX

•

I = 0: No interface byte

D = 0: No default entry

Configuration index = 1

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ATTRIBUTE MEMORY DESCRIPTION AND OPERATION

SSD-CXXX(I)-3150 DATA SHEET

Table 21: Card Information Structure (Continued)

Attribute

Offset

Data

Description of Contents

CIS Function

DAh

21h

MS IR IO

•

M = 0: No miscellaneous information Feature selection

MS = 00: No memory space

information

byte TPCE_FS

•

IR = 0: No interrupt information

present

IO = 0: No I/O port information

present

•

T = 0: No timing information present

P = 1: V only information

DCh

B5h

DI PI AI SI HV LV NV Nominal voltage only follows

Power parameters

for V

•

R: Reserved

DI: Powerdown current information

PI: Peak current information

AI: Average current information

SI: Static current information

HV: Maximum voltage information

LV: Minimum voltage information

NV: Nominal voltage information

DEh

1Eh

Mantissa

Exponent

Nominal voltage = 3.0V

nominal value

E0h

E2h

E4h

E6h

4Dh

1Bh

12h

C3h

Extension

+0.3V

Extension byte

Tuple code

CISTPL_TABLE_ENTRY

TPL_LINK

Configuration table entry tuple

Link length is 18 bytes

Link to next tuple

MS IR IO

•

M = 0: No miscellaneous information Feature selection

MS = 00: No memory space

information

byte TPCE_FS

•

IR = 0: No interrupt information

present

IO = 0: No I/O port information

present

•

T = 0: No timing information present

P = 1: V only information

E8h

41h

DI PI AI SI HV LV NV Nominal voltage only follows

Power parameters

for V

•

R: Reserved

DI: Powerdown current information

PI: Peak current information

AI: Average current information

SI: Static current information

HV: Maximum voltage information

LV: Minimum voltage information

NV: Nominal voltage information

EAh

99h

MS IR IO

•

M = 1: No miscellaneous information Feature selection

MS = 00: No Memory space

information

byte TPCE_FS

•

IR = 1: No interrupt information

present

IO = 1: No I/O port information

present

•

T = 0: No timing information present

P = 01: V only information

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ATTRIBUTE MEMORY DESCRIPTION AND OPERATION

SSD-CXXX(I)-3150 DATA SHEET

Table 21: Card Information Structure (Continued)

Attribute

Offset

Data

Description of Contents

CIS Function

ECh

27h

DI PI AI SI HV LV NV Nominal voltage only follows

Power parameters

for V

•

R: Reserved

DI: Powerdown current information

PI: Peak current information

AI: Average current information

SI: Static current information

HV: Maximum voltage information

LV: Minimum voltage information

NV: Nominal voltage information

EEh

F0h

F2h

F4h

55h

4Dh

5Dh

75h

Mantissa

Exponent

Nominal voltage = 5V

nominal value

minimum value

maximum value

nominal 4.5V

nominal 5.5V

Maximum average current over 10ms is Maximum average

80mA

current

F6h

EAh

AddrLine

•

R = 1: Range follows

I/O space

description field

TPCE_IO

S = 1: 16-bit hosts supported

E = 1: 8-bit hosts supported

IO AddrLines: 10 lines decoded

F8h

FAh

61h LS AS

N Range

•

LS = 1: Size of lengths is 1 byte

AS = 2: Size of address is 2 bytes

N Range = 1: Address range -1

I/O range format

description

70h

First I/O base address (LSB)

First I/O range

address

FCh

FEh

01h

07h

First I/O base address (MSB)

First I/O length -1

First I/O range

length

100h

76h

Second I/O base address (LSB)

Second I/O range

address

102h

104h

03h

01h

Second I/O base address (MSB)

Second I/O length

Second I/O range

length

106h

108h

EEh

21h

IRQ

Level

•

S = 1: Share logic active

P = 1: Pulse mode IRQ supported

L = 1: Level mode IRQ supported

M = 0: Bit mask of IRQs present — miscellaneous

IRQ level is IRQ14

Interrupt request

description structure

TPCE_IR

features field

TPCE_MI

•

X = 0: No more miscellaneous fields -

R: Reserved

P = 1: Powerdown supported

RO = 0: Not read only mode

A = 0: Audio not supported

T = 0: Single drive

10Ah

10Ch

1Bh

06h

CISTPL_TABLE_ENTRY

TPL_LINK

Configuration table entry tuple

Link length is 6 bytes

Tuple code

Link to next tuple

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ATTRIBUTE MEMORY DESCRIPTION AND OPERATION

SSD-CXXX(I)-3150 DATA SHEET

Table 21: Card Information Structure (Continued)

Attribute

Offset

Data

Description of Contents

CIS Function

10Eh

03h

Configuration Index

ATA primary I/O mapped configuration Configuration table

index byte

•

I = 0: No interface byte

D = 0: No default entry

Configuration index = 2

TPCE_INDX

110h

01h

MS IR IO

•

M = 0: No miscellaneous information Feature selection

MS = 00: No memory space

information

byte TPCE_FS

•

IR = 0: No interrupt information

present

IO = 0: No I/O port information

present

•

T = 0: No timing information present

P = 1: V only information

112h

21h

DI PI AI SI HV LV NV Nominal voltage only follows

Power parameters

for V

•

R: Reserved

DI: Powerdown current information

PI: Peak current information

AI: Average current information

SI: Static current information

HV: Maximum voltage information

LV: Minimum voltage information

NV: Nominal voltage information

114h

B5h

Mantissa

Extension

Mantissa

Exponent

Nominal voltage = 3.0V

+0.3V

nominal value

116h

118h

1Eh

4Dh

Extension byte

Exponent

Maximum average current over 10ms is Maximum average

45mA

current

11Ah

11Ch

11Eh

1Bh

04h

07h

CISTPL_MANFID

Manufacturer’s ID code

Link length is 4 bytes

Tuple code

Link to next tuple

TPCE_INDX

TPL_LINK

Configuration Index

AT fixed disk secondary I/O 3.3V

configuration

120h

00h

MS IR IO

P: Power information type

TPCL_FS

122h

124h

126h

128h

12Ah

12Ch

12Eh

130h

132h

134h

136h

138h

13Ah

28h

D3h

14h

00h

15h

1Ah

04h

01h

53h

49h

4Ch

49h

43h

Manufacturer code for SiliconDrive CF Reserved

CISTPL_NO_LINK

No link control tuple

Tuple code

Link is 0 bytes

Link to next tuple

CISTPL_VERS_1

Level 1 version

Tuple code

TPL_LINK

Link length is 26h bytes

Link to next tuple

TPPLV1_MAJOR

PC Card 2.0/JEIDA4.1

END marker

TPPLV1_MINOR

PC Card 2.0/JEIDA4.1

Tuple code

Information string

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ATTRIBUTE MEMORY DESCRIPTION AND OPERATION

SSD-CXXX(I)-3150 DATA SHEET

Table 21: Card Information Structure (Continued)

Attribute

Offset

Data

Description of Contents

CIS Function

13Ch

13Eh

140h

142h

144h

146h

4Fh

4Eh

53h

59h

53h

54h

45h

4Dh

53h

00h

56h

45h

52h

32h

2Eh

30h

00h

FFh

14Ah

14Ch

14Eh

150h

152h

154h

156h

158h

15Ah

15Ch

Space

160h

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ATTRIBUTE MEMORY DESCRIPTION AND OPERATION

SSD-CXXX(I)-3150 DATA SHEET

CONFIGURATION OPTION REGISTER (200H)

The Configuration Option register is used to configure the SiliconDrive CF,

define the address decoding, and initiate the software RESET sequence.

Table 22: Configuration Option Register (200h)

Operation

Read/

Write

SRESET LevIREQ

Configuration Index

Default

Value

Bit(s)

Description

SRESET

When set, this bit initiates a software-reset sequence, which

is equivalent to a power-on reset or hardware reset.

LevlREQ

IREQ# interrupt signal level mode select:

• Logic 0 = Pulse mode

• Logic 1 = Level mode

Configuration • Memory-mapped mode

000000B

000001B

000010B

000011B

Index

• Independent I/O mode

• Primary mode

• Secondary mode

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ATTRIBUTE MEMORY DESCRIPTION AND OPERATION

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CONFIGURATION AND STATUS REGISTER (202H)

The Configuration and Status Register (CSR) informs the host of any status

changes with regard to power-down.

Table 23: Configuration and Status Register (202h)

Operation

Read

Write

Changed SigChg IOis8

PwrDn Int

Default

Value

Bit(s)

Description

Changed

Indicates that either CREADY (D5) or CWPort (D4) of the Pin

Replacement register is set. Additionally, this bit changes state

as the Powerdown (D2) bit changes.

SigChg

Iois8

Outputs the inverse state of the Changed bit to the hardware

interface signal STSCHG# at the card interface.

Informs the host of the valid data bus width for the operations in

progress:

• 0 = 16-bit data transfer

• 1 = 8-bit data transfer

PwrDwn

Indicates the state of the Card, which is either operating -0 or

powerdown mode 1. During powerdown mode, no commands

are accepted. Additionally, the host may not initiate a

powerdown request when the card is busy via the Status

Int

Indicates the inverse of the IREQ# status signal.

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ATTRIBUTE MEMORY DESCRIPTION AND OPERATION

SSD-CXXX(I)-3150 DATA SHEET

PIN PLACEMENT REGISTER (204H)

Table 24: Pin Placement Register (204h)

Operation

CBVD1 CBVD2 CRDY CWProt RBVD1 RBVD2 RRDY RWProt

Read/

Write

Default

Value

Bit(s)

Description

CRDY

CWProt

RRDY

Indicates a bit change in the RRDY (D1) bit.

Indicates a bit change in the RWProt (D0) bit.

When set:

• High 1 informs the host that the card is ready

• Low 0 state indicates the card is busy

RWProt

Indicates Write Protect is enabled when set to 1, and disabled

when 0.

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ATTRIBUTE MEMORY DESCRIPTION AND OPERATION

SSD-CXXX(I)-3150 DATA SHEET

SOCKET AND COPY REGISTER (206H)

Table 25: Socket and Copy Register (206h)

Operation

Read/Write

RFU

Copy Number

Socket Number

Default Value

Bit(s)

Description

Reserved for future use.

Indicates the card number. Allows the host to differentiate

RFU

Copy

Number

between identical cards by writing to the bit of the card that is

being accessed. This value is compared to the DRV bit in the

ATA Drive/Head register.

• Card 0: 000B = (D6, D5, D4) (default)

• Card 1: 001B = (D6, D5, D4) (alternate)

Socket

Number

The host writes the socket number that identifies the inserted

card.

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COMMON MEMORY DESCRIPTION AND OPERATION

SSD-CXXX(I)-3150 DATA SHEET

COMMON MEMORY DESCRIPTION AND OPERATION

Common memory space can be accessed when the SiliconDrive is configured

in memory-mapped mode.

COMMON MEMORY READ OPERATIONS

Common memory read operations are issued by asserting CE1#, CE2#, or

both, and OE# low, REG#, and WE# must be inactive.

Table 26: Common Memory Read Operations

Function Mode REG# CE1# CE2# A0 OE#

WE#

D[15:8] D[7:0]

Standby

High-Z High-Z

High-Z Even

High-Z Odd

Byte Access

Word Access

Odd

Even

Odd Byte Only

Access

High-Z

COMMON MEMORY WRITE OPERATIONS

Common memory write operations are issued by asserting CE1#, CE2#, or

both, and WE# low, REG#, and OE# must be inactive.

Table 27: Common Memory Write Operations

Function Mode REG# CE1# CE2# A0 OE#

WE#

D[15:8] D[7:0]

Standby

High-Z High-Z

High-Z Even

High-Z Odd

Byte Access

Word Access

Odd

Even

Odd Byte Only

Access

High-Z

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I/O SPACE DESCRIPTION AND OPERATION

SSD-CXXX(I)-3150 DATA SHEET

I/O SPACE DESCRIPTION AND OPERATION

I/O SPACE READ OPERATIONS

Table 28: I/O Space Read Operations

Function Mode REG# CE1# CE2# A0 IORD# IOWR# D[15:8] D[7:0]

Standby

High-Z High-Z

High-Z Even

High-Z Odd

Byte Access

Word Access

I/O Inhibit

Odd

High-Z High-Z

Odd High-Z

Even

Odd Byte Only

Access

I/O SPACE WRITE OPERATIONS

Table 29: I/O Space Write Operations

Function Mode REG# CE1# CE2# A0 IORD# IOWR# D[15:8] D[7:0]

Standby

Byte Access

Even

Odd

Even

Word Access

I/O Inhibit

Odd

Odd Byte Only

Access

Odd

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ATA AND TRUE IDE REGISTER DECODING

SSD-CXXX(I)-3150 DATA SHEET

ATA AND TRUE IDE REGISTER DECODING

SiliconDrive can be configured as either a a memory-mapped or an an I/O

devices. As noted earlier, communication to and from the drive is

accomplished using the ATA Command Block.

MEMORY-MAPPED REGISTER DECODING

In memory-mapped mode, the SiliconDrive registers are accessed via

standard memory references (i.e., OE# and WE#). The ATA registers are

mapped to common memory space in a 2KB window starting at address 0.

Table 30: Memory-Mapped Register Decoding

Reg# Offset A10 A9:A4 A3 A2 A1 A0 OE# = L

WE# = L

Even Data

Read

Even Data

Write

Error

Feature

Sector Count Sector Count

Sector

Number

Cylinder Low Cylinder Low

Cylinder High Cylinder High

Drive/Head

Status

Drive/Head

Command

Duplicate

Even Data

Read

Duplicate

Even Data

Write

Duplicate Odd Duplicate Odd

Data Read

Data Write

Duplicate

Error

Duplicate

Feature

Alternate

Status

Device Control

Drive Address Reserved

Even Data

Read

Even Data

Write

Odd Data

Read

Odd Data

Write

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ATA AND TRUE IDE REGISTER DECODING

SSD-CXXX(I)-3150 DATA SHEET

INDEPENDENT I/O MODE REGISTER DECODING

Independent I/O mode or contiguous I/O mode requires the host to decode a

continuous block of 16 I/O registers to select the SiliconDrive.

Table 31: Independent I/O Mode Register Decoding

Reg# Offset A10 A9:A4 A3 A2 A1 A0 OE# = L

WE# = L

Even Data

Read

Even Data

Write

Error

Feature

Sector Count Sector Count

Sector

Number

Cylinder Low Cylinder Low

Cylinder High Cylinder High

Drive/Head

Status

Drive/Head

Command

Duplicate

Even Data

Read

Duplicate

Even Data

Write

Duplicate Odd Duplicate Odd

Data Read Data Write

Duplicate Error Duplicate

Feature

Alternate

Status

Device Control

Drive Address Reserved

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ATA AND TRUE IDE REGISTER DECODING

SSD-CXXX(I)-3150 DATA SHEET

PRIMARY AND SECONDARY I/O MAPPED REGISTER DECODING

Table 32: Primary and Secondary I/O Mapped Register Decoding

A9:A4 A9:A4

Primary Secondary

Reg# A10

A3 A2 A1 A0 IORD# = L IOWR# = L

1Fxh

17xh

Even Data

Read

Even Data

Write

1Fxh

17xh

Error

Feature

Sector

Count

Sector

Count

1Fxh

17xh

Sector

Number

Sector

Number

Cylinder

Low

Cylinder

Low

Cylinder

High

Cylinder

High

1Fxh

3Fxh

17xh

37xh

Drive/Head Drive/Head

Status

Command

Alternate

Status

Device

Control

3Fxh

37xh

Drive

Reserved

Address

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ATA AND TRUE IDE REGISTER DECODING

TASK FILE REGISTER SPECIFICATION

SSD-CXXX(I)-3150 DATA SHEET

The Task File registers are used for reading and writing the storage data in the

SiliconDrive. The decoded addresses are as shown in the following table.

Table 33: Task File Register Specification

CS0# CS1# DA02 DA01 DA00 DIOR# = L

DIOW# = L

Data

Error

Feature

Sector Count

Sector Number Sector Number

Cylinder Low

Cylinder High

Drive/Head

Status

Cylinder Low

Cylinder High

Drive/Head

Command

Invalid

High-Z

Not Used

High-Z

Not Used

High-Z

Not Used

Alternate Status Device Control

Device Address Not Used

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ATA REGISTERS

SSD-CXXX(I)-3150 DATA SHEET

ATA REGISTERS

DATA REGISTER

The Data register is a 16-bit register used to transfer data blocks between the

host and drive buffers. The register may set to 8-bit mode by using the Set

Features Command defined in "Seek — 7Xh" on page 77.

ERROR REGISTER

The Error register contains the error status, if any, generated from the last

executed ATA command. The contents are qualified by the ERR bit being set

in "Status Register" on page 53.

Table 34: Error Register

Operation

Read

BBK UNC

IDNF MCR ABRT TKNOF AMNF

Default

Value

Bit(s) Description

Bad Block Detected (BBK). Set when a bad block is detected.

Uncorrectable Data Error (UNC). Set when an uncorrectable error

is encountered.

Media Changed (MC). Set to 0.

ID Not Found (IDNF). Set when the sector ID is not found.

MCR (Media Change Request). Set to 0.

Aborted Command (ABRT). Set when a command is aborted due

to a drive error.

Track 0 Not Found (TKONF). Set when the execute drive

diagnostic command is executed.

Address Mark Not Found (AMNF). Set in the case of a general

error.

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ATA REGISTERS

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FEATURE REGISTER

The Feature register is command-specific and used to enable and disable

interface features. This register supports only either odd or even byte data

transfers.

Table 35: Feature Register

Operation

Read/Write

Feature Byte

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ATA REGISTERS

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SECTOR COUNT REGISTER

The Sector Count register is used to read or write the sector count of the data

for which an ATA transfer has been made.

Table 36: Sector Count Register

Operation

Read/Write

Default Value

Sector Count

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ATA REGISTERS

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SECTOR NUMBER REGISTER

The Sector Number register is set by the host to specify the starting sector

number associated with the next ATA command to be executed. Following a

qualified ATA command sequence, the device sets the register value to the

last sector read or written as a result of the previous AT command.

When Logical Block Addressing (LBA) mode is implemented and the host

issues a command, the contents of the register describe the Logical Block

Number bits A[7:0]. Following an ATA command, the device loads the register

with the LBA block number resulting from the last ATA command.

Table 37: Sector Number Register

Operation

Read/Write

Sector Number (CHS Addressing)

Logical Block Number bits A07-A00 (LBA Addressing)

Default Value

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ATA REGISTERS

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CYLINDER LOW REGISTER

The Cylinder Low register is set by the host to specify the cylinder number low

byte. Following an ATA command, the content of the register is written by the

device, identifying the cylinder number low byte.

In LBA mode, the 8-bit register maintains the contents of the Logical Block

number address bits A15:A08.

Table 38: Cylinder Low Register

Operation

Read/Write

Cylinder Number Low Byte (CHS Addressing)

Logical Block Number bits A15-A08 (LBA Addressing)

Default Value

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ATA REGISTERS

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CYLINDER HIGH REGISTER

The Cylinder High register is set by the host to specify the cylinder number

high byte. Following an ATA command, the content of the register is set

internally by the device, identifying the cylinder number high byte.

In LBA mode, the 8-bit register maintains the contents of the Logical Block

number address bits A23:A16.

Table 39: Cylinder High Register

Operation

Read/Write

Cylinder Number Low Byte (CHS Addressing)

Logical Block Number bits A23-A16 (LBA Addressing)

Default Value

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ATA REGISTERS

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DRIVE/HEAD REGISTER

The Drive/Head register is used by the host and the device to select the type

of addressing (CHS or LBA), the drive letter, and either bits 3-0 of the head

number in CHS mode or logical block number bits 27-24 in LBA mode.

Table 40: Drive/Head Register

Operation

Read/Write

LBA

DRV

HS3

HS2

HS1

HS0

LBA24

LBA27 LBA26 LBA25

Default

Value

The Drive/Head register is used by the host to specify one of a pair of ATA

drives present in the platform.

Bit(s)

Description

LBA. Selects between CHS (0) and LBA (1) addressing mode.

Drive Address (DRV). Indicates the drive number selected by the

host, either 0 or 1.

3-0

HS3 to 0. Indicates bits 3-0 of the head number in CHS addressing

mode or LBA bits 27-24 in LBA mode.

• CHS to LBA conversion: LBA = (C x HpC + H) x SpH + S -1

• LBA to CHS conversion:

¶ C = LBA/(HpC x SpH)

¶ H = (LBA/SpH) mod (HpC)

¶ S = (LBA mod(SpH)) + 1

...where:

¶ C is the cylinder number

¶ H is the head number

¶ S is the sector count

¶ HpC is the head count per cylinder count

¶ SpH is the sector count per head count (track)

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ATA REGISTERS

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STATUS REGISTER

The Status register provides the device’s current status to the host. The status

read by the host, the IREQ# bit is cleared.

Table 41: Status Register

Operation

Read/Write

Default Value

BSY DRDY DWF DSC DRQ CORR IDX ERR

Bit(s) Description

Busy (BSY). Set when the drive is busy and unable to process any

new ATA commands.

Data Ready (DRDY). Set when the device is ready to accept ATA

commands from the host.

Drive Write Fault (DWF). Always set to 0.

Drive Seek Complete (DSC). Set when the drive heads have been

positioned over a specific track.

Data Request (DRQ). Set when a device is ready to transfer a word

or byte of data to or from the host and the device.

Corrected Data (CORR). Always set to 0.

Index (IDX). Always set to 0.

Error (ERR). Set when an error occurs during the previous ATA

command.

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ATA REGISTERS

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COMMAND REGISTER

The Command register specifies the ATA command code being issued to the

drive by the host. Execution of the command begins immediately following the

issuance of the command register code by the host.

Table 42: Command Register

Operation

Read/Write

ATA Command Code

See "ATA Command Block and Set Description" on page 58 for a listing of the

supported ATA commands.

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ATA REGISTERS

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ALTERNATE STATUS REGISTER

The Alternate Status register is a read-only register indicating the status of the

device, following the previous ATA command. See "Status Register" on page

53 for specific details.

Table 43: Alternate Status Register

Operation

Read/Write

Default Value

BSY DRDY DWF DSC DRQ CORR IDX ERR

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ATA REGISTERS

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DEVICE CONTROL REGISTER

The Device Control register is used to control the interrupt request and issue

ATA software resets.

Table 44: Device Control Register

Operation

Write

SRST nIEN

Bit(s)

Description

7-4

Reserved bits.

Always set to 1.

Software Reset (SRST). When set, resets the ATA software.

Interrupt Enable (nIEN). When set, device interrupts are disabled.

There is no function in the memory-mapped mode.

Always set to 0.

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ATA REGISTERS

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DEVICE ADDRESS REGISTER

The Device Address register is used to maintain compatibility with ATA disk

drive interfaces.

Table 45: Device Address Register

Operation

Read/Write

Default Value

nWTG nHS3 nHS2 nHS1 nHS0 nDS1 nDS0

Bit(s) Description

Reserved bit.

Write Gate (nWTG). Low when a write to the device is in process.

5-2

nHS3 to nHS0. The negated binary address of the currently selected

head.

nDS1. Low when drive 1 is selected and active.

nDS0. Low when drive 0 is selected and active.

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ATA COMMAND BLOCK AND SET DESCRIPTION

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ATA COMMAND BLOCK AND SET DESCRIPTION

In accordance with the ANSI ATA Specification, the device implements seven

registers that are used to transfer instructions to the device by the host. These

commands follow the ANSI standard ATA protocol. A description of the ATA

command block is provided in the following table.

Table 46: ATA Command Block and Set Description

Operation

Feature

Sector Count

Sector Number

Cylinder Low

Cylinder High

Drive Head

Command

LBA

Drive

ATA COMMAND SET

Table 47: ATA Command Set

Registers Used

FR SC SN CY DH LBA

Command

Code

Class Command Name

Check Power Mode

98h, E5h

90h

Execute Drive

Diagnostics

Erase Sector

Format Track

Identify Drive

Idle

C0h

50h

ECh

97h, E3h

95h, E1h

91h

Idle Immediate

Initialize Drive

Parameters

Read Buffer

Read DMA*

Read Multiple

E4h

C8h

C4h

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ATA COMMAND BLOCK AND SET DESCRIPTION

SSD-CXXX(I)-3150 DATA SHEET

Table 47: ATA Command Set (Continued)

Registers Used

Command

Code

Class Command Name

FR SC SN CY DH LBA

Read Long Sector

Read Sector(s)

22h, 23h

20h, 21h

Read Verify Sector(s) 40h, 41h

Recalibrate

1Xh

Request Sense

Seek

03h

7Xh

Set Features

Set Multiple Mode

Set Sleep Mode

Standby

EFh

C6h

99h, E6h

96h, E2h

94h, E0h

87h

Standby Immediate

Translate Sector

Wear Level

F5h

Write Buffer

E8h

Write DMA*

CAh

Write Long Sector

Write Multiple

32h, 33h

C5h

Write Multiple w/o

Erase

CDh

Write Sector(s)

30h, 31h

38h

Write Sector(s) w/o

Erase

Write Verify

3Ch

* = This function does not apply to SiliconDrives that have DMA disabled.

Notes:

• CY = Cylinder

• SC = Sector Count

• DH = Drive/Head

• SN = Sector Number

• FR = Feature LBA — LBA bit of the Drive/Head register (D denotes that

only the drive bit is used)

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ATA COMMAND BLOCK AND SET DESCRIPTION

SSD-CXXX(I)-3150 DATA SHEET

Check Power Mode — 98h, E5h

The Check Power Mode command verifies the device’s current power mode.

When the device is configured for standby mode or is entering or exiting

standby, the BSY bit is set, the Sector Count register set to 00h, and the BSY

bit is cleared. In idle mode, BSY is set and the Sector Count register is set to

FFh. The BSY bit is then cleared and an interrupt is issued.

Table 48: Check Power Mode — 98h, E5h

Feature

Sector Count

Sector Number

Cylinder Low

Cylinder High

Drive Head

Command

Drive

98h or E5h

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ATA COMMAND BLOCK AND SET DESCRIPTION

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Executive Drive Diagnostic — 90h

The Executive Drive Diagnostic performs an internal read write diagnostic test

using (AA55h and 55AAh). If an error is detected in the read/write buffer, the

Error register reports the appropriate diagnostic code.

Table 49: Executive Drive Diagnostic — 90h

Feature

Sector Count

Sector Number

Cylinder Low

Cylinder High

Drive Head

Command

Drive

90h

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ATA COMMAND BLOCK AND SET DESCRIPTION

SSD-CXXX(I)-3150 DATA SHEET

Format Track — 50h

The Format Track command formats the common solid-state memory array.

Table 50: Format Track — 50h

Feature

Sector Count

Sector Number

Cylinder Low

Cylinder High

Drive Head

Command

Sector Count

Sector Number (LBA7-0)

Cylinder Low (LBA15-8)

Cylinder High (LBA23-16)

LBA

Drive Head Number (LBA27-24)

50h

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ATA COMMAND BLOCK AND SET DESCRIPTION

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Identify Drive — ECh

Issued by the host, the Identify Drive command provides 256 bytes of drive

attribute data (i.e., sector size, count, and so on) The identify drive data

structure is detailed in the following table.

Table 51: Identify Drive — ECh

Feature

Sector Count

Sector Number

Cylinder Low

Cylinder High

Drive Head

Command

Drive

ECh

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ATA COMMAND BLOCK AND SET DESCRIPTION

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Identify Drive — Drive Attribute Data

Table 52: Identify Drive — Drive Attribute Data

Data Default Bytes Data Description

Word

Address

044Ah (fixed

ID bit) in IDE

mode

General configuration bit information

• 15: Non-magnetic disk

• 14: Formatting speed latency

permissible gap needed

• 13: Track Offset option supported

• 12: Data Strobe Offset option supported

848A

(removable ID

bit) inPCMCIA

memory and I/

O modes

• 11: Over 0.5% rotational speed

difference

• 10: Disk transfer rate >10Mbps

• 9: 10Mbps >= disk transfer rate >5Mbps

• 8: 5Mbps >= disk transfer rate

• 7: Removable cartridge drive

• 6: Fixed drive

• 5: Spindle Motor Control option

executed

• 4: Over 15μs changing head time

• 3: Non-MFM encoding

• 2: Soft sector allocation

• 1: Hard sector allocation

• 0: Reserved

XXXXh

0000h

00XXh

0000h

XXXXh

0000h

XXXXh

Number of cylinders

Reserved

Number of heads

Number of unformatted bytes per track

Number of unformatted bytes per sector

Number of sectors per track

Number of sectors per device

Reserved

7-8

10-19

Serial number

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ATA COMMAND BLOCK AND SET DESCRIPTION

SSD-CXXX(I)-3150 DATA SHEET

Table 52: Identify Drive — Drive Attribute Data (Continued)

Word

Address

Data Default Bytes Data Description

0002h

Buffer type

• 0000h: Not specified

• 0001h: A single-ported, single-sector

buffer

• 0002h: A dual-ported multisector buffer

• 0003h: A dual-ported multisector buffer

with a read caching

0002h

0004h

Buffer size in 512-byte increments

Number of ECC bytes passed on read/

write long commands

23-26

27-46

XXXXh

0001h

Firmware revision (eight ASCII characters)

Model number (40 ASCII characters)

7-0: Maximum number of sectors that can

be transferred with a Read/Write Multiple

command per interrupt

0000h

0002h

Double word (32 bit) not supported

• 11: IORDY supported

• 9: LBA supported

• 8: DMA supported

0000h

0100h

0000h

Reserved

15-8: PIO data transfer cycle timing

15-8: DMA data transfer cycle timing

• 1: Words 64-70 are valid

• 0: Words 54-58 are valid

XXXXh

010Xh

Current number of cylinders

Current number of heads

Current sectors per track

Current capacity in sectors

57-58

7-0: Current sectors can be transferred

with a Read/Write Multiple command per

interrupt

60-61

XXXXh

0000h

Total number of sectors addressable in

LBA mode

Single-word DMA modes supported

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ATA COMMAND BLOCK AND SET DESCRIPTION

SSD-CXXX(I)-3150 DATA SHEET

Table 52: Identify Drive — Drive Attribute Data (Continued)

Word

Address

Data Default Bytes Data Description

0407h

0003h

0078h

Multiword DMA modes supported

PIO modes supported

Minimum DMA transfer cycle time per

word (ns)

0078h

0000h

Manufacturer’s recommended DMA

transfer cycle time (ns)

Minimum PIO transfer cycle time without

flow control (ns)

Minimum PIO transfer cycle time with

IORDY flow controls (ns)

69-127

118

Reserved

128-159 0000h

160-255 0000h

Vendor-unique

Reserved

192

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ATA COMMAND BLOCK AND SET DESCRIPTION

SSD-CXXX(I)-3150 DATA SHEET

Idle — 97h, E3h

When issued by the host, the device’s internal controller sets the BSY bit,

enters the Idle mode, clears the BSY bit, and generates an interrupt. If the

sector count is non-zero, it is interpreted as a timer count with each count

being 5ms, and the automatic power-down mode is enabled. If the sector

count is zero, the automatic power-down mode is disabled.

Table 53: Idle — 97h, E3h

Feature

Sector Count

Sector Number

Cylinder Low

Cylinder High

Drive Head

Command

Timer Count (5ms increments)

Drive

97h or E3h

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ATA COMMAND BLOCK AND SET DESCRIPTION

SSD-CXXX(I)-3150 DATA SHEET

Idle Immediate — 95h, E1h

When issued by the host, the device’s internal controller sets the BSY bit,

enters Idle Mode, clears the BSY bit, and issues an interrupt. The interrupt is

issued whether or not the Idle mode is fully entered.

Table 54: Idle Immediate — 95h, E1h

Feature

Sector Count

Sector Number

Cylinder Low

Cylinder High

Drive Head

Command

Drive

95h or E1h

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ATA COMMAND BLOCK AND SET DESCRIPTION

SSD-CXXX(I)-3150 DATA SHEET

Initialize Drive Parameters — 91h

Initialize Drive Parameters allows the host to set the sector counts per track

and the head counts per cylinder to 1 Fixed. Upon issuance of the command,

the device sets the BSY bit and associated parameters, clears the BSY bit,

and issues an interrupt.

Table 55: Initialize Drive Parameters — 91h

Feature

Sector Count

Sector Number

Cylinder Low

Cylinder High

Drive Head

Sector Count (Number of Sectors)

Drive

Head Number

(Number of Heads — 1)

Command

91h

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ATA COMMAND BLOCK AND SET DESCRIPTION

SSD-CXXX(I)-3150 DATA SHEET

Recalibrate — 1Xh

The Recalibrate command sets the cylinder low and high, head number to 0h,

and sector number to 1h in CHS mode. In LBA mode (i.e., LBA = 1), the sector

number is set to 0h.

Table 56: Recalibrate — 1Xh

Feature

Sector Count

Sector Number

Cylinder Low

Cylinder High

Drive Head

Command

LBA

Drive

1Xh

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ATA COMMAND BLOCK AND SET DESCRIPTION

SSD-CXXX(I)-3150 DATA SHEET

Read Buffer — E4h

The Read Buffer command allows the host to read the contents of the sector

buffer. When issued, the device sets the BSY bit and sets up the sector buffer

data in preparation for the read operation. When the data is ready, the DRQ bit

is set and the BSY bit in the Status register are set and cleared, respectively.

Table 57: Read Buffer — E4h

Feature

Sector Count

Sector Number

Cylinder Low

Cylinder High

Drive Head

Command

Drive

E4h

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ATA COMMAND BLOCK AND SET DESCRIPTION

SSD-CXXX(I)-3150 DATA SHEET

Read DMA — C8h

The Read DMA command allows the host to read data using the DMA transfer

protocol.

Note: This function does not apply to SiliconDrives that have DMA

disabled.

Table 58: Read DMA — C8h

Feature

Sector Count

Sector Number

Cylinder Low

Cylinder High

Drive Head

Command

Sector Count

Sector Number (LBA7-0)

Cylinder Low (LBA15-8)

Cylinder High (LBA23-16)

LBA

Drive Head Number (LBA27-24)

C8h

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ATA COMMAND BLOCK AND SET DESCRIPTION

SSD-CXXX(I)-3150 DATA SHEET

Read Multiple — C4h

The Read Multiple command executes similarly to the Read Sector command,

with the exception that interrupts are issued only when a block containing the

counts of sectors defined by the Set Multiple command is transferred.

Table 59: Read Multiple — C4h

Feature

Sector Count

Sector Number

Cylinder Low

Cylinder High

Drive Head

Command

Sector Count

Sector Number (LBA7-0)

Cylinder Low (LBA15-8)

Cylinder High (LBA23-16)

LBA

Drive Head Number (LBA27-24)

C4h

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ATA COMMAND BLOCK AND SET DESCRIPTION

SSD-CXXX(I)-3150 DATA SHEET

Read Sector — 20h, 21h

The Read Sector command allows the host to read sectors 1 to 256 as

specified in the Sector Count register. If the sector count is set to 0h, all 256

sectors of data are made available. When the command code is issued and

the first sector of data has been transferred to the buffer, the DRQ bit is set.

The Read Sector command is terminated by writing the cylinder, head, and

sector number of the last sector read in the task file. On error, the read

operation is aborted in the errant sector.

Table 60: Read Sector — 20h, 21h

Feature

Sector Count

Sector Number

Cylinder Low

Cylinder High

Drive Head

Command

Sector Count

Sector Number (LBA7-0)

Cylinder Low (LBA15-8)

Cylinder High (LBA23-16)

LBA

Drive Head Number (LBA27-24)

20h or 21h

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ATA COMMAND BLOCK AND SET DESCRIPTION

SSD-CXXX(I)-3150 DATA SHEET

Read Long Sector(s) — 22h, 23h

The Read Long Sector(s) command operates similarly to the Read Sector(s)

command, with the exception that it transfers requested data sectors and ECC

data. The long instruction ECC byte transfer for Long commands is a byte

transfer at a fixed length of 4 bytes.

Table 61: Read Long Sector(s) — 22h, 23h

Feature

Sector Count

Sector Number

Cylinder Low

Cylinder High

Drive Head

Command

Sector Number (LBA7-0)

Cylinder Low (LBA15-8)

Cylinder High (LBA23-16)

LBA

Drive Head Number (LBA27-24)

22h or 23h

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ATA COMMAND BLOCK AND SET DESCRIPTION

SSD-CXXX(I)-3150 DATA SHEET

Read Verify Sector(s) — 40h, 41h

The Read Verify Sector(s) command operates similarly to the Read Sector(s)

command, with the exception that is does not set the DRQ bit and does not

transfer data to the host. When the requested sectors are verified, the onboard

controller clears the BSY bit and issues an interrupt.

Table 62: Read Verify Sector(s) — 40h, 41h

Feature

Sector Count

Sector Number

Cylinder Low

Cylinder High

Drive Head

Command

Sector Count

Sector Number (LBA7-0)

Cylinder Low (LBA15-8)

Cylinder High (LBA23-16)

LBA

Drive Head Number (LBA27-24)

40h or 41h

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ATA COMMAND BLOCK AND SET DESCRIPTION

SSD-CXXX(I)-3150 DATA SHEET

Seek — 7Xh

The Seek command seeks and picks up the head to the tracks specified in the

task file. When the command is issued, the solid-state memory chips do not

need to be formatted. After an appropriate amount of time, the DSC bit is set.

Table 63: Seek — 7Xh

Feature

Sector Count

Sector Number

Cylinder Low

Cylinder High

Drive Head

Command

Sector Number (LBA7-0)

Cylinder Low (LBA15-8)

Cylinder High (LBA23-16)

LBA

Drive Head Number (LBA27-24)

7Xh

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ATA COMMAND BLOCK AND SET DESCRIPTION

SSD-CXXX(I)-3150 DATA SHEET

Set Features — EFh

The Set Features command allows the host to configure the feature set of the

device according to the attributes listed in T a ble 65.

Table 64: Set Features — EFh

Feature

Sector Count

Sector Number

Cylinder Low

Cylinder High

Drive Head

Command

Drive

EFh

Table 65: Set Features’ Attributes

Operation

Enable 8-bit data transfer

Feature

01h

66h

81h

BBh

CCh

Disable reverting to power on defaults

Disable 8-bit data transfer

4 bytes of data apply on Read/Write Long commands

Enable revert to power on defaults

On power-up or following a hardware reset, the device is set to the default

mode 81h.

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ATA COMMAND BLOCK AND SET DESCRIPTION

SSD-CXXX(I)-3150 DATA SHEET

Set Multiple Mode — C6h

The Set Multiple Mode command allows the host to access the drive via Read

Multiple and Write Multiple ATA commands. Additionally, the command sets

the block count (i.e., the number of sectors within the block) for the Read/Write

Multiple command. The sector count per block is set in the Sector Count

Table 66: Set Multiple Mode — C6h

Feature

Sector Count

Sector Number

Cylinder Low

Cylinder High

Drive Head

Command

Sector Count

Drive

C6h

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ATA COMMAND BLOCK AND SET DESCRIPTION

SSD-CXXX(I)-3150 DATA SHEET

Set Sleep Mode — 99h, E6h

The Set Sleep Mode command allows the host to set the device in sleep

mode. When the onboard controller transitions to sleep mode, it clears the

BSY bit and issues an interrupt. The device interface then becomes inactive.

Sleep mode can be exited by issuing either a hardware or software reset.

Table 67: Set Sleep Mode — 99h, E6h

Feature

Sector Count

Sector Number

Cylinder Low

Cylinder High

Drive Head

Command

Drive

99h or E6h

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ATA COMMAND BLOCK AND SET DESCRIPTION

SSD-CXXX(I)-3150 DATA SHEET

Standby — 96h, E2h

When the Standby command is issued by the host, it transitions the device into

standby mode. If the Sector Count register is set to a value other than 0h, the

Auto Powerdown function is enabled and the device returns to Idle mode.

Table 68: Standby — 96h, E2h

Feature

Sector Count

Sector Number

Cylinder Low

Cylinder High

Drive Head

Command

Timer Count (5ms x Timer Count)

Drive

96h or E2h

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ATA COMMAND BLOCK AND SET DESCRIPTION

SSD-CXXX(I)-3150 DATA SHEET

Standby Immediate — 94h, E0h

When the Standby Immediate command is issued by the host, it transitions the

device into standby mode.

Table 69: Standby Immediate — 94h, E0h

Feature

Sector Count

Sector Number

Cylinder Low

Cylinder High

Drive Head

Command

Drive

94h or E0h

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ATA COMMAND BLOCK AND SET DESCRIPTION

SSD-CXXX(I)-3150 DATA SHEET

Write Buffer — E8h

The Write Buffer command allows the host to rewrite the contents of the

512- byte data buffer with the wanted data.

Table 70: Write Buffer — E8h

Feature

Sector Count

Sector Number

Cylinder Low

Cylinder High

Drive Head

Command

Drive

E8h

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ATA COMMAND BLOCK AND SET DESCRIPTION

SSD-CXXX(I)-3150 DATA SHEET

Write DMA — CAh

The Write DMA command allows the host to write data using the DMA transfer

protocol.

Note: This function does not apply to SiliconDrives that have DMA

disabled.

Table 71: Write DMA — CAh

Feature

Sector Count

Sector Number

Cylinder Low

Cylinder High

Drive Head

Command

Sector Count

Sector Number (LBA7-0)

Cylinder Low(LBA15-8)

Cylinder High(LBA23-16)

LBA

Drive Head Number(LBA27-24)

CAh

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ATA COMMAND BLOCK AND SET DESCRIPTION

SSD-CXXX(I)-3150 DATA SHEET

Write Multiple — C5h

The Write Multiple command operates in the same manner as the Write Sector

command. When issued, the device sets the BSY bit within 400ns and

generates an interrupt at the completion of a transferred block of sectors. The

DRQ bit is set at the beginning of a block transfer.

Table 72: Write Multiple — C5h

Feature

Sector Count

Sector Number

Cylinder Low

Cylinder High

Drive Head

Command

Sector Count

Sector Number (LBA7-0)

Cylinder Low(LBA15-8)

Cylinder High(LBA23-16)

LBA

Drive Head Number(LBA27-24)

C5h

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ATA COMMAND BLOCK AND SET DESCRIPTION

SSD-CXXX(I)-3150 DATA SHEET

Write Sector(s) — 30h, 31h

The Write Sector(s) command writes from 1 to 256 sectors as specified in the

Sector Count register. A sector count of 0 requests 256 sectors. When issued,

the device sets the BSY bit within 400ns and generates an interrupt at the

completion of a transferred block of sectors. The DRQ bit is set at the

beginning of a block transfer.

Table 73: Write Sector(s) — 30h, 31h

Feature

Sector Count

Sector Number

Cylinder Low

Cylinder High

Drive Head

Command

Sector Count

Sector Number (LBA7-0)

Cylinder Low (LBA15-8)

Cylinder High (LBA23-16)

LBA

Drive Head Number (LBA27-24)

30h or 31h

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ATA COMMAND BLOCK AND SET DESCRIPTION

SSD-CXXX(I)-3150 DATA SHEET

Write Long Sector(s) — 32h, 33h

The Write Long Sector(s) command operates in the same manner as the Write

Sector command — when issued, the device sets the BSY bit within 400ns

and generates an interrupt at the completion of a transferred block of sectors.

The DRQ bit is set at the beginning of a block transfer.

Table 74: Write Long Sector(s) — 32h, 33h

Feature

Sector Count

Sector Number

Cylinder Low

Cylinder High

Drive Head

Command

Sector Count

Sector Number (LBA7-0)

Cylinder Low (LBA15-8)

Cylinder High (LBA23-16)

LBA

Drive Head Number (LBA27-24)

32h or 33h

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ATA COMMAND BLOCK AND SET DESCRIPTION

SSD-CXXX(I)-3150 DATA SHEET

Erase Sector(s) — C0h

The Erase Sector(s) command is issued prior to the issuance of a Write

Sector(s) or Write Multiple w/o Erase command.

Table 75: Erase Sector(s) — C0h

Feature

Sector Count

Sector Number

Cylinder Low

Cylinder High

Drive Head

Command

Sector Count

Sector Number (LBA7-0)

Cylinder Low (LBA15-8)

Cylinder High (LBA23-16)

LBA

Drive Head Number (LBA27-24)

C0h

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ATA COMMAND BLOCK AND SET DESCRIPTION

SSD-CXXX(I)-3150 DATA SHEET

Request Sense — 03h

The Request Sense command identifies the extended error codes generated

by the preceding ATA command. The Request Sense command must be

issued immediately following the detection of an error via the Error register.

Table 76: Request Sense — 03h

Feature

Sector Count

Sector Number

Cylinder Low

Cylinder High

Drive Head

Command

Drive

03h

The extended error codes are defined in the following table.

Table 77: Extended Error Codes

Extended Error Codes

Description

00h

No error detected

01h

Self test is OK (no error)

Miscellaneous error

Invalid command

09h

20h

21h

Invalid address (requested head or sector invalid)

Address overflow (address too large)

Supply or generated voltage out of tolerance

Uncorrectable ECC error

2Fh

35h, 36h

11h

18h

Corrected ECC error

05h, 30h-32h, 37h,3Eh

Self test of diagnostic failed

10h, 14h

3Ah

ID not found

Spare sectors exhausted

1Fh

Data transfer error/aborted command

0Ch, 38h, 3Bh, 3Ch, 3Fh Computed media format

03h

Write/erase failed

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ATA COMMAND BLOCK AND SET DESCRIPTION

SSD-CXXX(I)-3150 DATA SHEET

Translate Sector — 87h

The Translate Sector command is not currently supported by the

SiliconSystems’ SiliconDrive. If the host issues this command, the device

responds with 0x00h in the data register.

Table 78: Translate Sector — 87h

Feature

Sector Count

Sector Number

Cylinder Low

Cylinder High

Drive Head

Command

Sector Count

Sector Number (LBA7-0)

Cylinder Low (LBA15-8)

Cylinder High (LBA23-16)

LBA

Drive Head Number (LBA27-24)

87h

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ATA COMMAND BLOCK AND SET DESCRIPTION

SSD-CXXX(I)-3150 DATA SHEET

Wear-Level — F5h

The Wear-Level command is supported as an NOP command for the

purposes of backward compatibility with the ANSI AT attachment standard.

This command sets the Sector Count register to 0x00h.

Table 79: Wear-Level — F5h

Feature

Sector Count

Sector Number

Cylinder Low

Cylinder High

Drive Head

Command

Completion Status

Drive

F5h

Flag

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ATA COMMAND BLOCK AND SET DESCRIPTION

SSD-CXXX(I)-3150 DATA SHEET

Write Multiple w/o Erase — CDh

The Write Multiple w/o Erase command functions identically to the Write

Multiple command, with the exception that the implied pre-erase (i.e., Erase

Sector(s) command) is not issued prior to writing the sectors.

Table 80: Write Multiple w/o Erase — CDh

Feature

Sector Count

Sector Number

Cylinder Low

Cylinder High

Drive Head

Command

Sector Count

Sector Number (LBA7-0)

Cylinder Low (LBA15-8)

Cylinder High (LBA23-16)

LBA

Drive Head Number (LBA27-24)

CDh

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ATA COMMAND BLOCK AND SET DESCRIPTION

SSD-CXXX(I)-3150 DATA SHEET

Write Sector(s) w/o Erase — 38h

The Write Sector(s) w/o Erase command functions similar to the Write Sector

command, with the exception that the implied pre-erase (i.e., Erase Sector(s)

command) is not issued prior to writing the sectors.

Table 81: Write Sector(s) w/o Erase — 38h

Feature

Sector Count

Sector Number

Cylinder Low

Cylinder High

Drive Head

Command

Sector Count

Sector Number (LBA7-0)

Cylinder Low (LBA15-8)

Cylinder High (LBA23-16)

LBA

Drive Head Number (LBA27-24)

38h

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ATA COMMAND BLOCK AND SET DESCRIPTION

SSD-CXXX(I)-3150 DATA SHEET

Write Verify — 3Ch

The Write Verify command verifies each sector immediately after it is written.

This command performs identically to the Write Sector(s) command, with the

added feature of verifying each sector written.

Table 82: Write Verify — 3Ch

Feature

Sector Count

Sector Number

Cylinder Low

Cylinder High

Drive Head

Command

Sector Count

Sector Number (LBA7-0)

Cylinder Low (LBA15-8)

Cylinder High (LBA23-16)

LBA

Drive Head Number (LBA27-24)

3Ch

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SALES AND SUPPORT

SSD-CXXX(I)-3150 DATA SHEET

SALES AND SUPPORT

To order or obtain information on pricing and delivery, contact your

SiliconSystems Sales Representative.

PART NUMBERING

NOMENCLATURE

The following table defines the SiliconDrive CF part numbering scheme.

Table 83: Part Numbering Nomenclature

SSD-

YYY

-3150

Part number suffix —

contact your

SiliconSystems’ Sales

Representative

Temperature Range:

•

Blank = Commercial

I = Industrial

Capacity: 32M = 32MB to 08G = 8GB

Form Factor:

•

C = CF

•

D = 2.5" Drive

M = Module

P = PC Card

SiliconSystems’ SiliconDrive

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PART NUMBERING

SSD-CXXX(I)-3150 DATA SHEET

PART NUMBERS

The following table lists the SiliconDrive’s part numbers.

Table 84: Part Numbers

Part Number

Capacity

SSD-C08G(I)-3150

SSD-C04G(I)-3150

SSD-C02G(I)-3150

SSD-C01G(I)-3150

SSD-C51M(I)-3150

SSD-C25M(I)-3150

SSD-C12M(I)-3150

SSD-C64M(I)-3150

SSD-C32M(I)-3150

8GB

4GB

2GB

1GB

512MB

256MB

128MB

64MB

32MB

SAMPLE LABEL

Standard Back Label with

Lot Code Information

Front Label

SiliconSystems, Inc.

SiliconDrive

8GB

SSD-C08G(I)-3150

A123/3150

Figure 8: Sample Label

SILICONSYSTEMS PROPRIETARY

This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc.

All unauthorized use and/or reproduction is prohibited.

3150C-10DSR

PAGE 96

FEBRUARY 2, 2009