Cypress Rambus XDR CY24271 User Manual
CY24272  
®
Rambus XDR™ Clock Generator with  
Zero SDA Hold Time  
Features  
Table 1. Device Comparison  
®
■ Meets Rambus Extended Data Rate (XDR™) clocking  
requirements  
CY24271  
CY24272  
SDA hold time = 300 ns  
(SMBus compliant)  
SDA hold time = 0 ns  
2
■ 25 ps typical cycle-to-cycle jitter  
❐ –135 dBc/Hz typical phase noise at 20 MHz offset  
(I C compliant)  
R
= 200Ω typical  
R
= 295Ω minimum  
RC  
RC  
■ 100 or 133 MHz differential clock input  
■ 300–667 MHz high speed clock support  
■ Quad (open drain) differential output drivers  
■ Supports frequency multipliers: 3, 4, 5, 6, 9/2 and 15/4  
■ Spread Aware™  
(Rambus standard drive)  
(Reduced output drive)  
■ 2.5V operation  
■ 28-pin TSSOP package  
Logic Block Diagram  
/BYPASS  
EN  
EN  
RegA  
CLK0  
CLK0B  
EN  
RegB  
CLK1  
Bypass  
MUX  
CLK1B  
EN  
RegC  
PLL  
REFCLK,REFCLKB  
CLK2  
CLK2B  
EN  
RegD  
CLK3  
CLK3B  
SCL  
SDA  
ID0  
ID1  
Cypress Semiconductor Corporation  
Document Number: 001-42414 Rev. **  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised November 9, 2007  
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CY24272  
PLL Multiplier  
Table 3 shows the frequency multipliers in the PLL, selectable by programming the SMBus registers MULT0, MULT1, and MULT2.  
Default multiplier at power up is 4.  
Table 3. PLL Multiplier Selection  
Register  
Output Frequency (MHz)  
Frequency Multiplier  
[1]  
[1]  
MULT2 MULT1 MULT0  
REFCLK = 100 MHz , REFSEL = 0 REFCLK = 133 MHz , REFSEL = 1  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
3
300  
400  
–
[2]  
4
400  
5
6
500  
600  
–
667  
–
Reserved  
9/2  
–
450  
–
600  
–
Reserved  
15/4  
375  
500  
Input Clock Signal  
Modes of Operation  
The XCG receives either a differential (REFCLK/REFCLKB) or a  
single-ended reference clocking input (REFCLK).  
The modes of operation are determined by the logic signals  
applied to the EN and /BYPASS pins and the values in the five  
SMBus Registers: RegTest, RegA, RegB, RegC, and RegD.  
Table 5 on page 4 shows selection from one to all four of the  
outputs, the Outputs Disabled Mode (EN = low), and Bypass  
Mode (EN = high, /BYPASS = low). There is an option reserved  
for vendor test. Disabled outputs are set to High Z.  
When the reference input clock is from a different clock source,  
it must meet the voltage levels and timing requirements listed in  
DC Operating Conditions on page 7 and AC Operating Condi-  
tions on page 8.  
For a single-ended clock input, an external voltage divider and a  
supply voltage, as shown in Figure 2 on page 6, provide a  
At power up, the SMBus registers default to the last entry in Table  
6 on page 5. The value at RegTest is 0. The values at RegA,  
RegB, RegC, and RegD are all ‘1’. Thus, all outputs are  
controlled by the logic applied to EN and /BYPASS.  
reference voltage V at the REFCLKB pin. This determines the  
TH  
proper trip point of REFCLK. For the range of V specified in  
TH  
DC Operating Conditions on page 7, the outputs also meet the  
DC and AC Operating Conditions tables.  
Table 4. SMBus Device Addresses for CY24272  
XCG  
8-bit SMBus Device Address Including Operation  
Hex  
Address  
Device  
Operation  
Write  
Five Most Significant Bits  
ID1  
ID0  
WR# / RD  
D8  
D9  
DA  
DB  
DC  
DD  
DE  
DF  
0
1
0
1
0
1
0
1
0
0
0
Read  
Write  
1
2
3
0
1
1
1
0
1
Read  
Write  
1
1
0
1
1
Read  
Write  
Read  
Notes  
1. Output frequencies shown in Table 3 are based on nominal input frequencies of 100 MHz and 133.3 MHz. The PLL multipliers are applicable to spread spectrum  
modulated input clock with maximum and minimum input cycle time. The REFSEL bit in SMBus 81h is set correctly as shown.  
2. Default PLL multiplier at power up.  
Document Number: 001-42414 Rev. **  
Page 3 of 13  
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CY24272  
Table 5. Modes of Operation for CY24272  
EN /BYPASS RegTest RegA RegB RegC RegD CLK0/CLK0B CLK1/CLK1B CLK2/CLK2B CLK3/CLK3B  
L
H
H
X
X
L
X
1
0
X
X
X
X
X
X
X
X
X
X
X
X
High Z  
High Z  
High Z  
High Z  
Reserved for Vendor Test  
REFCLK/  
REFCLKB  
REFCLK/  
REFCLKB  
REFCLK/  
REFCLKB  
REFCLK/  
REFCLKB  
[3]  
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
High Z  
High Z  
High Z  
High Z  
High Z  
High Z  
CLK/CLKB  
High Z  
High Z  
High Z  
High Z  
CLK/CLKB  
CLK/CLKB  
High Z  
High Z  
High Z  
CLK/CLKB  
High Z  
High Z  
CLK/CLKB  
CLK/CLKB  
CLK/CLKB  
CLK/CLKB  
High Z  
High Z  
High Z  
CLK/CLKB  
High Z  
High Z  
CLK/CLKB  
CLK/CLKB  
High Z  
High Z  
CLK/CLKB  
High Z  
CLK/CLKB  
CLK/CLKB  
CLK/CLKB  
CLK/CLKB  
CLK/CLKB  
CLK/CLKB  
CLK/CLKB  
CLK/CLKB  
High Z  
High Z  
CLK/CLKB  
High Z  
High Z  
CLK/CLKB  
CLK/CLKB  
High Z  
High Z  
CLK/CLKB  
High Z  
CLK/CLKB  
CLK/CLKB  
CLK/CLKB  
CLK/CLKB  
High Z  
CLK/CLKB  
High Z  
CLK/CLKB  
CLK/CLKB  
[4]  
[4]  
[4]  
[4]  
[4]  
0
1
1
1
1
CLK/CLKB  
Device ID and SMBus Device Address  
SMBus Data Byte Definitions  
The device ID (ID0 and ID1) is a part of the SMBus device 8-bit  
address. The least significant bit of the address designates a  
write or read operation. Table 4 on page 3 shows the addresses  
for four CY24272 devices on the same SMBus.  
Three data bytes are defined for the CY24272. Byte 0 is for  
programming the PLL multiplier registers and clock output  
registers.  
The definition of Byte 2 is shown in Table 6, Table 7, and Table 8  
on page 5. The upper five bits are the revision numbers of the  
device and the lower three bits are the ID numbers assigned to  
the vendor by Rambus.  
SMBus Protocol  
The CY24272 is a slave receiver supporting operations in the  
word and byte modes described in sections 5.5.4 and 5.5.5 of  
the SMBus Specification 2.0.  
DC specifications are modified to Rambus standard to support  
1.8, 2.5, and 3.3 volt devices. Time out detection and packet  
error protocol SMBus features are not supported.  
Hold time for SDA is reduced relative to the CY24271, so that it  
2
is compatible with I C.  
Notes  
3. Bypass Mode: REFCLK bypasses the PLL to the output drivers.  
4. Default mode of operation is at power up.  
Document Number: 001-42414 Rev. **  
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CY24272  
[5]  
Table 6. Command Code 80h  
Bit  
7
Register  
Reserved  
MULT2  
MULT1  
MULT0  
RegA  
POD  
Type  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
Description  
0
0
0
1
1
1
1
1
Reserved (no internal function)  
6
PLL Multiplier Select (reference Table 3 on page 3)  
5
4
3
Clock 0 Output Select  
Clock 1 Output Select  
Clock 2 Output Select  
Clock 3 Output Select  
2
RegB  
1
RegC  
0
RegD  
[5]  
Table 7. Command Code 81h  
Bit  
7
Register  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
REFSEL  
Reserved  
RegTest  
POD  
Type  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
Description  
0
0
0
0
1
0
0
0
Reserved (no internal function)  
6
5
4
3
Reserved (must be set to ‘1’ for proper operation)  
Reference Frequency Select (reference Table 3 on page 3)  
Reserved (must be set to ‘0’ for proper operation)  
Reserved (must be set to ‘0’ for proper operation)  
2
1
0
[5]  
Table 8. Command Code 82h  
Bit  
7
Register  
POD  
Type  
RO  
RO  
RO  
RO  
RO  
RO  
RO  
RO  
Description  
Device  
Revision  
Number  
?
?
?
?
?
0
1
0
Contact factory for Device Revision Number information.  
6
5
4
3
2
Vendor ID  
Rambus assigned Vendor ID Code  
1
0
Note  
5. RW = Read and Write, RO = Read Only, POD = Power on default. See Table 3 on page 3 for PLL multipliers and Table 5 on page 4 for clock output selections.  
Document Number: 001-42414 Rev. **  
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CY24272  
Figure 2. Differential and Single-Ended Clock Inputs  
Supply Voltage  
VTH  
REFCLKB  
REFCLK  
Input  
Input  
REFCLK  
XDR Clock Generator  
XDR Clock Generator  
Differential Input  
Single-ended Input  
Absolute Maximum Conditions  
Parameter  
Description  
Clock Buffer Supply Voltage  
Core Supply Voltage  
Condition  
Min  
–0.5  
–0.5  
–0.5  
–0.5  
–0.5  
–0.5  
–65  
0
Max  
4.6  
4.6  
4.6  
4.6  
Unit  
V
V
DD  
V
V
V
V
DDC  
DDP  
IN  
PLL Supply Voltage  
V
Input Voltage (SCL and SDA)  
Relative to V  
V
SS  
SS  
SS  
Input Voltage (REFCLK/REFCLKB) Relative to V  
V
V
+ 1.0  
V
DD  
DD  
Input Voltage  
Relative to V  
+ 0.5  
V
T
Temperature, Storage  
Temperature, Operating Ambient  
Temperature, Junction  
Non-functional  
Functional  
150  
°C  
°C  
°C  
°C/W  
S
T
70  
A
T
Functional  
–
150  
100  
J
Ø
Junction to Ambient thermal resis-  
tance  
Zero air flow  
–
JA  
ESD  
ESD Protection (Human Body Model) MIL-STD-883, Method 3015  
2000  
–
V
HBM  
Document Number: 001-42414 Rev. **  
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CY24272  
DC Operating Conditions  
Parameter  
Description  
Condition  
2.5V ± 5%  
2.5V ± 5%  
2.5V ± 5%  
Min  
2.375  
2.375  
2.375  
0.6  
Max  
2.625  
2.625  
2.625  
0.95  
+0.15  
550  
Unit  
V
V
V
V
V
V
V
Supply Voltage for PLL  
Supply Voltage for Core  
DDP  
V
DDC  
Supply Voltage for Clock Buffers  
V
DD  
Input High Voltage, REFCLK/REFCLKB  
V
IHCLK  
ILCLK  
IXCLK  
Input Low Voltage, REFCLK/REFCLKB  
–0.15  
200  
V
[6]  
[6]  
Crossing Point Voltage, REFCLK/REFCLKB  
Difference in Crossing Point Voltage, REFCLK/REFCLKB  
Input Signal High Voltage at ID0, ID1, EN, and /BYPASS  
Input Signal Low Voltage at ID0, ID1, EN, and /BYPASS  
mV  
mV  
V
ΔV  
–
150  
IXCLK  
V
V
V
V
V
V
V
1.4  
2.625  
0.8  
IH  
–0.15  
1.4  
V
IL  
[7]  
Input Signal High Voltage at SCL and SDA  
3.465  
0.8  
V
IH,SM  
IL,SM  
Input Signal Low Voltage at SCL and SDA  
Input Threshold Voltage for single-ended REFCLK  
Input Signal High Voltage for single-ended REFCLK  
Input Signal Low Voltage for single-ended REFCLK  
Ambient Operating Temperature  
–0.15  
0.35  
V
[8]  
0.5V  
V
TH  
DD  
V
+ 0.3  
2.625  
– 0.3  
V
IH,SE  
IL,SE  
TH  
–0.15  
V
V
TH  
T
0
70  
°C  
A
Notes  
6. Not 100% tested except V  
and ΔV  
. Parameters guaranteed by design and characterizations, not 100% tested in production.  
IXCLK  
IXCLK  
7. This range of SCL and SDA input high voltage enables the CY24272 for use with 3.3V, 2.5V, or 1.8V SMBus voltages.  
8. Single-ended operation guaranteed only when 0.8 < (V  
– V )/(V – V  
,
) < 1.2.  
IH,SE  
TH  
TH  
IL SE  
Document Number: 001-42414 Rev. **  
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CY24272  
AC Operating Conditions  
[6]  
The AC operating conditions follow.  
Parameter  
Description  
Condition  
Min  
9
Max  
11  
Unit  
ns  
t
REFCLK, REFCLKB input cycle time  
REFSEL = 0, /BYPASS = High  
REFSEL = 1, /BYPASS = High  
/BYPASS = Low  
CYCLE,IN  
7
8
ns  
4
–
ns  
[9]  
t
t
t
Input Cycle to Cycle Jitter  
–
185  
60%  
700  
ps  
JIT,IN(cc)  
[10]  
Input Duty Cycle  
Over 10,000 cycles  
40%  
175  
t
CYCLE  
DCIN  
/ t  
Rise and Fall Times  
Measured at 20%–80% of input  
voltage for REFCLK and  
REFCLKB inputs  
ps  
RIN FIN  
Δt  
/ t  
[11]  
Rise and Fall Times Difference  
–
–
150  
0.6  
ps  
%
RIN FIN  
p
Modulation Index for triangular modulation  
Modulation Index for non-triangular modulation  
Input Frequency Modulation  
MIN  
[12]  
–
0.5  
%
[11]  
f
t
30  
1
33  
4
kHz  
V/ns  
MIN  
Input Slew Rate (measured at 20%–80% of  
input voltage) for REFCLK  
SR,IN  
C
C
Capacitance at REFCLK inputs  
Capacitance at CMOS inputs  
–
–
7
pF  
pF  
IN,REF  
10  
IN,CMOS  
f
SMBus clock frequency input in SCL pin  
DC  
100  
kHz  
SCL  
DC Electrical Specifications  
Parameter  
Description  
Min  
Typ  
1.08  
400  
–
Max  
–
Unit  
V
[6]  
[13]  
V
V
V
V
Differential output crossing point voltage  
–
OX  
[6]  
[14]  
Output voltage swing (peak-to-peak single-ended)  
Absolute output low voltage at CLK[3:0], CLK[3:0]B  
–
0.85  
0.98  
–
–
mV  
V
COS  
[15]  
REF  
–
OL,ABS  
Reference voltage for swing controlled current, I  
Power Supply Current at 2.625V, f = 100 MHz, and f = 300 MHz  
1.0  
–
1.02  
85  
125  
7.2  
–
V
ISET  
[7]  
I
I
I
I
mA  
mA  
DD  
ref  
out  
[7]  
Power Supply Current at 2.625V, f = 133 MHz, and f = 667 MHz  
–
–
DD  
ref  
out  
[16]  
I
Ratio of output low current to reference current  
6.8  
25  
–
7.0  
–
OL/ REF  
[17]  
Minimum current at V  
mA  
V
OL,ABS  
OL,ABS  
V
SDA output low voltage at test condition of SDA output low current = 4 mA  
SDA output low voltage at test condition of SDA voltage = 0.8V  
–
0.4  
–
OL,SDA  
OL,SDA  
OZ  
I
I
6
–
mA  
μA  
Ω
Current during High Z per pin at CLK[3:0], CLK[3:0]B  
–
–
10  
–
[18]  
Z
Output dynamic impedance when clock output signal is at V = 0.9V  
1000  
–
OUT  
OL  
Notes  
9. Jitter measured at crossing points and is the absolute value of the worst case deviation.  
10. Measured at crossing points.  
11. If input modulation is used; input modulation is allowed but not required.  
12. The amount of allowed spreading for any non-triangular modulation is determined by the induced downstream tracking skew that cannot exceed the skew generated  
by the specified 0.6% triangular modulation. Typically, the amount of allowed non-triangular modulation is about 0.5%.  
13. V is measured on external divider network.  
OX  
14. V  
15. V  
= (clock output high voltage – clock output low voltage), measured on the external divider network.  
COS  
is measured at the clock output pins of the package.  
OL_ABS  
16. I  
is equal to V  
/R  
.
REF  
ISET RC  
17. Minimum I  
is measured at the clock output pin with R = 266 ohms or less.  
OL,ABS  
RC  
18. Z  
is defined at the output pins as (0.94V – 0.90V)/(I  
– I  
) under conditions specified for I  
.
OUT  
0.94  
0.90  
OL, ABS  
Document Number: 001-42414 Rev. **  
Page 8 of 13  
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CY24272  
AC Electrical Specification  
[6]  
The AC Electrical specifications follow.  
Parameter  
Description  
Min  
1.25  
–
Typ  
Max  
3.34  
40  
Unit  
ns  
[19]  
t
t
Clock Cycle time  
CYCLE  
JIT(cc)  
[20]  
Jitter over 1-6 clock cycles at 400–635 MHz  
Jitter over 1-6 clock cycles at 638–667 MHz  
25  
25  
ps  
–
30  
ps  
L
Phase noise SSB spectral purity L(f) at 20 MHz offset: 400–500 MHz  
–
–135  
–128 dBC/Hz  
20  
6
2.4  
(In addition, device must not exceed L(f) = 10log[1+(50x10 /f) ] –138 for  
f = 1 MHz to 100 MHz except for the region near f = REFCLK/Q where Q is  
the value of the internal reference divider.)  
t
Cycle-to-cycle duty cycle error at 400–635 MHz  
Cycle-to-cycle duty cycle error at 636–667 MHz  
–
–
–
25  
25  
–
40  
30  
15  
ps  
ps  
ps  
JIT(hper,cc)  
Δt  
Drift in t  
when ambient temperature varies between 0°C and 70°C and  
SKEW  
SKEW  
[21]  
supply voltage varies between 2.375V and 2.625V.  
DC  
Long term average output duty cycle  
45%  
–100  
–
50  
–
55%  
100  
–
t
CYCLE  
t
t
PLL output phase error when tracking SSC  
ps  
EER,SCC  
,t  
Output rise and fall times at 400–667 MHz (measured at 20%–80% of output  
voltage)  
150  
ps  
CR CF  
t
Difference between output rise and fall times on the same pin of the single  
device (20%–80%) of 400–667 MHz  
–
–
100  
ps  
CR,CF  
[22]  
Table 9. SMBus Timing Specification  
Parameter  
Description  
Min Max  
Units  
FSMB  
SMBus Operating Frequency  
10  
4.7  
4.0  
100  
kHz  
μs  
TBUF  
Bus free time between Stop and Start Condition  
THD:STA  
Hold time after (Repeated) Start Condition.  
After this period, the first clock is generated.  
μs  
TSU:STA  
TSU:STO  
THD:DAT  
TSU:DAT  
TTIMEOUT  
TLOW  
Repeated Start Condition setup time  
Stop Condition setup time  
Data Hold time  
4.7  
4.0  
0
μs  
μs  
ns  
ns  
Data Setup time  
250  
Detect clock low timeout  
Clock low period  
Not supported  
4.7  
4.0  
μs  
THIGH  
Clock high period  
50  
25  
μs  
TLOW:SEXT Cumulative clock low extend time (slave device)  
ms  
CY24272 doesn’t  
extend  
TLOW:MEXT Cumulative clock low extend time (master device)  
10  
300  
1000  
500  
ms  
ns  
TF  
Clock/Data Fall Time  
TR  
Clock/Data Rise Time  
ns  
TPOR  
Time in which a device must be operational after power on reset  
ms  
Document Number: 001-42414 Rev. **  
Page 9 of 13  
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CY24272  
Test and Measurement Setup  
Figure 3. Clock Outputs  
Measurement  
Point  
VTS  
VT  
RT1  
R1  
ZCH  
CLK  
R2  
R
3 CS  
RT2  
Swing Current  
Control  
Differential Driver  
ISET  
Measurement  
Point  
VTS  
R1  
VT  
RRC  
RT1  
RT2  
ZCH  
CLKB  
R2  
R
3 CS  
Figure 5 on page 11 shows the definition of the output crossing  
point. The nominal crossing point between the complementary  
outputs is defined as the 50% point of the DC voltage levels.  
There are two crossing points defined: Vx+ at the rising edge of  
CLK and Vx– at the falling edge of CLK. For some waveforms,  
Example External Resistor Values  
and Termination Voltages for a 50Ω Channel  
Parameter  
Value  
33.0  
18.0  
17.0  
60.4  
301  
Unit  
R
Ω
1
both Vx+ and Vx– are below Vx,nom (for example, if t is larger  
CR  
R
Ω
than t ).  
2
CF  
R
Ω
3
Jitter  
R
Ω
T1  
This section defines the specifications that relate to timing uncer-  
tainty (or jitter) of the input and output waveforms. Figure 6 on  
page 11 shows the definition of cycle-to-cycle jitter with respect  
to the falling edge of the CLK signal. Cycle-to-cycle jitter is the  
difference between cycle times of adjacent cycles. Equal require-  
ments apply rising edges of the CLK signal. Figure 7 on page 11  
R
Ω
T2  
C
2700  
432  
pF  
Ω
S
R
RC  
V
2.5V  
1.2V  
V
TS  
V
V
shows the definition of cycle-to-cycle duty cycle error (t  
).  
T
DC,ERR  
Cycle-to-cycle duty cycle is defined as the difference between  
(high times) of adjacent differential clock cycles. Equal  
t
PW+  
Signal Waveforms  
requirements apply to t  
, low times of the differential click  
PW-  
cycles.  
A physical signal that appears at the pins of a device is deemed  
valid or invalid depending on its voltage and timing relations with  
other signals. Input and output voltage waveforms are defined as  
shown in Figure 4 on page 11. Both rise and fall times are defined  
between the 20% and 80% points of the voltage swing, with the  
swing defined as V –V .  
H
L
Notes  
19. Max and min output clock cycle times are based on nominal outputs frequency of 300 and 667 MHz, respectively. For spread spectrum modulated differential or  
single-ended REFCLK, the output clock tracks the modulation of the input.  
20. Output short term jitter spec is the absolute value of the worst case deviation.  
21. tSKEW is the timing difference between any two of the four differential clocks and is measured at common mode voltage. ΔtSKEW is the change in tSKEW when the  
operating temperature and supply voltage change.  
22. tCR,CF applies only when appropriate RRC and output resistor network resistor values are selected to match pull up and pull down currents.  
Document Number: 001-42414 Rev. **  
Page 10 of 13  
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CY24272  
Figure 4. Input and Output Waveforms  
VH  
80%  
V(t)  
20%  
VL  
tR  
tF  
Figure 5. Crossing Point Voltage  
CLK  
Vx+  
Vx.nom  
Vx-  
CLKB  
Figure 6. Cycle-to-cycle Jitter  
CLK  
CLKB  
tCYCLE,i  
tCYCLE,i+1  
tJ = tCYCLE,i - tCYCLE,i+1 over 10,000 consecutive cycles  
Figure 7. Cycle-to-cycle Duty-cycle Error  
CLK  
CLKB  
tPW-(i)  
tPW-(i+1)  
tPW+(i+1)  
tPW+(i)  
tCYCLE,(i+1)  
tCYCLE,(i)  
tDC,ERR = tPW-(i) - tPW-(i+1) and tPW-(i+1) - tPW+(i+1)  
Document Number: 001-42414 Rev. **  
Page 11 of 13  
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CY24272  
Ordering Information  
Part Number  
Pb-Free  
Package Type  
Product Flow  
CY24272ZXC  
28-pin TSSOP  
28-pin TSSOP – Tape and Reel  
Commercial, 0°C to 70°C  
Commercial, 0°C to 70°C  
CY24272ZXCT  
Package Drawing and Dimension  
Figure 8. 28-Pin Thin Shrunk Small Outline Package (4.40-mm Body) ZZ28  
PIN 1 ID  
1
6.25[0.246]  
6.50[0.256]  
4.30[0.169]  
4.50[0.177]  
28  
0.65[0.025]  
BSC.  
1.10[0.043] MAX.  
0.25[0.010]  
BSC  
0.19[0.007]  
0.30[0.012]  
GAUGE  
PLANE  
0°-8°  
0.076[0.003]  
0.50[0.020]  
0.70[0.027]  
0.05[0.002]  
0.15[0.006]  
0.85[0.033]  
0.95[0.037]  
0.09[[0.003]  
0.20[0.008]  
SEATING  
PLANE  
9.60[0.378]  
9.80[0.386]  
51-85120-*A  
Document Number: 001-42414 Rev. **  
Page 12 of 13  
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CY24272  
Document History Page  
®
Document Title: CY24272 Rambus XDR™ Clock Generator with Zero SDA Hold Time  
Document Number: 001-42414  
Issue  
Date  
Orig. of  
Change  
REV.  
ECN NO.  
Description of Change  
**  
1749003 See ECN KVM/AESA New data sheet  
No 8 or 15/2 multipliers or 133MHz * 4 option  
Max frequency is 667MHz  
© Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any  
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,  
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical  
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems  
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),  
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,  
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress  
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without  
the express written permission of Cypress.  
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES  
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not  
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where  
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer  
assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Use may be limited by and subject to the applicable Cypress software license agreement.  
Document Number: 001-42414 Rev. **  
Revised November 9, 2007  
Page 13 of 13  
PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered  
2
trademarks referenced herein are property of the respective corporations. Purchase of I C components from Cypress or one of its sublicensed Associated Companies conveys a license under the  
2
2
2
Philips I C Patent Rights to use these components in an I C system, provided that the system conforms to the I C Standard Specification as defined by Philips. Spread Aware is a trademark of Cypress  
Semiconductor Corporation. Rambus is a registered trademark, and XDR is a trademark, of Rambus Inc. All products and company names mentioned in this document may be the trademarks of their  
respective holders.  
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