Cypress EZ OTG CY7C67200 User Manual

CY7C67200

EZ-OTG™ Programmable USB

On-The-Go

EZ-OTG Features

• Single-chipprogrammableUSBdual-role(Host/Peripheral)

controller with two configurable Serial Interface Engines

(SIEs) and two USB ports

• SPI supports both master and slave

• Supports 12 MHz external crystal or clock

• 2.7V to 3.6V power supply voltage

• Package option: 48-pin FBGA

• Supports USB OTG protocol

• On-chip 48-MHz 16-bit processor with dynamically

switchable clock speed

Typical Applications

• Configurable IO block supports a variety of IO options or up

to 25 bits of General Purpose IO (GPIO)

EZ-OTG is a very powerful and flexible dual-role USB

controller that supports a wide variety of applications. It is

primarily intended to enable USB OTG capability in applica-

tions such as:

• 4K × 16 internal mask ROM contains built-in BIOS that

supports a communication-ready state with access to I C™

EEPROM interface, external ROM, UART, or USB

• Cellular phones

• 8K x 16 internal RAM for code and data buffering

• PDAs and pocket PCs

• Video and digital still cameras

• MP3 players

• 16-bit parallel host port interface (HPI) with DMA/Mailbox

data path for an external processor to directly access all

on-chip memory and control on-chip SIEs

• Fast serial port supports from 9600 baud to 2.0M baud

• Mass storage devices

Block Diagram

CY7C67200

Timer 0

Timer 1

nRESET

Control

UART I/F

Watchdog

CY16

16-bit RISC CORE

I2C

EEPROM I/F

Vbus, ID

D+,D-

OTG

USB-A

HSS I/F

SPI I/F

SIE1

HOST/

Peripheral

USB Ports

GPIO [24:0]

D+,D-

USB-A

4Kx16

8Kx16

ROM BIOS

RAM

HPI I/F

GPIO

SIE2

Mobile

Power

PLL

Booster

Cypress Semiconductor Corporation

Document #: 38-08014 Rev. *G

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised November 14, 2006

[+] Feedback

CY7C67200

USB Interface

OTG Interface

EZ-OTG has two built-in Host/Peripheral SIEs that each have

a single USB transceiver, meeting the USB 2.0 specification

requirements for full and low speed (high speed is not support-

ed). In Host mode, EZ-OTG supports two downstream ports;

each supports control, interrupt, bulk, and isochronous trans-

fers. In Peripheral mode, EZ-OTG supports one peripheral

port with eight endpoints for each of the two SIEs. Endpoint 0

is dedicated as the control endpoint and only supports control

transfers. Endpoints 1 though 7 support Interrupt, bulk (up to

64 bytes per packet), or isochronous transfers (up to 1023

bytes per packet size). EZ-OTG also supports a combination

of Host and Peripheral ports simultaneously, as shown in

T a ble 2.

EZ-OTG has one USB port that is compatible with the USB

On-The-Go supplement to the USB 2.0 specification. The USB

OTG port has various hardware features to support Session

Request Protocol (SRP) and Host Negotiation Protocol (HNP).

OTG is only supported on USB PORT 1A.

OTG Features

• Internal Charge Pump to supply and control VBUS

• VBUS Valid Status (above 4.4V)

• VBUS Status for 2.4V < VBUS < 0.8V

• ID Pin Status

• Switchable 2-Kohm internal discharge resistor on VBUS

• Switchable 500-ohm internal pull-up resistor on VBUS

Table 2. USB Port Configuration Options

• Individually switchable internal pull-up and pull-down

resistors on the USB data lines

Port Configurations

OTG

Port 1A

OTG

Port 2A

–

OTG Pins

OTG + 1 Host

OTG + 1 Peripheral

1 Host + 1 Peripheral

2 Hosts

OTG

Host

Table 4. OTG Interface Pins

OTG

Peripheral

Host

Pin Name

Pin Number

Peripheral

Host

DM1A

DP1A

Host

1 Host

Host

–

OTGVBUS

OTGID

1 Host

–

Host

2 Peripherals

1 Peripheral

Peripheral

–

Peripheral

–

CSwitchA

CSwitchB

1 Peripheral

Peripheral

General Purpose IO Interface

USB Features

EZ-OTG has up to 25 GPIO signals available. Several other

optional interfaces use GPIO pins as well and may reduce the

overall number of available GPIOs.

• USB 2.0 compatible for full and low speed

• Up to two downstream USB host ports

• Up to two upstream USB peripheral ports

GPIO Description

• Configurable endpoint buffers (pointer and length), must

reside in internal RAM

All Inputs are sampled asynchronously with state changes oc-

curring at a rate of up to two 48 MHz clock cycles. GPIO pins

are latched directly into registers, a single flip-flop.

• Up to eight available peripheral endpoints (1 control

endpoint)

Unused Pin Descriptions

• SupportsControl, Interrupt, Bulk, andIsochronoustransfers

• Internal DMA channels for each endpoint

Unused USB pins must be tri-stated with the D+ line pulled

high through the internal pull-up resistor and the D– line pulled

low through the internal pull-down resistor.

• Internal pull up and pull down resistors

• Internal Series termination resistors on USB data lines

Unused GPIO pins must be configured as outputs and driven

low.

USB Pins

UART Interface

Table 3. USB Interface Pins

EZ-OTG has a built-in UART interface. The UART interface

supports data rates from 900 to 115.2K baud. It can be used

as a development port or for other interface requirements. The

UART interface is exposed through GPIO pins.

Pin Name

Pin Number

DM1A

DP1A

DM2A

DP2A

Document #: 38-08014 Rev. *G

Page 3 of 78

[+] Feedback

CY7C67200

UART Features

• Individual bit transfer for non-byte aligned serial communi-

cation in PIO mode

• Supports baud rates of 900 to 115.2K

• 8-N-1

• Programmable delay timing for the active/inactive master

SPI clock

UART Pins

• Auto or manual control for master mode slave select signal

• Complete access to internal memory

Table 5. UART Interface Pins

Pin Name

Pin Number

SPI Pins

The SPI port has a few different pin location options as shown

in T a ble 7. The pin location is selectable via the GPIO Control

Table 7. SPI Interface Pins

I C EEPROM Interface

EZ-OTG provides a master-only I2C interface for external se-

rial EEPROMs. The serial EEPROM can be used to store ap-

plication-specific code and data. This I2C interface is only to

be used for loading code out of EEPROM, it is not a general

I2C interface. The I2C EEPROM interface is a BIOS imple-

mentation and is exposed through GPIO pins. Refer to the

BIOS documentation for additional details on this interface.

Pin Name

Pin Number

nSSI

SCK

F6 or C6

MOSI

MISO

I C EEPROM Features

High-Speed Serial Interface

• Supports EEPROMs up to 64 KB (512K bit)

• Auto-detection of EEPROM size

EZ-OTG provides an HSS interface. The HSS interface is a

programmable serial connection with baud rate from 9600

baud to 2M baud. The HSS interface supports both byte and

block mode operations as well as hardware and software

handshaking. Complete control of EZ-OTG can be accom-

plished through this interface via an extensible API and com-

munication protocol. The HSS interface can be exposed

through GPIO pins or the External Memory port.

I C EEPROM Pins

Table 6. I C EEPROM Interface Pins

Pin Name

Pin Number

SMALL EEPROM

SCK

SDA

HSS Features

• 8-bit, no parity code

• Programmable baud rate from 9600 baud to 2M baud

• Selectable 1- or 2-stop bit on transmit

• Programmable intercharacter gap timing for Block Transmit

• 8-byte receive FIFO

LARGE EEPROM

SCK

SDA

• Glitch filter on receive

Serial Peripheral Interface

• Block mode transfer directly to/from EZ-OTG internal

memory (DMA transfer)

EZ-OTG provides an SPI interface for added connectivity.

EZ-OTG may be configured as either an SPI master or SPI

slave. The SPI interface can be exposed through GPIO pins

or the External Memory port.

• Selectable CTS/RTS hardware signal handshake protocol

• Selectable XON/XOFF software handshake protocol

• Programmable Receive interrupt, Block Transfer Done

interrupts

SPI Features

• Master or slave mode operation

• Complete access to internal memory

• DMA block transfer and PIO byte transfer modes

• Full duplex or half duplex data communication

• 8-byte receive FIFO and 8-byte transmit FIFO

• Selectable master SPI clock rates from 250 kHz to 12 MHz

• Selectable master SPI clock phase and polarity

• Slave SPI signaling synchronization and filtering

• Slave SPI clock rates up to 2 MHz

HSS Pins

Table 8. HSS Interface Pins

Pin Name

Pin Number

CTS

RTS

• Maskable interrupts for block and byte transfer modes

Document #: 38-08014 Rev. *G

Page 4 of 78

[+] Feedback

CY7C67200

[1, 2]

Host Port Interface (HPI)

Table 9. HPI Interface Pins

(continued)

EZ-OTG has an HPI interface. The HPI interface provides

DMA access to the EZ-OTG internal memory by an external

host, plus a bidirectional mailbox register for supporting

high-level communication protocols. This port is designed to

be the primary high-speed connection to a host processor.

Complete control of EZ-OTG can be accomplished through

this interface via an extensible API and communication

protocol. Other than the hardware communication protocols, a

host processor has identical control over EZ-Host whether

connecting to the HPI or HSS port. The HPI interface is

exposed through GPIO pins.

Pin Name

Pin Number

Note It should be noted that for up to 3 ms after BIOS starts

executing, GPIO[24:19] and GPIO[15:8] will be driven as

outputs for a test mode. If these pins need to be used as inputs,

a series resistor is required (10 ohm to 48 ohm is recom-

mended). Refer to BIOS documentation for addition details.

See section “Reset Pin” on page 9.

The two HPI address pins are used to address one of four

possible HPI port registers as shown in T a ble 10 below.

Table 10.HPI Addressing

HPI A[1:0]

HPI Data

HPI Features

• 16-bit data bus interface

• 16 MB/s throughput

HPI Mailbox

HPI Address

HPI Status

• Auto-increment of address pointer for fast block mode

transfers

• Direct memory access (DMA) to internal memory

• Bidirectional Mailbox register

Charge Pump Interface

VBUS for the USB On-The-Go (OTG) port can be produced by

EZ-OTG using its built-in charge pump and some external

components. The circuit connections should look similar to

Figure 1 below.

• Byte Swapping

• Complete access to internal memory

• Complete control of SIEs through HPI

• Dedicated HPI Status register

Figure 1. Charge Pump

HPI Pins

[1, 2]

Table 9. HPI Interface Pins

CSWITCHA

Pin Name

Pin Number

CY7C67200

INT

nRD

nWR

nCS

CSWITCHB

VBUS

OTGVBUS

Component details:

• D1 and D2: Schottky diodes with a current rating greater

than 60 mA.

D15

D14

D13

D12

D11

D10

• C1: Ceramic capacitor with a capacitance of 0.1 µF.

• C2: Capacitor value must be no more that 6.5 µF since that

is the maximum capacitance allowed by the USB OTG

specification for a dual-role device. The minimum value of

C2 is 1 µF. There are no restrictions on the type of capacitor

for C2.

If the VBUS charge pump circuit is not to be used,

CSWITCHA, CSWITCHB, and OTGVBUS can be left uncon-

nected.

Notes

1. HPI_INT is for the Outgoing Mailbox Interrupt.

2. HPI strobes are negative logic sampled on rising edge.

Document #: 38-08014 Rev. *G

Page 5 of 78

[+] Feedback

CY7C67200

Charge Pump Features

Figure 3. Power Supply Connection Without Booster

• Meets OTG Supplement Requirements, see T a ble 41, “DC

Characteristics: Charge Pump,” on page 66.

BOOSTVcc

3.0V to 3.6V

Power Supply

Charge Pump Pins

Table 11.Charge Pump Interface Pins

Pin Name

OTGVBUS

Pin Number

VSWITCH

CSwitchA

CSwitchB

VCC

AVCC

Booster Interface

EZ-OTG has an on-chip power booster circuit for use with

power supplies that range between 2.7V and 3.6V. The

booster circuit boosts the power to 3.3V nominal to supply

power for the entire chip. The booster circuit requires an

external inductor, diode, and capacitor. During power down

mode, the circuit is disabled to save power. Figure 2 shows

how to connect the booster circuit.

Booster Pins

Table 12.Charge Pump Interface Pins

Pin Name

BOOSTVcc

Pin Number

Figure 2. Power Supply Connection With Booster

VSWITCH

BOOSTVcc

2.7V to 3.6V

Power Supply

Crystal Interface

The recommended crystal circuit to be used with EZ-OTG is

shown in Figure 4. If an oscillator is used instead of a crystal

circuit, connect it to XTALIN and leave XTALOUT uncon-

nected. For further information on the crystal requirements,

see T a ble 39, “Crystal Requirements,” on page 65.

VSWITCH

3.3V

Figure 4. Crystal Interface

VCC

AVCC

XTALIN

CY7C67200

Component details:

12MHz

Parallel Resonant

Fundamental Mode

500uW

• L1: Inductor with inductance of 10 µH and a current rating

of at least 250 mA

20-33pf ±5%

• D1: Schottky diode with a current rating of at least 250 mA

XTALOUT

• C1: Tantalum or ceramic capacitor with a capacitance of at

least 2.2 µF

C2 = 22 pF

C1 = 22 pF

Figure 3 shows how to connect the power supply when the

booster circuit is not being used.

Document #: 38-08014 Rev. *G

Page 6 of 78

[+] Feedback

CY7C67200

Crystal Pins

Operational Modes

There are two modes of operation: Coprocessor and

Standalone.

Table 13.Crystal Pins

Pin Name

XTALIN

Pin Number

Coprocessor Mode

EZ-OTG can act as a coprocessor to an external host

processor. In this mode, an external host processor drives

EZ-OTG and is the main processor rather then EZ-OTG’s own

16-bit internal CPU. An external host processor may interface

to EZ-OTG through one of the following three interfaces in

coprocessor mode:

XTALOUT

Boot Configuration Interface

EZ-OTG can boot into any one of four modes. The mode it

boots into is determined by the TTL voltage level of

GPIO[31:30] at the time nRESET is deasserted. T a ble 14

shows the different boot pin combinations possible. After a

reset pin event occurs, the BIOS bootup procedure executes

for up to 3 ms. GPIO[31:30] are sampled by the BIOS during

bootup only. After bootup these pins are available to the appli-

cation as GPIOs.

• HPI mode, a 16-bit parallel interface with up to 16 MBytes

transfer rate

• HSS mode, a serial interface with up to 2M baud transfer

rate

• SPI mode, a serial interface with up to 2 Mbits/s transfer

rate.

Table 14.Boot Configuration Interface

At bootup GPIO[31:30] determine which of these three inter-

faces are used for coprocessor mode. Refer to T a ble 14 for

details. Bootloading begins from the selected interface after

POR + 3 ms of BIOS bootup.

GPIO31 GPIO30

Boot Mode

(Pin 39) (Pin 40)

Host Port Interface (HPI)

High Speed Serial (HSS)

Standalone Mode

Serial Peripheral Interface (SPI, slave

mode)

In standalone mode, there is no external processor connected

to EZ-OTG. Instead, EZ-OTG’s own internal 16-bit CPU is the

main processor and firmware is typically downloaded from an

EEPROM. Optionally, firmware may also be downloaded via

USB. Refer to T a ble 14 for booting into standalone mode.

I2C EEPROM (Standalone Mode)

GPIO[31:30] must be pulled high or low, as needed, using

resistors tied to V or GND with resistor values between 5K

ohm and 15K ohm. GPIO[31:30] must not be tied directly to

After booting into standalone mode (GPIO[31:30] = ‘11’), the

following pins are affected:

or GND. Note that in Standalone mode, the pull ups on

• GPIO[31:30] are configured as output pins to examine the

EEPROM contents.

those two pins are used for the serial I2C EEPROM (if imple-

mented). The resistors used for these pull ups must conform

to the serial EEPROM manufacturer's requirements.

• GPIO[28:27] are enabled for debug UART mode.

• GPIO[29] is configured as OTGID for OTG applications on

PORT1A.

If any mode other then standalone is chosen, EZ-OTG will be

in coprocessor mode. The device will power up with the appro-

priate communication interface enabled according to its boot

pins and wait idle until a coprocessor communicates with it.

See the BIOS documentation for greater detail on the boot

process.

— If OTGID is logic 1 then PORT1A (OTG) is configured

as a USB peripheral.

— If OTGID is logic 0 then PORT1A (OTG) is configured

as a USB host.

• Ports 1B, 2A, and 2B default as USB peripheral ports.

• All other pins remain INPUT pins.

Document #: 38-08014 Rev. *G

Page 7 of 78

[+] Feedback

CY7C67200

Minimum Hardware Requirements for Standalone Mode – Peripheral Only

Figure 5. Minimum Standalone Hardware Configuration – Peripheral Only

EZ-OTG

CY7C67200

Reset

Logic

nRESET

VCC, AVCC,

BoostVCC

VReg

VBus

D+

DPlus

Standard-B

or Mini-B

DMinus

D-

GND

SHIELD

Bootstrap Options

Vcc Vcc

10k 10k

GPIO[30]

GPIO[31]

SCL*

SDA*

Int. 16k x8

Code / Data

Bootloading Firmware

VCC

Up to 64k x8

EEPROM

SCL

SDA

Reserved

22pf

GND

XIN

GND, AGND,

BoostGND

12MHz

XOUT

22pf

Parallel Resonant

*Bootloading begins after POR + 3ms BIOS bootup

Fundamental Mode

500uW

20-33pf ±5%

*GPIO[31:30]

Up to 2k x8

>2k x8 to 64k x8 SDA SCL

SCL SDA

Sleep

Power Savings and Reset Description

Sleep mode is the main chip power down mode and is also

used for USB suspend. Sleep mode is entered by setting the

Sleep Enable (bit 1) of the Power Control register [0xC00A].

During Sleep mode (USB Suspend) the following events and

states are true:

The EZ-OTG modes and reset conditions are described in this

section.

Power Savings Mode Description

EZ-OTG has one main power savings mode, Sleep. For

detailed information on Sleep mode; See section “Sleep”.

• GPIO pins maintain their configuration during sleep (in

suspend).

Sleep mode is used for USB applications to support USB

suspend and non USB applications as the main chip power

down mode.

• External Memory Address pins are driven low.

• XTALOUT is turned off.

• Internal PLL is turned off.

In addition, EZ-OTG is capable of slowing down the CPU clock

speed through the CPU Speed register [0xC008] without

affecting other peripheral timing. Reducing the CPU clock

speed from 48 MHz to 24 MHz reduces the overall current

draw by around 8 mA while reducing it from 48 MHz to 3 MHz

reduces the overall current draw by approximately 15 mA.

• Firmware must disable the charge pump (OTG Control

Otherwise OTGVBUS will only drop to V – (2 schottky

diode drops).

• Booster circuit is turned off.

• USB transceivers is turned off.

• CPU suspends until a programmable wakeup event.

Document #: 38-08014 Rev. *G

Page 8 of 78

[+] Feedback

CY7C67200

External (Remote) Wakeup Source

registers, USB control registers, the stack, and other BIOS

variables. The upper internal memory space contains EZ-OTG

control registers from 0xC000 to 0xC0FF and the BIOS ROM

itself from 0xE000 to 0xFFFF. For more information on the

reserved lower memory or the BIOS ROM, refer to the

Programmers documentation and the BIOS documentation.

There are several possible events available to wake EZ-OTG

from Sleep mode as shown in T a ble 15. These may also be

used as remote wakeup options for USB applications. See

section “Power Control Register [0xC00A] [R/W]” on page 13.

Upon wakeup, code begins executing within 200 ms, the time

it takes the PLL to stabilize.

During development with the EZ-OTG toolset, the lower area

of User's space (0x04A4 to 0x1000) should be left available to

load the GDB stub. The GDB stub is required to allow the

toolset debug access into EZ-OTG.

[3, 4]

Table 15.wakeup Sources

Wakeup Source (if enabled)

Event

D+/D– Signaling

Level

Figure 6. Memory Map

USB Resume

OTGVBUS

OTGID

Internal Memory

Any Edge

Read

HW INTs

0x0000 - 0x00FF

HPI

HSS

Read

SW INTs

SPI

Read

Primary Registers

Swap Registers

HPI Int / Mailbox

0x0100 - 0x011F

0x0120 - 0x013F

0x0140 - 0x0148

0x014A - 0x01FF

IRQ0 (GPIO 24)

Any Edge

Power-On Reset (POR) Description

LCP Variables

The length of the power-on-reset event can be defined by (V

ramp to valid) + (Crystal start up). A typical application might

utilize a 12-ms power-on-reset event = ~7 ms + ~5 ms, respec-

tively.

0x0200- 0x02FF

USB Registers

0x0300- 0x030F

0x0310- 0x03FF

0x0400- 0x04A2

Slave Setup Packet

BIOS Stack

USB Slave & OTG

Reset Pin

The Reset pin is active low and requires a minimum pulse

duration of sixteen 12-MHz clock cycles (1.3 ms). A reset

event restores all registers to their default POR settings. Code

execution then begins 200 ms later at 0xFF00 with an imme-

diate jump to 0xE000, the start of BIOS.

USER SPACE

~15K

0x04A4- 0x3FFF

Note It should be noted that for up to 3 ms after BIOS starts

executing, GPIO[24:19] and GPIO[15:8] will be driven as out-

puts for a test mode. If these pins need to be used as inputs,

a series resistor is required (10 ohm to 48 ohm is recommend-

ed). Refer to BIOS documentation for addition details.

USB Reset

A USB Reset affects registers 0xC090 and 0xC0B0, all other

registers remain unchanged.

Memory Map

Memory map information is presented in this section.

Mapping

The EZ-OTG has just over 24 KB of addressable memory

mapped from 0x0000 to 0xFFFF. This 24 KB contains both

program and data space and is byte addressable. Figure 6.

shows the various memory region address locations.

Control Registers

0xC000- 0xC0FF

0xE000- 0xFFFF

Internal Memory

BIOS

Of the internal memory, 15 KB is allocated for user’s program

and data code. The lower memory space from 0x0000 to

0x04A2 is reserved for interrupt vectors, general purpose

Notes

3. Read data will be discarded (dummy data).

4. HPI_INT will assert on a USB Resume.registers

Document #: 38-08014 Rev. *G

Page 9 of 78

[+] Feedback

CY7C67200

Registers

Table 16.Processor Control Registers

Some registers have different functions for a read vs. a write

access or USB host vs. USB device mode. Therefore,

registers of this type have multiple definitions for the same

address.

CPU Flags Register

Address

R/W

0xC000

0xC002

0xC004

0xC008

0xC00A

0xC00E

0xC014

0xC03C

Hardware Revision Register

CPU Speed Register

R/W

The default register values listed in this data sheet may be

altered to some other value during BIOS initialization. Refer to

the BIOS documentation for Register initialization information.

R/W

Power Control Register

Interrupt Enable Register

Breakpoint Register

Processor Control Registers

There are eight registers dedicated to general processor

control. Each of these registers is covered in this section and

is summarized in T a ble 16.

USB Diagnostic Register

CPU Flags Register [0xC000] [R]

Figure 7. CPU Flags Register

Bit #

Field

Reserved...

Read/Write

Default

Bit #

...Reserved

Global

Interrupt

Enable

Negative

Flag

Overflow

Flag

Carry

Flag

Zero

Flag

Field

Read/Write

Default

result was either larger than the destination operand size (for

addition) or smaller than the destination operand should allow

for subtraction.

The CPU Flags register is a read only register that gives

processor flags status.

1: Overflow occurred

Global Interrupt Enable (Bit 4)

0: Overflow did not occur

The Global Interrupt Enable bit indicates if the Global Inter-

rupts are enabled.

Carry Flag (Bit 1)

1: Enabled

The Carry Flag bit indicates if an arithmetic operation resulted

in a carry for addition, or borrow for subtraction.

0: Disabled

1: Carry/Borrow occurred

Negative Flag (Bit 3)

0: Carry/Borrow did not occur

The Negative Flag bit indicates if an arithmetic operation

results in a negative answer.

Zero Flag (Bit 0)

1: MS result bit is ‘1’

The Zero Flag bit indicates if an instruction execution resulted

in a ‘0’.

0: MS result bit is not ‘1’

1: Zero occurred

Overflow Flag (Bit 2)

0: Zero did not occur

The Overflow Flag bit indicates if an overflow condition has

occurred. An overflow condition can occur if an arithmetic

Document #: 38-08014 Rev. *G

Page 10 of 78

[+] Feedback

CY7C67200

Bank Register [0xC002] [R/W]

Figure 8. Bank Register

Bit #

Field

Address...

Read/Write

Default

R/W

Bit #

...Address

R/W

Field

Reserved

Read/Write

Default

R/W

Table 17.Bank Register Example

The Bank register maps registers R0–R15 into RAM. The

eleven MSBs of this register are used as a base address for

registers R0–R15. A register address is automatically

generated by:

Bank

Hex Value

Binary Value

0x0100

0000 0001 0000 0000

R14

0x000E << 1 = 0x001C 0000 0000 0001 1100

0x011C 0000 0001 0001 1100

1. Shifting the four LSBs of the register address left by 1

RAM

Location

2. ORing the four shifted bits of the register address with the

12 MSBs of the Bank Register

Address (Bits [15:4])

3. Forcing the LSB to zero

The Address field is used as a base address for all register

addresses to start from.

For example, if the Bank register is left at its default value of

0x0100, and R2 is read, then the physical address 0x0102 will

be read. See T a ble 17 for details.

Reserved

All reserved bits must be written as ‘0’.

Hardware Revision Register [0xC004] [R]

Figure 9. Revision Register

Bit #

Field

Revision...

Read/Write

Default

Bit #

Field

...Revision

Read/Write

Default

Revision (Bits [15:0])

The Revision field contains the silicon revision number.

The Hardware Revision register is a read-only register that

indicates the silicon revision number. The first silicon revision

is represented by 0x0101. This number is increased by one for

each new silicon revision.

Document #: 38-08014 Rev. *G

Page 11 of 78

[+] Feedback

CY7C67200

CPU Speed Register [0xC008] [R/W]

Figure 10. CPU Speed Register

Bit #

Field

Reserved...

Read/Write

Default

Bit #

Field

...Reserved

CPU Speed

Read/Write

Default

R/W

The CPU Speed register allows the processor to operate at a user selected speed. This register only affects the CPU; all other

peripheral timing is still based on the 48-MHz system clock (unless otherwise noted).

CPU Speed (Bits[3:0])

The CPU Speed field is a divisor that selects the operating speed of the processor as defined in T a ble 18.

Table 18.CPU Speed Definition

CPU Speed [3:0]

0000

Processor Speed

48 MHz/1

0001

48 MHz/2

0010

48 MHz/3

0011

48 MHz/4

0100

48 MHz/5

0101

48 MHz/6

0110

48 MHz/7

0111

48 MHz/8

1000

48 MHz/9

1001

48 MHz/10

48 MHz/11

48 MHz/12

48 MHz/13

48 MHz/14

48 MHz/15

48 MHz/16

1010

1011

1100

1101

1110

1111

Reserved

All reserved bits must be written as ‘0’.

Document #: 38-08014 Rev. *G

Page 12 of 78

[+] Feedback

CY7C67200

Power Control Register [0xC00A] [R/W]

Figure 11. Power Control Register

Bit #

Reserved

Host/Device 2

Wake Enable

Reserved

Host/Device 1

OTG

Reserved

HSS

SPI

Field

Wake Enable Wake Enable

Read/Write

Default

R/W

Bit #

HPI

Wake Enable

Reserved

GPI

Wake Enable

Reserved

Boost 3V

Sleep

Enable

Halt

Enable

Field

Read/Write

Default

R/W

SPI Wake Enable (Bit 8)

The Power Control register controls the power-down and

wakeup options. Either the sleep mode or the halt mode

options can be selected. All other writable bits in this register

can be used as a wakeup source while in sleep mode.

The SPI Wake Enable bit enables or disables a wakeup

condition to occur on a falling SPI_nSS input transition. The

processor may take several hundreds of microseconds before

being operational after wakeup. Therefore, the incoming data

byte that causes the wakeup will be discarded.

Host/Device 2 Wake Enable (Bit 14)

1: Enable wakeup on falling SPI nSS input transition

The Host/Device 2 Wake Enable bit enables or disables a

wakeup condition to occur on an Host/Device 2 transition. This

wake up from the SIE port does not cause an interrupt to the

on-chip CPU.

0: Disable SPI_nSS interrupt

HPI Wake Enable (Bit 7)

The HPI Wake Enable bit enables or disables a wakeup

condition to occur on an HPI interface read.

1: Enable wakeup on Host/Device 2 transition.

0: Disable wakeup on Host/Device 2 transition.

1: Enable wakeup on HPI interface read

Host/Device 1 Wake Enable (Bit 12)

0: Disable wakeup on HPI interface read

The Host/Device 1 Wake Enable bit enables or disables a

wakeup condition to occur on an Host/Device 1 transition. This

wakeup from the SIE port does not cause an interrupt to the

on-chip CPU.

GPI Wake Enable (Bit 4)

The GPI Wake Enable bit enables or disables a wakeup

condition to occur on a GPIO(25:24) transition.

1: Enable wakeup on Host/Device 1 transition

1: Enable wakeup on GPIO(25:24) transition

0: Disable wakeup on GPIO(25:24) transition

Boost 3V OK (Bit 2)

0: Disable wakeup on Host/Device 1 transition

OTG Wake Enable (Bit 11)

The Boost 3V OK bit is a read only bit that returns the status

of the OTG Boost circuit.

The OTG Wake Enable bit enables or disables a wakeup

condition to occur on either an OTG VBUS_Valid or OTG ID

transition (IRQ20).

1: Boost circuit not ok and internal voltage rails are below 3.0V

1: Enable wakeup on OTG VBUS valid or OTG ID transition

0: Boost circuit ok and internal voltage rails are at or above

3.0V

0: Disable wakeup on OTG VBUS valid or OTG ID transition

Sleep Enable (Bit 1)

HSS Wake Enable (Bit 9)

Setting this bit to ‘1’ immediately initiates SLEEP mode. While

in SLEEP mode, the entire chip is paused achieving the lowest

standby power state. All operations are paused, the internal

clock is stopped, the booster circuit and OTG VBUS charge

pump are all powered down, and the USB transceivers are

powered down. All counters and timers are paused but will

retain their values. SLEEP mode exits by any activity selected

in this register. When SLEEP mode ends, instruction

execution resumes within 0.5 ms.

The HSS Wake Enable bit enables or disables a wakeup

condition to occur on an HSS Rx serial input transition. The

processor may take several hundreds of microseconds before

being operational after wakeup. Therefore, the incoming data

byte that causes the wakeup will be discarded.

1: Enable wakeup on HSS Rx serial input transition

0: Disable wakeup on HSS Rx serial input transition

1: Enable Sleep Mode

0: No Function

Document #: 38-08014 Rev. *G

Page 13 of 78

[+] Feedback

CY7C67200

Halt Enable (Bit 0)

immediately following the HALT instruction may be executed

before the waking interrupt is serviced (you may want to follow

the HALT instruction with two NOPs).

Setting this bit to ‘1’ immediately initiates HALT mode. While

in HALT mode, only the CPU is stopped. The internal clock still

runs and all peripherals still operate, including the USB

engines. The power savings using HALT in most cases will be

minimal, but in applications that are very CPU intensive the

incremental savings may provide some benefit.

1: Enable Halt Mode

0: No Function

Reserved

The HALT state is exited when any enabled interrupt is

triggered. Upon exiting the HALT state, one or two instructions

All reserved bits must be written as ‘0’.

Interrupt Enable Register [0xC00E] [R/W]

Figure 12. Interrupt Enable Register

Bit #

Reserved

OTG

Interrupt

Enable

SPI

Interrupt

Enable

Reserved

Host/Device 2 Host/Device 1

Interrupt

Enable

Interrupt

Enable

Field

Read/Write

Default

R/W

Bit #

HSS

Interrupt

Enable

In Mailbox

Interrupt

Enable

Out Mailbox

Interrupt

Enable

Reserved

UART

Interrupt

Enable

GPIO

Interrupt

Enable

Timer 1

Interrupt

Enable

Timer 0

Interrupt

Enable

Field

Read/Write

Default

R/W

Host/Device 1 Interrupt Enable (Bit 8)

The Interrupt Enable Register allows control of the hardware

interrupt vectors.

The Host/Device 1 Interrupt Enable bit enables or disables all

of the following Host/Device 1 hardware interrupts: Host 1

USB Done, Host

USB SOF/EOP, Host

OTG Interrupt Enable (Bit 12)

WakeUp/Insert/Remove, Device 1 Reset, Device 1 SOF/EOP

or WakeUp from USB, Device 1 Endpoint n.

The OTG Interrupt Enable bit enables or disables the OTG

ID/OTG4.4V Valid hardware interrupt.

1: Enable Host 1 and Device 1 interrupt

1: Enable OTG interrupt

0: Disable Host 1 and Device 1 interrupt

0: Disable OTG interrupt

HSS Interrupt Enable (Bit 7)

SPI Interrupt Enable (Bit 11)

The HSS Interrupt Enable bit enables or disables the following

High-speed Serial Interface hardware interrupts: HSS Block

Done, and HSS RX Full.

The SPI Interrupt Enable bit enables or disables the following

three SPI hardware interrupts: SPI TX, SPI RX, and SPI DMA

Block Done.

1: Enable HSS interrupt

1: Enable SPI interrupt

0: Disable HSS interrupt

0: Disable SPI interrupt

In Mailbox Interrupt Enable (Bit 6)

Host/Device 2 Interrupt Enable (Bit 9)

The In Mailbox Interrupt Enable bit enables or disables the

HPI: Incoming Mailbox hardware interrupt.

The Host/Device 2 Interrupt Enable bit enables or disables all

of the following Host/Device 2 hardware interrupts: Host 2

1: Enable MBXI interrupt

USB Done, Host

USB SOF/EOP, Host

0: Disable MBXI interrupt

WakeUp/Insert/Remove, Device 2 Reset, Device 2 SOF/EOP

or WakeUp from USB, Device 2 Endpoint n.

Out Mailbox Interrupt Enable (Bit 5)

1: Enable Host 2 and Device 2 interrupt

The Out Mailbox Interrupt Enable bit enables or disables the

HPI: Outgoing Mailbox hardware interrupt.

0: Disable Host 2 and Device 2 interrupt

1: Enable MBXO interrupt

0: Disable MBXO interrupt

Document #: 38-08014 Rev. *G

Page 14 of 78

[+] Feedback

CY7C67200

UART Interrupt Enable (Bit 3)

Timer 1 Interrupt Enable (Bit 1)

The UART Interrupt Enable bit enables or disables the

following UART hardware interrupts: UART TX and UART RX.

The Timer 1 Interrupt Enable bit enables or disables the

TImer1 Interrupt Enable. When this bit is reset, all pending

Timer 1 interrupts are cleared.

1: Enable UART interrupt

1: Enable TM1 interrupt

0: Disable UART interrupt

0: Disable TM1 interrupt

GPIO Interrupt Enable (Bit 2)

Timer 0 Interrupt Enable (Bit 0)

The GPIO Interrupt Enable bit enables or disables the General

Purpose IO Pins Interrupt (See the GPIO Control Register).

When GPIO bit is reset, all pending GPIO interrupts are also

cleared.

The Timer 0 Interrupt Enable bit enables or disables the

TImer0 Interrupt Enable. When this bit is reset, all pending

Timer 0 interrupts are cleared.

1: Enable GPIO interrupt

1: Enable TM0 interrupt

0: Disable GPIO interrupt

0: Disable TM0 interrupt

Reserved

All reserved bits must be written as ‘0’.

Breakpoint Register [0xC014] [R/W]

Figure 13. Breakpoint Register

Bit #

Field

Address...

Read/Write

Default

R/W

Bit #

Field

...Address

Read/Write

Default

R/W

The Breakpoint Register holds the breakpoint address. When the program counter match this address, the INT127 interrupt

occurs. To clear this interrupt, a zero value must be written to this register.

Address (Bits [15:0])

The Address field is a 16-bit field containing the breakpoint address.

Document #: 38-08014 Rev. *G

Page 15 of 78

[+] Feedback

CY7C67200

USB Diagnostic Register [0xC03C] [R/W]

Figure 14. USB Diagnostic Register

Bit #

Reserved

Port 2A

Diagnostic

Enable

Reserved

Port 1A

Diagnostic

Enable

Reserved...

Field

Read/Write

Default

R/W

Bit #

...Reserved

Pull-down

Enable

LS Pull-up

Enable

FS Pull-up

Enable

Reserved

Force Select

Field

Read/Write

Default

R/W

FS Pull-up Enable (Bit 4)

The USB Diagnostic Register provides control of diagnostic

modes. It is intended for use by device characterization tests,

not for normal operations. This register is Read/Write by the

on-chip CPU but is write-only via the HPI port.

The FS Pull-up Enable bit enables or disables a full-speed

pull-up resistor (pull up on D+) for testing.

1: Enable full-speed pull-up resistor on D+

0: Pull-up resistor is not connected on D+

Port 2A Diagnostic Enable (Bit 15)

Force Select (Bits [2:0])

The Port 2A Diagnostic Enable bit enables or disables Port 2A

for the test conditions selected in this register.

The Force Select field bit selects several different test

condition states on the data lines (D+/D–). See T a ble 19 for

details.

1: Apply any of the following enabled test conditions: J/K,

DCK, SE0, RSF, RSL, PRD

Table 19.Force Select Definition

0: Do not apply test conditions

Force Select [2:0]

Data Line State

Assert SE0

Toggle JK

Assert J

Port 1A Diagnostic Enable (Bit 15)

1xx

01x

001

000

The Port 1A Diagnostic Enable bit enables or disables Port 1A

for the test conditions selected in this register.

1: Apply any of the following enabled test conditions: J/K,

DCK, SE0, RSF, RSL, PRD

Assert K

0: Do not apply test conditions

Reserved

Pull-down Enable (Bit 6)

All reserved bits must be written as ‘0’.

The Pull-down Enable bit enables or disables full-speed

pull-down resistors (pull down on both D+ and D–) for testing.

Timer Registers

1: Enable pull-down resistors on both D+ and D–

There are three registers dedicated to timer operations. Each

of these registers are discussed in this section and are

summarized in T a ble 20.

0: Disable pull-down resistors on both D+ and D–

LS Pull-up Enable (Bit 5)

Table 20.Timer Registers

The LS Pull-up Enable bit enables or disables a low-speed

pull-up resistor (pull up on D–) for testing.

Watchdog Timer Register

Timer 0 Register

Address

0xC00C

0xC010

0xC012

R/W

1: Enable low-speed pull-up resistor on D–

0: Pull-up resistor is not connected on D–

Timer 1 Register

Document #: 38-08014 Rev. *G

Page 16 of 78

[+] Feedback

CY7C67200

Watchdog Timer Register [0xC00C] [R/W]

Figure 15. Watchdog Timer Register

Bit #

Field

Reserved...

Read/Write

Default

R/W

Bit #

...Reserved

Timeout

Flag

Period

Select

Lock

Enable

WDT

Enable

Reset

Strobe

Field

Read/Write

Default

R/W

Lock Enable (Bit 2)

The Watchdog Timer register provides status and control over

the Watchdog timer. The Watchdog timer can also interrupt the

processor.

The Lock Enable bit does not allow any writes to this register

until a reset. In doing so the Watchdog timer can be set up and

enabled permanently so that it can only be cleared on reset

(the WDT Enable bit is ignored).

Timeout Flag (Bit 5)

1: Watchdog timer permanently set

The Timeout Flag bit indicates if the Watchdog timer has

expired. The processor can read this bit after exiting a reset to

determine if a Watchdog timeout occurred. This bit is cleared

on the next external hardware reset.

0: Watchdog timer not permanently set

WDT Enable (Bit 1)

The WDT Enable bit enables or disables the Watchdog timer.

1: Enable Watchdog timer operation

0: Disable Watchdog timer operation

1: Watchdog timer expired

0: Watchdog timer did not expire

Period Select (Bits [4:3])

Reset Strobe (Bit 0)

The Period Select field is defined in T a ble 21. If this time

expires before the Reset Strobe bit is set, the internal

processor is reset.

The Reset Strobe is a write-only bit that resets the Watchdog

timer count. It must be set to ‘1’ before the count expires to

avoid a Watchdog trigger

Table 21.Period Select Definition

1: Reset Count

Period Select[4:3]

WDT Period Value

1.4 ms

Reserved

All reserved bits must be written as ‘0’.

5.5 ms

22.0 ms

66.0 ms

Document #: 38-08014 Rev. *G

Page 17 of 78

[+] Feedback

CY7C67200

Timer n Register [R/W]

• Timer 0 Register 0xC010

• Timer 1 Register 0xC012

Figure 16. Timer n Register

Bit #

Field

Count...

Read/Write

Default

R/W

Bit #

Field

...Count

Read/Write

Default

R/W

The Timer n Register sets the Timer n count. Both Timer 0 and Timer 1 decrement by one every 1-µs clock tick. Each can provide

an interrupt to the CPU when the timer reaches zero.

Count (Bits [15:0])

The Count field sets the Timer count.

General USB Registers

There is one set of registers dedicated to general USB control. This set consists of two identical registers, one for Host/Device

Port 1 and one for Host/Device Port 2. This register set has functions for both USB host and USB peripheral options and is covered

in this section and summarized in T a ble 22. USB Host-only registers are covered in Section “USB Host Only Registers” on page

19 and USB Device-only registers are covered in Section “USB Device Only Registers” on page 28.

Table 22.USB Registers

Address (SIE1/SIE2)

R/W

USB n Control Register

0xC08A/0xC0AA

R/W

USB n Control Register [R/W]

• USB 1 Control Register 0xC08A

• USB 2 Control Register 0xC0AA

Figure 17. USB n Control Register

Bit #

Reserved

Port A

D+ Status

Port A

D– Status

Reserved

LOA

Mode

Select

Reserved

Field

Read/Write

Default

R/W

Bit #

Port A

Resistors Enable

Reserved

Port A

Force D± State

Suspend

Enable

Reserved

Port A

SOF/EOP Enable

Field

Read/Write

Default

R/W

The USB n Control register is used in both host and device mode. It monitors and controls the SIE and the data lines of the USB

ports. This register can be accessed by the HPI interface.

Document #: 38-08014 Rev. *G

Page 18 of 78

[+] Feedback

CY7C67200

Port A D+ Status (Bit 13)

Table 24.Port A Force D± State

Port A Force D± State

The Port A D+ Status bit is a read-only bit that indicates the

value of DATA+ on Port A.

Function

MSB

LSB

1: D+ is high

Normal Operation

0: D+ is low

Force USB Reset, SE0 State

Force J-State

Port A D– Status (Bit 12)

The Port A D– Status bit is a read-only bit that indicates the

value of DATA– on Port A.

Force K-State

Suspend Enable (Bit 2)

1: D– is high

The Suspend Enable bit enables or disables the suspend

feature on both ports. When suspend is enabled the USB

transceivers are powered down and can not transmit or

received USB packets but can still monitor for a wakeup

condition.

0: D– is low

LOA (Bit 10)

The LOA bit selects the speed of Port A.

1: Port A is set to Low-speed mode

0: Port A is set to Full-speed mode

1: Enable suspend

0: Disable suspend

Mode Select (Bit 9)

Port A SOF/EOP Enable (Bit 0)

The Mode Select bit sets the SIE for host or device operation.

When set for device operation only one USB port is supported.

The active port is selected by the Port Select bit in the Host n

Count Register.

The Port A SOF/EOP Enable bit is only applicable in host

mode. In Device mode this bit must be written as ‘0’. In host

mode this bit enables or disables SOFs or EOPs for Port A.

Either SOFs or EOPs will be generated depending on the LOA

bit in the USB n Control Register when Port A is active.

1: Host mode

0: Device mode

1: Enable SOFs or EOPs

0: Disable SOFs or EOPs

Port A Resistors Enable (Bit 7)

The Port A Resistors Enable bit enables or disables the

pull-up/pull-down resistors on Port A. When enabled, the

Mode Select bit and LOA bit of this register sets the

pull-up/pull-down resistors appropriately. When the Mode

Select is set for Host mode, the pull-down resistors on the data

lines (D+ and D–) are enabled. When the Mode Select is set

for Device mode, a single pull-up resistor on either D+ or D–,

determined by the LOA bit, will be enabled. See T a ble 23 for

details.

Reserved

All reserved bits must be written as ‘0’.

USB Host Only Registers

There are twelve sets of dedicated registers to USB host only

operation. Each set consists of two identical registers (unless

otherwise noted); one for Host Port 1 and one for Host Port 2.

These register sets are covered in this section and summa-

rized in T a ble 25.

1: Enable pull-up/pull-down resistors

Table 25.USB Host Only Register

Address

0: Disable pull-up/pull-down resistors

R/W

(Host 1/Host 2)

Table 23.USB Data Line Pull-up and Pull-down Resistors

Host n Control Register

0xC080/0xC0A0 R/W

0xC082/0xC0A2 R/W

0xC084/0xC0A4 R/W

Port n

Mode

L0A

Resistors

Enable

Function

Host n Address Register

Host n Count Register

Select

Pullup/PulldownonD+and

D– Disabled

Host n Endpoint Status Register

Host n PID Register

0xC086/0xC0A6

0xC088/0xC0A8

Pull down on D+ and D–

Enabled

Host n Count Result Register

Host n Device Address Register

Pull up on USB D– Enabled

Pull up on USB D+ Enabled

Host n Interrupt Enable Register 0xC08C/0xC0AC R/W

Host n Status Register 0xC090/0xC0B0 R/W

Host n SOF/EOP Count Register 0xC092/0xC0B2 R/W

Port A Force D± State (Bits [4:3])

The Port A Force D± State field controls the forcing state of the

D+ D– data lines for Port A. This field forces the state of the

Port A data lines independent of the Port Select bit setting. See

T a ble 24 for details.

Host n SOF/EOP Counter

0xC094/0xC0B4

Host n Frame Register

0xC096/0xC0B6

Document #: 38-08014 Rev. *G

Page 19 of 78

[+] Feedback

CY7C67200

Host n Control Register [R/W]

• Host 1 Control Register 0xC080

• Host 2 Control Register 0xC0A0

Figure 18. Host n Control Register

Bit #

Field

Reserved

Read/Write

Default

Bit #

Preamble

Enable

Sequence

Select

Sync

ISO

Reserved

Arm

Field

Enable

R/W

Enable

Read/Write

Default

R/W

1: The next enabled packet will be transferred after the SOF

or EOP packet is transmitted

The Host n Control register allows high-level USB transaction

control.

0: The next enabled packet will be transferred as soon as the

SIE is free

Preamble Enable (Bit 7)

ISO Enable (Bit 4)

The Preamble Enable bit enables or disables the transmission

of a preamble packet before all low-speed packets. This bit

should only be set when communicating with a low-speed

device.

The ISO Enable bit enables or disables an Isochronous trans-

action.

1: Enable Isochronous transaction

1: Enable Preamble packet

0: Disable Isochronous transaction

0: Disable Preamble packet

Arm Enable (Bit 0)

Sequence Select (Bit 6)

The Arm Enable bit arms an endpoint and starts a transaction.

This bit is automatically cleared to ‘0’ when a transaction is

complete.

The Sequence Select bit sets the data toggle for the next

packet. This bit has no effect on receiving data packets;

sequence checking must be handled in firmware.

1: Arm endpoint and begin transaction

1: Send DATA1

0: Endpoint disarmed

0: Send DATA0

Reserved

Sync Enable (Bit 5)

All reserved bits must be written as ‘0’.

The Sync Enable bit synchronizes the transfer with the SOF

packet in full-speed mode and the EOP packet in low-speed

mode.

Document #: 38-08014 Rev. *G

Page 20 of 78

[+] Feedback

CY7C67200

Host n Address Register [R/W]

• Host 1 Address Register 0xC082

• Host 2 Address Register 0xC0A2

Figure 19. Host n Address Register

Bit #

Field

Address...

Read/Write

Default

R/W

Bit #

Field

...Address

Read/Write

Default

R/W

Address (Bits [15:0])

The Host n Address register is used as the base pointer into

memory space for the current host transactions.

The Address field sets the address pointer into internal RAM

or ROM.

Host n Count Register [R/W]

• Host 1 Count Register 0xC084

• Host 2 Count Register 0xC0A4

Figure 20. Host n Count Register

Bit #

Field

Reserved

Count...

Read/Write

Default

R/W

Bit #

Field

...Count

Read/Write

Default

R/W

Count (Bits [9:0])

The Host n Count register is used to hold the number of bytes

(packet length) for the current transaction. The maximum

packet length is 1023 bytes in ISO mode. The Host Count

value is used to determine how many bytes to transmit, or the

maximum number of bytes to receive. If the number of

received bytes is greater then the Host Count value then an

overflow condition will be flagged by the Overflow bit in the

Host n Endpoint Status register.

The Count field sets the value for the current transaction data

packet length. This value is retained when switching between

host and device mode, and back again.

Reserved

All reserved bits must be written as ‘0’.

Document #: 38-08014 Rev. *G

Page 21 of 78

[+] Feedback

CY7C67200

Host n Endpoint Status Register [R]

• Host 1 Endpoint Status Register 0xC086

• Host 2 Endpoint Status Register 0xC0A6

Figure 21. Host n Endpoint Status Register

Bit #

Reserved

Overflow

Flag

Underflow

Flag

Reserved

Field

Read/Write

Default

Bit #

Stall

Flag

NAK

Flag

Length

Exception

Flag

Reserved

Sequence

Status

Timeout

Flag

Error

Flag

ACK

Flag

Field

Read/Write

Default

Length Exception Flag (Bit 5)

The Host n Endpoint Status register is a read-only register that

provides status for the last USB transaction.

The Length Exception Flag bit indicates the received data in

the data stage of the last transaction does not equal the

maximum Host Count specified in the Host n Count register. A

Length Exception can either mean an overflow or underflow

and the Overflow and Underflow flags (bits 11 and 10, respec-

tively) should be checked to determine which event occurred.

Overflow Flag (Bit 11)

The Overflow Flag bit indicates that the received data in the

last data transaction exceeded the maximum length specified

in the Host n Count Register. The Overflow Flag should be

checked in response to a Length Exception signified by the

Length Exception Flag set to ‘1’.

1: An overflow or underflow condition occurred

0: An overflow or underflow condition did not occur

1: Overflow condition occurred

Sequence Status (Bit 3)

0: Overflow condition did not occur

The Sequence Status bit indicates the state of the last received

data toggle from the device. Firmware is responsible for

monitoring and handling the sequence status. The Sequence

bit is only valid if the ACK bit is set to ‘1’. The Sequence bit is

set to ‘0’ when an error is detected in the transaction and the

Error bit will be set.

Underflow Flag (Bit 10)

The Underflow Flag bit indicates that the received data in the

last data transaction was less then the maximum length

specified in the Host n Count register. The Underflow Flag

should be checked in response to a Length Exception signified

by the Length Exception Flag set to ‘1’.

1: DATA1

0: DATA0

1: Underflow condition occurred

Timeout Flag (Bit 2)

0: Underflow condition did not occur

The Timeout Flag bit indicates if a timeout condition occurred

for the last transaction. A timeout condition can occur when a

device either takes too long to respond to a USB host request

or takes too long to respond with a handshake.

Stall Flag (Bit 7)

The Stall Flag bit indicates that the peripheral device replied

with a Stall in the last transaction.

1: Timeout occurred

1: Device returned Stall

0: Timeout did not occur

0: Device did not return Stall

Error Flag (Bit 1)

NAK Flag (Bit 6)

The Error Flag bit indicates a transaction failed for any reason

other than the following: Timeout, receiving a NAK, or

The NAK Flag bit indicates that the peripheral device replied

with a NAK in the last transaction.

receiving

STALL. Overflow and Underflow are not

1: Device returned NAK

considered errors and do not affect this bit. CRC5 and CRC16

errors will result in an Error flag along with receiving incorrect

packet types.

0: Device did not return NAK

1: Error detected

0: No error detected

Document #: 38-08014 Rev. *G

Page 22 of 78

[+] Feedback

CY7C67200

ACK Flag (Bit 0)

1: For non-Isochronous transfers, the transaction was ACKed.

For Isochronous transfers, the transaction was completed

successfully.

The ACK Flag bit indicates two different conditions depending

on the transfer type. For non-Isochronous transfers, this bit

represents a transaction ending by receiving or sending an

ACK packet. For Isochronous transfers, this bit represents a

successful transaction that will not be represented by an ACK

packet.

0: For non-Isochronous transfers, the transaction was not

ACKed. For Isochronous transfers, the transaction was not

completed successfully.

Host n PID Register [W]

• Host 1 PID Register 0xC086

• Host 2 PID Register 0xC0A6

Figure 22. Host n PID Register

Bit #

Field

Reserved

Read/Write

Default

Bit #

Field

PID Select

Endpoint Select

Read/Write

Default

Table 26.PID Select Definition (continued)

PID TYPE PID Select [7:4]

PREAMBLE

The Host n PID register is a write-only register that provides

the PID and Endpoint information to the USB SIE to be used

in the next transaction.

1100 (C Hex)

1010 (A Hex)

1110 (E Hex)

0011 (3 Hex)

1011 (B Hex)

NAK

PID Select (Bits [7:4])

STALL

DATA0

DATA1

The PID Select field defined as in T a ble 26. ACK and NAK

tokens are automatically sent based on settings in the Host n

Control register and do not need to be written in this register.

Table 26.PID Select Definition

Endpoint Select (Bits [3:0])

PID TYPE

PID Select [7:4]

1101 (D Hex)

1001 (9 Hex)

0001 (1 Hex)

0101 (5 Hex)

The Endpoint field allows addressing of up to 16 different

endpoints.

set-up

Reserved

OUT

SOF

All reserved bits must be written as ‘0’.

Document #: 38-08014 Rev. *G

Page 23 of 78

[+] Feedback

CY7C67200

Host n Count Result Register [R]

• Host 1 Count Result Register 0xC088

• Host 2 Count Result Register 0xC0A8

Figure 23. Host n Count Result Register

Bit #

Field

Result...

Read/Write

Default

Bit #

Field

...Result

Read/Write

Default

Result (Bits [15:0])

The Host n Count Result register is a read-only register that

contains the size difference in bytes between the Host Count

Value specified in the Host n Count register and the last packet

received. If an overflow or underflow condition occurs, that is

the received packet length differs from the value specified in

the Host n Count register, the Length Exception Flag bit in the

Host n Endpoint Status register will be set. The value in this

and the Error Flag bit is not set; both bits are in the Host n

Endpoint Status register.

The Result field contains the differences in bytes between the

received packet and the value specified in the Host n Count

to ‘111111’, a 2’s complement value indicating the additional

byte count of the received packet. If an underflow condition

occurs, Result [15:0] indicates the excess byte count (number

of bytes not used).

Reserved

All reserved bits must be written as ‘0’.

Host n Device Address Register [W]

• Host 1 Device Address Register 0xC088

• Host 2 Device Address Register 0xC0A8

Figure 24. Host n Device Address Register

Bit #

Field

Reserved...

Read/Write

Default

Bit #

Field

...Reserved

Address

Read/Write

Default

Address (Bits [6:0])

The Host n Device Address register is a write-only register that

contains the USB Device Address that the host wishes to

communicate with.

The Address field contains the value of the USB address for

the next device that the host is going to communicate with.

This value must be written by firmware.

Reserved

All reserved bits must be written as ‘0’.

Document #: 38-08014 Rev. *G

Page 24 of 78

[+] Feedback

CY7C67200

Host n Interrupt Enable Register [R/W]

• Host 1 Interrupt Enable Register 0xC08C

• Host 2 Interrupt Enable Register 0xC0AC

Figure 25. Host n Interrupt Enable Register

Bit #

VBUS

Interrupt Enable

ID Interrupt

Enable

Reserved

SOF/EOP

Interrupt Enable

Reserved

Field

Read/Write

Default

R/W

Bit #

Reserved

Port A

Wake Interrupt Enable

Reserved

Port A Connect

Change

Interrupt Enable

Reserved

Done

Interrupt Enable

Field

Read/Write

Default

R/W

Port A Wake Interrupt Enable (Bit 6)

The Host n Interrupt Enable register allows control over

host-related interrupts.

The Port A Wake Interrupt Enable bit enables or disables the

remote wakeup interrupt for Port A.

In this register a bit set to ‘1’ enables the corresponding

interrupt while ‘0’ disables the interrupt.

1: Enable remote wakeup interrupt for Port A

0: Disable remote wakeup interrupt for Port A

VBUS Interrupt Enable (Bit 15)

Port A Connect Change Interrupt Enable (Bit 4)

The VBUS Interrupt Enable bit enables or disables the OTG

VBUS interrupt. When enabled this interrupt triggers on both

the rising and falling edge of VBUS at the 4.4V status (only

supported in Port 1A). This bit is only available for Host 1 and

is a reserved bit in Host 2.

The Port A Connect Change Interrupt Enable bit enables or

disables the Connect Change interrupt on Port A. This

interrupt triggers when either a device is inserted (SE0 state

to J state) or a device is removed (J state to SE0 state).

1: Enable Connect Change interrupt

1: Enable VBUS interrupt

0: Disable Connect Change interrupt

0: Disable VBUS interrupt

Done Interrupt Enable (Bit 0)

ID Interrupt Enable (Bit 14)

The Done Interrupt Enable bit enables or disables the USB

Transfer Done interrupt. The USB Transfer Done triggers

when either the host responds with an ACK, or a device

responds with any of the following: ACK, NAK, STALL, or

Timeout. This interrupt is used for both Port A and Port B.

The ID Interrupt Enable bit enables or disables the OTG ID

interrupt. When enabled this interrupt triggers on both the

rising and falling edge of the OTG ID pin (only supported in

Port 1A). This bit is only available for Host 1 and is a reserved

bit in Host 2.

1: Enable USB Transfer Done interrupt

1: Enable ID interrupt

0: Disable USB Transfer Done interrupt

0: Disable ID interrupt

Reserved

SOF/EOP Interrupt Enable (Bit 9)

All reserved bits must be written as ‘0’.

The SOF/EOP Interrupt Enable bit enables or disables the

SOF/EOP timer interrupt.

1: Enable SOF/EOP timer interrupt

0: Disable SOF/EOP timer interrupt

Document #: 38-08014 Rev. *G

Page 25 of 78

[+] Feedback

CY7C67200

Host n Status Register [R/W]

• Host 1 Status Register 0xC090

• Host 2 Status Register 0xC0B0

Figure 26. Host n Status Register

Bit #

VBUS

Interrupt Flag

ID Interrupt

Flag

Reserved

SOF/EOP

Interrupt Flag

Reserved

Field

Read/Write

Default

R/W

Bit #

Reserved

Port A

Wake Interrupt

Flag

Reserved

Port A Connect

Change

Interrupt Flag

Reserved

Port A

SE0

Status

Reserved

Done

Interrupt Flag

Field

Read/Write

Default

R/W

Port A Wake Interrupt Flag (Bit 6)

The Host n Status register provides status information for host

operation. Pending interrupts can be cleared by writing a ‘1’ to

the corresponding bit. This register can be accessed by the

HPI interface.

The Port A Wake Interrupt Flag bit indicates remote wakeup

on Port A.

1: Interrupt triggered

0: Interrupt did not trigger

VBUS Interrupt Flag (Bit 15)

Port A Connect Change Interrupt Flag (Bit 4)

The VBUS Interrupt Flag bit indicates the status of the OTG

VBUS interrupt (only for Port 1A). When enabled this interrupt

triggers on both the rising and falling edge of VBUS at 4.4V.

This bit is only available for Host 1 and is a reserved bit in

Host 2.

The Port A Connect Change Interrupt Flag bit indicates the

status of the Connect Change interrupt on Port A. This bit

triggers ‘1’ on either a rising edge or falling edge of a USB

Reset condition (device inserted or removed). Together with

the Port A SE0 Status bit, it can be determined whether a

device was inserted or removed.

1: Interrupt triggered

0: Interrupt did not trigger

1: Interrupt triggered

ID Interrupt Flag (Bit 14)

0: Interrupt did not trigger

The ID Interrupt Flag bit indicates the status of the OTG ID

interrupt (only for Port 1A). When enabled this interrupt

triggers on both the rising and falling edge of the OTG ID pin.

This bit is only available for Host 1 and is a reserved bit in

Host 2.

Port A SE0 Status (Bit 2)

The Port A SE0 Status bit indicates if Port A is in an SE0 state

or not. Together with the Port A Connect change Interrupt Flag

bit, it can be determined whether a device was inserted

(non-SE0 condition) or removed (SE0 condition).

1: Interrupt triggered

1: SE0 condition

0: Interrupt did not trigger

0: Non-SE0 condition

SOF/EOP Interrupt Flag (Bit 9)

Done Interrupt Flag (Bit 0)

The SOF/EOP Interrupt Flag bit indicates the status of the

SOF/EOP Timer interrupt. This bit triggers ‘1’ when the

SOF/EOP timer expires.

The Done Interrupt Flag bit indicates the status of the USB

Transfer Done interrupt. The USB Transfer Done triggers

when either the host responds with an ACK, or a device

responds with any of the following: ACK, NAK, STALL, or

Timeout. This interrupt is used for both Port A and Port B.

1: Interrupt triggered

0: Interrupt did not trigger

1: Interrupt triggered

0: Interrupt did not trigger

Document #: 38-08014 Rev. *G

Page 26 of 78

[+] Feedback

CY7C67200

Host n SOF/EOP Count Register [R/W]

• Host 1 SOF/EOP Count Register 0xC092

• Host 2 SOF/EOP Count Register 0xC0B2

Figure 27. Host n SOF/EOP Count Register

Bit #

Field

Reserved

Count...

Read/Write

Default

R/W

Bit #

Field

...Count

Read/Write

Default

R/W

Count (Bits [13:0])

The Host n SOF/EOP Count register contains the SOF/EOP

Count Value that is loaded into the SOF/EOP counter. This

value is loaded each time the SOF/EOP counter counts down

to zero. The default value set in this register at power-up is

0x2EE0, which will generate a 1-ms time frame. The

SOF/EOP counter is a down counter decremented at a

12-MHz rate. When this register is read, the value returned is

the programmed SOF/EOP count value.

The Count field sets the SOF/EOP counter duration.

Reserved

All reserved bits must be written as ‘0’.

Host n SOF/EOP Counter Register [R]

• Host 1 SOF/EOP Counter Register 0xC094

• Host 2 SOF/EOP Counter Register 0xC0B4

Figure 28. Host n SOF/EOP Counter Register

Bit #

Field

Reserved

Counter...

Read/Write

Default

Bit #

Field

...Counter

Read/Write

Default

Counter (Bits [13:0])

The Host n SOF/EOP Counter register contains the current

value of the SOF/EOP down counter. This value can be used

to determine the time remaining in the current frame.

The Counter field contains the current value of the SOF/EOP

down counter.

Document #: 38-08014 Rev. *G

Page 27 of 78

[+] Feedback

CY7C67200

Host n Frame Register [R]

• Host 1 Frame Register 0xC096

• Host 2 Frame Register 0xC0B6

Figure 29. Host n Frame Register

Bit #

Field

Reserved

Frame...

Read/Write

Default

Bit #

Field

...Frame

Read/Write

Default

Reserved

The Host n Frame register maintains the next frame number

to be transmitted (current frame number + 1). This value is

updated after each SOF transmission. This register resets to

0x0000 after each CPU write to the Host n SOF/EOP Count

All reserved bits must be written as ‘0’.

USB Device Only Registers

There are ten sets of USB Device Only registers. All sets

consist of at least two registers, one for Device Port 1 and one

for Device Port 2. In addition, each Device port has eight

possible endpoints. This gives each endpoint register set eight

registers for each Device Port for a total of 16 registers per set.

The USB Device Only registers are covered in this section and

summarized in T a ble 27.

Frame (Bits [10:0])

The Frame field contains the next frame number to be trans-

mitted.

Table 27.USB Device Only Registers

Address

R/W

(Device 1/Device 2)

Device n Endpoint n Control Register

Device n Endpoint n Address Register

Device n Endpoint n Count Register

Device n Endpoint n Status Register

Device n Endpoint n Count Result Register

Device n Interrupt Enable Register

Device n Address Register

0x02n0

R/W

0x02n2

0x02n4

0x02n6

0x02n8

0xC08C/0xC0AC

0xC08E/0xC0AE

0xC090/0xCB0

0xC092/0xC0B2

0xC094/0xC0B4

Device n Status Register

Device n Frame Number Register

Device n SOF/EOP Count Register

Device n Endpoint n Control Register [R/W]

• Device n Endpoint 0 Control Register [Device 1: 0x0200 Device 2: 0x0280]

• Device n Endpoint 1 Control Register [Device 1: 0x0210 Device 2: 0x0290]

• Device n Endpoint 2 Control Register [Device 1: 0x0220 Device 2: 0x02A0]

• Device n Endpoint 3 Control Register [Device 1: 0x0230 Device 2: 0x02B0]

• Device n Endpoint 4 Control Register [Device 1: 0x0240 Device 2: 0x02C0]

• Device n Endpoint 5 Control Register [Device 1: 0x0250 Device 2: 0x02D0]

• Device n Endpoint 6 Control Register [Device 1: 0x0260 Device 2: 0x02E0]

• Device n Endpoint 7 Control Register [Device 1: 0x0270 Device 2: 0x02F0]

Document #: 38-08014 Rev. *G

Page 28 of 78

[+] Feedback

CY7C67200

Figure 30. Device n Endpoint n Control Register

Bit #

Field

Reserved

Read/Write

Default

Bit #

IN/OUT

Ignore

Enable

Sequence

Select

Stall

Enable

ISO

Enable

NAK

Interrupt

Enable

Direction

Select

Enable

Arm

Enable

Field

Read/Write

Default

R/W

NAK Interrupt Enable (Bit 3)

The Device n Endpoint n Control register provides control over

a single EP in device mode. There are a total of eight

endpoints for each of the two ports. All endpoints have the

same definition for their Device n Endpoint n Control register.

The NAK Interrupt Enable bit enables and disables the gener-

ation of an Endpoint n interrupt when the device responds to

the host with a NAK. The Endpoint n Interrupt Enable bit in the

Device n Interrupt Enable register must also be set. When a

NAK is sent to the host, the corresponding EP Interrupt Flag

in the Device n Status register will be set. In addition, the NAK

Flag in the Device n Endpoint n Status register will be set.

IN/OUT Ignore Enable (Bit 6)

The IN/OUT Ignore Enable bit forces endpoint 0 (EP0) to

ignore all IN and OUT requests. This bit must be set so that

EP0 only excepts Setup packets at the start of each transfer.

This bit must be cleared to except IN/OUT transactions. This

bit only applies to EP0.

1: Enable NAK interrupt

0: Disable NAK interrupt

Direction Select (Bit 2)

1: Ignore IN/OUT requests

The Direction Select bit needs to be set according to the

expected direction of the next data stage in the next trans-

action. If the data stage direction is different from what is set

in this bit, it will get NAKed and either the IN Exception Flag or

the OUT Exception Flag will be set in the Device n Endpoint n

Status register. If a setup packet is received and the Direction

Select bit is set incorrectly, the setup will be ACKed and the

Set-up Status Flag will be set (refer to the setup bit of the

Device n Endpoint n Status register for details).

0: Do not ignore IN/OUT requests

Sequence Select (Bit 6)

The Sequence Select bit determines whether a DATA0 or a

DATA1 will be sent for the next data toggle. This bit has no

effect on receiving data packets, sequence checking must be

handled in firmware.

1: Send a DATA1

1: OUT transfer (host to device)

0: Send a DATA0

0: IN transfer (device to host)

Stall Enable (Bit 5)

Enable (Bit 1)

The Stall Enable bit sends a Stall in response to the next

request (unless it is a setup request, which are always

ACKed). This is a sticky bit and continues to respond with

Stalls until cleared by firmware.

The Enable bit must be set to allow transfers to the endpoint.

If Enable is set to ‘0’ then all USB traffic to this endpoint is

ignored. If Enable is set ‘1’ and Arm Enable (bit 0) is set ‘0’ then

NAKs will automatically be returned from this endpoint (except

setup packets, which are always ACKed as long as the Enable

bit is set).

1: Send Stall

0: Do not send Stall

1: Enable transfers to an endpoint

ISO Enable (Bit 4)

0: Do not allow transfers to an endpoint

The ISO Enable bit enables and disables an Isochronous

transaction. This bit is only valid for EPs 1–7 and has no

function for EP0.

Arm Enable (Bit 0)

The Arm Enable bit arms the endpoint to transfer or receive a

packet. This bit is cleared to ‘0’ when a transaction is complete.

1: Enable Isochronous transaction

0: Disable Isochronous transaction

1: Arm endpoint

0: Endpoint disarmed

Reserved

All reserved bits must be written as ‘0’.

Document #: 38-08014 Rev. *G

Page 29 of 78

[+] Feedback

CY7C67200

Device n Endpoint n Address Register [R/W]

• Device n Endpoint 0 Address Register [Device 1: 0x0202 Device 2: 0x0282]

• Device n Endpoint 1 Address Register [Device 1: 0x0212 Device 2: 0x0292]

• Device n Endpoint 2 Address Register [Device 1: 0x0222 Device 2: 0x02A2]

• Device n Endpoint 3 Address Register [Device 1: 0x0232 Device 2: 0x02B2]

• Device n Endpoint 4 Address Register [Device 1: 0x0242 Device 2: 0x02C2]

• Device n Endpoint 5 Address Register [Device 1: 0x0252 Device 2: 0x02D2]

• Device n Endpoint 6 Address Register [Device 1: 0x0262 Device 2: 0x02E2]

• Device n Endpoint 7 Address Register [Device 1: 0x0272 Device 2: 0x02F2]

Figure 31. Device n Endpoint n Address Register

Bit #

Field

Address...

...Address

Read/Write

Default

R/W

Bit #

Field

Read/Write

Default

R/W

The Device n Endpoint n Address register is used as the base pointer into memory space for the current Endpoint transaction.

There are a total of eight endpoints for each of the two ports. All endpoints have the same definition for their Device n Endpoint

n Address register.

Address (Bits [15:0])

The Address field sets the base address for the current transaction on a signal endpoint.

Device n Endpoint n Count Register [R/W]

• Device n Endpoint 0 Count Register [Device 1: 0x0204 Device 2: 0x0284]

• Device n Endpoint 1 Count Register [Device 1: 0x0214 Device 2: 0x0294]

• Device n Endpoint 2 Count Register [Device 1: 0x0224 Device 2: 0x02A4]

• Device n Endpoint 3 Count Register [Device 1: 0x0234 Device 2: 0x02B4]

• Device n Endpoint 4 Count Register [Device 1: 0x0244 Device 2: 0x02C4]

• Device n Endpoint 5 Count Register [Device 1: 0x0254 Device 2: 0x02D4]

• Device n Endpoint 6 Count Register [Device 1: 0x0264 Device 2: 0x02E4]

• Device n Endpoint 7 Count Register [Device 1: 0x0274 Device 2: 0x02F4]

Figure 32. Device n Endpoint n Count Register

Bit #

Field

Reserved

Count...

Read/Write

Default

R/W

Bit #

Field

...Count

Read/Write

Default

R/W

Document #: 38-08014 Rev. *G

Page 30 of 78

[+] Feedback

CY7C67200

The Device n Endpoint n Count register designates the maximum packet size that can be received from the host for OUT transfers

for a single endpoint. This register also designates the packet size to be sent to the host in response to the next IN token for a

single endpoint. The maximum packet length is 1023 bytes in ISO mode. There are a total of eight endpoints for each of the two

ports. All endpoints have the same definition for their Device n Endpoint n Count register.

Count (Bits [9:0])

The Count field sets the current transaction packet length for a single endpoint.

Reserved

All reserved bits must be written as ‘0’.

Device n Endpoint n Status Register [R/W]

• Device n Endpoint 0 Status Register [Device 1: 0x0206 Device 2: 0x0286]

• Device n Endpoint 1 Status Register [Device 1: 0x0216 Device 2: 0x0296]

• Device n Endpoint 2 Status Register [Device 1: 0x0226 Device 2: 0x02A6]

• Device n Endpoint 3 Status Register [Device 1: 0x0236 Device 2: 0x02B6]

• Device n Endpoint 4 Status Register [Device 1: 0x0246 Device 2: 0x02C6]

• Device n Endpoint 5 Status Register [Device 1: 0x0256 Device 2: 0x02D6]

• Device n Endpoint 6 Status Register [Device 1: 0x0266 Device 2: 0x02E6]

• Device n Endpoint 7 Status Register [Device 1: 0x0276 Device 2: 0x02F6]

Figure 33. Device n Endpoint n Status Register

Bit #

Reserved

Overflow

Flag

Underflow

Flag

OUT

Field

Exception Flag Exception Flag

Read/Write

Default

R/W

Bit #

Stall

Flag

NAK

Flag

Length

Exception Flag

Setup

Flag

Sequence

Flag

Timeout

Flag

Error

Flag

ACK

Flag

Field

Read/Write

Default

R/W

Underflow Flag (Bit 10)

The Device n Endpoint n Status register provides packet status

information for the last transaction received or transmitted.

This register is updated in hardware and does not need to be

cleared by firmware. There are a total of eight endpoints for

each of the two ports. All endpoints have the same definition

for their Device n Endpoint n Status register.

The Underflow Flag bit indicates that the received data in the

last data transaction was less then the maximum length

specified in the Device n Endpoint n Count register. The

Underflow Flag should be checked in response to a Length

Exception signified by the Length Exception Flag set to ‘1’.

1: Underflow condition occurred

The Device n Endpoint n Status register is a memory-based

operations are initiated. After initialization, this register must

not be written to again.

0: Underflow condition did not occur

OUT Exception Flag (Bit 9)

The OUT Exception Flag bit indicates when the device

received an OUT packet when armed for an IN.

Overflow Flag (Bit 11)

1: Received OUT when armed for IN

The Overflow Flag bit indicates that the received data in the

last data transaction exceeded the maximum length specified

in the Device n Endpoint n Count register. The Overflow Flag

should be checked in response to a Length Exception signified

by the Length Exception Flag set to ‘1’.

0: Received IN when armed for IN

1: Overflow condition occurred

0: Overflow condition did not occur

Document #: 38-08014 Rev. *G

Page 31 of 78

[+] Feedback

CY7C67200

IN Exception Flag (Bit 8)

1: Setup packet was received

The IN Exception Flag bit indicates when the device received

an IN packet when armed for an OUT.

0: Setup packet was not received

Sequence Flag (Bit 3)

1: Received IN when armed for OUT

The Sequence Flag bit indicates whether the last data toggle

received was a DATA1 or a DATA0. This bit has no effect on

receiving data packets; sequence checking must be handled

in firmware.

0: Received OUT when armed for OUT

Stall Flag (Bit 7)

The Stall Flag bit indicates that a Stall packet was sent to the

host.

1: DATA1 was received

0: DATA0 was received

1: Stall packet was sent to the host

0: Stall packet was not sent

Timeout Flag (Bit 2)

The Timeout Flag bit indicates whether a timeout condition

occurred on the last transaction. On the device side, a timeout

can occur if the device sends a data packet in response to an

IN request but then does not receive a handshake packet in a

predetermined time. It can also occur if the device does not

receive the data stage of an OUT transfer in time.

NAK Flag (Bit 6)

The NAK Flag bit indicates that a NAK packet was sent to the

host.

1: NAK packet was sent to the host

0: NAK packet was not sent

1: Timeout occurred

Length Exception Flag (Bit 5)

0: Timeout condition did not occur

The Length Exception Flag bit indicates the received data in

the data stage of the last transaction does not equal the

maximum Endpoint Count specified in the Device n Endpoint

n Count register. A Length Exception can either mean an

overflow or underflow and the Overflow and Underflow flags

(bits 11 and 10, respectively) should be checked to determine

which event occurred.

Error Flag (Bit 2)

The Error Flag bit is set if a CRC5 and CRC16 error occurs, or

if an incorrect packet type is received. Overflow and Underflow

are not considered errors and do not affect this bit.

1: Error occurred

0: Error did not occur

1: An overflow or underflow condition occurred

0: An overflow or underflow condition did not occur

ACK Flag (Bit 0)

The ACK Flag bit indicates whether the last transaction was

ACKed.

Setup Flag (Bit 4)

The Setup Flag bit indicates that a setup packet was received.

In device mode setup packets are stored at memory location

0x0300 for Device 1 and 0x0308 for Device 2. Setup packets

are always accepted regardless of the Direction Select and

Arm Enable bit settings as long as the Device n EP n Control

1: ACK occurred

0: ACK did not occur

Document #: 38-08014 Rev. *G

Page 32 of 78

[+] Feedback

CY7C67200

Device n Endpoint n Count Result Register [R/W]

• Device n Endpoint 0 Count Result Register [Device 1: 0x0208 Device 2: 0x0288]

• Device n Endpoint 1 Count Result Register [Device 1: 0x0218 Device 2: 0x0298]

• Device n Endpoint 2 Count Result Register [Device 1: 0x0228 Device 2: 0x02A8]

• Device n Endpoint 3 Count Result Register [Device 1: 0x0238 Device 2: 0x02B8]

• Device n Endpoint 4 Count Result Register [Device 1: 0x0248 Device 2: 0x02C8]

• Device n Endpoint 5 Count Result Register [Device 1: 0x0258 Device 2: 0x02D8]

• Device n Endpoint 6 Count Result Register [Device 1: 0x0268 Device 2: 0x02E8]

• Device n Endpoint 7 Count Result Register [Device 1: 0x0278 Device 2: 0x02F8]

Figure 34. Device n Endpoint n Count Result Register

Bit #

Field

Result...

...Result

Read/Write

Default

R/W

Bit #

Field

Read/Write

Default

R/W

Result (Bits [15:0])

The Device n Endpoint n Count Result register contains the

size difference in bytes between the Endpoint Count specified

in the Device n Endpoint n Count register and the last packet

received. If an overflow or underflow condition occurs, that is

the received packet length differs from the value specified in

the Device n Endpoint n Count register, the Length Exception

Flag bit in the Device n Endpoint n Status register will be set.

The value in this register is only considered when the Length

Exception Flag bit is set and the Error Flag bit is not set; both

bits are in the Device n Endpoint n Status register.

The Result field contains the differences in bytes between the

received packet and the value specified in the Device n

Endpoint n Count register. If an overflow condition occurs,

Result [15:10] is set to ‘111111’, a 2’s complement value

indicating the additional byte count of the received packet. If

an underflow condition occurs, Result [15:0] indicates the

excess byte count (number of bytes not used).

Reserved

All reserved bits must be written as ‘0’.

The Device n Endpoint n Count Result register is a memory

based register that must be initialized to 0x0000 before USB

Device operations are initiated. After initialization, this register

must not be written to again.

Document #: 38-08014 Rev. *G

Page 33 of 78

[+] Feedback

CY7C67200

Device n Interrupt Enable Register [R/W]

• Device 1 Interrupt Enable Register 0xC08C

• Device 2 Interrupt Enable Register 0xC0AC

Figure 35. Device n Interrupt Enable Register

Bit #

VBUS

Interrupt

Enable

ID Interrupt

Enable

Reserved

SOF/EOP

Timeout

Interrupt Enable

Reserved

SOF/EOP

Interrupt

Enable

Reset

Interrupt

Enable

Field

Read/Write

Default

R/W

Bit #

EP7 Interrupt EP6 Interrupt EP5 Interrupt EP4 Interrupt EP3 Interrupt EP2 Interrupt EP1 Interrupt EP0 Interrupt

Field

Enable

R/W

Enable

R/W

Enable

R/W

Enable

R/W

Enable

R/W

Enable

R/W

Enable

R/W

Enable

R/W

Read/Write

Default

SOF/EOP Interrupt Enable (Bit 9)

The Device n Interrupt Enable register provides control over

device-related interrupts including eight different endpoint

interrupts.

The SOF/EOP Interrupt Enable bit enables or disables the

SOF/EOP received interrupt.

1: Enable SOF/EOP Received interrupt

VBUS Interrupt Enable (Bit 15)

0: Disable SOF/EOP Received interrupt

The VBUS Interrupt Enable bit enables or disables the OTG

VBUS interrupt. When enabled this interrupt triggers on both

the rising and falling edge of VBUS at the 4.4V status (only

supported in Port 1A). This bit is only available for Device 1

and is a reserved bit in Device 2.

Reset Interrupt Enable (Bit 8)

The Reset Interrupt Enable bit enables or disables the USB

Reset Detected interrupt

1: Enable USB Reset Detected interrupt

1: Enable VBUS interrupt

0: Disable USB Reset Detected interrupt

0: Disable VBUS interrupt

EP7 Interrupt Enable (Bit 7)

ID Interrupt Enable (Bit 14)

The EP7 Interrupt Enable bit enables or disables an endpoint

seven (EP7) Transaction Done interrupt. An EPx Transaction

Done interrupt triggers when any of the following responses or

events occur in a transaction for the device’s given Endpoint:

send/receive ACK, send STALL, Timeout occurs, IN Exception

Error, or OUT Exception Error. In addition, the NAK Interrupt

Enable bit in the Device n Endpoint Control register can also

be set so that NAK responses triggers this interrupt.

The ID Interrupt Enable bit enables or disables the OTG ID

interrupt. When enabled this interrupt triggers on both the

rising and falling edge of the OTG ID pin (only supported in

Port 1A). This bit is only available for Device 1 and is a

reserved bit in Device 2.

1: Enable ID interrupt

0: Disable ID interrupt

1: Enable EP7 Transaction Done interrupt

SOF/EOP Timeout Interrupt Enable (Bit 11)

0: Disable EP7 Transaction Done interrupt

The SOF/EOP Timeout Interrupt Enable bit enables or

disables the SOF/EOP Timeout Interrupt. When enabled this

interrupt triggers when the USB host fails to send a SOF or

EOP packet within the time period specified in the Device n

SOF/EOP Count register. In addition, the Device n Frame

Interrupt triggers between receiving SOF/EOPs.

EP6 Interrupt Enable (Bit 6)

The EP6 Interrupt Enable bit enables or disables an endpoint

six (EP6) Transaction Done interrupt. An EPx Transaction

Done interrupt triggers when any of the following responses or

events occur in a transaction for the device’s given Endpoint:

send/receive ACK, send STALL, Timeout occurs, IN Exception

Error, or OUT Exception Error. In addition, the NAK Interrupt

Enable bit in the Device n Endpoint Control register can also

be set so that NAK responses triggers this interrupt.

1: SOF/EOP timeout occurred

0: SOF/EOP timeout did not occur

1: Enable EP6 Transaction Done interrupt

0: Disable EP6 Transaction Done interrupt

Document #: 38-08014 Rev. *G

Page 34 of 78

[+] Feedback

CY7C67200

EP5 Interrupt Enable (Bit 5)

EP2 Interrupt Enable (Bit 2)

The EP5 Interrupt Enable bit enables or disables an endpoint

five (EP5) Transaction Done interrupt. An EPx Transaction

Done interrupt triggers when any of the following responses or

events occur in a transaction for the device’s given Endpoint:

send/receive ACK, send STALL, Timeout occurs, IN Exception

Error, or OUT Exception Error. In addition, the NAK Interrupt

Enable bit in the Device n Endpoint Control register can also

be set so that NAK responses triggers this interrupt.

The EP2 Interrupt Enable bit enables or disables an endpoint

two (EP2) Transaction Done interrupt. An EPx Transaction

Done interrupt triggers when any of the following responses or

events occur in a transaction for the device’s given Endpoint:

send/receive ACK, send STALL, Timeout occurs, IN Exception

Error, or OUT Exception Error. In addition, the NAK Interrupt

Enable bit in the Device n Endpoint Control register can also

be set so that NAK responses triggers this interrupt.

1: Enable EP5 Transaction Done interrupt

1: Enable EP2 Transaction Done interrupt

0: Disable EP5 Transaction Done interrupt

0: Disable EP2 Transaction Done interrupt

EP4 Interrupt Enable (Bit 4)

EP1 Interrupt Enable (Bit 1)

The EP4 Interrupt Enable bit enables or disables an endpoint

four (EP4) Transaction Done interrupt. An EPx Transaction

Done interrupt triggers when any of the following responses or

events occur in a transaction for the device’s given Endpoint:

send/receive ACK, send STALL, Timeout occurs, IN Exception

Error, or OUT Exception Error. In addition, the NAK Interrupt

Enable bit in the Device n Endpoint Control register can also

be set so that NAK responses triggers this interrupt.

The EP1 Interrupt Enable bit enables or disables an endpoint

one (EP1) Transaction Done interrupt. An EPx Transaction

Done interrupt triggers when any of the following responses or

events occur in a transaction for the device’s given Endpoint:

send/receive ACK, send STALL, Timeout occurs, IN Exception

Error, or OUT Exception Error. In addition, the NAK Interrupt

Enable bit in the Device n Endpoint Control register can also

be set so that NAK responses triggers this interrupt.

1: Enable EP4 Transaction Done interrupt

1: Enable EP1 Transaction Done interrupt

0: Disable EP4 Transaction Done interrupt

0: Disable EP1 Transaction Done interrupt

EP3 Interrupt Enable (Bit 3)

EP0 Interrupt Enable (Bit 0)

The EP3 Interrupt Enable bit enables or disables an endpoint

three (EP3) Transaction Done interrupt. An EPx Transaction

Done interrupt triggers when any of the following responses or

events occur in a transaction for the device’s given Endpoint:

send/receive ACK, send STALL, Timeout occurs, IN Exception

Error, or OUT Exception Error. In addition, the NAK Interrupt

Enable bit in the Device n Endpoint Control register can also

be set so that NAK responses triggers this interrupt.

The EP0 Interrupt Enable bit enables or disables an endpoint

zero (EP0) Transaction Done interrupt. An EPx Transaction

Done interrupt triggers when any of the following responses or

events occur in a transaction for the device’s given Endpoint:

send/receive ACK, send STALL, Timeout occurs, IN Exception

Error, or OUT Exception Error. In addition, the NAK Interrupt

Enable bit in the Device n Endpoint Control register can also

be set so that NAK responses triggers this interrupt.

1: Enable EP3 Transaction Done interrupt

1: Enable EP0 Transaction Done interrupt

0: Disable EP3 Transaction Done interrupt

0: Disable EP0 Transaction Done interrupt

Reserved

All reserved bits must be written as ‘0’.

Document #: 38-08014 Rev. *G

Page 35 of 78

[+] Feedback

CY7C67200

Device n Address Register [W]

• Device 1 Address Register 0xC08E

• Device 2 Address Register 0xC0AE

Figure 36. Device n Address Register

Bit #

Field

Reserved...

Read/Write

Default

Bit #

Field

...Reserved

Address

Read/Write

Default

The Device n Address register holds the device address assigned by the host. This register initializes to the default address 0 at

reset but must be updated by firmware when the host assigns a new address. Only USB data sent to the address contained in

this register will be responded to, all others are ignored.

Address (Bits [6:0])

The Address field contains the USB address of the device assigned by the host.

Reserved

All reserved bits must be written as ‘0’.

Device n Status Register [R/W]

• Device 1 Status Register 0xC090

• Device 2 Status Register 0xC0B0

Figure 37. Device n Status Register

Bit #

VBUS

Interrupt Flag

ID Interrupt

Flag

Reserved

SOF/EOP

Reset

Field

Interrupt Flag Interrupt Flag

Read/Write

Default

R/W

Bit #

EP7 Interrupt EP6 Interrupt EP5 Interrupt EP4 Interrupt EP3 Interrupt EP2 Interrupt EP1 Interrupt EP0 Interrupt

Field

Flag

R/W

Flag

R/W

Flag

R/W

Flag

R/W

Flag

R/W

Flag

R/W

Flag

R/W

Flag

R/W

Read/Write

Default

ID Interrupt Flag (Bit 14)

The Device n Status register provides status information for

device operation. Pending interrupts can be cleared by writing

a ‘1’ to the corresponding bit. This register can be accessed

by the HPI interface.

The ID Interrupt Flag bit indicates the status of the OTG ID

interrupt (only for Port 1A). When enabled this interrupt

triggers on both the rising and falling edge of the OTG ID pin.

This bit is only available for Device 1 and is a reserved bit in

Device 2.

VBUS Interrupt Flag (Bit 15)

1: Interrupt triggered

The VBUS Interrupt Flag bit indicates the status of the OTG

VBUS interrupt (only for Port 1A). When enabled this interrupt

triggers on both the rising and falling edge of VBUS at 4.4V.

This bit is only available for Device 1 and is a reserved bit in

Device 2.

0: Interrupt did not trigger

SOF/EOP Interrupt Flag (Bit 9)

The SOF/EOP Interrupt Flag bit indicates if the SOF/EOP

received interrupt has triggered.

1: Interrupt triggered

0: Interrupt did not trigger

Document #: 38-08014 Rev. *G

Page 36 of 78

[+] Feedback

CY7C67200

Reset Interrupt Flag (Bit 8)

0: Interrupt did not trigger

The Reset Interrupt Flag bit indicates if the USB Reset

Detected interrupt has triggered.

EP3 Interrupt Flag (Bit 3)

The EP3 Interrupt Flag bit indicates if the endpoint three (EP3)

Transaction Done interrupt has triggered. An EPx Transaction

Done interrupt triggers when any of the following responses or

events occur in a transaction for the device’s given EP:

send/receive ACK, send STALL, Timeout occurs, IN Exception

Error, or OUT Exception Error. In addition, if the NAK Interrupt

Enable bit in the Device n Endpoint Control register is set, this

interrupt also triggers when the device NAKs host requests.

1: Interrupt triggered

0: Interrupt did not trigger

EP7 Interrupt Flag (Bit 7)

The EP7 Interrupt Flag bit indicates if the endpoint seven

(EP7) Transaction Done interrupt has triggered. An EPx

Transaction Done interrupt triggers when any of the following

responses or events occur in a transaction for the device’s

given EP: send/receive ACK, send STALL, Timeout occurs, IN

Exception Error, or OUT Exception Error. In addition, if the

NAK Interrupt Enable bit in the Device n Endpoint Control

NAKs host requests.

1: Interrupt triggered

0: Interrupt did not trigger

EP2 Interrupt Flag (Bit 2)

The EP2 Interrupt Flag bit indicates if the endpoint two (EP2)

Transaction Done interrupt has triggered. An EPx Transaction

Done interrupt triggers when any of the following responses or

events occur in a transaction for the device’s given EP:

send/receive ACK, send STALL, Timeout occurs, IN Exception

Error, or OUT Exception Error. In addition, if the NAK Interrupt

Enable bit in the Device n Endpoint Control register is set, this

interrupt also triggers when the device NAKs host requests.

1: Interrupt triggered

0: Interrupt did not trigger

EP6 Interrupt Flag (Bit 6)

The EP6 Interrupt Flag bit indicates if the endpoint six (EP6)

Transaction Done interrupt has triggered. An EPx Transaction

Done interrupt triggers when any of the following responses or

events occur in a transaction for the device’s given EP:

send/receive ACK, send STALL, Timeout occurs, IN Exception

Error, or OUT Exception Error. In addition, if the NAK Interrupt

Enable bit in the Device n Endpoint Control register is set, this

interrupt also triggers when the device NAKs host requests.

1: Interrupt triggered

0: Interrupt did not trigger

EP1 Interrupt Flag (Bit 1)

The EP1 Interrupt Flag bit indicates if the endpoint one (EP1)

Transaction Done interrupt has triggered. An EPx Transaction

Done interrupt triggers when any of the following responses or

events occur in a transaction for the device’s given EP:

send/receive ACK, send STALL, Timeout occurs, IN Exception

Error, or OUT Exception Error. In addition, if the NAK Interrupt

Enable bit in the Device n Endpoint Control register is set, this

interrupt also triggers when the device NAKs host requests.

1: Interrupt triggered

0: Interrupt did not trigger

EP5 Interrupt Flag (Bit 5)

The EP5 Interrupt Flag bit indicates if the endpoint five (EP5)

Transaction Done interrupt has triggered. An EPx Transaction

Done interrupt triggers when any of the following responses or

events occur in a transaction for the device’s given EP:

send/receive ACK, send STALL, Timeout occurs, IN Exception

Error, or OUT Exception Error. In addition, if the NAK Interrupt

Enable bit in the Device n Endpoint Control register is set, this

interrupt also triggers when the device NAKs host requests.

1: Interrupt triggered

0: Interrupt did not trigger

EP0 Interrupt Flag (Bit 0)

The EP0 Interrupt Flag bit indicates if the endpoint zero (EP0)

Transaction Done interrupt has triggered. An EPx Transaction

Done interrupt triggers when any of the following responses or

events occur in a transaction for the device’s given EP:

send/receive ACK, send STALL, Timeout occurs, IN Exception

Error, or OUT Exception Error. In addition, if the NAK Interrupt

Enable bit in the Device n Endpoint Control register is set, this

interrupt also triggers when the device NAKs host requests.

1: Interrupt triggered

0: Interrupt did not trigger

EP4 Interrupt Flag (Bit 4)

The EP4 Interrupt Flag bit indicates if the endpoint four (EP4)

Transaction Done interrupt has triggered. An EPx Transaction

Done interrupt triggers when any of the following responses or

events occur in a transaction for the device’s given EP:

send/receive ACK, send STALL, Timeout occurs, IN Exception

Error, or OUT Exception Error. In addition, if the NAK Interrupt

Enable bit in the Device n Endpoint Control register is set, this

interrupt also triggers when the device NAKs host requests.

1: Interrupt triggered

0: Interrupt did not trigger

Reserved

All reserved bits must be written as ‘0’.

1: Interrupt triggered

Document #: 38-08014 Rev. *G

Page 37 of 78

[+] Feedback

CY7C67200

Device n Frame Number Register [R]

• Device 1 Frame Number Register 0xC092

• Device 2 Frame Number Register 0xC0B2

Figure 38. Device n Frame Number Register

Bit #

SOF/EOP

Timeout Flag

SOF/EOP

Timeout Interrupt Counter

Reserved

Frame...

Field

Read/Write

Default

Bit #

Field

...Frame

Read/Write

Default

SOF/EOP Timeout Interrupt Counter (Bits [14:12])

The Device n Frame Number register is a read only register

that contains the Frame number of the last SOF packet

received. This register also contains a count of SOF/EOP

Timeout occurrences.

The SOF/EOP Timeout Interrupt Counter field increments by

1 from 0 to 7 for each SOF/EOP Timeout Interrupt. This field

resets to 0 when a SOF/EOP is received. This field is only

updated when the SOF/EOP Timeout Interrupt Enable bit in

the Device n Interrupt Enable register is set.

SOF/EOP Timeout Flag (Bit 15)

Frame (Bits [10:0])

The SOF/EOP Timeout Flag bit indicates when an SOF/EOP

Timeout Interrupt occurs.

The Frame field contains the frame number from the last

received SOF packet in full speed mode. This field has no

function for low-speed mode. If a SOF Timeout occurs, this

field contains the last received Frame number.

1: An SOF/EOP Timeout interrupt occurred

0: An SOF/EOP Timeout interrupt did not occur

Device n SOF/EOP Count Register [W]

• Device 1 SOF/EOP Count Register 0xC094

• Device 2 SOF/EOP Count Register 0xC0B4

Figure 39. Device n SOF/EOP Count Register

Bit #

Field

Reserved

Count...

Read/Write

Default

Bit #

Field

...Count

Read/Write

Default

1-ms SOF/EOP interval, the SOF/EOP count must be set

slightly greater then 0x2EE0.

The Device n SOF/EOP Count register must be written with

the time expected between receiving a SOF/EOPs. If the

SOF/EOP counter expires before an SOF/EOP is received, an

SOF/EOP Timeout Interrupt can be generated. The SOF/EOP

Timeout Interrupt Enable and SOF/EOP Timeout Interrupt

Flag are located in the Device n Interrupt Enable and Status

registers, respectively.

Count (Bits [13:0])

The Count field contains the current value of the SOF/EOP

down counter. At power-up and reset, this value is set to

0x2EE0 and for expected 1-ms SOF/EOP intervals, this

SOF/EOP count should be increased slightly.

The SOF/EOP count must be set slightly greater than the

expected SOF/EOP interval. The SOF/EOP counter decre-

ments at a 12-MHz rate. Therefore in the case of an expected

Reserved

All reserved bits must be written as ‘0’.

Document #: 38-08014 Rev. *G

Page 38 of 78

[+] Feedback

CY7C67200

OTG Control Registers

Table 28.OTG Registers

There is one register dedicated for OTG operation. This

Address

C098H

R/W

OTG Control Register

R/W

OTG Control Register [0xC098] [R/W]

Figure 40. OTG Control Register

Bit #

Field

Reserved

VBUS

Pull-up

Enable

Receive

Disable

Charge Pump

Enable

VBUS

Discharge

Enable

D+

Pull-up

Enable

D–

Pull-up

Enable

Read/Write

Default

R/W

Bit #

Field

D+

Pull-down

Enable

D–

Pull-down

Enable

Reserved

OTG Data

Status

VBUS Valid

Flag

Read/Write

Default

R/W

D– Pull-up Enable (Bit 8)

The OTG Control register allows control and monitoring over

the OTG port on Port1A.

The D– Pull-up Enable bit enables or disables a pull-up

resistor on the OTG D– data line.

1: OTG D– dataline pull-up resistor enabled

VBUS Pull-up Enable (Bit 13)

0: OTG D– dataline pull-up resistor disabled

The VBUS Pull-up Enable bit enables or disables a 500 ohm

pull-up resistor onto OTG VBus.

D+ Pull-down Enable (Bit 7)

1: 500 ohm pull-up resistor enabled

The D+ Pull-down Enable bit enables or disables a pull-down

resistor on the OTG D+ data line.

0: 500 ohm pull-up resistor disabled

1: OTG D+ dataline pull-down resistor enabled

Receive Disable (Bit 12)

0: OTG D+ dataline pull-down resistor disabled

The Receive Disable bit enables or powers down (disables)

the OTG receiver section.

D– Pull-down Enable (Bit 6)

1: OTG receiver powered down and disabled

The D– Pull-down Enable bit enables or disables a pull-down

resistor on the OTG D– data line.

0: OTG receiver enabled

1: OTG D– dataline pull-down resistor enabled

Charge Pump Enable (Bit 11)

0: OTG D– dataline pull-down resistor disabled

The Charge Pump Enable bit enables or disables the OTG

VBus charge pump.

OTG Data Status (Bit 2)

1: OTG VBus charge pump enabled

The OTG Data Status bit is a read only bit and indicates the

TTL logic state of the OTG VBus pin.

0: OTG VBus charge pump disabled

1: OTG VBus is greater than 2.4V

VBUS Discharge Enable (Bit 10)

0: OTG VBus is less than 0.8V

The VBUS Discharge Enable bit enables or disables a 2K-ohm

discharge pull-down resistor onto OTG VBus.

ID Status (Bit 1)

1: 2K-ohm pull-down resistor enabled

The ID Status bit is a read only bit that indicates the state of

the OTG ID pin on Port A.

0: 2K-ohm pull-down resistor disabled

1: OTG ID Pin is not connected directly to ground (>10K ohm)

D+ Pull-up Enable (Bit 9)

0: OTG ID Pin is connected directly ground (< 10 ohm)

The D+ Pull-up Enable bit enables or disables a pull-up

resistor on the OTG D+ data line.

1: OTG D+ dataline pull-up resistor enabled

0: OTG D+ dataline pull-up resistor disabled

Document #: 38-08014 Rev. *G

Page 39 of 78

[+] Feedback

CY7C67200

VBUS Valid Flag (Bit 0)

1: OTG VBus is greater then 4.4V

0: OTG VBus is less then 4.4V

The VBUS Valid Flag bit indicates whether OTG VBus is

greater than 4.4V. After turning on VBUS, firmware should wait

at least 10 µs before this reading this bit.

Reserved

All reserved bits must be written as ‘0’.

GPIO Registers

There are seven registers dedicated for GPIO operations. These seven registers are covered in this section and summarized in

T a ble 29.

Table 29.GPIO Registers

Address

0xC006

0xC01E

0xC020

0xC022

0xC024

0xC026

0xC028

R/W

GPIO Control Register

GPIO0 Output Data Register

GPIO0 Input Data Register

GPIO0 Direction Register

GPIO1 Output Data Register

GPIO1 Input Data Register

GPIO1 Direction Register

R/W

GPIO Control Register [0xC006] [R/W]

Figure 41. GPIO Control Register

Bit #

Write Protect

Enable

Reserved

SAS

Enable

Mode

Select

Field

Read/Write

Default

R/W

Bit #

HSS

Reserved

SPI

Reserved

Interrupt 0

Enable

Field

Enable

R/W

Polarity Select

Read/Write

Default

R/W

Mode Select (Bits [10:8])

The GPIO Control register configures the GPIO pins for

various interface options. It also controls the polarity of the

GPIO interrupt on IRQ0 (GPIO24).

The Mode Select field selects how GPIO[15:0] and

GPIO[24:19] are used as defined in T a ble 30.

Table 30.Mode Select Definition

Write Protect Enable (Bit 15)

Mode Select

GPIO Configuration

[10:8]

The Write Protect Enable bit enables or disables the GPIO

write protect. When Write Protect is enabled, the GPIO Mode

Select [15:8] bits are read-only until a chip reset.

111

110

Reserved

SCAN – (HW) Scan diagnostic. For produc-

tion test only. Not for normal operation

1: Enable Write Protect

0: Disable Write Protect

101

100

011

010

001

000

HPI – Host Port Interface

Reserved

SAS Enable (Bit 11)

Reserved

The SAS Enable bit, when in SPI mode, reroutes the SPI port

SPI_nSSI pin to GPIO[15] rather then GPIO[9].

Reserved

1: Reroute SPI_nss to GPIO[15]

Reserved

GPIO – General Purpose Input Output

0: Leave SPI_nss on GPIO[9]

Document #: 38-08014 Rev. *G

Page 40 of 78

[+] Feedback

CY7C67200

HSS Enable (Bit 7)

Interrupt 0 Polarity Select (Bit 1)

The HSS Enable bit routes HSS to GPIO[15:12].

1: HSS is routed to GPIO

The Interrupt 0 Polarity Select bit selects the polarity for IRQ0.

1: Sets IRQ0 to rising edge

0: HSS is not routed to GPIOs. GPIO[15:12] are free for other

0: Sets IRQ0 to falling edge

purposes.

Interrupt 0 Enable (Bit 0)

SPI Enable (Bit 5)

The Interrupt 0 Enable bit enables or disables IRQ0. The GPIO

bit on the interrupt Enable register must also be set in order for

this for this interrupt to be enabled.

The SPI Enable bit routes SPI to GPIO[11:8]. If the SAS

Enable bit is set, it overrides and routes the SPI_nSSI pin to

GPIO15.

1: Enable IRQ0

1: SPI is routed to GPIO[11:8]

0: Disable IRQ0

0: SPI is not routed to GPIO[11:8]. GPIO[11:8] are free for

other purposes.

Reserved

All reserved bits must be written as ‘0’.

GPIO 0 Output Data Register [0xC01E] [R/W]

Figure 42. GPIO 0 Output Data Register

Bit #

GPIO15

R/W

GPIO14

R/W

GPIO13

R/W

GPIO12

R/W

GPIO11

R/W

GPIO10

R/W

GPIO9

R/W

GPIO8

R/W

Field

Read/Write

Default

Bit #

GPIO7

R/W

GPIO6

R/W

GPIO5

R/W

GPIO4

R/W

GPIO3

R/W

GPIO2

R/W

GPIO1

R/W

GPIO0

R/W

Field

Read/Write

Default

The GPIO 0 Output Data register controls the output data of the GPIO pins. The GPIO 0 Output Data register controls GPIO15

to GPIO0 while the GPIO 1 Output Data register controls GPIO31 to GPIO19. When read, this register reads back the last data

written, not the data on pins configured as inputs (see Input Data Register).

Writing a 1 to any bit will output a high voltage on the corresponding GPIO pin.

Reserved

All reserved bits must be written as ‘0’.

GPIO 1 Output Data Register [0xC024] [R/W]

Figure 43. GPIO n Output Data Register

Bit #

GPIO31

R/W

GPIO30

R/W

GPIO29

R/W

GPIO24

R/W

Field

Reserved

Read/Write

Default

Bit #

GPIO23

R/W

GPIO22

R/W

GPIO21

R/W

GPIO20

R/W

Field

GPIO19

R/W

Reserved

Read/Write

Default

The GPIO 1 Output Data register controls the output data of the GPIO pins. The GPIO 0 Output Data register controls GPIO15

to GPIO0 while the GPIO 1 Output Data register controls GPIO31 to GPIO19. When read, this register reads back the last data

written, not the data on pins configured as inputs (see Input Data Register).

Document #: 38-08014 Rev. *G

Page 41 of 78

[+] Feedback

CY7C67200

Writing a 1 to any bit will output a high voltage on the corresponding GPIO pin.

Reserved

All reserved bits must be written as ‘0’.

GPIO 0 Input Data Register [0xC020] [R]

Figure 44. GPIO 0 Input Data Register

Bit #

Field

GPIO15

GPIO14

GPIO13

GPIO12

GPIO11

GPIO10

GPIO9

GPIO8

Read/Write

Default

Bit #

Field

GPIO7

GPIO6

GPIO5

GPIO4

GPIO3

GPIO2

GPIO1

GPIO0

Read/Write

Default

The GPIO 0 Input Data register reads the input data of the GPIO pins. The GPIO 0 Input Data register reads from GPIO15 to

GPIO0 while the GPIO 1 Input Data register reads from GPIO31 to GPIO19.

Every bit represents the voltage of that GPIO pin.

GPIO 1 Input Data Register [0xC026] [R]

Figure 45. GPIO 1 Input Data Register

Bit #

Field

GPIO31

GPIO30

GPIO29

Reserved

GPIO24

Read/Write

Default

Bit #

Field

GPIO23

GPIO22

GPIO21

GPIO20

GPIO19

Reserved

Read/Write

Default

The GPIO 1 Input Data register reads the input data of the GPIO pins. The GPIO 0 Input Data register reads from GPIO15 to

GPIO0 while the GPIO 1 Input Data register reads from GPIO31 to GPIO19.

Every bit represents the voltage of that GPIO pin.

GPIO 0 Direction Register [0xC022] [R/W]

Figure 46. GPIO 0 Direction Register

Bit #

GPIO15

R/W

GPIO14

R/W

GPIO13

R/W

GPIO12

R/W

GPIO11

R/W

GPIO10

R/W

GPIO9

R/W

GPIO8

R/W

Field

Read/Write

Default

Bit #

GPIO7

R/W

GPIO6

R/W

GPIO5

R/W

GPIO4

R/W

GPIO3

R/W

GPIO2

R/W

GPIO1

R/W

GPIO0

R/W

Field

Read/Write

Default

Document #: 38-08014 Rev. *G

Page 42 of 78

[+] Feedback

CY7C67200

The GPIO 0 Direction register controls the direction of the GPIO data pins (input/output). The GPIO 0 Direction register controls

GPIO15 to GPIO0 while the GPIO 1 Direction register controls GPIO31 to GPIO19.

When any bit of this register is set to ‘1’, the corresponding GPIO data pin becomes an output. When any bit of this register is

set to ‘0’, the corresponding GPIO data pin becomes an input.

Reserved

All reserved bits must be written as ‘0’.

GPIO 1 Direction Register [0xC028] [R/W]

Figure 47. GPIO 1 Direction Register

Bit #

GPIO31

R/W

GPIO30

R/W

GPIO29

R/W

GPIO24

R/W

Field

Reserved

Read/Write

Default

R/W

Bit #

GPIO23

R/W

GPIO22

R/W

GPIO21

R/W

GPIO20

R/W

Reserved

R/W

Field

GPIO19

R/W

Read/Write

Default

R/W

The GPIO 1 Direction register controls the direction of the GPIO data pins (input/output). The GPIO 0 Direction register controls

GPIO15 to GPIO0 while the GPIO 1 Direction register controls GPIO31 to GPIO19.

When any bit of this register is set to ‘1’, the corresponding GPIO data pin becomes an output. When any bit of this register is

set to ‘0’, the corresponding GPIO data pin becomes an input.

Reserved

All reserved bits must be written as ‘0’.

HSS Registers

There are eight registers dedicated to HSS operation. Each of these registers are covered in this section and summarized in

T a ble 31.

Table 31.HSS Registers

Address

0xC070

0xC072

0xC074

0xC076

0xC078

0xC07A

0xC07C

0xC07E

R/W

HSS Control Register

HSS Baud Rate Register

HSS Transmit Gap Register

HSS Data Register

HSS Receive Address Register

HSS Receive Length Register

HSS Transmit Address Register

HSS Transmit Length Register

Document #: 38-08014 Rev. *G

Page 43 of 78

[+] Feedback

CY7C67200

HSS Control Register [0xC070] [R/W]

Figure 48. HSS Control Register

Bit #

HSS

Enable

RTS

CTS

XOFF

Enable

CTS

Enable

Receive

Interrupt

Enable

Done

Interrupt

Enable

Polarity Select Polarity Select

Field

Read/Write

Default

R/W

Bit #

Transmit

Receive

One

Transmit

Ready

Packet

Mode

Receive

Overflow

Flag

Receive

Packet Ready

Flag

Receive

Ready

Flag

DoneInterrupt DoneInterrupt

Stop Bit

Field

Enable

R/W

Enable

R/W

Select

Read/Write

Default

R/W

Receive Interrupt Enable (Bit 9)

The HSS Control register provides high-level status and

control over the HSS port.

The Receive Interrupt Enable bit enables or disables the

Receive Ready and Receive Packet Ready interrupts.

1: Enable the Receive Ready and Receive Packet Ready

interrupts

HSS Enable (Bit 15)

The HSS Enable bit enables or disables HSS operation.

1: Enables HSS operation

0: Disable the Receive Ready and Receive Packet Ready

interrupts

0: Disables HSS operation

Done Interrupt Enable (Bit 8)

RTS Polarity Select (Bit 14)

The Done Interrupt Enable bit enables or disables the Transmit

Done and Receive Done interrupts.

The RTS Polarity Select bit selects the polarity of RTS.

1: RTS is true when LOW

1: Enable the Transmit Done and Receive Done interrupts

0: Disable the Transmit Done and Receive Done interrupts

0: RTS is true when HIGH

Transmit Done Interrupt Flag (Bit 7)

CTS Polarity Select (Bit 13)

The Transmit Done Interrupt Flag bit indicates the status of the

Transmit Done Interrupt. It will set when a block transmit is

finished. To clear the interrupt, a ‘1’ must be written to this bit.

The CTS Polarity Select bit selects the polarity of CTS.

1: CTS is true when LOW

0: CTS is true when HIGH

1: Interrupt triggered

XOFF (Bit 12)

0: Interrupt did not trigger

The XOFF bit is a read-only bit that indicates if an XOFF has

been received. This bit is automatically cleared when an XON

is received.

Receive Done Interrupt Flag (Bit 6)

The Receive Done Interrupt Flag bit indicates the status of the

Receive Done Interrupt. It will set when a block transmit is

finished. To clear the interrupt, a ‘1’ must be written to this bit.

1: XOFF received

0: XON received

1: Interrupt triggered

XOFF Enable (Bit 11)

0: Interrupt did not trigger

The XOFF Enable bit enables or disables XON/XOFF software

handshaking.

One Stop Bit (Bit 5)

The One Stop Bit bit selects between one and two stop bits for

transmit byte mode. In receive mode, the number of stop bits

may vary and does not need to be fixed.

1: Enable XON/XOFF software handshaking

0: Disable XON/XOFF software handshaking

CTS Enable (Bit 10)

1: One stop bit

The CTS Enable bit enables or disables CTS/RTS hardware

handshaking.

0: Two stop bits

1: Enable CTS/RTS hardware handshaking

0: Disable CTS/RTS hardware handshaking

Document #: 38-08014 Rev. *G

Page 44 of 78

[+] Feedback

CY7C67200

Transmit Ready (Bit 4)

Receive Packet Ready Flag (Bit 1)

The Transmit Ready bit is a read only bit that indicates if the

HSS Transmit FIFO is ready for the CPU to load new data for

transmission.

The Receive Packet Ready Flag bit is a read only bit that

indicates if the HSS receive FIFO is full with eight bytes.

1: HSS receive FIFO is full

1: HSS transmit FIFO ready for loading

0: HSS receive FIFO is not full

0: HSS transmit FIFO not ready for loading

Receive Ready Flag (Bit 0)

Packet Mode Select (Bit 3)

The Receive Ready Flag is a read only bit that indicates if the

HSS receive FIFO is empty.

The Packet Mode Select bit selects between Receive Packet

Ready and Receive Ready as the interrupt source for the

RxIntr interrupt.

1: HSS receive FIFO is not empty (one or more bytes is

reading for reading)

1: Selects Receive Packet Ready as the source

0: HSS receive FIFO is empty

0: Selects Receive Ready as the source

Receive Overflow Flag (Bit 2)

The Receive Overflow Flag bit indicates if the Receive FIFO

overflowed when set. This flag can be cleared by writing a ‘1’

to this bit.

1: Overflow occurred

0: Overflow did not occur

HSS Baud Rate Register [0xC072] [R/W]

Figure 49. HSS Baud Rate Register

Bit #

Baud...

R/W

Field

Reserved

Read/Write

Default

R/W

Bit #

Field

...Baud

Read/Write

Default

R/W

The HSS Baud Rate register sets the HSS Baud Rate. At reset, the default value is 0x0017 which sets the baud rate to 2.0 MHz.

Baud (Bits [12:0])

The Baud field is the baud rate divisor minus one, in units of 1/48 MHz. Therefore the Baud Rate = 48 MHz/(Baud + 1). This puts

a constraint on the Baud Value as follows: (24 – 1) < Baud > (5000 – 1)

Reserved

All reserved bits must bit written as ‘0’.

Document #: 38-08014 Rev. *G

Page 45 of 78

[+] Feedback

CY7C67200

HSS Transmit Gap Register [0xC074] [R/W]

Figure 50. HSS Transmit Gap Register

Bit #

Field

Reserved

Read/Write

Default

Bit #

Field

Transmit Gap Select

Read/Write

Default

R/W

The HSS Transmit Gap register is only valid in block transmit mode. It allows for a programmable number of stop bits to be inserted

thus overwriting the One Stop Bit in the HSS Control register. The default reset value of this register is 0x0009, equivalent to two

stop bits.

Transmit Gap Select (Bits [7:0])

The Transmit Gap Select field sets the inactive time between transmitted bytes. The inactive time = (Transmit Gap Select – 7) *

bit time. Therefore an Transmit Gap Select Value of 8 is equal to having one Stop bit.

Reserved

All reserved bits must be written as ‘0’.

HSS Data Register [0xC076] [R/W]

Figure 51. HSS Data Register

Bit #

Field

Reserved

Read/Write

Default

Bit #

Field

Data

Read/Write

Default

R/W

The HSS Data register contains data received on the HSS port (not for block receive mode) when read. This receive data is valid

when the Receive Ready bit of the HSS Control register is set to ‘1’. Writing to this register initiates a single byte transfer of data.

The Transmit Ready Flag in the HSS Control register must read ‘1’ before writing to this register (this avoids disrupting the

previous/current transmission).

Data (Bits [7:0])

The Data field contains the data received or to be transmitted on the HSS port.

Reserved

All reserved bits must be written as ‘0’.

Document #: 38-08014 Rev. *G

Page 46 of 78

[+] Feedback

CY7C67200

HSS Receive Address Register [0xC078] [R/W]

Figure 52. HSS Receive Address Register

Bit #

Field

Address...

Read/Write

Default

R/W

Bit #

Field

...Address

Read/Write

Default

R/W

The HSS Receive Address register is used as the base pointer address for the next HSS block receive transfer.

Address (Bits [15:0])

The Address field sets the base pointer address for the next HSS block receive transfer.

HSS Receive Counter Register [0xC07A] [R/W]

Figure 53. HSS Receive Counter Register

Bit #

Field

Reserved

Counter...

Read/Write

Default

R/W

Bit #

Field

...Counter

Read/Write

Default

R/W

The HSS Receive Counter register designates the block byte length for the next HSS receive transfer. This register must be

loaded with the word count minus one to start the block receive transfer. As each byte is received this register value is decre-

mented. When read, this register indicates the remaining length of the transfer.

Counter (Bits [9:0])

The Counter field value is equal to the word count minus one giving a maximum value of 0x03FF (1023) or 2048 bytes. When

the transfer is complete this register returns 0x03FF until reloaded.

Reserved

All reserved bits must be written as ‘0’.

Document #: 38-08014 Rev. *G

Page 47 of 78

[+] Feedback

CY7C67200

HSS Transmit Address Register [0xC07C] [R/W]

Figure 54. HSS Transmit Address Register

Bit #

Field

Address...

Read/Write

Default

R/W

Bit #

Field

...Address

Read/Write

Default

R/W

The HSS Transmit Address register is used as the base pointer address for the next HSS block transmit transfer.

Address (Bits [15:0])

The Address field sets the base pointer address for the next HSS block transmit transfer.

HSS Transmit Counter Register [0xC07E] [R/W]

Figure 55. HSS Transmit Counter Register

Bit #

Field

Reserved

Counter...

Read/Write

Default

R/W

Bit #

Field

...Counter

Read/Write

Default

R/W

HPI Registers

The HSS Transmit Counter register designates the block byte

length for the next HSS transmit transfer. This register must be

loaded with the word count minus one to start the block

transmit transfer. As each byte is transmitted this register

value is decremented. When read, this register indicates the

remaining length of the transfer.

There are five registers dedicated to HPI operation. In

addition, there is an HPI status port which can be address over

HPI. Each of these registers is covered in this section and are

summarized in T a ble 32.

Table 32.HPI Registers

HPI Breakpoint Register

Interrupt Routing Register

SIE1msg Register

Address

0x0140

0x0142

0x0144

0x0148

0xC0C6

R/W

Counter (Bits [9:0])

The Counter field value is equal to the word count minus one

giving a maximum value of 0x03FF (1023) or 2048 bytes.

When the transfer is complete this register returns 0x03FF

until reloaded.

SIE2msg Register

Reserved

HPI Mailbox Register

R/W

All reserved bits must be written as ‘0’.

Document #: 38-08014 Rev. *G

Page 48 of 78

[+] Feedback

CY7C67200

HPI Breakpoint Register [0x0140] [R]

Figure 56. HPI Breakpoint Register

Bit #

Field

Address...

Read/Write

Default

Bit #

Field

...Address

Read/Write

Default

The HPI Breakpoint register is a special on-chip memory location, which the external processor can access using normal HPI

memory read/write cycles. This register is read-only by the CPU but is read/write by the HPI port. The contents of this register

have the same effect as the Breakpoint register [0xC014]. This special Breakpoint register is used by software debuggers which

interface through the HPI port instead of the serial port.

When the program counter matches the Breakpoint Address, the INT127 interrupt triggers. To clear this interrupt, a zero value

must be written to this register.

Address (Bits [15:0])

The Address field is a 16-bit field containing the breakpoint address.

Interrupt Routing Register [0x0142] [R]

Figure 57. Interrupt Routing Register

Bit #

VBUS to HPI

Enable

ID to HPI

Enable

SOF/EOP2 to SOF/EOP2 to SOF/EOP1 to SOF/EOP1 to Reset2 to HPI HPI Swap 1

Field

HPI Enable

CPU Enable

HPI Enable

CPU Enable

Enable

Read/Write

Default

Bit #

Resume2 to

HPI Enable

Resume1 to

HPI Enable

Reserved

Done2 to HPI Done1 to HPI Reset1 to HPI HPI Swap 0

Field

Enable

Read/Write

Default

ID to HPI Enable (Bit 14)

The Interrupt Routing register allows the HPI port to take over

some or all of the SIE interrupts that usually go to the on-chip

CPU. This register is read-only by the CPU but is read/write by

the HPI port. By setting the appropriate bit to ‘1’, the SIE

interrupt is routed to the HPI port to become the HPI_INTR

signal and also readable in the HPI Status register. The bits in

this register select where the interrupts are routed. The

individual interrupt enable is handled in the SIE interrupt

enable register.

The ID to HPI Enable bit routes the OTG ID interrupt to the HPI

port instead of the on-chip CPU.

1: Route signal to HPI port

0: Do not route signal to HPI port

SOF/EOP2 to HPI Enable (Bit 13)

The SOF/EOP2 to HPI Enable bit routes the SOF/EOP2

interrupt to the HPI port.

1: Route signal to HPI port

VBUS to HPI Enable (Bit 15)

0: Do not route signal to HPI port

The VBUS to HPI Enable bit routes the OTG VBUS interrupt

to the HPI port instead of the on-chip CPU.

1: Route signal to HPI port

0: Do not route signal to HPI port

Document #: 38-08014 Rev. *G

Page 49 of 78

[+] Feedback

CY7C67200

SOF/EOP2 to CPU Enable (Bit 12)

Resume2 to HPI Enable (Bit 7)

The SOF/EOP2 to CPU Enable bit routes the SOF/EOP2

interrupt to the on-chip CPU. Since the SOF/EOP2 interrupt

can be routed to both the on-chip CPU and the HPI port the

firmware must ensure only one of the two (CPU, HPI) resets

the interrupt.

The Resume2 to HPI Enable bit routes the USB Resume

interrupt that occurs on Host 2 to the HPI port instead of the

on-chip CPU.

1: Route signal to HPI port

0: Do not route signal to HPI port

1: Route signal to CPU

Resume1 to HPI Enable (Bit 6)

0: Do not route signal to CPU

The Resume1 to HPI Enable bit routes the USB Resume

interrupt that occurs on Host 1 to the HPI port instead of the

on-chip CPU.

SOF/EOP1 to HPI Enable (Bit 11)

The SOF/EOP1 to HPI Enable bit routes the SOF/EOP1

interrupt to the HPI port.

1: Route signal to HPI port

0: Do not route signal to HPI port

Done2 to HPI Enable (Bit 3)

SOF/EOP1 to CPU Enable (Bit 10)

The Done2 to HPI Enable bit routes the Done interrupt for

Host/Device 2 to the HPI port instead of the on-chip CPU.

The SOF/EOP1 to CPU Enable bit routes the SOF/EOP1

interrupt to the on-chip CPU. Since the SOF/EOP1 interrupt

can be routed to both the on-chip CPU and the HPI port the

firmware must ensure only one of the two (CPU, HPI) resets

the interrupt.

1: Route signal to HPI port

0: Do not route signal to HPI port

Done1 to HPI Enable (Bit 2)

1: Route signal to CPU

The Done1 to HPI Enable bit routes the Done interrupt for

Host/Device 1 to the HPI port instead of the on-chip CPU.

0: Do not route signal to CPU

1: Route signal to HPI port

Reset2 to HPI Enable (Bit 9)

0: Do not route signal to HPI port

The Reset2 to HPI Enable bit routes the USB Reset interrupt

that occurs on Device 2 to the HPI port instead of the on-chip

CPU.

Reset1 to HPI Enable (Bit 1)

The Reset1 to HPI Enable bit routes the USB Reset interrupt

that occurs on Device 1 to the HPI port instead of the on-chip

CPU.

1: Route signal to HPI port

0: Do not route signal to HPI port

1: Route signal to HPI port

HPI Swap 1 Enable (Bit 8)

0: Do not route signal to HPI port

Both HPI Swap bits (bits 8 and 0) must be set to identical

values. When set to ‘00’, the most significant data byte goes

to HPI_D[15:8] and the least significant byte goes to

HPI_D[7:0]. This is the default setting. By setting to ‘11’, the

most significant data byte goes to HPI_D[7:0] and the least

significant byte goes to HPI_D[15:8].

HPI Swap 0 Enable (Bit 0)

Both HPI Swap bits (bits 8 and 0) must be set to identical

values. When set to ‘00’, the most significant data byte goes

to HPI_D[15:8] and the least significant byte goes to

HPI_D[7:0]. This is the default setting. By setting to ‘11’, the

most significant data byte goes to HPI_D[7:0] and the least

significant byte goes to HPI_D[15:8].

Document #: 38-08014 Rev. *G

Page 50 of 78

[+] Feedback

CY7C67200

SIEXmsg Register [W]

• SIE1msg Register 0x0144

• SIE2msg Register 0x0148

Figure 58. SIEXmsg Register

Bit #

Field

Data...

Read/Write

Default

Bit #

Field

...Data

Read/Write

Default

The SIEXmsg register allows an interrupt to be generated on the HPI port. Any write to this register causes the SIEXmsg flag in

the HPI Status Port to go high and also causes an interrupt on the HPI_INTR pin. The SIEXmsg flag is automatically cleared

when the HPI port reads from this register.

Data (Bits [15:0])

The Data field[15:0] simply must have any value written to it to cause SIExmsg flag in the HPI Status Port to go high.

HPI Mailbox Register [0xC0C6] [R/W]

Figure 59. HPI Mailbox Register

Bit #

Field

Message...

Read/Write

Default

R/W

Bit #

Field

...Message

Read/Write

Default

R/W

The HPI Mailbox register provides a common mailbox between the CY7C67200 and the external host processor.

If enabled, the HPI Mailbox RX Full interrupt triggers when the external host processor writes to this register. When the

CY7C67200 reads this register the HPI Mailbox RX Full interrupt automatically gets cleared.

If enabled, the HPI Mailbox TX Empty interrupt triggers when the external host processor reads from this register. The HPI Mailbox

TX Empty interrupt is automatically cleared when the CY7C67200 writes to this register.

In addition, when the CY7C67200 writes to this register, the HPI_INTR signal on the HPI port asserts signaling the external

processor that there is data in the mailbox to read. The HPI_INTR signal deasserts when the external host processor reads from

this register.

Message (Bits [15:0])

The Message field contains the message that the host processor wrote to the HPI Mailbox register.

Document #: 38-08014 Rev. *G

Page 51 of 78

[+] Feedback

CY7C67200

HPI Status Port [] [HPI: R]

Figure 60. HPI Status Port

Bit #

VBUS

Flag

Reserved

SOF/EOP2

Flag

Reserved

SOF/EOP1

Flag

Reset2

Flag

Mailbox In

Flag

Field

Read/Write

Default

Bit #

Resume2

Flag

Resume1

Flag

SIE2msg

Done2

Flag

Done1

Flag

Reset1

Flag

Mailbox Out

Flag

SIE1msg

Field

Read/Write

Default

Mailbox In Flag (Bit 8)

The HPI Status Port provides the external host processor with

the MailBox status bits plus several SIE status bits. This

SIE status bits are provided to aid external device driver

firmware development, and are not recommended for applica-

tions that do not have an intimate relationship with the on-chip

BIOS.

The Mailbox In Flag bit is a read-only bit that indicates if a

message is ready in the incoming mailbox. This interrupt

clears when on-chip CPU reads from the HPI Mailbox register.

1: Interrupt triggered

0: Interrupt did not trigger

Resume2 Flag (Bit 7)

Reading from the HPI Status Port does not result in a CPU HPI

interface memory access cycle. The external host may contin-

uously poll this register without degrading the CPU or DMA

performance.

The Resume2 Flag bit is a read-only bit that indicates if a USB

resume interrupt occurs on either Host/Device 2.

1: Interrupt triggered

0: Interrupt did not trigger

VBUS Flag (Bit 15)

The VBUS Flag bit is a read-only bit that indicates whether

OTG VBus is greater than 4.4V. After turning on VBUS,

firmware should wait at least 10 µs before this reading this bit.

Resume1 Flag (Bit 6)

The Resume1 Flag bit is a read-only bit that indicates if a USB

resume interrupt occurs on either Host/Device 1.

1: OTG VBus is greater then 4.4V

1: Interrupt triggered

0: OTG VBus is less then 4.4V

0: Interrupt did not trigger

ID Flag (Bit 14)

SIE2msg (Bit 5)

The ID Flag bit is a read-only bit that indicates the state of the

OTG ID pin.

The SIE2msg Flag bit is a read-only bit that indicates if the

CY7C67200 CPU has written to the SIE2msg register. This bit

is cleared on an HPI read.

SOF/EOP2 Flag (Bit 12)

1: The SIE2msg register has been written by the CY7C67200

CPU

The SOF/EOP2 Flag bit is a read-only bit that indicates if a

SOF/EOP interrupt occurs on either Host/Device 2.

0: The SIE2msg register has not been written by the

CY7C67200 CPU

1: Interrupt triggered

0: Interrupt did not trigger

SIE1msg (Bit 4)

SOF/EOP1 Flag (Bit 10)

The SIE1msg Flag bit is a read-only bit that indicates if the

CY7C67200 CPU has written to the SIE1msg register. This bit

is cleared on an HPI read.

The SOF/EOP1 Flag bit is a read-only bit that indicates if a

SOF/EOP interrupt occurs on either Host/Device 1.

1: Interrupt triggered

1: The SIE1msg register has been written by the CY7C67200

CPU

0: Interrupt did not trigger

0: The SIE1msg register has not been written by the

CY7C67200 CPU

Reset2 Flag (Bit 9)

The Reset2 Flag bit is a read-only bit that indicates if a USB

Reset interrupt occurs on either Host/Device 2.

Done2 Flag (Bit 3)

In host mode the Done2 Flag bit is a read-only bit that indicates

if a host packet done interrupt occurs on Host 2. In device

1: Interrupt triggered

0: Interrupt did not trigger

Document #: 38-08014 Rev. *G

Page 52 of 78

[+] Feedback

CY7C67200

mode this read only bit indicates if any of the endpoint inter-

rupts occurs on Device 2. Firmware needs to determine which

endpoint interrupt occurred.

Reset1 Flag (Bit 1)

The Reset1 Flag bit is a read-only bit that indicates if a USB

Reset interrupt occurs on either Host/Device 1.

1: Interrupt triggered

0: Interrupt did not trigger

Done1 Flag (Bit 2)

Mailbox Out Flag (Bit 0)

In host mode the Done 1 Flag bit is a read-only bit that

indicates if a host packet done interrupt occurs on Host 1. In

device mode this read-only bit indicates if any of the endpoint

interrupts occurs on Device 1. Firmware needs to determine

which endpoint interrupt occurred.

The Mailbox Out Flag bit is a read-only bit that indicates if a

message is ready in the outgoing mailbox. This interrupt clears

when the external host reads from the HPI Mailbox register.

1: Interrupt triggered

0: Interrupt did not trigger

1: Interrupt triggered

0: Interrupt did not trigger

SPI Registers

There are 12 registers dedicated to SPI operation. Each register is covered in this section and summarized in T a ble 33.

Table 33.SPI Registers

SPI Configuration Register

Address

0xC0C8

0xC0CA

0xC0CC

0xC0CE

0xC0D0

0xC0D2

0xC0D4

0xC0D6

0xC0D8

0xC0DA

0xC0DC

0xC0DE

R/W

SPI Control Register

SPI Interrupt Enable Register

SPI Status Register

SPI Interrupt Clear Register

SPI CRC Control Register

SPI CRC Value

R/W

SPI Data Register

SPI Transmit Address Register

SPI Transmit Count Register

SPI Receive Address Register

SPI Receive Count Register

SPI Configuration Register [0xC0C8] [R/W]

Figure 61. SPI Configuration Register

Bit #

3Wire

Enable

Phase

Select

SCK Polarity

Select

Scale Select

Reserved

Field

Read/Write

Default

R/W

Bit #

Master

Active Enable

Master

Enable

SS Delay Select

Field

Read/Write

Default

R/W

The SPI Configuration register controls the SPI port. Fields apply to both master and slave mode unless otherwise noted.

Document #: 38-08014 Rev. *G

Page 53 of 78

[+] Feedback

CY7C67200

3Wire Enable (Bit 15)

Master Active Enable (Bit 7)

The 3Wire Enable bit indicates if the MISO and MOSI data

lines are tied together allowing only half duplex operation.

The Master Active Enable bit is a read-only bit that indicates if

the master state machine is active or idle. This field only

applies to master mode.

1: MISO and MOSI data lines are tied together

1: Master state machine is active

0: Normal MISO and MOSI Full Duplex operation (not tied

together)

0: Master state machine is idle

Phase Select (Bit 14)

Master Enable (Bit 6)

The Phase Select bit selects advanced or delayed SCK phase.

This field only applies to master mode.

The Master Enable bit sets the SPI interface to master or

slave. This bit is only writable when the Master Active Enable

bit reads ‘0’, otherwise value will not change.

1: Advanced SCK phase

1: Master SPI interface

0: Delayed SCK phase

0: Slave SPI interface

SCK Polarity Select (Bit 13)

SS Enable (Bit 5)

This SCK Polarity Select bit selects the polarity of SCK.

1: Positive SCK polarity

The SS Enable bit enables or disables the master SS output.

1: Enable master SS output

0: Negative SCK polarity

0: Disable master SS output (three-state master SS output, for

single SS line in slave mode)

Scale Select (Bits [12:9])

The Scale Select field provides control over the SCK

frequency, based on 48 MHz. See T a ble 34 for a definition of

this field. This field only applies to master mode.

SS Delay Select (Bits [4:0])

When the SS Delay Select field is set to ‘00000’ this indicates

manual mode. In manual mode SS is controlled by the SS

Manual bit of the SPI Control register. When the SS Delay

Select field is set between ‘00001’ to ‘11111’, this value

indicates the count in half bit times of auto transfer delay for:

SS LOW to SCK active, SCK inactive to SS HIGH, SS HIGH

time. This field only applies to master mode.

Table 34.Scale Select Field Definition for SCK Frequency

Scale Select [12:9]

0000

SCK Frequency

12 MHz

8 MHz

0001

0010

6 MHz

0011

4 MHz

0100

3 MHz

0101

2 MHz

0110

1.5 MHz

1 MHz

0111

1000

750 KHz

500 KHz

375 KHz

250 KHz

375 KHz

250 KHz

375 KHz

250 KHz

1001

1010

1011

1100

1101

1110

1111

Document #: 38-08014 Rev. *G

Page 54 of 78

[+] Feedback

CY7C67200

SPI Control Register [0xC0CA] [R/W]

Figure 62. SPI Control Register

Bit #

SCK

Strobe

FIFO

Init

Byte

Mode

Full Duplex

Manual

Read

Enable

Transmit

Ready

Receive

Data Ready

Field

Read/Write

Default

R/W

R/w

R/W

Bit #

Transmit

Empty

Receive

Full

Transmit Bit Length

Receive Bit Length

Field

Read/Write

Default

R/W

R/w

R/W

Read Enable (Bit 10)

The SPI Control register controls the SPI port. Fields apply to

both master and slave mode unless otherwise noted.

The Read Enable bit initiates a read phase for a master mode

transfer or set the slave to receive (in slave mode).

1: Initiates a read phase for a master transfer or sets a slave

to receive. In master mode this bit is sticky and remains set

until the read transfer begins.

SCK Strobe (Bit 15)

The SCK Strobe bit starts the SCK strobe at the selected

frequency and polarity (set in the SPI Configuration register),

but not phase. This bit feature can only be enabled when in

master mode and must be during a period of inactivity. This bit

is self-clearing.

0: Initiates the write phase for slave operation

Transmit Ready (Bit 9)

The Transmit Ready bit is a read-only bit that indicates if the

transmit port is ready to empty and ready to be written.

1: SCK Strobe Enable

0: No Function

1: Ready for data to be written to the port. The transmit FIFO

is not full.

FIFO Init (Bit 14)

0: Not ready for data to be written to the port

The FIFO Init bit initializes the FIFO and clear the FIFO Error

Status bit. This bit is self-clearing.

Receive Data Ready (Bit 8)

1: FIFO Init Enable

The Receive Data Ready bit is a read-only bit that indicates if

the receive port has data ready.

0: No Function

1: Receive port has data ready to read

Byte Mode (Bit 13)

0: Receive port does not have data ready

The Byte Mode bit selects between PIO (byte mode) and DMA

(block mode) operation.

Transmit Empty (Bit 7)

1: Set PIO (byte mode) operation

The Transmit Empty bit is a read-only bit that indicates if the

transmit FIFO is empty.

0: Set DMA (block mode) operation

1: Transmit FIFO is empty

Full Duplex (Bit 12)

0: Transmit FIFO is not empty

The Full Duplex bit selects between full-duplex and half-duplex

operation.

Receive Full (Bit 6)

1: Enable full duplex. Full duplex is not allowed and will not set

if the 3Wire Enable bit of the SPI Configuration register is set

to ‘1’

The Receive Full bit is a read-only bit that indicates if the

receive FIFO is full.

1: Receive FIFO is full

0: Enable half-duplex operation

0: Receive FIFO is not full

SS Manual (Bit 11)

Transmit Bit Length (Bits [5:3])

The SS Manual bit activates or deactivates SS if the SS Delay

Select field of the SPI Control register is all zeros and is

configured as master interface. This field only applies to

master mode.

The Transmit Bit Length field controls whether a full byte or

partial byte is to be transmitted. If Transmit Bit Length is ‘000’,

a full byte is transmitted. If Transmit Bit Length is ‘001’ to ‘111’,

the value indicates the number of bits that will be transmitted.

1: Activate SS, master drives SS line asserted LOW

0: Deactivate SS, master drives SS line deasserted HIGH

Document #: 38-08014 Rev. *G

Page 55 of 78

[+] Feedback

CY7C67200

Receive Bit Length (Bits [2:0])

The Receive Bit Length field controls whether a full byte or partial byte will be received. If Receive Bit Length is ‘000’ then a full

byte will be received. If Receive Bit Length is ‘001’ to ‘111’, then the value indicates the number of bits that will be received.

SPI Interrupt Enable Register [0xC0CC] [R/W]

Figure 63. SPI Interrupt Enable Register

Bit #

Field

Reserved...

Read/Write

Default

Bit #

...Reserved

Receive

Transmit

Transfer

Field

Interrupt Enable Interrupt Enable Interrupt Enable

Read/Write

Default

R/W

1: Enables byte mode transmit interrupt

The SPI Interrupt Enable register controls the SPI port.

0: Disables byte mode transmit interrupt

Receive Interrupt Enable (Bit 2)

Transfer Interrupt Enable (Bit 0)

The Receive Interrupt Enable bit enables or disables the byte

mode receive interrupt (RxIntVal).

The Transfer Interrupt Enable bit enables or disables the block

mode interrupt (XfrBlkIntVal).

1: Enable byte mode receive interrupt

1: Enables block mode interrupt

0: Disable byte mode receive interrupt

0: Disables block mode interrupt

Transmit Interrupt Enable (Bit 1)

Reserved

The Transmit Interrupt Enable bit enables or disables the byte

mode transmit interrupt (TxIntVal).

All reserved bits must be written as ‘0’.

SPI Status Register [0xC0CE] [R]

Figure 64. SPI Status Register

Bit #

Field

Reserved

Read/Write

Default

Bit #

FIFO Error

Flag

Reserved

Receive

Transmit

Transfer

Field

Interrupt Flag Interrupt Flag Interrupt Flag

Read/Write

Default

occured.This bit automatically clear when the SPI FIFO Init

Enable bit of the SPI Control register is set.

The SPI Status register is a read only register that provides

status for the SPI port.

1: Indicates FIFO error

0: Indicates no FIFO error

FIFO Error Flag (Bit 7)

The FIFO Error Flag bit is a read only bit that indicates if a FIFO

error occurred. When this bit is set to ‘1’ and the Transmit

Empty bit of the SPI Control register is set to ‘1’, then a Tx FIFO

underflow has occurred. Similarly, when set with the Receive

Full bit of the SPI Control register, a Rx FIFO overflow has

Receive Interrupt Flag (Bit 2)

The Receive Interrupt Flag is a read only bit that indicates if a

byte mode receive interrupt has triggered.

1: Indicates a byte mode receive interrupt has triggered

0: Indicates a byte mode receive interrupt has not triggered

Document #: 38-08014 Rev. *G

Page 56 of 78

[+] Feedback

CY7C67200

Transmit Interrupt Flag (Bit 1)

Transfer Interrupt Flag (Bit 0)

The Transmit Interrupt Flag is a read only bit that indicates a

byte mode transmit interrupt has triggered.

The Transfer Interrupt Flag is a read only bit that indicates a

block mode interrupt has triggered.

1: Indicates a byte mode transmit interrupt has triggered

1: Indicates a block mode interrupt has triggered

0: Indicates a byte mode transmit interrupt has not triggered

0: Indicates a block mode interrupt has not triggered

SPI Interrupt Clear Register [0xC0D0] [W]

Figure 65. SPI Interrupt Clear Register

Bit #

Field

Reserved

Read/Write

Default

Bit #

Reserved

Transmit

Transfer

Field

Interrupt Clear Interrupt Clear

Read/Write

Default

Transfer Interrupt Clear (Bit 0)

The SPI Interrupt Clear register is a write-only register that

allows the SPI Transmit and SPI Transfer Interrupts to be

cleared.

The Transfer Interrupt Clear bit is a write-only bit that will clear

the block mode interrupt. This bit is self clearing.

1: Clear the block mode interrupt

0: No function

Transmit Interrupt Clear (Bit 1)

The Transmit Interrupt Clear bit is a write-only bit that clears

the byte mode transmit interrupt. This bit is self-clearing.

Reserved

All reserved bits must be written as ‘0’.

1: Clear the byte mode transmit interrupt

0: No function

SPI CRC Control Register [0xC0D2] [R/W]

Figure 66. SPI CRC Control Register

Bit #

CRC Mode

CRC

Enable

CRC

Clear

Receive

CRC

One in

CRC

Zero in

CRC

Reserved...

Field

Read/Write

Default

R/W

Bit #

Field

...Reserved

Read/Write

Default

The SPI CRC Control register provides control over the CRC

source and polynomial value.

Table 35.CRC Mode Definition

CRCMode

CRC Polynomial

CRC Mode (Bits [15:14)

[9:8]

The CRCMode field selects the CRC polynomial as defined in

T a ble 35.

MMC 16-bit: X^16 + X^12 + X^5 + 1

(CCITT Standard)

CRC7 7-bit: X^7+ X^3 + 1

MST 16-bit: X^16+ X^15 + X^2 + 1

Reserved, 16-bit polynomial 1.

Document #: 38-08014 Rev. *G

Page 57 of 78

[+] Feedback

CY7C67200

CRC Enable (Bit 13)

One in CRC (Bit 10)

The CRC Enable bit enables or disables the CRC operation.

1: Enables CRC operation

The One in CRC bit is a read-only bit that indicates if the CRC

value is all zeros or not.

1: CRC value is not all zeros

0: Disables CRC operation

0: CRC value is all zeros

CRC Clear (Bit 12)

Zero in CRC (Bit 9)

The CRC Clear bit will clear the CRC with a load of all ones.

This bit is self clearing and always reads ‘0’.

The Zero in CRC bit is a read-only bit that indicates if the CRC

value is all ones or not.

1: Clear CRC with all ones

1: CRC value is not all ones

0: No Function

0: CRC value is all ones

Receive CRC (Bit 11)

Reserved

The Receive CRC bit determines whether the receive bit

stream or the transmit bit stream is used for the CRC data input

in full duplex mode. This bit is a don’t care in half-duplex mode.

All reserved bits must be written as ‘0’.

1: Assigns the receive bit stream

0: Assigns the transmit bit stream

SPI CRC Value Register [0xC0D4] [R/W]

Figure 67. SPI CRC Value Register

Bit #

Field

CRC...

Read/Write

Default

R/W

Bit #

Field

...CRC

Read/Write

Default

R/W

The SPI CRC Value register contains the CRC value.

CRC (Bits [15:0])

The CRC field contains the SPI CRC. In CRC Mode CRC7, the CRC value will be a seven bit value [6:0]. Therefore bits [15:7]

are invalid in CRC7 mode.

SPI Data Register [0xC0D6] [R/W]

Figure 68. SPI Data Register

Bit #

Field

Reserved

Read/Write

Default

Bit #

Field

Data

Read/Write

Default

R/W

The SPI Data register contains data received on the SPI port when read. Reading it empties the eight byte receive FIFO in PIO

byte mode. This receive data is valid when the receive bit of the SPI Interrupt Value is set to ‘1’ (RxIntVal triggers) or the Receive

Document #: 38-08014 Rev. *G

Page 58 of 78

[+] Feedback

CY7C67200

Data Ready bit of the SPI Control register is set to ‘1’. Writing to this register in PIO byte mode will initiate a transfer of data, the

number of bits defined by Transmit Bit Length field in the SPI Control register.

Data (Bits [7:0])

The Data field contains data received or to be transmitted on the SPI port.

Reserved

All reserved bits must be written as ‘0’.

SPI Transmit Address Register [0xC0D8] [R/W]

Figure 69. SPI Transmit Address Register

Bit #

Field

Address...

Read/Write

Default

R/W

Bit #

Field

...Address

Read/Write

Default

R/W

The SPI Transmit Address register is used as the base address for the SPI transmit DMA.

Address (Bits [15:0])

The Address field sets the base address for the SPI transmit DMA.

SPI Transmit Count Register [0xC0DA] [R/W]

Figure 70. SPI Transmit Count Register

Bit #

Count...

R/W

Field

Reserved

Read/Write

Default

R/W

Bit #

Field

...Count

Read/Write

Default

R/W

The SPI Transmit Count register designates the block byte length for the SPI transmit DMA transfer.

Count (Bits [10:0])

The Count field sets the count for the SPI transmit DMA transfer.

Reserved

All reserved bits must be written as ‘0’.

Document #: 38-08014 Rev. *G

Page 59 of 78

[+] Feedback

CY7C67200

SPI Receive Address Register [0xC0DC [R/W]

Figure 71. SPI Receive Address Register

Bit #

Field

Address...

Read/Write

Default

R/W

Bit #

Field

...Address

Read/Write

Default

R/W

The SPI Receive Address register is issued as the base address for the SPI Receive DMA.

Address (Bits [15:0])

The Address field sets the base address for the SPI receive DMA.

SPI Receive Count Register [0xC0DE] [R/W]

Figure 72. SPI Receive Count Register

Bit #

Count...

R/W

Field

Reserved

Read/Write

Default

R/W

Bit #

Field

...Count

Read/Write

Default

R/W

The SPI Receive Count register designates the block byte length for the SPI receive DMA transfer.

Count (Bits [10:0])

The Count field sets the count for the SPI receive DMA transfer.

Reserved

All reserved bits must be written as ‘0’.

UART Registers

There are three registers dedicated to UART operation. Each of these registers is covered in this section and summarized in

T a ble 36.

Table 36.UART Registers

UART Control Register

Address

0xC0E0

0xC0E2

0xC0E4

R/W

UART Status Register

UART Data Register

R/W

Document #: 38-08014 Rev. *G

Page 60 of 78

[+] Feedback

CY7C67200

UART Control Register [0xC0E0] [R/W]

Figure 73. UART Control Register

Bit #

Field

Reserved...

Read/Write

Default

Bit #

...Reserved

Scale

Select

Baud

Select

UART

Enable

Field

Read/Write

Default

R/W

Baud Select (Bits [3:1])

The UART Control register enables or disables the UART

allowing GPIO7 (UART_TXD) and GPIO6 (UART_RXD) to be

freed up for general use. This register must also be written to

set the baud rate, which is based on a 48-MHz clock.

Refer to T a ble 37 for a definition of this field.

Table 37.UART Baud Select Definition

Baud Rate

Baud Select [3:1]

Baud Rate

w/DIV8 = 1

w/DIV8 = 0

Scale Select (Bit 4)

000

001

010

011

100

101

110

111

115.2K baud

57.6K baud

38.4K baud

28.8K baud

19.2K baud

14.4K baud

9.6K baud

14.4K baud

7.2K baud

4.8K baud

3.6K baud

2.4K baud

1.8K baud

1.2K baud

0.9K baud

The Scale Select bit acts as a prescaler that will divide the

baud rate by eight.

1: Enable prescaler

0: Disable prescaler

7.2K baud

UART Enable (Bit 0)

The UART Enable bit enables or disables the UART.

1: Enable UART

0: Disable UART. This allows GPIO6 and GPIO7 to be used

for general use

Reserved

All reserved bits must be written as ‘0’.

UART Status Register [0xC0E2] [R]

Figure 74. UART Status Register

Bit #

Field

Reserved...

Read/Write

Default

Bit #

Field

...Reserved

Receive Full

Transmit Full

Read/Write

Default

The UART Status register is a read-only register that indicates the status of the UART buffer.

Document #: 38-08014 Rev. *G

Page 61 of 78

[+] Feedback

CY7C67200

Receive Full (Bit 1)

Transmit Full (Bit 0)

The Receive Full bit indicates whether the receive buffer is full.

It can be programmed to interrupt the CPU as interrupt #5

when the buffer is full. This can be done though the UART bit

of the Interrupt Enable register (0xC00E). This bit will automat-

ically be cleared when data is read from the UART Data

The Transmit Full bit indicates whether the transmit buffer is

full. It can be programmed to interrupt the CPU as interrupt #4

when the buffer is empty. This can be done though the UART

bit of the Interrupt Enable register (0xC00E). This bit will

automatically be set to ‘1’ after data is written by EZ-Host to

the UART Data register (to be transmitted). This bit will

automatically be cleared to ‘0’ after the data is transmitted.

1: Receive buffer full

1: Transmit buffer full (transmit busy)

0: Receive buffer empty

0: Transmit buffer is empty and ready for a new byte of data

UART Data Register [0xC0E4] [R/W]

Figure 75. UART Data Register

Bit #

Field

Reserved

Read/Write

Default

Bit #

Field

Data

Read/Write

Default

R/W

The UART Data register contains data to be transmitted or received from the UART port. Data written to this register will start a

data transmission and also causes the UART Transmit Empty Flag of the UART Status register to set. When data received on

the UART port is read from this register, the UART Receive Full Flag of the UART Status register will be cleared.

Data (Bits [7:0])

The Data field is where the UART data to be transmitted or received is located

Reserved

All reserved bits must be written as ‘0’.

Document #: 38-08014 Rev. *G

Page 62 of 78

[+] Feedback

CY7C67200

Pin Diagram

The following describes the CY7C67200 48-pin FBGA.

Figure 76. EZ-OTG Pin Diagram

GPIO3/D3

VCC

GND

GPIO1/D1

nRESET

Reserved

GPIO0/D0

GPIO4/D4

AGND

GPIO7/D7/TX

GND

GPIO6/D6/RX

OTGVBUS

DM2A

GPIO2/D2

GPIO5/D5

GPIO8/D8/

MISO

GPIO9/D9/

nSSI

CSWITCHA

CSWITCHB

DP2A

GPIO11/D1/

MOSI

GPIO10/D10/

SCK

VCC

BOOSTGND

VSWITCH

DP1A

GPIO14/D14/

RTS

GPIO13/D13/

RXD

GPIO12/D12/

TXD

BOOSTVCC

DM1A

GPIO30/SDA

GPIO29/

OTGID

GPIO19/A0

GPIO15/D15/

CTS/nSSI

XTALIN

AVCC

XTALOUT

GPIO23/nRD/

nWAIT

GPIO21/nCS/

nRESET

GND

GPIO31/SCL

GND

VCC

GPIO20/A1

GPIO24/INT/

IRQ0

GPIO22/nWR

Pin Descriptions

Table 38.Pin Descriptions

Name

Type

Description

GPIO31/SCK

GPIO30/SDA

GPIO29/OTGID

GPIO31: General Purpose IO

SCK: I2C EEPROM SCK

GPIO30: General Purpose IO

SDA: I2C EEPROM SDA

GPIO29: General Purpose IO

OTGID: Input for OTG ID pin. When used as OTGID, this pin must be

tied high through an external pull-up resistor. Assuming V = 3.0V, a

10K to 40K resistor must be used.

GPIO24: General Purpose IO

GPIO24/INT/IRQ0

INT: HPI INT

IRQ0: Interrupt Request 0. See Register 0xC006. This pin is also one

of two possible GPIO wakeup sources.

GPIO23/nRD

GPIO22/nWR

GPIO21/nCS

GPIO23: General Purpose IO

nRD: HPI nRD

GPIO22: General Purpose IO

nWR: HPI nWR

GPIO21: General Purpose IO

nCS: HPI nCS

Document #: 38-08014 Rev. *G

Page 63 of 78

[+] Feedback

CY7C67200

Table 38.Pin Descriptions (continued)

Name

Type

Description

GPIO20: General Purpose IO

GPIO20/A1

A1: HPI A1

GPIO19/A0

GPIO19: General Purpose IO

A0: HPI A0

GPIO15/D15/CTS/

nSSI

GPIO15: General Purpose IO

D15: D15 for HPI

CTS: HSS CTS

nSSI: SPI nSSI

GPIO14/D14/RTS

GPIO13/D13/RXD

GPIO12/D12/TXD

GPIO11/D11/MOSI

GPIO10/D10/SCK

GPIO9/D9/nSSI

GPIO8/D8/MISO

GPIO7/D7/TX

GPIO14: General Purpose IO

D14: D14 for HPI

RTS: HSS RTS

GPIO13: General Purpose IO

D13: D13 for HPI

RXD: HSS RXD (Data is received on this pin)

GPIO12: General Purpose IO

D12: D12 for HPI

TXD: HSS TXD (Data is transmitted from this pin)

GPIO11: General Purpose IO

D11: D11 for HPI

MOSI: SPI MOSI

GPIO10: General Purpose IO

D10: D10 for HPI

SCK: SPI SCK

GPIO9: General Purpose IO

D9: D9 for HPI

nSSI: SPI nSSI

GPIO8: General Purpose IO

D8: D8 for HPI

MISO: SPI MISO

GPIO7: General Purpose IO

D7: D7 for HPI

TX: UART TX (Data is transmitted from this pin)

GPIO6/D6/RX

GPIO6: General Purpose IO

D6: D6 for HPI

RX: UART RX (Data is received on this pin)

GPIO5/D5

GPIO4/D4

GPIO3/D3

GPIO2/D2

GPIO1/D1

GPIO0/D0

GPIO5: General Purpose IO

D5: D5 for HPI

GPIO4: General Purpose IO

D4: D4 for HPI

GPIO3: General Purpose IO

D3: D3 for HPI

GPIO2: General Purpose IO

D2: D2 for HPI

GPIO1: General Purpose IO

D1: D1 for HPI

GPIO0: General Purpose IO

D0: D0 for HPI

DM1A

DP1A

USB Port 1A D–

USB Port 1A D+

DM2A

USB Port 2A D–

DP2A

USB Port 2A D+

XTALIN

XTALOUT

nRESET

Input

Output

Input

Crystal Input or Direct Clock Input

Crystal output. Leave floating if direct clock source is used.

Reset

Document #: 38-08014 Rev. *G

Page 64 of 78

[+] Feedback

CY7C67200

Table 38.Pin Descriptions (continued)

Name

Type

–

Description

Tie to Gnd for normal operation.

Booster Power Input: 2.7V to 3.6V

Reserved

BOOSTV

Power

VSWITCH

BOOSTGND

OTGVBUS

CSWITCHA

CSWITCHB

Analog Output Booster Switching Output

Ground

Analog IO

Analog

Power

Booster Ground

USB OTG Vbus

Charge Pump Capacitor

USB Power

AGND

Ground

Power

USB Ground

H2, D6, A4

G6, B6, A1, H1

Main V

GND

Ground

Main Ground

Absolute Maximum Ratings

This section lists the absolute maximum ratings. Stresses above those listed can cause permanent damage to the device.

Exposure to maximum rated conditions for extended periods can affect device operation and reliability.

Storage Temperature ............................................................................................................................................–40°C to +125°C

Ambient Temperature with Power Supplied............................................................................................................–40°C to +85°C

Supply Voltage to Ground Potential...........................................................................................................................0.0V to +3.6V

DC Input Voltage to Any General Purpose Input Pin .............................................................................................................. 5.5V

DC Voltage Applied to XTALIN....................................................................................................................... –0.5V to V + 0.5V

Static Discharge Voltage (per MIL-STD-883, Method 3015)............................................................................................. > 2000V

Max Output Current, per Input Output. .................................................................................................................................. 4 mA

Operating Conditions

T (Ambient Temperature Under Bias)....................................................................................................................–40°C to +85°C

Supply Voltage (V , AV ) ....................................................................................................................................+3.0V to +3.6V

[5]

Supply Voltage (BoostV

)

...................................................................................................................................+2.7V to +3.6V

Ground Voltage........................................................................................................................................................................... 0V

(Oscillator or Crystal Frequency)............................................................................................................. 12 MHz ± 500 ppm

OSC

............................................................................................................................................................................ Parallel Resonant

Crystal Requirements (XTALIN, XTALOUT)

Table 39.Crystal Requirements

Crystal Requirements, (XTALIN, XTALOUT)

Parallel Resonant Frequency

Min.

Typical

Max.

Unit

MHz

PPM

Frequency Stability

Load Capacitance

Driver Level

–500

+500

500

µW

Start-up Time

Mode of Vibration: Fundamental

Note

5. The on-chip voltage booster circuit boosts BoostV to provide a nominal 3.3V V supply.

Document #: 38-08014 Rev. *G

Page 65 of 78

[+] Feedback

CY7C67200

DC Characteristics

[6]

Table 40.DC Characteristics

Parameter

, AV

Description

Supply Voltage

Conditions

Min.

3.0

Typ.

Max.

3.6

Unit

3.3

BoosV

Supply Voltage

2.7

3.6

Input HIGH Voltage

Input LOW Voltage

Input Leakage Current

Output Voltage HIGH

Output LOW Voltage

Output Current HIGH

Output Current LOW

Input Pin Capacitance

2.0

5.5

0.8

0< V < V

–10.0

2.4

+10.0

µA

= 4 mA

OUT

= –4 mA

0.4

µA

Except D+/D–

D+/D–

Hysteresis on nReset Pin

Supply Current

250

HYS

[7, 8]

2 transceivers powered

100

180

500

[7, 8]

Supply Current with Booster Enabled 2 transceivers powered

135

210

CCB

Sleep Current

USB Peripheral: includes 1.5K

internal pull up

SLEEP

Without 1.5K internal pull up

µA

Sleep Current with Booster Enabled USB Peripheral: includes 1.5K

internal pull up

210

500

µA

SLEEPB

Without 1.5K internal pull up

µA

Table 41.DC Characteristics: Charge Pump

Parameter

Description

Conditions

Min.

Typ.

Max.

5.25

100

Unit

Regulated OTGVBUS Voltage

8 mA< I

< 10 mA

LOAD

4.4

A_VBUS_OUT

Rise Time

I = 10 mA

LOAD

A_VBUS_RISE

A_VBUS_OUT

BUS

Maximum Load Current

OUTVBUS Bypass Capacitance 4.4V< V

< 5.25V

BUS

1.0

6.5

200

342

DRD_VBUS

OTGVBUS Leakage Voltage

Dataline Leakage Voltage

Charge Pump Current Draw

OTGVBUS not driven

A_VBUS_LKG

DRD_DATA_LKG

CHARGE

= 8 mA

= 0 mA

= 8 mA

= 0 mA

LOAD

Charge Pump Current Draw with I

Booster Active

CHARGEB

B-Device (SRP Capable)

Discharge Current

0V< V

< 5.25V

BUS

B_DSCHG_IN

A-Device VBUS Valid

4.4

A_VBUS_VALID

Notes

6. All tests were conducted with Charge pump off.

7. and I values are the same regardless of USB host or peripheral configuration.

CCB

8. There is no appreciable difference in I and I

values when only one transceiver is powered.

CCB

Document #: 38-08014 Rev. *G

Page 66 of 78

[+] Feedback

CY7C67200

Table 41.DC Characteristics: Charge Pump (continued)

Parameter

Description

A-Device Session Valid

B-Device Session Valid

B-Device Session End

Efficiency When Loaded

Data Line Pull Down

Conditions

Min.

0.8

Typ.

Max.

2.0

Unit

A_SESS_VALID

0.8

4.0

B_SESS_VALID

0.2

0.8

A_SESS_END

= 8 mA, VCC = 3.3V

V is not being driven

BUS

LOAD

14.25

24.8

100

Ω

A-device V

to GND

Input Impedance

kΩ

A_BUS_IN

BUS

B-device V

SRP Pull Up

Pull-up voltage = 3.0V

281

656

Ω

B_SRP_UP

BUS

SRP Pull Down

B_SRP_DWN

USB Transceiver

USB 2.0-compatible in full- and low-speed modes.

This product was tested as compliant to the USB-IF specification under the test identification number (TID) of 100390449 and is

listed on the USB-IF’s integrators list.

AC Timing Characteristics

Reset Timing

t_RESET

nRESET

t_IOACT

nRD or nWRL or nWRH

Reset Timing

Parameter

Description

nRESET Pulse Width

nRESET HIGH to nRD or nWRx Active

Min.

Typ.

Max.

Unit

clocks

µs

[9]

RESET

IOACT

200

Note

9. Clock is 12 MHz nominal.

Document #: 38-08014 Rev. *G

Page 67 of 78

[+] Feedback

CY7C67200

Clock Timing

t_CLK

t_LOW

XTALIN

t_FALL

t_HIGH

t_RISE

Clock Timing

Parameter

Description

Min.

Typ.

12.0

3.0

Max.

Unit

MHz

f_CLK

Clock Frequency

[10]

v_XINH

Clock Input High

1.5

3.6

(XTALOUT left floating)

t_CLK

Clock Period

83.17

83.33

83.5

t_HIGH

Clock High Time

Clock Low Time

Clock Rise Time

Clock Fall Time

t_LOW

t_RISE

5.0

t_FALL

Duty Cycle

I C EEPROM Timing

1. I2C EEPROM Bus Timing - Serial I/O

t_HIGH

t_LOW

t_R

t_F

SCL

t_SU.DAT

t_BUF

t_SU.STA

t_HD.DAT

t_SU.STO

t_HD.STA

SDA IN

t_AA

t_DH

SDA OUT

Parameter

Description

Min.

Typical

Max.

Unit

kHz

f_SCL

Clock Frequency

400

t_LOW

t_HIGH

t_AA

Clock Pulse Width Low

Clock Pulse Width High

Clock Low to Data Out Valid

Bus Idle Before New Transmission

Start Hold Time

1300

600

900

1300

600

t_BUF

t_HD.STA

t_SU.STA

t_HD.DAT

t_SU.DAT

t_R

Start Setup Time

Data In Hold Time

Data In Setup Time

Input Rise Time

100

300

t_F

Input Fall Time

t_SU.STO

Stop Setup Time

600

t_DH

Data Out Hold Time

Note

10. v_XINHis required to be 3.0V to obtain an internal 50/50 duty cycle clock.

Document #: 38-08014 Rev. *G

Page 68 of 78

[+] Feedback

CY7C67200

HPI (Host Port Interface) Write Cycle Timing

t_CYC

t_ASU

t_WP

t_AH

ADDR [1:0]

t_CSH

t_CSSU

nCS

nWR

nRD

Dout [15:0]

t_DSU

t_WDH

Parameter

t_ASU

Description

Min.

–1

Typical

Max.

Unit

Address Setup

Address Hold

t_AH

t_CSSU

t_CSH

Chip Select Setup

Chip Select Hold

Data Setup

t_DSU

t_WDH

t_WP

Write Data Hold

Write Pulse Width

Write Cycle Time

T^[11]

t_CYC

Note

11. T = system clock period = 1/48 MHz.

Document #: 38-08014 Rev. *G

Page 69 of 78

[+] Feedback

CY7C67200

HPI (Host Port Interface) Read Cycle Timing

t_CYC

t_ASU

t_RP

t_AH

ADDR [1:0]

t_CSH

t_CSSU

nCS

t_RDH

nWR

nRD

Din [15:0]

t_ACC

t_RDH

Parameter

t_ASU

Description

Min.

–1

Typ.

Max.

Unit

Address Setup

Address Hold

t_AH

–1

t_CSSU

t_CSH

Chip Select Setup

Chip Select Hold

–1

t_ACC

Data Access Time, from HPI_nRD falling

T^[11]

t_RDH

Read Data Hold, relative to the earlier of HPI_nRD

rising or HPI_nCS rising

t_RP

Read Pulse Width

Read Cycle Time

T^[11]

t_CYC

Document #: 38-08014 Rev. *G

Page 70 of 78

[+] Feedback

CY7C67200

HSS BYTE Mode Transmit

qt_clk

CPU_A[2:0]

CPUHSS_cs

CPU_wr

CPU may start another BYTE

transmit right after TxRdy

goes high

TxRdy flag

HSS_TxD

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

bit 7

stop bit

start bit

bit 0

start of last data bit to TxRdy high:

0 min, 4 T max.

(T is qt_clk period)

TxRdy low to start bit delay:

programmable

1 or 2 stop bits.

1 stop bit shown.

Byte transmit

triggered by a

CPU write to the

HSS_TxData register

0 min, BT max when starting from IDEL.

For back to back transmit, new START Bit

begins immediately following previous STOP bit.

(BT = bit period)

qt_clk, CPU_A, CPUHSS_cs, CPU_wr are internal signals, included in the diagram to illustrate relationship between CPU opera-

tions and HSS port operations.

Bit 0 is LSB of data byte. Data bits are HIGH true: HSS_TxD HIGH = data bit value ‘1’.

BT = bit time = 1/baud rate.

HSS Block Mode Transmit

HSS_TxD

GAP

BLOCK mode transmit timing is similar to BYTE mode, except the STOP bit time is controlled by the HSS_GAP value.

The BLOCK mode STOP bit time, t_GAP= (HSS_GAP – 9) BT, where BT is the bit time, and HSS_GAP is the content of the HSS

Transmit Gap register 90xC074].

The default t_GAPis 2 BT.

BT = bit time = 1/baud rate.

HSS BYTE and BLOCK Mode Receive

BT +/- 5%

received byte added to

receive FIFO during the final data bit time

BT +/- 5%

HSS_RxD

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

bit 7

stop bit start bit

start bit

bit 0

10 BT +/- 5%

Receive data arrives asynchronously relative to the internal clock.

Incoming data bit rate may deviate from the programmed baud rate clock by as much as ±5% (with HSS_RATE value of 23 or

higher).

BYTE mode received bytes are buffered in a FIFO. The FIFO not empty condition becomes the RxRdy flag.

BLOCK mode received bytes are written directly to the memory system.

Bit 0 is LSB of data byte. Data bits are HIGH true: HSS_RxD HIGH = data bit value ‘1’.

BT = bit time = 1/baud rate.

Document #: 38-08014 Rev. *G

Page 71 of 78

[+] Feedback

CY7C67200

Hardware CTS/RTS Handshake

tCTShold

tCTSsetup

HSS_RTS

HSS_CTS

HSS_TxD

Start of transmission not delayed by HSS_CTS

Start of transmission delayed until HSS_CTS goes high

t_CTSset-up: HSS_CTS setup time before HSS_RTS = 1.5T min.

_CTShold: HSS_CTS hold time after START bit = 0 ns min.

T = 1/48 MHz.

When RTS/CTS hardware handshake is enabled, transmission can be held off by deasserting HSS_CTS at least 1.5T before

HSS_RTS. Transmission resumes when HSS_CTS returns HIGH. HSS_CTS must remain HIGH until START bit.

HSS_RTS is deasserted in the third data bit time.

An application may choose to hold HSS_CTS until HSS_RTS is deasserted, which always occurs after the START bit.

Document #: 38-08014 Rev. *G

Page 72 of 78

[+] Feedback

CY7C67200

Table 42. Register Summary

R/W

Address Register

Bit 15

Bit 14

Bit 6

Bit 13

Bit 5

Bit 12

Bit 4

Bit 11

Bit 3

Bit 10

Bit 2

Bit 9

Bit 1

Bit 8

Bit 0

Default High

Default Low

0000 0000

0001 0100

Bit 7

0x0140

0x0142

HPI Breakpoint

Address...

...Address

Interrupt Routing

VBUS to HPI ID to HPI

Enable Enable

SOF/EOP2 to SOF/EOP2 to SOF/EOP1 to SOF/EOP1 to Reset2 to HPI HPI Swap 1

HPI Enable CPU Enable HPI Enable CPU Enable Enable Enable

Resume2 to Resume1 to Reserved

Done2 to HPI Done1 to HPI Reset1 to HPI HPI Swap 0

0000 0000

HPI Enable

Enable

1: 0x0144 SIEXmsg

2: 0x0148

Data...

xxxx xxxx

...Data

R/W

0x02n0

Device n Endpoint n Control

Reserved

IN/OUT

Ignore Enable Select

Sequence

Stall

Enable

ISO

Enable

NAK Interrupt Direction

Enable

ARM

Enable

Select

R/W

R.W

R/W

0x02n2

0x02n4

0x02n6

Device n Endpoint n Address Address...

xxxx xxxx

...Address

Reserved

...Count

Device n Endpoint n Count

Device n Endpoint n Status

Count...

OUT

Reserved

Overflow

Flag

Underflow

Flag

Exception Flag Exception Flag

Stall

Flag

NAK

Flag

Length

Set-up

Sequence

Status

Timeout

Flag

Error

Flag

ACK

Flag

xxxx xxxx

Exception Flag Flag

R/W

0x02n8

0xC000

Device n Endpoint n Count Re- Result...

xxxx xxxx

0000 0000

000x xxxx

sult

...Result

CPU Flags

Reserved...

...Reserved

Global Inter- Negative

Overflow

Flag

Carry

Flag

Zero

Flag

rupt Enable

Flag

R/W

0xC002

0xC004

0xC006

Bank

Address...

...Address

Revision...

...Revision

0000 0001

000x xxxx

xxxx xxxx

0000 0000

Reserved

Hardware Revision

GPIO Control

R/W

Write Protect UD

Enable

Reserved

SAS

Enable

Mode

Select

HSS

Enable

Reserved

SPI

Enable

Reserved

Interrupt 0

0000 0000

Polarity Select Enable

R/W

0xC008

CPU Speed

Reserved...

.Reserved

Reserved

0000 0000

0000 000F

0000 0000

CPU Speed

0xC00A Power Control

Host/Device 2 Reserved

Wake Enable

Host/Device 1 OTG

Wake Enable Wake Enable

Reserved

HSS

SPI

Wake Enable Wake Enable

HPI

Wake Enable

Reserved

GPI

Wake Enable

Reserved

Boost 3V

Sleep

Enable

Halt

Enable

0000 0000

R/W

0xC00C Watchdog Timer

0xC00E Interrupt Enable

Reserved...

...Reserved

0000 0000

Timeout

Flag

Period

Select

Lock

WDT

Reset

Enable

Strobe

Reserved

OTG

Interrupt

Enable

SPI

Interrupt

Enable

Reserved

Host/Device 2 Host/Device 1 0000 0000

Interrupt

Enable

Interrupt

Enable

HSS Interrupt In Mailbox

Out Mailbox

Interrupt

Enable

Reserved

UART

Interrupt

Enable

GPIO

Interrupt

Enable

Timer 1

Interrupt

Enable

Timer 0

Interrupt

Enable

0001 0000

Enable

Interrupt

Enable

R/W

0xC098

OTG Control

Reserved

VBUS

Receive

Charge Pump VBUS Dis-

D+

D–

0000 0000

0000 0XXX

Pull-up Enable Disable

Enable

charge Enable Pull-up Enable Pull-up Enable

D+

Pull-down

Enable

D–

Pull-down

Enable

Reserved

OTG Data Sta- ID

tus

VBUS Valid

Flag

Status

R/W

0: 0xC010 Timer n

1: 0xC012

Count...

...Count

Address...

...Address

Address...

...Address

GPIO15

GPIO7

1111 1111

0000 0000

0xC014

Breakpoint

1: 0xC018 Extended Page n Map

2: 0xC01A

0xC01E GPIO 0 Output Data

GPIO14

GPIO6

GPIO14

GPIO6

GPIO14

GPIO6

GPIO13

GPIO5

GPIO13

GPIO5

GPIO13

GPIO5

GPIO12

GPIO4

GPIO12

GPIO4

GPIO12

GPIO4

GPIO11

GPIO3

GPIO11

GPIO3

GPIO11

GPIO3

GPIO10

GPIO2

GPIO10

GPIO2

GPIO10

GPIO2

GPIO9

GPIO1

GPIO9

GPIO1

GPIO9

GPIO1

GPIO8

GPIO0

GPIO8

GPIO0

GPIO8

GPIO0

0000 0000

0xC020

0xC022

GPIO 0 Input Data

GPIO 0 Direction

GPIO15

GPIO7

R/W

GPIO15

GPIO7

Document #: 38-08014 Rev. *G

Page 73 of 78

[+] Feedback

CY7C67200

Table 42. Register Summary (continued)

R/W

Address Register

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 3

Bit 10

Bit 2

Bit 9

Bit 1

Bit 8

Default High

Default Low

0000 0000

Bit 7

Bit 6

Bit 5

Bit 4

Bit 0

0xC024

0xC026

0xC028

GPIO 1 Output Data

GPIO31

GPIO23

GPIO31

GPIO23

GPIO31

GPIO23

Reserved

GPIO30

GPIO22

GPIO30

GPIO22

GPIO30

GPIO22

GPIO29

GPIO21

GPIO29

GPIO21

GPIO29

GPIO21

Reserved

GPIO20

Reserved

GPIO20

Reserved

GPIO20

GPIO24

GPIO19

Reserved

GPIO 1 Input Data

GPIO 1 Direction

GPIO24

R/W

0xC03C USB Diagnostic

Port 2A Diag- Reserved

nostic Enable

Port 1A Diag- Reserved...

nostic Enable

...Reserved

Pull-down

Enable

LS Pull-up

Enable

FS Pull-up

Enable

Reserved

Force Select

0000 0000

R/W

0xC070

HSS Control

HSS

Enable

RTS

CTS

XOFF

Enable

CTS

Enable

Receive Inter- Done Interrupt 0000 0000

rupt Enable Enable

Polarity Select Polarity Select

TransmitDone Receive Done One

Interrupt Flag Interrupt Flag Stop Bit

Transmit

Ready

Packet

Receive

Receive Pack- Receive

0000 0000

Mode Select Overflow Flag et Ready Flag Ready Flag

R/W

0xC072

0xC074

0xC076

0xC078

HSS Baud Rate

HSS Transmit Gap

HSS Data

Reserved

...Baud

HSS Baud...

0000 0000

0001 0111

0000 0000

0000 1001

xxxx xxxx

0000 0000

Reserved

Transmit Gap Select

Reserved

Data

HSS Receive Address

Address...

...Address

Reserved

...Counter

Address..

...Address

Reserved

...Counter

Reserved

0xC07A HSS Receive Counter

0xC07C HSS Transmit Address

0xC07E HSS Transmit Counter

Counter...

0xC080

0xC0A0

Host n Control

Preamble

Enable

Sequence

Select

Sync

Enable

ISO

Enable

Reserved

Arm

Enable

R/W

0xC082

0xC0A2

Host n Address

Host n Count

Host n PID

Address...

...Address

Reserved

...Count

0000 0000

0xC084

0xC0A4

Port Select

Reserved

Count...

0xC086

0xC0A6

Reserved

Overflow

Flag

Underflow

Flag

Reserved

Stall

Flag

NAK

Flag

Length

Exception Flag

Reserved

Sequence

Status

Timeout

Flag

Error

Flag

ACK

Flag

0000 0000

0xC086

0xC0A4

Host n EP Status

Reserved

PID Select

Result...

0000 0000

xxxx 0000

Endpoint Select

0xC088

0xC0A8

Host n Count Result

Host n Device Address

...Result

0xC088

0xC0A8

Reserved...

...Reserved

Reserved

Address

R/W

0xC08A USB n Control

0xC0AA

Port A

Reserved

LOA

Mode

Reserved

D+ Status

D– Status

Select

Port A

Resistors

Enable

Reserved

Port A

Force D±

State

Suspend

Enable

Reserved

Port A

SOF/EOP

Enable

0000 0000

R/W

0xC08C Host 1 Interrupt Enable

VBUS

Interrupt

Enable

Interrupt

Enable

Reserved

SOF/EOP

Interrupt

Enable

Reserved

Port A

Wake Interrupt

Enable

Port A Con-

nect Change

Interrupt

Done

Interrupt

Enable

R/W

0xC08C Device 1 Interrupt Enable

VBUS

Reserved

SOF/EOP

Timeout Inter-

rupt Enable

Reserved

SOF/EOP

Interrupt

Enable

Reset

0000 0000

Interrupt

Enable

Interrupt

Enable

Interrupt

Enable

EP7

Interrupt

Enable

EP6

Interrupt

Enable

EP5

Interrupt

Enable

EP4

Interrupt

Enable

EP3

Interrupt

Enable

EP2

Interrupt

Enable

EP1

Interrupt

Enable

EP0

Interrupt

Enable

0xC08E Device n Address

0xC0AE

Reserved...

...Reserved

0000 0000

Address

Document #: 38-08014 Rev. *G

Page 74 of 78

[+] Feedback

CY7C67200

Table 42. Register Summary (continued)

R/W

Address Register

Bit 15

Bit 7

Bit 14

Bit 6

Bit 13

Bit 12

Bit 4

Bit 11

Bit 3

Bit 10

Bit 2

Bit 9

Bit 1

Bit 8

Default High

Default Low

xxxx xxxx

Bit 5

Bit 0

R/W

0xC090

Host 1 Status

VBUS

Interrupt

Flag

Interrupt

Flag

Reserved

SOF/EOP

Interrupt

Flag

Reserved

Port A

Reserved

Port A Con-

nect

Reserved

Port A

SE0

Reserved

Done

xxxx xxxx

Wake Interrupt

Flag

Interrupt

Flag

Change

Status

Interrupt Flag

R/W

0xC090

Device 1 Status

VBUS

Interrupt

Flag

Interrupt

Flag

SOF/EOP

Interrupt

Flag

Reset

Interrupt

Flag

xxxx xxxx

EP7

Interrupt

Flag

EP6

Interrupt

Flag

EP5

Interrupt

Flag

EP4

Interrupt

Flag

EP3

Interrupt

Flag

EP2

Interrupt

Flag

EP1

Interrupt

Flag

EP0

Interrupt

Flag

R/W

0xC092

0xC0B2

Host n SOF/EOP Count

Device n Frame Number

Reserved

...Count

Count...

0010 1110

1110 0000

0000 0000

0xC092

0xC0B2

SOF/EOP

Timeout

Flag

SOF/EOP

Reserved

Frame...

Timeout

Interrupt Count

...Frame

Reserved

...Counter

Reserved

...Count

0000 0000

0xC094

0xC0B4

Host n SOF/EOP Counter

Device n SOF/EOP Count

Host n Frame

Counter...

Count...

0xC094

0xC0B4

0xC096

0xC0B6

Reserved

...Frame

Reserved

Frame...

0000 0000

R/W

0xC0AC Host 2 Interrupt Enable

SOF/EOP

Interrupt

Enable

Reserved

Port A

Reserved

Port A Con-

nect Change

Interrupt

Reserved

SOF/EOP

Done

0000 0000

Wake Interrupt

Enable

Interrupt

Enable

R/W

0xC0AC Device 2 Interrupt Enable

Wake

SOF/EOP

Interrupt

Enable

Reset

Interrupt

Enable

0000 0000

Timeout Inter- Interrupt

rupt Enable Enable

EP7

Interrupt

Enable

EP6

Interrupt

Enable

EP5

Interrupt

Enable

EP4

Interrupt

Enable

EP3

Interrupt

Enable

EP2

Interrupt

Enable

EP1

Interrupt

Enable

EP0

Interrupt

Enable

R/W

0xC0B0 Host 2 Status

0xC0B0 Device 2 Status

Reserved

SOF/EOP

Reserved

xxxx xxxx

Interrupt Flag

Reserved

Port A

Reserved

Port A Con-

nect Change

Interrupt Flag

Reserved

Port A

SE0

Reserved

Done

Interrupt

Flag

Wake Interrupt

Flag

Status

Reserved

EP7

SOF/EOP

Timeout

Interrupt

Enable

Wake

Interrupt

Flag

SOF/EOP

Interrupt

Flag

Reset

Interrupt

Flag

xxxx xxxx

EP6

EP5

EP4

EP3

EP2

EP1

EP0

xxxx xxxx

Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag

R/W

0xC0C6 HPI Mailbox

Message...

...Message

0000 0000

1000 0000

0xC0C8 SPI Configuration

3Wire

Enable

Phase

Select

SCK

Polarity Select

Scale Select

Reserved

Master

SS Delay Select

0001 1111

0000 0001

1000 0000

Active Enable Enable

Enable

R/W

0xC0CA SPI Control

SCK

Strobe

FIFO

Init

Byte

Mode

FullDuplex

Manual

Read

Transmit

Ready

Receive

Data Ready

Enable

Transmit

Empty

Receive

Full

Transmit Bit Length

Receive Bit Length

0xC0CC SPI Interrupt Enable

Reserved...

...Reserved

0000 0000

Receive

Interrupt

Enable

Transmit

Interrupt

Enable

Transfer

Interrupt

Enable

0xC0CE SPI Status

Reserved...

0000 0000

FIFO Error

Flag

Reserved

Receive

Transmit

Transfer

Interrupt Flag Interrupt Flag Interrupt Flag

0xC0D0 SPI Interrupt Clear

Reserved...

...Reserved

0000 0000

Transmit

Interrupt Clear Interrupt Clear

R/W

0xC0D2 SPI CRC Control

0xC0D4 SPI CRC Value

CRC Mode

...Reserved

CRC..

CRC Enable CRC Clear

Receive CRC One in CRC Zero in CRC Reserved...

0000 0000

1111 1111

...CRC

Document #: 38-08014 Rev. *G

Page 75 of 78

[+] Feedback

CY7C67200

Table 42. Register Summary (continued)

R/W

Address Register

Bit 15

Bit 14

Bit 6

Bit 13

Bit 5

Bit 12

Bit 4

Bit 11

Bit 3

Bit 10

Bit 2

Bit 9

Bit 1

Bit 8

Bit 0

Default High

Default Low

xxxx xxxx

Bit 7

0xC0D6 SPI Data Port t

0xC0D8 SPI Transmit Address

0xC0DA SPI Transmit Count

0xC0DC SPI Receive Address

0xC0DE SPI Receive Count

0xC0E0 UART Control

Reserved

Data

xxxx xxxx

Address...

...Address

Reserved

...Count

0000 0000

0000 0111

Count...

Address...

...Address

Reserved

...Count

Reserved...

...Reserved

Scale

Select

Baud

Select

UART

Enable

0xC0E2 UART Status

Reserved...

...Reserved

0000 0000

Receive

Full

Transmit

Full

R/W

0xC0E4 UART Data

HPI Status Port

Reserved

Data

0000 0000

VBUS

Flag

Reserved

SIE2msg

SOF/EOP2

Flag

Reserved

SOF/EOP1

Flag

Reset2

Flag

Mailbox In

Flag

Resume2

Flag

Resume1

Flag

SIE1msg

Done2

Flag

Done1

Flag

Reset1

Flag

Mailbox Out

Flag

Document #: 38-08014 Rev. *G

Page 76 of 78

[+] Feedback

CY7C67200

Ordering Information

Table 43.Ordering Information

Ordering Code

CY7C67200-48BAXI

CY7C67200-BAXIT

CY3663

Package Type

PB-Free

Temperature Range

48FBGA

–40 to 85°C

48FBGA, Tape and reel

Development Kit

Package Diagram

48-Ball (7.00 mm x 7.00 mm x 1.2 mm) FBGA BA48

BOTTOM VIEW

Ø0.05 M C

TOP VIEW

PIN 1 CORNER

(LASER MARK)

Ø0.25 M C A B

Ø0.30 0.05(48X)

1.875

0.75

3.75

7.00 0.10

0.15(4X)

51-85096-*F

SEATING PLANE

1.20 MAX.

Purchase of I²C™ components from Cypress, or one of its sublicensed Associated Companies, conveys a license under the

Philips I²C Patent Rights to use these components in an I²C system, provided that the system conforms to the I²C Standard

Specification as defined by Philips. EZ-OTG is a trademark of Cypress Semiconductor. All product and company names mentioned

in this document are trademarks of their respective holders.

Document #: 38-08014 Rev. *G

Page 77 of 78

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

[+] Feedback

CY7C67200

Document History Page

Document Title: CY7C67200 EZ-OTG™ Programmable USB On-The-Go Host/Peripheral Controller

Document Number: 38-08014

Issue

Date

Orig. of

Change

REV.

ECN NO.

Description of Change

111872

116988

124954

03/22/02

08/23/02

04/10/03

MUL

New Data Sheet

Preliminary Data Sheet

Added Memory Map Section and Ordering Information Section

Moved Functional Register Map Tables into Register section

General Clean-up

Changed from “Preliminary“ to “Preliminary Confidential“

126211

05/23/03

MUL

Added Interface Description Section and Power Savings and Reset Section

Added Char Data

General Clean-up

Removed DRAM, MDMA, and EPP

Added “Programmable” to the title page

127334

129394

05/29/03

10/07/03

KKV

MUL

Corrected font to enable correct symbol display

Final Data Sheet

Changed Memory Map Section

Added USB OTG Logo

General Clean-up

472875

See ECN

ARI

Removed “power consumption” bullet from the Features bullet list.

Corrected number GPIO[31:20] to read GPIO[31:30] in Section “Standalone

Mode”.

Made sentence into a Note in Section “Reset Pin” and repeated the note in

Section “Host Port Interface (HPI)”.

Corrected the Host/Device 1 Interrupt Enable (Bit 8) Information in Section

“Interrupt Enable Register [0xC00E] [R/W]”.

Corrected data on Write Protect Enable (Bit 15) Section “GPIO Control

only until a chip reset“.

Re-wrote the Register Description in Section “SIEXmsg Register [W]”.

Put document on 2-column template and corrected grammar. Put the figure

captions at the top of the figures per new template specifications.

Added Static Discharge Voltage information in Section “Absolute Maximum

Ratings”

Added compliance statement and TID in Section “USB Transceiver”.

567317

See ECN KKVTMP Added the lead free information on the Ordering Information Section. Imple-

mented the new template with no numbers on the headings.

Document #: 38-08014 Rev. *G

Page 78 of 78

[+] Feedback

Lumens Technology Computer Drive DC190 User Manual
LG Electronics New Chocolate BL40 User Manual
LaCie Little Disk User Manual
Krell Industries CD Player User Manual
Keurig B200 User Manual
Huawei U8800 51 User Manual
Bloomfield 2212 User Manual
Black & Decker DLX850 User Manual
Alpine CDA W560EG User Manual
Addonics Technologies JUPITER CIPHER EXDRIVE JCEDIF64 User Manual