PowerPC™ 405 Processor
Block Reference Guide
Embedded Development Kit
UG018 (v2.0) August 20, 2004
R
Download from Www.Somanuals.com. All Manuals Search And Download.
PowerPC™ 405 Processor Block Reference Guide
UG018 (v2.0) August 20, 2004
The following table shows the revision history for this document.
Version
1.0
Revision
09/ 16/ 02
09/ 02/ 03
04/ 26/ 04
06/ 15/ 04
08/ 20/ 04
Initial Embedded Development Kit (EDK) release.
Updated for EDK 6.1 release
1.1
DRAFT
DRAFT
2.0
Early Access release (DRAFT).
Second Early Access release (DRAFT).
Updated to include Virtex-4 functionality.
UG018 (v2.0) August 20, 2004
PowerPC™ 405 Processor Block Reference Guide
1-800-255-7778
Download from Www.Somanuals.com. All Manuals Search And Download.
PowerPC™ 405 Processor Block Reference Guide
1-800-255-7778
UG018 (v2.0) August 20, 2004
Download from Www.Somanuals.com. All Manuals Search And Download.
Table of Contents
Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Typographical. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
General Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
PowerPC Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
PowerPC Embedded-Environment Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
PowerPC 405 Software Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Privilege Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Address Translation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Register Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
PowerPC 405 Hardware Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Central-Processing Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Exception Handling Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Memory Management Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Instruction and Data Caches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Timer Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
PowerPC 405 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
PowerPC 405 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Signal Naming Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Clock and Power Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
CPM Interface I/ O Signal Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
CPM Interface I/ O Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
System Design Considerations for Clock Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
CPU Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
CPU Control Interface I/ O Signal Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
CPU Control Interface I/ O Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Reset Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Reset Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Reset Interface I/ O Signal Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Reset Interface I/ O Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Instruction-Side Processor Local Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
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Instruction-Side PLB Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Instruction-Side PLB I/ O Signal Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Instruction-Side PLB Interface I/ O Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . 51
Instruction-Side PLB Interface Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Data-Side Processor Local Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Data-Side PLB Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Data-Side PLB Interface I/ O Signal Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Data-Side PLB Interface I/ O Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Data-Side PLB Interface Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Device-Control Register Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Internal Device Control Register (DCR) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Virtex-II Pro and Virtex-II ProX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Virtex-4-FX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
External DCR Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
External DCR Bus Interface I/ O Signal Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
External DCR Bus Interface I/ O Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . 105
External DCR Bus Interface Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
External Interrupt Controller Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
EIC Interface I/ O Signal Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
EIC Interface I/ O Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
PPC405 JTAG Debug Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
JTAG Interface I/ O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
JTAG Interface I/ O Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
JTAG Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
VHDL and Verilog Instantiation Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Debug Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Debug Interface I/ O Signal Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Debug Interface I/ O Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Trace Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Trace Interface Signal Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Trace Interface I/ O Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
PVR Interface I/ O Signal Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
PVR Interface I/ O Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Additional FPGA Specific Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Additional FPGA I/ O Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Functional Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Common Features for DSOCM and ISOCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Features for Data-Side OCM (DSOCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Features for Instruction-Side OCM (ISOCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
OCM Controller Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
DSOCM Controller Load/ Store Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
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ISOCM Controller Instruction Fetch Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
DSOCM Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
ISOCM Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Programmer’s Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
DCR Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
DSARC/ ISARC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
DSCNTL Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
ISCNTL Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
DCR Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
DCR Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Single-Cycle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Multi-Cycle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
ISOCM Instruction Fetching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Writing to ISBRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
DSOCM Data Load, Fixed Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
DSOCM Store, Fixed Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
DSOCM Data Load, Variable Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
DSOCM Data Store, Variable Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Application Notes and Reference Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
FCM Instruction Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Enabling the APU Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Instruction Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Instruction Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
APU Controller Pre-Defined Instruction Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
APU Controller User-Defined Instruction Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . 189
FCM Pre-Defined Instruction Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
FCM User-Defined Instruction Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
FCM Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
FCM Instruction Flushing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Execution Hazards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
APU Controller Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
General Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
UDI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
DCR Access to the Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Interface Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
APU Controller Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
APU Controller Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
APU Controller Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
FCM Interface Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Autonomous Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Blocking Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Non-Blocking Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
FCM Load Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
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FCM Store Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
FCM Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
FCM Decoding Using Decode Busy Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
RISCWatch Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
RISCTrace Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Timing Parameter Tables and Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
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Preface
About This Guide
This guide serves as a technical reference describing the hardware interface to the
PowerPC® 405 processor block. It contains information on input/ output signals, timing
relationships between signals, and the mechanisms software can use to control the
interface operation. The document is intended for use by FPGA and system hardware
designers and by system programmers who need to understand how certain operations
affect hardware external to the processor.
Guide Contents
This manual contains the following chapters:
x
x
x
PowerPC embedded-environment architecture and the features supported by the
PowerPC 405.
the PowerPC 405 processor block. Where appropriate, timing diagrams are provided
to assist in understanding the functional relationship between multiple signals.
timing specifications, and programming model for the PowerPC 405 on-chip memory
(OCM) controller. The OCM controller serves as a dedicated interface between the
block RAMs in the FPGA and OCM signals available on the embedded PowerPC 405
core.
x
x
controller, which allows the designer to extend the native PowerPC 405 instruction set
with custom instructions that are executed by an FPGA Fabric Co-processor Module
(FCM). The APU controller is available only for Virtex-4 family devices.
requirements between the PowerPC 405 processor block and the RISCWatch and
RISCTrace tools.
x
x
order.
associated with the IBM PPC405 Processor Block.
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Preface: About This Guide
Additional Resources
some of the resources you can access from this website. You can also directly access these
resources using the provided URLs.
Resource
Tutorials
Description/URL
Tutorials covering Xilinx design flows, from design entry to
verification and debugging
Answer Browser
Database of Xilinx solution records
Application Notes Descriptions of device-specific design techniques and approaches
Data Sheets
Device-specific information on Xilinx device characteristics,
including readback, boundary scan, configuration, length count,
and debugging
Problem Solvers
Tech Tips
Interactive tools that allow you to troubleshoot your design issues
Latest news, design tips, and patch information for the Xilinx
design environment
The following documents contain additional information of potential interest to readers of
this manual:
x
x
XILINX PowerPC Processor Reference Guide
XILINX Virtex-II Pro Platform FPGA Handbook
Conventions
This document uses the following conventions. An example illustrates each convention.
Typographical
The following typographical conventions are used in this document:
Convention
Meaning or Use
Example
Messages, prompts, and
Courier font
program files that the system speed grade: - 100
displays
Literal commands that you
ngdbuild design_name
enter in a syntactical statement
Courier bold
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Convention
Meaning or Use
Example
File o Open
Ctrl+C
Commands that you select
from a menu
Helvetica bold
Keyboard shortcuts
Variables in a syntax
statement for which you must ngdbuild design_name
supply values
See the Development System
Italic font
References to other manuals
Emphasis in text
Reference Guide for more
information.
If a wire is drawn so that it
overlaps the pin of a symbol,
the two nets are not connected.
An optional entry or
parameter. However, in bus
specifications, such as
bus[7:0], they are required.
ngdbuild [option_name]
design_name
Square brackets [ ]
Braces { }
A list of items from which you
must choose one or more
lowpwr ={on|off}
lowpwr ={on|off}
Separates items in a list of
choices
Vertical bar
|
IOB #1: Name = QOUT’
IOB #2: Name = CLKIN’
.
.
.
Vertical ellipsis
.
.
.
Repetitive material that has
been omitted
Repetitive material that has
been omitted
allow block block_name
loc1 loc2 ... locn;
Horizontal ellipsis . . .
Online Document
The following conventions are used in this document:
Convention
Meaning or Use
Example
See the section “Additional
Resources” for details.
Cross-reference link to a
location in the current
document
Blue text
Refer to “Title Formats” in
Chapter 1 for details.
Reference to a location in
another document
See Figure 2-5 in the Virtex-II
Handbook.
Red text
Go to http:/ / www.xilinx.com
for the latest speed files.
Blue, underlined text
Hyperlink to a website (URL)
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Preface: About This Guide
General Conventions
Table 1-1 lists the general notational conventions used throughout this document.
Table 1-1: General Notational Conventions
Convention
Definition
mnemonic
variable
ActiveLow
n
Instruction mnemonics are shown in lower-case bold.
Variable items are shown in italic.
An overbar indicates an active-low signal.
A decimal number
0xn
A hexadecimal number
0bn
A binary number
OBJECTb
A single bit in any object (a register, an instruction, an
address, or a field) is shown as a subscripted number or
name
OBJECTb:b
A range of bits in any object (a register, an instruction,
an address, or a field)
OBJECTb,b, . . .
A list of bits in any object (a register, an instruction, an
address, or a field)
REGISTER[FIELD]
Fields within any register are shown in square brackets
A list of fields in any register
REGISTER[FIELD, FIELD . . .
REGISTER[FIELD:FIELD]
]
A range of fields in any register
Registers
Table 1-2 lists the PowerPC 405 registers used in this document and their descriptive
names.
Table 1-2: PowerPC 405 Registers
Register
CCR0
Descriptive Name
Core-configuration register 0
DBCRn
DBSR
ESR
Debug-control register n
Debug-status register
Exception-syndrome register
Machine-state register
Programmable-interval timer
Time-base lower
MSR
PIT
TBL
TBU
Time-base upper
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Table 1-2: PowerPC 405 Registers (Continued)
Register Descriptive Name
TCR
Timer-control register
Timer-status register
TSR
Terms
active
As applied to signals, this term indicates a signal is in a state
that causes an action to occur in the receiving device, or
indicates an action occurred in the sending device. An active-
high signal drives a logic 1 when active. An active-low signal
drives a logic 0 when active.
assert
As applied to signals, this term indicates a signal is driven to its
active state.
atomic access
A memory access that attempts to read from and write to the
same address uninterrupted by other accesses to that address.
The term refers to the fact that such transactions are indivisible.
big endian
Book-E
A memory byte ordering where the address of an item
corresponds to the most-significant byte.
An version of the PowerPC architecture designed specifically
for embedded applications.
cache block
cache line
Synonym for cache line.
A portion of a cache array that contains a copy of contiguous
system-memory addresses. Cache lines are 32-bytes long and
aligned on a 32-byte address.
cache set
clear
Synonym for congruence class.
To write a bit value of 0.
clock
Unless otherwise specified, this term refers to the PowerPC 405
processor clock.
congruence class
cycle
A collection of cache lines with the same index.
The time between two successive rising edges of the associated
clock.
dead cycle
deassert
dirty
A cycle in which no useful activity occurs on the associated
interface.
As applied to signals, this term indicates a signal is driven to its
inactive state.
An indication that cache information is more recent than the
copy in memory.
doubleword
Eight bytes, or 64 bits.
effective address
The untranslated memory address as seen by a program.
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Preface: About This Guide
exception
An abnormal event or condition that requires the processor’s
attention. They can be caused by instruction execution or an
external device. The processor records the occurrence of an
exception and they often cause an interrupt to occur.
fill buffer
flush
A buffer that receives and sends data and instructions between
the processor and PLB. It is used when cache misses occur and
when access to non-cacheable memory occurs.
A cache operation that involves writing back a modified entry
to memory, followed by an invalidation of the entry.
GB
Gigabyte, or one-billion bytes.
Two bytes, or 16 bits.
halfword
hit
An indication that requested information exists in the accessed
cache array, the associated fill buffer, or on the corresponding
OCM interface.
inactive
As applied to signals, this term indicates a signal is in a state
that does not cause an action to occur, nor does it indicate an
action occurred. An active-high signal drives a logic 0 when
inactive. An active-low signal drives a logic 1 when inactive.
interrupt
The process of stopping the currently executing program so that
an exception can be handled.
invalidate
A cache or TLB operation that causes an entry to be marked as
invalid. An invalid entry can be subsequently replaced.
KB
Kilobyte, or one-thousand bytes.
line buffer
A buffer located in the cache array that can temporarily hold the
contents of an entire cache line. It is loaded with the contents of
a cache line when a cache hit occurs.
line fill
A transfer of the contents of the instruction or data line buffer
into the appropriate cache.
line transfer
A transfer of an aligned, sequentially addressed 4-word or 8-
word quantity (instructions or data) across the PLB interface.
The transfer can be from the PLB slave (read) or to the PLB slave
(write).
little endian
A memory byte ordering where the address of an item
corresponds to the least-significant byte.
logical address
MB
Synonym for effective address.
Megabyte, or one-million bytes.
memory
miss
Collectively, cache memory and system memory.
An indication that requested information does not exist in the
accessed cache array, the associated fill buffer, or on the
corresponding OCM interface.
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OEA
The PowerPC operating-environment architecture, which
defines the memory-management model, supervisor-level
registers and instructions, synchronization requirements, the
exception model, and the time-base resources as seen by
supervisor programs.
on chip
In system-on-chip implementations, this indicates on the same
FPGA chip as the processor core, but external to the processor
core.
pending
As applied to interrupts, this indicates that an exception
occurred, but the interrupt is disabled. The interrupt occurs
when it is later enabled.
physical address
The address used to access physically-implemented memory.
This address can be translated from the effective address. When
address translation is not used, this address is equal to the
effective address.
PLB
Processor local bus.
privileged mode
The operating mode typically used by system software.
Privileged operations are allowed and software can access all
registers and memory.
problem state
process
Synonym for user mode.
A program (or portion of a program) and any data required for
the program to run.
real address
scalar
Synonym for physical address.
Individual data objects and instructions. Scalars are of arbitrary
size.
set
To write a bit value of 1.
sleep
A state in which the PowerPC 405 processor clock is prevented
from toggling. The execution state of the PowerPC 405 does not
change when in the sleep state.
sticky
A bit that can be set by software, but cleared only by the
processor. Alternatively, a bit that can be cleared by software,
but set only by the processor.
string
A sequence of consecutive bytes.
supervisor state
system memory
Synonym for privileged mode.
Physical memory installed in a computer system external to the
processor core, such RAM, ROM, and flash.
tag
As applied to caches, a set of address bits used to uniquely
identify a specific cache line within a congruence class. As
applied to TLBs, a set of address bits used to uniquely identify
a specific entry within the TLB.
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Preface: About This Guide
UISA
The PowerPC user instruction-set architecture, which defines
the base user-level instruction set, registers, data types, the
memory model, the programming model, and the exception
model as seen by user programs.
user mode
VEA
The operating mode typically used by application software.
Privileged operations are not allowed in user mode, and
software can access a restricted set of registers and memory.
The PowerPC virtual-environment architecture, which defines
a multi-access memory model, the cache model, cache-control
instructions, and the time-base resources as seen by user
programs.
virtual address
An intermediate address used to translate an effective address
into a physical address. It consists of a process ID and the
effective address. It is only used when address translation is
enabled.
wake up
word
The transition of the PowerPC 405 out of the sleep state. The
PowerPC 405 processor clock begins toggling and the execution
state of the PowerPC 405 advances from that of the sleep state.
Four bytes, or 32 bits.
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Chapter 1
Introduction to the
PowerPC 405 Processor
The PowerPC 405 is a 32-bit implementation of the PowerPC embedded-environment
architecture that is derived from the PowerPC architecture. Specifically, the PowerPC 405 is
an embedded PowerPC 405D5 (for Virtex-II Pro) or 405F6 (for Virtex-4) processor core. The
term processor block is used throughout this document to refer to the combination of a
PPC405D5 or PPC405F6 core, on-chip memory logic (OCM), an APU controller (Virtex-4
only), and the gasket logic and interface.
The PowerPC architecture provides a software model that ensures compatibility between
implementations of the PowerPC family of microprocessors. The PowerPC architecture
defines parameters that guarantee compatible processor implementations at the
application-program level, allowing broad flexibility in the development of derivative
PowerPC implementations that meet specific market requirements.
This chapter provides an overview of the PowerPC architecture and an introduction to the
features of the PowerPC 405 core. The following topics are included:
x
x
x
x
PowerPC Architecture
The PowerPC architecture is a 64-bit architecture with a 32-bit subset. The various features
of the PowerPC architecture are defined at three levels. This layering provides flexibility
by allowing degrees of software compatibility across a wide range of implementations. For
example, an implementation such as an embedded controller can support the user
instruction set, but not the memory management, exception, and cache models where it
might be impractical to do so.
The three levels of the PowerPC architecture are defined in Table 1-1.
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Chapter 1: Introduction to the PowerPC 405 Processor
Table 1-1: Three Levels of PowerPC Architecture
User Instruction-Set Architecture Virtual Environment Architecture
Operating Environment
Architecture (OEA)
(UISA)
(VEA)
x Defines the architecture level to
which user-level (sometimes
referred to as problem state)
software should conform
x Defines additional user-level
functionality that falls outside
typical user-level software
requirements
x Defines supervisor-level
resources typically required by
an operating system
x Defines the memory-
management model, supervisor-
level registers, synchronization
requirements, and the exception
model
x Defines the base user-level
instruction set, user-level
x Describes the memory model for
an environment in which
multiple devices can access
memory
registers, data types, floating-
point memory conventions,
exception model as seen by user
programs, memory model, and
the programming model
x Defines aspects of the cache
model and cache-control
instructions
x Defines the time-base resources
from a supervisor-level
perspective
x Defines the time-base resources
from a user-level perspective
x
Note: All PowerPC implementations
adhere to the UISA.
Note: Implementations that conform to Note: Implementations that conform to
the VEA level are guaranteed to conform the OEA level are guaranteed to conform
to the UISA level.
to the UISA and VEA levels.
The PowerPC architecture requires that all PowerPC implementations adhere to the UISA,
offering compatibility among all PowerPC application programs. However, different
versions of the VEA and OEA are permitted.
Embedded applications written for the PowerPC 405 are compatible with other PowerPC
implementations. Privileged software generally is not compatible. The migration of
privileged software from the PowerPC architecture to the PowerPC 405 is in many cases
straightforward because of the simplifications made by the PowerPC embedded-
environment architecture. Refer to the PowerPC Processor Reference Guide for more
information on programming the PowerPC 405.
PowerPC Embedded-Environment Architecture
The PowerPC 405 is an implementation of the PowerPC embedded-environment
architecture. This architecture is optimized for embedded controllers and is a forerunner to
the PowerPC Book-E architecture. The PowerPC embedded-environment architecture
provides an alternative definition for certain features specified by the PowerPC VEA and
OEA. Implementations that adhere to the PowerPC embedded-environment architecture
also adhere to the PowerPC UISA. PowerPC embedded-environment processors are 32-bit
only implementations and thus do not include the special 64-bit extensions to the PowerPC
UISA. Also, floating-point support can be provided either in hardware or software by
PowerPC embedded-environment processors.
The following are features of the PowerPC embedded-environment architecture:
x
x
Memory management optimized for embedded software environments.
Cache-management instructions for optimizing performance and memory control in
complex applications that are graphically and numerically intensive.
x
Storage attributes for controlling memory-system behavior.
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x
x
Special-purpose registers for controlling the use of debug resources, timer resources,
interrupts, real-mode storage attributes, memory-management facilities, and other
architected processor resources.
A device-control-register address space for managing on-chip peripherals such as
memory controllers.
x
x
x
A dual-level interrupt structure and interrupt-control instructions.
Multiple timer resources.
Debug resources that enable hardware-debug and software-debug functions such as
instruction breakpoints, data breakpoints, and program single-stepping.
Virtual Environment
The virtual environment defines architectural features that enable application programs to
create or modify code, to manage storage coherency, and to optimize memory-access
performance. It defines the cache and memory models, the timekeeping resources from a
user perspective, and resources that are accessible in user mode but are primarily used by
system-library routines. The following summarizes the virtual-environment features of the
PowerPC embedded-environment architecture:
x
Storage model:
i
Storage-control instructions as defined in the PowerPC virtual-environment
architecture. These instructions are used to manage instruction caches and data
caches, and for synchronizing and ordering instruction execution.
i
i
Storage attributes for controlling memory-system behavior. These are: write-
through, cacheability, memory coherence (optional), guarded, and endian.
Operand-placement requirements and their effect on performance.
x
The time-base function as defined by the PowerPC virtual-environment architecture,
for user-mode read access to the 64-bit time base.
Operating Environment
The operating environment describes features of the architecture that enable operating
systems to allocate and manage storage, to handle errors encountered by application
programs, to support I/ O devices, and to provide operating-system services. It specifies
the resources and mechanisms that require privileged access, including the memory-
protection and address-translation mechanisms, the exception-handling model, and
privileged timer resources. Table 1-2 summarizes the operating-environment features of
the PowerPC embedded-environment architecture.
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Chapter 1: Introduction to the PowerPC 405 Processor
Table 1-2: OEA Features of the PowerPC Embedded-Environment Architecture
Operating
Environment
Features
Register model
x Privileged special-purpose registers (SPRs) and instructions for accessing those
registers
x Device control registers (DCRs) and instructions for accessing those registers
Storage model
x Privileged cache-management instructions
x Storage-attribute controls
x Address translation and memory protection
x Privileged TLB-management instructions
Exception model
x Dual-level interrupt structure supporting various exception types
x Specification of interrupt priorities and masking
x Privileged SPRs for controlling and handling exceptions
x Interrupt-control instructions
x Specification of how partially executed instructions are handled when an interrupt
occurs
Debug model
x Privileged SPRs for controlling debug modes and debug events
x Specification for seven types of debug events
x Specification for allowing a debug event to cause a reset
x The ability of the debug mechanism to freeze the timer resources
Time-keeping model
x 64-bit time base
x 32-bit decrementer (the programmable-interval timer)
x Three timer-event interrupts:
i Programmable-interval timer (PIT)
i Fixed-interval timer (FIT)
i Watchdog timer (WDT)
x Privileged SPRs for controlling the timer resources
x The ability to freeze the timer resources using the debug mechanism
x
Requirements for special registers and the TLB
Synchronization
requirements
x
x
Requirements for instruction fetch and for data access
Specifications for context synchronization and execution synchronization
Reset and initialization x Specification for two internal mechanisms that can cause a reset:
requirements
i Debug-control register (DBCR)
i Timer-control register (TCR)
x Contents of processor resources after a reset
x The software-initialization requirements, including an initialization code example
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