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BL ChipScope PLBv46 IBA (Bus Analyzer) (v1.00a)
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DS619 (v1.0) September 17, 2007
Product Specification
Introduction
LogiCORE™ Facts
The ChipScope™ PLB IBA core is a specialized Bus
Analyzer core designed to debug embedded systems that
contain the IBM CoreConnect™ Processor Local Bus (PLB)
version 4.6. The ChipScope PLB46 IBA core in EDK is
based on a Tcl script that generates an HDL wrapper to the
PLB IBA and calls the ChipScope Core Generator to
generate the netlist based on user parameters.
Core Specifics
Supported Device Virtex-E, Virtex, Spartan™-3A DSP,
Family
Spartan-3AN, Spartan-3A, Spartan-3E,
Spartan-3, Spartan-IIE, Spartan-II, Virtex-5
LX, Virtex-5 LXT Virtex-5 SXT, Virtex-4 FX,
Virtex-4 LX, Virtex-4 SX, Virtex-II Pro,
Virtex-II, Virtex-II Pro, Virtex-4
Version of Core
chipscope_plb46_iba V1.00a
Resources Used
Features
Min
Max
Slices
The ChipScope PLBv46 IBA is a soft IP core designed for
Xilinx® FPGAs and contains the following features:
LUTs
•
Probes the master, slave, arbiter, and error status
signals of the PLBv46 bus
FFs
Block RAMs
•
•
•
Probes the PLBv46 OR'ed slave signals
Provided with Core
Product Specification
VHDL/EDIF
Automatically adjusts ports to the PLBv46 bus width
Documentation
Separates master, slave, and error status signals into
independent match units which can be enabled or
disabled by a design parameter
Design File
Formats
Constraints File
Verification
N/A
N/A
N/A
•
•
•
•
•
•
•
Allows independent enabling or disabling of probed
master, slave, and error status signals for data capture
Instantiation
Template
Supports trigger port customization by a design
parameter
Reference Designs None
Design Tool Requirements
Supports match unit type customization for each trigger
port by a design parameter
Xilinx
Implementation
Tools
ISE™ 9.2i or later
Supports sample depths from 1024-131,072 on
Virtex™-5 Devices selectable by a design parameter
Can probe as few as 1 signals and as many as 1115
signals on a Virtex-5 device
Verification
Simulation
Synthesis
ChipScope Pro 9.2i or later
Not supported in simulation
XST
Provides a separate input bus to allow a user-defined
input debug port
Support
Supports a trigger output indicator pin that can be sent
off chip or to other cores
Provided by Xilinx, Inc.
© 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
PowerPC is a trademark of IBM, Inc. All other trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS619 (v1.0) September 17, 2007
Product Specification
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ChipScope PLBv46 IBA (Bus Analyzer) (v1.00a)
Table 1: IBA_PLBv46 Pin Descriptions (Continued)
Port
P34
MU
Signal Name
Interface
Slave
I/O
Description
PLB Transfer Attribute
MU_2C PLB_TAttribute[0:15]
I
Address
Slave
P35
P36
MU_3A PLB_ABus[0:31]
MU_3B PLB_UABus[0:31]
I
I
PLB address bus, lower 32 bits
PLB address bus, upper 32 bits
Slave
Data
P37
P38
MU_4
MU_5
PLB_wrDBus[0: C_PLBV46_DWIDTH-1] Slave
I
I
PLB write data bus
PLB_SrdDBus[0:
Sim
Output of SL_rdDBus OR gate
C_PLBV46_DWIDTH-1]
Slave
P39
P40
P41
P42
MU_6A PLB_rdPrim[0:
C_PLBV46_NUM_SLAVES-1]
Slave
I
I
I
I
PLB secondary to primary read request
indicator
MU_6A PLB_wrPrim[0:
C_PLBV46_NUM_SLAVES-1]
Slave
Slave
Slave
PLB secondary to primary write request
indicator
MU_6A Sl_AddrAck[0:
C_PLBV46_NUM_SLAVES-1]
Slave Address acknowledge
MU_6A Sl_Rearbitrate[0:
C_PLBV46_NUM_SLAVES-1]
Slave bus re-arbitrate indicator
P43
P44
MU_6A Sl_wait[0: C_PLBV46_NUM_SLAVES-1] Slave
I
I
Slave wait indicator
MU_6A Sl_rdBTerm[0:
C_PLBV46_NUM_SLAVES -1]
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave terminate read burst indicator
P45
P46
P47
P48
P49
P50
P51
P52
P53
MU_6A Sl_rdComp[0:
C_PLBV46_NUM_SLAVES -1]
I
I
I
I
I
I
I
I
I
Slave read transfer complete indicator
Slave read data acknowledge
Slave terminate write burst indicator
Slave write transfer complete indicator
Slave write data acknowledge
Slave read word address
MU_6A Sl_rdDAck[0:
C_PLBV46_NUM_SLAVES-1]
MU_6A Sl_wrBTerm[0:
C_PLBV46_NUM_SLAVES -1]
MU_6A Sl_wrComp[0:
C_PLBV46_NUM_SLAVES -1]
MU_6A Sl_wrDAck[0:
C_PLBV46_NUM_SLAVES-1]
MU_6B Sl_rdWdAddr[0:
C_PLBV46_NUM_SLAVES*4-1]
MU_6B Sl_SSize[0:
C_PLBV46_NUM_SLAVES*2-1]
Slave data bus port size indicator
Slave busy indicator
MU_7
Sl_MBusy[0: C_PLBV46_NUM_SLAVES Slave
*C_PLBV46_NUM_MASTERS-1]
MU_8
Sl_MRdErr[0:
C_PLBV46_NUM_SLAVES
*C_PLBV46_NUM_MASTERS-1]
Slave
Slave read error indicator
P54
MU_9
Sl_MWrErr[0:
C_PLBV46_NUM_SLAVES
*C_PLBV46_NUM_MASTERS-1]
Slave
I
Slave write error indicator
PLB Arbitration Signals
P55
P56
P57
MU_10 M_request[0:
C_PLBV46_NUM_MASTERS-1]
Master
I
I
I
Master bus request
Master bus request priority
Master Bus Lock
MU_10 M_priority[0:
Master
C_PLBV46_NUM_MASTERS*2-1]
MU_10 M_busLock[0:
Master
C_PLBV46_NUM_MASTERS-1]
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ChipScope PLBv46 IBA (Bus Analyzer) (v1.00a)
Table 1: IBA_PLBv46 Pin Descriptions (Continued)
Port
P58
MU
Signal Name
Interface
Master
I/O
Description
MU_10 M_abort[0:
I
Master abort bus request indicator
C_PLBV46_NUM_MASTERS-1]
P59
P60
P61
P62
P63
MU_10 PLB_rdPendPri[0:1]
Master
Master
I
I
PLB pending read request priority
PLB pending write request priority
PLB pending bus read request indicator
PLB pending bus write request indicator
PLB current request priority
MU_10 PLB_wrPendPri[0:1]
MU_10 PLB_rdPendReq
MU_10 PLB_wrPendReq
MU_10 PLB_reqPri[0:1]
Master /Slave I
Master /Slave I
Master /Slave I
PLB Master Signals
P64
P65
P66
P67
P68
P69
P70
P71
P72
P73
P74
P75
P76
P77
P78
P79
MU_11 M_lockErr[0:
Master
Master
Master
Master
Master
Master
Master
Master
Master
Master
Master
Master
Master
Master
Master
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Master lock error indicator
C_PLBV46_NUM_MASTERS-1]
MU_11 M_rdBurst[0:
C_PLBV46_NUM_MASTERS-1]
Master read burst indicator
MU_11 M_wrBurst[0:
C_PLBV46_NUM_MASTERS-1]
Master write burst indicator
MU_11 M_RNW[0:
C_PLBV46_NUM_MASTERS-1]
Master read not write
MU_11 PLB_MBusy[0:
C_PLBV46_NUM_MASTERS-1]
PLB Master slave busy indicator
PLB Master Address acknowledge
PLB Master terminate read burst indicator
PLB Master read data acknowledge
PLB Master bus re-arbitrate indicator
PLB Master terminate write burst indicator
PLB Master write data acknowledge
Master data bus port width
MU_11 PLB_MAddrAck[0:
C_PLBV46_NUM_MASTERS-1]
MU_11 PLB_MRdBTerm[0:
C_PLBV46_NUM_MASTERS-1]
MU_11 PLB_MRdDAck[0:
C_PLBV46_NUM_MASTERS-1]
MU_11 PLB_MRearbitrate[0:
C_PLBV46_NUM_MASTERS-1]
MU_11 PLB_MWrBTerm[0:
C_PLBV46_NUM_MASTERS-1]
MU_11 PLB_MWrDAck[0:
C_PLBV46_NUM_MASTERS-1]
MU_12 M_mSize[0:
C_PLBV46_NUM_MASTERS*2-1]
MU_12 M_size[0:
C_PLBV46_NUM_MASTERS*4-1]
Master transfer size
MU_12 PLB_MSSize[0:
C_PLBV46_NUM_MASTERS*2-1]
PLB Master slave data bus width indicator
Master transfer type
MU_12 M_type[0:
C_PLBV46_NUM_MASTERS*3-1]
MU_13 M_BE[0: C_PLBV46_NUM_MASTERS* Master
C_PLBV46_DWIDTH/8-1]
Master byte enables
PLBv46 bus. The core divides related ports into 13 match
unit groups (MUs) as shown in the second column of the
table. Each match unit group can connect to a trigger port of
the IBA. Certain match unit groups, such as MU_1, are
further subdivided to allow more fine control of the signals
attached to a trigger port. For example, PLB_Rst is part of
MU_1A and PLB_MRdErr is part of MU_1B but both will be
combined into MU_1 when enabled.
Every match unit label has a match type and match counter
width parameter. The match unit type describes the type of
compare operation that can be done with the match unit.
The valid values for this type are defined for each match
unit. For instance C_MU_1_TYPE only supports basic and
basic with edges because multiple signals make up this
match unit bus; whereas for C_MU_3_TYPE, all compare
options are available because this match unit has only one
connected signal bus type. The match counter width allows
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ChipScope PLBv46 IBA (Bus Analyzer) (v1.00a)
a user to look for multiple occurrences of the match event.
This counter width is controllable through the
enabled and defined with unique C_MU_xx_TYPE pattern
match units.
C_MU_xx_CNT_W parameter (xx is a place holder for
1-13). When this parameter is set to 0 only 1 occurrence is
counted, otherwise the match event count is limited by the
width of this parameter.
The 6a and 6b match units are used for the slave side
interface. This match unit holds all the control and status
ports of all the slaves on the PLB. Similarly, match units 11,
12 and 13 have all the control and status of all the masters.
The number of match units to use is defined by the
C_MU_xx_NUM parameter. By default if a match unit does
not have the C_MU_xx_NUM parameter then only one
match unit is used for the match group. If the
C_MU_xx_NUM parameter is defined, then one or two
match units are available for this match group. What this
enables is looking at sequences of this particular match
group. For instance in match group 2 you may want a trigger
sequence to first look at PLB_PAValid=1 followed by a rising
edge on PLB_SaddrAck. For this specific trigger the first
match unit is set to look for PLB_PAValid=1 and the second
is set for PLB_SaddrAck=R.
Note: When these match units are enabled, all slaves or masters
are enabled. You cannot individually enable a particular master.
The match units 7, 8, and 9 are slave side signals for BUSY,
READ, and WRITE error controls going to the master.
These units are broken out individually because this bus
has one signal for each master on each slave.
Consequently, you can have up to 256 signals on each one
of these match units (if PLB goes to a 16 slave, 16 master
solution).
The arbiter status signals can be monitored using match
unit 10. The signals probed by this match unit can help
identify the order of the PLB master transactions that are
being sorted on the bus.
The first match unit is labeled 1a and 1b. The 1a group of
signals makes up the reset and error flag signals. The 1b
group contains master related error signals. The generator
allows adding 1a, 1b or both of these groups to the core via
the generic parameters C_USE_MU_1A, and
ChipScope PLB46 IBA Parameters
C_USE_MU_1B respectively.
To create a ChipScope PLB46 IBA uniquely tailored for your
system and to optimize performance, specific features can
be parameterized on the PLB IBA. Table 2 describes the
features that can be parameterized.
The second match unit has labels 2a, 2b, and 2c. The 2a
signals contain 16 of the primitive ports which provide
essential PLB bus transaction information. The 2b signals
contain buses that identify widths and master information of
the active transaction. The 2c label is used for the
transaction attribute bus. The three subdivided match unit
groups can be all or individually enabled using the
parameters C_USE_MU_2A, C_USE_MU_2B, and
C_USE_MU_2C.
The ChipScope PLB IBA peripheral supports multiple
trigger units that connect to the PLB Control bus, Address
bus, Data bus, lumped Slave or Master busses. Each one of
these trigger units can be enabled and parameterized
independently. Table 2 lists all the parameters used in
selecting the trigger port connections. These parameters
define what signals are connected to the trigger ports, the
match unit type, and if the signals are stored in the sample
buffer.
The third, fourth, and fifth match units are used for the
address, data write, and data read buses respectively. Each
bus has a dedicated match unit so it can be individually
Table 2: IBA_PLBv46 Design Parameters
Default
Value
VHDL
Type
Generic
G1
Feature/Description
Target Family
Parameter Name
C_FAMILY
Allowable Values
Spartan3,
Virtex5
String
Spartan3E,
Spartan3A,
Spartan3ADSP,
Spartan3AN,
Virtex, VirtexE,
Virtex4, Virtex5
G2
G3
G4
G5
G6
G7
Device
C_DEVICE
String
String
String
Integer
Integer
Integer
Device Package
C_PACKAGE
Device speed grade
Number of PLB Masters
Number of PLB Slaves
C_SPEEDGRADE
C_PLBV46_NUM_MASTERS
C_PLBV46_NUM_SLAVES
C_PLBV46_MID_WIDTH
1-8
1-8
1-5
2
1
2
Number of bits required to encode the
number of PLB Masters
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ChipScope PLBv46 IBA (Bus Analyzer) (v1.00a)
Table 2: IBA_PLBv46 Design Parameters (Continued)
Default
Value
VHDL
Type
Generic
G8
Feature/Description
Parameter Name
Allowable Values
PLB Address Bus Width
PLB Data Bus Width
C_PLBV46_AWIDTH
C_PLBV46_DWIDTH
32
32
Integer
Integer
G9
32,64,128
64
IBA Storage Options and Trig Out
G10
Number of data samples captured for every C_NUM_DATA_SAMPLES
trigger match. Note that the range of
acceptable values depends on the
512, 1024, 2048,
4096, 8192, 16384,
32768, 65536,
131072
1024
Integer
C_FAMILY value.
G11
G12
Number of sequencer levels. If 0 then no
sequencer is used.
C_MAX_SEQUENCER_
LEVELS
0-16
0
1
Integer
Integer
1=Enable data store qualification (filtering) C_ENABLE_STORAGE_
0=Disable
0,1
QUALIFICATION
G13
Enable Trigger Out
C_ENABLE_TRIGGER_OUT
1,0
1,0
0
Integer
Trigger In, PLB Reset, and PLB Error Status
G14
G15
Use system reset and error status signals C_USE_MU_1A_RST_ERR_
STAT
1
0
Integer
Integer
Use master error status signals
C_USE_MU_1B_MSTR_RST_ 1,0
ERR_STAT
G16
G17
G18
Use iba_trig_in
C_USE_MU_1C_TRIG_IN
C_MU_1_TRIG_IN_WIDTH
1,0
0
0
0
Integer
Integer
Integer
Trigger in width, 0=disable
0=basic, 1=basic w/ edges
0-189
0,1
C_MU_1_TYPE_TRIG_RST_
ERR_STAT
G19
G20
Match unit counter width. 0 means do not C_MU_1_CNT_W_TRIG_
use. RST_ERR_STAT
0,1-32
0,1
0
1
Integer
Integer
1=Enable storing MU 1 signals in the data C_MU_1_EN_STORE_TRIG_
sample storage buffer.
0=Disable
RST_ERR_STAT
C_USE_MU_1A or C_USE_MU_1B must
be 1 in order to store.
PLB Grouped Control Bus
C_USE_MU_2A_STD_CTL
C_USE_MU_2B_SIZE_BE
G21
G22
Use the grouped control bus signals
1,0
1,0
1
1
Integer
Integer
Use the grouped size and byte enable
signals
G23
G24
G25
G26
Use PLB_TAttribute signals
Number of match units to use
0=basic, 1=basic w/ edges
C_USE_MU_2C_TATTR
C_MU_2_NUM_GRP_CTL
C_MU_2_TYPE_GRP_CTL
1,0
1
1
0
0
Integer
Integer
Integer
Integer
1,2
0,1
Match unit counter width. 0 means do not C_MU_2_CNT_W_GRP_CTL
use
0,1-32
G27
1=Enable storing MU 2 signals in the data C_MU_2_EN_STORE_GRP_
0,1
1
Integer
sample storage buffer.
0=Disable
CTL
C_USE_MU_2A_STD_CTL or
C_USE_MU_2B_SIZE_BE or
C_USE_MU_2C_TATTR must be 1 in order
to store.
PLB Address
G28
G29
Use PLB_ABus
Use PLB_UABus
C_USE_MU_3A_ABUS
C_USE_MU_3B_UABUS
1,0
1,0
1
1
Integer
Integer
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ChipScope PLBv46 IBA (Bus Analyzer) (v1.00a)
Table 2: IBA_PLBv46 Design Parameters (Continued)
Default
Value
VHDL
Type
Generic
G30
Feature/Description
Parameter Name
Allowable Values
0=basic, 1=basic w/ edges,
2=extended, 3= extended w/edges,
4=range, 5=range w/edges
C_MU_3_TYPE_ADDR
0,1,2,3,4,5
0
Integer
G31
G32
Match unit counter width. 0 means do not C_MU_3_CNT_W_ADDR
use
0,1-32
0,1
0
1
Integer
Integer
1=Enable storing MU 3 signals in the data C_MU_3_EN_STORE_ADDR
sample storage buffer.
0=Disable
C_USE_MU_3A_ABUS or must
C_USE_MU_3B_UABUS be 1 in order to
store.
PLB Data
G33
G34
Use PLB_wrDBus
C_USE_MU_4_WR_DBUS
C_MU_4_TYPE_WR_DBUS
1,0
0
0
Integer
Integer
0=basic, 1=basic w/ edges,
2=extended, 3= extended w/edges,
4=range, 5=range w/edges
0,1,2,3,4,5
G35
G36
Match unit counter width. 0 means do not C_MU_4_CNT_W_WR_DBUS 0,1-32
use.
0
1
Integer
Integer
1=Enable storing MU 4 signals in the data C_MU_4_EN_STORE_WR_
0,1
sample storage buffer.
0=Disable
DBUS
C_USE_MU_4_WR_DBUS must be 1 in
order to store.
G37
G38
Use PLB_srdDBus
C_USE_MU_5_RD_DBUS
C_MU_5_TYPE_RD_BUS
1,0
1
0
Integer
Integer
0=basic, 1=basic w/ edges,
2=extended, 3= extended w/edges,
4=range, 5=range w/edges
0,1,2,3,4,5
G39
G40
Match unit counter width. 0 means do not C_MU_5_CNT_W_RD_DBUS 0,1-32
use
0
1
Integer
Integer
1=Enable storing MU 5 signals in the data C_MU_5_EN_STORE_RD_
0,1
sample storage buffer.
0=Disable
DBUS
C_USE_MU_5_RD_DBUS must be 1 in
order to store.
Slave Control Bus
G41
G42
Use Slave Congrol signals
C_USE_MU_6A_SLV_CTL
1,0
1,0
0
0
Integer
Integer
USE SI_rdWdAddr and SI_SSize
C_USE_MU_6B_SLV_SZ_
WADDR
G43
G44
G45
Number of match units to use
0=basic, 1=basic w/ edges
C_MU_6_NUM_SLV_CTL_
BUS
1,2
0,1
0
0
0
Integer
Integer
Integer
C_MU_6_TYPE_SLV_CTL_
BUS
Match unit counter width. 0 means do not C_MU_6_CNT_W_SLV_CTL_ 0,1-32
use BUS
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ChipScope PLBv46 IBA (Bus Analyzer) (v1.00a)
Table 2: IBA_PLBv46 Design Parameters (Continued)
Default
Value
VHDL
Type
Generic
G46
Feature/Description
Parameter Name
Allowable Values
1=Enable storing MU 6 signals in the data C_MU_6_EN_STORE_SLV_
sample storage buffer.
0=Disable
0,1
1
Integer
CTL_BUS
C_USE_MU_6A_SLV_CTL or
C_USE_MU_6B_SLV_SZ_WADDR must
be 1 in order to store.
Slave Busy Status
G47
G48
G49
USE SI_MBusy signal
C_USE_MU_7_SLV_BSY
C_MU_7_TYPE_SLV_BSY
1,0
0
0
0
Integer
Integer
Integer
0=basic, 1=basic w/ edges
0,1
Match unit counter width. 0 means do not C_MU_7_CNT_W_SLV_BSY
use
0,1-32
G50
1=Enable storing MU 7 signals in the data C_MU_7_EN_STORE_SLV_
0,1
1
Integer
sample storage buffer.
0=Disable
BSY
C_USE_MU_7_SLV_BSY must be 1 in
order to store.
Slave Read/Writer Error Status
C_USE_MU_8_SLV_RD_ERR 1,0
G51
G52
Use SI_MRdErr
0
0
Integer
Integer
0=basic, 1=basic w/ edges
C_MU_8_TYPE_SLV_RD_
ERR
0,1
G53
G54
Match unit counter width. 0 means do not C_MU_8_CNT_W_SLV_RD_
use ERR
0,1-32
0,1
0
1
Integer
Integer
1=Enable storing MU 8 signals in the data C_MU_8_EN_STORE_SLV_
sample storage buffer.
0=Disable
RD_ERR
C_USE_MU_8_SLV_RD_ERR must be 1
in order to store.
G55
G56
Use SI_MWrErr
C_USE_MU_9_SLV_WR_ERR 1,0
0
0
Integer
Integer
0=basic, 1=basic w/ edges
C_MU_9_TYPE_SLV_WR_
ERR
0,1
G57
G58
Match unit counter width. 0 means do not C_MU_9_CNT_W_SLV_WR_
use ERR
0,1-32
0,1
0
1
Integer
Integer
1=Enable storing MU 9 signals in the data C_MU_9_EN_STORE_SLV_
sample storage buffer.
0=Disable
WR_ERR
C_USE_MU_9_SLV_WR_ERR must be 1
in order to store.
PLB Arbitration
G59
G60
G61
Use Master arbitration signals
0=basic, 1=basic w/ edges
C_USE_MU_10_ARB_CTL
C_MU_10_TYPE_ARB_CTL
1,0
0,1
0
0
0
Integer
Integer
Integer
Match unit counter width. 0 means do not C_MU_10_CNT_W_ARB_CTL 0,1-32
use
G62
1=Enable storing MU 10 signals in the data C_MU_10_EN_STORE_ARB_ 0,1
1
Integer
sample storage buffer.
0=Disable
CTL
C_USE_MU_10_ARB_CTL must be 1 in
order to store.
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ChipScope PLBv46 IBA (Bus Analyzer) (v1.00a)
Table 2: IBA_PLBv46 Design Parameters (Continued)
Default
Value
VHDL
Type
Generic
Feature/Description
Parameter Name
Allowable Values
PLB Master Control Bus
C_USE_MU_11_MSTR_CTL
C_MU_11_NUM_MSTR_CTL
G63
Use Master Control Signals
Number of match units to use
0=basic, 1=basic w/ edges
1,0
1,2
0
Integer
Integer
Integer
Integer
G64
G65
G66
1
0
0
C_MU_11_TYPE_MSTR_CTL 0,1
Match unit counter width. 0 means do not C_MU_11_CNT_W_MSTR_
use CTL
0,1-32
G67
1=Enable storing MU 11 signals in the data C_MU_11_EN_STORE_
0,1
0
Integer
sample storage buffer.
0=Disable
MSTR_CTL
C_USE_MU_11_MSTR_CTL must be 1 in
order to store.
PLB Master Size and Type Status
C_USE_MU_12_MSTR_SZ
G68
G69
G70
Use Master Size and Type Signals
0=basic, 1=basic w/ edges
1,0
0,1
0
0
0
Integer
Integer
Integer
C_MU_12_TYPE_MSTR_SZ
Match unit counter width. 0 means do not C_MU_12_CNT_W_MSTR_SZ 0,1-32
use
G71
1=Enable storing MU 12 signals in the data C_MU_12_EN_STORE_
0,1
1
Integer
sample storage buffer.
0=Disable
MSTR_SZ
C_USE_MU_12_MSTR_SZ must be 1 in
order to store.
PLB Master Byte Enable
C_USE_MU_13_MSTR_BE
C_MU_13_TYPE_MSTR_BE
G72
G73
G74
Use M_BE
1,0
0,1
0
0
0
Integer
Integer
Integer
0=basic, 1=basic w/ edges
Match unit counter width. 0 means do not C_MU_13_CNT_W_MSTR_BE 0,1-32
use
G75
1=Enable storing MU 13 signals in the data C_MU_13_EN_STORE_
0,1
1
Integer
sample storage buffer.
0=Disable
MSTR_BE
C_USE_MU_13_MSTR_BE must be 1 in
order to store.
Table 2 lists the IBA PLBv46 parameterized features.
basic and basic with edges since multiple signals make up
this match unit. Alternately, for C_MU_3_TYPE all compare
options are available since this match unit has the complete
PLB_ABus bus connected to it. The match counter width
allows you to look for multiple occurrences of the match
event. This counter width is controllable through the
C_MU_xx_CNT_W parameter (where xx is a place holder
for the MU signal value, 1-13). When this parameter is set to
0, only one occurrence is counted; otherwise, the maximum
match event count is limited by the width of this parameter.
These parameters control the ports that are attached to the
IBA trigger and storage units. They also are used to
configure the storage and match unit options available for
the different trigger ports.
The IBA ports are subdivided into logical groups call match
units have a set of parameters which are used to enable and
define the trigger port configuration for a particular set of
PLBv46 signals.
The number of match units is defined by the
Every match unit group has a match type and match
counter width parameter. The match unit type describes the
type of compare operation that can be done on a match
unit. The valid values for this type are defined for each
match unit. For example, C_MU_1_TYPE only supports
C_MU_xx_NUM parameter. By default, if a match unit does
not have the C_MU_xx_NUM parameter, only one match
unit is used for the match unit group. If the C_MU_xx_NUM
parameter is defined, then one or two match units can be
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Product Specification
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ChipScope PLBv46 IBA (Bus Analyzer) (v1.00a)
assigned for this match group. When multiple match units
are available, sequences of a match unit group can be
detected. For example, in MU_2, a trigger sequence could
be created to look for PLB_PAValid=1 followed by a rising
edge on PLB_SaddrAck. For this specific trigger event the
first match unit of MU_2 would be set to PLB_PAValid=1 and
the second to PLB_SaddrAck=R.
Design Implementation
The ChipScope PLB IBA design is implemented in a Tcl
script. When the EDK Platgen tool is run, this Tcl script is
called and it internally calls the ChipScope Pro Core
generator in command line mode providing a generated
argument (.arg) file to create a customized ILA. This ILA is
customized per the IBA settings and is attached to the
PLB46 bus using a custom HDL wrapper.
Allowable Parameter Combinations
XST is the synthesis tool used for synthesizing the wrapper
HDL generated for the ChipScope PLB IBA. The EDIF
netlist output from XST and ChipScope Core Generator are
then input to the Xilinx Foundation tool suite for actual
device implementation.
All parameters are independent of each other. Each
parameter must be in the range or exact value listed in the
allowable values of Table 2. Certain combinations will
disable the sub-parameters. As an example consider when
C_USE_MU_3 is set to 0. In this case all the
C_MU_3_<XYZ> parameters are ignored because the
match unit group has been disabled.
Target Technology
The intended target technology is all Xilinx FPGAs.
Depending on the architecture certain parameters may fail
during a design rule check. For instance, if you specify
C_NUM_DATA_SAMPLES to be 32768 for a non-Virtex-5
device, you will get an error message. Also there you must
have a width of at least one signal going to the data sample
storage buffer.
Device Utilization and Performance
Benchmarks
The device utilization varies widely based on the parameter
combinations set by the user.
ChipScope PLB46 IBA Module Register
Descriptions
Restrictions
Maximum number of signals that can be stored for
non-Virtex-5 device families is limited to 256 signals. For
Virtex-5 family devices the limit is 1024 signals.
Not applicable.
ChipScope PLB46 IBA Module Interrupt
Descriptions
Reference Documents
Not applicable.
ChipScope Pro Software and Cores User Guide
ChipScope PLB46 IBA Module Block
Diagram
Revision History
Date
Version
Revision
08/02/07
1.0
Initial release
Chipscope
ICON
mon_plb
Chipscope
PLB46_IBA
clk
iba_trig_in
DS619_02_041707
Figure 1: ChipScope PLB46 IBA Block Diagram
DS619 (v1.0) September 17, 2007
Product Specification
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