Summit Power Supply S93WD462 User Manual

SUMMIT  
MICROELECTRONICS, Inc.  
S93WD462/S93WD463  
Precision Supply-Voltage Monitor and Reset Controller  
With a Watchdog Timer and 1k-bit Microwire Memory  
FEATURES  
OVERVIEW  
Precision Monitor & RESET Controller  
The S93WD462 and S93WD463 are precision power  
— RESET and RESET Outputs  
— Guaranteed RESET Assertion to VCC = 1V  
— 150ms Reset Pulse Width  
— Internal 1.26V Reference with ±1% Accuracy  
— ZERO External Components Required  
supervisory circuits providing both active high and  
active low reset output. Both devices also incorporate a  
watchdog timer with a nominal time-out value of 1.6  
seconds.  
Both devices have 1k-bits of E2PROM memory that is  
accessibleviatheindustrystandardmicrowirebus.The  
S93WD462 is configured with an internal ORG pin tied  
low providing a 8-bit byte organization and the  
S93WD463 is configured with an internal ORG pin tied  
high providing a 16-bit word organization. Both the  
S93WD462 and S93WD463 have page write capabil-  
ity. The devices are designed for a minimum 100,000  
Watchdog Timer  
— Nominal 1.6 Second Time-out Period  
— Reset by Any Transition of CS  
Memory  
— 1K-bit Microwire Memory  
— S93WD462  
– Internally Ties ORG Low  
– 100% Compatible With all 8-bit  
Implementations  
program/erase cycles and have data retention in ex-  
cess of 100 years.  
– Sixteen Byte Page Write Capability  
— S93WD463  
– Internally Ties ORG High  
– 100% Compatible With all 16-bit  
Implementations  
– Eight Word Page Write Capability  
BLOCK DIAGRAM  
V
CC  
8
RESET#  
6
RESET  
PULSE  
GENERATOR  
5kHz  
OSCILLATOR  
+
V
TRIP  
RESET  
CONTROL  
RESET  
7
WATCHDOG  
TIMER  
1.26V  
CS  
1
MODE  
DECODE  
SK  
DI  
ADDRESS  
DECODER  
WRITE  
CONTROL  
2
3
2
E PROM  
MEMORY  
ARRAY  
DATA I/O  
DO  
4
5
2029 T BD 2.0  
Telephone 408-378-6461  
GND  
© SUMMIT MICROELECTRONICS, Inc. 2001  
300 Orchard City Drive, Suite 131  
Campbell, CA 95008  
Fax 408-378-6586  
Characteristics subject to change without notice  
2029 2.2 1/23/01  
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1
S93WD462/S93WD463  
Instructions, addresses, and write data are clocked into  
the DI pin on the rising edge of the clock (SK). The DO  
pin is normally in a high impedance state except when  
reading data from the device, or when checking the  
ready/busy status after a write operation.  
Read  
Upon receiving a READ command and an address  
(clocked into the DI pin), the DO pin of the S93WD462/  
WD463 will come out of the high impedance state and,  
will first output an initial dummy zero bit, then begin  
shifting out the data addressed (MSB first). The output  
databitswilltoggleontherisingedgeoftheSKclockand  
are stable after the specified time delay  
(tPD0 or tPD1).  
The ready/busy status can be determined after the start  
of a write operation by selecting the device (CS high)  
and polling the DO pin; DO low indicates that the write  
operationisnotcompleted, whileDOhighindicatesthat  
the device is ready for the next instruction. See the  
Applications Aid section for detailed use of the ready  
busy status.  
Write  
After receiving a WRITE command, address and the  
data, the CS (Chip Select) pin must be deselected for a  
minimum of 250ns (tCSMIN). The falling edge of CS will  
start automatic erase and write cycle to the memory  
location specified in the instruction. The ready/busy  
status of the S93WD462/WD463 can be determined by  
selecting the device and polling the DO pin.  
The format for all instructions is: one start bit; two op  
code bits and either six (x16) or seven (x8) address or  
instruction bits.  
t
t
t
SKLOW  
CSH  
SKHI  
SK  
t
t
DIH  
DIS  
VALID  
VALID  
DI  
t
CSS  
CS  
t
t
t
t
DIS  
CSMIN  
PD0, PD1  
DO  
DATAVALID  
2029 ILL 3.0  
Figure 1. Sychronous Data Timing  
SK  
t
CS  
CS  
DI  
STANDBY  
A
N
A
N1  
A
0
1
1
0
t
HZ  
t
HIGH-Z  
HIGH-Z  
PD0  
DO  
0
D
N
D
N1  
D
1
D
0
2029 ILL4.0  
Figure 2. Read Instruction Timing  
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S93WD462/S93WD463  
Erase  
Erase All  
Upon receiving an ERASE command and address, the  
CS (Chip Select) pin must be deselected for a minimum  
of 250ns (tCSMIN). The falling edge of CS will start the  
auto erase cycle of the selected memory location. The  
ready/busy status of the S93WD462/WD463 can be  
determined by selecting the device and polling the DO  
pin. Once cleared, the content of a cleared location  
returns to a logical 1state.  
Upon receiving an ERAL command, the CS (Chip Se-  
lect) pin must be deselected for a minimum of 250ns  
(tCSMIN). ThefallingedgeofCSwillstarttheselfclocking  
clear cycle of all memory locations in the device. The  
clocking of the SK pin is not necessary after the device  
has entered the self clocking mode. The ready/busy  
status of the S93WD462/WD463 can be determined by  
selecting the device and polling the DO pin. Once  
cleared, the contents of all memory bits will be in a  
logical 1state.  
Erase/Write Enable and Disable  
The S93WD462/WD463 powers up in the write disable  
state. Any writing after power-up or after an EWDS  
(write disable) instruction must first be preceded by the  
EWEN (write enable) instruction. Once the write in-  
struction is enabled, it will remain enabled until power to  
the device is removed, or the EWDS instruction is sent.  
The EWDS instruction can be used to disable all  
S93WD462/WD463 write and clear instructions, and  
will prevent any accidental writing or clearing of the  
device. Data can be read normally from the device  
regardless of the write enable/disable status.  
Write All  
Upon receiving a WRAL command and data, the CS  
(Chip Select) pin must be deselected for a minimum of  
250ns (tCSMIN). The falling edge of CS will start the self  
clocking data write to all memory locations in the device.  
The clocking of the SK pin is not necessary after the  
device has entered the self clocking mode. The ready/  
busy status of the S93WD462/WD463 can be deter-  
mined by selecting the device and polling the DO pin. It  
is not necessary for all memory locations to be cleared  
before the WRAL command is executed.  
Page Write  
address. Internally the address pointer is incremented  
after receiving each group of sixteen clocks; however,  
once the address counter reaches xxx x111 it will roll  
over to xx x000 with the next clock. After the last bit is  
clockedinnointernalwriteoperationwilloccuruntilCS  
is brought low.  
93WD462 - Assume WEN has been issued. The host  
will then take CS high, and begin clocking in the start  
bit, write command and 7-bit address immediately  
followed by the first byte of data to be written. The host  
can then continue clocking in 8-bit bytes of data with  
each byte to be written to the next higher address.  
Internally the address pointer is incremented after  
receiving each group of eight clocks; however, once  
the address counter reaches xxx 1111 it will roll over  
to xxx 0000 with the next clock. After the last bit is  
clockedinnointernalwriteoperationwilloccuruntilCS  
is brought low.  
Continuous Read  
This begins just like a standard read with the host  
issuing a read instruction and clocking out the data  
byte [word]. If the host then keeps CS high and  
continues generating clocks on SK, the S93WD462/  
WD463 will output data from the next higher address  
location. The S93WD462/WD463 will continue  
incrementing the address and outputting data so long  
asCSstayshigh.Ifthehighestaddressisreached,the  
address counter will roll over to address 0000. CS  
going low will reset the instruction register and any  
subsequent read must be initiated in the normal man-  
ner of issuing the command and address.  
93WD463 - Assume WEN has been issued. The host  
will then take CS high, and begin clocking in the start  
bit, write command and 6-bit address immediately  
followed by the first 16-bit word of data to be written.  
The host can then continue clocking in 16-bit words of  
data with each word to be written to the next higher  
4
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S93WD462/S93WD463  
SK  
t
CS  
STANDBY  
STATUS  
VERIFY  
CS  
DI  
A
N
A
N-1  
A
0
D
N
D
0
1
0
1
t
t
HZ  
SV  
BUSY  
READY  
HIGH-Z  
DO  
HIGH-Z  
t
EW  
2029 ILL 5.0  
Figure 3. Write Instruction Timing  
SK  
STANDBY  
STATUS VERIFY  
CS  
DI  
t
CS  
A
N
A
0
A
N-1  
1
1
1
t
t
SV  
HZ  
HIGH-Z  
DO  
BUSY  
EW  
READY  
HIGH-Z  
t
2029 ILL6.0  
Figure 4. Erase Instruction Timing  
SK  
STANDBY  
CS  
DI  
1
0
0
*
* ENABLE = 11  
DISABLE = 00  
2029 Fig05  
Figure 5. EWEN/EWDS Instruction Timing  
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S93WD462/S93WD463  
SK  
CS  
DI  
STANDBY  
STATUS VERIFY  
t
CS  
1
0
0
1
0
t
t
SV  
HZ  
HIGH-Z  
DO  
BUSY  
READY  
HIGH-Z  
t
EW  
2029 ILL 8.0  
Figure 6. ERAL Instruction Timing  
SK  
CS  
DI  
STANDBY  
STATUS VERIFY  
t
CS  
D
D
1
0
0
0
1
N
O
t
t
HZ  
SV  
DO  
BUSY  
READY  
HIGH-Z  
t
EW  
2029 ILL 10.0  
Figure 7. WRAL Instruction Timing  
INSTRUCTION SET  
Instruction  
Start  
Bit  
Opcode  
Address  
x8  
Data  
x8  
Comments  
x16  
x16  
READ  
ERASE  
WRITE  
EWEN  
EWDS  
ERAL  
1
1
1
1
1
1
1
10  
11  
01  
00  
00  
00  
00  
A6A0  
A6A0  
A5A0  
A5A0  
A5A0  
11xxxx  
00xxxx  
10xxxx  
01xxxx  
Read Address ANA0  
Clear Address ANA0  
Write Address ANA0  
Write Enable  
A6A0  
D7D0  
D15D0  
11xxxxx  
00xxxxx  
10xxxxx  
01xxxxx  
Write Disable  
Clear All Addresses  
WRAL  
D7D0  
D15D0  
Write All Addresses  
2029 PGM T5.0  
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S93WD462/S93WD463  
ABSOLUTE MAXIMUM RATINGS*  
Temperature Under Bias .................................................................................................................................... 55°C to +125°C  
Storage Temperature ......................................................................................................................................... 65°C to +150°C  
Voltage on any Pin with Respect to Ground(1) ............................................................................................. 2.0V to +VCC +2.0V  
VCC with Respect to Ground .................................................................................................................................. 2.0V to +7.0V  
Package Power Dissipation Capability (Ta = 25°C) ............................................................................................................. 1.0W  
Lead Soldering Temperature (10 secs) .............................................................................................................................. 300°C  
Output Short Circuit Current(2) ........................................................................................................................................... 100 mA  
*COMMENT  
StressesabovethoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratingsonly,andfunctional  
operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to  
any absolute maximum rating for extended periods may affect device performance and reliability.  
RECOMMENDED OPERATING CONDITIONS  
Temperature  
Commercial  
Industrial  
Min  
0°C  
Max  
+70°C  
+85°C  
-40°C  
2029 PGM T7.0  
RELIABILITY CHARACTERISTICS  
Symbol  
Parameter  
Endurance  
Min.  
100,000  
100  
Max.  
Units  
Cycles/Byte  
Years  
(3)  
NEND  
(3)  
TDR  
Data Retention  
ESD Susceptibility  
Latch-Up  
(3)  
VZAP  
2000  
100  
Volts  
(3)(4)  
ILTH  
mA  
D.C. OPERATING CHARACTERISTICS (over recommended operating conditions unless otherwise specified)  
Limits  
Symbol  
Parameter  
Min.  
Typ.  
Max.  
Units  
Test Conditions  
ICC  
Power Supply Current  
(Operating)  
3
mA  
DI = 0.0V, fSK = 1MHz  
VCC = 5.0V, CS = 5.0V,  
Output Open  
ISB  
Power Supply Current  
(Standby)  
50  
µA  
CS = 0V  
Reset Outputs Open  
ILI  
Input Leakage Current  
2
µA  
µA  
VIN = 0V to VCC  
ILO  
Output Leakage Current  
(Including ORG pin)  
10  
VOUT = 0V to VCC  
CS = 0V  
,
VIL1  
VIH1  
Input Low Voltage  
Input High Voltage  
-0.1  
2
0.8  
V
V
4.5V-VCC<5.5V  
1.8V-VCC<2.7V  
VCC+1  
VIL2  
VIH2  
Input Low Voltage  
Input High Voltage  
0
VCCX0.2  
VCC+1  
V
V
VCCX0.7  
VOL1  
VOH1  
Output Low Voltage  
Output High Voltage  
0.4  
V
V
4.5V-VCC<5.5V  
IOL = 2.1mA  
IOH = -400µA  
2.4  
VOL2  
VOH2  
Output Low Voltage  
Output High Voltage  
0.2  
V
V
1.8V-VCC<2.7V  
IOL = 1mA  
IOH = -100µA  
VCC-0.2  
2029 PGM T3.0  
Note:  
(1) The minimum DC input voltage is 0.5V. During transitions, inputs may undershoot to 2.0V for periods of less than 20 ns. Maximum DC  
voltage on output pins is V +0.5V, which may overshoot to V +2.0V for periods of less than 20 ns.  
CC  
CC  
(2) Output shorted for no more than one second. No more than one output shorted at a time.  
(3) This parameter is tested initially and after a design or process change that affects the parameter.  
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from 1V to V +1V.  
CC  
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S93WD462/S93WD463  
PIN CAPACITANCE  
Symbol  
Test  
Max.  
Units  
pF  
Conditions  
VOUT=OV  
VIN=OV  
(1)  
COUT  
OUTPUT CAPACITANCE (DO)  
5
5
(1)  
CIN  
INPUT CAPACITANCE (CS, SK, DI, ORG)  
pF  
Note:  
(1) This parameter is tested initially and after a design or process change that affects the parameter.  
2029 PGM T4.0  
A.C. CHARACTERISTICS (over recommended operating conditions unless otherwise specified)  
Limits  
V
CC=2.7V-4.5V VCC=4.5V-5.5V  
Test  
SYMBOL PARAMETER  
Min. Max. Min. Max. UNITS Conditions  
tCSS  
tCSH  
tDIS  
CS Setup Time  
100  
0
50  
0
ns  
ns  
ns  
ns  
µs  
µs  
ns  
ms  
µs  
µs  
µs  
µs  
CS Hold Time  
DI Setup Time  
200  
200  
100  
100  
tDIH  
tPD1  
tPD0  
DI Hold Time  
Output Delay to 1  
0.5  
0.5  
200  
10  
0.25  
0.25  
100  
10  
Output Delay to 0  
CL = 100pF  
(1)  
tHZ  
Output Delay to High-Z  
Program/Erase Pulse Width  
Minimum CS Low Time  
Minimum SK High Time  
Minimum SK Low Time  
Output Delay to Status Valid  
Maximum Clock Frequency  
tEW  
tCSMIN  
tSKHI  
tSKLOW  
tSV  
0.5  
0.5  
0.5  
0.25  
0.25  
0.25  
0.5  
0.25  
SKMAX  
DC  
500  
DC  
1000 KHZ  
2029 PGM T6.0  
Note:  
(1) This parameter is tested initially and after a design or process change that affects the parameter.  
8
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S93WD462/S93WD463  
RESET CIRCUIT AC and DC ELECTRICAL CHARACTERISTICS  
2.7  
5 Volt-A  
5 Volt-B  
Symbol  
Parameter  
Min  
2.55  
130  
Max  
2.7  
270  
5
Min  
Max  
4.5  
270  
5
Min  
Max  
4.75  
270  
5
Unit  
V
V
Reset Trip Point  
Power-Up Reset Timeout  
to RESET Output Delay  
4.25  
130  
4.50  
130  
TRIP  
PURST  
RPD  
t
t
ms  
µs  
V
V
TRIP  
V
RESET# Output Valid  
1
1
1
RVALID  
GLITCH  
t
Glitch Reject Pulse Width  
30  
30  
30  
ns  
V
V
RESET# Output Low Voltage I =1mA  
0.4  
0.4  
0.4  
OLRS  
OHRS  
OL  
V
RESET Output High I  
V
-.75  
CC  
V
-.75  
CC  
V -.75  
CC  
V
OH  
2029 PGM T1.0  
t
GLITCH  
V
TRIP  
V
RVALID  
t
RPD  
V
t
CC  
PURST  
t
PURST  
RESET#  
t
RPD  
RESET  
2029 T fig08 2.0  
Figure 8. RESET Timing Diagram  
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S93WD462/S93WD463  
8 Pin SOIC  
Ref. JEDEC MS-012  
0.150 - 0.157  
(3.80 - 4.00)  
1
Inches  
(Millimeters)  
0.189 - 0.196  
(4.80 - 5.00)  
0.053 - 0.069  
(1.35 - 1.75)  
0.010 - 0.020  
×45º  
(0.25 - 0.50)  
0.004 - 0.010  
0.016 - 0.050  
(0.40 - 1.27)  
(0.10 - 0.25)  
0.013 - 0.020  
(0.33 - 0.51)  
0.228 - 0.244  
(5.80 - 6.20)  
.05 (1.27) TYP.  
8 Pin SOIC  
8 Pin PDIP  
0.355 - 0.400  
(9.02 - 10.2)  
Ref. JEDEC MS-001  
0.24 - 0.28  
(6.1 - 7.1)  
PIN 1 INDICATOR  
Inches  
(Millimeters)  
0.045 - 0.070  
(1.14 - 1.78)  
0.300 - 0.325  
(7.62 - 8.25)  
0.115 - 0.195  
0.21  
MAX.  
(2.92 - 4.95)  
(5.33)  
.015  
Min.  
(.381)  
1
SEATING PLANE  
0.008 - 0.014  
(0.20 - 0.36)  
.100  
0.43  
(2.54)  
0.014 - 0.022  
(0.36 - 0.56)  
MAX.  
(10.9)  
0.115 - 0.195  
(2.92 - 4.95)  
8 Pin PDIP  
10  
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S93WD462/S93WD463  
Frequently the reset controller will be deployed on a PC board that provides a peripheral function to a system.  
Examples might be modem or network cards in a PC or a PCMCIA card in a laptop. In instances like this the peripheral  
cardmayhavearequirementforacleanresetfunctiontoinsureproperoperation. Thesystemmayormaynotprovide  
a reset pulse of sufficient duration to clear the peripheral or to protect data stored in a nonvolatile memory.  
The I/O capability of the RESET pins can provide a solution. The systems reset signal to the peripheral can be fed  
intotheS93WD462/WD463anditinturncancleanupthesignalandprovideaknownentitytotheperipheralscircuits.  
The figure below shows the basic timing characteristics under the assumption the reset input is shorter in duration  
than tPURST. The same reset output affect can be attained by using the active high reset input.  
RESET#  
Input  
RESET#  
Output  
RESET  
Output  
t
PURST  
2029 T fig09 2.0  
When planning your resistor pull-up and pull-down values, use the following chart to help determine min. resistances.  
Worst Case RESET Sink/Source Capabilities at Various VCC Levels  
Parameter  
Symbol  
Condition  
Min  
Typ  
Max  
0.3  
0.3  
0.3  
0.3  
0.3  
0.4  
0.4  
0.4  
0.4  
0.4  
Units  
VCC = 1.0V, IOL=100µA  
VCC = 1.2V, IOL=100µA  
VCC = 3.0V, IOL=500µA  
VCC = 3.6V, IOL=500µA  
VCC = 4.5V, IOL=750µA  
VCC = 1.0V, IOL=100µA  
VCC = 1.2V, IOL=150µA  
VCC = 3.0V, IOL=750µA  
VCC = 3.6V, IOL=1mA  
VCC = 4.5V, IOL=1mA  
VCC = 1.0V, IOH=400µA  
VCC = 1.2V, IOH=800µA  
VCC = 3.0V, IOH=800µA  
VCC = 3.6V, IOH=800µA  
VCC = 4.5V, IOH=800µA  
V
V
V
V
V
V
V
V
V
V
V
V
V
V
RESET# Output  
VOL  
Voltage  
RESET# Output  
VOL  
Voltage  
VCC-0.75  
VCC-0.75  
VCC-0.5  
VCC-0.5  
VCC-0.5  
RESET Output  
Voltage  
VOH  
V
2029 PGM T5.0  
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S93WD462/S93WD463  
Ready/Busy Status  
During the internal write operation the S93WD462/WD463 memory array is inaccessible. After starting the write  
operation(takingCSlow)thehostcanimplementa10mstimeoutroutineoralternativelyitcanemployapollingroutine  
that tests the state of the DO pin.  
After starting the write, testing for the status is easily accomplished by taking CS high and testing the state of DO. If  
it is low the device is still busy with the internal write. If it is high the write operation has completed.  
For the polling routine the host has the option of toggling CS for each test of DO, or it can place CS high and then  
intermittently test DO. SK is not required for any of these operations. Once the device is ready, it will continue to drive  
DO high whenever the S93WD462/WD463 is selected. The ready state of DO can be cleared by clocking in a start  
bit;thisstartbitcaneitherbethebeginningofanewcommandsequenceoritcanbeadummystartbitwithCSreturning  
low before the host issues a new command.  
SK  
CS  
STATUS VERIFY  
t
CS  
DI  
t
t
SV  
HZ  
HIGH-Z  
DO  
BUSY  
READY  
HIGH-Z  
STATUS CLEARED  
t
EW  
2029 ILL 13.0  
12  
2029 2.2 1/23/01  
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S93WD462/S93WD463  
ORDERING INFORMATION  
S93WD462 P A T  
Tape & Reel Option  
Blank = Tube  
T = Tape & Reel  
Base Part Number  
S93WD462 = 8-bit configuration  
S93WD463 = 16-bit configuration  
Package  
Operating Voltage Range  
A = 4.5V to 5.5V V  
B = 4.5V to 5.5V V  
min. @ 4.25V  
min. @ 4.50V  
P = 8 lead PDIP  
S = 8 lead 150mil SOIC  
TRIP  
TRIP  
2.7 = 2.7V to 5.5V V  
min. @ 2.55V  
TRIP  
2029 Tree 2.0  
13  
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2029 2.2 1/23/01  
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S93WD462/S93WD463  
NOTICE  
SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in  
order to improve design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for  
the use of any circuits described herein, conveys no license under any patent or other right, and makes no  
representation that the circuits are free of patent infringement. Charts and schedules contained herein reflect  
representative operating parameters, and may vary depending upon a users specific application. While the  
information in this publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any  
damages arising as a result of any error or omission.  
SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support or aviation  
applications where the failure or malfunction of the product can reasonably be expected to cause any failure of either  
system or to significantly affect their safety or effectiveness. Products are not authorized for use in such applications  
unless SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or  
damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT  
Microelectronics, Inc. is adequately protected under the circumstances.  
© Copyright 2001 SUMMIT Microelectronics, Inc.  
This Document supersedes all previous versions..  
14  
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