SMSC Switch LAN9312 User Manual

AUTO_MDIX_1

When configured low, Auto-MDIX is disabled. When

configured high, Auto-MDIX is enabled.

Note:

If AMDIXCTL is set, this strap had no effect.

manual_mdix_strap_1

autoneg_strap_1

Port 1 Manual MDIX Strap: Configures MDI(0) or MDIX(1)

for Port 1 when the auto_mdix_strap_1 is low and the

AMDIXCTL bit of the Port x PHY Special Control/Status

Port x PHY Basic Control Register

Port 1 Auto Negotiation Enable Strap: Configures the

default value for the Auto-Negotiation (PHY_AN) enable bit

in the PHY_BASIC_CTRL_1 register (See

Section 14.4.2.1). When configured low, auto-negotiation is

disabled. When configured high, auto-negotiation is

enabled.

This strap also affects the default value of the following bits:

„ PHY_SPEED_SEL_LSB and PHY_DUPLEX bits of the

(PHY_BASIC_CONTROL_x)

„ 10BASE-T Full Duplex (bit 6) and 10BASE-T Half Duplex

(bit 5) bits of the Port x PHY Auto-Negotiation

„ MODE[2:0] bits of the Port x PHY Special Modes Register

Control Register (PHY_BASIC_CONTROL_x)

Refer to the respective register definition sections for

additional information.

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Table 4.2 Soft-Strap Configuration Strap Definitions (continued)

PIN / DEFAULT

VALUE

STRAP NAME

DESCRIPTION

speed_strap_1

Port 1 Speed Select Strap: Configures the default value

for the Speed Select LSB (PHY_SPEED_SEL_LSB) bit in

the PHY_BASIC_CTRL_1 register (See Section 14.4.2.1).

When configured low, 10 Mbps is selected. When

configured high, 100 Mbps is selected.

This strap also affects the default value of the following bits:

„ PHY_SPEED_SEL_LSB bit of the Port x PHY Basic

„ 10BASE-T Full Duplex (bit 6) and 10BASE-T Half Duplex

(bit 5) bits of the Port x PHY Auto-Negotiation

„ MODE[2:0] bits of the Port x PHY Special Modes Register

Negotiation Advertisement Register (PHY_AN_ADV_x)

Refer to the respective register definition sections for

additional information.

duplex_strap_1

Port 1 Duplex Select Strap: Configures the default value

for the Duplex Mode (PHY_DUPLEX) bit in the

PHY_BASIC_CTRL_1 register (See Section 14.4.2.1).

When configured low, half-duplex is selected. When

configured high, full-duplex is selected.

This strap also affects the default value of the following bits:

„ PHY_DUPLEX bit of the Port x PHY Basic Control

„ 10BASE-T Full Duplex (bit 6) of the Port x PHY Auto-

„ MODE[2:0] bits of the Port x PHY Special Modes Register

Transmit Flow Control Enable (TX_FC_1) and Port 1 Full-

Refer to the respective register definition sections for

additional information.

BP_EN_strap_1

FD_FC_strap_1

Port 1 Backpressure Enable Strap: Configures the

default value for the Port 1 Backpressure Enable

(BP_EN_1) bit of the Port 1 Manual Flow Control Register

(MANUAL_FC_1). When configured low, backpressure is

disabled. When configured high, backpressure is enabled.

Port 1 Full-Duplex Flow Control Enable Strap:

Configures the default value of the Port 1 Full-Duplex

Duplex Receive Flow Control Enable (RX_FC_1) bits in the

Port 1 Manual Flow Control Register (MANUAL_FC_1),

which are used when manual full-duplex control is selected.

When configured low, full-duplex Pause packet detection

and generation are disabled. When configured high, full-

duplex Pause packet detection and generation are enabled.

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Table 4.2 Soft-Strap Configuration Strap Definitions (continued)

DESCRIPTION

PIN / DEFAULT

VALUE

STRAP NAME

manual_FC_strap_1

Port 1 Manual Flow Control Enable Strap: Configures the

default value of the Port 1 Full-Duplex Manual Flow Control

Select (MANUAL_FC_1) bit in the Port 1 Manual Flow

Control Register (MANUAL_FC_1). When configured low,

flow control is determined by auto-negotiation (if enabled),

and symmetric PAUSE is advertised (bit 10 of the Port x

PHY Auto-Negotiation Advertisement Register

(PHY_AN_ADV_x) is set).

When configured high, flow control is determined by the

Port 1 Full-Duplex Transmit Flow Control Enable

(TX_FC_1) and Port 1 Full-Duplex Receive Flow Control

Enable (RX_FC_1) bits, and symmetric PAUSE is not

advertised (bit 10 of the Port x PHY Auto-Negotiation

Advertisement Register (PHY_AN_ADV_x) is cleared).

auto_mdix_strap_2

Port 2 Auto-MDIX Enable Strap: Configures the default

value for the Auto-MDIX functionality on Port 2 when the

AMDIXCTL bit in the Port x PHY Special Control/Status

AUTO_MDIX_2

When configured low, Auto-MDIX is disabled. When

configured high, Auto-MDIX is enabled.

Note:

If AMDIXCTL is set, this strap had no effect.

manual_mdix_strap_2

autoneg_strap_2

Port 2 Manual MDIX Strap: Configures MDI(0) or MDIX(1)

for Port 2 when the auto_mdix_strap_2 is low and the

AMDIXCTL bit of the Port x PHY Special Control/Status

Port x PHY Basic Control Register

Port 2 Auto Negotiation Enable Strap: Configures the

default value for the Auto-Negotiation (PHY_AN) enable bit

in the PHY_BASIC_CTRL_2 register (See

Section 14.4.2.1). When configured low, auto-negotiation is

disabled. When configured high, auto-negotiation is

enabled.

This strap also affects the default value of the following bits:

„ PHY_SPEED_SEL_LSB and PHY_DUPLEX bits of the

(PHY_BASIC_CONTROL_x)

„ 10BASE-T Full Duplex (bit 6) and 10BASE-T Half Duplex

(bit 5) bits of the Port x PHY Auto-Negotiation

„ MODE[2:0] bits of the Port x PHY Special Modes Register

Control Register (PHY_BASIC_CONTROL_x)

Refer to the respective register definition sections for

additional information.

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Table 4.2 Soft-Strap Configuration Strap Definitions (continued)

PIN / DEFAULT

VALUE

STRAP NAME

DESCRIPTION

speed_strap_2

Port 2 Speed Select Strap: Configures the default value

for the Speed Select LSB (PHY_SPEED_SEL_LSB) bit in

the PHY_BASIC_CTRL_2 register (See Section 14.4.2.1).

When configured low, 10 Mbps is selected. When

configured high, 100 Mbps is selected.

This strap also affects the default value of the following bits:

„ PHY_SPEED_SEL_LSB bit of the Port x PHY Basic

„ 10BASE-T Full Duplex (bit 6) and 10BASE-T Half Duplex

(bit 5) bits of the Port x PHY Auto-Negotiation

„ MODE[2:0] bits of the Port x PHY Special Modes Register

Negotiation Advertisement Register (PHY_AN_ADV_x)

Refer to the respective register definition sections for

additional information.

duplex_strap_2

Port 2 Duplex Select Strap: Configures the default value

for the Duplex Mode (PHY_DUPLEX) bit in the

PHY_BASIC_CTRL_2 register (See Section 14.4.2.1).

When configured low, half-duplex is selected. When

configured high, full-duplex is selected.

This strap also affects the default value of the following bits:

„ PHY_DUPLEX bit of the Port x PHY Basic Control

„ 10BASE-T Full Duplex (bit 6) of the Port x PHY Auto-

„ MODE[2:0] bits of the Port x PHY Special Modes Register

Transmit Flow Control Enable (TX_FC_2) and Port 2 Full-

Refer to the respective register definition sections for

additional information.

BP_EN_strap_2

FD_FC_strap_2

Port 2 Backpressure Enable Strap: Configures the

default value for the Port 2 Backpressure Enable

(BP_EN_2) bit of the Port 2 Manual Flow Control Register

(MANUAL_FC_2). When configured low, backpressure is

disabled. When configured high, backpressure is enabled.

Port 2 Full-Duplex Flow Control Enable Strap:

Configures the default value of the Port 2 Full-Duplex

Duplex Receive Flow Control Enable (RX_FC_2) bits in the

Port 2 Manual Flow Control Register (MANUAL_FC_2),

which are used when manual full-duplex control is selected.

When configured low, full-duplex Pause packet detection

and generation are disabled. When configured high, full-

duplex Pause packet detection and generation are enabled.

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Table 4.2 Soft-Strap Configuration Strap Definitions (continued)

DESCRIPTION

PIN / DEFAULT

VALUE

STRAP NAME

manual_FC_strap_2

Port 2 Manual Flow Control Enable Strap: Configures the

default value of the Port 2 Full-Duplex Manual Flow Control

Select (MANUAL_FC_2) bit in the Port 2 Manual Flow

Control Register (MANUAL_FC_2). When configured low,

flow control is determined by auto-negotiation (if enabled),

and symmetric PAUSE is advertised (bit 10 of the Port x

PHY Auto-Negotiation Advertisement Register

(PHY_AN_ADV_x) is set).

When configured high, flow control is determined by the

Port 2 Full-Duplex Transmit Flow Control Enable

(TX_FC_2) and Port 2 Full-Duplex Receive Flow Control

Enable (RX_FC_2) bits, and symmetric PAUSE is not

advertised (bit 10 of the Port x PHY Auto-Negotiation

Advertisement Register (PHY_AN_ADV_x) is cleared).

BP_EN_strap_mii

FD_FC_strap_mii

Port 0(Host MAC) Backpressure Enable Strap:

Configures the default value for the Port 0 Backpressure

Enable (BP_EN_MII) bit of the Port 0(Host MAC) Manual

Flow Control Register (MANUAL_FC_MII). When

configured low, backpressure is disabled. When configured

high, backpressure is enabled.

Port 0(Host MAC) Full-Duplex Flow Control Enable

Strap: Configures the default of the TX_FC_MII and

RX_FC_MII bits in the Port 0(Host MAC) Manual Flow

Control Register (MANUAL_FC_MII) which are used when

manual full-duplex flow control is selected. When

configured low, flow control is disabled on RX/TX. When

configured high, flow control is enabled on RX/TX.

manual_FC_strap_mii

Port 0(Host MAC) Manual Flow Control Enable Strap:

Configures the default value of the MANUAL_FC_MII bit in

the Port 0(Host MAC) Manual Flow Control Register

(MANUAL_FC_MII). When configured low, flow control is

determined by Virtual Auto-Negotiation (if enabled). When

configured high, flow control is determined by TX_FC_MII

and RX_FC_MII bits in the Port 0(Host MAC) Manual Flow

Control Register (MANUAL_FC_MII).

SQE_test_disable_strap_mii

SQE Heartbeat Disable Strap: Configures the Signal

Quality Error (Heartbeat) test function by controlling the

default value of the SQEOFF (bit 0) of the Virtual PHY

Special Control/Status Register

(VPHY_SPECIAL_CONTROL_STATUS). When configured

low, SQEOFF defaults to 0 and SQE test is enabled. When

configured high, SQEOFF defaults to 1 and SQE test is

disabled.

4.2.4.2

Hard-Straps

Hard-straps are latched upon Power-On Reset (POR) or pin reset (nRST) only. Unlike soft-straps,

hard-straps always have an associated pin and cannot be overridden by the EEPROM Loader. These

straps are used as either direct configuration values or as register defaults. T a ble 4.3 provides a list of

all hard-straps and their associated pin. These straps, along with their pin assignments are also fully

defined in Chapter 3, "Pin Description and Configuration," on page 26.

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Table 4.3 Hard-Strap Configuration Strap Definitions

STRAP NAME

DESCRIPTION

eeprom_type_strap

EEPROM Type Strap: Configures the EEPROM type.

EEPROM_TYPE

0 = Microwire Mode

1 = I C Mode

EEPROM_SIZE_[1:0]

PHY_ADDR_SEL

eeprom_size_strap[1:0]

phy_addr_sel_strap

EEPROM Size Strap [1:0]: Configures the EEPROM size

range as specified in Section 10.2, "I2C/Microwire Master

EEPROM Controller," on page 137.

PHY Address Select Strap: Configures the default MII

management address values for the PHYs and Virtual PHY

as detailed in Section 7.1.1, "PHY Addressing," on page 82.

4.3

Power Management

The LAN9312 Port 1 and Port 2 PHYs and the Host MAC support several power management and

wakeup features.

The LAN9312 can be programmed to issue an external wake signal (PME) via several methods,

including wake on LAN, wake on link status change (energy detect), and magic packet wakeup. The

PME signal is ideal for triggering system power-up using remote Ethernet wakeup events. A simplified

diagram of the logic that controls the PME and PME_INT signals can be seen in Figure 4.1.

The PME module handles the latching of the Port 1 & 2 PHY Energy-Detect Status (ED_STS1 and

ED_STS2) and Wake-On LAN Status (WOL_STS) bits of the Power Management Control Register

(PMT_CTRL). This module also masks the status bits with the corresponding enable bits (ED_EN1,

ED_EN2, WOL_EN) and combines the results together to generate the PME_INT status bit in the

Interrupt Status Register (INT_STS). The PME_INT status bit is then masked with the PME_EN bit and

conditioned before becoming the PME output pin.

The PME output characteristics can be configured via the PME_TYPE, PME_IND, and PME_POL bits

of the Power Management Control Register (PMT_CTRL). These bits allow the PME to be open-drain,

active high push-pull, or active-low push-pull and configure the output to be continuous, or pulse for

50mS.

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WUFR (bit 6) of

HMAC_WUCSR register

WOL_EN (bit 9) of

PMT_CTRL register

WUEN (bit 2) of

HMAC_WUCSR register

WOL_STS (bit 5) of

PMT_CTRL register

MPR (bit 5) of

HMAC_WUCSR register

MPEN (bit 1) of

HMAC_WUCSR register

ED_EN1 (bit 14) of

PMT_CTRL register

INT7 (bit 7) of

PHY_INTERRUPT_SOURCE_1 register

ED_STS1 (bit 16) of

PMT_CTRL register

INT7_MASK (bit 7) of

PHY_INTERRUPT_SOURCE_1 register

ED_EN2 (bit 15) of

PMT_CTRL register

INT7 (bit 7) of

ED_STS2 (bit 17) of

PHY_INTERRUPT_SOURCE_2 register

PMT_CTRL register

INT7_MASK (bit 7) of

PHY_INTERRUPT_SOURCE_2 register

Other System

Interrupts

PME_INT (bit 17)

of INT_STS register

Polarity &

Buffer Type

Logic

Denotes a level-triggered "sticky" status bit

IRQ

PME_INT_EN (bit 17)

of INT_EN register

IRQ_EN (bit 8)

of IRQ_CFG register

PME_EN (bit 1) of

PMT_CTRL register

50ms

PME

PME_IND (bit 3) of

PMT_CTRL register

LOGIC

PME_POL (bit 2) of

PMT_CTRL register

PME_TYPE (bit 6) of

PMT_CTRL register

Figure 4.1 PME and PME_INT Signal Generation

4.3.1

Port 1 & 2 PHY Power Management

The Port 1 & 2 PHYs provide independent general power-down and energy-detect power-down modes

which reduce PHY power consumption. General power-down mode provides power savings by

powering down the entire PHY, except the PHY management control interface. General power-down

mode must be manually enabled and disabled as described in Section 7.2.9.1, "PHY General Power-

Down," on page 95.

In energy-detect power-down mode, the PHY will resume from power-down when energy is seen on

the cable (typically from link pulses). If the ENERGYON interrupt (INT7) of either PHYs Port x PHY

Interrupt Mask Register (PHY_INTERRUPT_MASK_x) is unmasked, then the corresponding PHY will

generate an interrupt. These interrupts are reflected in the Interrupt Status Register (INT_STS) bit 27

(PHY_INT2) for the Port 2 PHY, and bit 26 (PHY_INT1) for the Port 1 PHY. These interrupts can be

used to trigger the IRQ interrupt output pin, as described in Section 5.2.3, "Ethernet PHY Interrupts,"

on page 52. Refer to Section 7.2.9.2, "PHY Energy Detect Power-Down," on page 95 for details on the

operation and configuration of the PHY energy-detect power-down mode.

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The Port 1 & 2 PHY energy-detect events are capable of asserting the PME output by additionally

setting the PME_EN and ED_EN2 (Port 2 PHY) or ED_EN1 (Port 1 PHY) bits of the Power

Management Control Register (PMT_CTRL).

4.3.2

Host MAC Power Management

The Host MAC provides wake-up frame and magic packet detection modes. When enabled in the Host

MAC Wake-up Control and Status Register (HMAC_WUCSR) (via the WUEN bit for wake-up frames,

and the MPEN bit for magic packets), detection of wake-up frames or magic packets causes the WUFR

and MPR bits of the HMAC_WUCSR register to set, respectively. If either of the WUFR and MPR bits

are set, the WOL_STS bit of the Power Management Control Register (PMT_CTRL) will be set. These

events can enable PME output assertion by additionally setting the PME_EN bit of the Power

Management Control Register (PMT_CTRL).

The IRQ interrupt output can be triggered by a wake-up frame or magic packet as described in Section

5.2.6, "Power Management Interrupts," on page 53.

Refer to Section 9.5, "Wake-up Frame Detection," on page 116 and Section 9.5.1, "Magic Packet

Detection," on page 118 for additional details on these features.

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Chapter 5 System Interrupts

5.1

Functional Overview

This chapter describes the system interrupt structure of the LAN9312. The LAN9312 provides a multi-

tier programmable interrupt structure which is controlled by the System Interrupt Controller. The

programmable system interrupts are generated internally by the various LAN9312 sub-modules and

can be configured to generate a single external host interrupt via the IRQ interrupt output pin. The

programmable nature of the host interrupt provides the user with the ability to optimize performance

dependent upon the application requirements. The IRQ interrupt buffer type, polarity, and de-assertion

interval are modifiable. The IRQ interrupt can be configured as an open-drain output to facilitate the

sharing of interrupts with other devices. All internal interrupts are maskable and capable of triggering

the IRQ interrupt.

5.2

Interrupt Sources

The LAN9312 is capable of generating the following interrupt types:

„

1588 Time Stamp Interrupts (Port 2,1,0 and GPIO 9,8)

Switch Fabric Interrupts (Buffer Manager, Switch Engine, and Port 2,1,0 MACs)

Ethernet PHY Interrupts (Port 1,2 PHYs)

GPIO Interrupts (GPIO[11:0])

Host MAC Interrupts (FIFOs)

Power Management Interrupts

General Purpose Timer Interrupt (GPT)

Software Interrupt (General Purpose)

Device Ready Interrupt

All interrupts are accessed and configured via registers arranged into a multi-tier, branch-like structure,

as shown in Figure 5.1. At the top level of the LAN9312 interrupt structure are the Interrupt Status

(IRQ_CFG).

The Interrupt Status Register (INT_STS) and Interrupt Enable Register (INT_EN) aggregate and

enable/disable all interrupts from the various LAN9312 sub-modules, combining them together to

create the IRQ interrupt. These registers provide direct interrupt access/configuration to the Host MAC,

General Purpose Timer, software, and device ready interrupts. These interrupts can be monitored,

enabled/disabled, and cleared, directly within these two registers. In addition, interrupt event

indications are provided for the 1588 Time Stamp, Switch Fabric, Port 1 & 2 Ethernet PHYs, Power

Management, and GPIO interrupts. These interrupts differ in that the interrupt sources are generated

and cleared in other sub-block registers. The INT_STS register does not provide details on what

specific event within the sub-module caused the interrupt, and requires the software to poll an

additional sub-module interrupt register (as shown in Figure 5.1) to determine the exact interrupt

source and clear it. For interrupts which involve multiple registers, only after the interrupt has been

serviced and cleared at its source will it be cleared in the INT_STS register.

The Interrupt Configuration Register (IRQ_CFG) is responsible for enabling/disabling the IRQ interrupt

output pin as well as configuring its properties. The IRQ_CFG register allows the modification of the

IRQ pin buffer type, polarity, and de-assertion interval. The de-assertion timer guarantees a minimum

interrupt de-assertion period for the IRQ output and is programmable via the INT_DEAS field of the

Interrupt Configuration Register (IRQ_CFG). A setting of all zeros disables the de-assertion timer. The

de-assertion interval starts when the IRQ pin de-asserts, regardless of the reason.

Note: The de-assertion timer does not apply to the PME interrupt. Assertion of the PME interrupt

does not affect the de-assertion timer.

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Top Level Interrupt Registers

(System CSRs)

INT_CFG

INT_STS

INT_EN

1588 Time Stamp Interrupt Register

Bit 29 (1588_EVNT)

of INT_STS register

1588_INT_STS_EN

Switch Fabric Interrupt Registers

Bit 28 (SWITCH_INT)

of INT_STS register

SW_IMR

SW_IPR

Buffer Manager Interrupt Registers

Bit 6 (BM)

BM_IMR

of SW_IPR register

BM_IPR

Switch Engine Interrupt Registers

Bit 5 (SWE)

SWE_IMR

of SW_IPR register

SWE_IPR

Port [2,1,0] MAC Interrupt Registers

Bits [2,1,0] (MAC_[2,1,MII])

MAC_IMR_[2,1,MII]

of SW_IPR register

MAC_IPR_[2,1,MII]

Port 2 PHY Interrupt Registers

PHY_INTERRUPT_SOURCE_2

PHY_INTERRUPT_MASK_2

Bit 27 (PHY_INT2)

of INT_STS register

Port 1 PHY Interrupt Registers

PHY_INTERRUPT_SOURCE_1

PHY_INTERRUPT_MASK_1

Bit 26 (PHY_INT1)

of INT_STS register

Power Management Control Register

Bit 17 (PME_INT)

of INT_STS register

PMT_CTRL

GPIO Interrupt Register

Bit 12 (GPIO)

of INT_STS register

GPIO_INT_STS_EN

Figure 5.1 Functional Interrupt Register Hierarchy

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The following sections detail each category of interrupts and their related registers. Refer to

Chapter 14, "Register Descriptions," on page 166 for bit-level definitions of all interrupt registers.

5.2.1

1588 Time Stamp Interrupts

Multiple 1588 Time Stamp interrupt sources are provided by the LAN9312. The top-level 1588_EVNT

(bit 29) of the Interrupt Status Register (INT_STS) provides indication that a 1588 interrupt event

occurred in the 1588 Interrupt Status and Enable Register (1588_INT_STS_EN).

The 1588 Interrupt Status and Enable Register (1588_INT_STS_EN) provides enabling/disabling and

status of all 1588 interrupt conditions. These include TX/RX 1588 clock capture indication on Ports

2,1,0, 1588 clock capture for GPIO[8:9] events, as well as 1588 timer interrupt indication.

In order for a 1588 interrupt event to trigger the external IRQ interrupt pin, the desired 1588 interrupt

event must be enabled in the 1588 Interrupt Status and Enable Register (1588_INT_STS_EN), bit 29

(1588_EVNT_EN) of the Interrupt Enable Register (INT_EN) must be set, and IRQ output must be

enabled via bit 8 (IRQ_EN) of the Interrupt Configuration Register (IRQ_CFG).

For additional details on the 1588 Time Stamp interrupts, refer to Section 11.6, "IEEE 1588 Interrupts,"

on page 160.

5.2.2

Switch Fabric Interrupts

Multiple Switch Fabric interrupt sources are provided by the LAN9312 in a three-tiered register

structure as shown in Figure 5.1. The top-level SWITCH_INT (bit 28) of the Interrupt Status Register

(INT_STS) provides indication that a Switch Fabric interrupt event occurred in the Switch Engine

Interrupt Pending Register (SWE_IPR).

In turn, the Switch Engine Interrupt Pending Register (SWE_IPR) and Switch Engine Interrupt Mask

(Buffer Manager, Switch Engine, and Port 2,1,0 MACs).

The low-level Switch Fabric sub-module interrupt pending and mask registers of the Buffer Manager,

Switch Engine, and Port 2,1,0 MACs provide multiple interrupt sources from their respective sub-

modules. These low-level registers provide the following interrupt sources:

„

Buffer Manager (Buffer Manager Interrupt Mask Register (BM_IMR) and Buffer Manager Interrupt

Pending Register (BM_IPR))

—Status B Pending

—Status A Pending

„

Switch Engine (Switch Engine Interrupt Mask Register (SWE_IMR) and Switch Engine Interrupt

Pending Register (SWE_IPR))

—Interrupt Pending

Port 2,1,0 MACs (Port x MAC Interrupt Mask Register (MAC_IMR_x) and Port x MAC Interrupt

Pending Register (MAC_IPR_x))

—No currently supported interrupt sources. These registers are reserved for future use.

In order for a Switch Fabric interrupt event to trigger the external IRQ interrupt pin, the following must

be configured:

„

The desired Switch Fabric sub-module interrupt event must be enabled in the corresponding mask

Interrupt Mask Register (SWE_IMR) for the Switch Engine, and/or Port x MAC Interrupt Mask

„

The desired Switch Fabric sub-module interrupt event must be enabled in the Switch Engine

Interrupt Mask Register (SWE_IMR)

„

Bit 28 (SWITCH_INT_EN) of the Interrupt Enable Register (INT_EN) must be set

IRQ output must be enabled via bit 8 (IRQ_EN) of the Interrupt Configuration Register (IRQ_CFG)

For additional details on the Switch Fabric interrupts, refer to Section 6.6, "Switch Fabric Interrupts,"

on page 81.

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5.2.3

Ethernet PHY Interrupts

The Port 1 and Port 2 PHYs each provide a set of identical interrupt sources. The top-level PHY_INT1

(bit 26) and PHY_INT2 (bit 27) of the Interrupt Status Register (INT_STS) provides indication that a

PHY interrupt event occurred in the P ort x PHY Interrupt Source Flags Register

(PHY_INTERRUPT_SOURCE_x).

Port 1 and Port 2 PHY interrupts are enabled/disabled via their respective Port x PHY Interrupt Mask

via the Port x PHY Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x). The Port 1 and

Port 2 PHYs are each capable of generating unique interrupts based on the following events:

„

ENERGYON Activated

Auto-Negotiation Complete

Remote Fault Detected

Link Down (Link Status Negated)

Auto-Negotiation LP Acknowledge

Parallel Detection Fault

Auto-Negotiation Page Received

In order for a Port 1 or Port 2 interrupt event to trigger the external IRQ interrupt pin, the desired PHY

interrupt event must be enabled in the corresponding Port x PHY Interrupt Mask Register

(PHY_INTERRUPT_MASK_x), the PHY_INT1(Port 1 PHY) and/or PHY_INT2(Port 2 PHY) bits of the

Interrupt Enable Register (INT_EN) must be set, and IRQ output must be enabled via bit 8 (IRQ_EN)

of the Interrupt Configuration Register (IRQ_CFG).

For additional details on the Ethernet PHY interrupts, refer to Section 7.2.8.1, "PHY Interrupts," on

page 94.

5.2.4

GPIO Interrupts

Each GPIO[11:0] of the LAN9312 is provided with its own interrupt. The top-level GPIO (bit 12) of the

Interrupt Status Register (INT_STS) provides indication that a GPIO interrupt event occurred in the

General Purpose I/O Interrupt Status and Enable Register (GPIO_INT_STS_EN). The General

Purpose I/O Interrupt Status and Enable Register (GPIO_INT_STS_EN) provides enabling/disabling

and status of each GPIO[11:0] interrupt.

In order for a GPIO interrupt event to trigger the external IRQ interrupt pin, the desired GPIO interrupt

must be enabled in the G eneral Purpose I/O Interrupt Status and Enable Register

(GPIO_INT_STS_EN), bit 12 (GPIO_EN) of the Interrupt Enable Register (INT_EN) must be set, and

IRQ output must be enabled via bit 8 (IRQ_EN) of the Interrupt Configuration Register (IRQ_CFG).

For additional details on the GPIO interrupts, refer to Section 13.2.2, "GPIO Interrupts," on page 163.

5.2.5

Host MAC Interrupts

The top-level Interrupt Status Register (INT_STS), and Interrupt Enable Register (INT_EN) provide the

status and enabling/disabling of multiple Host MAC related interrupts. All Host MAC interrupts are

monitored and configured directly within these two registers. The following Host MAC related interrupt

events are supported:

„

TX Stopped

RX Stopped

RX Dropped Frame Counter Halfway

TX IOC

RX DMA

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„

TX Status FIFO Overflow

Receive Watchdog Time-Out

Receiver Error

Transmitter Error

TX Data FIFO Underrun

TX Data FIFO Overrun

TX Data FIFO Available

TX Status FIFO Full

TX Status FIFO Level

RX Dropped Frame

RX Data FIFO Level

RX Status FIFO Full

RX Status FIFO Level

In order for a Host MAC interrupt event to trigger the external IRQ interrupt pin, the desired Host MAC

interrupt event must be enabled in the Interrupt Enable Register (INT_EN), and IRQ output must be

enabled via bit 8 (IRQ_EN) of the Interrupt Configuration Register (IRQ_CFG).

Refer to the Interrupt Status Register (INT_STS) on page 174 and Chapter 9, "Host MAC," on page 112

for additional information on bit definitions and Host MAC operation.

5.2.6

Power Management Interrupts

Multiple Power Management Event interrupt sources are provided by the LAN9312. The top-level

PME_INT (bit 17) of the Interrupt Status Register (INT_STS) provides indication that a Power

Management interrupt event occurred in the Power Management Control Register (PMT_CTRL).

The Power Management Control Register (PMT_CTRL) provides enabling/disabling and status of all

Power Management conditions. These include energy-detect on the Port 1/2 PHYs, and Wake-On-LAN

(wake-up frame or magic packet) detection by the Host MAC.

In order for a Power Management interrupt event to trigger the external IRQ interrupt pin, the desired

Power Management interrupt event must be enabled in the Power Management Control Register

(PMT_CTRL) (bits 15, 14, and/or 9), bit 17 (PME_INT_EN) of the Interrupt Enable Register (INT_EN)

must be set, and IRQ output must be enabled via bit 8 (IRQ_EN) of the Interrupt Configuration Register

(IRQ_CFG).

For additional details on power management, refer to Section 4.3, "Power Management," on page 46.

5.2.7

General Purpose Timer Interrupt

A General Purpose Timer (GPT) interrupt is provided in the top-level Interrupt Status Register

(INT_STS) and Interrupt Enable Register (INT_EN) (bit 19). This interrupt is issued when the General

Purpose Timer Configuration Register (GPT_CFG) wraps past zero to FFFFh, and is cleared when bit

19 of the Interrupt Status Register (INT_STS) is written with 1.

In order for a General Purpose Timer interrupt event to trigger the external IRQ interrupt pin, the GPT

must be enabled via the bit 29 (TIMER_EN) in the General Purpose Timer Configuration Register

(GPT_CFG), bit 19 of the Interrupt Enable Register (INT_EN) must be set, and IRQ output must be

enabled via bit 8 (IRQ_EN) of the Interrupt Configuration Register (IRQ_CFG).

For additional details on the General Purpose Timer, refer to Section 12.1, "General Purpose Timer,"

on page 161.

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5.2.8

5.2.9

Software Interrupt

A general purpose software interrupt is provided in the top level Interrupt Status Register (INT_STS)

and Interrupt Enable Register (INT_EN). The SW_INT interrupt (bit 31) of the Interrupt Status Register

(INT_STS) is generated when SW_INT_EN (bit 31) of the Interrupt Enable Register (INT_EN) is set.

This interrupt provides an easy way for software to generate an interrupt, and is designed for general

software usage.

Device Ready Interrupt

A device ready interrupt is provided in the top-level Interrupt Status Register (INT_STS) and Interrupt

Enable Register (INT_EN). The READY interrupt (bit 30) of the Interrupt Status Register (INT_STS)

indicates that the LAN9312 is ready to be accessed after a power-up or reset condition. Writing a 1 to

this bit in the Interrupt Status Register (INT_STS) will clear it.

In order for a device ready interrupt event to trigger the external IRQ interrupt pin, bit 30 of the Interrupt

Enable Register (INT_EN) must be set, and IRQ output must be enabled via bit 8 (IRQ_EN) of the

Interrupt Configuration Register (IRQ_CFG).

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Chapter 6 Switch Fabric

6.1

Functional Overview

At the core of the LAN9312 is the high performance, high efficiency 3 port Ethernet switch fabric. The

switch fabric contains a 3 port VLAN layer 2 switch engine that supports untagged, VLAN tagged, and

priority tagged frames. The switch fabric provides an extensive feature set which includes spanning

tree protocol support, multicast packet filtering and Quality of Service (QoS) packet prioritization by

VLAN tag, destination address, port default value or DIFFSERV/TOS, allowing for a range of

prioritization implementations. 32K of buffer RAM allows for the storage of multiple packets while

forwarding operations are completed, and a 1K entry forwarding table provides room for MAC address

forwarding tables. Each port is allocated a cluster of 4 dynamic QoS queues which allow each queue

size to grow and shrink with traffic, effectively utilizing all available memory. This memory is managed

dynamically via the buffer manager block within the switch fabric. All aspects of the switch fabric are

managed via the switch fabric configuration and status registers (CSR), which are indirectly accessible

via the memory mapped system control and status registers.

The switch fabric consists of four major block types:

„

Switch Fabric CSRs - These registers provide access to various switch fabric parameters for

configuration and monitoring.

10/100 Ethernet MACs - A total of three MACs are included in the switch fabric which provide basic

10/100 Ethernet functionality for each switch fabric port.

Switch Engine (SWE) - This block is the core of the switch fabric and provides VLAN layer 2

switching for all three switch ports.

Buffer Manager (BM) - This block provides control of the free buffer space, transmit queues, and

scheduling.

Refer to Figure 2.1 Internal LAN9312 Block Diagram on page 21 for details on the interconnection of

the switch fabric blocks within the LAN9312.

6.2

Switch Fabric CSRs

The switch fabric CSRs provide register level access to the various parameters of the switch fabric.

Switch fabric related registers can be classified into two main categories based upon their method of

access: direct and indirect.

The directly accessible switch fabric registers are part of the main system CSRs of the LAN9312 and

are detailed in Section 14.2.6, "Switch Fabric," on page 229. These registers provide switch fabric

manual flow control (Ports 0-2), data/command registers (for access to the indirect switch fabric

registers), and switch MAC address configuration.

The indirectly accessible switch fabric registers reside within the switch fabric and must be accessed

indirectly via the Switch Fabric CSR Interface Data Register (SWITCH_CSR_DATA) and Switch Fabric

CSR Interface Command Register (SWITCH_CSR_CMD), or the set of Switch Fabric CSR Interface

Direct Data Register (SWITCH_CSR_DIRECT_DATA). The indirectly accessible switch fabric CSRs

provide full access to the many configurable parameters of the switch engine, buffer manager, and

each switch port. The switch fabric CSRs are detailed in Section 14.5, "Switch Fabric Control and

Status Registers," on page 307.

For detailed descriptions of all switch fabric related registers, refer to Chapter 14, "Register

Descriptions," on page 166.

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6.2.1

Switch Fabric CSR Writes

To perform a write to an individual switch fabric register, the desired data must first be written into the

Switch Fabric CSR Interface Data Register (SWITCH_CSR_DATA). The write cycle is initiated by

performing a single write to the S witch Fabric CSR Interface Command Register

(SWITCH_CSR_CMD) with CSR_BUSY (bit 31) set, the CSR_ADDRESS field (bits 15:0) set to the

desired register address, the R_nW (bit 30) cleared, the AUTO_INC and AUTO_DEC fields cleared,

and the desired CSR byte enable bits selected (bits 19:16). The completion of the write cycle is

indicated by the clearing of the CSR_BUSY bit.

A second write method may be used which utilizes the auto increment/decrement function of the

Switch Fabric CSR Interface Command Register (SWITCH_CSR_CMD) for writing sequential register

addresses. When using this method, the Switch Fabric CSR Interface Command Register

(SWITCH_CSR_CMD) must first be written with the auto increment(AUTO_INC) or auto

decrement(AUTO_DEC) bit set, the CSR_ADDRESS field written with the desired register address, the

R_nW bit cleared, and the desired CSR byte enable bits selected (typically all set). The write cycles

are then initiated by writing the desired data into the Switch Fabric CSR Interface Data Register

(SWITCH_CSR_DATA). The completion of the write cycle is indicated by the clearing of the

CSR_BUSY bit, at which time the address in the Switch Fabric CSR Interface Command Register

(SWITCH_CSR_CMD) is incremented or decremented accordingly. The user may then initiate a

subsequent write cycle by writing the desired data into the Switch Fabric CSR Interface Data Register

(SWITCH_CSR_DATA).

The third write method is to use the direct data range write function. Writes within the Switch Fabric

CSR Interface Direct Data Register (SWITCH_CSR_DIRECT_DATA) address range automatically set

the appropriate register address, set all four byte enable bits (CSR_BE[3:0]), clears the R_nW bit, and

sets the CSR_BUSY bit of the S witch Fabric CSR Interface Command Register

(SWITCH_CSR_CMD). The completion of the write cycle is indicated by the clearing of the

CSR_BUSY bit. Since the address range of the switch fabric CSRs exceeds that of the Switch Fabric

CSR Interface Direct Data Register (SWITCH_CSR_DIRECT_DATA) address range, a sub-set of the

switch fabric CSRs are mapped to the Switch Fabric CSR Interface Direct Data Register

(SWITCH_CSR_DIRECT_DATA) address range as detailed in T a ble 14.3, “Switch Fabric CSR to

SWITCH_CSR_DIRECT_DATA Address Range Map,” on page 240.

Figure 6.1 illustrates the process required to perform a switch fabric CSR write. The minimum wait

periods as specified in T a ble 8.1, “Read After Write Timing Rules,” on page 102 are required where

noted.

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CSR Write Auto

CSR Write Direct

Address

CSR Write

Increment /

Decrement

Idle

Write

Direct

Data

Write

Command

Write Data

Range

min wait period

Write

Command

Read

Command

Write Data

CSR_BUSY = 0

CSR_BUSY = 1

min wait period

Read

Command

CSR_BUSY = 0

CSR_BUSY = 1

CSR_BUSY = 0

CSR_BUSY = 1

Figure 6.1 Switch Fabric CSR Write Access Flow Diagram

6.2.2

Switch Fabric CSR Reads

To perform a read of an individual switch fabric register, the read cycle must be initiated by performing

a single write to the Switch Fabric CSR Interface Command Register (SWITCH_CSR_CMD) with

CSR_BUSY (bit 31) set, the CSR_ADDRESS field (bits 15:0) set to the desired register address, the

R_nW (bit 30) set, and the AUTO_INC and AUTO_DEC fields cleared. Valid data is available for

reading when the CSR_BUSY bit is cleared, indicating that the data can be read from the Switch Fabric

CSR Interface Data Register (SWITCH_CSR_DATA).

A second read method may be used which utilizes the auto increment/decrement function of the Switch

Fabric CSR Interface Command Register (SWITCH_CSR_CMD) for reading sequential register

addresses. When using this method, the Switch Fabric CSR Interface Command Register

(SWITCH_CSR_CMD) must first be written with the auto increment(AUTO_INC) or auto

decrement(AUTO_DEC) bit set, the CSR_ADDRESS field written with the desired register address,

and the R_nW bit set. The completion of a read cycle is indicated by the clearing of the CSR_BUSY

bit, at which time the data can be read from the Switch Fabric CSR Interface Data Register

(SWITCH_CSR_DATA). When the data is read, the address in the Switch Fabric CSR Interface

Command Register (SWITCH_CSR_CMD) is incremented or decremented accordingly, and another

read cycle is started automatically. The user should clear the AUTO_INC and AUTO_DEC bits before

reading the last data to avoid an unintended read cycle.

Figure 6.2 illustrates the process required to perform a switch fabric CSR read. The minimum wait

periods as specified in T a ble 8.1, “Read After Write Timing Rules,” on page 102 are required where

noted.

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CSR Read Auto

CSR Read

Increment /

Decrement

Idle

Write

Command

min wait period

CSR_BUSY = 1

Read

Command

CSR_BUSY = 0

last

data?

Read Data

Yes

Write

Command

Read Data

Figure 6.2 Switch Fabric CSR Read Access Flow Diagram

6.2.3

Flow Control Enable Logic

Each switch fabric port (0,1,2) is provided with two flow control enable inputs per port, one for

transmission and one for reception. Flow control on transmission allows the transmitter to generate

back pressure in half-duplex mode, and pause packets in full-duplex. Flow control in reception enables

the reception of pause packets to pause transmissions.

The state of these enables is based on the state of the ports duplex and Auto-negotiation settings and

the values of the corresponding Manual Flow Control register (Port 1 Manual Flow Control Register

(MANUAL_FC_1), Port 2 Manual Flow Control Register (MANUAL_FC_2), or Port 0(Host MAC)

Manual Flow Control Register (MANUAL_FC_MII)). T a ble 6.1 details the switch fabric flow control

enable logic.

When in half-duplex mode, the transmit flow control (back pressure) enable is determined directly by

the BP_EN_x bit of the ports manual flow control register. When Auto-negotiation is disabled, or the

MANUAL_FC_x bit of the ports manual flow control register is set, the switch port flow control enables

during full-duplex are determined by the TX_FC_x and RX_FC_x bits of the ports manual flow control

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control enables during full-duplex are determined by Auto-negotiation.

Note: The flow control values in the Port x PHY Auto-Negotiation Advertisement Register

(PHY_AN_ADV_x) and Virtual PHY Auto-Negotiation Advertisement Register

(VPHY_AN_ADV) are not affected by the values of the manual flow control register. Refer to

Section 7.2.5.1, "PHY Pause Flow Control," on page 92 and Section 7.3.1.3, "Virtual PHY

Pause Flow Control," on page 98 for additional information on PHY and Virtual PHY flow

control settings respectively.

Table 6.1 Switch Fabric Flow Control Enable Logic

BP_EN_x

Half

BP_EN_x

TX_FC_x

RX_FC_x

Full

RX_FC_x

Full

BP_EN_x

Half (Note 6.1)

Half

BP_EN_x

Full

Note 6.1 If Auto-negotiation is enabled and complete, but the link partner is not Auto-negotiation

capable, half-duplex is forced via the parallel detect function.

Note 6.2 For the Port 1 and Port 2 PHYs, these are the bits from the Port x PHY Auto-Negotiation

Advertisement Register (PHY_AN_ADV_x) and Port x PHY Auto-Negotiation Link Partner

Base Page Ability Register (PHY_AN_LP_BASE_ABILITY_x). For the Virtual PHY, these

are the local/partner swapped outputs from the bits in the Virtual PHY Auto-Negotiation

Advertisement Register (VPHY_AN_ADV) and Virtual PHY Auto-Negotiation Link Partner

Base Page Ability Register (VPHY_AN_LP_BASE_ABILITY). Refer to Section 7.3.1,

"Virtual PHY Auto-Negotiation," on page 96 for more information.

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Per T a ble 6.1, the following cases are possible:

„

Case 1 - Auto-negotiation is still in progress. Since the result is not yet established, flow control is

disabled.

„

Case 2 - Auto-negotiation is enabled and unsuccessful (link partner not Auto-negotiation capable).

The link partner ability is undefined, effectively a don’t-care value, in this case. The duplex setting

will default to half-duplex in this case. Flow control is determined by the BP_EN_x bit.

„

Case 3 - Auto-negotiation is enabled and successful with half-duplex as a result. The link partner

ability is undefined since it only applies to full-duplex operation. Flow control is determined by the

BP_EN_x bit.

Cases 4-11 -Auto-negotiation is enabled and successful with full-duplex as the result. In these

cases, the advertisement registers and the link partner ability controls the RX and TX enables.

These cases match IEEE 802.3 Annex 28B.3.

„Cases 4,5,6,8,10 - No flow control enabled

„Case 7 - Asymmetric pause towards partner (away from switch port)

„Case 9 - Symmetric pause

„Case 11 - Asymmetric pause from partner (towards switch port)

6.3

10/100 Ethernet MACs

The switch fabric contains three 10/100 MAC blocks, one for each switch port (0,1,2). The 10/100 MAC

provides the basic 10/100 Ethernet functionality, including transmission deferral and collision back-

off/retry, receive/transmit FCS checking and generation, receive/transmit pause flow control, and

transmit back pressure. The 10/100 MAC also includes RX and TX FIFOs and per port statistic

counters.

6.3.1

Receive MAC

The receive MAC (IEEE 802.3) sublayer decomposes Ethernet packets acquired via the internal MII

interface by stripping off the preamble sequence and Start of Frame Delimiter (SFD). The receive MAC

checks the FCS, the MAC Control Type, and the byte count against the drop conditions. The packet

is stored in the RX FIFO as it is received.

The receive MAC determines the validity of each received packet by checking the Type field, FCS, and

oversize or undersize conditions. All bad packets will be either immediately dropped or marked (at the

end) as bad packets.

Oversized packets are normally truncated at 1519 or 1523 (VLAN tagged) octets and marked as

erroneous. The MAC can be configured to accept packets up to 2048 octets (inclusive), in which case

the oversize packets are truncated at 2048 bytes and marked as erroneous.

Undersized packets are defined as packets with a length less than the minimum packet size. The

minimum packet size is defined to be 64 bytes, exclusive of preamble sequence and SFD.

The FCS and length/type fields of the frame is checked to detect if the packet has a valid MAC control

frame. When the MAC receives a MAC control frame with a valid FCS and determines the operation

code is a pause command (Flow Control frame), the MAC will load its internal pause counter with the

Number_of_Slots variable from the MAC control frame just received. Anytime the internal pause

counter is zero, the transmit MAC will be allowed to transmit (XON). If the internal pause counter is

not zero, the receive MAC will not allow the transmit MAC to transmit (XOFF). When the transmit MAC

detects an XOFF condition it will continue to transmit the current packet, terminating transmission after

the current packet has been transmitted until receiving the XON condition from the receive MAC. The

pause counter will begin to decrement at then end of the current transmission, or immediately if no

transmission is underway. If another pause command is received while the transmitter is already in

pause, the new pause time indicated by the Flow Control packet will be loaded into the pause counter.

The pause function is enabled by either Auto-negotiation, or manually as discussed in Section 6.2.3,

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"Flow Control Enable Logic," on page 58. Pause frames are consumed by the MAC and not sent to

the switch engine. Non-pause control frames are optionally filtered or forwarded.

When the receive FIFO is full and additional data continues to be received, an overrun condition occurs

and the frame is discarded (FIFO space recovered) or marked as a bad frame.

The receive MAC can be disabled from receiving all frames by clearing the RX Enable bit of the Port

x MAC Receive Configuration Register (MAC_RX_CFG_x).

The size of the RX FIFO is 256 bytes. If a bad packet with less than 64 bytes is received, it will be

flushed from the FIFO automatically and the FIFO space recovered. Packets equal to or larger than

64 bytes with an error will be marked and reported to the switch engine. The switch engine will

subsequently drop the packet.

6.3.1.1

Receive Counters

The receive MAC gathers statistics on each packet and increments the related counter registers. The

following receive counters are supported for each switch fabric port. Refer to T a ble 14.12, “Indirectly

Accessible Switch Control and Status Registers,” on page 307 and Section 14.5.2.3 through

Section 14.5.2.22 for detailed descriptions of these counters.

„

Total undersized packets (Section 14.5.2.3, on page 324)

Total packets 64 bytes in size (Section 14.5.2.4, on page 325)

Total packets 65 through 127 bytes in size (Section 14.5.2.5, on page 326)

Total packets 128 through 255 bytes in size (Section 14.5.2.6, on page 327)

Total packets 256 through 511 bytes in size (Section 14.5.2.7, on page 328)

Total packets 512 through 1023 bytes in size (Section 14.5.2.8, on page 329)

Total packets 1024 through maximum bytes in size (Section 14.5.2.9, on page 330)

Total oversized packets (Section 14.5.2.10, on page 331)

Total OK packets (Section 14.5.2.11, on page 332)

Total packets with CRC errors (Section 14.5.2.12, on page 333)

Total multicast packets (Section 14.5.2.13, on page 334)

Total broadcast packets (Section 14.5.2.14, on page 335)

Total MAC Pause packets (Section 14.5.2.15, on page 336)

Total fragment packets (Section 14.5.2.16, on page 337)

Total jabber packets (Section 14.5.2.17, on page 338)

Total alignment errors (Section 14.5.2.18, on page 339)

Total bytes received from all packets (Section 14.5.2.19, on page 340)

Total bytes received from good packets (Section 14.5.2.20, on page 341)

Total packets with a symbol error (Section 14.5.2.21, on page 342)

Total MAC control packets (Section 14.5.2.22, on page 343)

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6.3.2

Transmit MAC

The transmit MAC generates an Ethernet MAC frame from TX FIFO data. This includes generating the

preamble and SFD, calculating and appending the frame checksum value, optionally padding

undersize packets to meet the minimum packet requirement size (64 bytes), and maintaining a

standard inter-frame gap time during transmit.

The transmit MAC can operate at 10/100Mbps, half- or full-duplex, and with or without flow control

depending on the state of the transmission. In half-duplex mode the transmit MAC meets CSMA/CD

IEEE 802.3 requirements. The transmit MAC will re-transmit if collisions occur during the first 64 bytes

(normal collisions), or will discard the packet if collisions occur after the first 64 bytes (late collisions).

The transmit MAC follows the standard truncated binary exponential back-off algorithm, collision and

jamming procedures.

The transmit MAC pre-pends the standard preamble and SFD to every packet from the FIFO. The

transmit MAC also follows as default, the standard Inter-Frame Gap (IFG). The default IFG is 96 bit

times and can be adjusted via the IFG Config field of the Port x MAC Transmit Configuration Register

(MAC_TX_CFG_x).

Packet padding and cyclic redundant code (FCS) calculation may be optionally performed by the

transmit MAC. The auto-padding process automatically adds enough zeros to packets shorter than 64

bytes. The auto-padding and FCS generation is controlled via the TX Pad Enable bit of the Port x MAC

Transmit Configuration Register (MAC_TX_CFG_x).

The transmit FIFO acts as a temporary buffer between the transmit MAC and the switch engine. The

FIFO logic manages the re-transmission for normal collision conditions or discards the frames for late

or excessive collisions.

When in full-duplex mode, the transmit MAC uses the flow-control algorithm specified in IEEE 802.3.

MAC pause frames are used primarily for flow control packets, which pass signalling information

between stations. MAC pause frames have a unique type of 8808h, and a pause op-code of 0001h.

The MAC pause frame contains the pause value in the data field. The flow control manager will auto-

adapt the procedure based on traffic volume and speed to avoid packet loss and unnecessary pause

periods.

When in half-duplex mode, the MAC uses a back pressure algorithm. The back pressure algorithm is

based on a forced collision and an aggressive back-off algorithm.

6.3.2.1

Transmit Counters

The transmit MAC gathers statistics on each packet and increments the related counter registers. The

following transmit counters are supported for each switch fabric port. Refer to T a ble 14.12, “Indirectly

Accessible Switch Control and Status Registers,” on page 307 and Section 14.5.2.25 through

Section 14.5.2.42 for detailed descriptions of these counters.

„

Total packets deferred (Section 14.5.2.25, on page 346)

Total pause packets (Section 14.5.2.26, on page 347)

Total OK packets (Section 14.5.2.27, on page 348)

Total packets 64 bytes in size (Section 14.5.2.28, on page 349)

Total packets 65 through 127 bytes in size (Section 14.5.2.29, on page 350)

Total packets 128 through 255 bytes in size (Section 14.5.2.30, on page 351)

Total packets 256 through 511 bytes in size (Section 14.5.2.31, on page 352)

Total packets 512 through 1023 bytes in size (Section 14.5.2.32, on page 353)

Total packets 1024 through maximum bytes in size (Section 14.5.2.33, on page 354)

Total undersized packets (Section 14.5.2.34, on page 355)

Total bytes transmitted from all packets (Section 14.5.2.35, on page 356)

Total broadcast packets (Section 14.5.2.36, on page 357)

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„

Total multicast packets (Section 14.5.2.37, on page 358)

Total packets with a late collision (Section 14.5.2.38, on page 359)

Total packets with excessive collisions (Section 14.5.2.39, on page 360)

Total packets with a single collision (Section 14.5.2.40, on page 361)

Total packets with multiple collisions (Section 14.5.2.41, on page 362)

Total collision count (Section 14.5.2.42, on page 363)

6.4

Switch Engine (SWE)

The switch engine (SWE) is a VLAN layer 2 (link layer) switching engine supporting 3 ports. The SWE

supports the following types of frame formats: untagged frames, VLAN tagged frames, and priority

tagged frames. The SWE supports both the 802.3 and Ethernet II frame formats.

The SWE provides the control for all forwarding/filtering rules. It handles the address learning and

aging, and the destination port resolution based upon the MAC address and VLAN of the packet. The

SWE implements the standard bridge port states for spanning tree and provides packet metering for

input rate control. It also implements port mirroring, broadcast throttling, and multicast pruning and

filtering. Packet priorities are supported based on the IPv4 TOS bits and IPv6 Traffic Class bits using

a DIFFSERV Table mapping, the non-DIFFSERV mapped IPv4 precedence bits, VLAN priority using

a per port Priority Regeneration Table, DA based static priority, and Traffic Class mapping to one of 4

QoS transmit priority queues.

The following sections detail the various features of the switch engine.

6.4.1

MAC Address Lookup Table

The Address Logic Resolution (ALR) maintains a 1024 entry MAC Address Table. The ALR searches

the table for the destination MAC address. If the search finds a match, the associated data is returned

indicating the destination port or ports, whether to filter the packet, the packets priority (used if

enabled), and whether to override the ingress and egress spanning tree port state. Figure 6.3 displays

the ALR table entry structure. Refer to the Switch Engine ALR Write Data 0 Register

(SWE_ALR_WR_DAT_0) and Switch Engine ALR Write Data 1 Register (SWE_ALR_WR_DAT_1) for

detailed descriptions of these bits.

...

Bit

Valid

Age /

Override

Static

Filter

Priority

Port

MAC Address

Figure 6.3 ALR Table Entry Structure

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6.4.1.1

Learning/Aging/Migration

The ALR adds new MAC addresses upon ingress along with the associated receive port.

If the source MAC address already exists, the entry is refreshed. This action serves two purposes.

First, if the source port has changed due to a network reconfiguration (migration), it is updated.

Second, each instance the entry is refreshed, the aging status bit is set, keeping the entry active.

Learning can be disabled per port via the Enable Learning on Ingress field of the Switch Engine Port

Ingress Configuration Register (SWE_PORT_INGRSS_CFG).

During each aging period, the ALR scans the learned MAC addresses. For entries which have the

aging status bit set, the ALR simply clears the bit. As mentioned above, if a MAC address is

subsequently refreshed, the aging bit will be set again and the process would repeat. If a learned entry

already had its aging status bit cleared (by a previous scan), the ALR will instead remove the learned

entry. Therefore, if two scans occur before a MAC address is refreshed, the entry will be aged and

removed. Each aging period is approximately 5 minutes. Therefore an entry will be aged and removed

at a minimum of 5 minutes, and a maximum of 10 minutes.

6.4.1.2

6.4.1.3

Static Entries

If a MAC address entry is manually added by the host CPU, it can be (and typically is) marked as

static. Static entries are not subjected to the aging process. Static entries also cannot be changed by

the learning process (including migration).

Multicast Pruning

The destination port that is returned as a result of a destination MAC address lookup may be a single

port or any combination of ports. The latter is used to setup multicast address groups. An entry with

a multicast MAC address would be entered manually by the host CPU with the appropriate destination

port(s). Typically, the Static bit should also be set to prevent automatic aging of the entry.

6.4.1.4

6.4.1.5

Address Filtering

Filtering can be performed on a destination MAC address. Such an entry would be entered manually

by the host CPU with the Filter bit active. Typically, the Static bit should also be set to prevent

automatic aging of the entry.

Spanning Tree Port State Override

A special spanning tree port state override setting can be applied to MAC address entries. When the

host CPU manually adds an entry with both the Static and Age bits set, packets with a matching

destination address will bypass the spanning tree port state and will be forwarded. This feature is

typically used to allow the reception of the BPDU packets while a port is in the non-forwarding state.

Refer to Section 6.4.5, "Spanning Tree Support," on page 70 for additional details.

6.4.1.6

6.4.1.7

MAC Destination Address Lookup Priority

If enabled in the S witch Engine Global Ingress Configuration Register

(SWE_GLOBAL_INGRSS_CFG), the transmit priority for static MAC address entries is taken from the

associated data of that entry.

Host Access

The ALR contains a learning engine that is used by the host CPU to add, delete, and modify the MAC

Address Table. This engine is accessed by using the Switch Engine ALR Command Register

(SWE_ALR_CMD), Switch Engine ALR Command Status Register (SWE_ALR_CMD_STS), Switch

Engine ALR Write Data 0 Register (SWE_ALR_WR_DAT_0), and Switch Engine ALR Write Data 1

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The following procedure should be followed in order to add, delete, and modify the ALR entries:

1. Write the Switch Engine ALR Write Data 0 Register (SWE_ALR_WR_DAT_0) and Switch Engine

ALR Write Data 1 Register (SWE_ALR_WR_DAT_1) with the desired MAC address and control

bits.

Note:An entry can be deleted by setting the Valid and Static bits to 0.

2. Write the Switch Engine ALR Command Register (SWE_ALR_CMD) register with 0004h (Make

Entry)

3. Poll the Make Pending bit in the Switch Engine ALR Command Status Register

(SWE_ALR_CMD_STS) until it is cleared.

4. Write the Switch Engine ALR Command Register (SWE_ALR_CMD) with 0000h.

The ALR contains a search engine that is used by the host to read the MAC Address Table. This

engine is accessed by using the Switch Engine ALR Command Register (SWE_ALR_CMD), Switch

Engine ALR Read Data 0 Register (SWE_ALR_RD_DAT_0), and Switch Engine ALR Read Data 1

Note: The entries read are not necessarily in the same order as they were learned or manually

added.

The following procedure should be followed in order to read the ALR entries:

1. Write the Switch Engine ALR Command Register (SWE_ALR_CMD) with 0002h (Get First Entry).

2. Write the Switch Engine ALR Command Register (SWE_ALR_CMD) with 0000h (Clear the Get

First Entry Bit)

3. Poll the Valid and End of Table bits in the Switch Engine ALR Read Data 1 Register

(SWE_ALR_RD_DAT_1) until either are set.

4. If the Valid bit is set, then the entry is valid and the data from the Switch Engine ALR Read Data

0 Register (SWE_ALR_RD_DAT_0) and Switch Engine ALR Read Data 1 Register

(SWE_ALR_RD_DAT_1) can be stored.

5. If the End of Table bit is set, then exit.

6. Write the Switch Engine ALR Command Register (SWE_ALR_CMD) with 0001h (Get Next Entry).

7. Write the Switch Engine ALR Command Register (SWE_ALR_CMD) with 0000h (Clear the Get

Next Entry bit)

8. Go to step 3.

Note: Refer to Section 14.5.3.1, on page 366 through Section 14.5.3.6, on page 373 for detailed

definitions of these registers.

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6.4.2

Forwarding Rules

Upon ingress, packets are filtered or forwarded based on the following rules:

„

If the destination port equals the source port (local traffic), the packet is filtered.

If the source port is not in the forwarding state, the packet is filtered (unless the Spanning Tree

Port State Override is in effect).

„

If the destination port is not in the forwarding state, the packet is filtered (unless the Spanning Tree

Port State Override is in effect).

„

If the Filter bit for the Destination Address is set in the ALR table, the packet is filtered.

If the packet has a unicast destination MAC address which is not found in the ALR table and the

Drop Unknown bit is set, the packet is filtered.

„

If the packet has a multicast destination MAC address which is not found in the ALR table and the

Filter Multicast bit is set, the packet is filtered.

If the packet has a broadcast destination MAC address and the Broadcast Storm Control level has

been reached, the packet is discarded.

„

If Drop on Yellow is set, the packet is colored Yellow, and randomly selected, it is discarded.

If Drop on Red is set and the packet is colored Red, it is discarded.

If the destination address was not found in the ALR table (an unknown or a broadcast) and the

Broadcast Buffer Level is exceeded, the packet is discarded.

„

If there is insufficient buffer space, the packet is discarded.

When the switch is enabled for VLAN support, these following rules also apply:

„

If the packet is untagged or priority tagged and the Admit Only VLAN bit for the ingress port is set,

the packet is filtered.

„

If the packet is tagged and has a VID equal to FFFh, it is filtered.

If Enable Membership Checking on Ingress is set, Admit Non Member is cleared, and the source

port is not a member of the incoming VLAN, the packet is filtered.

„

If Enable Membership Checking on Ingress is set and the destination port is not a member of the

incoming VLAN, the packet is filtered.

If the destination address was not found in the ALR table (as unknown or broadcast) and the VLAN

broadcast domain containment resulted in zero valid destination ports, the packet is filtered.

Note: For the last three cases, if the VID is not in the VLAN table, the VLAN is considered foreign

and the membership result is NULL. A NULL membership will result in the packet being filtered

if Enable Membership Checking is set. A NULL membership will also result in the packet being

filtered if the destination address is not found in the ALR table (since the packet would have

no destinations).

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6.4.3

Transmit Priority Queue Selection

The transmit priority queue may be selected from five options. As shown in Figure 6.4, the priority may

be based on:

„

the static value for the destination address in the ALR table

the precedence bits in the IPv4 TOS octet

the DIFFSERV mapping table indexed by the IPv4 TOS octet or the IPv6 Traffic Class octet

the VLAN tag priority field using the per port Priority Regeneration table

the port default

The last four options listed are sent through the Traffic Class table which maps the selected priority to

one of the four output queues. The static value from the ALR table directly specifies the queue.

Packet is from Host

Packet is Tagged

Packet is IPv4

Packet is IP

VL Higher Priority

Use Precedence

Use IP

VLAN Enable

ALR Static Bit

DA Highest Priority

IPv4(TOS)

IPv6(TC)

programmable

DIFFSERV table

programmable

Traffic Class

table

IPv4 Precedence

priority

calculation

static DA

override

priority queue

programmable

port default

table

Source Port

programmable

Priority

Regeneration

VLAN Priority

ALR Priority

table

per port

Figure 6.4 Switch Engine Transmit Queue Selection

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The transmit queue priority is based on the packet type and device configuration as shown in

Figure 6.5. Refer to Section 14.5.3.16, "Switch Engine Global Ingress Configuration Register

(SWE_GLOBAL_INGRSS_CFG)," on page 383 for definitions of the configuration bits.

Get Queue

Packet from Host

DA Highest

Priority

wait for ALR result

ALR Static Bit

VL Higher

Priority

VLAN Enable &

Packet is

Tagged

Packet is IPv4/v6

& Use IP

VLAN Enable &

Packet is

Tagged

Packet is IPv 4

Use Precedence

Resolved Priority =

Default Priority[Source

Port]

Resolved Priority =

Priority Regen[VLAN

Priority]

Resolved Priority =

IP Precedence

Resolved Priority =

DIFFSERV[TOS]

Resolved Priority =

DIFFSERV[TC]

Queue =

ALR Priority

Traffic Class[Resolved Priority]

Get Queue Done

Figure 6.5 Switch Engine Transmit Queue Calculation

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6.4.3.1

Port Default Priority

As detailed in Figure 6.5, the default priority is based on the ingress ports priority bits in its port VID

value. The PVID table is read and written by using the Switch Engine VLAN Command Register

(SWE_VLAN_CMD), Switch Engine VLAN Write Data Register (SWE_VLAN_WR_DATA), Switch

Engine VLAN Read Data Register (SWE_VLAN_RD_DATA), and Switch Engine VLAN Command

Status Register (SWE_VLAN_CMD_STS). Refer to Section 14.5.3.8, on page 375 through Section

14.5.3.11, on page 378 for detailed VLAN register descriptions.

6.4.3.2

6.4.3.3

IP Precedence Based Priority

The transmit priority queue can be chosen based on the Precedence bits of the IPv4 TOS octet. This

is supported for tagged and non-tagged packets for both type field and length field encapsulations. The

Precedence bits are the three most significant bits of the IPv4 TOS octet.

DIFFSERV Based Priority

The transmit priority queue can be chosen based on the DIFFSERV usage of the IPv4 TOS or IPv6

Traffic Class octet. This is supported for tagged and non-tagged packets for both type field and length

field encapsulations.

The DIFFSERV table is used to determine the packet priority from the 6-bit Differentiated Services (DS)

field. The DS field is defined as the six most significant bits of the IPv4 TOS octet or the IPv6 Traffic

Class octet and is used as an index into the DIFFSERV table. The output of the DIFFSERV table is

then used as the priority. This priority is then passed through the Traffic Class table to select the

transmit priority queue.

Note: The DIFFSERV table is not initialized upon reset or power-up. If DIFFSERV is enabled, then

the full table must be initialized by the host.

The DIFFSERV table is read and written by using the Switch Engine DIFFSERV T a ble Command

(SWE_DIFFSERV_TBL_WR_DATA), Switch Engine DIFFSERV T a ble Read Data Register

(SWE_DIFFSERV_TBL_RD_DATA), and Switch Engine DIFFSERV T a ble Command Status Register

(SWE_DIFFSERV_TBL_CMD_STS). Refer to Section 14.5.3.12, on page 379 through Section

14.5.3.15, on page 382 for detailed DIFFSERV register descriptions.

6.4.3.4

VLAN Priority

As detailed in Figure 6.5, the transmit priority queue can be taken from the priority field of the VLAN

tag. The VLAN priority is sent through a per port Priority Regeneration table, which is used to map the

VLAN priority into a user defined priority.

The Priority Regeneration table is programmed by using the Switch Engine Port 0 Ingress VLAN

Priority Regeneration T a ble Register (SWE_INGRSS_REGEN_TBL_MII), Switch Engine Port 1 Ingress

VLAN Priority Regeneration T a ble Register (SWE_INGRSS_REGEN_TBL_1), and Switch Engine Port

2 Ingress VLAN Priority Regeneration T a ble Register (SWE_INGRSS_REGEN_TBL_2). Refer to

Section 14.5.3.33, on page 402 through Section 14.5.3.35, on page 404 for detailed descriptions of

these registers.

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6.4.4

VLAN Support

The switch engine supports 16 active VLANs out of a possible 4096. The VLAN table contains the 16

active VLAN entries, each consisting of the VID, the port membership, and un-tagging instructions.

...

Member

Port 2

Un-tag

Port 2

Member

Port 1

Un-tag

Port 1

Member

MII

Un-tag

MII

VID

Figure 6.6 VLAN Table Entry Structure

On ingress, if a packet has a VLAN tag containing a valid VID (not 000h or FFFh), the VID table is

searched. If the VID is found, the VLAN is considered active and the membership and un-tag

instruction is used. If the VID is not found, the VLAN is considered foreign and the membership result

is NULL. A NULL membership will result in the packet being filtered if Enable Membership Checking

is set. A NULL membership will also result in the packet being filtered if the destination address is not

found in the ALR table (since the packet would have no destinations).

On ingress, if a packet does not have a VLAN tag or if the VLAN tag contains VID with a value of 0

(priority tag), the packet is assigned a VLAN based on the Port Default VID (PVID) and Priority. The

PVID is then used to access the above VLAN table.

The VLAN membership of the packet is used for ingress and egress checking and for VLAN broadcast

domain containment. The un-tag instructions are used at egress on ports defined as hybrid ports.

Refer to Section 14.5.3.8, on page 375 through Section 14.5.3.11, on page 378 for detailed VLAN

6.4.5

Spanning Tree Support

Hardware support for the Spanning Tree Protocol (STP) and the Rapid Spanning Tree Protocol (RSTP)

includes a per port state register as well as the override bit in the MAC Address Table entries (Section

6.4.1.5, on page 64) and the host CPU port special tagging (Section 6.4.10, on page 75).

The Switch Engine Port State Register (SWE_PORT_STATE) is used to place a port into one of the

modes as shown in T a ble 6.2. Normally only Port 1 and Port 2 are placed into modes other than

forwarding. Port 0 should normally be left in forwarding mode.

Table 6.2 Spanning Tree States

Port State

Hardware Action

Software Action

01 - Blocking

(also used for

disabled)

Received packets on the port are

discarded.

The MAC Address Table should be programmed

with entries that the host CPU needs to receive

(e.g. the BPDU address). The static and override

Transmissions to the port are blocked. bits should be set.

Learning on the port is disabled. The host CPU should not send any packets to the

port in this state.

The host CPU should discard received packets

from this port when in the Disabled state.

Note:

There is no hardware distinction between

the Blocking and Disabled states.

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Table 6.2 Spanning Tree States (continued)

Port State

Hardware Action

Software Action

11 - Listening

Received packets on the port are

discarded.

The MAC Address Table should be programmed

with entries that the host CPU needs to receive

(e.g. the BPDU address). The static and override

Transmissions to the port are blocked. bits should be set.

Learning on the port is disabled.

The host CPU may send packets to the port in this

state.

10 - Learning

Received packets on the port are

discarded.

The MAC Address Table should be programmed

with entries that the host CPU needs to receive

(e.g. the BPDU address). The static and override

Transmissions to the port are blocked. bits should be set.

Learning on the port is enabled.

The host CPU may send packets to the port in this

state.

00 - Forwarding

Received packets on the port are

forwarded normally.

The MAC Address Table should be programmed

with entries that the host CPU needs to receive

(e.g. the BPDU address). The static and override

bits should be set.

Transmissions to the port are sent

normally.

The host CPU may send packets to the port in this

state.

Learning on the port is enabled.

6.4.6

Ingress Flow Metering and Coloring

The LAN9312 supports hardware ingress rate limiting by metering packet streams and marking packets

as either Green, Yellow, or Red according to three traffic parameters: Committed Information Rate

(CIR), Committed Burst Size (CBS), and Excess Burst Size (EBS). A packet is marked Green if it does

not exceed the CBS, Yellow if it exceeds to CBS but not the EBS, or Red otherwise.

Ingress flow metering and coloring is enabled via the Ingress Rate Enable bit in the Switch Engine

Ingress Rate Configuration Register (SWE_INGRSS_RATE_CFG). Once enabled, each incoming

packet is classified into a stream. Streams are defined as per port (3 streams), per priority (8 streams),

or per port & priority (24 streams) as selected via the Rate Mode bits in the Switch Engine Ingress

Rate Configuration Register (SWE_INGRSS_RATE_CFG). Each stream can have a different CIR

setting. All streams share common CBS and EBS settings. CIR, CBS, and EBS are programmed via

the Switch Engine Ingress Rate Command Register (SWE_INGRSS_RATE_CMD) and Switch Engine

Ingress Rate Write Data Register (SWE_INGRSS_RATE_WR_DATA).

Each stream is metered according to RFC 2697. At the rate set by the CIR, two token buckets are

credited per stream. First, the Committed Burst bucket is incremented up to the maximum set by the

CBS. Once the Committed Burst bucket is full, the Excess Burst bucket is incremented up to the

maximum set by the EBS. The CIR rate is specified in time per byte. The value programmed is in

approximately 20 nS per byte increments. Typical values are listed in T a ble 6.3. When a port is

receiving at 10Mbps, any setting faster than 39 has the effect of not limiting the rate.

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Table 6.3 Typical Ingress Rate Settings

CIR Setting

Time Per Byte

Bandwidth

0-3

80 nS

100 nS

100 Mbps

80 Mbps

67 Mbps

57 Mbps

50 Mbps

40 Mbps

31 Mbps

20 Mbps

10 Mbps

5 Mbps

120 nS

140 nS

160 nS

200 nS

260 nS

400 nS

800 nS

1600 nS

3220 nS

8060 nS

16100 nS

32220 nS

80580 nS

161140 nS

160

402

804

1610

4028

8056

2.5 Mbps

1 Mbps

500 Kbps

250 Kbps

100 Kbps

50 Kbps

After each packet is received, the bucket is decremented. If the Committed Burst bucket has sufficient

tokens, it is debited and the packet is colored Green. If the Committed Burst bucket lacks sufficient

tokens for the packet, the Excess Burst bucket is checked. If the Excess Burst bucket has sufficient

tokens, it is debited, the packet is colored Yellow and is subjected to random discard. If the Excess

Burst bucket lacks sufficient tokens for the packet, the packet is colored Red and is discarded.

Note: All of the token buckets are initialized to the default value of 1536. If lower values are

programmed into the CBS and EBS parameters, the token buckets will need to be normally

depleted below these values before the values have any affect on limiting the maximum value

of the token buckets.

Refer to Section 14.5.3.25, on page 393 through Section 14.5.3.29, on page 398 for detailed register

descriptions.

6.4.6.1

Ingress Flow Calculation

Based on the flow monitoring mode, an ingress flow definition can include the ingress priority. This is

calculated similarly to the transmit queue with the exception that the Priority Regeneration and the

Traffic Class table are not used. As shown in Figure 6.7, the priority can be based on:

„

The precedence bits in the IPv4 TOS octet

The DIFFSERV mapping table indexed by the IPv4 TOS octet or the IPv6 Traffic Class octet

The VLAN tag priority field (but not through the per port Priority Regeneration table)

The port default

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Packet is from Host

Packet is Tagged

Packet is IPv4

Packet is IP

VL Higher Priority

Use Precedence

Use IP

VLAN Enable

IPv4(TOS)

IPv6(TC)

Programmable

DIFFSERV Table

IPv4 Precedence

Priority

Calculation

flow priority

Programmable

Port Default

Table

Source Port

VLAN Priority

Figure 6.7 Switch Engine Ingress Flow Priority Selection

The ingress flow calculation is based on the packet type and the device configuration as shown in

Figure 6.8.

Get Flow Priority

Packet from Host

VL Higher

Priority

Vlan Enable &

Packet is

Tagged

Packet is IPv4/v6

& Use IP

Vlan Enable &

Packet is

Tagged

Packet is IPv4

Use Precedence

Flow Priority =

Default Priority[Source

Port]

Flow Priority =

IP Precedence

Flow Priority=

DIFFSERV[TOS]

Flow Priority =

DIFFSERV[TC]

Flow Priority=

VLAN Priority

Get Flow Priority Done

Figure 6.8 Switch Engine Ingress Flow Priority Calculation

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6.4.7

Broadcast Storm Control

In addition to ingress rate limiting, the LAN9312 supports hardware broadcast storm control on a per

port basis. This feature is enabled via the Switch Engine Broadcast Throttling Register

(SWE_BCST_THROT). The allowed rate per port is specified as the number of bytes multiplied by 64

allowed to be received every 1.72 mS interval. Packets that exceed this limit are dropped. Typical

values are listed in T a ble 6.4. When a port is receiving at 10Mbps, any setting above 34 has the effect

of not limiting the rate.

Table 6.4 Typical Broadcast Rate Settings

Broadcast Throttle Level

Bandwidth

252

168

134

75 Mbps

50 Mbps

40 Mbps

20 Mbps

10 Mbps

5 Mbps

2.4 Mbps

1.2 Mbps

900 Kbps

600 Kbps

300 Kbps

In addition to the rate limit, the Buffer Manager Broadcast Buffer Level Register (BM_BCST_LVL)

specifies the maximum number of buffers that can be used by broadcasts, multicasts, and unknown

unicasts.

6.4.8

IPv4 IGMP / IPv6 MLD Support

The LAN9312 provides Internet Group Management Protocol (IGMP) and Multicast Listener Discovery

(MLD) hardware support using two mechanisms: IGMP/MLD snooping and Multicast Pruning.

On ingress, if IGMP packet snooping is enabled in the Switch Engine Global Ingress Configuration

MLD/IGMP snoop port (typically set to the port to which the host CPU is connected). IGMP packets

are identified as IPv4 packets with a protocol of 2. Both Ethernet and IEEE 802.3 frame formats are

supported as are VLAN tagged packets.

On ingress, if MLD packet snooping is enabled in the Switch Engine Global Ingress Configuration

MLD/IGMP snoop port (typically set to the port to which the host CPU is connected). MLD packets are

identified as IPv6 packets with a next header value of 58 decimal (ICMPv6). Both Ethernet and IEEE

802.3 frame formats are supported as are VLAN tagged packets.

Once the IGMP or MLD packets are received by the host CPU, the host software can decide which

port or ports need to be members of the multicast group. This group is then added to the ALR table

as detailed in Section 6.4.1.3, "Multicast Pruning," on page 64. The host software should also forward

the original IGMP packet if necessary.

Normally, packets are never transmitted back to the receiving port. For IGMP/MLD snooping, this may

optionally be enabled via the S witch Engine Global Ingress Configuration Register

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(SWE_GLOBAL_INGRSS_CFG). This function would be used if the snooping port wished to participate

in the IGMP/MLD group without the need to perform special handling in the transmit portion of the

driver software.

Note: Most forwarding rules are skipped when a packet is snooped. However, a packet is still filtered

if:

„The source port is not in the forwarding state (unless Spanning Tree Port State Override is in

effect.

„VLAN’s are enabled, the packet is untagged or priority tagged, and the Admit Only VLAN bit

for the ingress port is set.

„VLAN’s are enabled and the packet is tagged and had a VID equal to FFFh.

„VLAN’s are enabled, Enabled Membership Checking on Ingress is set, Admit Non Member is

cleared, and the source port is not a member of the incoming VLAN.

6.4.9

Port Mirroring

The LAN9312 supports port mirroring where packets received or transmitted on a port or ports can

also be copied onto another “sniffer” port.

Port mirroring is configured using the Switch Engine Port Mirroring Register (SWE_PORT_MIRROR).

Multiple mirrored ports can be defined, but only one sniffer port can be defined.

When receive mirroring is enabled, packets that are forwarded from a port designated as a mirrored

port are also transmitted by the sniffer port. For example, Port 2 is setup to be a mirrored port and

Port 0 is setup to be the sniffer port. If a packet is received on Port 2 with a destination of Port 1, it

is forwarded to both Port 1 and Port 0.

When transmit mirroring is enabled, packets that are forwarded to a port designated as a mirrored port

are also transmitted by the sniffer port. For example, Port 2 is setup to be a mirrored port and Port 0

is setup to be the sniffer port. If a packet is received on Port 1 with a destination of Port 2, it is

forwarded to both Port 2 and Port 0.

Note: A packet will never be transmitted out of the receiving port. A receive packet is not normally

mirrored if it is filtered. This can optionally be enabled.

6.4.10

Host CPU Port Special Tagging

The Switch Engine Ingress Port Type Register (SWE_INGRSS_PORT_TYP) and Buffer Manager

Egress Port Type Register (BM_EGRSS_PORT_TYPE) are used to enable a special VLAN tag that is

used by the host CPU. This special tag is used to specify the port(s) where packets from the CPU

should be sent, and to indicate which port received the packet that was forwarded to the CPU.

6.4.10.1

Packets from the Host CPU

The Switch Engine Ingress Port Type Register (SWE_INGRSS_PORT_TYP) configures the switch to

use the special VLAN tag in packets from the host CPU as a destination port indicator. A setting of

11b should be used on the port that is connected to the host CPU (typically Port 0). A setting of 00b

should be used on the normal network ports.

The special VLAN tag is a normal VLAN tag where the VID field is used as the destination port

indicator. If VID bit 3 is zero, then bits 0 and 1 specify the destination port (0, 1, 2) or broadcast (3).

If VID bit 3 is one, then the normal ALR lookup is performed and learning is performed on the source

address. The PRI field from the VLAN tag is used as the packet priority.

Upon egress from the destination port(s), the special tag is removed. If a regular VLAN tag needs to

be sent as part of the packet, then it should be part of the packet data from the host CPU port or set

as an unused bit in the VID field.

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Note: When specifying Port 0 as the destination port, the VID will be set to 0. A VID of 0 is normally

considered a priority tagged packet. Such a packet will be filtered if Admit Only VLAN is set

on the host CPU port. Either avoid setting Admit Only VLAN on the host CPU port or set an

unused bit in the VID field.

Note: The maximum size tagged packet that can normally be sent into a switch port (from the Host

MAC) is 1522 bytes. Since the special tag consumes four bytes of the packet length, the

outgoing packet is limited to 1518 bytes, even if it contains a regular VLAN tag as part of the

packet data. If a larger outgoing packet is required, the Jumbo2K bit in the Port x MAC Receive

Configuration Register (MAC_RX_CFG_x) of Port 0 should be set.

6.4.10.2

Packets to the Host CPU

The Buffer Manager Egress Port Type Register (BM_EGRSS_PORT_TYPE) configures the switch to

add the special VLAN tag in packets to the host CPU as a source port indicator. A setting of 11b should

be used only on the port that is connected to the host CPU (typically Port 0). Other settings can be

used on the normal network ports as needed.

The special VLAN tag is a normal VLAN tag where bits 0 and 1 of the VID field specify the source

port (0, 1, or 2).

Upon egress from the host CPU port, the special tag is added. If a regular VLAN tag already exists,

it is not deleted. Instead it will follow the special tag.

Note: Since the special tag adds four bytes to the length of the packet, it is possible for a normally

tagged, maximum size, incoming packet to become 1526 bytes in length. In order for the Host

MAC to receive this length packet without indicating a length error, the Host MAC VLAN2 T a g

T a g Register (HMAC_VLAN1) should be set to a value other than 8100h. This configuration

will allow frames up to 1538 bytes in length to be received.

Note: Since the special tag adds four bytes to the length of the packet, it is possible for a normally

tagged, maximum size, incoming jumbo packet to become 2052 bytes in length. This packet

will be received by the Host MAC with the following conditions:

„The receive status will indicate Frame Too Long

„Up to four bytes of the end of packet may be truncated (the maximum receive length at the

Host MAC is 2048).

6.4.11

Counters

A counter is maintained per port that contains the number of MAC address that were not learned or

were overwritten by a different address due to MAC Address Table space limitations. These counters

are accessible via the following registers:

„

Switch Engine Port 0 Learn Discard Count Register (SWE_LRN_DISCRD_CNT_MII)

Switch Engine Port 1 Learn Discard Count Register (SWE_LRN_DISCRD_CNT_1)

Switch Engine Port 2 Learn Discard Count Register (SWE_LRN_DISCRD_CNT_2)

A counter is maintained per port that contains the number of packets filtered at ingress. This count

includes packets filtered due to broadcast throttling, but does not include packets dropped due to

ingress rate limiting. These counters are accessible via the following registers:

„

Switch Engine Port 0 Ingress Filtered Count Register (SWE_FILTERED_CNT_MII)

Switch Engine Port 1 Ingress Filtered Count Register (SWE_FILTERED_CNT_1)

Switch Engine Port 2 Ingress Filtered Count Register (SWE_FILTERED_CNT_2)

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6.5

Buffer Manager (BM)

The buffer manager (BM) provides control of the free buffer space, the multiple priority transmit

queues, transmission scheduling, and packet dropping. VLAN tag insertion and removal is also

performed by the buffer manager. The following sections detail the various features of the buffer

manager.

6.5.1

Packet Buffer Allocation

The packet buffer consists of 32KB of RAM that is dynamically allocated in 128 byte blocks as packets

are received. Up to 16 blocks may be used per packet, depending on the packet length. The blocks

are linked together as the packet is received. If a packet is filtered, dropped, or contains a receive

error, the buffers are reclaimed.

6.5.1.1

Buffer Limits and Flow Control Levels

The BM keeps track of the amount of buffers used per each ingress port. These counts are used to

generate flow control (half-duplex backpressure or full-duplex pause frames) and to limit the amount

of buffer space that can be used by any individual receiver (hard drop limit). The flow control and drop

limit thresholds are dynamic and adapt based on the current buffer usage. Based on the number of

active receiving ports, the drop level and flow control pause and resume thresholds adjust between

fixed settings and two user programmable levels via the Buffer Manager Drop Level Register

(BM_DROP_LVL), Buffer Manager Flow Control Pause Level Register (BM_FC_PAUSE_LVL), and

Buffer Manager Flow Control Resume Level Register (BM_FC_RESUME_LVL) respectively.

The BM also keeps a count of the number of buffers that are queued for multiple ports (broadcast

queue). This count is compared against the Buffer Manager Broadcast Buffer Level Register

(BM_BCST_LVL), and if the configured drop level is reached or exceeded, subsequent packets are

dropped.

6.5.2

Random Early Discard (RED)

Based on the ingress flow monitoring detailed in Section 6.4.6, "Ingress Flow Metering and Coloring,"

on page 71, packets are colored as Green, Yellow, or Red. Packets colored Red are always discarded

if the Drop on Red bit in the Buffer Manager Configuration Register (BM_CFG) is set. If the Drop on

Yellow bit in the Buffer Manager Configuration Register (BM_CFG) is set, packets colored Yellow are

randomly discarded based on the moving average number of buffers used by the ingress port.

The probability of a discard is programmable into the Random Discard Weight table via the Buffer

Manager Random Discard T a ble Command Register (BM_RNDM_DSCRD_TBL_CMD), Buffer

Manager Random Discard T a ble Write Data Register (BM_RNDM_DSCRD_TBL_WDATA), and Buffer

Manager Random Discard T a ble Read Data Register (BM_RNDM_DSCRD_TBL_RDATA). The

Random Discard Weight table contains sixteen entries, each 10-bits wide. Each entry corresponds to

a range of the average number of buffers used by the ingress port. Entry 0 is for 0 to 15 buffers, entry

1 is for 16 to 31 buffers, etc. The probability for each entry us set in 1/1024’s. For example, a setting

of 1 is 1-in-1024, or approximately 0.1%. A setting of all ones (1023) is 1023-in-1024, or approximately

99.9%.

Refer to Section 14.5.4.10, "Buffer Manager Random Discard T a ble Command Register

(BM_RNDM_DSCRD_TBL_CMD)," on page 420 for additional details on writing and reading the

Random Discard Weight table.

6.5.3

Transmit Queues

Once a packet has been completely received, it is queued for transmit. There are four queues per

transmit port, one for each level of transmit priority. Each queue is virtual (if there are no packets for

that port/priority, the queue is empty), and dynamic (a queue may be any length if there is enough

memory space). When a packet is read from the memory and sent out to the corresponding port, the

used buffers are released.

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6.5.4

Transmit Priority Queue Servicing

When a transmit queue is non-empty, it is serviced and the packet is read from the buffer RAM and

sent to the transmit MAC. If there are multiple queues that require servicing, one of two methods may

be used: fixed priority ordering, or weighted round-robin ordering. If the Fixed Priority Queue Servicing

bit in the Buffer Manager Configuration Register (BM_CFG) is set, a strict order, fixed priority is

selected. Transmit queue 3 has the highest priority, followed by 2, 1, and 0. If the Fixed Priority Queue

Servicing bit in the Buffer Manager Configuration Register (BM_CFG) is cleared, a weighted round-

robin order is followed. Assuming all four queues are non-empty, the service is weighted with a 9:4:2:1

ratio (queue 3,2,1,0). The servicing is blended to avoid burstiness (e.g. queue 3, then queue 2, then

queue 3, etc.).

6.5.5

Egress Rate Limiting (Leaky Bucket)

For egress rate limiting, the leaky bucket algorithm is used on each output priority queue. For each

output port, the bandwidth that is used by each priority queue can be limited. If any egress queue

receives packets faster than the specified egress rate, packets will be accumulated in the packet

memory. After the memory is used, packet dropping or flow control will be triggered.

Note: Egress rate limiting occurs before the Transmit Priority Queue Servicing, such that a lower

priority queue will be serviced if a higher priority queue is being rate limited.

The egress limiting is enabled per priority queue. After a packet is selected to be sent, its length is

recorded. The switch then waits a programmable amount of time, scaled by the packet length, before

servicing that queue once again. The amount of time per byte is programmed into the Buffer Manager

Egress Rate registers (refer to Section 14.5.4.14 through Section 14.5.4.19 for detailed register

definitions). The value programmed is in approximately 20 nS per byte increments. Typical values are

listed in T a ble 6.5. When a port is transmitting at 10 Mbps, any setting above 39 has the effect of not

limiting the rate.

Table 6.5 Typical Egress Rate Settings

EGRESS RATE

SETTING

BANDWIDTH @

64 BYTE PACKET

BANDWIDTH @

512 BYTE PACKET 1518 BYTE PACKET

BANDWIDTH @

TIME PER BYTE

0-3

80 nS

100 nS

76 Mbps (Note 6.3)

66 Mbps

96 Mbps (Note 6.3)

78 Mbps

65 Mbps

56 Mbps

49 Mbps

39 Mbps

30 Mbps

20 Mbps

10 Mbps

5 Mbps

99 Mbps (Note 6.3)

80 Mbps

67 Mbps

57 Mbps

50 Mbps

40 Mbps

31 Mbps

20 Mbps

10 Mbps

5 Mbps

120 nS

55 Mbps

140 nS

48 Mbps

160 nS

42 Mbps

200 nS

34 Mbps

260 nS

26 Mbps

400 nS

17 Mbps

800 nS

8.6 Mbps

4.4 Mbps

2.2 Mbps

870 Kbps

440 Kbps

220 Kbps

87 Kbps

1580 nS

3180 nS

7940 nS

15900 nS

31800 nS

79480 nS

158960 nS

158

396

794

1589

3973

7947

2.5 Mbps

990 Kbps

490 Kbps

250 Kbps

98 Kbps

2.5 Mbps

1 Mbps

500 Kbps

250 Kbps

100 Kbps

50 Kbps

44 Kbps

49 Kbps

Note 6.3 These are the unlimited max bandwidths when IFG and preamble are taken into account.

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6.5.6

Adding, Removing, and Changing VLAN Tags

Based on the port configuration and the received packet formation, a VLAN tag can be added to,

removed from, or modified in a packet. There are four received packet type cases: non-tagged, priority-

tagged, normal-tagged, and CPU special-tagged. There are also four possible settings for an egress

port: dumb, access, hybrid, and CPU. In addition, each VLAN table entry can specify the removal of

the VLAN tag (the entry’s un-tag bit).

The tagging/un-tagging rules are specified as follows:

„

Dumb Port - This port type generally does not change the tag.

When a received packet is non-tagged, priority-tagged, or normal-tagged, the packet passes

untouched.

When a packet is received special-tagged from a CPU port, the special tag is removed.

„

Access Port - This port type generally does not support tagging.

When a received packet in non-tagged, the packet passes untouched.

When a received packet is priority-tagged or normal-tagged, the tag is removed.

When a received packet is special-tagged from a CPU port, the special tag is removed.

„

CPU Port - Packets transmitted from this port type generally contain a special tag. Special tags

are described in detail in Section 6.4.10, "Host CPU Port Special T a gging," on page 75.

Hybrid Port - Generally, this port type supports a mix of normal-tagged and non-tagged packets.

It is the most complex, but most flexible port type.

For clarity, the following details the incoming un-tag instruction. As described in Section 6.4.4, "VLAN

Support," on page 70, the un-tag instruction is one of three un-tag bits from the applicable entry in the

VLAN table, selected by the ingress port number. The entry in the VLAN table is either the VLAN from

the received packet or the ingress ports default VID.

„

When a received packet is non-tagged, a new VLAN tag is added if two conditions are met. First,

the Insert Tag bit for the egress port in the Buffer Manager Egress Port Type Register

(BM_EGRSS_PORT_TYPE) must be set. Second, the un-tag instruction associated with the

ingress ports default VID must be cleared. The VLAN tag that is added will have a VID and Priority

taken from the ingress ports default VID and priority.

„

When a received packet is priority-tagged, either the tag is removed or it is modified.

If the un-tag instruction associated with the ingress ports default VID is set, then the tag is removed.

Otherwise, the tag is modified. The VID of the new VLAN tag is changed to the ingress ports default

VID. If the Change Priority bit in the Buffer Manager Egress Port Type Register

(BM_EGRSS_PORT_TYPE) for the egress port is set, then the Priority field of the new VLAN tag

is also changed to the ingress ports default priority.

„

When a received packet is normal-tagged, either the tag is removed, modified, or passed.

If the un-tag instruction associated with the VID in the received packet is set, then the tag is

removed.

Else, if the Change Tag bit in the Buffer Manager Egress Port Type Register

(BM_EGRSS_PORT_TYPE) for the egress port is clear, the packet is untouched.

Else, if both the Change VLAN ID and the Change Priority bits in the Buffer Manager Egress Port

Type Register (BM_EGRSS_PORT_TYPE) for the egress port are clear, the packet passes

untouched.

Otherwise, the tag is modified. If the Change VLAN ID bit for the egress port is set, the VOD of

the new VLAN tag is changed to the egress ports default ID. If the Change Priority bit for the egress

port is set, the Priority field of the new VLAN is changed to the egress ports default priority.

„

When a packet is received special-tagged from a CPU port, the special tag is removed.

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Hybrid tagging is summarized in Figure 6.9.

Receive Tag

Type

Non-tagged

Normal Tagged Priority Tagged

Special Tagged

Default VID

[ingress_port]

Un-tag Bit

Insert Tag

[egress_port]

Default VID

[ingress_port]

Un-tag Bit

Change Priority

[egress_port]

Add Tag

VID = Default VID

[ingress_port]

Priority = Default Priority

[ingress_port]

Modify Tag

VID = Default VID

[ingress_port]

Priority = Default Priority

[ingress_port]

Modify Tag

VID = Default VID

[ingress_port]

Send Packet Untouched

Strip Tag

Priority = Unchanged

Received VID

Un-tag Bit

Change Tag

[egress_port]

Change VLAN ID

[egress_port]

Change Priority

[egress_port]

Change Priority

[egress_port]

Modify Tag

VID = Default VID

[egress_port]

Priority = Default Priority

[egress_port]

Modify Tag

VID = Default VID

[egress_port]

Priority = Unchanged

Modify Tag

VID = Unchanged

Priority = Default Priority

[egress_port]

Send Packet Untouched

Strip Tag

Figure 6.9 Hybrid Port Tagging and Un-tagging

The default VLAN ID and priority of each port may be configured via the following registers:

„

Buffer Manager Port 0 Default VLAN ID and Priority Register (BM_VLAN_MII)

Buffer Manager Port 1 Default VLAN ID and Priority Register (BM_VLAN_1)

Buffer Manager Port 2 Default VLAN ID and Priority Register (BM_VLAN_2)

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6.5.7

Counters

A counter is maintained per port that contains the number of packets dropped due to buffer space limits

and ingress rate limit discarding (Red and random Yellow dropping). These counters are accessible

via the following registers:

„

Buffer Manager Port 0 Drop Count Register (BM_DRP_CNT_SRC_MII)

Buffer Manager Port 1 Drop Count Register (BM_DRP_CNT_SRC_1)

Buffer Manager Port 2 Drop Count Register (BM_DRP_CNT_SRC_2)

A counter is maintained per port that contains the number of packets dropped due solely to ingress

rate limit discarding (Red and random Yellow dropping). This count value can be subtracted from the

drop counter, as described above, to obtain the drop counts due solely to buffer space limits. The

ingress rate drop counters are accessible via the following registers:

„

Buffer Manager Port 0 Ingress Rate Drop Count Register (BM_RATE_DRP_CNT_SRC_MII)

Buffer Manager Port 1 Ingress Rate Drop Count Register (BM_RATE_DRP_CNT_SRC_1)

Buffer Manager Port 2 Ingress Rate Drop Count Register (BM_RATE_DRP_CNT_SRC_2)

6.6

Switch Fabric Interrupts

The switch fabric is capable of generating multiple maskable interrupts from the buffer manager, switch

engine, and MACs. These interrupts are detailed in Section 5.2.2, "Switch Fabric Interrupts," on

page 51.

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Chapter 7 Ethernet PHYs

7.1

Functional Overview

The LAN9312 contains three PHYs: Port 1 PHY, Port 2 PHY and a Virtual PHY. The Port 1 & 2 PHYs

are identical in functionality and each connect their corresponding Ethernet signal pins to the switch

fabric MAC of their respective port. These PHYs interface with their respective MAC via an internal MII

interface. The Virtual PHY provides the virtual functionality of a PHY and allows connection of the Host

MAC to port 0 of the switch fabric as if it was connected to a single port PHY. All PHYs comply with

the IEEE 802.3 Physical Layer for Twisted Pair Ethernet and can be configured for full/half duplex 100

Mbps (100BASE-TX) or 10Mbps (10BASE-T) Ethernet operation. All PHY registers follow the IEEE

802.3 (clause 22.2.4) specified MII management register set and can be configured indirectly via the

Host MAC, or directly via the memory mapped Virtual PHY registers. Refer to Section 14.4, "Ethernet

PHY Control and Status Registers" for details on the Ethernet PHY registers.

The LAN9312 Ethernet PHYs are discussed in detail in the following sections:

„

Section 7.2, "Port 1 & 2 PHYs," on page 83

Section 7.3, "Virtual PH Y ," on page 96

7.1.1

PHY Addressing

Each individual PHY is assigned a unique default PHY address via the phy_addr_sel_strap

configuration strap as shown in T a ble 7.1. In addition, the Port 1 PHY and Port 2 PHY addresses can

be changed via the PHY Address (PHYADD) field in the Port x PHY Special Modes Register

(PHY_SPECIAL_MODES_x). For proper operation, all LAN9312 PHY addresses must be unique. No

check is performed to assure each PHY is set to a different address. Configuration strap values are

latched upon the de-assertion of a chip-level reset as described in Section 4.2.4, "Configuration

Straps," on page 40.

Table 7.1 Default PHY Serial MII Addressing

VIRTUAL PHY DEFAULT

ADDRESS VALUE

PORT 1 PHY DEFAULT PORT 2 PHY DEFAULT

PHY_ADDR_SEL_STRAP

ADDRESS VALUE

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7.2

Port 1 & 2 PHYs

Functionally, each PHY can be divided into the following sections:

„

100BASE-TX Transmit and 100BASE-TX Receive

10BASE-T Transmit and 10BASE-T Receive

PHY Auto-negotiation

HP Auto-MDIX

MII MAC Interface

PHY Management Control

Note 7.1 Because the Port 1 PHY and Port 2 PHY are functionally identical, this section will describe

them as the “Port x PHY”, or simply “PHY”. Wherever a lowercase “x” has been appended

to a port or signal name, it can be replaced with “1” or “2” to indicate the Port 1 or Port 2

PHY respectively. All references to “PHY” in this section can be used interchangeably for

both the Port 1 & 2 PHYs. This nomenclature excludes the Virtual PHY.

A block diagram of the Port x PHYs main components can be seen in Figure 7.1.

Auto-

Negotiation

10/100

Transmitter

TXPx/TXNx

MII

MAC

Interface

MII

To External

Port x Ethernet Pins

HP Auto-MDIX

To Port x

RXPx/RXNx

Switch Fabric MAC

10/100

Reciever

PHY Management

Control

MDIO

To Host MAC

LEDs

PLL

Registers

Interrupts

To System

Interrupt Controller

To GPIO/LED

Controller

From

System Clocks Controller

Figure 7.1 Port x PHY Block Diagram

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7.2.1

100BASE-TX Transmit

The 100BASE-TX transmit data path is shown in Figure 7.2. Shaded blocks are those which are

internal to the PHY. Each major block is explained in the following sections.

100M

PLL

Internal

MII Transmit Clock

Port x

MAC

MII MAC

Interface

4B/5B

Encoder

Scrambler

and PISO

Internal

MII 25 MHz by 4 bits

25MHz

by 4 bits

25MHz by

5 bits

125 Mbps Serial

NRZI

Converter

MLT-3

Converter

100M

TX Driver

NRZI

MLT-3

Magnetics

MLT-3

RJ45

CAT-5

Figure 7.2 100BASE-TX Transmit Data Path

MII MAC Interface

7.2.1.1

7.2.1.2

For a transmission, the switch fabric MAC drives the transmit data to the PHYs MII MAC Interface.

The MII MAC Interface is described in detail in Section 7.2.7, "MII MAC Interface".

Note: The PHY is connected to the switch fabric MAC via standard MII signals. Refer to the IEEE

802.3 specification for additional details.

4B/5B Encoder

The transmit data passes from the MII block to the 4B/5B Encoder. This block encodes the data from

4-bit nibbles to 5-bit symbols (known as “code-groups”) according to T a ble 7.2. Each 4-bit data-nibble

is mapped to 16 of the 32 possible code-groups. The remaining 16 code-groups are either used for

control information or are not valid.

The first 16 code-groups are referred to by the hexadecimal values of their corresponding data nibbles,

0 through F. The remaining code-groups are given letter designations with slashes on either side. For

example, an IDLE code-group is /I/, a transmit error code-group is /H/, etc.

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Table 7.2 4B/5B Code Table

CODE

GROUP

RECEIVER

INTERPRETATION

TRANSMITTER

INTERPRETATION

SYM

11110

01001

10100

10101

01010

01011

01110

01111

10010

10011

10110

10111

11010

11011

11100

11101

11111

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

DATA

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

DATA

/I/

IDLE

Sent after /T/R/ until the MII Transmitter

Enable signal (TXEN) is received

11000

10001

01101

00111

/J/

/K/

/T/

/R/

First nibble of SSD, translated to “0101”

following IDLE, else MII Receive Error

(RXER)

Sent for rising MII Transmitter Enable

signal (TXEN)

Second nibble of SSD, translated to

“0101” following J, else MII Receive

Error (RXER)

Sent for rising MII Transmitter Enable

signal (TXEN)

First nibble of ESD, causes de-assertion

of CRS if followed by /R/, else assertion

of MII Receive Error (RXER)

Sent for falling MII Transmitter Enable

signal (TXEN)

Second nibble of ESD, causes de-

assertion of CRS if following /T/, else

assertion of MII Receive Error (RXER)

Sent for falling MII Transmitter Enable

signal (TXEN)

00100

00110

/H/

/V/

Transmit Error Symbol

Sent for rising MII Transmit Error (TXER)

INVALID

INVALID, MII Receive Error (RXER) if

during MII Receive Data Valid (RXDV)

11001

00000

00001

/V/

INVALID, MII Receive Error (RXER) if

during MII Receive Data Valid (RXDV)

INVALID

INVALID, MII Receive Error (RXER) if

during MII Receive Data Valid (RXDV)

INVALID, MII Receive Error (RXER) if

during MII Receive Data Valid (RXDV)

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Table 7.2 4B/5B Code Table (continued)

CODE

GROUP

RECEIVER

INTERPRETATION

TRANSMITTER

INTERPRETATION

SYM

00010

00011

00101

01000

01100

10000

/V/

INVALID, MII Receive Error (RXER) if

during MII Receive Data Valid (RXDV)

INVALID

/V/

INVALID, MII Receive Error (RXER) if

during MII Receive Data Valid (RXDV)

INVALID, MII Receive Error (RXER) if

during MII Receive Data Valid (RXDV)

INVALID, MII Receive Error (RXER) if

during MII Receive Data Valid (RXDV)

INVALID, MII Receive Error (RXER) if

during MII Receive Data Valid (RXDV)

INVALID, MII Receive Error (RXER) if

during MII Receive Data Valid (RXDV)

7.2.1.3

Scrambler and PISO

Repeated data patterns (especially the IDLE code-group) can have power spectral densities with large

narrow-band peaks. Scrambling the data helps eliminate these peaks and spread the signal power

more uniformly over the entire channel bandwidth. This uniform spectral density is required by FCC

regulations to prevent excessive EMI from being radiated by the physical wiring. The scrambler also

performs the Parallel In Serial Out conversion (PISO) of the data.

The seed for the scrambler is generated from the PHY address, ensuring that each PHY will have its

own scrambler sequence. For more information on PHY addressing, refer to Section 7.1.1, "PHY

Addressing".

7.2.1.4

7.2.1.5

NRZI and MLT-3 Encoding

The scrambler block passes the 5-bit wide parallel data to the NRZI converter where it becomes a

serial 125MHz NRZI data stream. The NRZI is then encoded to MLT-3. MLT-3 is a tri-level code where

a change in the logic level represents a code bit “1” and the logic output remaining at the same level

represents a code bit “0”.

100M Transmit Driver

The MLT-3 data is then passed to the analog transmitter, which drives the differential MLT-3 signal on

output pins TXPx and TXNx (where “x” is replaced with “1” for the Port 1 PHY, or “2” for the Port 2

PHY), to the twisted pair media across a 1:1 ratio isolation transformer. The 10BASE-T and 100BASE-

TX signals pass through the same transformer so that common “magnetics” can be used for both. The

transmitter drives into the 100Ω impedance of the CAT-5 cable. Cable termination and impedance

matching require external components.

7.2.1.6

100M Phase Lock Loop (PLL)

The 100M PLL locks onto the reference clock and generates the 125MHz clock used to drive the 125

MHz logic and the 100BASE-TX Transmitter.

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7.2.2

100BASE-TX Receive

The 100BASE-TX receive data path is shown in Figure 7.3. Shaded blocks are those which are internal

to the PHY. Each major block is explained in the following sections.

100M

PLL

Internal

MII Receive Clock

Port x

MAC

MII MAC

Interface

Internal

MII 25MHz by 4 bits

25MHz

by 4 bits

4B/5B

Decoder

Descrambler

and SIPO

25MHz by

5 bits

125 Mbps Serial

MLT-3

DSP: Timing

recovery, Equalizer

and BLW Correction

NRZI

Converter

MLT-3

Converter

NRZI

A/D

Converter

MLT-3

Magnetics

RJ45

CAT-5

6 bit Data

Figure 7.3 100BASE-TX Receive Data Path

7.2.2.1

7.2.2.2

A/D Converter

The MLT-3 data from the cable is fed into the PHY on inputs RXPx and RXNx (where “x” is replaced

with “1” for the Port 1 PHY, or “2” for the Port 2 PHY) via a 1:1 ratio transformer. The ADC samples

the incoming differential signal at a rate of 125M samples per second. Using a 64-level quantizer, 6

digital bits are generated to represent each sample. The DSP adjusts the gain of the A/D Converter

(ADC) according to the observed signal levels such that the full dynamic range of the ADC can be

used.

DSP: Equalizer, BLW Correction and Clock/Data Recovery

The 6 bits from the ADC are fed into the DSP block. The equalizer in the DSP section compensates

for phase and amplitude distortion caused by the physical channel (magnetics, connectors, and CAT-

5 cable). The equalizer can restore the signal for any good-quality CAT-5 cable between 1m and 150m.

If the DC content of the signal is such that the low-frequency components fall below the low frequency

pole of the isolation transformer, then the droop characteristics of the transformer will become

significant and Baseline Wander (BLW) on the received signal will result. To prevent corruption of the

received data, the PHY corrects for BLW and can receive the ANSI X3.263-1995 FDDI TP-PMD

defined “killer packet” with no bit errors.

The 100M PLL generates multiple phases of the 125MHz clock. A multiplexer, controlled by the timing

unit of the DSP, selects the optimum phase for sampling the data. This is used as the received

recovered clock. This clock is used to extract the serial data from the received signal.

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7.2.2.3

7.2.2.4

NRZI and MLT-3 Decoding

The DSP generates the MLT-3 recovered levels that are fed to the MLT-3 converter. The MLT-3 is then

converted to an NRZI data stream.

Descrambler and SIPO

The descrambler performs an inverse function to the scrambler in the transmitter and also performs

the Serial In Parallel Out (SIPO) conversion of the data.

During reception of IDLE (/I/) symbols. the descrambler synchronizes its descrambler key to the

incoming stream. Once synchronization is achieved, the descrambler locks on this key and is able to

descramble incoming data.

Special logic in the descrambler ensures synchronization with the remote PHY by searching for IDLE

symbols within a window of 4000 bytes (40us). This window ensures that a maximum packet size of

1514 bytes, allowed by the IEEE 802.3 standard, can be received with no interference. If no IDLE-

symbols are detected within this time-period, receive operation is aborted and the descrambler re-starts

the synchronization process.

The de-scrambled signal is then aligned into 5-bit code-groups by recognizing the /J/K/ Start-of-Stream

Delimiter (SSD) pair at the start of a packet. Once the code-word alignment is determined, it is stored

and utilized until the next start of frame.

7.2.2.5

7.2.2.6

7.2.2.7

5B/4B Decoding

The 5-bit code-groups are translated into 4-bit data nibbles according to the 4B/5B table shown in

T a ble 7.2. The translated data is presented on the internal MII RXD[3:0] signal lines to the switch fabric

MAC. The SSD, /J/K/, is translated to “0101 0101” as the first 2 nibbles of the MAC preamble.

Reception of the SSD causes the PHY to assert the RXDV signal, indicating that valid data is available

on the RXD bus. Successive valid code-groups are translated to data nibbles. Reception of either the

End of Stream Delimiter (ESD) consisting of the /T/R/ symbols, or at least two /I/ symbols causes the

PHY to de-assert carrier sense and RXDV. These symbols are not translated into data.

Receiver Errors

During a frame, unexpected code-groups are considered receive errors. Expected code groups are the

DATA set (0 through F), and the /T/R/ (ESD) symbol pair. When a receive error occurs, the internal

MII’s RXER signal is asserted and arbitrary data is driven onto the internal receive data bus (RXD) to

the switch fabric MAC. Should an error be detected during the time that the /J/K/ delimiter is being

decoded (bad SSD error), RXER is asserted and the value 1110b is driven onto the internal receive

data bus (RXD) to the switch fabric MAC. Note that the internal MII’s data valid signal (RXDV) is not

yet asserted when the bad SSD occurs.

MII MAC Interface

For reception, the 4-bit data nibbles are sent to the MII MAC Interface block where they are sent via

MII to the switch fabric MAC. The MII MAC Interface is described in detail in Section 7.2.7, "MII MAC

Interface".

Note: The PHY is connected to the switch fabric MAC via standard MII signals. Refer to the IEEE

802.3 specification for additional details.

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7.2.3

10BASE-T Transmit

Data to be transmitted comes from the switch fabric MAC. The 10BASE-T transmitter receives 4-bit

nibbles from the internal MII at a rate of 2.5MHz and converts them to a 10Mbps serial data stream.

The data stream is then Manchester-encoded and sent to the analog transmitter, which drives a signal

onto the twisted pair via the external magnetics.

10BASE-T transmissions use the following blocks:

„

MII MAC Interface (digital)

10M TX Driver (digital/analog)

10M PLL (analog)

7.2.3.1

7.2.3.2

MII MAC Interface

For a transmission, the switch fabric MAC drives the transmit data to the PHYs MII MAC Interface.

The MII MAC Interface is described in detail in Section 7.2.7, "MII MAC Interface".

Note: The PHY is connected to the switch fabric MAC via standard MII signals. Refer to the IEEE

802.3 specification for additional details.

10M TX Driver and PLL

The 4-bit wide data is sent to the 10M TX Driver block. The nibbles are converted to a 10Mbps serial

NRZI data stream. The 10M PLL locks onto the external clock or internal oscillator and produces a

20MHz clock. This is used to Manchester encode the NRZ data stream. When no data is being

transmitted (TXEN is low), the 10M TX Driver block outputs Normal Link Pulses (NLPs) to maintain

communications with the remote link partner. The manchester encoded data is sent to the analog

transmitter where it is shaped and filtered before being driven out as a differential signal across the

TXPx and TXNx outputs (where “x” is replaced with “1” for the Port 1 PHY, or “2” for the Port 2 PHY).

7.2.4

10BASE-T Receive

The 10BASE-T receiver gets the Manchester-encoded analog signal from the cable via the magnetics.

It recovers the receive clock from the signal and uses this clock to recover the NRZI data stream. This

10M serial data is converted to 4-bit data nibbles which are passed to the controller across the internal

MII at a rate of 2.5MHz.

10BASE-T reception uses the following blocks:

„

Filter and SQUELCH (analog)

10M RX (digital/analog)

MII MAC Interface (digital)

10M PLL (analog)

7.2.4.1

Filter and Squelch

The Manchester signal from the cable is fed into the PHY on inputs RXPx and RXNx (where “x” is

replaced with “1” for Port 1, or “2” for Port 2) via 1:1 ratio magnetics. It is first filtered to reduce any

out-of-band noise. It then passes through a SQUELCH circuit. The SQUELCH is a set of amplitude

and timing comparators that normally reject differential voltage levels below 300mV and detect and

recognize differential voltages above 585mV.

7.2.4.2

10M RX and PLL

The output of the SQUELCH goes to the 10M RX block where it is validated as Manchester encoded

data. The polarity of the signal is also checked. If the polarity is reversed (local RXP is connected to

RXN of the remote partner and vice versa), then this is identified and corrected. The reversed condition

is indicated by the flag “XPOL“, bit 4 in Port x PHY Special Control/Status Indication Register

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(PHY_SPECIAL_CONTROL_STAT_IND_x). The 10M PLL locks onto the received Manchester signal

and generates the received 20MHz clock from it. Using this clock, the Manchester encoded data is

extracted and converted to a 10MHz NRZI data stream. It is then converted from serial to 4-bit wide

parallel data.

The RX10M block also detects valid 10BASE-T IDLE signals - Normal Link Pulses (NLPs) - to maintain

the link.

7.2.4.3

MII MAC Interface

For reception, the 4-bit data nibbles are sent to the MII MAC Interface block where they are sent via

MII to the switch fabric MAC. The MII MAC Interface is described in detail in Section 7.2.7, "MII MAC

Interface".

Note: The PHY is connected to the switch fabric MAC via standard MII signals. Refer to the IEEE

802.3 specification for additional details.

7.2.4.4

Jabber Detection

Jabber is a condition in which a station transmits for a period of time longer than the maximum

permissible packet length, usually due to a fault condition, that results in holding the TXEN input for

an extended period of time. Special logic is used to detect the jabber state and abort the transmission

to the line, within 45ms. Once TXEN is deasserted, the logic resets the jabber condition.

7.2.5

PHY Auto-negotiation

The purpose of the auto-negotiation function is to automatically configure the PHY to the optimum link

parameters based on the capabilities of its link partner. Auto-negotiation is a mechanism for

exchanging configuration information between two link-partners and automatically selecting the highest

performance mode of operation supported by both sides. Auto-negotiation is fully defined in clause 28

of the IEEE 802.3 specification and is enabled by setting bit 12 (PHY_AN) of the Port x PHY Basic

Control Register (PHY_BASIC_CONTROL_x).

The advertised capabilities of the PHY are stored in the Port x PHY Auto-Negotiation Advertisement

both full or half-duplex modes. Besides the connection speed, the PHY can advertise remote fault

indication and symmetric or asymmetric pause flow control as defined in the IEEE 802.3 specification.

The LAN9312 does not support “Next Page” capability. Many of the default advertised capabilities of

the PHY are determined via configuration straps as shown in Section 14.4.2.5, "Port x PHY Auto-

Negotiation Advertisement Register (PHY_AN_ADV_x)," on page 293. Refer to Section 4.2.4,

"Configuration Straps," on page 40 for additional details on how to use the LAN9312 configuration

straps.

Once auto-negotiation has completed, information about the resolved link and the results of the

negotiation process are reflected in the speed indication bits in the Port x PHY Special Control/Status

Partner Base Page Ability Register (PHY_AN_LP_BASE_ABILITY_x).

The auto-negotiation protocol is a purely physical layer activity and proceeds independently of the MAC

controller.

The following blocks are activated during an Auto-negotiation session:

„

Auto-negotiation (digital)

100M ADC (analog)

100M PLL (analog)

100M equalizer/BLW/clock recovery (DSP)

10M SQUELCH (analog)

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„

10M PLL (analog)

10M TX Driver (analog)

Auto-negotiation is started by the occurrence of any of the following events:

„

Power-On Reset (POR)

Hardware reset (nRST)

PHY Software reset (via Reset Control Register (RESET_CTL), or bit 15 of the Port x PHY Basic

Control Register (PHY_BASIC_CONTROL_x))

„

PHY Power-down reset (Section 7.2.9, "PHY Power-Down Modes," on page 94)

PHY Link status down (bit 2 of the Port x PHY Basic Status Register (PHY_BASIC_STATUS_x) is

cleared)

„

Setting the Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x), bit 9 high (auto-neg

restart)

„

Digital Reset (via bit 0 of the Reset Control Register (RESET_CTL))

Issuing an EEPROM Loader RELOAD command (Section 10.2.4, "EEPROM Loader," on page 149)

Note: Refer to Section 4.2, "Resets," on page 36 for information on these and other system resets.

On detection of one of these events, the PHY begins auto-negotiation by transmitting bursts of Fast

Link Pulses (FLP). These are bursts of link pulses from the 10M TX Driver. They are shaped as Normal

Link Pulses and can pass uncorrupted down CAT-3 or CAT-5 cable. A Fast Link Pulse Burst consists

of up to 33 pulses. The 17 odd-numbered pulses, which are always present, frame the FLP burst. The

16 even-numbered pulses, which may be present or absent, contain the data word being transmitted.

Presence of a data pulse represents a “1”, while absence represents a “0”.

The data transmitted by an FLP burst is known as a “Link Code Word.” These are defined fully in IEEE

802.3 clause 28. In summary, the PHY advertises 802.3 compliance in its selector field (the first 5 bits

of the Link Code Word). It advertises its technology ability according to the bits set in the Port x PHY

Auto-Negotiation Advertisement Register (PHY_AN_ADV_x).

There are 4 possible matches of the technology abilities. In the order of priority these are:

„

100M Full Duplex (highest priority)

100M Half Duplex

10M Full Duplex

10M Half Duplex (lowest priority)

If the full capabilities of the PHY are advertised (100M, full-duplex), and if the link partner is capable

of 10M and 100M, then auto-negotiation selects 100M as the highest performance mode. If the link

partner is capable of half and full-duplex modes, then auto-negotiation selects full-duplex as the highest

performance mode.

Once a speed and duplex match has been determined, the link code words are repeated with the

acknowledge bit set. Any difference in the main content of the link code words at this time will cause

auto-negotiation to re-start. Auto-negotiation will also re-start if all of the required FLP bursts are not

received.

Writing the Port x PHY Auto-Negotiation Advertisement Register (PHY_AN_ADV_x) bits [8:5] allows

software control of the capabilities advertised by the PHY. Writing the Port x PHY Auto-Negotiation

Advertisement Register (PHY_AN_ADV_x) does not automatically re-start auto-negotiation. The Port

x PHY Basic Control Register (PHY_BASIC_CONTROL_x), bit 9 must be set before the new abilities

will be advertised. Auto-negotiation can also be disabled via software by clearing bit 12 of the Port x

PHY Basic Control Register (PHY_BASIC_CONTROL_x).

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7.2.5.1

PHY Pause Flow Control

The Port 1 & 2 PHYs are capable of generating and receiving pause flow control frames per the IEEE

802.3 specification. The PHYs advertised pause flow control abilities are set via bits 10 (Symmetric

Pause) and 11 (Asymmetric Pause) of the Port x PHY Auto-Negotiation Advertisement Register

(PHY_AN_ADV_x). This allows the PHY to advertise its flow control abilities and auto-negotiate the

flow control settings with its link partner. The default values of these bits are determined via

configuration straps as defined in Section 14.4.2.5, "Port x PHY Auto-Negotiation Advertisement

The pause flow control settings may also be manually set via the manual flow control registers Port 1

Manual Flow Control Register (MANUAL_FC_1) and Port 2 Manual Flow Control Register

(MANUAL_FC_2). These registers allow the switch fabric ports flow control settings to be manually set

when auto-negotiation is disabled or the Manual Flow Control Select bit 0 is set. The currently enabled

duplex and flow control settings can also be monitored via these registers. The flow control values in

the Port x PHY Auto-Negotiation Advertisement Register (PHY_AN_ADV_x) are not affected by the

values of the manual flow control register. Refer to Section 6.2.3, "Flow Control Enable Logic," on

page 58 for additional information.

7.2.5.2

Parallel Detection

If the LAN9312 is connected to a device lacking the ability to auto-negotiate (i.e. no FLPs are

detected), it is able to determine the speed of the link based on either 100M MLT-3 symbols or 10M

Normal Link Pulses. In this case the link is presumed to be half-duplex per the IEEE 802.3 standard.

This ability is known as “Parallel Detection.” This feature ensures interoperability with legacy link

partners. If a link is formed via parallel detection, then bit 0 in the Port x PHY Auto-Negotiation

Expansion Register (PHY_AN_EXP_x) is cleared to indicate that the link partner is not capable of auto-

negotiation. If a fault occurs during parallel detection, bit 4 of the Port x PHY Auto-Negotiation

Expansion Register (PHY_AN_EXP_x) is set.

The P ort

PHY Auto-Negotiation Link Partner Base Page Ability Register

(PHY_AN_LP_BASE_ABILITY_x) is used to store the Link Partner Ability information, which is coded

in the received FLPs. If the link partner is not auto-negotiation capable, then this register is updated

after completion of parallel detection to reflect the speed capability of the link partner.

7.2.5.3

Restarting Auto-Negotiation

Auto-negotiation can be re-started at any time by setting bit 9 of the Port x PHY Basic Control Register

(PHY_BASIC_CONTROL_x). Auto-negotiation will also re-start if the link is broken at any time. A

broken link is caused by signal loss. This may occur because of a cable break, or because of an

interruption in the signal transmitted by the Link Partner. Auto-negotiation resumes in an attempt to

determine the new link configuration.

If the management entity re-starts Auto-negotiation by writing to bit 9 of the Port x PHY Basic Control

operations. Once the internal break link time of approximately 1200ms has passed in the Auto-

negotiation state-machine, the auto-negotiation will re-start. In this case, the link partner will have also

dropped the link due to lack of a received signal, so it too will resume auto-negotiation.

7.2.5.4

Disabling Auto-Negotiation

Auto-negotiation can be disabled by clearing bit 12 of the Port x PHY Basic Control Register

(PHY_BASIC_CONTROL_x). The PHY will then force its speed of operation to reflect the speed (bit

13) and duplex (bit 8) of the Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x). The

speed and duplex bits in the Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x) should

be ignored when auto-negotiation is enabled.

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7.2.5.5

Half Vs. Full-Duplex

Half-duplex operation relies on the CSMA/CD (Carrier Sense Multiple Access / Collision Detect)

protocol to handle network traffic and collisions. In this mode, the carrier sense signal, CRS, responds

to both transmit and receive activity. If data is received while the PHY is transmitting, a collision results.

In full-duplex mode, the PHY is able to transmit and receive data simultaneously. In this mode, CRS

responds only to receive activity. The CSMA/CD protocol does not apply and collision detection is

disabled.

7.2.6

HP Auto-MDIX

HP Auto-MDIX facilitates the use of CAT-3 (10 BASE-T) or CAT-5 (100 BASE-T) media UTP

interconnect cable without consideration of interface wiring scheme. If a user plugs in either a direct

connect LAN cable or a cross-over patch cable, as shown in Figure 7.4 (See Note 7.1 on page 83), the

PHY is capable of configuring the TXPx/TXNx and RXPx/RXNx twisted pair pins for correct transceiver

operation.

The internal logic of the device detects the TX and RX pins of the connecting device. Since the RX

and TX line pairs are interchangeable, special PCB design considerations are needed to accommodate

the symmetrical magnetics and termination of an Auto-MDIX design.

The Auto-MDIX function can be disabled through bit 15 (AMDIXCTRL) of the Port x PHY Special

Control/Status Indication Register (PHY_SPECIAL_CONTROL_STAT_IND_x). When AMDIXCTRL is

cleared, Auto-MDIX can be selected via the auto_mdix_strap_x configuration strap. The MDIX can also

be configured manually via the manual_mdix_strap_x if both the AMDIXCTRL bit and the

auto_mdix_strap_x configuration strap are low. Refer to Section 3.2, "Pin Descriptions," on page 28 for

more information on the configuration straps.

When bit 15 (AMDIXCTRL) of the Port x PHY Special Control/Status Indication Register

(PHY_SPECIAL_CONTROL_STAT_IND_x) is set to 1, the Auto-MDIX capability is determined by bits

13 and 14 of the P ort

PHY Special Control/Status Indication Register

(PHY_SPECIAL_CONTROL_STAT_IND_x).

RJ-45 8-pin straight-through

for 10BASE-T/100BASE-TX

signaling

RJ-45 8-pin cross-over for

10BASE-T/100BASE-TX

signaling

TXPx

TXNx

TXPx

TXNx

TXPx

TXNx

RXPx

Not Used

RXNx

Not Used

RXNx

Not Used

RXNx

Not Used

RXNx

Not Used

Direct Connect Cable

Cross-Over Cable

Figure 7.4 Direct Cable Connection vs. Cross-Over Cable Connection

7.2.7

MII MAC Interface

The MII MAC Interface is responsible for the transmission and reception of the Ethernet data to and

from the switch fabric MAC. The PHY is connected internally to the switch fabric MAC via standard

MII signals per IEEE 802.3.

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For a transmission, the switch fabric MAC drives the transmit data onto the internal MII TXD bus and

asserts TXEN to indicate valid data. The data is in the form of 4-bit wide data at a rate of 25MHz for

100BASE-TX, or 2.5MHz for 10BASE-T.

For reception, the 4-bit data nibbles are sent to the MII MAC Interface block. These data nibbles are

clocked to the controller at a rate of 25MHz for 100BASE-TX, or 2.5MHz for 10BASE-T. RXCLK is the

output clock for the internal MII bus. It is recovered from the received data to clock the RXD bus. If

there is no received signal, it is derived from the system reference clock.

7.2.8

PHY Management Control

The PHY Management Control block is responsible for the management functions of the PHY,

including register access and interrupt generation. A Serial Management Interface (SMI) is used to

support registers 0 through 6 as required by the IEEE 802.3 (Clause 22), as well as the vendor specific

registers allowed by the specification. The SMI interface consists of the MII Management Data (MDIO)

signal and the MII Management Clock (MDC) signal. These signals interface to the Host MAC and

allow access to all PHY registers. Refer to Section 14.4.2, "Port 1 & 2 PHY Registers," on page 285

for a list of all supported registers and register descriptions. Non-supported registers will be read as

FFFFh.

7.2.8.1

PHY Interrupts

The PHY contains the ability to generate various interrupt events as described in T a ble 7.3. Reading

the Port x PHY Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x) shows the source of

the interrupt, and clears the interrupt signal. The Port x PHY Interrupt Mask Register

(PHY_INTERRUPT_MASK_x) enables or disables each PHY interrupt. The PHY Management Control

block aggregates the enabled interrupts status into an internal signal which is sent to the System

Interrupt Controller and is reflected via the Interrupt Status Register (INT_STS) bit 26 (PHY_INT1) for

the Port 1 PHY, and bit 27 (PHY_INT2) for the Port 2 PHY. For more information on the LAN9312

interrupts, refer to Chapter 5, "System Interrupts," on page 49.

Table 7.3 PHY Interrupt Sources

PHY_INTERRUPT_MASK_x &

PHY_INTERRUPT_SOURCE_x REGISTER BIT #

INTERRUPT SOURCE

ENERGYON Activated

Auto-Negotiation Complete

Remote Fault Detected

Link Down (Link Status Negated)

Auto-Negotiation LP Acknowledge

Parallel Detection Fault

Auto-Negotiation Page Received

7.2.9

PHY Power-Down Modes

There are two power-down modes for the PHY:

„

PHY General Power-Down

PHY Energy Detect Power-Down

Note: For more information on the various power management features of the LAN9312, refer to

Section 4.3, "Power Management," on page 46.

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Note: The power-down modes of each PHY (Port 1 PHY and Port 2 PHY) are controlled

independently.

Note: The PHY power-down modes do not reload or reset the PHY registers.

7.2.9.1

7.2.9.2

PHY General Power-Down

This power-down mode is controlled by bit 11 of the Port x PHY Basic Control Register

(PHY_BASIC_CONTROL_x). In this mode the entire PHY, except the PHY management control

interface, is powered down. The PHY will remain in this power-down state as long as bit 11 is set.

When bit 11 is cleared, the PHY powers up and is automatically reset.

PHY Energy Detect Power-Down

This power-down mode is enabled by setting bit 13 (EDPWRDOWN) of the Port x PHY Mode

Control/Status Register (PHY_MODE_CONTROL_STATUS_x). When in this mode, if no energy is

detected on the line, the entire PHY is powered down except for the PHY management control

interface, the SQUELCH circuit, and the ENERGYON logic. The ENERGYON logic is used to detect

the presence of valid energy from 100BASE-TX, 10BASE-T, or auto-negotiation signals and is

responsible for driving the ENERGYON signal (bit 1) of the Port x PHY Mode Control/Status Register

(PHY_MODE_CONTROL_STATUS_x).

In this mode, when the ENERGYON signal is cleared, the PHY is powered down and no data is

transmitted from the PHY. When energy is received, via link pulses or packets, the ENERGYON signal

goes high, and the PHY powers up. The PHY automatically resets itself into its previous state prior to

power-down, and asserts the INT7 interrupt (bit 7) of the Port x PHY Interrupt Source Flags Register

(PHY_INTERRUPT_SOURCE_x). The first and possibly second packet to activate ENERGYON may

be lost.

When bit 13 (EDPWRDOWN) of the P ort x PHY Mode Control/Status Register

(PHY_MODE_CONTROL_STATUS_x) is low, energy detect power-down is disabled.

The energy detect power down feature is part of the broader power management features of the

LAN9312 and can be used to trigger the power management event output pin (PME). This is

accomplished by enabling the energy detect power-down feature of the PHY as described above, and

setting the corresponding energy detect enable (bit 14 for Port 1 PHY, bit 15 for Port 2 PHY) of the

Power Management Control Register (PMT_CTRL). Refer to Section 4.3, "Power Management," on

page 46 for additional information.

7.2.10

PHY Resets

In addition to the chip-level hardware reset (nRST) and Power-On Reset (POR), the PHY supports

three block specific resets. These are discussed in the following sections. For detailed information on

all LAN9312 resets and the reset sequence refer to Section 4.2, "Resets," on page 36.

Note: The DIGITAL_RST bit in the Reset Control Register (RESET_CTL) does not reset the PHYs.

Only a hardware reset (nRST) or an EEPROM RELOAD command will automatically reload

the configuration strap values into the PHY registers. For all other PHY resets, these values

will need to be manually configured via software.

7.2.10.1

PHY Software Reset via RESET_CTL

The PHY can be reset via the Reset Control Register (RESET_CTL). The Port 1 PHY is reset by

setting bit 1 (PHY1_RST), and the Port 2 PHY is reset by setting bit 2 (PHY2_RST). These bits are

self clearing after approximately 102uS. This reset does not reload the configuration strap values into

the PHY registers.

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7.2.10.2

7.2.10.3

7.2.11

PHY Software Reset via PHY_BASIC_CTRL_x

The PHY can also be reset by setting bit 15 (PHY_RST) of the Port x PHY Basic Control Register

(PHY_BASIC_CONTROL_x). This bit is self clearing and will return to 0 after the reset is complete.

This reset does not reload the configuration strap values into the PHY registers.

PHY Power-Down Reset

After the PHY has returned from a power-down state, a reset of the PHY is automatically generated.

The PHY power-down modes do not reload or reset the PHY registers. Refer to Section 7.2.9, "PHY

Power-Down Modes," on page 94 for additional information.

LEDs

Each PHY provides LED indication signals to the GPIO/LED block of the LAN9312. This allows

external LEDs to be used to indicate various PHY related functions such as TX/RX activity, speed,

duplex, or link status. Refer to Chapter 13, "GPIO/LED Controller," on page 162 for additional

information on the configuration of these signals.

7.2.12

Required Ethernet Magnetics

The magnetics selected for use with the LAN9312 should be an Auto-MDIX style magnetic, which is

widely available from several vendors. Please review the SMSC Application note 8.13 “Suggested

Magnetics” for the latest qualified and suggested magnetics. A list of vendors and part numbers are

provided within the application note.

7.3

Virtual PHY

The Virtual PHY provides a basic MII management interface (MDIO) to the Host MAC per the IEEE

802.3 (clause 22) so that an unmodified driver can be supported as if the Host MAC was attached to

a single port PHY. This functionality is designed to allow easy and quick integration of the LAN9312

into designs with minimal driver modifications. The Virtual PHY provides a full bank of registers which

comply with the IEEE 802.3 specification. This enables the Virtual PHY to provide various status and

control bits similar to those provided by a real PHY. These include the output of speed selection,

duplex, loopback, isolate, collision test, and auto-negotiation status. For a list of all Virtual PHY

registers and related bit descriptions, refer to Section 14.4.1, "Virtual PHY Registers," on page 285.

7.3.1

Virtual PHY Auto-Negotiation

The purpose of the auto-negotiation function is to automatically configure the Virtual PHY to the

optimum link parameters based on the capabilities of its link partner. Because the Virtual PHY has no

actual link partner, the auto-negotiation process is emulated with deterministic results.

Auto-negotiation is enabled by setting bit 12 (VPHY_AN) of the Virtual PHY Basic Control Register

(VPHY_BASIC_CTRL) and is restarted by the occurrence of any of the following events:

„

Power-On Reset (POR)

Hardware reset (nRST)

PHY Software reset (via bit 3 of the Reset Control Register (RESET_CTL), bit 0 of the Power

Management Control Register (PMT_CTRL), or bit 15 of the Virtual PHY Basic Control Register

(VPHY_BASIC_CTRL))

„

Setting the Virtual PHY Basic Control Register (VPHY_BASIC_CTRL), bit 9 high (auto-neg restart)

Digital Reset (via bit 10 of the Reset Control Register (RESET_CTL))

Issuing an EEPROM Loader RELOAD command (Section 10.2.4, "EEPROM Loader," on page 149)

The emulated auto-negotiation process is much simpler than the real process and can be categorized

into three steps:

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1. Bit

(Auto-Negotiation Complete) is set in the Virtual PHY Basic Status Register

(VPHY_BASIC_STATUS).

2. Bit 1 (Page Received) is set in the Virtual PHY Auto-Negotiation Expansion Register

(VPHY_AN_EXP).

3. The auto-negotiation result (speed and duplex) is determined and registered.

The auto-negotiation result (speed and duplex) is determined using the Highest Common Denominator

(HCD) of the Virtual PHY Auto-Negotiation Advertisement Register (VPHY_AN_ADV) and Virtual PHY

Auto-Negotiation Link Partner Base Page Ability Register (VPHY_AN_LP_BASE_ABILITY) as

specified in the IEEE 802.3 standard. The technology ability bits of these registers are ANDed, and if

there are multiple bits in common, the priority is determined as follows:

„

100Mbps Full Duplex (highest priority)

100Mbps Half Duplex

10Mbps Full Duplex

10Mbps Half Duplex (lowest priority)

For example, if the full capabilities of the Virtual PHY are advertised (100Mbps, Full Duplex), and if

the link partner is capable of 10Mbps and 100Mbps, then auto-negotiation selects 100Mbps as the

highest performance mode. If the link partner is capable of half and full-duplex modes, then auto-

negotiation selects full-duplex as the highest performance operation. In the event that there are no bits

in common, an emulated Parallel Detection is used.

The Virtual PHY Auto-Negotiation Advertisement Register (VPHY_AN_ADV) defaults to having all four

ability bits set. These values can be reconfigured via software. Once the auto-negotiation is complete,

any change to the Virtual PHY Auto-Negotiation Advertisement Register (VPHY_AN_ADV) will not take

affect until the auto-negotiation process is re-run. The emulated link partner always advertises all four

abilities (100BASE-X full duplex, 100BASE-X half duplex, 10BASE-T full duplex, and 10BASE-T half

duplex) in the Virtual PHY Auto-Negotiation Link Partner Base Page Ability Register

(VPHY_AN_LP_BASE_ABILITY). Neither the Virtual PHY or the emulated link partner support next

page capability, remote faults, or 100BASE-T4.

If there is at least one common selection between the emulated link partner and the Virtual PHY

advertised abilities, then the auto-negotiation succeeds, the Link Partner Auto-Negotiation Able bit 0

of the Virtual PHY Auto-Negotiation Expansion Register (VPHY_AN_EXP) is set, and the technology

ability bits in the Virtual PHY Auto-Negotiation Link Partner Base Page Ability Register

(VPHY_AN_LP_BASE_ABILITY) are set to indicate the emulated link partners abilities.

Note: For the Virtual PHY, the auto-negotiation register bits (and management of such) are used by

the Host MAC. So the perception of local and link partner is reversed. The local device is the

Host MAC, while the link partner is the switch fabric. This is consistent with the intention of the

Virtual PHY.

7.3.1.1

Parallel Detection

In the event that there are no common bits between the advertised ability and the emulated link

partners ability, auto-negotiation fails and emulated parallel detect is used. In this case, the Link

Partner Auto-Negotiation Able (bit 0) in the Virtual PHY Auto-Negotiation Expansion Register

(VPHY_AN_EXP) will be cleared, and the communication set to 100Mbps half-duplex. Only one of the

technology ability bits in the Virtual PHY Auto-Negotiation Link Partner Base Page Ability Register

(VPHY_AN_LP_BASE_ABILITY) will be set, indicating the emulated parallel detect result.

7.3.1.2

Disabling Auto-Negotiation

Auto-negotiation can be disabled in the Virtual PHY by clearing bit 12 (VPHY_AN) of the Virtual PHY

Basic Control Register (VPHY_BASIC_CTRL). The Virtual PHY will then force its speed of operation

to reflect the speed (bit 13) and duplex (bit 8) of the Virtual PHY Basic Control Register

(VPHY_BASIC_CTRL). The speed and duplex bits in the Virtual PHY Basic Control Register

(VPHY_BASIC_CTRL) should be ignored when auto-negotiation is enabled.

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7.3.1.3

Virtual PHY Pause Flow Control

The Virtual PHY supports pause flow control per the IEEE 802.3 specification. The Virtual PHYs

advertised pause flow control abilities are set via bits 10 (Symmetric Pause) and 11 (Asymmetric

Pause) of the Virtual PHY Auto-Negotiation Advertisement Register (VPHY_AN_ADV). This allows the

Virtual PHY to advertise its flow control abilities and auto-negotiate the flow control settings with the

emulated link partner. The default values of these bits are as shown in Section 14.2.8.5, "Virtual PHY

Auto-Negotiation Advertisement Register (VPHY_AN_ADV)," on page 252.

The symmetric/asymmetric pause ability of the emulated link partner is based upon the advertised

pause flow control abilities of the Virtual PHY in (bits 10 & 11) of the Virtual PHY Auto-Negotiation

Advertisement Register (VPHY_AN_ADV). Thus, the emulated link partner always accommodates the

asymmetric/symmetric pause ability settings requested by the Virtual PHY, as shown in T a ble 14.5,

“Emulated Link Partner Pause Flow Control Ability Default Values,” on page 255.

The pause flow control settings may also be manually set via the Port 0(Host MAC) Manual Flow

Control Register (MANUAL_FC_MII). This register allows the switch fabric port 0 flow control settings

to be manually set when auto-negotiation is disabled or the Manual Flow Control Select bit 0 is set.

The currently enabled duplex and flow control settings can also be monitored via this register. The flow

control values in the Virtual PHY Auto-Negotiation Advertisement Register (VPHY_AN_ADV) are not

affected by the values of the manual flow control register. Refer to Section 6.2.3, "Flow Control Enable

Logic," on page 58 for additional information.

7.3.2

Virtual PHY Resets

In addition to the chip-level hardware reset (nRST) and Power-On Reset (POR), the Virtual PHY

supports three block specific resets. These are is discussed in the following sections. For detailed

information on all LAN9312 resets, refer to Section 4.2, "Resets," on page 36.

7.3.2.1

7.3.2.2

7.3.2.3

Virtual PHY Software Reset via RESET_CTL

The Virtual PHY can be reset via the Reset Control Register (RESET_CTL) by setting bit 3

(VPHY_RST). This bit is self clearing after approximately 102uS.

Virtual PHY Software Reset via VPHY_BASIC_CTRL

The Virtual PHY can also be reset by setting bit 15 (VPHY_RST) of the Virtual PHY Basic Control

Virtual PHY Software Reset via PMT_CTRL

The Virtual PHY can be reset via the Power Management Control Register (PMT_CTRL) by setting bit

10 (VPHY_RST). This bit is self clearing after approximately 102uS.

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Chapter 8 Host Bus Interface (HBI)

8.1

Functional Overview

The Host Bus Interface (HBI) module provides a high-speed asynchronous SRAM-like slave interface

that facilitates communication between the LAN9312 and a host system. The HBI allows access to the

System CSRs and handles byte swapping based on the dynamic endianess select. The HBI interfaces

to the switch fabric via the Host MAC, which contains the TX/RX Data and Status FIFOs, Host MAC

registers and power management features. Refer to Chapter 9, "Host MAC," on page 112 for detailed

information on the Host MAC.

The following is an overview of the functions provided by the HBI:

Asynchronous 32-bit Host Bus Interface: The HBI provides an asynchronous SRAM-like Host Bus

Interface that is compatible with most CPUs.

„

Host data bus endianess control: The HBI supports dynamic selection of big and little endian

host byte ordering based on the END_SEL input pin. This highly flexible interface provides mixed

endian access for registers and memory.

Direct FIFO access modes: When the FIFO_SEL input pin is high during host access, all host

write operations are to the TX data FIFO and all host read operations are from the RX data FIFOs.

This feature facilitates operation with host DMA controllers that do not support FIFO operations.

System CSR’s: The HBI allows for configuration and monitoring of the various LAN9312 functions

through the System Control and Status Registers (CSRs). These registers are accessible to the host

via the Host Bus Interface and allow direct (and indirect) access to all the LAN9312 functions. For a

full list of all System CSR’s and their descriptions, refer to Section 14.2, "System Control and Status

Registers".

Interrupt support: The HBI supports a variety of interrupt sources. Individual interrupts can be

monitored and enabled/disabled via registers within the System CSRs for output on the IRQ pin. For

more information on interrupts, refer to Chapter 5, "System Interrupts," on page 49.

For a list of all HBI related pins, refer to T a ble 3.4 on page 30 in Chapter 3, Pin Description and

Configuration.

8.2

8.3

Host Memory Mapping

The host memory map has two unique modes: normal operation mode, and direct FIFO access mode.

During normal operation, the base address decode map is as described in Figure 14.1 on page 166,

allowing access to the full range of System Management CSRs and the TX/RX Data and Status FIFOs.

This is the default mode of operation. The second mode of operation is the direct FIFO access mode.

In direct FIFO access mode, all host write operations are to the TX Data FIFO and all host read

operations are from the RX Data FIFO. Refer to Section 14.1.3, "Direct FIFO Access Mode," on

page 167 for additional information.

Host Endianess

The LAN9312 supports big and little endian host byte ordering based upon the END_SEL pin. When

END_SEL is low, host access is little endian. When END_SEL is high, host access is big endian. In a

typical application, END_SEL is connected to a high-order address line, making endian selection

address based. This highly flexible interface provides mixed endian access for registers and memory

for both PIO and host DMA access. As an example, PIO transfers to/from the System CSRs can utilize

a different byte ordering than host DMA transactions to/from the RX and TX Data FIFOs.

All internal busses are 32-bit with little endian byte ordering. Logic within the host bus interface re-

orders bytes based on the state of the endian select signal (END_SEL).

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Data path operations for the supported endian configurations are illustrated in Figure 8.1, "Little Endian

Byte Ordering" and Figure 8.2, "Big Endian Byte Ordering".

32-BIT LITTLE ENDIAN

(END_SEL = 0)

INTERNAL ORDER

MSB

LSB

24 23

16 15

24 23

16 15

HOST DATA BUS

Figure 8.1 Little Endian Byte Ordering

32-BIT BIG ENDIAN

(END_SEL = 1)

INTERNAL ORDER

MSB

LSB

24 23

16 15

24 23

16 15

HOST DATA BUS

Figure 8.2 Big Endian Byte Ordering

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8.4

Host Interface Timing

This section details the characteristics and special restrictions of the various supported host cycles.

For detailed timing specifications on supported PIO read/write operations, refer to Section 15.5, "AC

Specifications". The LAN9312 supports the following host cycles:

Read Cycles:

„

PIO Reads (nCS or nRD controlled)

PIO Burst Reads (nCS or nRD controlled)

RX Data FIFO Direct PIO Reads (nCS or nRD controlled)

RX Data FIFO Direct PIO Burst Reads (nCS or nRD controlled)

Write Cycles:

„

PIO Writes (nCS or nWR controlled)

TX Data FIFO Direct PIO Writes (nCS or nWR controlled)

8.4.1

Special Situations

8.4.1.1

Reset Ending During a Read Cycle

If a reset condition terminates during an active read cycle, the tail end of the read cycle will be ignored

by the LAN9312.

8.4.1.2

Writes Following a Reset

Following any reset, writes from the host bus are ignored until after a read cycle is performed.

8.4.2

Special Restrictions on Back-to Back Write-Read Cycles

It is important to note that there are specific restrictions on the timing of back-to-back host write-read

operations. These restrictions concern reading the host control registers after any write cycle to the

LAN9312. In some cases there is a delay between writing to the LAN9312, and the subsequent side

effect (change in the control register value). For example, when writing to the TX Data FIFO, it takes

up to 135ns for the level indication to change in the TX FIFO Information Register (TX_FIFO_INF).

In order to prevent the host from reading stale data after a write operation, minimum wait periods have

been established. These periods are specified in T a ble 8.1. The host processor is required to wait the

specified period of time after any write to the LAN9312 before reading the resource specified in the

table. These wait periods are for read operations that immediately follow any write cycle. Note that the

required wait period is dependant upon the register being read after the write.

Performing “dummy” reads of the Byte Order T e st Register (BYTE_TEST) register is a convenient way

to guarantee that the minimum write-to-read timing restriction is met. T a ble 8.1 shows the number of

dummy reads that are required before reading the register indicated. The number of BYTE_TEST

reads in this table is based on the minimum timing for T_cyc(45ns). For microprocessors with slower

busses the number of reads may be reduced as long as the total time is equal to, or greater than the

time specified in the table. Note that dummy reads of the BYTE_TEST register are not required as

long as the minimum time period is met.

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Table 8.1 Read After Write Timing Rules

MINIMUM WAIT TIME FOR

READ FOLLOWING ANY

WRITE CYCLE (IN NS)

NUMBER OF BYTE_TEST

READS

(ASSUMING T

OF 45NS)

CYC

RX Data FIFO

RX Status FIFO

RX Status FIFO PEEK

TX Status FIFO

TX Status FIFO PEEK

ID_REV

IRQ_CFG

135

INT_STS

INT_EN

BYTE_TEST

FIFO_INT

RX_CFG

TX_CFG

HW_CFG

RX_DP_CTRL

RX_FIFO_INF

TX_FIFO_INF

135

315

135

180

PMT_CTRL

GPT_CFG

GPT_CNT

FREE_RUN

RX_DROP

MAC_CSR_CMD

MAC_CSR_DATA

AFC_CFG

1588_CLOCK_HI_RX_CAPTURE_1

1588_CLOCK_LO_RX_CAPTURE_1

1588_SEQ_ID_SRC_UUID_HI_RX_CAPTURE_1

1588_SRC_UUID_LO_RX_CAPTURE_1

1588_CLOCK_HI_TX_CAPTURE_1

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Table 8.1 Read After Write Timing Rules (continued)

MINIMUM WAIT TIME FOR

READ FOLLOWING ANY

WRITE CYCLE (IN NS)

NUMBER OF BYTE_TEST

READS

(ASSUMING T

OF 45NS)

CYC

1588_CLOCK_LO_TX_CAPTURE_1

1588_SEQ_ID_SRC_UUID_HI_TX_CAPTURE_1

1588_SRC_UUID_LO_TX_CAPTURE_1

1588_CLOCK_HI_RX_CAPTURE_2

1588_CLOCK_LO_RX_CAPTURE_2

1588_SEQ_ID_SRC_UUID_HI_RX_CAPTURE_2

1588_SRC_UUID_LO_RX_CAPTURE_2

1588_CLOCK_HI_TX_CAPTURE_2

1588_CLOCK_LO_TX_CAPTURE_2

1588_SEQ_ID_SRC_UUID_HI_TX_CAPTURE_2

1588_SRC_UUID_LO_TX_CAPTURE_2

1588_CLOCK_HI_RX_CAPTURE_MII

1588_CLOCK_LO_RX_CAPTURE_MII

1588_SEQ_ID_SRC_UUID_HI_RX_CAPTURE_MII

1588_SRC_UUID_LO_RX_CAPTURE_MII

1588_CLOCK_HI_TX_CAPTURE_MII

1588_CLOCK_LO_TX_CAPTURE_MII

1588_SEQ_ID_SRC_UUID_HI_TX_CAPTURE_MII

1588_SRC_UUID_LO_TX_CAPTURE_MII

1588_CLOCK_HI_CAPTURE_GPIO_8

1588_CLOCK_LO_CAPTURE_GPIO_8

1588_CLOCK_HI_CAPTURE_GPIO_9

1588_CLOCK_LO_CAPTURE_GPIO_9

1588_CLOCK_HI

1588_CLOCK_LO

1588_CLOCK_ADDEND

1588_CLOCK_TARGET_HI

1588_CLOCK_TARGET_LO

1588_CLOCK_TARGET_RELOAD_HI

1588_CLOCK_TARGET_RELOAD_LO

1588_AUX_MAC_HI

1588_AUX_MAC_LO

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Table 8.1 Read After Write Timing Rules (continued)

MINIMUM WAIT TIME FOR

READ FOLLOWING ANY

WRITE CYCLE (IN NS)

NUMBER OF BYTE_TEST

READS

(ASSUMING T

OF 45NS)

CYC

1588_CONFIG

1588_INT_STS_EN

MANUAL_FC_1

MANUAL_FC_2

MANUAL_FC_MII

SWITCH_CSR_DATA

SWITCH_CSR_CMD

E2P_CMD

E2P_DATA

LED_CFG

VPHY_BASIC_CTRL

VPHY_BASIC_STATUS

VPHY_ID_MSB

VPHY_ID_LSB

VPHY_AN_ADV

VPHY_AN_LP_BASE_ABILITY

VPHY_AN_EXP

VPHY_SPECIAL_CONTROL_STATUS

GPIO_CFG

GPIO_DATA_DIR

GPIO_INT_STS_EN

SWITCH_MAC_ADDRH

SWITCH_MAC_ADDRL

RESET_CTL

SWITCH_CSR_DIRECT_DATA

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8.4.3

Special Restrictions on Back-to-Back Read Cycles

There are also restrictions on specific back-to-back host read operations. These restrictions concern

reading specific registers after reading a resource that has side effects. In many cases there is a delay

between reading the LAN9312, and the subsequent indication of the expected change in the control

and status register values.

In order to prevent the host from reading stale data on back-to-back reads, minimum wait periods have

been established. These periods are specified in T a ble 8.2. The host processor is required to wait the

specified period of time between read operations of specific combinations of resources. The wait period

is dependant upon the combination of registers being read.

Performing “dummy” reads of the Byte Order T e st Register (BYTE_TEST) register is a convenient way

to guarantee that the minimum wait time restriction is met. T a ble 8.2 below also shows the number of

dummy reads that are required for back-to-back read operations. The number of BYTE_TEST reads

in this table is based on the minimum timing for T_cyc(45ns). For microprocessors with slower busses

the number of reads may be reduced as long as the total time is equal to, or greater than the time

specified in the table. Dummy reads of the BYTE_TEST register are not required as long as the

minimum time period is met.

Table 8.2 Read After Read Timing Rules

OR PERFORM THIS MANY

WAIT FOR THIS MANY

READS OF BYTE_TEST…

AFTER READING...

NANOSECONDS...

(ASSUMING T OF 45NS)

BEFORE READING...

CYC

RX Data FIFO

RX Status FIFO

TX Status FIFO

RX_DROP

135

180

RX_FIFO_INF

TX_FIFO_INF

RX_DROP

SWITCH_CSR_DATA

SWITCH_CSR_CMD

Note 8.1

VPHY_AN_EXP

Note 8.1 This timing applies only to the auto-increment and auto-decrement modes of Switch Fabric

CSR register access.

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8.4.4

PIO Reads

PIO reads can be used to access System CSR’s or RX Data and RX/TX Status FIFOs. PIO reads can

be performed using Chip Select (nCS) or Read Enable (nRD). A PIO Read cycle begins when both

nCS and nRD are asserted. Either or both of these control signals must de-assert between cycles for

the period specified in T a ble 15.8, “PIO Read Cycle Timing Values,” on page 446. The cycle ends when

either or both nCS and nRD are de-asserted. They may be asserted and de-asserted in any order.

Read data is valid as indicated in the functional timing diagram in Figure 8.3.

The endian select signal (END_SEL) has the same timing characteristics as the address lines.

Please refer to Section 15.5.4, "PIO Read Cycle Timing," on page 446 for the AC timing specifications

for PIO read operations.

Note: Some registers have restrictions on the timing of back-to-back write-read cycles. Please refer

to Section 8.4.2 for information on these restrictions.

VALID

END_SEL

A[x:2]

nCS, nRD

VALID

D[31:0] (OUTPUT)

Figure 8.3 Functional Timing for PIO Read Operation

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8.4.5

PIO Burst Reads

In this mode, performance is improved by allowing up to 8 DWORD read cycles back-to-back. PIO

burst reads can be performed using Chip Select (nCS) or Read Enable (nRD). A PIO Burst Read

begins when both nCS and nRD are asserted. Either or both of these control signals must de-assert

between bursts for the period specified in T a ble 15.9, “PIO Burst Read Cycle Timing Values,” on

page 447. The burst cycle ends when either or both nCS and nRD are de-asserted. They may be

asserted and de-asserted in any order. Read data is valid as indicated in the functional timing diagram

in Figure 8.4.

Note: Fresh data is supplied each time A[2] toggles.

The endian select signal (END_SEL) has the same timing characteristics as the upper address lines.

Please refer to Section 15.5.5, "PIO Burst Read Cycle Timing," on page 447 for the AC timing

specifications for PIO burst read operations.

Note: PIO burst reads are only supported for the RX Data FIFO. Burst reads from other registers are

not supported.

VALID

END_SEL

A[x:5]

VALID

A[4:2]

nCS, nRD

VALID

D[31:0] (OUTPUT)

Figure 8.4 Functional Timing for PIO Burst Read Operation

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8.4.6

RX Data FIFO Direct PIO Reads

In this mode only A[2] is decoded, and any read of the LAN9312 will read the RX Data FIFO. This

mode is enabled when FIFO_SEL is driven high during a read access. This is normally accomplished

by connecting the FIFO_SEL signal to a high-order address line. This mode is useful when the host

processor must increment its address when accessing the LAN9312.

Timing is identical to a PIO read and the FIFO_SEL and END_SEL signals have the same timing

characteristics as the address lines. An RX Data FIFO direct PIO read cycle begins when both nCS

and nRD are asserted. Either or both of these control signals must de-assert between cycles for the

period specified in T a ble 15.10, “RX Data FIFO Direct PIO Read Cycle Timing Values,” on page 448.

The cycle ends when either or both nCS and nRD are de-asserted. These signals may be asserted

and de-asserted in any order. Read data is valid as indicated in the functional timing diagram in

Figure 8.5.

Note: A[9:3] are ignored during RX Data FIFO direct PIO reads.

Please refer to Section 15.5.6, "RX Data FIFO Direct PIO Read Cycle Timing," on page 448 for the

AC timing specifications for RX Data FIFO direct PIO read operations.

FIFO_SEL

VALID

END_SEL

A[x:3]

A[2]

nCS, nRD

VALID

D[31:0] (OUTPUT)

(READ DATA FROM RX DATA FIFO)

Figure 8.5 Functional Timing for RX Data FIFO Direct PIO Read Operation

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8.4.7

RX Data FIFO Direct PIO Burst Reads

In this mode only A[2] is decoded, and any burst read of the LAN9312 will read the RX Data FIFO.

This mode is enabled when FIFO_SEL is driven high during a read access. This is normally

accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode is useful

when the host processor must increment its address when accessing the LAN9312. Timing is identical

to a PIO burst read, and the FIFO_SEL and END_SEL signals have the same timing characteristics

as the address lines.

In this mode, performance is improved by allowing an unlimited number of back-to-back DWORD read

cycles. RX Data FIFO direct PIO burst reads can be performed using chip select (nCS) or read enable

(nRD). An RX Data FIFO direct PIO burst read begins when both nCS and nRD are asserted. Either

or both of these control signals must de-assert between bursts for the period specified in T a ble 15.11,

“RX Data FIFO Direct PIO Burst Read Cycle Timing Values,” on page 449. The burst cycle ends when

either or both nCS and nRD are de-asserted. They may be asserted and de-asserted in any order.

Read data is valid as indicated in the functional timing diagram in Figure 8.6.

Note: Fresh data is supplied each time A[2] toggles.

Please refer to Section 15.5.7, "RX Data FIFO Direct PIO Burst Read Cycle Timing," on page 449 for

the AC timing specifications for PIO RX Data FIFO direct PIO burst read operations.

FIFO_SEL

END_SEL

A[x:3]

A[2]

nCS, nRD

D[31:0] (OUTPUT)

(READ DATA FROM RX DATA FIFO)

Figure 8.6 Functional Timing for RX Data FIFO Direct PIO Burst Read Operation

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8.4.8

PIO Writes

PIO writes are used for all LAN9312 write cycles. PIO writes can be performed using Chip Select (nCS)

or Write Enable (nWR). A PIO write cycle begins when both nCS and nWR are asserted. The cycle

ends when either or both nCS and nWR are de-asserted. Either or both of these control signals must

de-assert between cycles for the period specified in T a ble 15.12, “PIO Write Cycle Timing Values,” on

page 450. They may be asserted and de-asserted in any order. Either or both of these control signals

must be de-asserted between cycles for the period specified. The PIO write cycle is illustrated in the

functional timing diagram in Figure 8.7.

The END_SEL signal has the same timing characteristics as the address lines.

Please refer to Section 15.5.8, "PIO Write Cycle Timing," on page 450 for the AC timing specifications

for PIO write operations.

VALID

END_SEL

A[x:2]

nCS, nWR

VALID

D[31:0] (INPUT)

Figure 8.7 Functional Timing for PIO Write Operation

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8.4.9

TX Data FIFO Direct PIO Writes

In this mode only A[2] is decoded, and any write to the LAN9312 will write the TX Data FIFO. This

mode is enabled when FIFO_SEL is driven high during a write access. This is normally accomplished

by connecting the FIFO_SEL signal to a high-order address line. This mode is useful when the host

processor must increment its address when accessing the LAN9312.

Timing is identical to a PIO write, and the FIFO_SEL and END_SEL signals have the same timing

characteristics as the address lines. A TX Data FIFO direct PIO write cycle begins when both nCS and

nWR are asserted. Either or both of these control signals must de-assert between cycles for the period

specified in T a ble 15.13, “TX Data FIFO Direct PIO Write Cycle Timing Values,” on page 451. The cycle

ends when either or both nCS and nWR are de-asserted. They may be asserted and de-asserted in

any order. The TX Data FIFO direct PIO write cycle is illustrated in the functional timing diagram in

Figure 8.8.

Note: A[9:3] are ignored during TX Data FIFO direct PIO writes.

Please refer to Section 15.5.9, "TX Data FIFO Direct PIO Write Cycle Timing," on page 451 for the AC

timing specifications for TX Data FIFO direct PIO write operations.

FIFO_SEL

VALID

END_SEL

A[x:3]

A[2]

nCS, nWR

D[31:0] (INPUT)

VALID

(WRITE DATA TO TX DATA FIFO)

Figure 8.8 Functional Timing for TX Data FIFO Direct PIO Write Operation

8.5

HBI Interrupts

The HBI allows access to all interrupt configuration and status registers within the LAN9312. The

LAN9312 implements a multi-tier interrupt hierarchy with the Interrupt Configuration Register

(IRQ_CFG), Interrupt Status Register (INT_STS), and Interrupt Enable Register (INT_EN) at the top

level. These registers allow for the configuration of which interrupts trigger the IRQ, as well as the IRQ

deassertion and polarity properties. Interrupts may be generated from the 1588 Timestamping, Switch

Fabric, Port 1 PHY, Port 2 PHY, Host MAC, EEPROM Loader, General Purpose Timer, General

Purpose I/O, and Power Management blocks.

For more information of the LAN9312 interrupts, refer to Chapter 5, System Interrupts.

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Chapter 9 Host MAC

9.1

Functional Overview

The Host MAC incorporates the essential protocol requirements for operating an Ethernet/IEEE 802.3-

compliant node and provides an interface between the Host Bus Interface (HBI) and the Ethernet PHYs

and Switch Fabric. On the front end, the Host MAC interfaces to the HBI via 2 sets of FIFO’s (TX Data

FIFO, TX Status FIFO, RX Data FIFO, RX Status FIFO). An additional bus is used to access the Host

MAC CSR’s via the Host MAC CSR Interface Command Register (MAC_CSR_CMD) and Host MAC

CSR Interface Data Register (MAC_CSR_DATA) system registers.

The receive and transmit FIFO’s allow increased packet buffer storage to the Host MAC. The FIFOs

are a conduit between the HBI and the Host MAC through which all transmitted and received data and

status information is passed. Deep FIFOs allow a high degree of latency tolerance relative to the

various transport and OS software stacks reducing and minimizing overrun conditions. Both the Host

MAC and the TX/RX FIFOs have separate receive and transmit data paths.

The Host MAC can store up to 250 Ethernet packets utilizing FIFOs, totaling 16KB, with a packet

granularity of 4 bytes. This memory is shared by the RX and TX blocks and is configurable in terms

of allocation via the Hardware Configuration Register (HW_CFG) register to the ranges described in

Section 9.7.3, "FIFO Memory Allocation Configuration". This depth of buffer storage minimizes or

eliminates receive overruns.

On the back end, the Host MAC interfaces with the 10/100 Ethernet PHY’s (Virtual PHY, Port 1 PHY,

Port 2 PHY) via an internal SMI (Serial Management Interface) bus. This allows the Host MAC access

to the PHY’s internal registers via the Host MAC MII Access Register (HMAC_MII_ACC) and Host

MAC MII Data Register (HMAC_MII_DATA). The Host MAC interfaces to the Switch Engine Port 0 via

an internal MII (Media Independent Interface) connection allowing for incoming and outgoing Ethernet

packet transfers.

The Host MAC can operate at either 100Mbps or 10Mbps in both half-duplex or full-duplex modes.

When operating in half-duplex mode, the Host MAC complies fully with Section 4 of ISO/IEC 8802-3

(ANSI/IEEE standard) and ANSI/IEEE 802.3 standards. When operating in full-duplex mode, the Host

MAC complies with IEEE 802.3 full-duplex operation standard.

The Host MAC provides programmable enhanced features designed to minimize host supervision, bus

utilization, and pre- or post-message processing. These features include the ability to disable retries

after a collision, dynamic Frame Check Sequence (FCS) generation on a frame-by-frame basis,

automatic pad field insertion and deletion to enforce minimum frame size attributes, and automatic

retransmission and detection of collision frames. The Host MAC can sustain transmission or reception

of minimally-sized back-to-back packets at full line speed with an interpacket gap (IPG) of 9.6

microseconds for 10 Mbps and 0.96 microseconds for 100 Mbps.

The primary attributes of the Host MAC are:

„

Transmit and receive message data encapsulation

Framing (frame boundary delimitation, frame synchronization)

Error detection (physical medium transmission errors)

Media access management

Medium allocation (collision detection, except in full-duplex operation)

Contention resolution (collision handling, except in full-duplex operation)

Flow control during full-duplex mode

Decoding of control frames (PAUSE command) and disabling the transmitter

Generation of control frames

Interface between the Host Bus Interface and the Ethernet PHYs/Switch Fabric.

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9.2

Flow Control

The Host MAC supports full-duplex flow control using the pause operation and control frame. Half-

duplex flow control using back pressure is also supported. The Host MAC flow control is configured

via the memory mapped Host MAC Automatic Flow Control Configuration Register (AFC_CFG) located

in the System CSR space and the Host MAC Flow Control Register (HMAC_FLOW) located in the

Host MAC CSR space.

Note: The Host MAC controls the flow between the switch fabric and the Host MAC, not the network

flow control. The switch fabric handles the network flow control independently.

9.2.1

Full-Duplex Flow Control

In full-duplex mode, flow control is achieved via the pause operation and the transmission of control

frames. The pause operation inhibits transmission of data frames for a specified period of time. A

pause operation consists of a frame containing the globally assigned multicast address (01-80-C2-00-

00-01), the PAUSE opcode, and a parameter indicating the quantum of slot time (512 bit times) to

inhibit data transmissions. The PAUSE parameter may range from 0 to 65,535 slot times. The Host

MAC logic, upon receiving a frame with the reserved multicast address and PAUSE opcode, inhibits

data frame transmissions for the length of time indicated. If a pause request is received while a

transmission is in progress, the pause will take effect after the transmission is complete. Control frames

are received, processed by the Host MAC, and passed on.

The Host MAC also has the capability of transmitting control frames (pause command) via hardware

and software control. The software driver requests the Host MAC to transmit a control frame and gives

the value of the PAUSE time to be used in the control frame. The Host MAC function constructs a

control frame by setting the appropriate values in the corresponding fields (as defined in the 802.3

specification) and transmits the frame to the internal MII interface. The transmission of the control

frame is not affected by the current state of the Pause timer value that may be set due to a recently

received control frame.

9.2.2

Half-Duplex Flow Control (Backpressure)

In half-duplex mode, back pressure is used for flow control. Whenever the receive buffer/FIFO

becomes full or crosses a certain threshold level, the Host MAC starts sending a jam signal. The Host

MAC transmit logic enters a state at the end of current transmission (if any), where it waits for the

beginning of a received frame. Once a new frame starts, the Host MAC starts sending the jam signal,

which will result in a collision. After sensing the collision, the remote station will back off its

transmission. The Host MAC continues sending the jam to make other stations defer transmission. The

Host MAC only generates this collision-based back pressure when it receives a new frame, in order

to avoid any late collisions.

9.3

Virtual Local Area Network (VLAN) Support

Virtual Local Area Networks (VLANs), as defined within the IEEE 802.3 standard, provide network

administrators a means of grouping nodes within a larger network into broadcast domains. To

implement a VLAN, four extra bytes are added to the basic Ethernet packet. As shown in Figure 9.1,

the four bytes are inserted after the Source Address Field and before the Type/Length field. The first

two bytes of the VLAN tag identify the tag, and by convention are set to the value 0x8100. The last

two bytes identify the specific VLAN associated with the packet and provide a priority field.

The LAN9312 supports VLAN-tagged packets and provides two Host MAC registers, Host MAC VLAN1

T a g Register (HMAC_VLAN1) and Host MAC VLAN2 T a g Register (HMAC_VLAN2), which are used

to identify VLAN-tagged packets. The HMAC_VLAN1 register is used to specify the VLAN1 tag which

will increase the legal frame length from 1518 to 1522 bytes. The HMAC_VLAN2 register is used to

specify the VLAN2 tag which will increase the legal frame length from 1518 to 1538 bytes. If a packet

arrives bearing either of these tags in the two bytes succeeding the Source Address field, the controller

will recognize the packet as a VLAN-tagged packet, allowing the packet to be received and processed

by the host software. If both VLAN1 and VLAN2 tag Identifiers are used, each should be unique. If

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both are set to the same value, VLAN1 is given higher precedence and the maximum legal frame

length is set to 1522.

Standard Ethernet Frame (1518 Bytes)

Preamble

7 Bytes

SOF

1 Byte

Dest. Addr. Source Addr.

6 Bytes 6 Bytes

Type

2 Bytes

Data

46-1500 Bytes

FCS

4 Bytes

Ethernet Frame with VLAN TAG (1522 Bytes)

Preamble

7 Bytes

SOF

1 Byte

Dest. Addr. Source Addr.

6 Bytes 6 Bytes

TPID

Type

Data

46-1500 Bytes

FCS

4 Bytes

2 Bytes 2 Bytes 2 Bytes

Tag Control Information

(TCI)

TPID

2 Bytes

User Priority CFI

VLAN ID

12 Bits

3 Bits

1 Bit

Defines the VLAN to

which the frame belongs

Canonical Address Format Indicator

Indicates the frame’s priority

Tag Protocol ID: \x81-00

Figure 9.1 VLAN Frame

9.4

Address Filtering

The Ethernet address fields of an Ethernet packet consist of two 6-byte fields: one for the destination

address and one for the source address. The first bit of the destination address signifies whether it is

a physical address or a multicast address.

The Host MAC address check logic filters the frame based on the Ethernet receive filter mode that has

been enabled. The various filter modes of the Host MAC are specified based on the state of the control

bits in the Host MAC Control Register (HMAC_CR), as shown in T a ble 9.1. Please refer to the Section

14.3.1, "Host MAC Control Register (HMAC_CR)," on page 270 for more information on this register.

If the frame fails the filter, the Host MAC does not receive the packet. The host has the option of

accepting or ignoring the packet.

Note: This filtering function is performed after any switch fabric filtering functions. The user must

ensure the switch filtering is setup properly to allow packets to be passed to the Host MAC for

further filtering.

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Table 9.1 Address Filtering Modes

MCPAS

PRMS

INVFILT

HPFILT

DESCRIPTION

MAC address perfect filtering only

for all addresses.

MAC address perfect filtering for

physical address and hash filtering

for multicast addresses

Hash Filtering for physical and

multicast addresses

Inverse Filtering

Promiscuous

Pass all multicast frames. Frames

with physical addresses are

perfect-filtered

Pass all multicast frames. Frames

with physical addresses are hash-

filtered

9.4.1

Perfect Filtering

This filtering mode passes only incoming frames whose destination address field exactly matches the

value programmed into the Host MAC Address High Register (HMAC_ADDRH) and the Host MAC

Address Low Register (HMAC_ADDRL). The MAC address is formed by the concatenation of these

two registers.

9.4.2

Hash Only Filtering

This type of filtering checks for incoming receive packets (from switch Port 0) with either multicast or

physical destination addresses, and executes an imperfect address filtering against the hash table. The

hash table is formed by merging the values in the Host MAC Multicast Hash T a ble High Register

(HMAC_HASHH) and the Host MAC Multicast Hash T a ble Low Register (HMAC_HASHL) to form a

64-bit hash table.

During imperfect hash filtering, the upper 6-bits of the destination address of the incoming frame are

used to index the contents of the hash table. The most significant bit of the destination address

determines the register to be used (HMAC_HASHH or HMAC_HASHL), while the other five bits

determine the bit within the register. A value of 00000 selects Bit 0 of the HMAC_HASHL register and

a value of 11111 selects Bit 31 of the HMAC_HASHH register.

9.4.3

Hash Perfect Filtering

In hash perfect filtering, if the received frame is a physical address, the Host MAC packet filter will

perfect-filter the incoming frame’s destination field with the value programmed into the Host MAC

Address High Register (HMAC_ADDRH) and the Host MAC Address Low Register (HMAC_ADDRL).

However, if the incoming frame is a multicast frame, the Host MAC packet filter function performs an

imperfect address filtering against the hash table.

The imperfect filtering against the hash table is the same imperfect filtering process described in

Section 9.4.2, "Hash Only Filtering".

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9.4.4

Inverse Filtering

In inverse filtering, the Host MAC packet filter accepts incoming frames (from switch Port 0) with a

destination address not matching the perfect address (i.e., the value programmed into the Host MAC

Address High Register (HMAC_ADDRH) and the Host MAC Address Low Register (HMAC_ADDRL))

and rejects frames with destination addresses matching the perfect address.

For all filtering modes, when the MCPAS bit of the Host MAC Control Register (HMAC_CR) is set, all

multicast frames are accepted. When the PRMS bit is set, all frames are accepted regardless of their

destination address. This includes all broadcast frames as well.

9.5

Wake-up Frame Detection

Setting the Wake-Up Frame Enable bit (WUEN) in the Host MAC Wake-up Control and Status Register

(HMAC_WUCSR), places the Host MAC in the wake-up frame detection mode. In this mode, normal

data reception is disabled, and detection logic within the Host MAC examines received data for the

pre-programmed wake-up frame patterns. The Host MAC can be programmed to notify the host of the

wake-up frame detection with the assertion of the host interrupt (IRQ) or power management event

(PME) signal. Upon detection, the Wake-Up Frame Received bit (WUFR) in the HMAC_WUCSR

operation.

Before putting the Host MAC into the wake-up frame detection state, the host must provide the

detection logic with a list of sample frames and their corresponding byte masks. This information must

be written into the Host MAC Wake-up Frame Filter Register (HMAC_WUFF). The wake-up frame filter

is configured through this register using an index mechanism. After power-on reset, hardware reset,

or soft reset, the Host MAC loads the first value written to the HMAC_WUFF register to the first

DWORD in the wake-up frame filter (filter 0 byte mask). The second value written to this register is

loaded to the second DWORD in the wake-up frame filter (filter 1 byte mask) and so on for all eight

DWORDs. The wake-up frame filter functionally is described below.

The Host MAC supports four programmable wake-up filters that support many different receive packet

patterns. If remote wake-up mode is enabled, the remote wake-up function receives all frames

addressed to the Host MAC. It then checks each frame against the enabled filter and recognizes the

frame as a remote wake-up frame if it passes the wakeup frame filter register’s address filtering and

CRC value match.

In order to determine which bytes of the frames should be checked by the CRC module, the Host MAC

uses a programmable byte mask and a programmable pattern offset for each of the four supported

filters.

The pattern’s offset defines the location of the first byte that should be checked in the frame. Since

the destination address is checked by the address filtering function, the pattern offset is always greater

than 12.

The byte mask is a 31-bit field that specifies whether or not each of the 31 contiguous bytes within

the frame, beginning in the pattern offset, should be checked. If bit j in the byte mask is set, the

detection logic checks byte offset +j in the frame. In order to load the wake-up frame filter, the host

must perform eight writes to the Host MAC Wake-up Frame Filter Register (HMAC_WUFF). T a ble 9.2

shows the wake-up frame filter register’s structure.

Note: The switch fabric must be configured to pass wake-up packets to the Host MAC for this function

to operate properly.

Note: When wake-up frame detection is enabled via the WUEN bit of the Host MAC Wake-up Control

and Status Register (HMAC_WUCSR), a broadcast wake-up frame will wake-up the device

despite the state of the Disable Broadcast Frames (BCAST) bit in the Host MAC Control

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Table 9.2 Wake-Up Frame Filter Register Structure

Filter 0 Byte Mask

Filter 1 Byte Mask

Filter 2 Byte Mask

Filter 3 Byte Mask

Reserved

Filter 3

Command

Reserved

Filter 2

Command

Reserved

Filter 1

Command

Reserved

Filter 0

Command

Filter 3 Offset

Filter 1 CRC-16

Filter 3 CRC-16

Filter 2 Offset

Filter 1Offset

Filter 0 Offset

Filter 0 CRC-16

Filter 2 CRC-16

The Filter i Byte Mask defines which incoming frame bytes Filter i will examine to determine whether

or not this is a wake-up frame. T a ble 9.3, describes the byte mask’s bit fields.

Table 9.3 Filter i Byte Mask Bit Definitions

FILTER I BYTE MASK DESCRIPTION

FIELD

DESCRIPTION

Must be zero (0)

30:0

Byte Mask: If bit j of the byte mask is set, the CRC machine processes byte number pattern - (offset

+ j) of the incoming frame. Otherwise, byte pattern - (offset + j) is ignored.

The Filter i command register controls Filter i operation. T a ble 9.4 shows the Filter i command register.

Table 9.4 Filter i Command Bit Definitions

FILTER i COMMANDS

FIELD

DESCRIPTION

Address Type: Defines the destination address type of the pattern. When bit is set, the pattern

applies only to multicast frames. When bit is cleared, the pattern applies only to unicast frames.

2:1

RESERVED

Enable Filter: When bit is set, Filter i is enabled, otherwise, Filter i is disabled.

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The Filter i Offset register defines the offset in the frame’s destination address field from which the

frames are examined by Filter i. T a ble 9.5 describes the Filter i Offset bit fields.

Table 9.5 Filter i Offset Bit Definitions

FILTER i OFFSET DESCRIPTION

DESCRIPTION

FIELD

7:0

Pattern Offset: The offset of the first byte in the frame on which CRC is checked for wake-up frame

recognition. The minimum value of this field must be 12 since there should be no CRC check for

the destination address and the source address fields. The Host MAC checks the first offset byte

of the frame for CRC and checks to determine whether the frame is a wake-up frame. Offset 0 is

the first byte of the incoming frame's destination address.

The Filter i CRC-16 register contains the CRC-16 result of the frame that should pass Filter i.

T a ble 9.6 describes the Filter i CRC-16 bit fields.

Table 9.6 Filter i CRC-16 Bit Definitions

FILTER i CRC-16 DESCRIPTION

FIELD

DESCRIPTION

15:0

Pattern CRC-16: This field contains the 16-bit CRC value from the pattern and the byte mask

programmed to the wake-up filter register function. This value is compared against the CRC

calculated on the incoming frame, and a match indicates the reception of a wakeup frame.

9.5.1

Magic Packet Detection

Setting the Magic Packet Enable bit (MPEN) in the Host MAC Wake-up Control and Status Register

(HMAC_WUCSR) places the Host MAC in the “Magic Packet” detection mode. In this mode, normal

data reception is disabled, and detection logic within the Host MAC examines received data for a Magic

Packet. The LAN9312 can be programmed to notify the host of the “Magic Packet” detection with the

assertion of the host interrupt (IRQ) or power management event signal (PME). Upon detection, the

Magic Packet Received bit (MPR) in the HMAC_WUCSR register is set. When the host clears the

MPEN bit, the Host MAC will resume normal receive operation. Please refer to Section 14.3.12, "Host

MAC Wake-up Control and Status Register (HMAC_WUCSR)," on page 284 for additional information

on this register.

In Magic Packet mode, the Host MAC constantly monitors each frame addressed to the node for a

specific Magic Packet pattern. Only packets matching the Host MAC address or broadcast address are

checked for the Magic Packet requirements. Once the address requirement has been met, the Host

MAC checks the received frame for the pattern 48’hFF_FF_FF_FF_FF_FF after the destination and

source address field. The Host MAC then looks in the frame for 16 repetitions of the Host MAC address

without any breaks or interruptions. In case of a break in the 16 address repetitions, the Host MAC

again scans for the 48'hFF_FF_FF_FF_FF_FF pattern in the incoming frame. The 16 repetitions may

be anywhere in the frame but must be preceded by the synchronization stream. The device will also

accept a multicast frame, as long as it detects the 16 duplications of the Host MAC address.

For example, if the Host MAC address is 00h 11h 22h 33h 44h 55h, then the MAC scans for the

following data sequence in an Ethernet frame:

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Destination Address Source Address ……………FF FF FF FF FF FF

00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55

…CRC

Note: The switch fabric must be configured to pass magic packets to the Host MAC for this function

to operate properly.

9.6

Host MAC Address

The Host MAC address is configured via the Host MAC Address Low Register (HMAC_ADDRL) and

Host MAC Address High Register (HMAC_ADDRH). These registers contain the 48-bit physical

address of the Host MAC. The contents of these registers may be loaded directly by the host, or

optionally, by the EEPROM Loader from EEPROM at power-on (if a programmed EEPROM is

detected). The MAC address value loaded by the EEPROM Loader into the Host MAC address

registers (for host packet unicast qualification), is also loaded into the Switch Fabric MAC address

registers (for pause packet / flow control): Switch Fabric MAC Address Low Register

(SWITCH_MAC_ADDRL) and Switch Fabric MAC Address High Register (SWITCH_MAC_ADDRH).

These two sets of registers are loaded simultaneously via the same EEPROM byte addresses.

T a ble 9.7 below illustrates the byte ordering of the HMAC_ADDRL/SWITCH_MAC_ADDRL and

HMAC_ADDRH/SWITCH_MAC_ADDRH registers with respect to the reception of the Ethernet

physical address. Also shown is the correlation between the EEPROM addresses and

HMAC_ADDRL/SWITCH_MAC_ADDRL and HMAC_ADDRH/SWITCH_MAC_ADDRH registers.

Table 9.7 EEPROM Byte Ordering and Register Correlation

EEPROM Address

Order of Reception on Ethernet

01h

02h

03h

04h

05h

06h

HMAC_ADDRL[7:0]

SWITCH_MAC_ADDRL[7:0]

1^st

HMAC_ADDRL[15:8]

SWITCH_MAC_ADDRL[15:8]

2^nd

3^rd

4^th

5^th

6^th

HMAC_ADDRL[23:16]

SWITCH_MAC_ADDRL[23:16]

HMAC_ADDRL[31:24]

SWITCH_MAC_ADDRL[31:24]

HMAC_ADDRH[7:0]

SWITCH_MAC_ADDRH[7:0]

HMAC_ADDRH[15:8]

SWITCH_MAC_ADDRH[15:8]

For example, if the desired Ethernet physical address is 12-34-56-78-9A-BC, the HMAC_ADDRL and

HMAC_ADDRH registers would be programmed as shown in Figure 9.2. The values required to

automatically load this configuration from the EEPROM are also shown.

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24 23

16 15

8 7

BCh

9Ah

06h

05h

04h

03h

02h

01h

00h

HMAC_ADDRH / SWITCH_MAC_ADDRH

31 24 23 16 15 8 7

BCh

9Ah

78h

56h

34h

12h

78h

56h

34h

12h

A5h

EEPROM

HMAC_ADDRL / SWITCH_MAC_ADDRL

Figure 9.2 Example EEPROM MAC Address Setup

Note: By convention, the right nibble of the left most byte of the Ethernet address (in this example,

the 2 of the 12h) is the most significant nibble and is transmitted/received first.

For more information on the EEPROM and EEPROM Loader, refer to Section 10.2, "I2C/Microwire

Master EEPROM Controller," on page 137.

9.7

FIFOs

The LAN9312 contains four host-accessible FIFOs (TX Status, RX Status, TX Data, and RX Data) and

two internal inaccessible Host MAC TX/RX MIL FIFO’s (TX MIL FIFO, RX MIL FIFO).

9.7.1

TX/RX FIFOs

The TX/RX Data and Status FIFOs store the incoming and outgoing address and data information,

acting as a conduit between the host bus interface (HBI) and the Host MAC. The sizes of these FIFOs

are configurable via the Hardware Configuration Register (HW_CFG) register to the ranges described

in T a ble 9.8. Refer to Section 9.7.3, "FIFO Memory Allocation Configuration" for additional information.

The the RX and TX FIFOs related register definitions can be found in section Section 14.2.2, "Host

MAC & FIFO’s".

The TX and RX Data FIFOs have the base address of 00h and 20h respectively. However, each FIFO

is also accessible at seven additional contiguous memory locations, as can be seen in Figure 14.1.

The Host may access the TX or RX Data FIFOs at any of these alias port locations, as they all function

identically and contain the same data. This alias port addressing is implemented to allow hosts to burst

through sequential addresses.

The TX and RX Status FIFOs can each be read from two register locations; the Status FIFO Port, and

the Status FIFO PEEK. The TX and RX Status FIFO Ports (48h and 40h respectively) will perform a

destructive read, popping the data from the TX or RX Status FIFO. The TX and RX Status FIFO PEEK

of the FIFOs.

Proper use of the The TX/RX Data and Status FIFOs, including the correct data formatting is described

in detail in Section 9.8, "TX Data Path Operation," on page 122 and Section 9.9, "RX Data Path

Operation," on page 132.

9.7.2

MIL FIFOs

The MAC Interface Layer (MIL), within the Host MAC, contains a 2KB transmit and a 128 Byte receive

FIFO which are separate from the TX and RX FIFOs. These MIL FIFOs are not directly accessible

from the HBI. The differentiation between the TX/RX FIFOs and the TX/RX MIL FIFOs is that once the

transmit or receive packets are in the MIL FIFOs, the host no longer can control or access the TX or

RX data. The MIL FIFOs are essentially the working buffers of the Host MAC logic. In the case of

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reception, the data must be moved into the RX FIFOs before the host can access the data. For TX

operations, the MIL operates in store-and-forward mode and will queue an entire frame before

beginning transmission.

As space in the TX MIL FIFO frees, data is moved into it from the TX Data FIFO. Depending on the

size of the frames to be transmitted, the Host MAC can hold up to two Ethernet frames. This is in

addition to any TX data that may be queued in the TX Data FIFO.

Conversely, as data is received, it is moved from the Host MAC to the RX MIL FIFO, and then into

the RX Data FIFO. When the RX Data FIFO fills up, data will continue to collect in the RX MIL FIFO.

If the RX MIL FIFO fills up and overruns, subsequent RX frames will be lost until room is made in the

RX Data FIFO. For each frame of data that is lost, the Host MAC RX Dropped Frames Counter

RX and TX MIL FIFO levels are not visible to the host processor and operate independent of the

TX/RX FIFOs. FIFO levels set for the TX/RX Data and Status FIFOs do not take into consideration the

MIL FIFOs.

9.7.3

FIFO Memory Allocation Configuration

TX and RX FIFO space is configurable through the Hardware Configuration Register (HW_CFG). The

user must select the FIFO allocation by setting the TX FIFO Size (TX_FIF_SZ) field in the Hardware

Configuration Register (HW_CFG). The TX_FIF_SZ field selects the total allocation for the TX data

path, including the TX Status FIFO size. The TX Status FIFO size is fixed at 512 Bytes (128 TX Status

DWORDs). The TX Status FIFO length is subtracted from the total TX FIFO size with the remainder

being the TX Data FIFO Size. The minimum size of the TX FIFOs is 2KB (TX Data and TX Status

FIFOs combined). Note that TX Data FIFO space includes both commands and payload data.

RX FIFO Size is the remainder of the unallocated FIFO space (16384 bytes – TX FIFO Size). The RX

Status FIFO size is always equal to 1/16 of the RX FIFO size. The RX Status FIFO length is subtracted

from the total RX FIFO size with the remainder being the RX Data FIFO Size.

For example, if TX_FIF_SZ = 6 then:

Total TX FIFO Size = 6144 Bytes (6KB)

TX Status FIFO Size = 512 Bytes (Fixed)

TX Data FIFO Size = 6144 – 512 = 5632 Bytes

RX FIFO Size = 16384 – 6144 = 10240 Bytes (10KB)

RX Status FIFO Size = 10240 / 16 = 640 Bytes (160 RX Status DWORDs)

RX Data FIFO Size = 10240 – 640 = 9600 Bytes

T a ble 9.8 contains an overview of the configurable TX/RX FIFO sizes and defaults. T a ble 9.9 shows

every valid setting for the TX_FIF_SZ field and the resulting FIFO sizes. Note that settings not shown

in this table are reserved and should not be used.

Note: The RX Data FIFO is considered full 4 DWORDs before the length that is specified in the

HW_CFG register.

Table 9.8 TX/RX FIFO Configurable Sizes

FIFO

SIZE RANGE

DEFAULT

TX Status

RX Status

TX Data

512

704

128-892

1536-13824

1920-13440

4608

10560

RX Data

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Table 9.9 Valid TX/RX FIFO Allocations

TX DATA FIFO

SIZE (BYTES)

TX STATUS FIFO

SIZE (BYTES)

RX DATA FIFO

SIZE (BYTES)

RX STATUS FIFO

SIZE (BYTES)

TX_FIF_SZ

1536

2560

3584

4608

5632

6656

7680

8704

9728

10752

11776

12800

13824

512

13440

12480

11520

10560

9600

8640

7680

6720

5760

4800

3840

2880

1920

896

832

768

704

640

576

512

448

384

320

256

192

128

9.8

TX Data Path Operation

Data is queued for transmission by writing it into the TX Data FIFO. Each packet to be transmitted

may be divided among multiple buffers. Each buffer starts with a two DWORD TX command (TX

command ‘A’ and TX command ‘B’). The TX command instructs the LAN9312 on the handling of the

associated buffer. Packet boundaries are delineated using control bits within the TX command.

The host provides a 16-bit Packet Tag field in the TX command. The Packet Tag value is appended

to the corresponding TX status DWORD. All Packet Tag fields must have the same value for all buffers

in a given packet. If tags differ between buffers in the same packet the TXE error will be asserted. Any

value may be chosen for a Packet Tag as long as all tags in the same Packet are identical. Packet

Tags also provide a method of synchronization between transmitted packets and their associated

status. Software can use unique Packet Tags to assist with validating matching status completions.

Note: The use of Packet Tags is not required by the hardware. This field can be used by the LAN

software driver for any application. Packet Tags is only one application example.

The Packet Length field in the TX command specifies the number of bytes in the associated packet.

All Packet Length fields must have the same value for all buffers in a given packet. Hardware

compares the Packet Length field and the actual amount of data received by the Ethernet controller.

If the actual packet length count does not match the Packet Length field as defined in the TX

command, the Transmitter Error (TXE) flag is asserted.

The LAN9312 can be programmed to start payload transmission of a buffer on a byte boundary by

setting the “Data Start Offset” field in the TX command. The “Data Start Offset” field points to the actual

start of the payload data within the first 8 DWORDs of the buffer. Data before the “Data Start Offset”

pointer will be ignored. When a packet is split into multiple buffers, each successive buffer may begin

on any arbitrary byte.

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The LAN9312 can be programmed to strip padding from the end of a transmit packet in the event that

the end of the packet does not align with the host burst boundary. This feature is necessary when the

LAN9312 is operating in a system that always performs multi-word bursts. In such cases the LAN9312

must guarantee that it can accept data in multiples of the Burst length regardless of the actual packet

length. When configured to do so, the LAN9312 will accept extra data at the end of the packet and

will remove the extra padding before transmitting the packet. The LAN9312 automatically removes data

up to the boundary specified in the Buffer End Alignment field specified in each TX command.

The host can instruct the LAN9312 to issue an interrupt when the buffer has been fully loaded into the

TX FIFO contained in the LAN9312 and transmitted. This feature is enabled through the TX command

‘Interrupt on Completion’ field.

Upon completion of transmission, irrespective of success or failure, the status of the transmission is

written to the TX Status FIFO. TX status is available to the host and may be read using PIO operations.

An interrupt can be optionally enabled by the host to indicate the availability of a programmable

number TX status DWORDS.

Before writing the TX command and payload data to the TX FIFO, the host must check the available

TX FIFO space by performing a PIO read of the TX FIFO Information Register (TX_FIFO_INF). The

host must ensure that it does not overfill the TX FIFO or the TX Error (TXE) flag will be asserted.

The host proceeds to write the TX command by first writing TX command ‘A’, then TX command ‘B’.

After writing the command, the host can then move the payload data into the TX FIFO. TX status

DWORDs are stored in the TX Status FIFO to be read by the host at a later time upon completion of

the data transmission onto the wire.

Figure 9.3 Simplified Host TX Flow Diagram

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9.8.1

TX Buffer Format

TX buffers exist in the host’s memory in a given format. The host writes a TX command word into the

TX data buffer before moving the Ethernet packet data. The TX command A and command B are 32-

bit values that are used by the LAN9312 in the handling and processing of the associated Ethernet

packet data buffer. Buffer alignment, segmentation and other packet processing parameters are

included in the command structure. The buffer format is illustrated in Figure 9.4.

Host Write

Order

TX Command 'A'

TX Command 'B'

1st

2nd

3rd

Optional offset DWORD0

Optional offset DWORDn

Offset + Data DWORD0

Last Data & PAD

Optional Pad DWORD0

Last

Optional Pad DWORDn

Figure 9.4 TX Buffer Format

Figure 9.4 shows the TX Buffer as it is written into the LAN9312. It should be noted that not all of the

data shown in this diagram is actually stored in the TX Data FIFO. This must be taken into account

when calculating the actual TX Data FIFO usage. Please refer to Section 9.8.5, "Calculating Actual TX

Data FIFO Usage" for a detailed explanation on calculating the actual TX Data FIFO usage.

9.8.2

TX Command Format

The TX command instructs the TX FIFO controller on handling the subsequent buffer. The command

precedes the data to be transmitted. The TX command is divided into two, 32-bit words; TX command

‘A’ and TX command ‘B’.

There is a 16-bit Packet Tag in the TX command ‘B’ command word. Packet Tags may, if host software

desires, be unique for each packet (i.e., an incrementing count). The value of the tag will be returned

in the TX status word for the associated packet. The Packet tag can be used by host software to

uniquely identify each status word as it is returned to the host.

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Both TX command ‘A’ and TX command ‘B’ are required for each buffer in a given packet. TX

command ‘B’ must be identical for every buffer in a given packet. If the TX command ‘B’ words do not

match, the Ethernet controller will assert the Transmitter Error (TXE) flag.

9.8.2.1

TX Command ‘A’

Table 9.10 TX Command 'A' Format

DESCRIPTION

BITS

Interrupt on Completion (IOC). When set, the TX_IOC bit will be asserted in the Interrupt Status

30:26

25:24

Reserved. These bits are reserved. Always write zeros to this field to guarantee future compatibility.

Buffer End Alignment. This field specifies the alignment that must be maintained on the last data

transfer of a buffer. The host will add extra DWORDs of data up to the alignment specified in the

table below. The LAN9312 will remove the extra DWORDs. This mechanism can be used to maintain

cache line alignment on host processors.

[25]

[24]

End Alignment

4-byte alignment

16-byte alignment

32-byte alignment

Reserved

23:21

20:16

Reserved. These bits are reserved. Always write zeros to this field to guarantee future compatibility

Data Start Offset (bytes). This field specifies the offset of the first byte of TX data. The offset value

can be anywhere from 0 bytes to a 31 byte offset.

15:14

Reserved. These bits are reserved. Always write zeros to this field to guarantee future compatibility

First Segment (FS). When set, this bit indicates that the associated buffer is the first segment of the

packet.

Last Segment. When set, this bit indicates that the associated buffer is the last segment of the

packet

Reserved. These bits are reserved. Always write zeros to this field to guarantee future compatibility.

10:0

Buffer Size (bytes). This field indicates the number of bytes contained in the buffer following this

command. This value, along with the Buffer End Alignment field, is read and checked by the

LAN9312 and used to determine how many extra DWORDs were added to the end of the Buffer. A

running count is also maintained in the LAN9312 of the cumulative buffer sizes for a given packet.

This cumulative value is compared against the Packet Length field in the TX command ‘B’ word and

if they do not correlate, the TXE flag is set.

Note:

The buffer size specified does not include the buffer end alignment padding or data start

offset added to a buffer.

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9.8.2.2

TX Command ‘B’

Table 9.11 TX Command 'B' Format

DESCRIPTION

BITS

31:16

Packet Tag. The host should write a unique packet identifier to this field. This identifier is added to

the corresponding TX status word and can be used by the host to correlate TX status words with

their corresponding packets.

Note:

The use of packet tags is not required by the hardware. This field can be used by the LAN

software driver for any application. Packet Tags is one application example.

15:14

Reserved. These bits are reserved. Always write zeros to this field to guarantee future compatibility.

Add CRC Disable. When set, the automatic addition of the CRC is disabled.

Disable Ethernet Frame Padding. When set, this bit prevents the automatic addition of padding to

an Ethernet frame of less than 64 bytes. The CRC field is also added despite the state of the Add

CRC Disable field.

Reserved. These bits are reserved. Always write zeros to this field to guarantee future compatibility.

10:0

Packet Length (bytes). This field indicates the total number of bytes in the current packet. This

length does not include the offset or padding. If the Packet Length field does not match the actual

number of bytes in the packet the Transmitter Error (TXE) flag will be set.

9.8.3

TX Data Format

The TX data section begins at the third DWORD in the TX buffer (after TX command ‘A’ and TX

command ‘B’). The location of the first byte of valid buffer data to be transmitted is specified in the

“Data Start Offset” field of the TX command ‘A’ word. T a ble 9.12, "TX DATA Start Offset", shows the

correlation between the setting of the LSB’s in the “Data Start Offset” field and the byte location of the

first valid data byte. Additionally, transmit buffer data can be offset by up to 7 additional DWORDS as

indicated by the upper three MSB’s (5:2) in the “Data Start Offset” field.

Table 9.12 TX DATA Start Offset

Data Start Offset [1:0]:

First TX Data Byte:

D[31:24]

D[23:16]

D[15:8]

D[7:0]

TX data is contiguous until the end of the buffer. The buffer may end on a byte boundary. Unused

bytes at the end of the packet will not be sent to the Host MAC Interface Layer for transmission.

The Buffer End Alignment field in TX command ‘A’ specifies the alignment that must be maintained for

the associated buffer. End alignment may be specified as 4-, 16-, or 32-byte. The host processor is

responsible for adding the additional data to the end of the buffer. The hardware will automatically

remove this extra data.

9.8.3.1

TX Buffer Fragmentation Rules

Transmit buffers must adhere to the following rules:

„

Each buffer can start and end on any arbitrary byte alignment

The first buffer of any transmit packet can be any length

Middle buffers (i.e., those with First Segment = Last Segment = 0) must be greater than, or equal

to 4 bytes in length

„

The final buffer of any transmit packet can be any length

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The MIL operates in store-and-forward mode and has specific rules with respect to fragmented

packets. The total space consumed in the TX MIL FIFO must be limited to no more than 2KB - 3

DWORDs (2,036 bytes total). Any transmit packet that is so highly fragmented that it takes more space

than this must be un-fragmented (by copying to a driver-supplied buffer) before the transmit packet

can be sent to the LAN9312.

One approach to determine whether a packet is too fragmented is to calculate the actual amount of

space that it will consume, and check it against 2,036 bytes. Another approach is to check the number

of buffers against a worst-case limit of 86 (see explanation below).

9.8.3.2

Calculating Worst-Case TX MIL FIFO Usage

The actual space consumed by a buffer in the TX MIL FIFO consists only of any partial DWORD offsets

in the first/last DWORD of the buffer, plus all of the whole DWORDs in between. Any whole DWORD

offsets and/or alignments are stripped off before the buffer is loaded into the TX Data FIFO, and TX

command words are stripped off before the buffer is written to the TX MIL FIFO, so none of those

DWORDs count as space consumed. The worst-case overhead for a TX buffer is 6 bytes, which

assumes that it started on the high byte of a DWORD and ended on the low byte of a DWORD. A TX

packet consisting of 86 such fragments would have an overhead of 516 bytes (6 * 86) which, when

added to a 1514-byte max-size transmit packet (1516 bytes, rounded up to the next whole DWORD),

would give a total space consumption of 2,032 bytes, leaving 4 bytes to spare; this is the basis for the

"86 fragment" rule mentioned above. For more information on the MIL FIFO’s refer to Section 9.7.2,

"MIL FIFOs," on page 120.

9.8.4

TX Status Format

TX status is passed to the host CPU through a separate FIFO mechanism. A status word is returned

for each packet transmitted. Data transmission is suspended if the TX Status FIFO becomes full. Data

transmission will resume when the host reads the TX status and there is room in the FIFO for more

“TX Status” data.

The host can optionally choose to not read the TX status. The TX status can be ignored by setting the

“TX Status Discard Allow Overrun Enable” (TXSAO) bit in the Transmit Configuration Register

(TX_CFG). If this option is chosen TX status will not be written to the FIFO. Setting this bit high allows

the transmitter to continue operation with a full TX Status FIFO. In this mode the status information is

still available in the TX Status FIFO, and TX status interrupts still function. In the case of an overrun,

the TXSUSED counter will stay at zero and no further TX status will be written to the TX Status FIFO

until the host frees space by reading TX status. If TXSAO is enabled, a TXE error will not be generated

if the TX Status FIFO overruns. In this mode the host is responsible for re-synchronizing TX status in

the case of an overrun.

Note: Though the Host MAC is communicating locally with the switch fabric MAC, the events

described in the TX Status word may still occur.

BITS

DESCRIPTION

31:16

Packet TAG. Unique identifier written by the host into the Packet Tag field of the TX command ‘B’

word. This field can be used by the host to correlate TX status words with the associated TX packets.

Error Status (ES). When set, this bit indicates that the Ethernet controller has reported an error. This

bit is the logical OR of bits 11, 10, 9, 8, 2, 1 in this status word.

14:12

Reserved. These bits are reserved. Always write zeros to this field to guarantee future compatibility.

Loss of Carrier. When set, this bit indicates the loss of carrier during transmission.

No Carrier. When set, this bit indicates that the carrier signal from the transceiver was not present

during transmission.

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BITS

DESCRIPTION

Late Collision. When set, indicates that the packet transmission was aborted after the collision

window of 64 bytes.

Excessive Collisions. When set, this bit indicates that the transmission was aborted after 16

collisions while attempting to transmit the current packet.

Reserved. This bit is reserved. Always write zeros to this field to guarantee future compatibility.

6:3

Collision Count. This counter indicates the number of collisions that occurred before the packet was

transmitted. It is not valid when excessive collisions (bit 8) is also set.

Excessive Deferral. If the deferred bit is set in the control register, the setting of the excessive

deferral bit indicates that the transmission has ended because of a deferral of over 24288 bit times

during transmission.

Reserved. This bit is reserved. Always write zeros to this field to guarantee future compatibility

Deferred. When set, this bit indicates that the current packet transmission was deferred.

9.8.5

Calculating Actual TX Data FIFO Usage

The following rules are used to calculate the actual TX Data FIFO space consumed by a TX Packet:

„

TX command 'A' is stored in the TX Data FIFO for every TX buffer

TX command 'B' is written into the TX Data FIFO when the First Segment (FS) bit is set in TX

command 'A'

„

Any DWORD-long data added as part of the “Data Start Offset” is removed from each buffer before

the data is written to the TX Data FIFO. Any data that is less than 1 DWORD is passed to the TX

Data FIFO.

„

Payload from each buffer within a Packet is written into the TX Data FIFO.

Any DWORD-long data added as part of the End Padding is removed from each buffer before the

data is written to the TX Data FIFO. Any end padding that is less than 1 DWORD is passed to the

TX Data FIFO

9.8.6

Transmit Examples

9.8.6.1

TX Example 1

In this example a single, 111-Byte Ethernet packet will be transmitted. This packet is divided into three

buffers. The three buffers are as follows:

Buffer 0:

„

7-Byte “Data Start Offset”

79-Bytes of payload data

16-Byte “Buffer End Alignment”

Buffer 1:

„

0-Byte “Data Start Offset”

15-Bytes of payload data

16-Byte “Buffer End Alignment”

Buffer 2:

„

10-Byte “Data Start Offset”

17-Bytes of payload data

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„

16-Byte “Buffer End Alignment”

Figure 9.5 illustrates the TX command structure for this example, and also shows how data is passed

to the TX Data FIFO.

Data Written to the

Memory Mapped

TX Data FIFO Port

TX Command 'A'

Buffer End Alignment = 1

Data Start Offset = 7

First Segment = 1

Last Segment = 0

Buffer Size = 79

TX Command 'A'

TX Command 'B'

Data Passed to the

TX Data FIFO

7-Byte Data Start Offset

TX Command 'A'

TX Command 'B'

Packet Length = 111

79-Byte Payload

Pad DWORD 1

79-Byte Payload

10-Byte

End Padding

TX Command 'A'

15-Byte Payload

TX Command 'A'

Buffer End Alignment = 1

Data Start Offset = 0

First Segment = 0

Last Segment = 0

Buffer Size = 15

TX Command 'A'

TX Command 'B'

TX Command 'A'

17-Byte Payload

15-Byte Payload

TX Command 'B'

Packet Length = 111

10-Byte

End Offset Padding

TX Command 'A'

Buffer End Alignment = 1

Data Start Offset = 10

First Segment = 0

Last Segment = 1

Buffer Size = 17

TX Command 'A'

TX Command 'B'

10-Byte

Data Start Offset

NOTE: Extra bytes

between buffers are

not transmitted

TX Command 'B'

Packet Length = 111

17-Byte Payload Data

5-Byte End Padding

Figure 9.5 TX Example 1

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9.8.6.2

TX Example 2

In this example, a single 183-Byte Ethernet packet will be transmitted. This packet is in a single buffer

as follows:

„

2-Byte “Data Start Offset”

183-Bytes of payload data

4-Byte “Buffer End Alignment”

Figure 9.6 illustrates the TX command structure for this example, and also shows how data is passed

to the TX Data FIFO. Note that the packet resides in a single TX Buffer, therefore both the FS and LS

bits are set in TX command ‘A’.

Data Written to the

Data Passed to the

TX Data FIFO

Memory Mapped

TX Data FIFO Port

TX Command 'A'

Buffer End Alignment = 0

Data Start Offset = 6

First Segment = 1

Last Segment = 1

Buffer Size =183

TX Command 'A'

TX Command 'B'

TX Command 'A'

TX Command 'B'

6-Byte Data Start Offset

TX Command 'B'

Packet Length = 183

183-Byte Payload Data

3B End Padding

NOTE: Extra bytes between buffers

are not transmitted

Figure 9.6 TX Example 2

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9.8.7

Transmitter Errors

If the Transmitter Error (TXE) flag is asserted for any reason, the transmitter will continue operation.

TX Error (TXE) will be asserted under the following conditions:

„

If the actual packet length count does not match the Packet Length field as defined in the TX

command.

„

Both TX command ‘A’ and TX command ‘B’ are required for each buffer in a given packet. TX

command ‘B’ must be identical for every buffer in a given packet. If the TX command ‘B’ words do

not match, the Ethernet controller will assert the Transmitter Error (TXE) flag.

„

Host overrun of the TX Data FIFO.

Overrun of the TX Status FIFO (unless TXSAO is enabled)

9.8.8

Stopping and Starting the Transmitter

To halt the transmitter, the host must set the STOP_TX bit in the Transmit Configuration Register

(TX_CFG). The transmitter will finish sending the current frame (if there is a frame transmission in

progress). When the transmitter has received the TX status for this frame, it will clear the STOP_TX

and TX_ON bits, and will pulse the TXSTOP_INT in the Interrupt Status Register (INT_STS).

Once stopped, the host can optionally clear the TX Status and TX Data FIFOs. The host must re-

enable the transmitter by setting the TX_ON bit. If the there are frames pending in the TX Data FIFO

(i.e., TX Data FIFO was not purged), the transmission will resume with this data.

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9.9

RX Data Path Operation

When an Ethernet Packet is received, the Host MAC Interface Layer (MIL) first begins to transfer the

RX data. This data is loaded into the RX Data FIFO. The RX Data FIFO pointers are updated as data

is written into the FIFO.

The last transfer from the MIL is the RX status word. The LAN9312 implements a separate FIFO for

the RX status words. The total available RX data and status queued in the RX FIFO can be read from

the RX FIFO Information Register (RX_FIFO_INF). The host may read any number of available RX

status words before reading the RX Data FIFO.

The host must use caution when reading the RX data and status. The host must never read more data

than what is available in the FIFO’s. If this is attempted an underrun condition will occur. If this error

occurs, the Ethernet controller will assert the Receiver Error (RXE) interrupt. If an underrun condition

occurs, a soft reset is required to regain host synchronization.

A configurable beginning offset is supported in the LAN9312. The RX data Offset field in the Receive

Configuration Register (RX_CFG) controls the number of bytes that the beginning of the RX data buffer

is shifted. The host can set an offset from 0-31 bytes. The offset may be changed in between RX

packets, but it must not be changed during an RX packet read.

The LAN9312 can be programmed to add padding at the end of a receive packet in the event that the

end of the packet does not align with the host burst boundary. This feature is necessary when the

LAN9312 is operating in a system that always performs multi-DWORD bursts. In such cases the

LAN9312 must guarantee that it can transfer data in multiples of the Burst length regardless of the

actual packet length. When configured to do so, the LAN9312 will add extra data at the end of the

packet to allow the host to perform the necessary number of reads so that the Burst length is not cut

short. Once a packet has been padded by the H/W, it is the responsibility of the host to interrogate the

packet length field in the RX status and determine how much padding to discard at the end of the

packet.

It is possible to read multiple packets out of the RX Data FIFO in one continuous stream. It should be

noted that the programmed Offset and Padding will be added to each individual packet in the stream,

since packet boundaries are maintained.

9.9.1

RX Slave PIO Operation

Using PIO mode, the host can either implement a polling or interrupt scheme to empty the received

packet out of the RX Data FIFO. The host will remain in the idle state until it receives an indication

(interrupt or polling) that data is available in the RX Data FIFO. The host will then read the RX Status

FIFO to get the packet status, which will contain the packet length and any other status information.

The host should perform the proper number of reads, as indicated by the packet length plus the start

offset and the amount of optional padding added to the end of the frame, from the RX Data FIFO. A

typical host receive routine using interrupts can be seen in Figure 9.7, while a typical host receive

routine using polling can be seen in Figure 9.8.

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init

Idle

RX Interrupt

Read RX

Status

DWORD

Not Last Packet

Last Packet

Read RX

Packet

Figure 9.7 Host Receive Routine Using Interrupts

init

Read

RX_FIFO_INF

Valid Status DWORD

Read RX

Status

DWORD

Not Last Packet

Last Packet

Read RX

Packet

Figure 9.8 Host Receive Routine Using Polling

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9.9.1.1

Receive Data FIFO Fast Forward

The RX data path implements an automatic data discard function. Using the RX Data FIFO Fast

Forward bit (RX_FFWD) in the Receive Datapath Control Register (RX_DP_CTRL), the host can

instruct the LAN9312 to skip the packet at the head of the RX Data FIFO. The RX Data FIFO pointers

are automatically incremented to the beginning of the next RX packet.

When performing a fast-forward, there must be at least 4 DWORDs of data in the RX Data FIFO for

the packet being discarded. For cases with less than 4 DWORDs, do not use RX_FFWD. In this case

data must be read from the RX Data FIFO and discarded using standard PIO read operations.

After initiating a fast-forward operation, do not perform any reads of the RX Data FIFO until the

RX_FFWD bit is cleared. Other resources can be accessed during this time (i.e., any registers and/or

the other three FIFO’s). Also note that the RX_FFWD will only fast-forward the RX Data FIFO, not the

RX Status FIFO. After an RX fast-forward operation the RX status must still be read from the RX Status

FIFO.

The receiver does not have to be stopped to perform a fast-forward operation.

9.9.1.2

Force Receiver Discard (Receiver Dump)

In addition to the Receive data Fast Forward feature, LAN9312 also implements a receiver "dump"

feature. This feature allows the host processor to flush the entire contents of the RX Data and RX

Status FIFOs. When activated, the read and write pointers for the RX Data and Status FIFO’s will be

returned to their reset state. To perform a receiver dump, the LAN9312 receiver must be halted. Once

the receiver stop completion is confirmed, the RX_DUMP bit can be set in the Receive Configuration

on stopping the receiver, please refer to Section 9.9.4, "Stopping and Starting the Receiver". For more

information on the RX_DUMP bit, please refer to Section 14.2.2.1, "Receive Configuration Register

(RX_CFG)," on page 180.

9.9.2

RX Packet Format

The RX status words can be read from the RX Status FIFO port, while the RX data packets can be

read from the RX Data FIFO. RX data packets are formatted in a specific manner before the host can

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read them as shown in Figure 9.9. It is assumed that the host has previously read the associated

status word from the RX Status FIFO, to ascertain the data size and any error conditions.

Host Read

Order

Optional offset DWORD0

1st

2nd

Optional offset DWORDn

ofs + First Data DWORD

Last Data DWORD

Optional Pad DWORD0

Optional Pad DWORDn

Last

Figure 9.9 RX Packet Format

9.9.3

RX Status Format

Note: Though the Host MAC is communicating locally with the switch fabric MAC, the events

described in the RX Status word may still occur.

BITS

DESCRIPTION

Reserved. This bit is reserved. Reads 0.

Filtering Fail. When set, this bit indicates that the associated frame failed the address recognizing

filtering.

29:16

Packet Length. The size, in bytes, of the corresponding received frame.

Error Status (ES). When set this bit indicates that the Host MAC Interface Layer (MIL) has reported

an error. This bit is the Internal logical “or” of bits 11,7,6 and 1.

Reserved. These bits are reserved. Reads 0.

Broadcast Frame. When set, this bit indicates that the received frame has a Broadcast address.

Length Error (LE). When set, this bit indicates that the actual length does not match with the

length/type field of the received frame.

Runt Frame. When set, this bit indicates that frame was prematurely terminated before the collision

window (64 bytes). Runt frames are passed on to the host only if the Pass Bad Frames bit (PASSBAD)

of the Host MAC Control Register (HMAC_CR) is set.

Multicast Frame. When set, this bit indicates that the received frame has a Multicast address.

9:8

Reserved. These bits are reserved. Reads 0.

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BITS

DESCRIPTION

Frame Too Long. When set, this bit indicates that the frame length exceeds the maximum Ethernet

specification of 1518 bytes. This is only a frame too long indication and will not cause the frame

reception to be truncated.

Collision Seen. When set, this bit indicates that the frame has seen a collision after the collision

window. This indicates that a late collision has occurred.

Frame Type. When set, this bit indicates that the frame is an Ethernet-type frame (Length/Type field

in the frame is greater than 1500). When reset, it indicates the incoming frame was an 802.3 type

frame. This bit is not set for Runt frames less than 14 bytes.

Receive Watchdog time-out. When set, this bit indicates that the incoming frame is greater than

2048 bytes through 2560 bytes, therefore expiring the Receive Watchdog Timer.

MII Error. When set, this bit indicates that a receive error was detected during frame reception.

Dribbling Bit. When set, this bit indicates that the frame contained a non-integer multiple of 8 bits.

This error is reported only if the number of dribbling bits in the last byte is at least 3 in the 10 Mbps

operating mode. This bit will not be set when the collision seen bit[6] is set. If set and the CRC error

bit is [1] reset, then the packet is considered to be valid.

CRC Error. When set, this bit indicates that a CRC error was detected. This bit is also set when the

RX_ER pin is asserted during the reception of a frame even though the CRC may be correct. This bit

is not valid if the received frame is a Runt frame, or a late collision was detected or when the

Watchdog Time-out occurs.

Reserved. These bits are reserved. Reads 0

9.9.4

Stopping and Starting the Receiver

To stop the receiver, the host must clear the RXEN bit in the Host MAC Control Register (HMAC_CR).

When the receiver is halted, the RXSTOP_INT will be pulsed and reflected in the Interrupt Status

The host must re-enable the receiver by setting the RXEN bit.

9.9.5

Receiver Errors

If the Receiver Error (RXE) flag is asserted in the Interrupt Status Register (INT_STS) for any reason,

the receiver will continue operation. RX Error (RXE) will be asserted under the following conditions:

„

A host underrun of RX Data FIFO

A host underrun of the RX Status FIFO

An overrun of the RX Status FIFO

It is the duty of the host to identify and resolve any error conditions.

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Chapter 10 Serial Management

10.1

Functional Overview

This chapter details the LAN9312 serial management functionality of the I²C/Microwire EEPROM

Controller and the supporting EEPROM Loader.

The I²C/Microwire EEPROM controller is an I²C/Microwire master module which interfaces an optional

external EEPROM with the system register bus and the EEPROM Loader. Multiple types

(I²C/Microwire) and sizes of external EEPROMs are supported. Configuration of the EEPROM type

and size are accomplished via the eeprom_type_strap and eeprom_size_strap[1:0] configuration straps

respectively. Various commands are supported for each EEPROM type, allowing for the storage and

retrieval of static data. The I²C interface conforms to the Philips I C-Bus Specification.

The EEPROM Loader provides the automatic loading of configuration settings from the EEPROM into

the LAN9312 at reset. The EEPROM Loader module interfaces to the EEPROM Controller, Ethernet

PHYs, and the system CSRs.

10.2

I²C/Microwire Master EEPROM Controller

Based on the configuration strap eeprom_type_strap, the I²C/Microwire EEPROM controller supports

either Microwire or I²C compatible EEPROMs. The I²C/Microwire serial management pins functionality

and characteristics differ dependant on the selected EEPROM type as summarized in T a ble 10.1.

Table 10.1 I C/Microwire Master Serial Management Pins Characteristics

EEPROM

TYPE/MODE

EE_SDA/EEDI PIN

EE_SDA

EEDO PIN

NOT USED

EECS PIN

NOT USED

EE_SCL/EECLK PIN

EE_SCL

I²C Master

EEPROM

Mode

Input enabled

(to I²C master)

Input enabled

(used for straps)

Input enabled

(used for straps)

Input enabled

(to I²C master and

used for straps)

Open-drain output

(from I²C master)

Output enabled

(driven low)

Output enabled

(driven low)

eeprom_type_strap

= 1

Open-drain output

(from I²C master)

Pull-down disabled

Microwire

Master

EEPROM

Mode

EEDI

EEDO

EECS

EECLK

Input enabled

(to Microwire master) (used for straps)

Input enabled

(used for straps)

Input enabled

(used for straps)

Output disabled

Output enabled (from

Microwire master)

Output enabled (from

Microwire master)

Output enabled (from

Microwire master)

eeprom_type_strap

= 0

Pull-down enabled

Note: When the EEPROM Loader is running, it has exclusive use of the I²C/Microwire EEPROM

controller. Refer to Section 10.2.4, "EEPROM Loader" for more information.

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10.2.1

EEPROM Controller Operation

I²C and Microwire master EEPROM operations are performed using the EEPROM Command Register

(E2P_CMD) and EEPROM Data Register (E2P_DATA).

In Microwire EEPROM mode, the following operations are supported:

„

ERASE (Erase Location)

ERAL (Erase All)

EWDS (Erase/Write Disable)

EWEN (Erase/Write Enable)

READ (Read Location)

WRITE (Write Location)

WRAL (Write All)

RELOAD (EEPROM Loader Reload - See Section 10.2.4, "EEPROM Loader")

Note: In I²C EEPROM mode, only a sub-set of the above commands (READ, WRITE, and RELOAD)

are supported.

Note: The EEPROM Loader uses the READ command only.

The supported commands of each mode are detailed in Section 14.2.4.1, "EEPROM Command

Microwire) are explained in Section 10.2.2, "I2C EEPROM" and Section 10.2.3, "Microwire EEPROM"

respectively.

When issuing a WRITE, or WRAL command, the desired data must first be written into the EEPROM

Data Register (E2P_DATA). The WRITE or WRAL command may then be issued by setting the

EPC_COMMAND field of the EEPROM Command Register (E2P_CMD) to the desired command

value. If the operation is a WRITE, the EPC_ADDRESS field in the EEPROM Command Register

(E2P_CMD) must also be set to the desired location. The command is executed when the EPC_BUSY

bit of the EEPROM Command Register (E2P_CMD) is set. The completion of the operation is indicated

when the EPC_BUSY bit is cleared.

When issuing a READ command, the EPC_COMMAND and EPC_ADDRESS fields of the EEPROM

Command Register (E2P_CMD) must be configured with the desired command value and the read

address, respectively. The READ command is executed by setting the EPC_BUSY bit of the EEPROM

Command Register (E2P_CMD). The completion of the operation is indicated when the EPC_BUSY

bit is cleared, at which time the data from the EEPROM may be read from the EEPROM Data Register

(E2P_DATA).

Other EEPROM operations (EWDS, EWEN, ERASE, ERAL, RELOAD) are performed by writing the

appropriate command into the EPC_COMMAND field of the EEPROM Command Register

(E2P_CMD). The command is executed by setting the EPC_BUSY bit of the EEPROM Command

modifying the EEPROM Command Register (E2P_CMD).

Note: The EEPROM device powers-up in the erase/write disabled state. To modify the contents of

the EEPROM, the EWEN command must first be issued.

If an operation is attempted and the EEPROM device does not respond within 30mS, the LAN9312

will time-out, and the EPC_TIMEOUT bit of the EEPROM Command Register (E2P_CMD) will be set.

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Figure 10.1 illustrates the process required to perform an EEPROM read or write operation.

EEPROM Write

EEPROM Read

Idle

Write

E2P_DATA

E2P_CMD

Write

Read

E2P_CMD

EPC_BUSY = 0

Read

E2P_CMD

E2P_DATA

EPC_BUSY = 0

Figure 10.1 EEPROM Access Flow Diagram

10.2.2

I C EEPROM

The I²C master implements a low level serial interface (start and stop condition generation, data bit

transmission and reception, acknowledge generation and reception) for connection to I²C EEPROMs,

and consists of a data wire (EE_SDA) and a serial clock (EE_SCL). The serial clock is driven by the

master, while the data wire is bi-directional. Both signals are open-drain and require external pull-up

resistors.

The serial clock is also used as an input as it can be held low by the slave device in order to wait-

state the data cycle. Once the slave has data available or is ready to receive, it will release the clock.

Assuming the masters clock low time is also expired, the clock will rise and the cycle will continue. In

the event that the slave device holds the clock low for more than 30mS, the current command

sequence is aborted and the EPC_TIMEOUT bit in the EEPROM Command Register (E2P_CMD) is

set. Both the clock and data signals have Schmitt trigger inputs and digital input filters. The digital filters

reject pulses that are less than 100nS.

Note: Since the I²C master is designed to access EEPROM only, multi-master arbitration is not

supported.

Based on the configuration strap eeprom_size_strap, various sized I²C EEPROMs are supported. The

varying size ranges are supported by additional bits in the address field (EPC_ADDRESS) of the

EEPROM Command Register (E2P_CMD). Within each size range, the largest EEPROM uses all the

address bits, while the smaller EEPROMs treat the upper address bits as don’t cares. The EEPROM

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controller drives all the address bits as requested regardless of the actual size of the EEPROM. The

supported size ranges for I²C operation are shown in T a ble 10.2.

Table 10.2 I C EEPROM Size Ranges

eeprom_size_strap[0]

# OF ADDRESS BYTES

EEPROM SIZE

EEPROM TYPES

1 (Note 10.1)

16 x 8 through 2048 x 8

24xx00, 24xx01, 24xx02,

24xx04, 24xx08, 24xx16

4096 x 8 through 65536 x 8 24xx32, 24xx64, 24xx128,

24xx256, 24xx512

Note 10.1 Bits in the control byte are used as the upper address bits.

The I²C master interface runs at the standard-mode rate of 100KHz and is fully compliant with the

Philips I C-Bus Specification. Refer to the he Philips I C-Bus Specification for detailed timing

information.

10.2.2.1

I C Protocol Overview

I²C is a bi-directional 2-wire data protocol. A device that sends data is defined as a transmitter and a

device that receives data is defined as a receiver. The bus is controlled by a master which generates

the EE_SCL clock, controls bus access, and generates the start and stop conditions. Either the master

or slave may operate as a transmitter or receiver as determined by the master.

The following bus states exist:

„

Idle: Both EE_SDA and EE_SCL are high when the bus is idle.

Start & Stop Conditions: A start condition is defined as a high to low transition on the EE_ SDA

line while EE_ SCL is high. A stop condition is defined as a low to high transition on the EE_SDA

line while EE_SCL is high. The bus is considered to be busy following a start condition and is

considered free 4.7uS/1.3uS (for 100KHz and 400KHz operation, respectively) following a stop

condition. The bus stays busy following a repeated start condition (instead of a stop condition).

Starts and repeated starts are otherwise functionally equivalent.

„

Data Valid: Data is valid, following the start condition, when EE_SDA is stable while EE_SCL is

high. Data can only be changed while the clock is low. There is one valid bit per clock pulse. Every

byte must be 8 bits long and is transmitted msb first.

Acknowledge: Each byte of data is followed by an acknowledge bit. The master generates a ninth

clock pulse for the acknowledge bit. The transmitter releases EE_SDA (high). The receiver drives

EE_SDA low so that it remains valid during the high period of the clock, taking into account the

setup and hold times. The receiver may be the master or the slave depending on the direction of

the data. Typically the receiver acknowledges each byte. If the master is the receiver, it does not

generate an acknowledge on the last byte of a transfer. This informs the slave to not drive the next

byte of data so that the master may generate a stop or repeated start condition.

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Figure 10.2 displays the various bus states of a typical I²C cycle.

data

can

change

data

can

change

data

can

change

data

can

change

data

stable

data

stable

EE_SDA

EE_SCL

Data Valid

or Ack

Data Valid

or Ack

Re-Start

Condition

Stop Condition

Start Condition

Figure 10.2 I C Cycle

10.2.2.2

I C EEPROM Device Addressing

The I²C EEPROM is addressed for a read or write operation by first sending a control byte followed

by the address byte or bytes. The control byte is preceded by a start condition. The control byte and

address byte(s) are each acknowledged by the EEPROM slave. If the EEPROM slave fails to send an

acknowledge, then the sequence is aborted and the EPC_TIMEOUT bit of the EEPROM Command

The control byte consists of a 4-bit control code, 3-bits of chip/block select and one direction bit. The

control code is 1010b. For single byte addressing EEPROMs, the chip/block select bits are used for

address bits 10, 9, and 8. For double byte addressing EEPROMs, the chip/block select bits are set

low. The direction bit is set low to indicate the address is being written.

Figure 10.3 illustrates typical I²C EEPROM addressing bit order for single and double byte addressing.

Address High

Byte

Address Low

Byte

Control Byte

Address Byte

Control Byte

Chip / Block R/~W

Select Bits

Chip / Block R/~W

Select Bits

Single Byte Addressing

Double Byte Addressing

Figure 10.3 I C EEPROM Addressing

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10.2.2.3

I C EEPROM Byte Read

Following the device addressing, a data byte may be read from the EEPROM by outputting a start

condition and control byte with a control code of 1010b, chip/block select bits as described in

Section 10.2.2.2, and the R/~W bit high. The EEPROM will respond with an acknowledge, followed by

8-bits of data. If the EEPROM slave fails to send an acknowledge, then the sequence is aborted and

the EPC_TIMEOUT bit in the EEPROM Command Register (E2P_CMD) is set. The I²C master then

sends a no-acknowledge, followed by a stop condition.

Figure 10.4 illustrates typical I²C EEPROM byte read for single and double byte addressing.

Control Byte

Data Byte

Control Byte

Data Byte

Chip / Block R/~W

Select Bits

Chip / Block R/~W

Select Bits

Single Byte Addressing Read

Double Byte Addressing Read

Figure 10.4 I C EEPROM Byte Read

For a register level description of a read operation, refer to Section 10.2.1, "EEPROM Controller

Operation," on page 138.

10.2.2.4

I C EEPROM Sequential Byte Reads

Following the device addressing, data bytes may be read sequentially from the EEPROM by outputting

a start condition and control byte with a control code of 1010b, chip/block select bits as described in

Section 10.2.2.2, and the R/~W bit high. The EEPROM will respond with an acknowledge, followed by

8-bits of data. If the EEPROM slave fails to send an acknowledge, then the sequence is aborted and

the EPC_TIMEOUT bit in the EEPROM Command Register (E2P_CMD) is set. The I²C master then

sends an acknowledge, and the EEPROM responds with the next 8-bits of data. This continues until

the last desired byte is read, at which point the I²C master sends a no-acknowledge, followed by a

stop condition.

Figure 10.4 illustrates typical I²C EEPROM sequential byte reads for single and double byte

addressing.

Control Byte

Data Byte

_C...

R/~W

Chip / Block

Select Bits

Single Byte Addressing Sequential Reads

Control Byte

Data Byte

...

Chip / Block R/~W

Select Bits

Double Byte Addressing Sequential Reads

Figure 10.5 I C EEPROM Sequential Byte Reads

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Sequential reads are used by the EEPROM Loader. Refer to Section 10.2.4, "EEPROM Loader" for

additional information.

For a register level description of a read operation, refer to Section 10.2.1, "EEPROM Controller

Operation," on page 138.

10.2.2.5

I C EEPROM Byte Writes

Following the device addressing, a data byte may be written to the EEPROM by outputting the data

after receiving the acknowledge from the EEPROM. The data byte is acknowledged by the EEPROM

slave and the I C master finishes the write cycle with a stop condition. If the EEPROM slave fails to

send an acknowledge, then the sequence is aborted and the EPC_TIMEOUT bit in the EEPROM

Command Register (E2P_CMD) is set.

Following the data byte write cycle, the I C master will poll the EEPROM to determine when the byte

write is finished. A start condition is sent followed by a control byte with a control code of 1010b,

chip/block select bits low, and the R/~W bit low. If the EEPROM is finished with the byte write, it will

respond with an acknowledge. Otherwise, it will respond with a no-acknowledge and the I C master

will repeat the poll. If the acknowledge does not occur within 30mS, a time-out occurs. Once the I C

master receives the acknowledge, it concludes by sending a start condition, followed by a stop

condition, which will place the EEPROM into standby.

Figure 10.4 illustrates typical I C EEPROM byte write.

Conclude

Data Cycle

Data Byte

Poll Cycle

Control Byte

... _S

R/~W

Chip / Block

Select Bits

Chip / Block

Select Bits

Chip / Block

Select Bits

Figure 10.6 I C EEPROM Byte Write

For a register level description of a write operation, refer to Section 10.2.1, "EEPROM Controller

Operation," on page 138.

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10.2.3

Microwire EEPROM

Based on the configuration strap eeprom_type_strap, various sized Microwire EEPROMs are

supported. The varying size ranges are supported by additional bits in the address field

(EPC_ADDRESS) of the EEPROM Command Register (E2P_CMD). Within each size range, the

largest EEPROM uses all the address bits, while the smaller EEPROMs treat the upper address bits

as don’t cares. The EEPROM controller drives all the address bits as requested regardless of the

actual size of the EEPROM. The supported size ranges for Microwire operation are shown in

T a ble 10.3.

Table 10.3 Microwire EEPROM Size Ranges

eeprom_size_strap[1:0]

# OF ADDRESS BITS

EEPROM SIZE

EEPROM TYPES

128 x 8

93xx46A

256 x 8 and 512 x 8

1024 x 8 and 2048 x 8

RESERVED

93xx56A, 93xx66A

93xx76A, 93xx86A

Refer to Section 15.5.10, "Microwire Timing," on page 452 for detailed Microwire timing information.

10.2.3.1

Microwire Master Commands

T a ble 10.4, T a ble 10.5, and T a ble 10.6 detail the Microwire command set, including the number of clock

cycles required, for 7, 9, and 11 address bits respectively. These commands are detailed in the

following sections as well as in Section 14.2.4.1, "EEPROM Command Register (E2P_CMD)," on

page 197.

Table 10.4 Microwire Command Set for 7 Address Bits

START

BIT

DATA TO

EEPROM

DATA FROM

EEPROM

# OF

CLOCKS

INST

OPCODE

ADDRESS

ERASE

ERAL

A6 A5 A4 A3 A2 A1 A0

(RDY/~BSY)

Hi-Z

EWDS

EWEN

READ

WRITE

WRAL

Hi-Z

A6 A5 A4 A3 A2 A1 A0

D7 - D0

(RDY/~BSY)

Table 10.5 Microwire Command Set for 9 Address Bits

DATA TO

START

BIT

DATA FROM

EEPROM

# OF

CLOCKS

INST

OPCODE

ADDRESS

EEPROM

ERASE

ERAL

A8 A7 A6 A5 A4 A3 A2 A1 A0

(RDY/~BSY)

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Table 10.5 Microwire Command Set for 9 Address Bits (continued)

START

BIT

DATA TO

EEPROM

DATA FROM

EEPROM

# OF

CLOCKS

INST

OPCODE

ADDRESS

EWDS

EWEN

READ

WRITE

WRAL

Hi-Z

A8 A7 A6 A5 A4 A3 A2 A1 A0

D7 - D0

(RDY/~BSY)

Table 10.6 Microwire Command Set for 11 Address Bits

DATA TO

START

BIT

DATA FROM

EEPROM

# OF

CLOCKS

INST

OPCODE

ADDRESS

EEPROM

A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

ERASE

ERAL

(RDY/~BSY)

Hi-Z

EWDS

EWEN

READ

WRITE

WRAL

Hi-Z

A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

D7 - D0

(RDY/~BSY)

10.2.3.2

ERASE (Erase Location)

If erase/write operations are enabled in the EEPROM, this command will erase the location selected

by the EPC_ADDRESS field of the EEPROM Command Register (E2P_CMD). The EPC_TIMEOUT

bit is set if the EEPROM does not respond within 30mS.

EECS

EECLK

EEDO

EEDI

Figure 10.7 EEPROM ERASE Cycle

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10.2.3.3

ERAL (Erase All)

If erase/write operations are enabled in the EEPROM, this command will initiate a bulk erase of the

entire EEPROM. The EPC_TIMEOUT bit of the EEPROM Command Register (E2P_CMD) is set if the

EEPROM does not respond within 30mS.

EECS

EECLK

EEDO

EEDI

Figure 10.8 EEPROM ERAL Cycle

10.2.3.4

EWDS (Erase/Write Disable)

After this command is issued, the EEPROM will ignore erase and write commands. To re-enable

erase/write operations, the EWEN command must be issued.

EECS

EECLK

EEDO

EEDI

Figure 10.9 EEPROM EWDS Cycle

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10.2.3.5

EWEN (Erase/Write Enable)

This command enables the EEPROM for erase and write operations. The EEPROM will allow erase

and write operations until the EWDS command is sent, or until power is cycled.

Note: The EEPROM will power-up in the erase/write disabled state. Any erase or write operations

will fail until an EWEN command is issued.

EECS

EECLK

EEDO

EEDI

Figure 10.10 EEPROM EWEN Cycle

10.2.3.6

READ (Read Location)

This command will cause a read of the EEPROM location pointed to by the EPC_ADDRESS field of

the EEPROM Command Register (E2P_CMD). The result of the read is available in the EEPROM Data

EECS

EECLK

EEDO

EEDI

Figure 10.11 EEPROM READ Cycle

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10.2.3.7

WRITE (Write Location)

If erase/write operations are enabled in the EEPROM, this command will cause the contents of the

EEPROM Data Register (E2P_DATA) to be written to the EEPROM location pointed to by the

EPC_ADDRESS field of the EEPROM Command Register (E2P_CMD). The EPC_TIMEOUT bit of the

EEPROM Command Register (E2P_CMD) is set if the EEPROM does not respond within 30mS.

EECS

EECLK

EEDO

EEDI

Figure 10.12 EEPROM WRITE Cycle

10.2.3.8

WRAL (Write All)

If erase/write operations are enabled in the EEPROM, this command will cause the contents of the

EEPROM Data Register (E2P_DATA) to be written to every EEPROM memory location. The

EPC_TIMEOUT bit of the EEPROM Command Register (E2P_CMD) is set if the EEPROM does not

respond within 30mS.

EECS

EECLK

EEDO

EEDI

Figure 10.13 EEPROM WRAL Cycle

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10.2.4

EEPROM Loader

The EEPROM Loader interfaces to the I C/Microwire EEPROM controller, the PHYs, and to the system

CSRs (via the Register Access MUX). Only system CSRs at addresses 100h and above are accessible

to the EEPROM Loader (with the addition of the PHY Management Interface Data Register

(PMI_DATA) and PHY Management Interface Access Register (PMI_ACCESS) at addresses A4 and

A8 respectively).

The EEPROM Loader runs upon a pin reset (nRST), power-on reset (POR), digital reset

(DIGITAL_RST bit in the Reset Control Register (RESET_CTL)), or upon the issuance of a RELOAD

command via the EEPROM Command Register (E2P_CMD). A soft reset will run the EEPROM

Loader, but only the MAC address is loaded into the Host MAC. Refer to Section 4.2, "Resets," on

page 36 for additional information on the LAN9312 resets.

The EEPROM contents must be loaded in a specific format for use with the EEPROM Loader. An

overview of the EEPROM content format is shown in T a ble 10.7. Each section of EEPROM contents

is discussed in detail in the following sections.

Table 10.7 EEPROM Contents Format Overview

EEPROM ADDRESS

DESCRIPTION

EEPROM Valid Flag

VALUE

A5h

MAC Address Low Word [7:0]

MAC Address Low Word [15:8]

MAC Address Low Word [23:16]

MAC Address Low Word [31:24]

MAC Address High Word [7:0]

MAC Address High Word [15:8]

Configuration Strap Values Valid Flag

Configuration Strap Values

Byte on the Network

A5h

8 - 11

See T a ble 10.8

A5h

Burst Sequence Valid Flag

Number of Bursts

See Section 10.2.4.5,

"Register Data"

14 and above

Burst Data

See Section 10.2.4.5,

"Register Data"

10.2.4.1

EEPROM Loader Operation

Upon a pin reset (nRST), power-on reset (POR), digital reset (DIGITAL_RST bit in the Reset Control

While the EEPROM Loader is active, the READY bit of the Hardware Configuration Register

(HW_CFG) and Power Management Control Register (PMT_CTRL) is cleared and no writes to the

LAN9312 should be attempted. The operational flow of the EEPROM Loader can be seen in

Figure 10.14.

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DIGITAL_RST, nRST,

POR, RELOAD

EPC_BUSY = 1

Read Byte 0

Load PHY registers with

current straps

Byte 0 = A5h

Read Bytes 1-6

EPC_BUSY = 0

Write Bytes 1-6 into Host

MAC and switch MAC

Address Registers

Soft Reset

Read Byte 7-11

EPC_BUSY = 1

Read Byte 0

Load PHY registers with

current straps

Byte 7 = A5h

Byte 0 = A5h

Write Bytes 8-11 into

Configuration Strap

registers

Read Bytes 1-6

Write Bytes 1-6 into Host

MAC Address Registers

Update PHY registers

Update VPHY registers

Update LED_CFG,

MANUAL_FC_1,

MANUAL_FC_2 and

MANUAL_FC_mii

registers

Read Byte 12

Byte 12 = A5h

Perform register data

load loop

Figure 10.14 EEPROM Loader Flow Diagram

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10.2.4.2

EEPROM Valid Flag

Following the release of nRST, POR, DIGITAL_RST, or a RELOAD command, the EEPROM Loader

starts by reading the first byte of data from the EEPROM. If the value of A5h is not read from the first

byte, the EEPROM Loader will load the current configuration strap values into the PHY registers (see

Section 10.2.4.4.1) and then terminate, clearing the EPC_BUSY bit in the EEPROM Command

EEPROM.

10.2.4.3

MAC Address

The next six bytes in the EEPROM, after the EEPROM Valid Flag, are written into the Host MAC

Address High Register (HMAC_ADDRH) and Host MAC Address Low Register (HMAC_ADDRL), and

the Switch Fabric MAC Address High Register (SWITCH_MAC_ADDRH) and Switch Fabric MAC

Address Low Register (SWITCH_MAC_ADDRL). The EEPROM bytes are written into the MAC

address registers in the order specified in T a ble 10.7. Refer to Section 9.6, "Host MAC Address," on

page 119 for additional information on MAC address loading.

10.2.4.3.1

HOST MAC ADDRESS RELOAD

While the EEPROM Loader is in the wait state, if a Host MAC reset is detected (via the Soft Reset bit

in the Hardware Configuration Register (HW_CFG)), the EEPROM Loader will read byte 0. If the byte

0 value is A5h, the EEPROM Loader will read bytes 1 through 6 from the EEPROM and reload the

Host MAC Address High Register (HMAC_ADDRH) and Host MAC Address Low Register

(HMAC_ADDRL). During this time, the EPC_BUSY bit in the EEPROM Command Register

(E2P_CMD) is set.

Note: The switch MAC address registers are not reloaded due to this condition.

10.2.4.4

Soft-Straps

The 7 byte of data to be read from the EEPROM is the Configuration Strap Values Valid Flag. If this

byte has a value of A5h, the next 4 bytes of data (8-11) are written into the configuration strap registers

per the assignments detailed in T a ble 10.8. If the flag byte is not A5h, these next 4 bytes are skipped

(they are still read to maintain the data burst, but are discarded). However, the current configuration

strap values are still loaded into the PHY registers (see Section 10.2.4.4.1). Refer to Section 4.2.4,

"Configuration Straps," on page 40 for more information on the LAN9312 configuration straps.

Table 10.8 EEPROM Configuration Bits

BYTE/BIT

BP_EN_

strap_1

FD_FC_

strap_1

manual_

FC_strap_1

manual_mdix

_strap_1

auto_mdix_

strap_1

speed_

strap_1

duplex_

strap_1

autoneg_

strap_1

Byte 8

BP_EN_

strap_2

FD_FC_

strap_2

manual_

FC_strap_2

manual_mdix

_strap_2

auto_mdix_

strap_2

speed_

strap_2

duplex_

strap_2

autoneg_

strap_2

Byte 9

LED_fun_strap[1:0]

BP_EN_

strap_mii

FD_FC_

strap_mii

manual_FC

_strap_mii

speed_

strap_mii

duplex_pol_

strap_mii

SQE_test_

disable_strap

_mii

Byte 10

LED_en_strap[7:0]

Byte 11

10.2.4.4.1

PHY REGISTERS SYNCHRONIZATION

Some PHY register defaults are based on configuration straps. In order to maintain consistency

between the updated configuration strap registers and the PHY registers, the Port x PHY Auto-

Negotiation Advertisement Register (PHY_AN_ADV_x), Port x PHY Special Modes Register

(PHY_SPECIAL_MODES_x), and Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x) are

written when the EEPROM Loader is run.

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The Port x PHY Auto-Negotiation Advertisement Register (PHY_AN_ADV_x) is written with the new

defaults as detailed in Section 14.4.2.5, "Port x PHY Auto-Negotiation Advertisement Register

(PHY_AN_ADV_x)," on page 293.

The Port x PHY Special Modes Register (PHY_SPECIAL_MODES_x) is written with the new defaults

as detailed in Section 14.4.2.9, "Port x PHY Special Modes Register (PHY_SPECIAL_MODES_x)," on

page 300.

The Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x) is written with the new defaults

as detailed in Section 14.4.2.1, "Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x)," on

page 287. Additionally, the Restart Auto-negotiation bit is set in this register. This re-runs the Auto-

negotiation using the new default values of the Port x PHY Auto-Negotiation Advertisement Register

(PHY_AN_ADV_x) register to determine the new Auto-negotiation results.

Note: Each of these PHY registers is written in its entirety, overwriting any previously changed bits.

10.2.4.4.2

VIRTUAL PHY REGISTERS SYNCHRONIZATION

Some PHY register defaults are based on configuration straps. In order to maintain consistency

between the updated configuration strap registers and the Virtual PHY registers, the Virtual PHY Auto-

Negotiation Advertisement Register (VPHY_AN_ADV), Virtual PHY Special Control/Status Register

(VPHY_SPECIAL_CONTROL_STATUS), and V irtual PHY Basic Control Register

(VPHY_BASIC_CTRL) are written when the EEPROM Loader is run.

The Virtual PHY Auto-Negotiation Advertisement Register (VPHY_AN_ADV) is written with the new

defaults as detailed in Section 14.2.8.5, "Virtual PHY Auto-Negotiation Advertisement Register

(VPHY_AN_ADV)," on page 252.

The Virtual PHY Special Control/Status Register (VPHY_SPECIAL_CONTROL_STATUS) is written

with the new defaults as detailed in Section 14.2.8.8, "Virtual PHY Special Control/Status Register

(VPHY_SPECIAL_CONTROL_STATUS)," on page 257.

The Virtual PHY Basic Control Register (VPHY_BASIC_CTRL) is written with the new defaults as

detailed in Section 14.2.8.1, "Virtual PHY Basic Control Register (VPHY_BASIC_CTRL)," on page 246.

Additionally, the Restart Auto-negotiation bit is set in this register. This re-runs the Auto-negotiation

using the new default values of the Virtual PHY Auto-Negotiation Advertisement Register

(VPHY_AN_ADV) register to determine the new Auto-negotiation results.

Note: Each of these VPHY registers is written in its entirety, overwriting any previously changed bits.

10.2.4.4.3

10.2.4.5

LED AND MANUAL FLOW CONTROL REGISTER SYNCHRONIZATION

Since the defaults of the LED Configuration Register (LED_CFG), Port 1 Manual Flow Control Register

(MANUAL_FC_1), Port 2 Manual Flow Control Register (MANUAL_FC_2), and Port 0(Host MAC)

Manual Flow Control Register (MANUAL_FC_MII) are based on configuration straps, the EEPROM

Loader reloads these registers with their new default values.

Optionally following the configuration strap values, the EEPROM data may be formatted to allow

access to the LAN9312 parallel, directly writable registers. Access to indirectly accessible registers

(e.g. Switch Engine registers, etc.) is achievable with an appropriate sequence of writes (at the cost

of EEPROM space).

This data is first preceded with a Burst Sequence Valid Flag (EEPROM byte 12). If this byte has a

value of A5h, the data that follows is recognized as a sequence of bursts. Otherwise, the EEPROM

Loader is finished, will go into a wait state, and clear the EPC_BUSY bit in the EEPROM Command

The data at EEPROM byte 13 and above should be formatted in a sequence of bursts. The first byte

is the total number of bursts. Following this is a series of bursts, each consisting of a starting address,

count, and the count x 4 bytes of data. This results in the following formula for formatting register data:

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8-bits number_of_bursts

repeat (number_of_bursts)

16-bits {starting_address[9:2] / count[7:0]}

repeat (count)

8-bits data[31:24], 8-bits data[23:16], 8-bits data[15:8], 8-bits data[7:0]

Note: The starting address is a DWORD address. Appending two 0 bits will form the register address.

As an example, the following is a 3 burst sequence, with 1, 2, and 3 DWORDs starting at register

addresses 40h, 80h, and C0h respectively:

A5h, (Burst Sequence Valid Flag)

3h, (number_of_bursts)

16{10h, 1h}, (starting_address1 divided by 4 / count1)

11h, 12h, 13h, 14h, (4 x count1 of data)

16{20h, 2h}, (starting_address2 divided by 4 / count2)

21h, 22h, 23h, 24h, 25h, 26h, 27h, 28h, (4 x count2 of data)

16{30h, 3h}, (starting_address3 divided by 4 / count3)

31h, 32h, 33h, 34h, 35h, 36h, 37h, 38h, 39h, 3Ah, 3Bh, 3Ch (4 x count3 of data)

In order to avoid overwriting the Switch CSR register interface or the PHY Management Interface

(PMI), the EEPROM Loader waits until the CSR Busy bit of the Switch Fabric CSR Interface Command

The EEPROM Loader checks that the EEPROM address space is not exceeded. If so, it will stop and

set the EEPROM Loader Address Overflow bit in the EEPROM Command Register (E2P_CMD). The

address limit is based on the eeprom_size_strap which specifies a range of sizes. The address limit

is set to the largest value of the specified range.

10.2.4.6

10.2.4.7

EEPROM Loader Finished Wait-State

Once finished with the last burst, the EEPROM Loader will go into a wait-state and the EPC_BUSY

bit of the EEPROM Command Register (E2P_CMD) will be cleared.

Reset Sequence and EEPROM Loader

In order to allow the EEPROM Loader to change the Port 1/2 PHYs and Virtual PHY strap inputs and

maintain consistency with the PHY and Virtual PHY registers, the following sequence is used:

1. After power-up or upon a hardware reset (nRST), the straps are sampled into the LAN9312 as

specified in Section 15.5.2, "Reset and Configuration Strap Timing," on page 444.

2. After the PLL is stable, the main chip reset is released and the EEPROM Loader reads the

EEPROM and configures (overrides) the strap inputs.

3. The EEPROM Loader writes select Port 1/2 and Virtual PHY registers, as specified in

Section 10.2.4.4.1 and Section 10.2.4.4.2, respectively.

Note: Step 3 is also performed in the case of a RELOAD command or digital reset.

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Chapter 11 IEEE 1588 Hardware Time Stamp Unit

11.1

Functional Overview

The LAN9312 provides hardware support for the IEEE 1588 Precision Time Protocol (PTP), allowing

clock synchronization with remote Ethernet devices, packet time stamping, and time driven event

generation. Time stamping is supported on all ports, with an individual IEEE 1588 Time Stamp module

connected to each port via the MII bus. Any port may function as a master or a slave clock per the

IEEE 1588 specification, and the LAN9312 as a whole may function as a boundary clock.

A 64-bit tunable clock is provided that is used as the time source for all IEEE 1588 time stamp related

functions. An IEEE 1588 Clock/Events block provides IEEE 1588 clock comparison based interrupt

generation and time stamp related GPIO event generation. Two LAN9312 GPIO pins (GPIO[8:9]) can

be used to trigger a time stamp capture when configured as an input, or output a signal from the GPIO

based on an IEEE 1588 clock target compare event when configured as an output. Section 11.1.2,

"Block Diagram" describes the various IEEE 1588 related blocks and how they interface to other

LAN9312 functions.

All features of the IEEE 1588 hardware time stamp unit can be monitored and configured via their

respective configuration and status registers. A detailed description of all IEEE 1588 CSRs is included

in Section 14.2.5, "IEEE 1588," on page 201.

11.1.1

IEEE 1588

IEEE 1588 specifies a Precision Time Protocol (PTP) used by master and slave clock devices to pass

time information in order to achieve clock synchronization. Five network message types are defined:

„

Sync

Delay_Req

Follow_Up

Delay_Resp

Management

Only the first four message types (Sync, Delay_Req, Follow_Up, Delay_Resp) are used for clock

synchronization. Using these messages, the protocol software may calculate the offset and network

delay between time stamps, adjusting the slave clock frequency as needed. Refer to the IEEE 1588

protocol for message definitions and proper usage.

A PTP domain is segmented into PTP sub-domains, which are then segmented into PTP

communication paths. Within each PTP communication path there is a maximum of one master clock,

which is the source of time for each slave clock. The determination of which clock is the master and

which clock(s) is(are) the slave(s) is not fixed, but determined by the IEEE 1588 protocol. Similarly,

each PTP sub-domain may have only one master clock, referred to as the Grand Master Clock.

PTP communication paths are conceptually equivalent to Ethernet collision domains and may contain

devices which extend the network. However, unlike Ethernet collision domains, the PTP

communication path does not stop at a network switch, bridge, or router. This leads to a loss of

precision when the network switch/bridge/router introduces a variable delay. Boundary clocks are

defined which conceptually bypass the switch/bridge/router (either physically or via device integration).

Essentially, a boundary clock acts as a slave to an upstream master, and as a master to a down stream

slave. A boundary clock may contain multiple ports, but a maximum of one slave port is permitted.

For more information on the IEEE 1588 protocol, refer to the National Institute of Standards and

Technology IEEE 1588 website:

http://ieee1588.nist.gov/

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11.1.2

Block Diagram

The LAN9312 IEEE 1588 implementation is illustrated in Figure 11.1, and consists of the following

major function blocks:

„

IEEE 1588 Time Stamp

These three identical blocks provide time stamping functions on all switch fabric ports.

„

IEEE 1588 Clock

This block provides a 64-bit tunable clock that is used as the time source for all IEEE 1588 time

stamp related functions.

„

IEEE 1588 Clock/Events

This block provides IEEE 1588 clock comparison-based interrupt generation and time stamp related

GPIO event generation.

IEEE 1588

Time Stamp

MII

Ethernet

10/100

PHY

To Host MAC

Switch Fabric

MII

10/100

PHY

IEEE 1588 Time Stamp

Clock Capture RX

IEEE 1588 Clock

32 Bit Addend

Src UUID Capture RX

Sequence ID Capture RX

IRQ Flag

32 Bit Accumulator

inc

Sync / Delay_Req

Msg Detect RX

carry

RX: Delay_Req for Master, Sync for Slave

host

64 Bit Clock

Clock Capture TX

Src UUID Capture TX

Sequence ID Capture TX

IRQ Flag

Sync / Delay_Req

Msg Detect TX

host

TX: Sync for Master, Delay_Req for Slave

IEEE 1588 Clock Events

64 Bit Reload / Add

load / add

64 Bit Clock Target

compare >=

GPIO[8:9]

(Outputs)

IRQ Flag

Clock Capture GPIO8

IRQ Flag

GPIO[8:9]

(Inputs)

IRQ Flags

IRQ Enables

To INT_STS register

Clock Capture GPIO9

IRQ Flag

host

Figure 11.1 IEEE 1588 Block Diagram

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11.2

IEEE 1588 Time Stamp

The LAN9312 contains three identical IEEE 1588 Time Stamp blocks as shown in Figure 11.1. These

blocks are responsible for capturing the source UUID, sequence ID, and current 64-bit IEEE 1588 clock

time upon detection of a Sync or Delay_Req message type on their respective port. The mode of the

clock (master or slave) determines which message is detected on receive and transmit. For slave clock

operation, Sync messages are detected on receive and Delay_Req messages on transmit. For master

clock operation, Delay_Req messages are detected on receive and Sync messages on transmit.

Follow_Up, Delay_Resp and Management packet types do not cause capture. Each port may be

individually configured as an IEEE 1588 master or slave clock via the master/slave bits (M_nS_1 for

Port 1, MnS_2 for Port2, and M_nS_MII for Port 0) in the 1588 Configuration Register (1588_CONFIG).

T a ble 11.1 summarizes the message type detection under slave and master IEEE 1588 clock

operation.

Table 11.1 IEEE 1588 Message Type Detection

IEEE 1588 CLOCK MODE

RECEIVE

TRANSMIT

Slave

Sync

Delay_Req

(M_nS_x = 0)

Master

Delay_Req

Sync

(M_nS_x = 1)

For ports 1 and 2, receive is defined as data from the PHY (from the outside world) and transmit is

defined as data to the PHY. This is consistent with the point-of-view of where the partner clock resides

(LAN9312 receives packets from the partner via the PHY, etc.). For the time stamp module connected

to the Host MAC (Port 0), the definition of transmit and receive is reversed. Receive is defined as data

from the switch fabric, while transmit is defined as data to the switch fabric. This is consistent with the

point-of-view of where the partner clock resides (LAN9312 receives packets from the partner via the

switch fabric, etc.).

As defined by IEEE 1588, and shown in Figure 11.2, the message time stamp point is defined as the

leading edge of the first data bit following the Start of Frame Delimiter (SFD). However, since the

packet contents are not yet known, the time stamp can not yet be loaded into the capture register.

Therefore, the time stamp is first stored into a temporary internal holding register at the start of every

packet.

Message Timestamp

Point

Ethernet

Start of Frame

Delimiter

First Octet

following

Start of Frame

Preamble

Octet

1 1 1

0 0 0 0 0 0 0

bit time

Figure 11.2 IEEE 1588 Message Time Stamp Point

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Clock synchronization and hardware processing between the network data and the time stamp capture

hardware causes the time stamp point to be slightly delayed. The host software can account for this

delay, as it is fairly deterministic. T a ble 11.2 details the time stamp capture delay as a function of the

mode of operation. Refer to Chapter 7, "Ethernet PHYs," on page 82 for details on these modes.

Table 11.2 Time Stamp Capture Delay

MODE OF OPERATION

DELAY (+/- 10 nS)

100 Mbps

10 Mbps

30 nS

120 nS

Once the packet type is matched, according to T a ble 11.1, and the Frame Check Sequence (FCS) is

verified, the following occurs:

„

The time stamp is loaded into the corresponding ports’ capture registers:

–On Reception: Port x 1588 Clock High-DWORD Receive Capture Register

(1588_CLOCK_HI_RX_CAPTURE_x) and Port x 1588 Clock Low-DWORD Receive Capture

–On Transmission: Port x 1588 Clock High-DWORD Transmit Capture Register

(1588_CLOCK_HI_TX_CAPTURE_x) and Port x 1588 Clock Low-DWORD Transmit Capture

The Sequence ID and Source UUID are loaded into the corresponding ports’ registers:

–On Reception: Port x 1588 Sequence ID, Source UUID High-WORD Receive Capture Register

(1588_SEQ_ID_SRC_UUID_HI_RX_CAPTURE_x) and Port x 1588 Source UUID Low-

DWORD Receive Capture Register (1588_SRC_UUID_LO_RX_CAPTURE_x)

–On Transmission: Port x 1588 Sequence ID, Source UUID High-WORD Transmit Capture

Low-DWORD Transmit Capture Register (1588_SRC_UUID_LO_TX_CAPTURE_x)

The corresponding maskable interrupt flag is set in the 1588 Interrupt Status and Enable Register

(1588_INT_STS_EN). (Refer to Section 11.6, "IEEE 1588 Interrupts," on page 160 for information

on IEEE 1588 interrupts.)

Note: Packets that do not contain an integral number of octets are not considered valid and do not

cause a capture.

11.2.1

Capture Locking

The corresponding ports’ clock capture, sequence ID, and source UUID registers can be optionally

locked when a capture event occurs, preventing them from being overwritten until the host clears the

corresponding interrupt flag in the 1588 Interrupt Status and Enable Register (1588_INT_STS_EN).

This is accomplished by setting the corresponding lock enable bit(s) in the 1588 Configuration Register

(1588_CONFIG). Each port has two lock enable control bits within this register, which allow the receive

and transmit portions of each port to be locked independently. In addition, a lock enable bit is provided

for each time stamp enabled GPIO (LOCK_ENABLE_GPIO_8 and LOCK_ENABLE_GPIO_9) which

prevents the corresponding GPIO clock capture registers from being overwritten when the GPIO

interrupt in 1588 Interrupt Status and Enable Register (1588_INT_STS_EN) is set. Refer to Section

14.2.5.22, "1588 Configuration Register (1588_CONFIG)," on page 222 for additional information on

the capture locking related bits.

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11.2.2

PTP Message Detection

In order to provide the most flexibility, loose packet type matching is used by the LAN9312. This

assumes that for all packets received with a valid FCS, only the MAC destination address is required

to qualify them as a PTP message. For Ethernet, four multicast addresses are specified in the PTP

protocol: 224.0.1.129 through 224.0.1.132. These map to Ethernet MAC addresses 01:00:5e:00:01:81

through 01:00:5e:00:01:84. Each of these addresses has one enable bit per port in the 1588

Configuration Register (1588_CONFIG) which enables/disables the corresponding address as a PTP

address on the specified port.

In addition to the fixed addresses, a user defined (host programmable) PTP address may be input via

the 1588 Auxiliary MAC Address High-WORD Register (1588_AUX_MAC_HI) and 1588 Auxiliary MAC

Address Low-DWORD Register (1588_AUX_MAC_LO). The user defined address may be

disabled/enabled as a PTP address on each port via the dedicated enable bits in the 1588

Configuration Register (1588_CONFIG). A summary of the supported PTP multicast addresses and

corresponding enable bits can be seen in T a ble 11.3.

Table 11.3 PTP Multicast Addresses

CORRESPONDING

MAC ADDRESS

RELATED ENABLE BITS IN THE

1588_CONFIG REGISTER

PTP ADDRESS

224.0.1.129

(Primary)

01:00:5e:00:01:81

01:00:5e:00:01:82

01:00:5e:00:01:83

01:00:5e:00:01:84

MAC_PRI_EN_1 (Port 1)

MAC_PRI_EN_2 (Port 2)

MAC_PRI_EN_MII (Port 0)

224.0.1.130

(Alternate 1)

MAC_ALT1_EN_1 (Port 1)

MAC_ALT1_EN_2 (Port 2)

MAC_ALT1_EN_MII (Port 0)

224.0.1.131

(Alternate 2)

MAC_ALT2_EN_1 (Port 1)

MAC_ALT2_EN_2 (Port 2)

MAC_ALT2_EN_MII (Port 0)

224.0.1.132

(Alternate 3)

MAC_ALT3_EN_1 (Port 1)

MAC_ALT3_EN_2 (Port 2)

MAC_ALT3_EN_MII (Port 0)

User Defined

User Defined Address

(1588_AUX_MAC_HI &

1588_AUX_MAC_LO registers)

MAC_USER_EN_1 (Port 1)

MAC_USER_EN_2 (Port 2)

MAC_USER_EN_MII (Port 0)

Once a packet is determined to match a PTP destination address, it is further qualified as a Sync or

Delay_Req message type. On Ethernet, PTP uses UDP messages. Within the UDP payload is the PTP

control byte (offset 32 starting at 0). This byte determines the message type: 0x00 for a Sync message,

0x01 for a Delay_Req message. The UDP payload starts at packet byte offset 42 (from 0) for untagged

packets and at byte offset 46 for tagged packets.

Note: Both tagged and untagged packets are supported. Only Ethernet II packet encoding and IPv4

are supported.

Note: For proper routing of the PTP packets, the host must program an entry into the switch engine

Address Logic Resolution (ALR) Table. The MAC address should be one of the reserved

Multicast addresses in T a ble 11.3, with Port 0(Host MAC) as a destination.The Static and Valid

bits must also be set. Refer to Chapter 6, "Switch Fabric," on page 55 for more information.

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11.3

IEEE 1588 Clock

The 64-bit IEEE 1588 clock is the time source for all IEEE 1588 related functions of the LAN9312. It

is readable and writable by the host via the 1588 Clock High-DWORD Register (1588_CLOCK_HI) and

1588 Clock Low-DWORD Register (1588_CLOCK_LO).

In order to accurately read this clock, a special procedure must be followed. Since two DWORD reads

are required to fully read the 64-bit clock, the possibility exists that as the lower 32-bits roll over, a

wrong intermediate value could be read. To prevent this, a snapshot register technique is used. When

the 1588_CLOCK_SNAPSHOT bit in the 1588 Command Register (1588_CMD) register is written with

“1”, the current value of the 1588 clock is saved, allowing it to be properly read.

When writing a new value to the IEEE 1588 clock, two 32-bit write cycles are required (one for each

clock register) before the registers are affected. The writes may be in any order. However, caution must

be observed when changing the clock value in a live environment as it will disrupt linear time. If the

clock must be adjusted during operation of the 1588 protocol, it is preferred to adjust the Addend value,

effectively speeding-up or slowing-down the clock until the correct time is achieved.

The 64-bit IEEE 1588 clock consists of the 32-bit 1 588 Clock Addend Register

(1588_CLOCK_ADDEND) that is added to a 32-bit Accumulator every 100 MHz clock. Upon overflow

of the Accumulator, the 64- bit IEEE 1588 clock is incremented. The Addend / Accumulator pair form

a high precision frequency divider which can be used to compensate for the inaccuracy of the

reference crystal. The nominal frequency of the 64-bit IEEE 1588 clock and the value of the Addend

are calculated as follows:

FreqClock = (Addend / 2 ) * 100 MHz

Addend = (FreqClock * 2 ) / 100 MHz

Typical values for the Addend are shown in T a ble 11.4. These values should be adjusted based on the

accuracy of the IEEE 1588 clock compared to the master clock per the PTP protocol. The adjustment

precision column of the table shows the percentage change for the specified IEEE 1588 clock

frequency if the Addend was to be incremented or decremented by 1.

Table 11.4 Typical IEEE 1588 Clock Addend Values

IEEE 1588 CLOCK

(FreqClock)

1588_CLOCK_ADDEND

(Addend)

ADJUSTMENT PRECISION %

-8

33 MHz

50 MHz

66 MHz

75 MHz

90 MHz

547AE147h

80000000h

A8F5C28Fh

C0000000h

E6666666h

7.1*10

-8

4.7*10

-8

3.5*10

-8

3.1*10

-8

2.6*10

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11.4

IEEE 1588 Clock/Events

The IEEE 1588 Clock/Events block is responsible for generating and controlling all IEEE 1588 clock

related events. A 64-bit comparator is included in this block which compares the 64-bit IEEE 1588 clock

with a 64-bit Clock Target loaded in the 1 588 Clock T a rget High-DWORD Register

(1588_CLOCK_TARGET_HI) and 1 588 Clock T a rget Low-DWORD Register

(1588_CLOCK_TARGET_LO).

When the IEEE 1588 clock equals the Clock Target, a clock event occurs which triggers the following:

„

The maskable interrupt 1588_TIMER_INT is set in the 1588 Interrupt Status and Enable Register

(1588_INT_STS_EN).

The RELOAD_ADD bit in the 1588 Configuration Register (1588_CONFIG) is checked to determine

the new Clock Target behavior:

–RELOAD_ADD = 1:

The new Clock Target is loaded from the 64-bit Reload / Add Registers (1588 Clock T a rget

Reload High-DWORD Register (1588_CLOCK_TARGET_RELOAD_HI) and 1588 Clock T a rget

Reload/Add Low-DWORD Register (1588_CLOCK_TARGET_RELOAD_LO)).

–RELOAD_ADD = 0:

The Clock Target is incremented by the 1588 Clock T a rget Reload/Add Low-DWORD Register

(1588_CLOCK_TARGET_RELOAD_LO).

Note: Writing the IEEE 1588 clock may cause the interrupt event to occur if the new IEEE 1588 clock

value is set equal to the current Clock Target.

The Clock Target reload function (RELOAD_ADD = 1) allows the host to pre-load the next trigger time.

The add function (RELOAD_ADD = 0), allows for a repeatable event. When the Clock Target overflows,

it will wrap around past 0, as will the 64-bit IEEE 1588 clock. Since the Clock Target and Reload / Add

Registers are 64-bits, they require two 32-bit write cycles, one to each half, before the registers are

affected. The writes may be in any order.

11.5

11.6

IEEE 1588 GPIOs

In addition to time stamping PTP packets, the IEEE 1588 clock value can be saved into a set of clock

capture registers based on the GPIO[9:8] inputs. When configured as outputs, GPIO[9:8] can be used

to output a signal based on an IEEE 1588 clock target compare event. Refer to Section 13.2.1, "GPIO

IEEE 1588 Timestamping," on page 163 for information on using GPIO[9:8] for IEEE 1588 time

stamping functions.

IEEE 1588 Interrupts

The IEEE 1588 hardware time stamp unit provides multiple interrupt conditions. These include time

stamp indication on the transmitter and receiver side of each port, individual GPIO[9:8] input time

stamp interrupts, and a clock comparison event interrupt. All IEEE 1588 interrupts are located in the

1588 Interrupt Status and Enable Register (1588_INT_STS_EN) and are fully maskable via their

respective enable bits. Refer to Section 14.2.5.23, "1588 Interrupt Status and Enable Register

(1588_INT_STS_EN)," on page 226 for bit-level definitions of all IEEE 1588 interrupts and enables.

All IEEE 1588 interrupts are ANDed with their individual enables and then ORed, as shown in

Figure 11.1, generating the 1588_EVNT bit of the Interrupt Status Register (INT_STS).

When configured as an input, GPIO[9:8] have the added functionality of clearing the Clock Target

interrupt bit (1588_TIMER_INT) of the 1588 Interrupt Status and Enable Register (1588_INT_STS_EN)

on an active edge. GPIO inputs must be active for greater than 40 nS to be recognized as clear events.

For more information on IEEE 1588 GPIO interrupts, refer to Section 13.2.2, "GPIO Interrupts," on

page 163.

Refer to Chapter 5, "System Interrupts," on page 49 for additional information on the LAN9312

interrupts.

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Chapter 12 General Purpose Timer & Free-Running Clock

This chapter details the LAN9312 General Purpose Timer (GPT) and the Free-Running Clock.

12.1

General Purpose Timer

The LAN9312 provides a 16-bit programmable General Purpose Timer that can be used to generate

periodic system interrupts. The resolution of this timer is 100uS.

The GPT loads the General Purpose Timer Count Register (GPT_CNT) with the value in the

GPT_LOAD field of the General Purpose Timer Configuration Register (GPT_CFG) when the

TIMER_EN bit of the General Purpose Timer Configuration Register (GPT_CFG) is asserted (1). On

a chip-level reset, or when the TIMER_EN bit changes from asserted (1) to de-asserted (0), the

GPT_LOAD field is initialized to FFFFh. The General Purpose Timer Count Register (GPT_CNT) is

also initialized to FFFFh on reset. Software can write a pre-load value into the GPT_LOAD field at any

time (e.g. before or after the TIMER_EN bit is asserted).

Once enabled, the GPT counts down until it reaches 0000h, or until a new pre-load value is written to

the GPT_LOAD field. At 0000h, the counter wraps around to FFFFh, asserts the GPT interrupt status

bit (GPT_INT) in the Interrupt Status Register (INT_STS), asserts the IRQ interrupt (if GPT_INT_EN is

set in the Interrupt Status Register (INT_STS)), and continues counting. GPT_INT is a sticky bit. Once

this bit is asserted, it can only be cleared by writing a 1 to the bit. Refer to Section 5.2.7, "General

Purpose Timer Interrupt," on page 53 for additional information on the GPT interrupt.

12.2

Free-Running Clock

The Free-Running Clock (FRC) is a simple 32-bit up-counter that operates from a fixed 25MHz clock.

The current FRC value can be read via the Free Running 25MHz Counter Register (FREE_RUN). On

assertion of a chip-level reset, this counter is cleared to zero. On de-assertion of a reset, the counter

is incremented once for every 25MHz clock cycle. When the maximum count has been reached, the

counter rolls over to zeros. The FRC does not generate interrupts.

Note: The free running counter can take up to 160nS to clear after a reset event.

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Chapter 13 GPIO/LED Controller

13.1

Functional Overview

The GPIO/LED Controller provides 12 configurable general purpose input/output pins, GPIO[11:0].

These pins can be individually configured to function as inputs, push-pull outputs, or open drain outputs

and each is capable of interrupt generation with configurable polarity. Two of the GPIO pins (GPIO[9:8])

can be used for IEEE 1588 timestamp functions, allowing GPIO driven 1588 time clock capture when

configured as an input, or GPIO output generation based on an IEEE 1588 clock target compare event.

In addition, 8 of the GPIO pins can be alternatively configured as LED outputs. These pins, GPIO[7:0]

(nP1LED[3:0] and nP2LED[3:0]), may be enabled to drive Ethernet status LEDs for external indication

of various attributes of the switch ports.

GPIO and LED functionality is configured via the GPIO/LED System Control and Status Registers

(CSRs), accessible through the Host Bus Interface (HBI). These registers are defined in Section

14.2.3, "GPIO/LED," on page 192.

13.2

GPIO Operation

The GPIO controller is comprised of 12 programmable input/output pins. These pins are individually

configurable via the GPIO CSRs. On application of a chip-level reset:

„

All GPIOs are set as inputs (GPDIR[11:0] cleared in General Purpose I/O Data & Direction Register

(GPIO_DATA_DIR))

All GPIO interrupts are disabled (GPIO[11:0]_INT_EN cleared in General Purpose I/O Interrupt

Status and Enable Register (GPIO_INT_STS_EN)

All GPIO interrupts are configured to low logic level triggering (GPIO_INT_POL[11:0] cleared in

General Purpose I/O Configuration Register (GPIO_CFG))

Note: GPIO[7:0] may be configured as LED outputs by default, dependant on the LED_en_stap[7:0]

configuration straps. Refer to Section 13.3, "LED Operation" for additional information.

The direction and buffer type of all 12 GPIOs are configured via the General Purpose I/O Configuration

direction of each GPIO, input or output, should be configured first via its respective GPIO direction bit

(GPDIR[11:0]) in the General Purpose I/O Data & Direction Register (GPIO_DATA_DIR). When

configured as an output, the output buffer type for each GPIO is selected by the GPIOBUF[11:0] bits

in the General Purpose I/O Configuration Register (GPIO_CFG). Push/pull and open-drain output

buffers are supported for each GPIO. When functioning as an open-drain driver, the GPIO output pin

is driven low when the corresponding data register bit (GPIOD in the General Purpose I/O Data &

Direction Register (GPIO_DATA_DIR)) is cleared to 0, and is not driven when set to 1.

When a GPIO is enabled as an output, the value output to the GPIO pin is set via the corresponding

GPIOD[11:0] bit in the General Purpose I/O Data & Direction Register (GPIO_DATA_DIR). For GPIOs

configured as inputs, the corresponding GPIOD[11:0] bit reflects the current state of the GPIO input.

Note: For GPIO[9:8], the pin direction is a function of both the GPDIR[9:8] bits of the General

Purpose I/O Data & Direction Register (GPIO_DATA_DIR) and the 1588_GPIO_OE[9:8] bits in

the General Purpose I/O Configuration Register (GPIO_CFG).

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13.2.1

GPIO IEEE 1588 Timestamping

Two of the GPIO pins, GPIO[9:8], have the option to be used for IEEE 1588 time stamp functions. This

allows a time stamp capture to be triggered when the GPIO is configured as an input, or output a signal

from the GPIO based on an IEEE 1588 clock target compare event when configured as an output.

Refer to Chapter 11, "IEEE 1588 Hardware Time Stamp Unit," on page 154 for additional information

on the IEEE 1588 time stamping functions of the LAN9312.

13.2.1.1

IEEE 1588 GPIO Inputs

When the GPIO[9:8] pins are configured as inputs, an active edge will capture the IEEE 1588 clock

into the high and low 1588 capture registers (1588_CLOCK_HI_CAPTURE_GPIO_x, and

1588_CLOCK_LO_CAPTURE_GPIO_x where “x” represents the number of the respective 1588

enabled GPIO) and set the corresponding interrupt flags GPIO[9:8]_INT and 1588_GPIO[9:8]_INT in

the General Purpose I/O Interrupt Status and Enable Register (GPIO_INT_STS_EN) and 1588

Interrupt Status and Enable Register (1588_INT_STS_EN) respectively. The GPIO[9:8] inputs can also

be configured to clear the Clock Target interrupt (1588_TIMER_INT) in the 1588 Interrupt Status and

Enable

(1588_INT_STS_EN)

setting

the

corresponding

GPIO_1588_TIMER_INT_CLEAR_EN[9:8] bit in the General Purpose I/O Configuration Register

(GPIO_CFG). GPIO inputs must be active for greater than 40nS to be recognized as capture or

interrupt clear events.

13.2.1.2

IEEE 1588 GPIO Outputs

The GPIO[9:8] pins can be configured as IEEE 1588 enabled outputs by setting the corresponding

1588_GPIO_OE[9:8] bits in the General Purpose I/O Configuration Register (GPIO_CFG). These bits

override the GPDIR[9:8] bits of the General Purpose I/O Data & Direction Register (GPIO_DATA_DIR)

and allow for GPIO output generation based on the IEEE 1588 clock target compare event. Clock

target compare events occur when the value loaded into the 1588 Clock T a rget High-DWORD Register

(1588_CLOCK_TARGET_HI) and 1 588 Clock T a rget Low-DWORD Register

(1588_CLOCK_TARGET_LO) matches the current IEEE 1588 clock value in the 1588 Clock High-

DWORD Register (1588_CLOCK_HI) and 1588 Clock Low-DWORD Register (1588_CLOCK_LO).

Upon detection of a clock target compare event, GPIO[9:8] can be configured to output a 100nS pulse,

toggle its output, or reflect the 1588_TIMER_INT bit in the 1588 Interrupt Status and Enable Register

(1588_INT_STS_EN) by enabling the GPIO_EVENT_9 or GPIO_EVENT_8 bits of the 1588

Configuration Register (1588_CONFIG). The clock event polarity, which determines whether the IEEE

1588 GPIO output is active high or active low, is controlled via the GPIO_EVENT_POL_9 and

GPIO_EVENT_POL_8 bits of the General Purpose I/O Configuration Register (GPIO_CFG).

Note: The 1588_GPIO_OE[9:8] bits do not override the GPIO buffer type bits GPIOBUF[9:8] in the

General Purpose I/O Configuration Register (GPIO_CFG).

13.2.2

GPIO Interrupts

Each GPIO of the LAN9312 provides the ability to trigger a unique GPIO interrupt in the General

Purpose I/O Interrupt Status and Enable Register (GPIO_INT_STS_EN). Reading the GPIO_INT[11:0]

bits of this register provides the current status of the corresponding interrupt, and each interrupt is

enabled by setting the corresponding GPIO_INT_EN[11:0] bit. The GPIO/LED Controller aggregates

the enabled interrupt values into an internal signal which is sent to the System Interrupt Controller and

is reflected via the Interrupt Status Register (INT_STS) bit 12 (GPIO). For more information on the

LAN9312 interrupts, refer to Chapter 5, "System Interrupts," on page 49.

13.2.2.1

GPIO Interrupt Polarity

The interrupt polarity can be set for each individual GPIO via the GPIO_INT_POL[11:0] bits in the

General Purpose I/O Configuration Register (GPIO_CFG). When set, a high logic level on the GPIO

pin will set the corresponding interrupt bit in the General Purpose I/O Interrupt Status and Enable

corresponding interrupt bit. Because GPIO[9:8] have added IEEE 1588 functionality, the

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GPIO_INT_POL[9:8] bits also determine the polarity of the clock events as described in

Section 13.2.1.2.

13.2.2.2

IEEE 1588 GPIO Interrupts

In addition to the standard GPIO interrupts in the General Purpose I/O Interrupt Status and Enable

to generate and clear specific IEEE 1588 related interrupts. When GPIO 9 or GPIO 8 are enabled as

inputs and an active edge occurs, the IEEE 1588 clock capture is indicated by the 1588_GPIO9_INT

and 1588_GPIO8_INT interrupts respectively in the 1588 Interrupt Status and Enable Register

(1588_INT_STS_EN). These interrupts are enabled by setting the corresponding 1588_GPIO9_EN

and 1588_GPIO8_EN bits in the 1588 Interrupt Status and Enable Register (1588_INT_STS_EN).

GPIO inputs must be active for greater than 40nS to be recognized as capture events.

When GPIO 8 and GPIO 9 are enabled, the 1588 Timer Interrupt bit (1588_TIMER_INT) of the 1588

Interrupt Status and Enable Register (1588_INT_STS_EN) can be cleared by an active edge on

GPIO[9:8]. A clear is only registered when the GPIO input is active for greater than 40nS.

13.3

LED Operation

Eight pins, GPIO[7:0], are shared with LED functions (nP1LED[3:0] and nP2LED[3:0]). These pins are

configured as LED outputs by setting the corresponding LED_EN bit in the LED Configuration Register

(LED_CFG). When configured as a LED, the pin is an open-drain, active-low output and the GPIO

related input buffer and pull-up are disabled. The LED outputs are always active low. As a result, a

low signal on the LED pin equates to the LED “on”, and a high signal equates to the LED “off”.

The functions associated with each LED pin are configurable via the LED_FUN[1:0] bits of the LED

Configuration Register (LED_CFG). These bits allow the configuration of each LED pin to indicate

various port related functions. These functions are described in T a ble 13.1 followed by a detailed

definition of each indication type.

The default values of the LED_FUN[1:0] and LED_EN[7:0] bits of the LED Configuration Register

(LED_CFG) are determined by the LED_fun_strap[1:0] and LED_en_strap[7:0] configuration straps.

For more information on the LED Configuration Register (LED_CFG) and its related straps, refer to

Section 14.2.3.4, "LED Configuration Register (LED_CFG)," on page 196.

Table 13.1 LED Operation as a Function of LED_CFG[9:8]

LED_CFG[9:8] (LED_FUN[1:0])

00b

01b

10b

11b

nP2LED3

(GPIO7)

Port 0

Activity

Port 2

nP2LED2

(GPIO6)

Link / Activity

Port 2

100Link / Activity

Port 2

Link

Port 2

nP2LED1

(GPIO5)

Full-duplex / Collision

Port 2

Full-duplex / Collision Full-duplex / Collision

TXEN

Port 2

nP2LED0

(GPIO4)

Speed

Port 2

10Link / Activity

Port 2

Speed

Port 2

RXDV

Port 2

nP1LED3

(GPIO3)

Port 0

Activity

Port 1

TXEN

Port 0

nP1LED2

(GPIO2)

Link / Activity

Port 1

100Link / Activity

Port 1

Link

Port 1

RXDV

Port 0

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Table 13.1 LED Operation as a Function of LED_CFG[9:8] (continued)

LED_CFG[9:8] (LED_FUN[1:0])

nP1LED1

(GPIO1)

Full-duplex / Collision

Port 1

Full-duplex / Collision Full-duplex / Collision

TXEN

Port 1

nP1LED0

(GPIO0)

Speed

Port 1

10Link / Activity

Port 1

Speed

Port 1

RXDV

Port 1

The various LED indication functions shown in T a ble 13.1 are described below:

„

TX Port 0 - The signal is pulsed low for 80mS to indicate activity from the switch fabric to the Host

MAC. This signal is then driven high for a minimum of 80mS, after which the process will repeat if

TX activity is again detected.

RX Port 0 - The signal is pulsed low for 80mS to indicate activity from the Host MAC to the switch

fabric. This signal is then driven high for a minimum of 80mS, after which the process will repeat

if RX activity is again detected.

Link / Activity - A steady low output indicates that the port has a valid link, while a steady high

indicates no link on the port. The signal is pulsed high for 80mS to indicate transmit or receive

activity on the port. The signal is then driven low for a minimum of 80mS, after which the process

will repeat if RX or TX activity is again detected.

„

Full-duplex / Collision - A steady low output indicates the port is in full-duplex mode, while a

steady high indicates no link on the port. In half-duplex mode, the signal is pulsed low for 80mS

to indicate a network collision. The signal is then driven high for a minimum of 80mS, after which

the process will repeat if another collision is detected.

„

Speed - A steady low output indicates the selected speed is 100Mbps. A steady high output

indicates the selected speed is 10Mbps. The signal will be held high if the port does not have a

valid link.

100Link / Activity - A steady low output indicates the port has a valid link and the speed is

100Mbps. The signal is pulsed high for 80mS to indicate TX or RX activity on the port. The signal

is then driven low for a minimum of 80mS, after which the process will repeat if RX or TX activity

is again detected. The signal will be held high if the port does not have a valid link.

„

10Link / Activity - A steady low output indicates the port has a valid link and the speed is 10Mbps.

The signal is pulsed high for 80mS to indicate transmit or receive activity on the port. The signal

is then driven low for a minimum of 80mS, after which the process will repeat if RX or TX activity

is again detected. This signal will be held high if the port does not have a valid link.

Activity - The signal is pulsed low for 80mS to indicate transmit or receive activity. The signal is

then driven high for a minimum of 80mS, after which the process will repeat if RX or TX activity is

again detected. The signal will be held high if the port does not have a valid link.

„

Link - A steady low indicates the port has a valid link.

TXEN Port 0 - Non-stretched TXEN signal from the switch fabric to the Host MAC.

RXDV Port 0 - Non-stretched RXDV signal from the Host MAC to the switch fabric.

TXEN - Non-stretched TXEN signal from the switch fabric to the PHY.

RXDV - Non-stretched RXDV signal from the PHY to the switch fabric.

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Chapter 14 Register Descriptions

This section describes the various LAN9312 control and status registers (CSR’s). These registers are

broken into 5 categories. The following sections detail the functionality and accessibility of all the

LAN9312 registers within each category:

„

Section 14.1, "TX/RX FIFO Ports," on page 167

Section 14.2, "System Control and Status Registers," on page 168

Section 14.3, "Host MAC Control and Status Registers," on page 269

Section 14.4, "Ethernet PHY Control and Status Registers," on page 285

Section 14.5, "Switch Fabric Control and Status Registers," on page 307

Figure 14.1 contains an overall base register memory map of the LAN9312. This memory map is not

drawn to scale, and should be used for general reference only.

Note: Register bit type definitions are provided in Section 1.3, "Register Nomenclature," on page 19.

Note: Not all LAN9312 registers are memory mapped or directly addressable. For details on the

accessibility of the various LAN9312 registers, refer the register sub-sections listed above.

3FFh

...

RESERVED

2E0h

2DCh

Switch CSR Direct Data

...

Registers

200h

1DCh

Virtual PHY Registers

1C0h

1B0h

1ACh

Switch Interface Registers

19Ch

1588 Registers

100h

0A8h

0A4h

Host MAC Interface Registers

050h

04Ch

048h

044h

040h

03Ch

TX Status FIFO PEEK

TX Status FIFO Port

RX Status FIFO PEEK

RX Status FIFO Port

TX Data FIFO Port

& Alias Ports

020h

01Ch

RX Data FIFO Port

& Alias Ports

Base + 000h

Figure 14.1 LAN9312 Base Register Memory Map

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14.1

TX/RX FIFO Ports

The LAN9312 contains four host-accessible FIFO’s: TX Status, RX Status, TX Data, and RX Data.

These FIFO’s store the incoming and outgoing address and data information, acting as a conduit

between the host bus interface (HBI) and the Host MAC. The sizes of these FIFO’s are configurable

via the Hardware Configuration Register (HW_CFG). Refer to Section 9.7.3, "FIFO Memory Allocation

Configuration," on page 121 for additional information on FIFO size configuration.

For additional information on the FIFO configuration registers accessible via the Host Bus Interface,

refer to their respective register definitions located in section Section 14.2.2, "Host MAC & FIFO’s".

14.1.1

14.1.2

14.1.3

TX/RX Data FIFO’s

The TX and RX Data FIFO ports have the base address of 020h and 000h respectively. However, each

FIFO is also accessible at seven additional contiguous memory locations, as can be seen in

Figure 14.1. The Host may access the TX or RX Data FIFO’s at any of these alias port locations, as

they all function identically and contain the same data. This alias port addressing is implemented to

allow hosts to burst through sequential addresses.

TX/RX Status FIFO’s

The TX and RX Status FIFO’s can each be read from two register locations; the Status FIFO Port, and

the Status FIFO PEEK. The TX and RX Status FIFO Ports (048h and 040h respectively) will perform

a destructive read, popping the data from the TX or RX Status FIFO. The TX and RX Status FIFO

PEEK register locations (04Ch and 044h respectively) allow a non-destructive read of the top (oldest)

location of the FIFO’s.

Direct FIFO Access Mode

When the FIFO_SEL pin is driven high, the LAN9312 enters the direct FIFO access mode. In this

mode, all host write operations are to the TX Data FIFO and all host read operations are from the RX

Data FIFO. When FIFO_SEL is asserted, only the A[2] host address signal is decoded. All other

address signals are ignored in this mode. When the endianess select pin (END_SEL) is low, the TX/RX

Data FIFO’s are accessed in little endian mode. When END_SEL is high, the TX/RX Data FIFO’s are

accessed in big endian mode. The A[2] input is used during Data FIFO direct PIO burst cycles to

delimit DWORD accesses. For more information on endianess selection, refer to section Section 8.3,

"Host Endianess".

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14.2

System Control and Status Registers

The System CSR’s are directly addressable memory mapped registers with a base address offset

range of 050h to 2DCh. These registers are addressable by the Host via the Host Bus Interface (HBI).

T a ble 14.1 lists the System CSR’s and their corresponding addresses in order. All system CSR’s are

reset to their default value on the assertion of a chip-level reset.

The System CSR’s can be divided into 9 sub-categories. Each of these sub-categories contains the

System CSR descriptions of the associated registers. The register descriptions are categorized as

follows:

„

Section 14.2.1, "Interrupts," on page 172

Section 14.2.2, "Host MAC & FIFO’s," on page 180

Section 14.2.3, "GPIO/LED," on page 192

Section 14.2.4, "EEPROM," on page 197

Section 14.2.5, "IEEE 1588," on page 201

Section 14.2.6, "Switch Fabric," on page 229

Section 14.2.7, "PHY Management Interface (PMI)," on page 243

Section 14.2.8, "Virtual PH Y ," on page 245

Section 14.2.9, "Miscellaneous," on page 259

Table 14.1 System Control and Status Registers

ADDRESS

OFFSET

SYMBOL

ID_REV

IRQ_CFG

050h

054h

058h

05Ch

060h

064h

068h

06Ch

070h

074h

078h

07Ch

080h

084h

088h

08Ch

Chip ID and Revision Register, Section 14.2.9.1

Interrupt Configuration Register, Section 14.2.1.1

Interrupt Status Register, Section 14.2.1.2

Interrupt Enable Register, Section 14.2.1.3

Reserved for Future Use

INT_STS

INT_EN

RESERVED

BYTE_TEST

FIFO_INT

Byte Order Test Register, Section 14.2.9.2

FIFO Level Interrupts Register, Section 14.2.1.4

Receive Configuration Register, Section 14.2.2.1

Transmit Configuration Register, Section 14.2.2.2

Hardware Configuration Register, Section 14.2.9.3

RX Datapath Control Register, Section 14.2.2.3

Receive FIFO Information Register,Section 14.2.2.4

Transmit FIFO Information Register, Section 14.2.2.5

Power Management Control Register, Section 14.2.9.4

Reserved for Future Use

RX_CFG

TX_CFG

HW_CFG

RX_DP_CTRL

RX_FIFO_INF

TX_FIFO_INF

PMT_CTRL

RESERVED

GPT_CFG

General Purpose Timer Configuration Register,

Section 14.2.9.5

GPT_CNT

090h

General Purpose Timer Count Register, Section 14.2.9.6

Reserved for Future Use

RESERVED

094h - 098h

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Table 14.1 System Control and Status Registers (continued)

ADDRESS

OFFSET

SYMBOL

FREE_RUN

RX_DROP

09Ch

0A0h

Free Running Counter Register, Section 14.2.9.7

Host MAC RX Dropped Frames Counter Register,

Section 14.2.2.6

MAC_CSR_CMD

PMI_DATA

0A4h

Host MAC CSR Interface Command Register,

Section 14.2.2.7

0A4h

EEPROM

Loader

PHY Management Interface Data Register (EEPROM

Loader Access Only), Section 14.2.7.1

Access Only

MAC_CSR_DATA

PMI_ACCESS

0A8h

Host MAC CSR Interface Data Register, Section 14.2.2.8

0A8h

EEPROM

Loader

PHY Management Interface Access Register (EEPROM

Loader Access Only), Section 14.2.7.2

Access Only

AFC_CFG

0ACh

Host MAC Automatic Flow Control Configuration Register,

Section 14.2.2.9

RESERVED

0B0h - 0FCh

100h

Reserved for Future Use

1588_CLOCK_HI_RX_CAPTURE_1

Port 1 1588 Clock High-DWORD Receive Capture

1588_CLOCK_LO_RX_CAPTURE_1

1588_SEQ_ID_SRC_UUID_HI_RX_CAPTURE_1

1588_SRC_UUID_LO_RX_CAPTURE_1

1588_CLOCK_HI_TX_CAPTURE_1

104h

108h

10Ch

110h

114h

118h

11C

Port 1 1588 Clock Low-DWORD Receive Capture Register,

Section 14.2.5.2

Port 1 1588 Sequence ID, Source UUID High-WORD

Receive Capture Register, Section 14.2.5.3

Port 1 1588 Source UUID Low-DWORD Receive Capture

Port 1 1588 Clock High-DWORD Transmit Capture

1588_CLOCK_LO_TX_CAPTURE_1

Port 1 1588 Clock Low-DWORD Transmit Capture

1588_SEQ_ID_SRC_UUID_HI_TX_CAPTURE_1

1588_SRC_UUID_LO_TX_CAPTURE_1

1588_CLOCK_HI_RX_CAPTURE_2

Port 1 1588 Sequence ID, Source UUID High-WORD

Transmit Capture Register, Section 14.2.5.7

Port 1 1588 Source UUID Low-DWORD Transmit Capture

120h

124h

128h

12Ch

130h

134h

138h

Port 2 1588 Clock High-DWORD Receive Capture

1588_CLOCK_LO_RX_CAPTURE_2

Port 2 1588 Clock Low-DWORD Receive Capture Register,

Section 14.2.5.2

1588_SEQ_ID_SRC_UUID_HI_RX_CAPTURE_2

1588_SRC_UUID_LO_RX_CAPTURE_2

1588_CLOCK_HI_TX_CAPTURE_2

Port 2 1588 Sequence ID, Source UUID High-WORD

Receive Capture Register, Section 14.2.5.3

Port 2 1588 Source UUID Low-DWORD Receive Capture

Port 2 1588 Clock High-DWORD Transmit Capture

1588_CLOCK_LO_TX_CAPTURE_2

Port 2 1588 Clock Low-DWORD Transmit Capture

1588_SEQ_ID_SRC_UUID_HI_TX_CAPTURE_2

Port 2 1588 Sequence ID, Source UUID High-WORD

Transmit Capture Register, Section 14.2.5.7

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Table 14.1 System Control and Status Registers (continued)

ADDRESS

OFFSET

SYMBOL

1588_SRC_UUID_LO_TX_CAPTURE_2

13Ch

140h

144h

148h

14Ch

150h

154h

158h

15Ch

160h

164h

168h

16Ch

Port 2 1588 Source UUID Low-DWORD Transmit Capture

1588_CLOCK_HI_RX_CAPTURE_MII

1588_CLOCK_LO_RX_CAPTURE_MII

1588_SEQ_ID_SRC_UUID_HI_RX_CAPTURE_MII

1588_SRC_UUID_LO_RX_CAPTURE_MII

1588_CLOCK_HI_TX_CAPTURE_MII

Port 0 1588 Clock High-DWORD Receive Capture

Port 0 1588 Clock Low-DWORD Receive Capture Register,

Section 14.2.5.2

Port 0 1588 Sequence ID, Source UUID High-WORD

Receive Capture Register, Section 14.2.5.3

Port 0 1588 Source UUID Low-DWORD Receive Capture

Port 0 1588 Clock High-DWORD Transmit Capture

1588_CLOCK_LO_TX_CAPTURE_MII

1588_SEQ_ID_SRC_UUID_HI_TX_CAPTURE_MII

1588_SRC_UUID_LO_TX_CAPTURE_MII

1588_CLOCK_HI_CAPTURE_GPIO_8

1588_CLOCK_LO_CAPTURE_GPIO_8

1588_CLOCK_HI_CAPTURE_GPIO_9

1588_CLOCK_LO_CAPTURE_GPIO_9

Port 0 1588 Clock Low-DWORD Transmit Capture

Port 0 1588 Sequence ID, Source UUID High-WORD

Transmit Capture Register, Section 14.2.5.7

Port 0 1588 Source UUID Low-DWORD Transmit Capture

GPIO 8 1588 Clock High-DWORD Capture Register,

Section 14.2.5.9

GPIO 8 1588 Clock Low-DWORD Capture Register,

Section 14.2.5.10

GPIO 9 1588 Clock High-DWORD Capture Register,

Section 14.2.5.11

GPIO 9 1588 Clock Low-DWORD Capture Register,

Section 14.2.5.12

1588_CLOCK_HI

1588_CLOCK_LO

170h

174h

178h

17Ch

1588 Clock High-DWORD Register, Section 14.2.5.13

1588 Clock Low-DWORD Register, Section 14.2.5.14

1588 Clock Addend Register, Section 14.2.5.15

1588_CLOCK_ADDEND

1588_CLOCK_TARGET_HI

1588 Clock Target High-DWORD Register,

Section 14.2.5.16

1588_CLOCK_TARGET_LO

1588_CLOCK_TARGET_RELOAD_HI

1588_CLOCK_TARGET_RELOAD_LO

1588_AUX_MAC_HI

180h

184h

188h

18Ch

190h

1588 Clock Target Low-DWORD Register,

Section 14.2.5.17

1588 Clock Target Reload High-DWORD Register,

Section 14.2.5.18

1588 Clock Target Reload/Add Low-DWORD Register,

Section 14.2.5.19

1588 Auxiliary MAC Address High-WORD Register,

Section 14.2.5.20

1588_AUX_MAC_LO

1588 Auxiliary MAC Address Low-DWORD Register,

Section 14.2.5.21

1588_CONFIG

1588_INT_STS_EN

1588_CMD

194h

198h

19Ch

1588 Configuration Register, Section 14.2.5.22

1588 Interrupt Status Enable Register, Section 14.2.5.23

1588 Command Register, Section 14.2.5.24

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Table 14.1 System Control and Status Registers (continued)

ADDRESS

OFFSET

SYMBOL

MANUAL_FC_1

MANUAL_FC_2

1A0h

1A4h

1A8h

1ACh

Port 1 Manual Flow Control Register, Section 14.2.6.1

Port 2 Manual Flow Control Register, Section 14.2.6.2

Port 0 Flow Control Register, Section 14.2.6.3

MANUAL_FC_MII

SWITCH_CSR_DATA

Switch Fabric CSR Interface Data Register,

Section 14.2.6.4

SWITCH_CSR_CMD

1B0h

Switch Fabric CSR Interface Command Register,

Section 14.2.6.5

E2P_CMD

E2P_DATA

1B4h

1B8h

1BCh

1C0h

1C4h

1C8h

1CCh

1D0h

EEPROM Command Register, Section 14.2.4.1

EEPROM Data Register, Section 14.2.4.2

LED_CFG

LED Configuration Register, Section 14.2.3.4

VPHY_BASIC_CTRL

VPHY_BASIC_STATUS

VPHY_ID_MSB

VPHY_ID_LSB

VPHY_AN_ADV

Virtual PHY Basic Control Register, Section 14.2.8.1

Virtual PHY Basic Status Register, Section 14.2.8.2

Virtual PHY Identification MSB Register, Section 14.2.8.3

Virtual PHY Identification LSB Register, Section 14.2.8.4

Virtual PHY Auto-Negotiation Advertisement Register,

Section 14.2.8.5

VPHY_AN_LP_BASE_ABILITY

VPHY_AN_EXP

1D4h

1D8h

1DCh

1E0h

1E4h

1E8h

Virtual PHY Auto-Negotiation Link Partner Base Page

Ability Register, Section 14.2.8.6

Virtual PHY Auto-Negotiation Expansion Register,

Section 14.2.8.7

VPHY_SPECIAL_CONTROL_STATUS

GPIO_CFG

Virtual PHY Special Control/Status Register,

Section 14.2.8.8

General Purpose I/O Configuration Register,

Section 14.2.3.1

GPIO_DATA_DIR

General Purpose I/O Data & Direction Register,

Section 14.2.3.2

GPIO_INT_STS_EN

General Purpose I/O Interrupt Status and Enable Register,

Section 14.2.3.3

RESERVED

SWITCH_MAC_ADDRH

SWITCH_MAC_ADDRL

RESET_CTL

1ECh

1F0h

Reserved for Future Use

Switch MAC Address High Register, Section 14.2.6.6

Switch MAC Address Low Register, Section 14.2.6.7

Reset Control Register, Section 14.2.9.8

Reserved for Future Use

1F4h

1F8h

RESERVED

1FCh

SWITCH_CSR_DIRECT_DATA

200h-2DCh

Switch Engine CSR Interface Direct Data Register,

Section 14.2.6.8

RESERVED

2E0h-3FFh

Reserved for Future Use

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14.2.1

Interrupts

This section details the interrupt related System CSR’s. These registers control, configure, and monitor

the IRQ interrupt output pin and the various LAN9312 interrupt sources. For more information on the

LAN9312 interrupts, refer to Chapter 5, "System Interrupts," on page 49.

14.2.1.1

Interrupt Configuration Register (IRQ_CFG)

Offset:

054h

Size:

32 bits

This read/write register configures and indicates the state of the IRQ signal.

BITS

DESCRIPTION

TYPE

DEFAULT

31:24

Interrupt De-assertion Interval (INT_DEAS)

This field determines the Interrupt Request De-assertion Interval in multiples

of 10 microseconds.

R/W

00h

Setting this field to zero causes the device to disable the INT_DEAS Interval,

reset the interval counter and issue any pending interrupts. If a new, non-

zero value is written to this field, any subsequent interrupts will obey the new

setting.

This field does not apply to the PME_INT interrupt.

23:15

RESERVED

Interrupt De-assertion Interval Clear (INT_DEAS_CLR)

Writing a 1 to this register clears the de-assertion counter in the Interrupt

Controller, thus causing a new de-assertion interval to begin (regardless of

whether or not the Interrupt Controller is currently in an active de-assertion

interval).

R/W

0: Normal operation

1: Clear de-assertion counter

Interrupt De-assertion Status (INT_DEAS_STS)

When set, this bit indicates that interrupts are currently in a de-assertion

interval, and will not be sent to the IRQ pin. When this bit is clear, interrupts

are not currently in a de-assertion interval, and will be sent to the IRQ pin.

0: No interrupts in de-assertion interval

1: Interrupts in de-assertion interval

Master Interrupt (IRQ_INT)

This read-only bit indicates the state of the internal IRQ line, regardless of

the setting of the IRQ_EN bit, or the state of the interrupt de-assertion

function. When this bit is set, one of the enabled interrupts is currently

active.

0: No enabled interrupts active

1: One or more enabled interrupts active

11:9

RESERVED

IRQ Enable (IRQ_EN)

R/W

This bit controls the final interrupt output to the IRQ pin. When clear, the IRQ

output is disabled and permanently de-asserted. This bit has no effect on

any internal interrupt status bits.

0: Disable output on IRQ pin

1: Enable output on IRQ pin

7:5

RESERVED

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BITS

DESCRIPTION

TYPE

DEFAULT

IRQ Polarity (IRQ_POL)

R/W

NASR

Note 14.1

When cleared, this bit enables the IRQ line to function as an active low

output. When set, the IRQ output is active high. When the IRQ is configured

as an open-drain output (via the IRQ_TYPE bit), this bit is ignored, and the

interrupt is always active low.

0: IRQ active low output

1: IRQ active high output

3:1

RESERVED

IRQ Buffer Type (IRQ_TYPE)

R/W

NASR

Note 14.1

When this bit is cleared, the IRQ pin functions as an open-drain output for

use in a wired-or interrupt configuration. When set, the IRQ is a push-pull

driver.

Note:

When configured as an open-drain output, the IRQ_POL bit is

ignored and the interrupt output is always active low.

0: IRQ pin open-drain output

1: IRQ pin push-pull driver

Note 14.1 Register bits designated as NASR are not reset when either the SRST bit in the Hardware

Configuration Register (HW_CFG) register or the DIGITAL_RST bit in the Reset Control

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14.2.1.2

Interrupt Status Register (INT_STS)

Offset:

058h

Size:

32 bits

This register contains the current status of the generated interrupts. A value of 1 indicates the

corresponding interrupt conditions have been met, while a value of 0 indicates the interrupt conditions

have not been met. The bits of this register reflect the status of the interrupt source regardless of

whether the source has been enabled as an interrupt in the Interrupt Enable Register (INT_EN). Where

indicated as R/WC, writing a 1 to the corresponding bits acknowledges and clears the interrupt.

BITS

DESCRIPTION

Software Interrupt (SW_INT)

This interrupt is generated when the SW_INT_EN bit of the Interrupt Enable

TYPE

DEFAULT

R/WC

Device Ready (READY)

R/WC

This interrupt indicates that the LAN9312 is ready to be accessed after a

power-up or reset condition.

1588 Interrupt Event (1588_EVNT)

This bit indicates an interrupt event from the IEEE 1588 module. This bit

should be used in conjunction with the 1588 Interrupt Status and Enable

event within the 1588 module.

Switch Fabric Interrupt Event (SWITCH_INT)

This bit indicates an interrupt event from the Switch Fabric. This bit should

be used in conjunction with the Switch Global Interrupt Pending Register

(SW_IPR) to determine the source of the interrupt event within the Switch

Fabric.

Port 2 PHY Interrupt Event (PHY_INT2)

This bit indicates an interrupt event from the Port 2 PHY. The source of the

interrupt can be determined by polling the Port x PHY Interrupt Source

Flags Register (PHY_INTERRUPT_SOURCE_x).

Port 1 PHY Interrupt Event (PHY_INT1)

This bit indicates an interrupt event from the Port 1 PHY. The source of the

interrupt can be determined by polling the Port x PHY Interrupt Source

Flags Register (PHY_INTERRUPT_SOURCE_x).

TX Stopped (TXSTOP_INT)

This interrupt is issued when STOP_TX bit in Transmit Configuration

R/WC

RX Stopped (RXSTOP_INT)

R/WC

This interrupt is issued when the Host MAC receiver is halted.

RX Dropped Frame Counter Halfway (RXDFH_INT)

This interrupt is issued when the Host MAC RX Dropped Frames Counter

80000000h).

RESERVED

TX IOC Interrupt (TX_IOC)

This interrupt is generated when a buffer with the IOC flag set has been

fully loaded into the TX Data FIFO.

R/WC

RX DMA Interrupt (RXD_INT)

R/WC

This interrupt is issued when the amount of data programmed in the RX

DMA Count (RX_DMA_CNT) field of the Receive Configuration Register

(RX_CFG) has been transferred out of the RX Data FIFO.

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BITS

DESCRIPTION

TYPE

DEFAULT

GP Timer (GPT_INT)

This interrupt is issued when the General Purpose Timer Count Register

(GPT_CNT) wraps past zero to FFFFh.

R/WC

RESERVED

Power Management Interrupt Event (PME_INT)

R/WC

This interrupt is issued when a Power Management Event is detected as

configured in the Power Management Control Register (PMT_CTRL). This

interrupt functions independent of the PME signal, and will still function if

the PME signal is disabled. Writing a '1' clears this bit regardless of the

state of the PME hardware signal. In order to clear this bit, all unmasked

bits in the Power Management Control Register (PMT_CTRL) must first be

cleared.

Note:

The Interrupt De-assertion interval does not apply to the PME

interrupt.

TX Status FIFO Overflow (TXSO)

R/WC

This interrupt is generated when the TX Status FIFO overflows.

Receive Watchdog Time-out (RWT)

This interrupt is generated when a packet larger than 2048 bytes has been

received by the Host MAC.

Note:

This can occur when the switch engine adds a tag to a non-tagged

jumbo packet that is originally larger than 2044 bytes.

Receiver Error (RXE)

R/WC

Indicates that the Host MAC receiver has encountered an error. Please

refer to Section 9.9.5, "Receiver Errors," on page 136 for a description of

the conditions that will cause an RXE.

Transmitter Error (TXE)

When generated, indicates that the Host MAC transmitter has encountered

an error. Please refer to Section 9.8.7, "Transmitter Errors," on page 131

for a description of the conditions that will cause a TXE.

GPIO Interrupt Event (GPIO)

This bit indicates an interrupt event from the General Purpose I/O. The

source of the interrupt can be determined by polling the General Purpose

I/O Interrupt Status and Enable Register (GPIO_INT_STS_EN)

RESERVED

TX Data FIFO Overrun Interrupt (TDFO)

This interrupt is generated when the TX Data FIFO is full, and another write

is attempted.

R/WC

TX Data FIFO Available Interrupt (TDFA)

R/WC

This interrupt is generated when the TX Data FIFO available space is

greater than the programmed level in the TX Data Available Level field of

the FIFO Level Interrupt Register (FIFO_INT).

TX Status FIFO Full Interrupt (TSFF)

R/WC

This interrupt is generated when the TX Status FIFO is full.

TX Status FIFO Level Interrupt (TSFL)

This interrupt is generated when the TX Status FIFO reaches the

programmed level in the TX Status Level field of the FIFO Level Interrupt

RX Dropped Frame Interrupt (RXDF_INT)

R/WC

This interrupt is issued whenever a receive frame is dropped by the Host

MAC.

RESERVED

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BITS

DESCRIPTION

TYPE

DEFAULT

RX Status FIFO Full Interrupt (RSFF)

This interrupt is generated when the RX Status FIFO is full.

R/WC

RX Status FIFO Level Interrupt (RSFL)

R/WC

This interrupt is generated when the RX Status FIFO reaches the

programmed level in the RX Status Level field of the FIFO Level Interrupt

2:0

RESERVED

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14.2.1.3

Interrupt Enable Register (INT_EN)

Offset:

05Ch

Size:

32 bits

This register contains the interrupt enables for the IRQ output pin. Writing 1 to any of the bits enables

the corresponding interrupt as a source for IRQ. Bits in the Interrupt Status Register (INT_STS) register

will still reflect the status of the interrupt source regardless of whether the source is enabled as an

interrupt in this register (with the exception of SW_INT_EN). For descriptions of each interrupt, refer

to the Interrupt Status Register (INT_STS) bits, which mimic the layout of this register.

BITS

DESCRIPTION

TYPE

DEFAULT

Software Interrupt Enable (SW_INT_EN)

R/W

Device Ready Enable (READY_EN)

1588 Interrupt Event Enable (1588_EVNT_EN)

Switch Engine Interrupt Event Enable (SWITCH_INT_EN)

Port 2 PHY Interrupt Event Enable (PHY_INT2_EN)

Port 1 PHY Interrupt Event Enable (PHY_INT1_EN)

TX Stopped Interrupt Enable (TXSTOP_INT_EN)

RX Stopped Interrupt Enable (RXSTOP_INT_EN)

RX Dropped Frame Counter Halfway Interrupt Enable

(RXDFH_INT_EN)

RESERVED

TX IOC Interrupt Enable (TIOC_INT_EN)

R/W

RX DMA Interrupt Enable (RXD_INT_EN)

GP Timer Interrupt Enable (GPT_INT_EN)

RESERVED

Power Management Event Interrupt Enable (PME_INT_EN)

TX Status FIFO Overflow Interrupt Enable (TXSO_EN)

Receive Watchdog Time-out Interrupt Enable (RWT_INT_EN)

Receiver Error Interrupt Enable (RXE_INT_EN)

Transmitter Error Interrupt Enable (TXE_INT_EN)

GPIO Interrupt Event Enable (GPIO_EN)

R/W

RESERVED - This bit must be written with 0b for proper operation.

TX Data FIFO Overrun Interrupt Enable (TDFO_EN)

TX Data FIFO Available Interrupt Enable (TDFA_EN)

TX Status FIFO Full Interrupt Enable (TSFF_EN)

TX Status FIFO Level Interrupt Enable (TSFL_EN)

RX Dropped Frame Interrupt Enable (RXDF_INT_EN)

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BITS

DESCRIPTION

TYPE

DEFAULT

RESERVED - This bit must be written with 0b for proper operation.

RX Status FIFO Full Interrupt Enable (RSFF_EN)

RX Status FIFO Level Interrupt Enable (RSFL_EN)

RESERVED

R/W

2:0

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14.2.1.4

FIFO Level Interrupt Register (FIFO_INT)

Offset:

068h

Size:

32 bits

This read/write register configures the limits where the RX/TX Data and Status FIFO’s will generate

system interrupts.

BITS

DESCRIPTION

TYPE

DEFAULT

31:24

TX Data Available Level

R/W

48h

The value in this field sets the level, in number of 64 Byte blocks, at which

the TX Data FIFO Available Interrupt (TDFA) will be generated. When the

TX Data FIFO free space is greater than this value, a TX Data FIFO

Available Interrupt (TDFA) will be generated in the Interrupt Status Register

(INT_STS).

23:16

TX Status Level

R/W

00h

The value in this field sets the level, in number of DWORD’s, at which the

TX Status FIFO Level Interrupt (TSFL) will be generated. When the TX

Status FIFO used space is greater than this value, a TX Status FIFO Level

Interrupt (TSFL) will be generated in the Interrupt Status Register

(INT_STS).

15:8

7:0

RESERVED - This field must be written with 00h for proper operation.

R/W

00h

RX Status Level

The value in this field sets the level, in number of DWORD’s, at which the

RX Status FIFO Level Interrupt (RSFL) will be generated. When the RX

Status FIFO used space is greater than this value, a RX Status FIFO Level

Interrupt (RSFL) will be generated in the Interrupt Status Register

(INT_STS).

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14.2.2

Host MAC & FIFO’s

This section details the Host MAC and TX/RX FIFO related System CSR’s.

These Host Bus Interface accessible registers allow for the configuration of the TX/RX FIFO’s, Host

MAC and indirect access to the complete set of Host MAC CSR’s. The Host MAC CSR’s are

accessible through the Host Bus Interface via the Host MAC CSR Interface Command Register

(MAC_CSR_CMD) and Host MAC CSR Interface Data Register (MAC_CSR_DATA).

Note: For more information on the TX/RX FIFO’s, refer to Section 14.1, "TX/RX FIFO Ports".

Note: The full list of Host MAC CSR’s are described in Section 14.3, "Host MAC Control and Status

Registers," on page 269. For more information on the Host MAC, refer to Chapter 9, "Host

MAC," on page 112.

14.2.2.1

Receive Configuration Register (RX_CFG)

Offset:

06Ch

Size:

32 bits

This register controls the Host MAC receive engine.

BITS

DESCRIPTION

TYPE

DEFAULT

31:30

RX End Alignment (RX_EA)

R/W

00b

This field specifies the alignment that must be maintained on the last data

transfer of a buffer. The LAN9312 will add extra DWORD’s of data up to

the alignment specified in the table below. The host is responsible for

removing these extra DWORD’s. This mechanism can be used to maintain

cache line alignment on host processors.

BIT

VALUES

[31:30]

END ALIGNMENT

4-Byte Alignment

16-Byte Alignment

32-Byte Alignment

RESERVED

Note:

The desired RX End Alignment must be set before reading a

packet. The RX End Alignment can be changed between reading

receive packets, but must not be changed if the packet is partially

read.

29:28

27:16

RESERVED

RX DMA Count (RX_DMA_CNT)

R/W

000h

This 12-bit field indicates the amount of data, in DWORD’s, to be

transferred out of the RX Data FIFO before asserting the RX DMA Interrupt

(RXD_INT). After being set, this field is decremented for each DWORD of

data that is read from the RX Data FIFO. This field can be overwritten with

a new value before it reaches zero.

Force RX Discard (RX_DUMP)

When a 1 is written to this bit, the RX Data and Status FIFO’s are cleared

of all pending data and the RX data and status pointers are cleared to zero.

Note:

Please refer to Section 9.9.1.2, "Force Receiver Discard (Receiver

Dump)," on page 134 for a detailed description regarding the use

of RX_DUMP.

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BITS

DESCRIPTION

TYPE

DEFAULT

14:13

12:8

RESERVED

RX Data Offset (RXDOFF)

R/W

00000b

This field controls the offset value, in bytes, that is added to the beginning

of an RX data packet. The start of the valid data will be shifted by the

number of bytes specified in this field. An offset of 0-31 bytes is a valid

number of offset bytes.

Note:

The two LSBs of this field (D[9:8]) must not be modified while the

RX is running. The receiver must be halted, and all data purged

before these two bits can be modified. The upper three bits

(DWORD offset) may be modified while the receiver is running.

Modifications to the upper bits will take affect on the next DWORD

read.

7:0

RESERVED

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14.2.2.2

Transmit Configuration Register (TX_CFG)

Offset:

070h

Size:

32 bits

This register controls the Host MAC transmit functions.

BITS

31:16

DESCRIPTION

TYPE

DEFAULT

RESERVED

Force TX Status Discard (TXS_DUMP)

When a 1 is written to this bit, the TX Status FIFO is cleared of all pending

status DWORD’s and the TX status pointers are cleared to zero.

Force TX Data Discard (TXD_DUMP)

When a 1 is written to this bit, the TX Data FIFO is cleared of all pending

data and the TX data pointers are cleared to zero.

13:3

RESERVED

TX Status Allow Overrun (TXSAO)

R/W

When this bit is cleared, Host MAC data transmission is suspended if the

TX Status FIFO becomes full. Setting this bit high allows the transmitter to

continue operation with a full TX Status FIFO.

Note:

This bit does not affect the operation of the TX Status FIFO Full

Interrupt (TSFF).

Transmitter Enable (TX_ON)

R/W

When this bit is set, the Host MAC transmitter is enabled. Any data in the

TX Data FIFO will be sent. This bit is cleared automatically when the

STOP_TX bit is set and the transmitter is halted.

Stop Transmitter (STOP_TX)

R/W

When this bit is set, the Host MAC transmitter will finish the current frame,

and will then stop transmitting. When the transmitter has stopped this bit will

clear. All writes to this bit are ignored while this bit is high.

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14.2.2.3

Receive Datapath Control Register (RX_DP_CTRL)

Offset:

078h

Size:

32 bits

This register is used to discard unwanted receive frames.

BITS

DESCRIPTION

TYPE

DEFAULT

RX Data FIFO Fast Forward (RX_FFWD)

R/W

Writing a 1 to this bit causes the RX Data FIFO to fast-forward to the start

of the next frame. This bit will remain high until the RX Data FIFO fast-

forward operation has completed. No reads should be issued to the RX Data

FIFO while this bit is high.

Note:

Please refer to section Section 9.9.1.1, "Receive Data FIFO Fast

Forward," on page 134 for detailed information regarding the use

of RX_FFWD.

30:0

RESERVED

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14.2.2.4

RX FIFO Information Register (RX_FIFO_INF)

Offset:

07Ch

Size:

32 bits

This register contains the indication of used space in the RX FIFO’s.

BITS

31:24

23:16

DESCRIPTION

TYPE

DEFAULT

RESERVED

RX Status FIFO Used Space (RXSUSED)

This field indicates the amount of space, in DWORD’s, currently used in the

RX Status FIFO.

15:0

RX Data FIFO Used Space (RXDUSED)

This field indicates the amount of space, in bytes, used in the RX Data FIFO.

For each receive frame, the field is incremented by the length of the receive

data. In cases where the payload does not end on a DWORD boundary, the

total will be rounded up to the nearest DWORD.

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14.2.2.5

TX FIFO Information Register (TX_FIFO_INF)

Offset:

080h

Size:

32 bits

This register contains the indication of free space in the TX Data FIFO and the used space in the TX

Status FIFO.

BITS

31:24

23:16

DESCRIPTION

TYPE

DEFAULT

RESERVED

TX Status FIFO Used Space (TXSUSED)

This field indicates the amount of space, in DWORD’s, currently used in the

TX Status FIFO.

15:0

TX Data FIFO Free Space (TXFREE)

1200h

This field indicates the amount of space, in bytes, available in the TX Data

FIFO. The application should never write more than is available, as indicated

by this value.

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14.2.2.6

Host MAC RX Dropped Frames Counter Register (RX_DROP)

Offset:

0A0h

Size:

32 bits

This register indicates the number of receive frames that have been dropped by the Host MAC.

BITS

DESCRIPTION

RX Dropped Frame Counter (RX_DFC)

This counter is incremented every time a receive frame is dropped by the

Host MAC. RX_DFC is cleared on any read of this register.

TYPE

DEFAULT

31:0

00000000h

Note:

The interrupt RXDFH_INT (bit 23 of the Interrupt Status Register

(INT_STS)) can be issued when this counter passes through its

halfway point (7FFFFFFFh to 80000000h).

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14.2.2.7

Host MAC CSR Interface Command Register (MAC_CSR_CMD)

Offset:

0A4h

Size:

32 bits

This read-write register is used to control the read and write operations to/from the Host MAC. This

indirectly access the Host MAC CSR’s.

Note: The full list of Host MAC CSR’s are described in Section 14.3, "Host MAC Control and Status

Registers," on page 269. For more information on the Host MAC, refer to Chapter 9, "Host

MAC," on page 112.

BITS

DESCRIPTION

TYPE

DEFAULT

CSR Busy

R/W

When a 1 is written into this bit, the read or write operation is performed to

the specified Host MAC CSR. This bit will remain set until the operation is

complete. In the case of a read, this indicates that the host can read valid

data from the Host MAC CSR Interface Data Register (MAC_CSR_DATA).

Note:

The MAC_CSR_CMD and MAC_CSR_DATA registers must not be

modified until this bit is cleared.

R/nW

R/W

When set, this bit indicates that the host is requesting a read operation.

When clear, the host is performing a write.

0: Host MAC CSR Write Operation

1: Host MAC CSR Read Operation

29:8

7:0

RESERVED

CSR Address

R/W

00h

The 8-bit value in this field selects which Host MAC CSR will be accessed

by the read or write operation. The index of each Host MAC CSR is defined

in Section 14.3, "Host MAC Control and Status Registers," on page 269.

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14.2.2.8

Host MAC CSR Interface Data Register (MAC_CSR_DATA)

Offset:

0A8h

Size:

32 bits

This read-write register is used in conjunction with the Host MAC CSR Interface Command Register

(MAC_CSR_CMD) to indirectly access the Host MAC CSR’s.

Note: The full list of Host MAC CSR’s are described in Section 14.3, "Host MAC Control and Status

Registers," on page 269. For more information on the Host MAC, refer to Chapter 9, "Host

MAC," on page 112.

BITS

DESCRIPTION

TYPE

DEFAULT

31:0

Host MAC CSR Data

R/W

00000000h

This field contains the value read from or written to the Host MAC CSR as

specified in the Host MAC CSR Interface Command Register

(MAC_CSR_CMD). Upon a read, the value returned depends on the R/nW

bit in the MAC_CSR_CMD register. If R/nW is a 1, the data in this register

is from the Host MAC. If R/nW is 0, the data is the value that was last written

into this register.

Note:

The MAC_CSR_CMD and MAC_CSR_DATA registers must not be

modified until the CSR Busy bit is cleared in the MAC_CSR_CMD

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14.2.2.9

Host MAC Automatic Flow Control Configuration Register (AFC_CFG)

Offset:

0ACh

Size:

32 bits

This read/write register configures the mechanism that controls the automatic and software-initiated

transmission of pause frames and back pressure from the Host MAC to the switch fabric. This register

is used in conjunction with the Host MAC Flow Control Register (HMAC_FLOW) in the Host MAC CSR

space. Pause frames and backpressure are sent to the switch fabric to stop it from sending packets

to the Host MAC. Network data into the switch fabric is affected only if the switch fabric buffering fills.

Note: The Host MAC will not transmit pause frames or assert back pressure if the transmitter is

disabled. This register controls only the Host MAC flow control and not the Switch Engine

MAC’s flow control.

Refer to section Section 9.2, "Flow Control" for additional information.

BITS

DESCRIPTION

TYPE

DEFAULT

31:24

23:16

RESERVED

Automatic Flow Control High Level (AFC_HI)

R/W

00h

This field specifies, in multiples of 64 bytes, the level at which flow control

will trigger. When this limit is reached, the chip will apply back pressure or

will transmit a pause frame as programmed in bits [3:0] of this register.

During full-duplex operation only a single pause frame is transmitted when

this level is reached. The pause time transmitted in this frame is

programmed in the FCPT field of the Host MAC Flow Control Register

(HMAC_FLOW) in the Host MAC CSR space.

During half-duplex operation each incoming frame that matches the criteria

in bits [3:0] of this register will be jammed for the period set in the

BACK_DUR field.

Note:

This level is also used for hard-wired flow control when

HW_FC_EN is set in the Port 0(Host MAC) Manual Flow Control

15:8

Automatic Flow Control Low Level (AFC_LO)

R/W

00h

This field specifies, in multiples of 64 bytes, the level at which a pause frame

is transmitted with a pause time setting of zero. When the amount of data

in the RX Data FIFO falls below this level the pause frame is transmitted. A

pause time value of zero instructs the other transmitting device to

immediately resume transmission. The zero time pause frame will only be

transmitted if the RX Data FIFO had reached the AFC_HI level and a pause

frame was sent. A zero pause time frame is sent whenever automatic flow

control in enabled in bits [3:0] of this register.

Note:

When automatic flow control is enabled the AFC_LO setting must

always be less than the AFC_HI setting.

Note:

This level is also used for hard-wired flow control when

HW_FC_EN is set in the Port 0(Host MAC) Manual Flow Control

7:4

Backpressure Duration (BACK_DUR)

R/W

When the Host MAC automatically asserts back pressure, it will be asserted

for this period of time. In full-duplex mode, this field has no function and is

not used. Please refer to T a ble 14.2, describing Backpressure Duration bit

mapping for more information.

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BITS

DESCRIPTION

TYPE

DEFAULT

Flow Control on Multicast Frame (FCMULT)

R/W

When this bit is set, the Host MAC will assert back pressure when the AFC

level is reached and a multicast frame is received. This field has no function

in full-duplex mode.

0: Flow Control on Multicast Frame Disabled

1: Flow Control on Multicast Frame Enabled

Flow Control on Broadcast Frame (FCBRD)

R/W

When this bit is set, the Host MAC will assert back pressure when the AFC

level is reached and a broadcast frame is received. This field has no function

in full-duplex mode.

0: Flow Control on Broadcast Frame Disabled

1: Flow Control on Broadcast Frame Enabled

Flow Control on Address Decode (FCADD)

When this bit is set, the Host MAC will assert back pressure when the AFC

level is reached and a frame addressed to the Host MAC is received. This

field has no function in full-duplex mode.

0: Flow Control on Address Decode Disabled

1: Flow Control on Address Decode Enabled

Flow Control on Any Frame (FCANY)

When this bit is set, the Host MAC will assert back pressure, or transmit a

pause frame when the AFC level is reached and any frame is received.

Setting this bit enables full-duplex flow control when the Host MAC is

operating in full-duplex mode.

When this mode is enabled during half-duplex operation, the Flow Controller

does not decode the Host MAC address and will send a JAM upon receipt

of a valid preamble (i.e., immediately at the beginning of the next frame after

the RX Data FIFO level is reached).

When this mode is enabled during full-duplex operation, the Flow Controller

will immediately instruct the Host MAC to send a pause frame when the RX

Data FIFO level is reached. The MAC will queue the pause frame

transmission for the next available window.

Setting this bit overrides bits [3:1] of this register.

Table 14.2 Backpressure Duration Bit Mapping

BACKPRESSURE DURATION

[7:4]

100Mbs Mode

5uS

10Mbs Mode

7.2uS

10uS

12.2uS

15uS

17.2uS

25uS

27.2uS

50uS

52.2uS

100uS

150uS

200uS

102.2uS

152.2uS

202.2uS

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Table 14.2 Backpressure Duration Bit Mapping (continued)

BACKPRESSURE DURATION

250uS

300uS

350uS

400uS

450uS

500uS

550uS

600uS

252.2uS

302.2uS

352.2uS

402.2uS

452.2uS

502.2uS

552.2uS

602.2uS

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14.2.3

GPIO/LED

This section details the General Purpose I/O (GPIO) and LED related System CSR’s.

14.2.3.1

General Purpose I/O Configuration Register (GPIO_CFG)

Offset:

1E0h

Size:

32 bits

This read/write register configures the GPIO input and output pins. The polarity of the 12 GPIO pins

is configured here as well as the IEEE 1588 timestamping and clock compare event output properties

of the GPIO[9:8] pins.

BITS

DESCRIPTION

TYPE

DEFAULT

31:30

29:28

RESERVED

GPIO 1588 Timer Interrupt Clear Enable 9-8

(GPIO_1588_TIMER_INT_CLEAR_EN[9:8])

R/W

00b

These bits enable inputs on GPIO9 and GPIO8 to clear the

1588_TIMER_INT bit of the 1588 Interrupt Status and Enable Register

(1588_INT_STS_EN). The polarity of these inputs is determined by

GPIO_INT_POL[9:8].

Note:

The GPIO must be configured as an input for this function to

operate. For the clear function, GPIO inputs are edge sensitive and

must be active for greater than 40 nS to be recognized.

27:16

GPIO Interrupt Polarity 11-0 (GPIO_INT_POL[11:0])

R/W

These bits set the interrupt polarity of the 12 GPIO pins. The configured

level (high/low) will set the corresponding GPIO_INT bit in the General

Purpose I/O Interrupt Status and Enable Register (GPIO_INT_STS_EN).

0: Sets low logic level trigger on corresponding GPIO pin

1: Sets high logic level trigger on corresponding GPIO pin

GPIO_INT_POL[9:8] also determines the polarity of the GPIO IEEE 1588

time clock capture events and the GPIO 1588 Timer Interrupt Clear inputs.

Refer to Section 13.2, "GPIO Operation," on page 162 for additional

information.

15:14

1588 GPIO Output Enable 9-8 (1588_GPIO_OE[9:8])

These bits configure GPIO 9 and GPIO 8 to output 1588 clock compare

events.

R/W

0: Disables the output of 1588 clock compare events

1: Enables the output of 1588 clock compare events

Note:

These bits override the direction bits in the General Purpose I/O

Data & Direction Register (GPIO_DATA_DIR) register. However,

the GPIO buffer type (GPIOBUF[11:0]) in the General Purpose I/O

Configuration Register (GPIO_CFG) is not overridden.

GPIO 9 Clock Event Polarity (GPIO_EVENT_POL_9)

This bit determines if the 1588 clock event output on GPIO 9 is active high

or low.

R/W

0: 1588 clock event output active low

1: 1588 clock event output active high

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BITS

DESCRIPTION

TYPE

DEFAULT

GPIO 8 Clock Event Polarity (GPIO_EVENT_POL_8)

This bit determines if the 1588 clock event output on GPIO 8 is active high

or low.

R/W

0: 1588 clock event output active low

1: 1588 clock event output active high

11:0

GPIO Buffer Type 11-0 (GPIOBUF[11:0])

This field sets the buffer types of the 12 GPIO pins.

R/W

0: Corresponding GPIO pin configured as an open-drain driver

1: Corresponding GPIO pin configured as a push/pull driver

As an open-drain driver, the output pin is driven low when the corresponding

data register is cleared, and is not driven when the corresponding data

As an open-drain driver used for 1588 Clock Events, the corresponding

GPIO_EVENT_POL_8 and GPIO_EVENT_POL_9 bits determine when the

corresponding pin is driven per the following table:

GPIOx Clock Event Polarity

1588 Clock Event

Pin State

not driven

driven low

not driven

yes

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14.2.3.2

General Purpose I/O Data & Direction Register (GPIO_DATA_DIR)

Offset:

1E4h

Size:

32 bits

This read/write register configures the direction of the 12 GPIO pins and contains the GPIO input and

output data bits.

BITS

DESCRIPTION

TYPE

DEFAULT

31:28

27:16

RESERVED

GPIO Direction 11-0 (GPIODIR[11:0])

These bits set the input/output direction of the 12 GPIO pins.

R/W

0: GPIO pin is configured as an input

1: GPIO pin is configured as an output

15:12

11:0

RESERVED

GPIO Data 11-0 (GPIOD[11:0])

R/W

When a GPIO pin is enabled as an output, the value written to this field is

output on the corresponding GPIO pin. Upon a read, the value returned

depends on the current direction of the pin. If the pin is an input, the data

reflects the current state of the corresponding GPIO pin. If the pin is an

output, the data is the value that was last written into this register. For

GPIOs 11-10 and 7-0, the pin direction is determined by the GPDIR bits of

this register. For GPIOs 9 and 8, the pin direction is determined by the

GPDIR bits and the 1588_GPIO_OE bits in the General Purpose I/O

Configuration Register (GPIO_CFG).

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14.2.3.3

General Purpose I/O Interrupt Status and Enable Register (GPIO_INT_STS_EN)

Offset:

1E8h

Size:

32 bits

This read/write register contains the GPIO interrupt status bits.

Writing a 1 to any of the interrupt status bits acknowledges and clears the interrupt. If enabled, these

interrupt bits are cascaded into bit 12 (GPIO) of the Interrupt Status Register (INT_STS). Writing a 1

to any of the interrupt enable bits will enable the corresponding interrupt as a source. Status bits will

still reflect the status of the interrupt source regardless of whether the source is enabled as an interrupt

in this register. Bit 12 (GPIO_EN) of the Interrupt Enable Register (INT_EN) must also be set in order

for an actual system level interrupt to occur. Refer to Chapter 5, "System Interrupts," on page 49 for

additional information.

BITS

DESCRIPTION

TYPE

DEFAULT

31:28

27:16

RESERVED

GPIO Interrupt Enable[11:0] (GPIO[11:0]_INT_EN)

When set, these bits enable the corresponding GPIO interrupt.

R/W

Note:

The GPIO interrupts must also be enabled via bit 12 (GPIO_EN) of

the Interrupt Enable Register (INT_EN) in order to cause the

interrupt pin (IRQ) to be asserted.

15:12

11:0

RESERVED

GPIO Interrupt[11:0] (GPIO[11:0]_INT)

R/WC

These signals reflect the interrupt status as generated by the GPIOs. These

interrupts are configured through the General Purpose I/O Configuration

Note:

As GPIO interrupts, GPIO inputs are level sensitive and must be

active greater than 40 nS to be recognized as interrupt inputs.

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14.2.3.4

LED Configuration Register (LED_CFG)

Offset:

1BCh

Size:

32 bits

This read/write register configures the GPIO[7:0] pins as LED[7:0] pins and sets their functionality.

BITS

DESCRIPTION

TYPE

DEFAULT

31:10

9:8

RESERVED

LED Function 1-0 (LED_FUN[1:0])

These bits control the function associated with each LED pin as shown in

T a ble 13.1 of Section 13.3, "LED Operation," on page 164.

R/W

Note 14.2

Note:

In order for these assignments to be valid, the particular pin must

be enabled as an LED output pin via the LED_EN[7:0] bits of this

7:0

LED Enable 7-0 (LED_EN[7:0])

This field toggles the functionality of the GPIO[7:0] pins between GPIO and

LED.

R/W

Note 14.3

0: Enables the associated pin as a GPIO signal

1: Enables the associated pin as a LED output

Note 14.2 The default value of this field is determined by the configuration strap LED_fun_strap[1:0].

Configuration strap values are latched on power-on reset or nRST de-assertion. Some

configuration straps can be overridden by values from the EEPROM Loader. Refer to

Section 4.2.4, "Configuration Straps," on page 40 for more information.

Note 14.3 The default value of this field is determined by the configuration strap LED_en_strap[7:0].

Configuration strap values are latched on power-on reset or nRST de-assertion. Some

configuration straps can be overridden by values from the EEPROM Loader. Refer to

Section 4.2.4, "Configuration Straps," on page 40 for more information.

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14.2.4

EEPROM

This section details the EEPROM related System CSR’s. These registers should only be used if an

EEPROM has been connected to the LAN9312. Refer to chapter Section 10.2, "I2C/Microwire Master

EEPROM Controller," on page 137 for additional information on the various modes (I C and Microwire)

of the EEPROM Controller (EPC).

14.2.4.1

EEPROM Command Register (E2P_CMD)

Offset:

1B4h

Size:

32 bits

This read/write register is used to control the read and write operations of the serial EEPROM.

BITS

DESCRIPTION

TYPE

DEFAULT

EEPROM Controller Busy (EPC_BUSY)

R/W

When a 1 is written into this bit, the operation specified in the

EPC_COMMAND field of this register is performed at the specified

EEPROM address. This bit will remain set until the selected operation is

complete. In the case of a read, this indicates that the Host can read valid

data from the EEPROM Data Register (E2P_DATA). The E2P_CMD and

E2P_DATA registers should not be modified until this bit is cleared. In the

case where a write is attempted and an EEPROM is not present, the

EPC_BUSY bit remains set until the EEPROM Controller Timeout

(EPC_TIMEOUT) bit is set. At this time the EPC_BUSY bit is cleared.

Note:

EPC_BUSY is set immediately following power-up, or pin reset, or

DIGITAL_RST reset. This bit is also set following the settings of the

SRST bit in the Hardware Configuration Register (HW_CFG). After

the EEPROM Loader has finished loading, the EPC_BUSY bit is

cleared. Refer to chapter Section 10.2.4, "EEPROM Loader," on

page 149 for more information.

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BITS

DESCRIPTION

TYPE

DEFAULT

30:28

EEPROM Controller Command (EPC_COMMAND)

R/W

000b

This field is used to issue commands to the EEPROM controller. The

EEPROM controller will execute a command when the EPC_BUSY bit is set.

A new command must not be issued until the previous command completes.

The field is encoded as follows:

[30]

[29]

[28]

Operation

READ

EWDS

EWEN

WRITE

WRAL

ERASE

ERAL

RELOAD

Note:

Only the READ, WRITE and RELOAD commands are valid for I²C mode.

If an unsupported command is attempted, the EPC_BUSY bit will be

cleared and EPC_TIMEOUT will be set.

The EEPROM operations are defined as follows:

READ (Read Location)

This command will cause a read of the EEPROM location pointed to by the

EPC_ADDRESS bit field. The result of the read is available in the EEPROM Data

EWDS (Erase/Write Disable)

(Microwire mode only) - When this command is issued, the EEPROM will ignore erase

and write commands. To re-enable erase/writes operations, issue the EWEN

command.

EWEN (Erase/Write Enable)

(Microwire mode only) - Enables the EEPROM for erase and write operations. The

EEPROM will allow erase and write operations until the EWDS command is sent, or

until the power is cycled. The Microwire EEPROM device will power-up in the

erase/write disabled state. Any erase or write operations will fail until an EWEN

command is issued.

WRITE (Write Location)

If erase/write operations are enabled in the EEPROM, this command will cause the

contents of the EEPROM Data Register (E2P_DATA) to be written to the EEPROM

location selected by the EPC_ADDRESS field. For Microwire, erase/write operations

must be enabled in the EEPROM.

WRAL (Write All)

(Microwire mode only) - If erase/write operations are enabled in the EEPROM, this

command will cause the contents of the EEPROM Data Register (E2P_DATA) to be

written to every EEPROM memory location.

ERASE (Erase Location)

(Microwire mode only) - If erase/write operations are enabled in the EEPROM, this

command will erase the location selected by the EPC_ADDRESS field.

ERAL (Erase All)

(Microwire mode only) - If erase/write operations are enabled in the EEPROM, this

command will initiate a bulk erase of the entire EEPROM.

RELOAD (EEPROM Loader Reload)

Instructs the EEPROM Loader to reload the device from the EEPROM. If a value of

A5h is not found in the first address of the EEPROM, the EEPROM is assumed to be

un-programmed and the RELOAD operation will fail. The CFG_LOADED bit indicates

a successful load. Following this command, the device will enter the not ready state.

The READY bit in the Hardware Configuration Register (HW_CFG) should be polled

to determine then the RELOAD is complete.

27:19

RESERVED

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BITS

DESCRIPTION

TYPE

DEFAULT

EEPROM Loader Address Overflow (LOADER_OVERFLOW)

This bit indicates that the EEPROM Loader tried to read past the end of the

EEPROM address space. This indicates misconfigured EEPROM data.

This bit is cleared when the EEPROM Loader is restarted with a RELOAD

command, Soft Reset(SRST), or a Digital Reset(DIGITAL_RST).

EEPROM Controller Timeout (EPC_TIMEOUT)

R/WC

This bit is set when a timeout occurs, indicating the last operation was

unsuccessful. If an EEPROM ERASE, ERAL, WRITE or WRAL operation is

performed and no response is received from the EEPROM within 30mS, the

EEPROM controller will timeout and return to its idle state.

For the I C mode, the bit is also set if the EEPROM fails to respond with

the appropriate ACKs, if the EEPROM slave device holds the clock low for

more than 30ms, or if an unsupported EPC_COMMAND is attempted.

This bit is cleared when written high.

Note:

When in Microwire mode, if an EEPROM device is not connected,

an internal pull-down on the EEDI pin will keep the EEDI signal low

and allow timeouts to occur. If EEDI is pulled high externally, EPC

commands will not time out if an EEPROM device is not connected.

In this case the EPC_BUSY bit will be cleared as soon as the

command sequence is complete. It should also be noted that the

ERASE, ERAL, WRITE and WRAL commands are the only EPC

commands that will timeout if an EEPROM device is not present

AND the EEDI signal is pulled low.

Configuration Loaded (CFG_LOADED)

When set, this bit indicates that a valid EEPROM was found and the

EEPROM Loader completed normally. This bit is set upon a successful load.

It is cleared on power-up, pin and DIGITAL_RST resets, Soft Reset(SRST),

or at the start of a RELOAD.

This bit is cleared when written high.

15:0

EEPROM Controller Address (EPC_ADDRESS)

This field is used by the EEPROM Controller to address a specific memory

location in the serial EEPROM. This address must be byte aligned.

R/W

0000h

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14.2.4.2

EEPROM Data Register (E2P_DATA)

Offset:

1B8h

Size:

32 bits

This read/write register is used in conjunction with the EEPROM Command Register (E2P_CMD) to

perform read and write operations with the serial EEPROM.

BITS

DESCRIPTION

TYPE

DEFAULT

31:8

7:0

RESERVED

EEPROM Data (EEPROM_DATA)

This field contains the data read from or written to the EEPROM.

R/W

00h

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14.2.5

IEEE 1588

This section details the IEEE 1588 timestamp related registers. Each port of the LAN9312 has a 1588

timestamp block with 8 related registers, 4 for transmit capture and 4 for receive capture. These sets

of registers are identical in functionality for each port, and thus their register descriptions have been

consolidated. In these cases, the register names will be amended with a lowercase “x” in place of the

port designation. The wildcard “x” should be replaced with “1”, “2”, or “MII” for the Port 1, Port 2, and

Port 0(Host MAC) respectively. A list of all the 1588 related registers can be seen in T a ble 14.1. For

more information on the IEEE 1588, refer to Chapter 11, "IEEE 1588 Hardware Time Stamp Unit," on

page 154.

14.2.5.1

Port x 1588 Clock High-DWORD Receive Capture Register (1588_CLOCK_HI_RX_CAPTURE_x)

Offset:

Port 1: 100h

Port 2: 120h

Port 0: 140h

Size:

32 bits

BITS

DESCRIPTION

TYPE

DEFAULT

31:0

Timestamp High (TS_HI)

This field contains the high 32-bits of the timestamp taken on the receipt of

a 1588 Sync or Delay_Req packet.

00000000h

Note: The selection between Sync or Delay_Req packets is based on the corresponding

master/slave bit in the 1588 Configuration Register (1588_CONFIG).

Note: There are multiple instantiations of this register, one for each port of the LAN9312. Refer to

Section 14.2.5 for additional information.

Note: For Port 0(Host MAC), receive is defined as data from the switch fabric, while transmit is to

the switch fabric.

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14.2.5.2

Port x 1588 Clock Low-DWORD Receive Capture Register (1588_CLOCK_LO_RX_CAPTURE_x)

Offset:

Port 1: 104h

Port 2: 124h

Port 0: 144h

Size:

32 bits

BITS

DESCRIPTION

TYPE

DEFAULT

31:0

Timestamp Low (TS_LO)

This field contains the low 32-bits of the timestamp taken on the receipt of

a 1588 Sync or Delay_Req packet.

00000000h

Note: The selection between Sync or Delay_Req packets is based on the corresponding

master/slave bit in the 1588 Configuration Register (1588_CONFIG).

Note: There are multiple instantiations of this register, one for each port of the LAN9312. Refer to

Section 14.2.5 for additional information.

Note: For Port 0(Host MAC), receive is defined as data from the switch fabric, while transmit is to

the switch fabric.

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14.2.5.3

Port x 1588 Sequence ID, Source UUID High-WORD Receive Capture Register

(1588_SEQ_ID_SRC_UUID_HI_RX_CAPTURE_x)

Offset:

Port 1: 108h

Port 2: 128h

Port 0: 148h

Size:

32 bits

BITS

DESCRIPTION

TYPE

DEFAULT

31:16

Sequence ID (SEQ_ID)

This field contains the Sequence ID from the 1588 Sync or Delay_Req

packet.

0000h

15:0

Source UUID High (SRC_UUID_HI)

This field contains the high 16-bits of the Source UUID from the 1588 Sync

or Delay_Req packet.

0000h

Note: The selection between Sync or Delay_Req packets is based on the corresponding

master/slave bit in the 1588 Configuration Register (1588_CONFIG).

Note: There are multiple instantiations of this register, one for each port of the LAN9312. Refer to

Section 14.2.5 for additional information.

Note: For Port 0(Host MAC), receive is defined as data from the switch fabric, while transmit is to

the switch fabric.

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14.2.5.4

Port x 1588 Source UUID Low-DWORD Receive Capture Register

(1588_SRC_UUID_LO_RX_CAPTURE_x)

Offset:

Port 1: 10Ch

Port 2: 12Ch

Port 0: 14Ch

Size:

32 bits

BITS

DESCRIPTION

TYPE

DEFAULT

31:0

Source UUID Low (SRC_UUID_LO)

This field contains the low 32-bits of the Source UUID from the 1588 Sync

or Delay_Req packet.

00000000h

Note: The selection between Sync or Delay_Req packets is based on the corresponding

master/slave bit in the 1588 Configuration Register (1588_CONFIG).

Note: There are multiple instantiations of this register, one for each port of the LAN9312. Refer to

Section 14.2.5 for additional information.

Note: For Port 0(Host MAC), receive is defined as data from the switch fabric, while transmit is to

the switch fabric.

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14.2.5.5

Port x 1588 Clock High-DWORD Transmit Capture Register (1588_CLOCK_HI_TX_CAPTURE_x)

Offset:

Port 1: 110h

Port 2: 130h

Port 0: 150h

Size:

32 bits

BITS

DESCRIPTION

TYPE

DEFAULT

31:0

Timestamp High (TS_HI)

This field contains the high 32-bits of the timestamp taken on the

transmission of a 1588 Sync or Delay_Req packet.

00000000h

Note: The selection between Sync or Delay_Req packets is based on the corresponding

master/slave bit in the 1588 Configuration Register (1588_CONFIG).

Note: There are multiple instantiations of this register, one for each port of the LAN9312. Refer to

Section 14.2.5 for additional information.

Note: For Port 0(Host MAC), receive is defined as data from the switch fabric, while transmit is to

the switch fabric.

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14.2.5.6

Port x 1588 Clock Low-DWORD Transmit Capture Register (1588_CLOCK_LO_TX_CAPTURE_x)

Offset:

Port 1: 114h

Port 2: 134h

Port 0: 154h

Size:

32 bits

BITS

DESCRIPTION

TYPE

DEFAULT

31:0

Timestamp Low (TS_LO)

This field contains the low 32-bits of the timestamp taken on the

transmission of a 1588 Sync or Delay_Req packet.

00000000h

Note: The selection between Sync or Delay_Req packets is based on the corresponding

master/slave bit in the 1588 Configuration Register (1588_CONFIG).

Note: There are multiple instantiations of this register, one for each port of the LAN9312. Refer to

Section 14.2.5 for additional information.

Note: For Port 0(Host MAC), receive is defined as data from the switch fabric, while transmit is to

the switch fabric.

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14.2.5.7

Port x 1588 Sequence ID, Source UUID High-WORD Transmit Capture Register

(1588_SEQ_ID_SRC_UUID_HI_TX_CAPTURE_x)

Offset:

Port 1: 118h

Port 2: 138h

Port 0: 158h

Size:

32 bits

BITS

DESCRIPTION

TYPE

DEFAULT

31:16

Sequence ID (SEQ_ID)

This field contains the Sequence ID from the 1588 Sync or Delay_Req

packet.

0000h

15:0

Source UUID High (SRC_UUID_HI)

This field contains the high 16-bits of the Source UUID from the 1588 Sync

or Delay_Req packet.

0000h

Note: The selection between Sync or Delay_Req packets is based on the corresponding

master/slave bit in the 1588 Configuration Register (1588_CONFIG).

Note: There are multiple instantiations of this register, one for each port of the LAN9312. Refer to

Section 14.2.5 for additional information.

Note: For Port 0(Host MAC), receive is defined as data from the switch fabric, while transmit is to

the switch fabric.

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14.2.5.8

Port x 1588 Source UUID Low-DWORD Transmit Capture Register

(1588_SRC_UUID_LO_TX_CAPTURE_x)

Offset:

Port 1: 11Ch

Port 2: 13Ch

Port 0: 15Ch

Size:

32 bits

BITS

DESCRIPTION

TYPE

DEFAULT

31:0

Source UUID Low (SRC_UUID_TX_LO)

This field contains the low 32-bits of the Source UUID from the 1588 Sync

or Delay_Req packet.

00000000h

Note: The selection between Sync or Delay_Req packets is based on the corresponding

master/slave bit in the 1588 Configuration Register (1588_CONFIG).

Note: There are multiple instantiations of this register, one for each port of the LAN9312. Refer to

Section 14.2.5 for additional information.

Note: For Port 0(Host MAC), receive is defined as data from the switch fabric, while transmit is to

the switch fabric.

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14.2.5.9

GPIO 8 1588 Clock High-DWORD Capture Register (1588_CLOCK_HI_CAPTURE_GPIO_8)

Offset:

160h

Size:

32 bits

This read only register combined with the GPIO 8 1588 Clock Low-DWORD Capture Register

(1588_CLOCK_LO_CAPTURE_GPIO_8) form the 64-bit GPIO 8 timestamp capture.

BITS

DESCRIPTION

TYPE

DEFAULT

31:0

Timestamp High (TS_HI)

This field contains the high 32-bits of the timestamp upon activation of GPIO

00000000h

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14.2.5.10

GPIO 8 1588 Clock Low-DWORD Capture Register (1588_CLOCK_LO_CAPTURE_GPIO_8)

Offset:

164h

Size:

32 bits

This read only register combined with the GPIO 8 1588 Clock High-DWORD Capture Register

(1588_CLOCK_HI_CAPTURE_GPIO_8) form the 64-bit GPIO 8 timestamp capture.

BITS

DESCRIPTION

TYPE

DEFAULT

31:0

Timestamp Low (TS_LO)

This field contains the low 32-bits of the timestamp upon activation of GPIO

00000000h

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14.2.5.11

GPIO 9 1588 Clock High-DWORD Capture Register (1588_CLOCK_HI_CAPTURE_GPIO_9)

Offset:

168h

Size:

32 bits

This read only register combined with the GPIO 9 1588 Clock Low-DWORD Capture Register

(1588_CLOCK_LO_CAPTURE_GPIO_9) form the 64-bit GPIO 9 timestamp capture.

BITS

DESCRIPTION

TYPE

DEFAULT

31:0

Timestamp High (TS_HI)

This field contains the high 32-bits of the timestamp upon activation of GPIO

00000000h

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14.2.5.12

GPIO 9 1588 Clock Low-DWORD Capture Register (1588_CLOCK_LO_CAPTURE_GPIO_9)

Offset:

16Ch

Size:

32 bits

This read only register combined with the GPIO 9 1588 Clock High-DWORD Capture Register

(1588_CLOCK_HI_CAPTURE_GPIO_9) form the 64-bit GPIO 9 timestamp capture.

BITS

DESCRIPTION

TYPE

DEFAULT

31:0

Timestamp Low (TS_LO)

This field contains the low 32-bits of the timestamp upon activation of GPIO

00000000h

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14.2.5.13 1588 Clock High-DWORD Register (1588_CLOCK_HI)

Offset:

170h

Size:

32 bits

This read/write register combined with 1588 Clock Low-DWORD Register (1588_CLOCK_LO) form the

64-bit 1588 Clock value. The 1588 Clock value is used for all 1588 timestamping. The 1588 Clock has

a base frequency of 100MHz, which can be adjusted via the 1588 Clock Addend Register

(1588_CLOCK_ADDEND) accordingly. Refer to Chapter 11, "IEEE 1588 Hardware Time Stamp Unit,"

on page 154 for additional information.

BITS

DESCRIPTION

TYPE

DEFAULT

31:0

Clock High (CLOCK_HI)

This field contains the high 32-bits of the 64-bit 1588 Clock.

R/W

00000000h

Note: Both this register and the 1588 Clock Low-DWORD Register (1588_CLOCK_LO) must be

written for either to be affected.

Note: The value read is the saved value of the 1588 Clock when the 1588_CLOCK_SNAPSHOT bit

in the 1588 Command Register (1588_CMD) is set.

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14.2.5.14 1588 Clock Low-DWORD Register (1588_CLOCK_LO)

Offset:

174h

Size:

32 bits

This read/write register combined with 1588 Clock High-DWORD Register (1588_CLOCK_HI) form the

64-bit 1588 Clock value. The 1588 Clock value is used for all 1588 timestamping. The 1588 Clock has

a base frequency of 100MHz, which can be adjusted via the 1588 Clock Addend Register

(1588_CLOCK_ADDEND) accordingly. Refer to Chapter 11, "IEEE 1588 Hardware Time Stamp Unit,"

on page 154 for additional information.

BITS

DESCRIPTION

TYPE

DEFAULT

31:0

Clock Low (CLOCK_LO)

This field contains the low 32-bits of the 64-bit 1588 Clock.

R/W

00000000h

Note: Both this register and the 1588 Clock High-DWORD Register (1588_CLOCK_HI) must be

written for either to be affected.

Note: The value read is the saved value of the 1588 Clock when the 1588_CLOCK_SNAPSHOT bit

in the 1588 Command Register (1588_CMD) is set.

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14.2.5.15 1588 Clock Addend Register (1588_CLOCK_ADDEND)

Offset:

178h

Size:

32 bits

This read/write register is responsible for adjusting the 64-bit 1588 Clock frequency. Refer to

Chapter 11, "IEEE 1588 Hardware Time Stamp Unit," on page 154 for details on how to properly use

this register.

BITS

DESCRIPTION

Clock Addend (CLOCK_ADDEND)

TYPE

DEFAULT

31:0

R/W

00000000h

This 32-bit value is added to the 1588 frequency divisor accumulator every

cycle. This allows the base 100MHz frequency of the 64-bit 1588 Clock to

be adjusted accordingly.

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14.2.5.16 1588 Clock Target High-DWORD Register (1588_CLOCK_TARGET_HI)

Offset:

17Ch

Size:

32 bits

This read/write register combined with 1 588 Clock T a rget Low-DWORD Register

(1588_CLOCK_TARGET_LO) form the 64-bit 1588 Clock Target value. The 1588 Clock Target value

is compared to the current 1588 Clock value and can be used to trigger an interrupt upon at match.

Refer to Chapter 11, "IEEE 1588 Hardware Time Stamp Unit," on page 154 for additional information.

BITS

DESCRIPTION

TYPE

DEFAULT

31:0

Clock Target High (CLOCK_TARGET_HI)

This field contains the high 32-bits of the 64-bit 1588 Clock Compare value.

R/W

00000000h

Note: Both

this

and

the

(1588_CLOCK_TARGET_LO) must be written for either to be affected.

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14.2.5.17 1588 Clock Target Low-DWORD Register (1588_CLOCK_TARGET_LO)

Offset:

180h

Size:

32 bits

This read/write register combined with 1 588 Clock T a rget High-DWORD Register

(1588_CLOCK_TARGET_HI) form the 64-bit 1588 Clock Target value. The 1588 Clock Target value is

compared to the current 1588 Clock value and can be used to trigger an interrupt upon at match. Refer

to Chapter 11, "IEEE 1588 Hardware Time Stamp Unit," on page 154 for additional information.

BITS

DESCRIPTION

TYPE

DEFAULT

31:0

Clock Target Low (CLOCK_TARGET_LO)

This field contains the low 32-bits of the 64-bit 1588 Clock Compare value.

R/W

00000000h

Note: Both

this

and

the

(1588_CLOCK_TARGET_HI) must be written for either to be affected.

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14.2.5.18

1588 Clock Target Reload High-DWORD Register (1588_CLOCK_TARGET_RELOAD_HI)

Offset:

184h

Size:

32 bits

This read/write register combined with 1588 Clock T a rget Reload/Add Low-DWORD Register

(1588_CLOCK_TARGET_RELOAD_LO) form the 64-bit 1588 Clock Target Reload value. The 1588

Clock Target Reload is the value that is reloaded to the 1588 Clock Compare value when a clock

compare event occurs and the Reload/Add (RELOAD_ADD) bit of the 1588 Configuration Register

(1588_CONFIG) is set. Refer to Chapter 11, "IEEE 1588 Hardware Time Stamp Unit," on page 154 for

additional information.

BITS

DESCRIPTION

TYPE

DEFAULT

31:0

Clock Target Reload High (CLOCK_TARGET_RELOAD_HI)

This field contains the high 32-bits of the 64-bit 1588 Clock Target Reload

value that is reloaded to the 1588 Clock Compare value.

R/W

00000000h

Note: Both this register and the 1588 Clock T a rget Reload/Add Low-DWORD Register

(1588_CLOCK_TARGET_RELOAD_LO) must be written for either to be affected.

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14.2.5.19

1588 Clock Target Reload/Add Low-DWORD Register (1588_CLOCK_TARGET_RELOAD_LO)

Offset:

188h

Size:

32 bits

This read/write register combined with 1588 Clock T a rget Reload High-DWORD Register

(1588_CLOCK_TARGET_RELOAD_HI) form the 64-bit 1588 Clock Target Reload value. The 1588

Clock Target Reload is the value that is reloaded or added to the 1588 Clock Compare value when a

clock compare event occurs. Whether this value is reloaded or added is determined by the Reload/Add

(RELOAD_ADD) bit of the 1588 Configuration Register (1588_CONFIG). Refer to Chapter 11, "IEEE

1588 Hardware Time Stamp Unit," on page 154 for additional information.

BITS

DESCRIPTION

TYPE

DEFAULT

31:0

Clock Target Reload Low (CLOCK_TARGET_RELOAD_LO)

This field contains the low 32-bits of the 64-bit 1588 Clock Target Reload

value that is reloaded to the 1588 Clock Compare value. Alternatively, these

32-bits are added to the 1588 Clock Compare value when configured

accordingly.

R/W

00000000h

Note: Both this register and the 1588 Clock T a rget Reload High-DWORD Register

(1588_CLOCK_TARGET_RELOAD_HI) must be written for either to be affected.

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14.2.5.20 1588 Auxiliary MAC Address High-WORD Register (1588_AUX_MAC_HI)

Offset:

18Ch

Size:

32 bits

This read/write register combined with the 1588 Auxiliary MAC Address Low-DWORD Register

(1588_AUX_MAC_LO) forms the 48-bit Auxiliary (user defined) MAC address. The Auxiliary MAC

address can be enabled for each port of the LAN9312 via their respective User Defined MAC Address

Enable bit in the 1588 Configuration Register (1588_CONFIG). Refer to Chapter 11, "IEEE 1588

Hardware Time Stamp Unit," on page 154 for additional information.

BITS

DESCRIPTION

TYPE

DEFAULT

31:16

15:0

RESERVED

Auxiliary MAC Address High (AUX_MAC_HI)

This field contains the high 16-bits of the Auxiliary MAC address used for

PTP packet detection.

R/W

0000h

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14.2.5.21 1588 Auxiliary MAC Address Low-DWORD Register (1588_AUX_MAC_LO)

Offset:

190h

Size:

32 bits

This read/write register combined with the 1588 Auxiliary MAC Address High-WORD Register

(1588_AUX_MAC_HI) forms the 48-bit Auxiliary (user defined) MAC address. The Auxiliary MAC

address can be enabled for each port of the LAN9312 via their respective User Defined MAC Address

Enable bit in the 1588 Configuration Register (1588_CONFIG). Refer to Chapter 11, "IEEE 1588

Hardware Time Stamp Unit," on page 154 for additional information.

BITS

DESCRIPTION

TYPE

DEFAULT

31:0

Auxiliary MAC Address Low (AUX_MAC_LO)

This field contains the low 32-bits of the Auxiliary MAC address used for

PTP packet detection.

R/W

00000000h

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14.2.5.22 1588 Configuration Register (1588_CONFIG)

Offset:

194h

Size:

32 bits

This read/write register is responsible for the configuration of the 1588 timestamps for all ports.

BITS

DESCRIPTION

Master/Slave Port 2 (M_nS_2)

TYPE

DEFAULT

R/W

When set, Port 2 is a time clock master and captures timestamps when a

Sync packet is transmitted and when a Delay_Req is received. When

cleared, Port 2 is a time clock slave and captures timestamps when a

Delay_Req packet is transmitted and when a Sync packet is received.

Primary MAC Address Enable Port 2 (MAC_PRI_EN_2)

R/W

This bit enables/disables the primary MAC address on Port 2.

0: Disables primary MAC address on Port 2

1: Enables MAC address 01:00:5E:00:01:81 as a PTP address on Port 2

Alternate MAC Address 1 Enable Port 2 (MAC_ALT1_EN_2)

This bit enables/disables the alternate MAC address 1 on Port 2.

0: Disables alternate MAC address on Port 2

1: Enables MAC address 01:00:5E:00:01:82 as a PTP address on Port 2

Alternate MAC Address 2 Enable Port 2 (MAC_ALT2_EN_2)

This bit enables/disables the alternate MAC address 2 on Port 2.

0: Disables alternate MAC address on Port 2

1: Enables MAC address 01:00:5E:00:01:83 as a PTP address on Port 2

Alternate MAC Address 3 Enable Port 2 (MAC_ALT3_EN_2)

This bit enables/disables the alternate MAC address 3 on Port 2.

0: Disables alternate MAC address on Port 2

1: Enables MAC address 01:00:5E:00:01:84 as a PTP address on Port 2

User Defined MAC Address Enable Port 2 (MAC_USER_EN_2)

This bit enables/disables the auxiliary MAC address on Port 2. The auxiliary

address is defined via the 1588_AUX_MAC_HI and 1588_AUX_MAC_LO

registers.

0: Disables auxiliary MAC address on Port 2

1: Enables auxiliary MAC address as a PTP address on Port 2

Lock Enable RX Port 2 (LOCK_RX_2)

R/W

This bit enables/disables the RX lock. This lock prevents a 1588 capture

from overwriting the Clock, UUDI and Sequence ID values if the 1588 RX

interrupt for Port 2 is already set due to a previous capture.

0: Disables RX Port 2 Lock

1: Enables RX Port 2 Lock

Lock Enable TX Port 2 (LOCK_TX_2)

This bit enables/disables the TX lock. This lock prevents a 1588 capture

from overwriting the Clock, UUDI and Sequence ID values if the 1588 TX

interrupt for Port 2 is already set due to a previous capture.

0: Disables TX Port 2 Lock

1: Enables TX Port 2 Lock

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BITS

DESCRIPTION

Master/Slave Port 1 (M_nS_1)

TYPE

DEFAULT

R/W

When set, Port 1 is a time clock master and captures timestamps when a

Sync packet is transmitted and when a Delay_Req is received. When

cleared, Port 1 is a time clock slave and captures timestamps when a

Delay_Req packet is transmitted and when a Sync packet is received.

Primary MAC Address Enable Port 1 (MAC_PRI_EN_1)

R/W

This bit enables/disables the primary MAC address on Port 1.

0: Disables primary MAC address on Port 1

1: Enables MAC address 01:00:5E:00:01:81 as a PTP address on Port 1

Alternate MAC Address 1 Enable Port 1 (MAC_ALT1_EN_1)

This bit enables/disables the alternate MAC address 1 on Port 1.

0: Disables alternate MAC address on Port 1

1: Enables MAC address 01:00:5E:00:01:82 as a PTP address on Port 1

Alternate MAC Address 2 Enable Port 1 (MAC_ALT2_EN_1)

This bit enables/disables the alternate MAC address 2 on Port 1.

0: Disables alternate MAC address on Port 1

1: Enables MAC address 01:00:5E:00:01:83 as a PTP address on Port 1

Alternate MAC Address 3 Enable Port 1 (MAC_ALT3_EN_1)

This bit enables/disables the alternate MAC address 3 on Port 1.

0: Disables alternate MAC address on Port 1

1: Enables MAC address 01:00:5E:00:01:84 as a PTP address on Port 1

User Defined MAC Address Enable Port 1 (MAC_USER_EN_1)

This bit enables/disables the auxiliary MAC address on Port 1. The auxiliary

address is defined via the 1588_AUX_MAC_HI and 1588_AUX_MAC_LO

registers.

0: Disables auxiliary MAC address on Port 1

1: Enables auxiliary MAC address as a PTP address on Port 1

Lock Enable RX Port 1 (LOCK_RX_1)

R/W

This bit enables/disables the RX lock. This lock prevents a 1588 capture

from overwriting the Clock, UUDI and Sequence ID values if the 1588 RX

interrupt for Port 1 is ready set due to a previous capture.

0: Disables RX Port 1 Lock

1: Enables RX Port 1 Lock

Lock Enable TX Port 1 (LOCK_TX_1)

This bit enables/disables the TX lock. This lock prevents a 1588 capture

from overwriting the Clock, UUDI and Sequence ID values if the 1588 TX

interrupt for Port 1 is ready set due to a previous capture.

0: Disables TX Port 1 Lock

1: Enables TX Port 1 Lock

Master/Slave Port 0(Host MAC)(M_nS_MII)

When set, Port 0 is a time clock master and captures timestamps when a

Sync packet is transmitted and when a Delay_Req is received. When

cleared, Port 0 is a time clock slave and captures timestamps when a

Delay_Req packet is transmitted and when a Sync packet is received.

Note:

For Port 0, receive is defined as data from the switch fabric, while

transmit is defined as data to the switch fabric.

Primary MAC Address Enable Port 0(Host MAC) (MAC_PRI_EN_MII)

This bit enables/disables the primary MAC address on Port 0.

R/W

0: Disables primary MAC address on Port 0

1: Enables MAC address 01:00:5E:00:01:81 as a PTP address on Port 0

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BITS

DESCRIPTION

TYPE

DEFAULT

Alternate MAC Address 1 Enable Port 0(Host MAC)

(MAC_ALT1_EN_MII)

This bit enables/disables the alternate MAC address 1 on Port 0.

R/W

0: Disables alternate MAC address on Port 0

1: Enables MAC address 01:00:5E:00:01:82 as a PTP address on Port 0

Alternate MAC Address 2 Enable Port 0(Host MAC)

(MAC_ALT2_EN_MII)

R/W

This bit enables/disables the alternate MAC address 2 on Port 0.

0: Disables alternate MAC address on Port 0

1: Enables MAC address 01:00:5E:00:01:83 as a PTP address on Port 0

Alternate MAC Address 3 Enable Port 0(Host MAC)

(MAC_ALT3_EN_MII)

This bit enables/disables the alternate MAC address 3 on Port 0.

0: Disables alternate MAC address on Port 0

1: Enables MAC address 01:00:5E:00:01:84 as a PTP address on Port 0

User Defined MAC Address Enable Port 0(Host MAC)

(MAC_USER_EN_MII)

This bit enables/disables the auxiliary MAC address on Port 0. The auxiliary

address is defined via the 1588_AUX_MAC_HI and 1588_AUX_MAC_LO

registers.

0: Disables auxiliary MAC address on Port 0

1: Enables auxiliary MAC address as a PTP address on Port 0

Lock Enable RX Port 0(Host MAC) (LOCK_RX_MII)

R/W

This bit enables/disables the RX lock. This lock prevents a 1588 capture

from overwriting the Clock, UUDI and Sequence ID values if the 1588 RX

interrupt for Port 0 is ready set due to a previous capture.

0: Disables RX Port 0 Lock

1: Enables RX Port 0 Lock

Note:

For Port 0, receive is defined as data from the switch fabric, while

transmit is to the switch fabric.

Lock Enable TX Port 0(Host MAC) (LOCK_TX_MII)

R/W

This bit enables/disables the TX lock. This lock prevents a 1588 capture

from overwriting the Clock, UUDI and Sequence ID values if the 1588 TX

interrupt for Port 0 is ready set due to a previous capture.

0: Disables TX Port 0 Lock

1: Enables TX Port 0 Lock

Note:

For Port 0, receive is defined as data from the switch fabric, while

transmit is to the switch fabric.

RESERVED

Lock Enable GPIO 9 (LOCK_GPIO_9)

R/W

This bit enables/disables the GPIO 9 lock. This lock prevents a 1588 capture

from overwriting the Clock value if the 1588_GPIO9 interrupt in the 1588

Interrupt Status and Enable Register (1588_INT_STS_EN) is already set

due to a previous capture.

0: Disables GPIO 9 Lock

1: Enables GPIO 9 Lock

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BITS

DESCRIPTION

Lock Enable GPIO 8 (LOCK_GPIO_8)

TYPE

DEFAULT

R/W

This bit enables/disables the GPIO 8 lock. This lock prevents a 1588 capture

from overwriting the Clock value if the 1588_GPIO8 interrupt in the 1588

Interrupt Status and Enable Register (1588_INT_STS_EN) is already set

due to a previous capture.

0: Disables GPIO 8 Lock

1: Enables GPIO 8 Lock

4:3

2:1

GPIO 9 Clock Event Mode (GPIO_EVENT_9)

These bits determine the output on GPIO 9 when a clock target compare

event occurs.

R/W

00b

00: 100ns pulse output

01: Toggle output

10: 1588_TIMER_INT bit value in the 1588_INT_STS_EN register output

11: RESERVED

Note:

The 1588_GPIO_OE[9] bit in the General Purpose I/O

Configuration Register (GPIO_CFG) must be set in order for the

GPIO output to be controlled by the 1588 block.

Note:

The polarity of the pulse or level is set by the

GPIO_EVENT_POL_9 bit in the General Purpose I/O Configuration

GPIO buffer type.

GPIO 8 Clock Event Mode (GPIO_EVENT_8)

These bits determine the output on GPIO 8 when a clock target compare

event occurs.

00: 100ns pulse output

01: Toggle output

10: 1588_TIMER_INT bit value in the 1588_INT_STS_EN register output

11: RESERVED

Note:

The 1588_GPIO_OE[8] bit in the General Purpose I/O

Configuration Register (GPIO_CFG) must be set in order for the

GPIO output to be controlled by the 1588 block.

Note:

The polarity of the pulse or level is set by the

GPIO_EVENT_POL_8 bit in the General Purpose I/O Configuration

GPIO buffer type.

Reload/Add (RELOAD_ADD)

This bit determines the course of action when a clock target compare event

occurs. When set, the 1588 Clock T a rget High-DWORD Register

(1588_CLOCK_TARGET_HI) and 1588 Clock T a rget Low-DWORD Register

(1588_CLOCK_TARGET_LO) are loaded from the 1588 Clock T a rget

Reload High-DWORD Register (1588_CLOCK_TARGET_RELOAD_HI) and

1588 Clock T a rget Reload/Add Low-DWORD Register

(1588_CLOCK_TARGET_RELOAD_LO) when a clock target compare event

occurs. When low, the Clock Target Low and High Registers are

incremented by the Clock Target Reload Low Register when a clock target

compare event occurs.

0: Reload upon a clock target compare event

1: Increment upon a clock target compare event

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14.2.5.23 1588 Interrupt Status and Enable Register (1588_INT_STS_EN)

Offset:

198h

Size:

32 bits

This read/write register contains the IEEE 1588 interrupt status and enable bits.

Writing a 1 to any of the interrupt status bits acknowledges and clears the interrupt. If enabled, these

interrupt bits are cascaded into bit 29 (1588_EVNT) of the Interrupt Status Register (INT_STS). Writing

a 1 to any of the interrupt enable bits will enable the corresponding interrupt as a source. Status bits

will still reflect the status of the interrupt source regardless of whether the source is enabled as an

interrupt in this register. Bit 29 (1588_EVNT_EN) of the Interrupt Enable Register (INT_EN) must also

be set in order for an actual system level interrupt to occur. Refer to Chapter 5, "System Interrupts,"

on page 49 for additional information.

BITS

DESCRIPTION

TYPE

DEFAULT

31:25

RESERVED

R/W

1588 Port 2 RX Interrupt Enable (1588_PORT2_RX_EN)

1588 Port 2 TX Interrupt Enable (1588_PORT2_TX_EN)

1588 Port 1 RX Interrupt Enable (1588_PORT1_RX_EN)

1588 Port 1 TX Interrupt Enable (1588_PORT1_TX_EN)

1588 Port 0(Host MAC) RX Interrupt Enable (1588_MII_RX_EN)

1588 Port 0(Host MAC) TX Interrupt Enable (1588_MII_TX_EN)

GPIO9 1588 Interrupt Enable (1588_GPIO9_EN)

GPIO8 1588 Interrupt Enable (1588_GPIO8_EN)

1588 Timer Interrupt Enable (1588_TIMER_EN)

RESERVED

15:9

1588 Port 2 RX Interrupt (1588_PORT2_RX_INT)

This interrupt indicates that a packet received by Port 2 matches the

configured PTP packet and the 1588 clock was captured.

R/WC

1588 Port 2 TX Interrupt (1588_PORT2_TX_INT)

R/WC

This interrupt indicates that a packet transmitted by Port 2 matches the

configured PTP packet and the 1588 clock was captured.

1588 Port 1 RX Interrupt (1588_PORT1_RX_INT)

This interrupt indicates that a packet received by Port 1 matches the

configured PTP packet and the 1588 clock was captured.

1588 Port 1 TX Interrupt (1588_PORT1_TX_INT)

This interrupt indicates that a packet transmitted by Port 1 matches the

configured PTP packet and the 1588 clock was captured.

1588 Port 0(Host MAC) RX Interrupt (1588_MII_RX_INT)

This interrupt indicates that a packet from the switch fabric to the Host MAC

the matches the configured PTP packet and the 1588 clock was captured.

Note:

For Port 0, receive is defined as data from the switch fabric, while

transmit is to the switch fabric.

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BITS

DESCRIPTION

TYPE

DEFAULT

1588 Port 0(Host MAC) TX Interrupt (1588_MII_TX_INT)

This interrupt indicates that a packet from the Host MAC to the switch fabric

matches the configured PTP packet and the 1588 clock was captured.

R/WC

Note:

For Port 0, receive is defined as data from the switch fabric, while

transmit is to the switch fabric.

1588 GPIO9 Interrupt (1588_GPIO9_INT)

R/WC

This interrupt indicates that an event on GPIO9 occurred and the 1588 clock

was captured. These interrupts are configured through the General Purpose

I/O Configuration Register (GPIO_CFG) register.

Note:

As 1588 capture inputs, GPIO inputs are edge sensitive and must

be active for greater than 40 nS to be recognized as interrupt

inputs.

1588 GPIO8 Interrupt (1588_GPIO8_INT)

This interrupt indicates that an event on GPIO8 occurred and the 1588 clock

was captured. These interrupts are configured through the General Purpose

I/O Configuration Register (GPIO_CFG) register.

Note:

As 1588 capture inputs, GPIO inputs are edge sensitive and must

be active for greater than 40 nS to be recognized as interrupt

inputs.

1588 Timer Interrupt (1588_TIMER_INT)

This interrupt indicates that the 1588 clock equaled or passed the Clock

Target value in the 1588 Clock T a rget High-DWORD Register

(1588_CLOCK_TARGET_HI) and 1588 Clock T a rget Low-DWORD Register

(1588_CLOCK_TARGET_LO).

Note:

This bit is also cleared by an active edge on GPIO[9:8] if enabled.

For the clear function, GPIO inputs are edge sensitive and must be

active for greater than 40 nS to be recognized as a clear input.

Refer to Section 13.2, "GPIO Operation," on page 162 for

additional information.

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14.2.5.24 1588 Command Register (1588_CMD)

Offset:

19Ch

Size:

32 bits

This register is used to issue 1588 commands. Using the clock snapshot bit allows the host to properly

read the current IEEE 1588 clock values from the 1588 Clock High-DWORD Register

(1588_CLOCK_HI) and 1588 Clock Low-DWORD Register (1588_CLOCK_LO). Refer to section

Section 11.3, "IEEE 1588 Clock," on page 159 for additional information.

BITS

DESCRIPTION

TYPE

DEFAULT

31:1

RESERVED

Clock Snapshot (1588_CLOCK_SNAPSHOT)

Setting this bit causes the current 1588 Clock High-DWORD Register

(1588_CLOCK_HI) and 1588 Clock Low-DWORD Register

(1588_CLOCK_LO) values to be saved so they can be read.

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14.2.6

Switch Fabric

This section details the memory mapped System CSR’s which are related to the Switch Fabric. The

flow control of all three ports of the switch fabric can be configured via the memory mapped System

CSR’s MANUAL_FC_1, MANUAL_FC_2 and MANUAL_FC_MII. The MAC address used by the switch

for Pause frames is configured via the SWITCH_MAC_ADDRH and SWITCH_MAC_ADDRL registers.

In addition, the SWITCH_CSR_CMD, SWITCH_CSR_DATA and SWITCH_CSR_DIRECT_DATA

registers serve as a memory mapped accessible interface to the full range of otherwise inaccessible

switch control and status registers. A list of all the switch fabric CSRs can be seen in T a ble 14.12. For

additional information on the switch fabric, including a full explanation on how to use the switch fabric

CSR interface registers, refer to Chapter 6, "Switch Fabric," on page 55. For detailed descriptions of

the Switch Fabric CSR’s that are accessible via these interface registers, refer to section Section 14.5,

"Switch Fabric Control and Status Registers".

14.2.6.1

Port 1 Manual Flow Control Register (MANUAL_FC_1)

Offset:

1A0h

Size:

32 bits

This read/write register allows for the manual configuration of the switch Port 1 flow control. This

or Auto-Negotiated. Refer to Section 6.2.3, "Flow Control Enable Logic," on page 58 for additional

information.

Note: The flow control values in the PHY_AN_ADV_1 register (see Section 14.4.2.5, on page 293)

within the PHY are not affected by the values of this register.

BITS

DESCRIPTION

TYPE

DEFAULT

31:7

RESERVED

Port 1 Backpressure Enable (BP_EN_1)

This bit enables/disables the generation of half-duplex backpressure on

switch Port 1.

R/W

Note 14.4

0: Disable backpressure

1: Enable backpressure

Port 1 Current Duplex (CUR_DUP_1)

Note 14.5

Note 14.6

This bit indicates the actual duplex setting of switch Port 1.

0: Full-Duplex

1: Half-Duplex

Port 1 Current Receive Flow Control Enable (CUR_RX_FC_1)

This bit indicates the actual receive flow setting of switch Port 1.

0: Flow control receive is currently disabled

1: Flow control receive is currently enabled

Port 1 Current Transmit Flow Control Enable (CUR_TX_FC_1)

This bit indicates the actual transmit flow setting of switch Port 1.

0: Flow control transmit is currently disabled

1: Flow control transmit is currently enabled

Port 1 Full-Duplex Receive Flow Control Enable (RX_FC_1)

When the MANUAL_FC_1 bit is set, or Auto-Negotiation is disabled, this bit

enables/disables the detection of full-duplex Pause packets on switch Port 1.

R/W

0: Disable flow control receive

1: Enable flow control receive

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BITS

DESCRIPTION

TYPE

DEFAULT

Port 1 Full-Duplex Transmit Flow Control Enable (TX_FC_1)

When the MANUAL_FC_1 bit is set, or Auto-Negotiation is disabled, this bit

enables/disables full-duplex Pause packets to be generated on switch Port

R/W

Note 14.6

0: Disable flow control transmit

1: Enable flow control transmit

Port 1 Full-Duplex Manual Flow Control Select (MANUAL_FC_1)

This bit toggles flow control selection between manual and auto-negotiation.

R/W

Note 14.7

0: If auto-negotiation is enabled, the auto-negotiation function

determines the flow control of switch Port 1 (RX_FC_1 and TX_FC_1

values ignored). If auto-negotiation is disabled, the RX_FC_1 and

TX_FC_1 values are used.

1: TX_FC_1 and RX_FC_1 bits determine the flow control of switch Port

1 when in full-duplex mode

Note 14.4 The default value of this field is determined by the BP_EN_strap_1 configuration strap. The

strap values are loaded during reset and can be re-written by the EEPROM Loader. Once

the EEPROM Loader re-writes the values, this register is updated with the new values.

See Section 4.2.4, "Configuration Straps," on page 40 for more information.

Note 14.5 The default value of this bit is determined by multiple strap settings. The strap values are

loaded during reset and can be re-written by the EEPROM Loader. Once the EEPROM

Loader re-writes the values, this register is updated with the new values. Refer to Section

6.2.3, "Flow Control Enable Logic," on page 58 for additional information.

Note 14.6 The default value of this field is determined by the FD_FC_strap_1 configuration strap. The

strap values are loaded during reset and can be re-written by the EEPROM Loader. Once

the EEPROM Loader re-writes the values, this register is updated with the new values.

See Section 4.2.4, "Configuration Straps," on page 40 for more information.

Note 14.7 The default value of this field is determined by the manual_FC_strap_1 configuration strap.

The strap values are loaded during reset and can be re-written by the EEPROM Loader.

Once the EEPROM Loader re-writes the values, this register is updated with the new

values. See Section 4.2.4, "Configuration Straps," on page 40 for more information.

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14.2.6.2

Port 2 Manual Flow Control Register (MANUAL_FC_2)

Offset:

1A4h

Size:

32 bits

This read/write register allows for the manual configuration of the switch Port 2 flow control. This

or Auto-Negotiated. Refer to Section 6.2.3, "Flow Control Enable Logic," on page 58 for additional

information.

Note: The flow control values in the PHY_AN_ADV_2 register (see Section 14.4.2.5, on page 293)

within the PHY are not affected by the values of this register.

BITS

DESCRIPTION

TYPE

DEFAULT

31:7

RESERVED

Port 2 Backpressure Enable (BP_EN_2)

This bit enables/disables the generation of half-duplex backpressure on

switch Port 2.

R/W

Note 14.8

0: Disable backpressure

1: Enable backpressure

Port 2 Current Duplex (CUR_DUP_2)

Note 14.9

Note 14.10

This bit indicates the actual duplex setting of switch Port 2.

0: Full-Duplex

1: Half-Duplex

Port 2 Current Receive Flow Control Enable (CUR_RX_FC_2)

This bit indicates the actual receive flow setting of switch Port 2.

0: Flow control receive is currently disabled

1: Flow control receive is currently enabled

Port 2 Current Transmit Flow Control Enable (CUR_TX_FC_2)

This bit indicates the actual transmit flow setting of switch Port 2.

0: Flow control transmit is currently disabled

1: Flow control transmit is currently enabled

Port 2 Full-Duplex Receive Flow Control Enable (RX_FC_2)

When the MANUAL_FC_2 bit is set, or Auto-Negotiation is disabled, this bit

enables/disables the detection of full-duplex Pause packets on switch Port 2.

R/W

0: Disable flow control receive

1: Enable flow control receive

Port 2 Full-Duplex Transmit Flow Control Enable (TX_FC_2)

When the MANUAL_FC_2 bit is set, or Auto-Negotiation is disabled, this bit

enables/disables full-duplex Pause packets to be generated on switch Port

R/W

Note 14.10

Note 14.11

0: Disable flow control transmit

1: Enable flow control transmit

Port 2 Full-Duplex Manual Flow Control Select (MANUAL_FC_2)

This bit toggles flow control selection between manual and auto-negotiation.

0: If auto-negotiation is enabled, the auto-negotiation function

determines the flow control of switch Port 2 (RX_FC_2 and TX_FC_2

values ignored). If auto-negotiation is disabled, the RX_FC_2 and

TX_FC_2 values are used.

1: TX_FC_2 and RX_FC_2 bits determine the flow control of switch Port

2 when in full-duplex mode

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Note 14.8 The default value of this field is determined by the BP_EN_strap_2 configuration strap. The

strap values are loaded during reset and can be re-written by the EEPROM Loader. Once

the EEPROM Loader re-writes the values, this register is updated with the new values.

See Section 4.2.4, "Configuration Straps," on page 40 for more information.

Note 14.9 The default value of this bit is determined by multiple strap settings. The strap values are

loaded during reset and can be re-written by the EEPROM Loader. Once the EEPROM

Loader re-writes the values, this register is updated with the new values. Refer to Section

6.2.3, "Flow Control Enable Logic," on page 58 for additional information.

Note 14.10 The default value of this field is determined by the FD_FC_strap_2 configuration strap. The

strap values are loaded during reset and can be re-written by the EEPROM Loader. Once

the EEPROM Loader re-writes the values, this register is updated with the new values.

See Section 4.2.4, "Configuration Straps," on page 40 for more information.

Note 14.11 The default value of this field is determined by the manual_FC_strap_2 configuration strap.

The strap values are loaded during reset and can be re-written by the EEPROM Loader.

Once the EEPROM Loader re-writes the values, this register is updated with the new

values. See Section 4.2.4, "Configuration Straps," on page 40 for more information.

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14.2.6.3

Port 0(Host MAC) Manual Flow Control Register (MANUAL_FC_MII)

Offset:

1A8h

Size:

32 bits

This read/write register allows for the manual configuration of the switch Port 0(Host MAC) flow control.

This register also provides read back of the currently enabled flow control settings, whether set

manually or Auto-Negotiated. Refer to Section 6.2.3, "Flow Control Enable Logic," on page 58 for

additional information.

Note: The flow control values in the Section 14.2.8.5, "Virtual PHY Auto-Negotiation Advertisement

BITS

DESCRIPTION

TYPE

DEFAULT

31:8

RESERVED

Port 0 Hard-wired Flow Control (HW_FC_MII)

R/W

When set to “1”, the Host MACs RX FIFO level is connected to the switch

engine’s transmitter and the switch engines RX FIFO level is connected to

the Host MACs transmitter. This achieves lower latency flow control.

Note:

All other flow control methods must be disabled when using this

feature. (MANUAL_FC_MII should be set, TX_FC_MII,

RX_FC_MII, and BP_EN_MII should be cleared. FCANY, FCADD,

FCBRD, and FCMULT in the AFC_CFG register should be

cleared).

Port 0 Backpressure Enable (BP_EN_MII)

This bit enables/disables the generation of half-duplex backpressure on

switch Port 0.

R/W

Note 14.12

0: Disable backpressure

1: Enable backpressure

Port 0 Current Duplex (CUR_DUP_MII)

Note 14.13

Note 14.14

This bit indicates the actual duplex setting of the switch Port 0.

0: Full-Duplex

1: Half-Duplex

Port 0 Current Receive Flow Control Enable (CUR_RX_FC_MII)

This bit indicates the actual receive flow setting of switch Port 0

0: Flow control receive is currently disabled

1: Flow control receive is currently enabled

Port 0 Current Transmit Flow Control Enable (CUR_TX_FC_MII)

This bit indicates the actual transmit flow setting of switch Port 0.

0: Flow control transmit is currently disabled

1: Flow control transmit is currently enabled

Port 0 Receive Flow Control Enable (RX_FC_MII)

When the MANUAL_FC_MII bit is set, or Virtual Auto-Negotiation is

disabled, this bit enables/disables the detection of full-duplex Pause packets

on switch Port 0.

R/W

0: Disable flow control receive

1: Enable flow control receive

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BITS

DESCRIPTION

TYPE

DEFAULT

Port 0 Transmit Flow Control Enable (TX_FC_MII)

When the MANUAL_FC_MII bit is set, or Virtual Auto-Negotiation is

disabled, this bit enables/disables full-duplex Pause packets to be generated

on switch Port 0.

R/W

Note 14.14

0: Disable flow control transmit

1: Enable flow control transmit

Port 0 Full-Duplex Manual Flow Control Select (MANUAL_FC_MII)

This bit toggles flow control selection between manual and auto-negotiation.

R/W

Note 14.15

0: If auto-negotiation is enabled, the auto-negotiation function

determines the flow control of switch Port 0 (RX_FC_MII and

TX_FC_MII values ignored). If auto-negotiation is disabled, the

RX_FC_MII and TX_FC_MII values are used.

1: TX_FC_MII and RX_FC_MII bits determine the flow control of switch

Port 0 when in full-duplex mode

Note 14.12 The default value of this field is determined by the BP_EN_strap_mii configuration strap.

The strap value is loaded during reset and can be re-written by the EEPROM Loader. Once

the EEPROM Loader re-writes the value, this register is updated with the new values. See

Section 4.2.4, "Configuration Straps," on page 40 for more information.

Note 14.13 The default value of this bit is determined by multiple strap settings. The strap values are

loaded during reset and can be re-written by the EEPROM Loader. Once the EEPROM

Loader re-writes the values, this register is updated with the new values. Refer to Section

6.2.3, "Flow Control Enable Logic," on page 58 for additional information.

Note 14.14 The default value of this field is determined by the FD_FC_strap_mii configuration strap.

The strap value is loaded during reset and can be re-written by the EEPROM Loader. Once

the EEPROM Loader re-writes the value, this register is updated with the new values. See

Section 4.2.4, "Configuration Straps," on page 40 for more information.

Note 14.15 The default value of this field is determined by the manual_FC_strap_mii configuration

strap. The strap value is loaded during reset and can be re-written by the EEPROM

Loader. Once the EEPROM Loader re-writes the value, this register is updated with the

new values. See Section 4.2.4, "Configuration Straps," on page 40 for more information.

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14.2.6.4

Switch Fabric CSR Interface Data Register (SWITCH_CSR_DATA)

Offset:

1ACh

Size:

32 bits

This read/write register is used in conjunction with the Switch Fabric CSR Interface Command Register

(SWITCH_CSR_CMD) to perform read and write operations with the Switch Fabric CSR’s. Refer to

Section 14.5, "Switch Fabric Control and Status Registers," on page 307 for details on the registers

indirectly accessible via this register.

BITS

DESCRIPTION

Switch CSR Data (CSR_DATA)

TYPE

DEFAULT

31:0

R/W

00000000h

This field contains the value read from or written to the Switch Fabric CSR.

The Switch Fabric CSR is selected via the CSR Address (CSR_ADDR[15:0])

bits of the Switch Fabric CSR Interface Command Register

(SWITCH_CSR_CMD).

Upon a read, the value returned depends on the R/nW bit in the Switch

Fabric CSR Interface Command Register (SWITCH_CSR_CMD). If R/nW is

set, the data is from the switch fabric. If R/nW is cleared, the data is the

value that was last written into this register.

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14.2.6.5

Switch Fabric CSR Interface Command Register (SWITCH_CSR_CMD)

Offset:

1B0h

Size:

32 bits

This read/write register is used in conjunction with the Switch Fabric CSR Interface Data Register

(SWITCH_CSR_DATA) to control the read and write operations to the various Switch Fabric CSR’s.

Refer to Section 14.5, "Switch Fabric Control and Status Registers," on page 307 for details on the

registers indirectly accessible via this register.

BITS

DESCRIPTION

TYPE

DEFAULT

CSR Busy (CSR_BUSY)

R/W

When a 1 is written to this bit, the read or write operation (as determined by

the R_nW bit) is performed to the specified Switch Fabric CSR in CSR

Address (CSR_ADDR[15:0]). This bit will remain set until the operation is

complete, at which time the bit will clear. In the case of a read, the clearing

of this bit indicates to the Host that valid data can be read from the Switch

Fabric CSR Interface Data Register (SWITCH_CSR_DATA). The

SWITCH_CSR_CMD and SWITCH_CSR_DATA registers should not be

modified until this bit is cleared.

Read/Write (R_nW)

R/W

This bit determines whether a read or write operation is performed by the

Host to the specified Switch Engine CSR.

0: Write

1: Read

Auto Increment (AUTO_INC)

This bit enables/disables the auto increment feature.

When this bit is set, a write to the Switch Fabric CSR Interface Data Register

(SWITCH_CSR_DATA) register will automatically set the CSR Busy

(CSR_BUSY) bit. Once the write command is finished, the CSR Address

(CSR_ADDR[15:0]) will automatically increment.

When this bit is set, a read from the Switch Fabric CSR Interface Data

Address (CSR_ADDR[15:0]) and set the CSR Busy (CSR_BUSY) bit. This

bit should be cleared by software before the last read from the

SWITCH_CSR_DATA register.

0: Disable Auto Increment

1: Enable Auto Increment

Note:

This bit has precedence over the Auto Decrement (AUTO_DEC) bit

Auto Decrement (AUTO_DEC)

This bit enables/disables the auto decrement feature.

R/W

When this bit is set, a write to the Switch Fabric CSR Interface Data Register

(SWITCH_CSR_DATA) will automatically set the CSR Busy (CSR_BUSY)

bit. Once the write command is finished, the CSR Address

(CSR_ADDR[15:0]) will automatically decrement.

When this bit is set, a read from the Switch Fabric CSR Interface Data

Address (CSR_ADDR[15:0]) and set the CSR Busy (CSR_BUSY) bit. This

bit should be cleared by software before the last read from the

SWITCH_CSR_DATA register.

0: Disable Auto Decrement

1: Enable Auto Decrement

27:20

RESERVED

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BITS

DESCRIPTION

CSR Byte Enable (CSR_BE[3:0])

TYPE

DEFAULT

19:16

R/W

This field is a 4-bit byte enable used for selection of valid bytes during write

operations. Bytes which are not selected will not be written to the

corresponding Switch Engine CSR.

CSR_BE[3] corresponds to register data bits [31:24]

CSR_BE[2] corresponds to register data bits [23:16]

CSR_BE[1] corresponds to register data bits [15:8]

CSR_BE[0] corresponds to register data bits [7:0]

Typically all four byte enables should be set for auto increment and auto

decrement operations.

15:0

CSR Address (CSR_ADDR[15:0])

R/W

00h

This field selects the 16-bit address of the Switch Fabric CSR that will be

accessed with a read or write operation. Refer to T a ble 14.12, “Indirectly

Accessible Switch Control and Status Registers,” on page 307 for a list of

Switch Fabric CSR addresses.

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14.2.6.6

Switch Fabric MAC Address High Register (SWITCH_MAC_ADDRH)

Offset:

1F0h

Size:

32 bits

This register contains the upper 16-bits of the MAC address used by the switch for Pause frames. This

(SWITCH_MAC_ADDRL). The contents of this register are optionally loaded from the EEPROM at

power-on through the EEPROM Loader if a programmed EEPROM is detected. The least significant

byte of this register (bits [7:0]) is loaded from address 05h of the EEPROM. The second byte (bits

[15:8]) is loaded from address 06h of the EEPROM. These EEPROM values are also loaded into the

Host MAC Address High Register (HMAC_ADDRH). The Host can update the contents of this field

after the initialization process has completed.

Refer to Section 9.6, "Host MAC Address," on page 119 for details on how the EEPROM Loader loads

this register. Section 10.2.4, "EEPROM Loader," on page 149 contains additional details on using the

EEPROM Loader.

BITS

DESCRIPTION

TYPE

DEFAULT

31:16

15:0

RESERVED

Physical Address[47:32]

This field contains the upper 16-bits (47:32) of the physical address of the

Switch Fabric MACs.

R/W

FFFFh

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14.2.6.7

Switch Fabric MAC Address Low Register (SWITCH_MAC_ADDRL)

Offset:

1F4h

Size:

32 bits

This register contains the lower 32-bits of the MAC address used by the switch for Pause frames. This

(SWITCH_MAC_ADDRH). The contents of this register are optionally loaded from the EEPROM at

power-on through the EEPROM Loader if a programmed EEPROM is detected. The least significant

byte of this register (bits [7:0]) is loaded from address 01h of the EEPROM. The most significant byte

(bits [31:24]) is loaded from address 04h of the EEPROM. These EEPROM values are also loaded

into the Host MAC Address Low Register (HMAC_ADDRL). The Host can update the contents of this

field after the initialization process has completed.

Refer to Section 9.6, "Host MAC Address," on page 119 for details on how the EEPROM Loader loads

this register. Refer to Section 10.2.4, "EEPROM Loader," on page 149 for information on using the

EEPROM Loader.

BITS

DESCRIPTION

TYPE

DEFAULT

31:0

Physical Address[31:0]

This field contains the lower 32-bits (31:0) of the physical address of the

Switch Fabric MACs.

R/W

FF0F8000h

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14.2.6.8

Switch Fabric CSR Interface Direct Data Register (SWITCH_CSR_DIRECT_DATA)

Offset:

200h - 2DCh

Size:

32 bits

This write-only register set is used to perform directly addressed write operations to the Switch Fabric

CSR’s. Using this set of registers, writes can be directly addressed to select Switch Fabric registers,

as specified in T a ble 14.3.

Writes within the Switch Fabric CSR Interface Direct Data Register (SWITCH_CSR_DIRECT_DATA)

address range automatically set the appropriate address, set the four byte enable bits, clear the R/nW

bit and set the Busy bit in the Switch Fabric CSR Interface Command Register (SWITCH_CSR_CMD).

The completion of the write cycle is indicated when the Busy bit is cleared. The address that is set in

the Switch Fabric CSR Interface Command Register (SWITCH_CSR_CMD) is mapped via T a ble 14.3.

For more information on this method of writing to the Switch Fabric CSR’s, refer to Section 6.2.3, "Flow

Control Enable Logic," on page 58.

BITS

DESCRIPTION

Switch CSR Data (CSR_DATA)

This field contains the value to be written to the corresponding Switch Fabric

TYPE

DEFAULT

31:0

00000000h

Note: This set of registers is for write operations only. Reads can be performed via the Switch Fabric

CSR Interface Command Register (SWITCH_CSR_CMD) and Switch Fabric CSR Interface

Data Register (SWITCH_CSR_DATA) registers only.

Table 14.3 Switch Fabric CSR to SWITCH_CSR_DIRECT_DATA Address Range Map

SWITCH FABRIC CSR

SWITCH_CSR_DIRECT_DATA

ADDRESS

General Switch CSRs

SW_RESET

SW_IMR

0001h

0004h

200h

204h

Switch Port 0 CSRs

0401h

MAC_RX_CFG_MII

MAC_TX_CFG_MII

208h

20Ch

210h

214h

0440h

MAC_TX_FC_SETTINGS_MII

MAC_IMR_MII

0441h

0480h

Switch Port 1 CSRs

0801h

MAC_RX_CFG_1

MAC_TX_CFG_1

218h

21Ch

220h

224h

0840h

MAC_TX_FC_SETTINGS_1

MAC_IMR_1

0841h

0880h

Switch Port 2 CSRs

0C01h

MAC_RX_CFG_2

228h

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Table 14.3 Switch Fabric CSR to SWITCH_CSR_DIRECT_DATA Address Range Map (continued)

SWITCH FABRIC CSR

SWITCH_CSR_DIRECT_DATA

ADDRESS

MAC_TX_CFG_2

MAC_TX_FC_SETTINGS_2

MAC_IMR_2

0C40h

0C41h

22Ch

230h

234h

0C80h

Switch Engine CSRs

1800h

SWE_ALR_CMD

SWE_ALR_WR_DAT_0

SWE_ALR_WR_DAT_1

SWE_ALR_CFG

238h

23Ch

240h

244h

248h

24Ch

250h

254h

258h

25Ch

260h

264h

268h

26Ch

270h

274h

278h

27Ch

280h

284h

288h

28Ch

290h

294h

1801h

1802h

1809h

SWE_VLAN_CMD

180Bh

SWE_VLAN_WR_DATA

SWE_DIFFSERV_TBL_CMD

SWE_DIFFSERV_TBL_WR_DATA

180Ch

1811h

1812h

SWE_GLB_INGRESS_CFG

SWE_PORT_INGRESS_CFG

SWE_ADMT_ONLY_VLAN

SWE_PORT_STATE

1840h

1841h

1842h

1843h

SWE_PRI_TO_QUE

1845h

SWE_PORT_MIRROR

SWE_INGRESS_PORT_TYP

1846h

1847h

SWE_BCST_THROT

SWE_ADMT_N_MEMBER

SWE_INGRESS_RATE_CFG

SWE_INGRESS_RATE_CMD

SWE_INGRESS_RATE_WR_DATA

SWE_INGRESS_REGEN_TBL_MII

SWE_INGRESS_REGEN_TBL_1

SWE_INGRESS_REGEN_TBL_2

1848h

1849h

184Ah

184Bh

184Dh

1855h

1856h

1857h

SWE_IMR

1880h

Buffer Manager (BM) CSRs

1C00h

BM_CFG

298h

29Ch

2A0h

BM_DROP_LVL

BM_FC_PAUSE_LVL

1C01h

1C02h

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Table 14.3 Switch Fabric CSR to SWITCH_CSR_DIRECT_DATA Address Range Map (continued)

SWITCH FABRIC CSR

SWITCH_CSR_DIRECT_DATA

ADDRESS

BM_FC_RESUME_LVL

BM_BCST_LVL

1C03h

1C04h

1C09h

1C0Ah

1C0Ch

1C0Dh

1C0Eh

1C0Fh

1C10h

1C11h

1C12h

1C13h

1C14h

1C15h

1C20h

2A4h

2A8h

2ACh

2B0h

2B4h

2B8h

2BCh

2C0h

2C4h

2C8h

2CCh

2D0h

2D4h

2D8h

2DCh

BM_RNDM_DSCRD_TBL_CMD

BM_RNDM_DSCRD_TBL_WDATA

BM_EGRSS_PORT_TYPE

BM_EGRSS_RATE_00_01

BM_EGRSS_RATE_02_03

BM_EGRSS_RATE_10_11

BM_EGRSS_RATE_12_13

BM_EGRSS_RATE_20_21

BM_EGRSS_RATE_22_23

BM_VLAN_MII

BM_VLAN_1

BM_VLAN_2

BM_IMR

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14.2.7

PHY Management Interface (PMI)

The PMI registers are used (by the EEPROM Loader only) to indirectly access the PHY registers.

Refer to Section 14.4, "Ethernet PHY Control and Status Registers," on page 285 for additional

information on the PHY registers.

Note: These registers are only accessible by the EEPROM Loader and NOT by the Host bus. Refer

to Section 10.2.4, "EEPROM Loader," on page 149 for additional information.

14.2.7.1

PHY Management Interface Data Register (PMI_DATA)

Offset:

0A4h

EEPROM Loader

Access Only

Size:

32 bits

This register is used in conjunction with the PHY Management Interface Access Register

(PMI_ACCESS) to perform write operations to the PHYs.

Note: This register is only accessible by the EEPROM Loader and NOT by the Host bus. Refer to

Section 10.2.4, "EEPROM Loader," on page 149 for additional information.

BITS

DESCRIPTION

TYPE

DEFAULT

31:16

15:0

RESERVED

MII Data

00000000h

This field contains the value written to the PHYs. For a write operation, this

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14.2.7.2

PHY Management Interface Access Register (PMI_ACCESS)

Offset:

0A8h

EEPROM Loader

Access Only

Size:

32 bits

This register is used to control the management cycles to the PHYs. A PHY access is initiated when

this register is written. This register is used in conjunction with the PHY Management Interface Data

Note: This register is only accessible by the EEPROM Loader and NOT by the Host bus. Refer to

Section 10.2.4, "EEPROM Loader," on page 149 for additional information.

BITS

DESCRIPTION

TYPE

DEFAULT

31:16

15:11

RESERVED

PHY Address (PHY_ADDR)

00000b

These bits select the PHY device being accessed. Refer to Section 7.1.1,

"PHY Addressing," on page 82 for information on PHY address

assignments.

10:6

MII Register Index (MIIRINDA)

00000b

These bits select the desired MII register in the PHY. Refer to Section 14.4,

"Ethernet PHY Control and Status Registers," on page 285 for detailed

descriptions on all PHY registers.

5:2

RESERVED

Note:

This bit must always be written with a value of 1.

RESERVED

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14.2.8

Virtual PHY

This section details the Virtual PHY System CSR’s. These registers provide status and control

information similar to that of a real PHY while maintaining IEEE 802.3 compatibility. The Virtual PHY

registers are addressable via the memory map, as described in T a ble 14.1, as well as serially via the

MII management protocol (IEEE 802.3 clause 22). When accessed serially, these registers are

accessed indirectly through the Host MAC MII Access Register (HMAC_MII_ACC) and Host MAC MII

Data Register (HMAC_MII_DATA) via the MII serial management protocol specified in IEEE 802.3

clause 22. When being accessed serially, the Virtual PHY will respond when the PHY address equals

the address assigned by the phy_addr_sel_strap configuration strap, as defined in Section 7.1.1, "PHY

Addressing," on page 82. A list of all Virtual PHY register indexes for serial access can be seen in

T a ble 14.4. For more information on the Virtual PHY access modes, refer to section Section 14.4. For

Virtual PHY functionality and operation information, see Section 7.3, "Virtual PH Y ," on page 96.

Note: All Virtual PHY registers follow the IEEE 802.3 (clause 22.2.4) specified MII management

specified register index (in decimal) is included under the LAN9312 memory mapped offset of

each Virtual PHY register as a reference. For additional information, refer to the IEEE 802.3

Specification.

Note: When serially accessed, the Virtual PHY registers are only 16-bits wide, as is standard for MII

management of PHY’s.

Table 14.4 Virtual PHY MII Serially Adressable Register Index

INDEX #

SYMBOL

VPHY_BASIC_CTRL

VPHY_BASIC_STATUS

VPHY_ID_MSB

Virtual PHY Basic Control Register, Section 14.2.8.1

Virtual PHY Basic Status Register, Section 14.2.8.2

Virtual PHY Identification MSB Register, Section 14.2.8.3

Virtual PHY Identification LSB Register, Section 14.2.8.4

VPHY_ID_LSB

VPHY_AN_ADV

Virtual PHY Auto-Negotiation Advertisement Register,

Section 14.2.8.5

VPHY_AN_LP_BASE_ABILITY

Virtual PHY Auto-Negotiation Link Partner Base Page Ability

VPHY_AN_EXP

Virtual PHY Auto-Negotiation Expansion Register,

Section 14.2.8.7

VPHY_SPEC_CTRL_STATUS

Virtual PHY Special Control/Status Register, Section 14.2.8.8

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14.2.8.1

Virtual PHY Basic Control Register (VPHY_BASIC_CTRL)

Offset:

Index (decimal):

1C0h

Size:

32 bits

This read/write register is used to configure the Virtual PHY.

Note: This register is re-written in its entirety by the EEPROM Loader following the release or reset

or a RELOAD command. Refer to Section 10.2.4, "EEPROM Loader," on page 149 for more

information.

BITS

DESCRIPTION

TYPE

DEFAULT

31:16

RESERVED

(See Note 14.16)

Reset (VPHY_RST)

R/W

When set, this bit resets all the Virtual PHY registers to their default state.

This bit is self clearing.

0: Normal Operation

1: Reset

Loopback (VPHY_LOOPBACK)

R/W

This bit enables/disables the loopback mode. When enabled, transmissions

from the Host MAC are not sent to the switch fabric. Instead, they are looped

back onto the receive path.

0: Loopback mode disabled (normal operation)

1: Loopback mode enabled

Speed Select LSB (VPHY_SPEED_SEL_LSB)

This bit is used to set the speed of the Virtual PHY when the Auto-

Negotiation (VPHY_AN) bit is disabled.

R/W

0: 10 Mbps

1: 100 Mbps

Auto-Negotiation (VPHY_AN)

This bit enables/disables Auto-Negotiation. When enabled, the Speed Select

LSB (VPHY_SPEED_SEL_LSB) and Duplex Mode (VPHY_DUPLEX) bits

are overridden.

0: Auto-Negotiation disabled

1: Auto-Negotiation enabled

Power Down (VPHY_PWR_DWN)

R/W

This bit is not used by the Virtual PHY and has no effect.

Isolate (VPHY_ISO)

This bit is not used by the Virtual PHY and has no effect.

Restart Auto-Negotiation (VPHY_RST_AN)

When set, this bit updates the emulated Auto-Negotiation results.

R/W

0: Normal operation

1: Auto-Negotiation restarted

Duplex Mode (VPHY_DUPLEX)

This bit is used to set the duplex when the Auto-Negotiation (VPHY_AN) bit

is disabled.

R/W

0: Half Duplex

1: Full Duplex

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BITS

DESCRIPTION

Collision Test (VPHY_COL_TEST)

This bit enables/disables the collision test mode. When set, the collision

signal to the Host MAC is active during transmission from the Host MAC.

TYPE

DEFAULT

R/W

Note:

It is recommended that this bit be used only when in loopback

mode.

0: Collision test mode disabled

1: Collision test mode enabled

Speed Select MSB (VPHY_SPEED_SEL_MSB)

This bit is not used by the Virtual PHY and has no effect. The value returned

is always 0.

5:0

RESERVED

Note 14.16 The reserved bits 31-16 are used to pad the register to 32-bits so that each register is on

a DWORD boundary. When accessed serially (through the MII management protocol), the

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14.2.8.2

Virtual PHY Basic Status Register (VPHY_BASIC_STATUS)

Offset:

Index (decimal):

1C4h

Size:

32 bits

This register is used to monitor the status of the Virtual PHY.

BITS

DESCRIPTION

TYPE

DEFAULT

31:16

RESERVED

(See Note 14.17)

100BASE-T4

This bit displays the status of 100BASE-T4 compatibility.

Note 14.18

0: PHY not able to perform 100BASE-T4

1: PHY able to perform 100BASE-T4

100BASE-X Full Duplex

This bit displays the status of 100BASE-X full duplex compatibility.

0: PHY not able to perform 100BASE-X full duplex

1: PHY able to perform 100BASE-X full duplex

100BASE-X Half Duplex

This bit displays the status of 100BASE-X half duplex compatibility.

0: PHY not able to perform 100BASE-X half duplex

1: PHY able to perform 100BASE-X half duplex

10BASE-T Full Duplex

This bit displays the status of 10BASE-T full duplex compatibility.

0: PHY not able to perform 10BASE-T full duplex

1: PHY able to perform 10BASE-T full duplex

10BASE-T Half Duplex

This bit displays the status of 10BASE-T half duplex compatibility.

0: PHY not able to perform 10BASE-T half duplex

1: PHY able to perform 10BASE-T half duplex

100BASE-T2 Full Duplex

This bit displays the status of 100BASE-T2 full duplex compatibility.

Note 14.18

0: PHY not able to perform 100BASE-T2 full duplex

1: PHY able to perform 100BASE-T2 full duplex

100BASE-T2 Half Duplex

This bit displays the status of 100BASE-T2 half duplex compatibility.

Note 14.18

0: PHY not able to perform 100BASE-T2 half duplex

1: PHY able to perform 100BASE-T2 half duplex

Extended Status

This bit displays whether extended status information is in register 15 (per

IEEE 802.3 clause 22.2.4).

Note 14.19

0: No extended status information in Register 15

1: Extended status information in Register 15

RESERVED

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BITS

DESCRIPTION

TYPE

DEFAULT

MF Preamble Suppression

This bit indicates whether the Virtual PHY accepts management frames with

the preamble suppressed.

0: Management frames with preamble suppressed not accepted

1: Management frames with preamble suppressed accepted

Auto-Negotiation Complete

This bit indicates the status of the Auto-Negotiation process.

Note 14.20

0: Auto-Negotiation process not completed

1: Auto-Negotiation process completed

Remote Fault

This bit indicates if a remote fault condition has been detected.

Note 14.21

0: No remote fault condition detected

1: Remote fault condition detected

Auto-Negotiation Ability

This bit indicates the status of the Virtual PHY’s auto-negotiation.

0: Virtual PHY is unable to perform auto-negotiation

1: Virtual PHY is able to perform auto-negotiation

Link Status

This bit indicates the status of the link.

Note 14.21

0: Link is down

1: Link is up

Jabber Detect

This bit indicates the status of the jabber condition.

Note 14.21

0: No jabber condition detected

1: Jabber condition detected

Extended Capability

This bit indicates whether extended register capability is supported.

Note 14.22

0: Basic register set capabilities only

1: Extended register set capabilities

Note 14.17 The reserved bits 31-16 are used to pad the register to 32-bits so that each register is on

a DWORD boundary. When accessed serially (through the MII management protocol), the

Note 14.18 The Virtual PHY supports 100BASE-X (half and full duplex) and 10BASE-T (half and full

duplex) only. All other modes will always return as 0 (unable to perform).

Note 14.19 The Virtual PHY does not support Register 15 or 1000 Mb/s operation. Thus this bit is

always returned as 0.

Note 14.20 The Auto-Negotiation Complete bit is first cleared on a reset, but set shortly after (when

the Auto-Negotiation process is run). Refer to Section 7.3.1, "Virtual PHY Auto-

Negotiation," on page 96 for additional details.

Note 14.21 The Virtual PHY never has remote faults, its link is always up, and does not detect jabber.

Note 14.22 The VIrtual PHY supports basic and some extended register capability. The Virtual PHY

supports Registers 0-6 (per the IEEE 802.3 specification).

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14.2.8.3

Virtual PHY Identification MSB Register (VPHY_ID_MSB)

Offset:

Index (decimal):

1C8h

Size:

32 bits

This read/write register contains the MSB of the Virtual PHY Organizationally Unique Identifier (OUI).

The LSB of the Virtual PHY OUI is contained in the Virtual PHY Identification LSB Register

(VPHY_ID_LSB).

BITS

DESCRIPTION

TYPE

DEFAULT

31:16

RESERVED

(See Note 14.23)

15:0

PHY ID

R/W

0000h

This field contains the MSB of the Virtual PHY OUI (Note 14.24).

Note 14.23 The reserved bits 31-16 are used to pad the register to 32-bits so that each register is on

a DWORD boundary. When accessed serially (through the MII management protocol), the

Note 14.24 IEEE allows a value of zero in each of the 32-bits of the PHY Identifier.

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14.2.8.4

Virtual PHY Identification LSB Register (VPHY_ID_LSB)

Offset:

Index (decimal):

1CCh

Size:

32 bits

This read/write register contains the LSB of the Virtual PHY Organizationally Unique Identifier (OUI).

The MSB of the Virtual PHY OUI is contained in the Virtual PHY Identification MSB Register

(VPHY_ID_MSB).

BITS

DESCRIPTION

TYPE

DEFAULT

31:16

RESERVED

(See Note 14.25)

15:10

9:4

PHY ID

R/W

00h

This field contains the lower 6-bits of the Virtual PHY OUI (Note 14.26).

Model Number

This field contains the 6-bit manufacturer’s model number of the Virtual PHY

(Note 14.26).

3:0

Revision Number

R/W

This field contain the 4-bit manufacturer’s revision number of the Virtual PHY

(Note 14.26).

Note 14.25 The reserved bits 31-16 are used to pad the register to 32-bits so that each register is on

a DWORD boundary. When accessed serially (through the MII management protocol), the

Note 14.26 IEEE allows a value of zero in each of the 32-bits of the PHY Identifier.

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14.2.8.5

Virtual PHY Auto-Negotiation Advertisement Register (VPHY_AN_ADV)

Offset:

Index (decimal):

1D0h

Size:

32 bits

This read/write register contains the advertised ability of the Virtual PHY and is used in the Auto-

Negotiation process with the link partner.

Note: This register is re-written in its entirety by the EEPROM Loader following the release or reset

or a RELOAD command. Refer to Section 10.2.4, "EEPROM Loader," on page 149 for more

information.

BITS

DESCRIPTION

TYPE

DEFAULT

31:16

RESERVED

(See Note 14.27)

This bit determines the advertised next page capability and is always 0.

Note 14.28

0: Virtual PHY does not advertise next page capability

1: Virtual PHY advertises next page capability

RESERVED

Remote Fault

This bit is not used since there is no physical link partner.

Note 14.29

RESERVED

Asymmetric Pause

This bit determines the advertised asymmetric pause capability.

R/W

0: No Asymmetric PAUSE toward link partner advertised

1: Asymmetric PAUSE toward link partner advertised

Pause

R/W

Note 14.30

This bit determines the advertised symmetric pause capability.

0: No Symmetric PAUSE toward link partner advertised

1: Symmetric PAUSE toward link partner advertised

100BASE-T4

This bit determines the advertised 100BASE-T4 capability and is always 0.

Note 14.31

0: 100BASE-T4 ability not advertised

1: 100BASE-T4 ability advertised

100BASE-X Full Duplex

R/W

This bit determines the advertised 100BASE-X full duplex capability.

0: 100BASE-X full duplex ability not advertised

1: 100BASE-X full duplex ability advertised

100BASE-X Half Duplex

This bit determines the advertised 100BASE-X half duplex capability.

0: 100BASE-X half duplex ability not advertised

1: 100BASE-X half duplex ability advertised

10BASE-T Full Duplex

This bit determines the advertised 10BASE-T full duplex capability.

0: 10BASE-T full duplex ability not advertised

1: 10BASE-T full duplex ability advertised

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BITS

DESCRIPTION

TYPE

DEFAULT

10BASE-T Half Duplex

This bit determines the advertised 10BASE-T half duplex capability.

R/W

0: 10BASE-T half duplex ability not advertised

1: 10BASE-T half duplex ability advertised

4:0

Selector Field

R/W

00001b

Note 14.32

This field identifies the type of message being sent by Auto-Negotiation.

00001: IEEE 802.3

Note 14.27 The reserved bits 31-16 are used to pad the register to 32-bits so that each register is on

a DWORD boundary. When accessed serially (through the MII management protocol), the

Note 14.28 The Virtual PHY does not support next page capability. This bit value will always be 0.

Note 14.29 The Remote Fault bit is not useful since there is no actual link partner to send a fault to.

Note 14.30 The Pause bit defaults to 1 if the manual_FC_strap_mii strap is low, and 0 if the

manual_FC_strap_mii strap is high. Configuration strap values are latched upon the de-

assertion of a chip-level reset as described in Section 4.2.4, "Configuration Straps," on

page 40.

Note 14.31 Virtual 100BASE-T4 is not supported.

Note 14.32 The Virtual PHY supports only IEEE 802.3. Only a value of 00001b should be used in this

field.

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14.2.8.6

Virtual PHY Auto-Negotiation Link Partner Base Page Ability Register (VPHY_AN_LP_BASE_ABILITY)

Offset:

Index (decimal):

1D4h

Size:

32 bits

This read-only register contains the advertised ability of the link partner’s PHY and is used in the Auto-

Negotiation process with the Virtual PHY. Because the Virtual PHY does not physically connect to an

actual link partner, the values in this register are emulated as described below.

BITS

DESCRIPTION

TYPE

DEFAULT

31:16

RESERVED

(See Note 14.33)

This bit indicates the emulated link partner PHY next page capability and is

always 0.

0: Link partner PHY does not advertise next page capability

1: Link partner PHY advertises next page capability

Acknowledge

This bit indicates whether the link code word has been received from the

partner and is always 1.

0: Link code word not yet received from partner

1: Link code word received from partner

Remote Fault

Since there is no physical link partner, this bit is not used and is always

returned as 0.

RESERVED

Asymmetric Pause

This bit indicates the emulated link partner PHY asymmetric pause

capability.

Note 14.35

0: No Asymmetric PAUSE toward link partner

1: Asymmetric PAUSE toward link partner

Pause

Note 14.35

This bit indicates the emulated link partner PHY symmetric pause capability.

0: No Symmetric PAUSE toward link partner

1: Symmetric PAUSE toward link partner

100BASE-T4

This bit indicates the emulated link partner PHY 100BASE-T4 capability.

This bit is always 0.

the Reset Control Register (RESET_CTL) or Power Management Control Register

0: 100BASE-T4 ability not supported

1: 100BASE-T4 ability supported

100BASE-X Full Duplex

This bit indicates the emulated link partner PHY 100BASE-X full duplex

capability.

Note 14.36

0: 100BASE-X full duplex ability not supported

1: 100BASE-X full duplex ability supported

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BITS

DESCRIPTION

TYPE

DEFAULT

100BASE-X Half Duplex

This bit indicates the emulated link partner PHY 100BASE-X half duplex

capability.

Note 14.36

0: 100BASE-X half duplex ability not supported

1: 100BASE-X half duplex ability supported

10BASE-T Full Duplex

Note 14.36

00001b

This bit indicates the emulated link partner PHY 10BASE-T full duplex

capability.

0: 10BASE-T full duplex ability not supported

1: 10BASE-T full duplex ability supported

10BASE-T Half Duplex

This bit indicates the emulated link partner PHY 10BASE-T half duplex

capability.

0: 10BASE-T half duplex ability not supported

1: 10BASE-T half duplex ability supported

4:0

Selector Field

This field identifies the type of message being sent by Auto-Negotiation.

00001: IEEE 802.3

Note 14.33 The reserved bits 31-16 are used to pad the register to 32-bits so that each register is on

a DWORD boundary. When accessed serially (through the MII management protocol), the

Note 14.34 The emulated link partner does not support next page, always instantly sends its link code

word, never sends a fault, and does not support 100BASE-T4.

Note 14.35 The emulated link partner’s asymmetric/symmetric pause ability is based upon the values

of the Asymmetric Pause and Pause bits of the Virtual PHY Auto-Negotiation

Advertisement Register (VPHY_AN_ADV). Thus the emulated link partner always

accommodates the request of the Virtual PHY, as shown in T a ble 14.5. See Section 7.3.1,

"Virtual PHY Auto-Negotiation," on page 96 for additional information.

Table 14.5 Emulated Link Partner Pause Flow Control Ability Default Values

VPHY Symmetric

Pause

(register 4.10)

VPHY Asymmetric

Pause

(register 4.11)

Link Partner

Symmetric Pause

(register 5.10)

Link Partner

AsymmetricPause

(register 5.11)

No Flow Control Enabled

Symmetric Pause

Asymmetric Pause Towards

Switch

Asymmetric Pause Towards MAC

Note 14.36 The emulated link partner always has the following capabilities: 100BASE-X full duplex,

100BASE-X half duplex, 10BASE-T full duplex, and 10BASE-T half duplex. For more

information on the Virtual PHY auto-negotiation, see Section 7.3.1, "Virtual PHY Auto-

Negotiation," on page 96.

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14.2.8.7

Virtual PHY Auto-Negotiation Expansion Register (VPHY_AN_EXP)

Offset:

Index (decimal):

1D8h

Size:

32 bits

This register is used in the Auto-Negotiation process.

BITS

DESCRIPTION

TYPE

DEFAULT

31:16

RESERVED

(See Note 14.37)

15:5

RESERVED

Parallel Detection Fault

This bit indicates whether a Parallel Detection Fault has been detected. This

bit is always 0.

Note 14.38

0: A fault hasn’t been detected via the Parallel Detection function

1: A fault has been detected via the Parallel Detection function

Link Partner Next Page Able

This bit indicates whether the link partner has next page ability. This bit is

always 0.

Note 14.39

0: Link partner does not contain next page capability

1: Link partner contains next page capability

Local Device Next Page Able

This bit indicates whether the local device has next page ability. This bit is

always 0.

Note 14.39

0: Local device does not contain next page capability

1: Local device contains next page capability

Page Received

RO/LH

This bit indicates the reception of a new page.

Note 14.40

0: A new page has not been received

1: A new page has been received

Link Partner Auto-Negotiation Able

This bit indicates the Auto-negotiation ability of the link partner.

Note 14.41

0: Link partner is not Auto-Negotiation able

1: Link partner is Auto-Negotiation able

Note 14.37 The reserved bits 31-16 are used to pad the register to 32-bits so that each register is on

a DWORD boundary. When accessed serially (through the MII management protocol), the

Note 14.38 Since the Virtual PHY link partner is emulated, there is never a Parallel Detection Fault

and this bit is always 0.

Note 14.39 Next page ability is not supported by the Virtual PHY or emulated link partner.

Note 14.40 The page received bit is clear when read. It is first cleared on reset, but set shortly

thereafter when the Auto-Negotiation process is run.

Note 14.41 The emulated link partner will show Auto-Negotiation able unless Auto-Negotiation fails (no

common bits between the advertised ability and the link partner ability).

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14.2.8.8

Virtual PHY Special Control/Status Register (VPHY_SPECIAL_CONTROL_STATUS)

Offset:

1DCh

Size:

32 bits

Index (decimal): 31

This read/write register contains a current link speed/duplex indicator and SQE control.

BITS

DESCRIPTION

TYPE

DEFAULT

31:16

RESERVED

(See Note 14.42)

RESERVED

Switch Looopback MII

When set, transmissions from the switch fabric Port 0(Host MAC) are not

sent to the Host MAC. Instead, they are looped back into the switch engine.

R/W

From the MAC viewpoint, this is effectively a FAR LOOPBACK.

If loopback is enabled during half-duplex operation, then the Enable Receive

Own Transmit bit in the Port x MAC Receive Configuration Register

(MAC_RX_CFG_x) must be set for this port. Otherwise, the switch fabric will

ignore receive activity when transmitting in half-duplex mode.

This mode works even if the Isolate bit of the Virtual PHY Basic Control

13:8

RESERVED

Switch Collision Test MII

When set, the collision signal to the switch fabric Port 0(Host MAC) is active

during transmission from the switch engine.

R/W

It is recommended that this bit be used only when using loopback mode.

6:5

4:2

RESERVED

Current Speed/Duplex Indication

This field indicates the current speed and duplex of the Virtual PHY link.

Note 14.43

[4]

[3]

[2]

Speed

Duplex

RESERVED

10Mbps

half-duplex

100Mbps

RESERVED

10Mbps

full-duplex

100Mbps

RESERVED

SQEOFF

R/W

NASR

Note 14.44

Note 14.45

This bit enables/disables the Signal Quality Error (Heartbeat) test.

0: SQE test enabled

1: SQE test disabled

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Note 14.42 The reserved bits 31-16 are used to pad the register to 32-bits so that each register is on

a DWORD boundary. When accessed serially (through the MII management protocol), the

Note 14.43 The default value of this field is the result of the Auto-Negotiation process if the Auto-

Negotiation (VPHY_AN) bit of the V irtual PHY Basic Control Register

(VPHY_BASIC_CTRL) is set. Otherwise, this field reflects the Speed Select LSB

(VPHY_SPEED_SEL_LSB) and Duplex Mode (VPHY_DUPLEX) bit settings of the

VPHY_BASIC_CTRL register. Refer to Section 7.3.1, "Virtual PHY Auto-Negotiation," on

page 96 for information on the Auto-Negotiation determination process of the Virtual PHY.

Note 14.44 Register bits designated as NASR are reset when the Virtual PHY Reset is generated via

(PMT_CTRL). The NASR designation is only applicable when the Reset (VPHY_RST) bit

of the Virtual PHY Basic Control Register (VPHY_BASIC_CTRL) is set.

Note 14.45 The default value of this field is determined via the SQE_test_disable_strap_mii

configuration strap. Refer to Section 4.2.4, "Configuration Straps," on page 40 for

additional information.

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14.2.9

Miscellaneous

This section details the remainder of the System CSR’s. These registers allow for monitoring and

configuration of various LAN9312 functions such as the Chip ID/revision, byte order testing, power

management, hardware configuration, general purpose timer, and free running counter.

14.2.9.1

Chip ID and Revision (ID_REV)

Offset:

050h

Size:

32 bits

This read-only register contains the ID and Revision fields for the LAN9312.

BITS

DESCRIPTION

TYPE

DEFAULT

31:16

Chip ID

This field indicates the chip ID.

9312h

15:0

Chip Revision

This field indicates the design revision.

Note 14.46

Note 14.46 Default value is dependent on device revision.

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14.2.9.2

Byte Order Test Register (BYTE_TEST)

Offset:

064h

Size:

32 bits

This read-only register can be used to determine the byte ordering of the current configuration. Byte

ordering is a function of the host data bus width and endianess. Refer to Section 8.3, "Host Endianess,"

on page 99 for additional information on byte ordering.

Note: This register can be read while the LAN9312 is in the reset or not ready states.

The BYTE_TEST register can optionally be used as a dummy read register when assuring minimum

write-to-read or read-to-read timing. Refer to Section 8.4.2, "Special Restrictions on Back-to Back

Write-Read Cycles," on page 101 and Section 8.4.3, "Special Restrictions on Back-to-Back Read

Cycles," on page 105 for additional information.

BITS

DESCRIPTION

TYPE

DEFAULT

87654321h

31:0

Byte Test (BYTE_TEST)

This field reflects the current byte ordering

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14.2.9.3

Hardware Configuration Register (HW_CFG)

Offset:

074h

Size:

32 bits

This register allows the configuration of various hardware features including TX/RX FIFO sizes, Host

MAC transmit threshold properties, and software reset. A detailed explanation of the allowable settings

for FIFO memory allocation can be found in Section 9.7.3, "FIFO Memory Allocation Configuration,"

on page 121.

Note: This register can be polled while the LAN9312 is in the reset or not ready state (READY bit is

cleared).

BITS

31:28

DESCRIPTION

TYPE

DEFAULT

RESERVED

Device Ready (READY)

When set, this bit indicates that the LAN9312 is ready to be accessed. Upon

power-up, nRST reset, soft reset, or digital reset, the host processor may

interrogate this field as an indication that the LAN9312 has stabilized and is

fully active.

This bit can cause an interrupt if enabled.

Note:

With the exception of the HW_CFG, PMT_CTRL, BYTE_TEST, and

RESET_CTL registers, read access to any internal resources is

forbidden while the READY bit is cleared. Writes to any address

are invalid until this bit is set.

Note:

This bit is identical to bit 0 of the Power Management Control

AMDIX_EN Strap State Port 2

Note 14.47

Note 14.48

This bit reflects the state of the auto_mdix_strap_2 strap that connects to

the PHY. The strap value is loaded with the level of the auto_mdix_strap_2

during reset and can be re-written by the EEPROM Loader. The strap value

can be overridden by bit 15 and 13 of the Port 2 PHY Special Control/Status

Indication Register (Section 14.4.2.10).

AMDIX_EN Strap State Port 1

This bit reflects the state of the auto_mdix_strap_1 strap that connects to

the PHY. The strap value is loaded with the level of the auto_mdix_strap_1

during reset and can be re-written by the EEPROM Loader. The strap value

can be overridden by bit 15 and 13 of the Port 1 PHY Special Control/Status

Indication Register (Section 14.4.2.10).

24:22

RESERVED

R/W

RESERVED - This bit must be written with 0b for proper operation.

Must Be One (MBO). This bit must be set to ‘1’ for normal device operation.

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BITS

DESCRIPTION

TYPE

DEFAULT

19:16

TX FIFO Size (TX_FIF_SZ)

R/W

This field sets the size of the TX FIFOs in 1KB values to a maximum of

14KB. The TX Status FIFO consumes 512 bytes of the space allocated by

TX_FIF_SIZ, and the TX Data FIFO consumes the remaining space

specified by TX_FIF_SZ. The minimum size of the TX FIFOs is 2KB (TX

Data FIFO and Status FIFO combined). The TX Data FIFO is used for both

TX data and TX commands.

The RX Status and Data FIFOs consume the remaining space, which is

equal to 16KB minus TX_FIF_SIZ. See section Section 9.7.3, "FIFO

Memory Allocation Configuration," on page 121 for more information.

15:14

13:12

RESERVED

R/W

RESERVED - This field must be written with 00b for proper operation.

RESERVED

00b

11:1

Soft Reset (SRST)

R/W

Writing 1 generates a software initiated reset to the Host Bus Interface, the

Host MAC, and System CSR’s below address 100h. The System CSR’s are

all reset except for any NASR bits. Soft reset also clears any TX or RX

errors in the Host MAC transmitter and receiver (TXE/RXE). This bit is self-

clearing. In order to reset all values, the Reset Control Register

(RESET_CTL) must be used.

Note:

This bit will read high during assertion of DIGITAL_RST in the

Reset Control Register (RESET_CTL). The LAN9312 must always

be read at least once after power-up or reset to ensure that write

operations function correctly.

Note 14.47 The default value of this field is determined by the configuration strap auto_mdix_strap_2.

See Section 4.2.4, "Configuration Straps," on page 40 for more information.

Note 14.48 The default value of this field is determined by the configuration strap auto_mdix_strap_1.

See Section 4.2.4, "Configuration Straps," on page 40 for more information.

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14.2.9.4

Power Management Control Register (PMT_CTRL)

Offset:

084h

Size:

32 bits

This read-write register controls the power management features and the PME pin of the LAN9312.

The ready state of the LAN9312 can be determined via the Device Ready (READY) bit of this register.

Refer to Section 4.3, "Power Management," on page 46 for additional information.

Note: This register is one of only four registers (the others are HW_CFG, BYTE_TEST, and

RESET_CTL) which can be polled while the LAN9312 is in the reset or not ready state (READY

bit is cleared).

BITS

31:18

DESCRIPTION

TYPE

DEFAULT

RESERVED

Energy-Detect Status Port 2 (ED_STS2)

This bit indicates an energy detect event occurred on the Port 2 PHY.

R/WC

In order to clear this bit, it is required that the event in the PHY be cleared

as well. The event sources are described in Section 4.3, "Power

Management," on page 46.

Energy-Detect Status Port 1 (ED_STS1)

R/WC

R/W

This bit indicates an energy detect event occurred on the Port 1 PHY.

In order to clear this bit, it is required that the event in the PHY be cleared

as well. The event sources are described in Section 4.3, "Power

Management," on page 46.

Energy-Detect Enable Port 2 (ED_EN2)

When set, the PME signal (if enabled via the PME_EN bit) will be asserted

in accordance with the PME_IND bit upon an energy-detect event from Port

2. When set, the PME_INT bit in the Interrupt Status Register (INT_STS) will

also be asserted upon an energy-detect event from Port 2, regardless of the

setting of the PME_EN bit.

Note:

The EDPWRDOWN bit of the Port x PHY Mode Control/Status

must also be set to enable the energy detect feature.

Energy-Detect Enable Port 1 (ED_EN1)

R/W

When set, the PME signal (if enabled via the PME_EN bit) will be asserted

in accordance with the PME_IND bit upon an energy-detect event from Port

1. When set, the PME_INT bit in the Interrupt Status Register (INT_STS) will

also be asserted upon an energy-detect event from Port 1, regardless of the

setting of the PME_EN bit.

Note:

The EDPWRDOWN bit in the Port x PHY Mode Control/Status

must also be set to enable the energy detect feature.

13:11

RESERVED

Virtual PHY Reset (VPHY_RST)

R/W

Writing a 1 to this bit resets the Virtual PHY. When the Virtual PHY is

released from reset, this bit is automatically cleared. All writes to this bit are

ignored while this bit is high.

Wake-On-LAN Enable (WOL_EN)

R/W

When set, the PME signal (if enabled via the PME_EN bit) will be asserted

in accordance with the PME_IND bit upon a WOL event. When set, the

PME_INT bit in the Interrupt Status Register (INT_STS) will also be asserted

upon a WOL event, regardless of the setting of the PME_EN bit.

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BITS

8:7

DESCRIPTION

TYPE

DEFAULT

RESERVED

PME Buffer Type (PME_TYPE)

When this bit is cleared, the PME pin functions as an open-drain buffer for

use in a wired-or configuration. When set, the PME pin is a push-pull driver.

R/W

NASR

Note:

When PME is configured as an open-drain output, the PME_POL

field of this register is ignored and the output is always active low.

0: PME pin open-drain output

1: PME pin push-pull driver

Wake On LAN Status (WOL_STS)

This bit indicates that a wake-up frame or magic packet was detected by the

Host MAC.

R/WC

In order to clear this bit, it is required that the event in the Host MAC be

cleared as well. The event sources are described in Section 4.3, "Power

Management," on page 46.

RESERVED

PME Indication (PME_IND)

R/W

The PME signal can be configured as a pulsed output or a static signal,

which is asserted upon detection of a wake-up event. When set, the PME

signal will pulse active for 50mS upon detection of a wake-up event. When

cleared, the PME signal is driven continuously upon detection of a wake-up

event.

0: PME 50mS pulse on detection of event

1: PME driven continuously on detection of event

The PME signal can be deactivated by clearing the WOL_STS bit or by

clearing the appropriate enable.

PME Polarity (PME_POL)

R/W

NASR

This bit controls the polarity of the PME signal. When set, the PME output

is an active high signal. When cleared, it is active low.

Note:

When PME is configured as an open-drain output, this field is

ignored and the output is always active low.

0: PME active low

1: PME active high

PME Enable (PME_EN)

When set, this bit enables the external PME signal pin. When cleared, the

external PME signal is disabled.

R/W

Note:

This bit does not affect the PME_INT interrupt bit of the Interrupt

Status Register (INT_STS).

0: PME pin disabled

1: PME pin enabled

Device Ready (READY)

When set, this bit indicates that the LAN9312 is ready to be accessed. Upon

power-up, nRST reset, soft reset, or digital reset, the host processor may

interrogate this field as an indication that the LAN9312 has stabilized and is

fully active.

This bit can cause an interrupt if enabled.

Note:

With the exception of the HW_CFG, PMT_CTRL, BYTE_TEST, and

RESET_CTL registers, read access to any internal resources is

forbidden while the READY bit is cleared. Writes to any address

are invalid until this bit is set.

Note:

This bit is identical to bit 27 of the Hardware Configuration Register

(HW_CFG).

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14.2.9.5

General Purpose Timer Configuration Register (GPT_CFG)

Offset:

08Ch

Size:

32 bits

This read/write register configures the LAN9312 General Purpose Timer (GPT). The GPT can be

configured to generate host interrupts at the interval defined in this register. The current value of the

GPT can be monitored via the General Purpose Timer Count Register (GPT_CNT). Refer to Section

12.1, "General Purpose Timer," on page 161 for additional information.

BITS

31:30

DESCRIPTION

TYPE

DEFAULT

RESERVED

General Purpose Timer Enable (TIMER_EN)

R/W

This bit enables the GPT. When set, the GPT enters the run state. When

cleared, the GPT is halted. On the 1 to 0 transition of this bit, the

GPT_LOAD field of this register will be preset to FFFFh.

0: GPT Disabled

1: GPT Enabled

28:16

15:0

RESERVED

General Purpose TImer Pre-Load (GPT_LOAD)

This value is pre-loaded into the GPT. This is the starting value of the GPT.

The timer will begin decrementing from this value when enabled.

R/W

FFFFh

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14.2.9.6

General Purpose Timer Count Register (GPT_CNT)

Offset:

090h

Size:

32 bits

This read-only register reflects the current general purpose timer (GPT) value. The register should be

used in conjunction with the General Purpose Timer Configuration Register (GPT_CFG) to configure

and monitor the GPT. Refer to Section 12.1, "General Purpose Timer," on page 161 for additional

information.

BITS

31:16

15:0

DESCRIPTION

TYPE

DEFAULT

RESERVED

General Purpose Timer Current Count (GPT_CNT)

This 16-bit field represents the current value of the GPT.

FFFFh

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14.2.9.7

Free Running 25MHz Counter Register (FREE_RUN)

Offset:

09Ch

Size:

32 bits

This read-only register reflects the current value of the free-running 25MHz counter. Refer to Section

12.2, "Free-Running Clock," on page 161 for additional information.

BITS

DESCRIPTION

Free Running Counter (FR_CNT)

TYPE

DEFAULT

31:0

00000000h

This field reflects the current value of the free-running 32-bit counter. At

reset, the counter starts at zero and is incremented by one every 25MHz

cycle. When the maximum count has been reached, the counter will rollover

to zero and continue counting.

Note:

The free running counter can take up to 160nS to clear after a reset

event.

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14.2.9.8

Reset Control Register (RESET_CTL)

Offset:

This register contains software controlled resets.

Note: This register can be read while the LAN9312 is in the reset or not ready states.

1F8h

Size:

32 bits

BITS

31:4

DESCRIPTION

TYPE

DEFAULT

RESERVED

Virtual PHY Reset (VPHY_RST)

R/W

Setting this bit resets the Virtual PHY. When the Virtual PHY is released from

reset, this bit is automatically cleared. All writes to this bit are ignored while

this bit is set.

Note:

This bit is not accessible via the EEPROM Loader.

Port 2 PHY Reset (PHY2_RST)

R/W

Setting this bit resets the Port 2 PHY. The internal logic automatically holds

the PHY reset for a minimum of 102uS. When the Port 2 PHY is released

from reset, this bit is automatically cleared. All writes to this bit are ignored

while this bit is set.

Note:

This bit is not accessible via the EEPROM Loader.

Port 1 PHY Reset (PHY1_RST)

R/W

Setting this bit resets the Port 1 PHY. The internal logic automatically holds

the PHY reset for a minimum of 102uS. When the Port 1 PHY is released

from reset, this bit is automatically cleared. All writes to this bit are ignored

while this bit is set.

Note:

This bit is not accessible via the EEPROM Loader.

Digital Reset (DIGITAL_RST)

R/W

Setting this bit resets the complete chip except the PLL, Virtual PHY, Port 1

PHY, and Port 2 PHY. The EEPROM Loader will automatically reload the

configuration following this reset, but will not reset the Virtual PHY, Port 1

PHY, or Port 2 PHY. If desired, the above PHY resets can be issued once

the device is configured. All system CSRs are reset except for any NASR

type bits. Any in progress EEPROM commands (including RELOAD) are

terminated.

When the chip is released from reset, this bit is automatically cleared. This

bit should be polled to determine when the reset is complete. All writes to

this bit are ignored while this bit is set.

Note:

The LAN9312must always be read at least once after power-up or

reset to ensure that write operations function properly.

Note:

This bit is not accessible via the EEPROM Loader.

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14.3

Host MAC Control and Status Registers

This section details the Host MAC System CSR’s. These registers are located in the Host MAC and

are accessed indirectly via the HBI system CSR’s. T a ble 14.6 lists Host MAC registers that are

accessible through the indexing method using the Host MAC CSR Interface Command Register

(MAC_CSR_CMD) and Host MAC CSR Interface Data Register (MAC_CSR_DATA).

The Host MAC registers allow configuration of the various Host MAC parameters including the Host

MAC address, flow control, multicast hash table, and wake-up configuration. The Host MAC CSR’s

also provide serial access to the PHYs via the registers HMAC_MII_ACC and HMAC_MII_DATA.

These registers allow access to the 10/100 Ethernet PHY registers and the switch engine (via Port 0).

Table 14.6 Host MAC Adressable Registers

INDEX #

SYMBOL

Reserved for Future Use

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

RESERVED

HMAC_CR

Host MAC Control Register, Section 14.3.1

HMAC_ADDRH

HMAC_ADDRL

HMAC_HASHH

HMAC_HASHL

HMAC_MII_ACC

HMAC_MII_DATA

HMAC_FLOW

HMAC_VLAN1

HMAC_VLAN2

HMAC_WUFF

HMAC_WUCSR

Host MAC Address High Register, Section 14.3.2

Host MAC Address Low Register, Section 14.3.3

Host MAC Multicast Hash Table High Register, Section 14.3.4

Host MAC Multicast Hash Table Low Register, Section 14.3.5

Host MAC MII Access Register, Section 14.3.6

Host MAC MII Data Register, Section 14.3.7

Host MAC Flow Control Register, Section 14.3.8

Host MAC VLAN1 Tag Register, Section 14.3.9

Host MAC VLAN2 Tag Register, Section 14.3.10

Host MAC Wake-up Frame Filter Register, Section 14.3.11

Host MAC Wake-up Control and Status Register,

Section 14.3.12

0Dh-FFh

RESERVED

Reserved for Future Use

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14.3.1

Host MAC Control Register (HMAC_CR)

Offset:

Size:

32 bits

This read/write register establishes the RX and TX operation modes and controls for address filtering

and packet filtering. Refer to Chapter 9, "Host MAC," on page 112 for additional information.

Bits 19-15, 13, and 11 determine if the Host MAC accepts the packets from the switch fabric. The

switch fabric address table and configuration determine which packets get sent to the Host MAC.

BITS

DESCRIPTION

TYPE

DEFAULT

Receive All Mode (RXALL)

R/W

When set, all incoming packets will be received and passed on to the

address filtering function for processing of the selected filtering mode on the

received frame. Address filtering then occurs and is reported in Receive

Status. When cleared, only frames that pass Destination Address filtering

will be sent to the application.

30:24

RESERVED

Disable Receive Own (RCVOWN)

R/W

When set, the Host MAC disables the reception of frames when TXEN (bit

3) is asserted. The Host MAC blocks the transmitted frame on the receive

path. When cleared, the Host MAC receives all packets, including those

transmitted by the Host MAC. This bit should be cleared when the Full

Duplex Mode bit is set.

RESERVED

Loopback operation Mode (LOOPBK)

R/W

Selects the loop back operation modes for the Host MAC. This field is only

valid for full duplex mode. In internal loopback mode, the TX frame is

received by the internal MII interface, and sent back to the Host MAC

without being sent to the switch fabric.

0: Normal Operation. Loopback disabled.

1: Loopback enabled

Note:

When enabling or disabling the loopback mode it can take up to

10μs for the mode change to occur. The transmitter and receiver

must be stopped and disabled when modifying the LOOPBK bit.

The transmitter or receiver should not be enabled within10μs of

modifying the LOOPBK bit.

Full Duplex Mode (FDPX)

R/W

When set, the Host MAC operates in Full-Duplex mode, in which it can

transmit and receive simultaneously.

Pass All Multicast (MCPAS)

When set, indicates that all incoming frames with a Multicast destination

address (first bit in the destination address field is 1) are received. Incoming

frames with physical address (Individual Address/Unicast) destinations are

filtered and received only if the address matches the Host MAC Address.

Promiscuous Mode (PRMS)

R/W

When set, indicates that any incoming frame is received regardless of its

destination address.

Inverse filtering (INVFILT)

When set, the address check function operates in inverse filtering mode.

This is valid only during Perfect filtering mode. Refer to Section 9.4.4,

"Inverse Filtering," on page 116 for additional information.

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BITS

DESCRIPTION

Pass Bad Frames (PASSBAD)

TYPE

DEFAULT

R/W

When set, all incoming frames that passed address filtering are received,

including runt frames and collided frames. Refer to Section 9.4, "Address

Filtering," on page 114 for additional information.

Hash Only Filtering mode (HO)

R/W

When set, the address check Function operates in the Imperfect address

filtering mode for both physical and multicast addresses. Refer to Section

9.4.2, "Hash Only Filtering," on page 115 for additional information.

RESERVED

Hash/Perfect Filtering Mode (HPFILT)

R/W

When cleared (0), the LAN9312 will implement a perfect address filter on

incoming frames according the address specified in the Host MAC address

registers (Host MAC Address High Register (HMAC_ADDRH) and Host

MAC Address Low Register (HMAC_ADDRL)).

When set (1), the address check function performs imperfect address

filtering of multicast incoming frames according to the hash table specified

in the multicast hash table register. If the Hash Only Filtering mode (HO) bit

15 is set, then the physical (IA) addresses are also imperfect filtered. If the

Hash Only Filtering mode (HO) bit is cleared, then the IA addresses are

perfect address filtered according to the MAC Address register Refer to

Section 9.4.3, "Hash Perfect Filtering," on page 115 for additional

information.

RESERVED

Disable Broadcast Frames (BCAST)

When set, disables the reception of broadcast frames. When cleared,

forwards all broadcast frames to the application.

R/W

Note:

When wake-up frame detection is enabled via the WUEN bit of the

Host MAC Wake-up Control and Status Register (HMAC_WUCSR),

a broadcast wake-up frame will wake-up the device despite the

state of this bit.

Disable Retry (DISRTY)

R/W

When set, the Host MAC attempts only one transmission. When a collision

is seen on the bus, the Host MAC ignores the current frame and goes to the

next frame and a retry error is reported in the Transmit status. When reset,

the Host MAC attempts 16 transmissions before signaling a retry error.

RESERVED

Automatic Pad Stripping (PADSTR)

R/W

When set, the Host MAC strips the pad field on all incoming frames, if the

length field is less than 46 bytes. The FCS field is also stripped, since it is

computed at the transmitting station based on the data and pad field

characters, and is invalid for a received frame that has had the pad

characters stripped. Receive frames with a 46-byte or greater length field

are passed to the application unmodified (FCS is not stripped). When

cleared, the Host MAC passes all incoming frames to the host unmodified.

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BITS

DESCRIPTION

TYPE

DEFAULT

7:6

BackOff Limit (BOLMT)

R/W

The BOLMT bits allow the user to set the back-off limit in a relaxed or

aggressive mode. According to IEEE 802.3, the Host MAC has to wait for a

random number [r] of slot-times(see note) after it detects a collision, where:

(eq.1)0 < r < K

The exponent K is dependent on how many times the current frame to be

transmitted has been retried, as follows:

(eq.2)K = min (n, 10) where n is the current number of retries.

If a frame has been retried three times, then K = 3 and r= 8 slot-times

maximum. If it has been retried 12 times, then K = 10, and r = 1024 slot-

times maximum.

An LFSR (linear feedback shift register) 20-bit counter emulates a 20 bit

random number generator, from which r is obtained. Once a collision is

detected, the number of the current retry of the current frame is used to

obtain K (eq.2). This value of K translates into the number of bits to use from

the LFSR counter. If the value of K is 3, the Host MAC takes the value in

the first three bits of the LFSR counter and uses it to count down to zero on

every slot-time. This effectively causes the Host MAC to wait eight slot-

times. To give the user more flexibility, the BOLMT value forces the number

of bits to be used from the LFSR counter to a predetermined value as in the

table below.

BOLMT Value

# Bits Used from LFSR Counter

00b

01b

10b

11b

Thus, if the value of K = 10, the Host MAC will look at the BOLMT if it is 00b,

then use the lower ten bits of the LFSR counter for the wait countdown. If the BOLMT

is 10b, then it will only use the value in the first four bits for the wait countdown,

etc.

Note:

Slot-time = 512 bit times. (See IEEE 802.3 Spec., sections 4.2.3.25

and 4.4.2.1)

Deferral Check (DFCHK)

R/W

When set, enables the deferral check in the Host MAC. The Host MAC will

abort the transmission attempt if it has deferred for more than 24,288 bit

times. Deferral starts when the transmitter is ready to transmit, but is

prevented from doing so because the CRS is active. Deferral time is not

cumulative. If the transmitter defers for 10,000 bit times, then transmits,

collides, backs off, and then has to defer again after completion of back-off,

the deferral timer resets to 0 and restarts. When this bit is cleared, the

deferral check is disabled in the Host MAC and the Host MAC defers

indefinitely.

RESERVED

Transmitter enable (TXEN)

R/W

When set, the Host MAC’s transmitter is enabled and it will transmit frames

from the buffer.

When cleared, the Host MAC’s transmitter is disabled and will not transmit

any frames.

Receiver Enable (RXEN)

R/W

When set, the Host MAC’s receiver is enabled and will receive frames.

When cleared, the MAC’s receiver is disabled and will not receive any

frames.

1:0

RESERVED

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14.3.2

Host MAC Address High Register (HMAC_ADDRH)

Offset:

Size:

32 bits

This read/write register contains the upper 16-bits of the physical address of the Host MAC. The

contents of this register are optionally loaded from the EEPROM at power-on through the EEPROM

Loader if a programmed EEPROM is detected. The least significant byte of this register (bits [7:0]) is

loaded from address 05h of the EEPROM. The second byte (bits [15:8]) is loaded from address 06h

of the EEPROM. Section 9.6, "Host MAC Address," on page 119 details the byte ordering of the

HMAC_ADDRL and HMAC_ADDRH registers with respect to the reception of the Ethernet physical

address. Please refer to Section 10.2, "I2C/Microwire Master EEPROM Controller," on page 137 for

more information on the EEPROM Loader.

BITS

DESCRIPTION

TYPE

DEFAULT

31:16

15:0

RESERVED

Physical Address [47:32]

R/W

FFFFh

This field contains the upper 16-bits (47:32) of the Physical Address of the

Host MAC. The content of this field is undefined until loaded from the

EEPROM at power-on. The host can update the contents of this field after

the initialization process has completed.

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14.3.3

Host MAC Address Low Register (HMAC_ADDRL)

Offset:

Size:

32 bits

This read/write register contains the lower 32-bits of the physical address of the Host MAC. The

contents of this register are optionally loaded from the EEPROM at power-on through the EEPROM

Loader if a programmed EEPROM is detected. The least significant byte of this register (bits [7:0]) is

loaded from address 01h of the EEPROM. The most significant byte of this register is loaded from

address 04h of the EEPROM. Section 9.6, "Host MAC Address," on page 119 details the byte ordering

of the HMAC_ADDRL and HMAC_ADDRH registers with respect to the reception of the Ethernet

physical address. Please refer to Section 10.2, "I2C/Microwire Master EEPROM Controller," on

page 137 for more information on the EEPROM Loader.

BITS

DESCRIPTION

TYPE

DEFAULT

31:0

Physical Address [31:0]

R/W

FFFFFFFFh

This field contains the lower 32-bits (31:0) of the Physical Address of the

Host MAC. The content of this field is undefined until loaded from the

EEPROM at power-on. The host can update the contents of this field after

the initialization process has completed.

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14.3.4

Host MAC Multicast Hash Table High Register (HMAC_HASHH)

Offset:

Size:

32 bits

The 64-bit Multicast table is used for group address filtering. For hash filtering, the contents of the

destination address in the incoming frame is used to index the contents of the Hash table. The most

significant bit determines the register to be used (Hi/Low), while the other five bits determine the bit

within the register. A value of 00000 selects Bit 0 of the Multicast Hash Table Lo register and a value

of 11111 selects the Bit 31 of the Multicast Hash Table Hi register.

If the corresponding bit is 1, then the multicast frame is accepted. Otherwise, it is rejected. If the “Pass All

Multicast” (MCPAS) bit of the Host MAC Control Register (HMAC_CR) is set, then all multicast frames are

accepted regardless of the multicast hash values.

The Multicast Hash Table High register contains the higher 32 bits of the hash table and the Multicast

Hash Table Low register contains the lower 32 bits of the hash table. Refer to Section 9.4, "Address

Filtering," on page 114 for more information on address filtering.

This table determines if the Host MAC accepts the packets from the switch fabric. The switch fabric

address table and configuration determine the packets that get sent to the Host MAC.

BITS

DESCRIPTION

Upper 32-bits of the 64-bit Hash Table

TYPE

DEFAULT

31:0

R/W

00000000h

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14.3.5

Host MAC Multicast Hash Table Low Register (HMAC_HASHL)

Offset:

Size:

32 bits

This read/write register defines the lower 32-bits of the Multicast Hash Table. Please refer to the Host

MAC Multicast Hash T a ble High Register (HMAC_HASHH) and Section 9.4, "Address Filtering" for

more information.

BITS

DESCRIPTION

Lower 32-bits of the 64-bit Hash Table

TYPE

DEFAULT

31:0

R/W

00000000h

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14.3.6

Host MAC MII Access Register (HMAC_MII_ACC)

Offset:

Size:

32 bits

This read/write register is used in conjunction with the Host MAC MII Data Register (HMAC_MII_DATA)

to access the internal PHY registers. Refer to Section 14.4, "Ethernet PHY Control and Status

Registers" for a list of accessible PHY registers and PHY address information.

BITS

DESCRIPTION

TYPE

DEFAULT

31:16

15:11

RESERVED

PHY Address (PHY_ADDR)

R/W

00000b

This field must be loaded with the PHY address that the MII access is

intended for. A list default PHY addresses can be seen in T a ble 7.1. Refer

to Section 7.1.1, "PHY Addressing," on page 82 for additional information on

PHY addressing.

10:6

MII Register Index (MIIRINDA)

These bits select the desired MII register in the PHY.

R/W

00000b

5:2

RESERVED

MII Write (MIIWnR)

R/W

Setting this bit tells the PHY that this will be a write operation using the Host

MAC MII Data Register (HMAC_MII_DATA). If this bit is cleared, a read

operation will occur, packing the data in the Host MAC MII Data Register

(HMAC_MII_DATA).

MII Busy (MIIBZY)

R/W

This bit must be polled to determine when the MII register access is

complete. This bit must read a logical 0 before writing to this register or the

Host MAC MII Data Register (HMAC_MII_DATA).

The LAN driver software must set this bit in order for the

LAN9312 to read or write any of the MII PHY registers.

During a MII register access, this bit will be set, signifying a read or write

access is in progress. The MII data register must be kept valid until the Host

MAC clears this bit during a PHY write operation. The MII data register is

invalid until the Host MAC has cleared this bit during a PHY read operation.

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14.3.7

Host MAC MII Data Register (HMAC_MII_DATA)

Offset:

Size:

32 bits

This read/write register is used in conjunction with the Host MAC MII Access Register

(HMAC_MII_ACC) to access the internal PHY registers. This register contains either the data to be

written to the PHY register specified in the HMAC_MII_ACC Register, or the read data from the PHY

BITS

DESCRIPTION

TYPE

DEFAULT

31:16

15:0

RESERVED

MII Data

R/W

0000h

This field contains the 16-bit value read from the PHY read operation or the

16-bit data value to be written to the PHY before an MII write operation.

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14.3.8

Host MAC Flow Control Register (HMAC_FLOW)

Offset:

Size:

32 bits

This read/write register controls the generation and reception of the Control (Pause command) frames

by the Host MAC’s flow control block. The control frame fields are selected as specified in the 802.3

Specification and the Pause-Time value from this register is used in the “Pause Time” field of the

control frame. In full-duplex mode the FCBSY bit is set until the control frame is completely transferred.

In half-duplex mode FCBSY is set while back pressure is being asserted. The host has to make sure

that the FCBSY bit is cleared before writing the register. The Pass Control Frame bit (FCPASS) does

not affect the sending of the frames, including Control Frames, to the host. The Flow Control Enable

(FCEN) bit enables the receive portion of the Flow Control block.

This register is used in conjunction with the Host MAC Automatic Flow Control Configuration Register

(AFC_CFG) in the System CSR’s to configure flow control. Software flow control is initiated using the

AFC_CFG register.

Note: The Host MAC will not transmit pause frames or assert back pressure if the transmitter is

disabled.

Note: For the Host MAC, flow control/backpressure is to/from the switch fabric, not the external

network.

BITS

DESCRIPTION

TYPE

DEFAULT

31:16

Pause Time (FCPT)

R/W

0000h

This field indicates the value to be used in the PAUSE TIME field in the

control frame. This field must be initialized before full-duplex automatic flow

control is enabled.

15:3

RESERVED

Pass Control Frames (FCPASS)

R/W

When set, the Host MAC sets the packet filter bit in the receive packet status

to indicate to the application that a valid pause frame has been received.

The application must accept or discard a received frame based on the

packet filter control bit. The Host MAC receives, decodes and performs the

Pause function when a valid Pause frame is received in Full-Duplex mode

and when flow control is enabled (FCE bit set). When this bit is cleared, the

Host MAC resets the Packet Filter bit in the Receive packet status.

The Host MAC always passes the data of all frames it receives (including

flow control frames) to the application. Frames that do not pass address

filtering, as well as frames with errors, are passed to the application. The

application must discard or retain the received frame’s data based on the

received frame’s STATUS field. Filtering modes (promiscuous mode, for

example) take precedence over the FCPASS bit.

Flow Control Enable (FCEN)

R/W

When set, enables the Host MAC flow control function. The Host MAC

decodes all incoming frames for control frames; if it receives a valid control

frame (PAUSE command), it disables the transmitter for a specified time

(Decoded pause time x slot time). When this bit is cleared, the Host MAC

flow control function is disabled; the MAC does not decode frames for

control frames.

Note:

Flow Control is applicable when the Host MAC is set in full duplex

mode. In half-duplex mode, this bit enables the backpressure

function to control the flow of received frames to the Host MAC.

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BITS

DESCRIPTION

TYPE

DEFAULT

Flow Control Busy (FCBSY)

R/W

In full-duplex mode, this bit should read logical 0 before writing to the Host

MAC Flow Control (HMAC_FLOW) register. To initiate a PAUSE control

frame, the bit must be set. During a transfer of control frame, this bit

continues to be set, signifying that a frame transmission is in progress. After

the PAUSE control frame’s transmission is complete, the Host MAC resets

the bit to 0.

Backpressure Enable (BkPresEn)

In half-duplex mode, this signal functions as a backpressure enable and is

set high whenever backpressure is transmitted.

Notes:

„ When writing this register, the FCBSY bit must always be zero.

„ Applications must always write a zero to this bit

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14.3.9

Host MAC VLAN1 Tag Register (HMAC_VLAN1)

Offset:

Size:

32 bits

This read/write register contains the VLAN tag field to identify VLAN1 frames. When a VLAN1 frame

is detected, the legal frame length is increased from 1518 bytes to 1522 bytes. Refer to Section 9.3,

"Virtual Local Area Network (VLAN) Support," on page 113 for additional information.

BITS

DESCRIPTION

TYPE

DEFAULT

31:16

15:0

RESERVED

VLAN1 Tag Identifier (VTI1)

R/W

FFFFh

This field contains the VLAN Tag used to identify VLAN1 frames. This field

is compared with the 13th and 14th bytes of the incoming frames for VLAN1

frame detection.

Note:

If used, this register is typically set to the standard VLAN value of

8100h.

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14.3.10 Host MAC VLAN2 Tag Register (HMAC_VLAN2)

Offset:

Size:

32 bits

This read/write register contains the VLAN tag field to identify VLAN2 frames. When a VLAN2 frame

is detected, the legal frame length is increased from 1518 bytes to 1538 bytes. Refer to Section 9.3,

"Virtual Local Area Network (VLAN) Support," on page 113 for additional information.

BITS

DESCRIPTION

TYPE

DEFAULT

31:16

15:0

RESERVED

VLAN2 Tag Identifier (VTI2)

R/W

FFFFh

This field contains the VLAN Tag used to identify VLAN2 frames. This field

is compared with the 13th and 14th bytes of the incoming frames for VLAN2

frame detection.

Note:

If used, this register is typically set to the standard VLAN value of

8100h. If both VLAN1 and VLAN2 Tag Identifiers are used, they

should be unique. If both are set to the same value, VLAN1 is

given higher precedence and the maximum legal frame length is

set to 1522.

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14.3.11 Host MAC Wake-up Frame Filter Register (HMAC_WUFF)

Offset:

Size:

32 bits

This write-only register is used to configure the wake-up frame filter. Refer to Section 9.5, "Wake-up

Frame Detection," on page 116 for additional information.

BITS

DESCRIPTION

Wake-Up Frame Filter (WFF)

TYPE

DEFAULT

31:0

The Wake-up frame filter is configured through this register using an

indexing mechanism. After power-on reset, digital reset, or soft reset, the

Host MAC loads the first value written to this location to the first DWORD in

the Wake-up frame filter (filter 0 byte mask). The second value written to this

location is loaded to the second DWORD in the wake-up frame filter (filter 1

byte mask) and so on. Once all eight DWORD’s have been written, the

internal pointer will once again point to the first entry and the filter entries

can be modified in the same manner.

Note:

This is a write-only register.

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14.3.12 Host MAC Wake-up Control and Status Register (HMAC_WUCSR)

Offset:

Size:

32 bits

This read/write register contains data and control settings pertaining to the Host MAC’s remote wake-

up status and capabilities. It is used in conjunction with the Host MAC Wake-up Frame Filter Register

(HMAC_WUFF) to fully configure the wake-up frame filter. Refer to Section 9.5, "Wake-up Frame

Detection," on page 116 for additional information.

BITS

DESCRIPTION

TYPE

DEFAULT

31:10

RESERVED

Global Unicast Enable (GUE)

R/W

When set, the Host MAC wakes up from power-saving mode on receipt of

a global unicast frame. This is accomplished by enabling global unicasts as

a wakeup frame qualifier. A global unicast frame has the MAC Address [0]

bits set to 0.

8:7

RESERVED

Remote Wake-Up Frame Received (WUFR)

The Host MAC sets this bit upon receiving a valid Remote Wake-up frame.

R/WC

Magic Packet Received (MPR)

The Host MAC sets this bit upon receiving a valid Magic Packet

R/WC

4-3

RESERVED

Wake-Up Frame enabled (WUEN)

R/W

When set, Remote Wake-Up mode is enabled and the Host MAC is capable

of detecting wake-up frames as programmed in the Host MAC Wake-up

Frame Filter Register (HMAC_WUFF).

Magic Packet Enable (MPEN)

R/W

When set, Magic Packet Wake-up mode is enabled.

RESERVED

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14.4

Ethernet PHY Control and Status Registers

This section details the various LAN9312 Ethernet PHY control and status registers. The LAN9312

contains three PHY’s: Port 1 PHY, Port 2 PHY and a Virtual PHY. All PHY registers follow the IEEE

802.3 (clause 22.2.4) specified MII management register set. All functionality and bit definitions comply

with these standards. The IEEE 802.3 specified register index (in decimal) is included with each

For additional information on the MII management protocol, refer to the IEEE 802.3 Specification.

Each individual PHY is assigned a unique PHY address as detailed in Section 7.1.1, "PHY

Addressing," on page 82.

14.4.1

Virtual PHY Registers

The Virtual PHY provides a basic MII management interface for communication with the Host MAC for

connection to the Host as if it was attached to a single port PHY. The Virtual PHY registers differ from

the Port 1 & 2 PHY registers in that they are addressable via the memory map, as described in

T a ble 14.1, as well as serially. These modes of access are described in Section 14.2.8, "Virtual PH Y ,"

on page 245.

Because the Virtual PHY registers are also memory mapped, their definitions have been included in

the System Control and Status Registers Section 14.2.8, "Virtual PH Y ," on page 245. A list of the Virtual

PHY MII addressable registers and their corresponding register index numbers is also included in

T a ble 14.4.

Note: When serially accessed, the Virtual PHY registers are only 16-bits wide, as is standard for MII

management of PHY’s.

14.4.2

Port 1 & 2 PHY Registers

The Port 1 and Port 2 PHY’s are comparable in functionality and have an identical set of non-memory

mapped registers. The Port 1 and Port 2 PHY registers are not memory mapped. These registers are

indirectly accessed through the Host MAC MII Access Register (HMAC_MII_ACC) and Host MAC MII

Data Register (HMAC_MII_DATA) registers in the Host MAC via the MII serial management protocol

specified in IEEE 802.3 clause 22. Because the Port 1 & 2 PHY registers are functionally identical,

their register descriptions have been consolidated. A lowercase “x” has been appended to the end of

each PHY register name in this section, where “x” should be replaced with “1” or “2” for the Port 1

PHY or the Port 2 PHY registers respectively. A list of the Port 1 & 2 PHY MII addressable registers

and their corresponding register index numbers is included in T a ble 14.7. Each individual PHY is

assigned a unique PHY address as detailed in Section 7.1.1, "PHY Addressing," on page 82.

Table 14.7 Port 1 & 2 PHY MII Serially Adressable Registers

INDEX #

SYMBOL

PHY_BASIC_CONTROL_x

PHY_BASIC_STATUS_x

PHY_ID_MSB_x

Port x PHY Basic Control Register, Section 14.4.2.1

Port x PHY Basic Status Register, Section 14.4.2.2

Port x PHY Identification MSB Register, Section 14.4.2.3

Port x PHY Identification LSB Register, Section 14.4.2.4

PHY_ID_LSB_x

PHY_AN_ADV_x

Port x PHY Auto-Negotiation Advertisement Register,

Section 14.4.2.5

PHY_AN_LP_BASE_ABILITY_x

Port x PHY Auto-Negotiation Link Partner Base Page Ability

PHY_AN_EXP_x

Port x PHY Auto-Negotiation Expansion Register,

Section 14.4.2.7

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Table 14.7 Port 1 & 2 PHY MII Serially Adressable Registers (continued)

INDEX #

SYMBOL

PHY_MODE_CONTROL_STATUS_x

Port x PHY Mode Control/Status Register, Section 14.4.2.8

Port x PHY Special Modes Register, Section 14.4.2.9

PHY_SPECIAL_MODES_x

PHY_SPECIAL_CONTROL_STAT_IND_x

Port x PHY Special Control/Status Indication Register,

Section 14.4.2.10

PHY_INTERRUPT_SOURCE_x

Port x PHY Interrupt Source Flags Register, Section 14.4.2.11

Port x PHY Interrupt Mask Register, Section 14.4.2.12

Port x PHY Special Control/Status Register, Section 14.4.2.13

PHY_INTERRUPT_MASK_x

PHY_SPECIAL_CONTROL_STATUS_x

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14.4.2.1

Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x)

Index (decimal):

Size:

16 bits

This read/write register is used to configure the Port x PHY.

Note: This register is re-written in its entirety by the EEPROM Loader following the release of reset

or a RELOAD command. Refer to Section 10.2.4, "EEPROM Loader," on page 149 for

additional information.

BITS

DESCRIPTION

TYPE

DEFAULT

Reset (PHY_RST)

When set, this bit resets all the Port x PHY registers to their default state,

except those marked as NASR type. This bit is self clearing.

R/W

0: Normal operation

1: Reset

Loopback (PHY_LOOPBACK)

R/W

This bit enables/disables the loopback mode. When enabled, transmissions

from the switch fabric are not sent to network. Instead, they are looped back

into the switch fabric.

Note:

If loopback is enabled during half-duplex operation, then the

Enable Receive Own Transmit bit in the Port x MAC Receive

Configuration Register (MAC_RX_CFG_x) must be set for the

specified port. Otherwise, the switch fabric will ignore receive

activity when transmitting in half-duplex mode.

0: Loopback mode disabled (normal operation)

1: Loopback mode enabled

Speed Select LSB (PHY_SPEED_SEL_LSB)

This bit is used to set the speed of the Port x PHY when the Auto-

Negotiation (PHY_AN) bit is disabled.

R/W

Note 14.49

Note 14.50

0: 10 Mbps

1: 100 Mbps

Auto-Negotiation (PHY_AN)

This bit enables/disables Auto-Negotiation. When enabled, the Speed Select

LSB (PHY_SPEED_SEL_LSB) and Duplex Mode (PHY_DUPLEX) bits are

overridden.

0: Auto-Negotiation disabled

1: Auto-Negotiation enabled

Power Down (PHY_PWR_DWN)

R/W

This bit controls the power down mode of the Port x PHY. After this bit is

cleared the PHY may auto-negotiate with it’s partner station. This process

can take up to a few seconds to complete. Once Auto-Negotiation is

complete, bit 5 (Auto-Negotiation Complete) of the Port x PHY Basic Status

Note:

The PHY_AN bit of this register must be cleared before setting this

bit.

0: Normal operation

1: General power down mode

RESERVED

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BITS

DESCRIPTION

TYPE

DEFAULT

Restart Auto-Negotiation (PHY_RST_AN)

When set, this bit restarts the Auto-Negotiation process.

R/W

0: Normal operation

1: Auto-Negotiation restarted

Duplex Mode (PHY_DUPLEX)

R/W

Note 14.51

This bit is used to set the duplex when the Auto-Negotiation (PHY_AN) bit

is disabled.

0: Half Duplex

1: Full Duplex

Collision Test Mode (PHY_COL_TEST)

This bit enables/disables the collision test mode of the Port x PHY. When

set, the collision signal is active during transmission. It is recommended that

this feature be used only in loopback mode.

0: Collision test mode disabled

1: Collision test mode enabled

6:0

RESERVED

Note 14.49 The default value of this bit is determined by the logical OR of the Auto-Negotiation strap

(autoneg_strap_1 for Port 1 PHY, autoneg_strap_2 for Port 2 PHY) and the speed select

strap (speed_strap_1 for Port 1 PHY, speed_strap_2 for Port 2 PHY). Essentially, if the

Auto-Negotiation strap is set, the default value is 1, otherwise the default is determined by

the value of the speed select strap. Refer to Section 4.2.4, "Configuration Straps," on

page 40 for more information.

Note 14.50 The default value of this bit is determined by the value of the Auto-Negotiation strap

(autoneg_strap_1 for Port 1 PHY, autoneg_strap_2 for Port 2 PHY). Refer to Section 4.2.4,

"Configuration Straps," on page 40 for more information.

Note 14.51 The default value of this bit is determined by the logical AND of the negation of the Auto-

Negotiation strap (autoneg_strap_1 for Port 1 PHY, autoneg_strap_2 for Port 2 PHY) and

the duplex select strap (duplex_strap_1 for Port 1 PHY, duplex_strap_2 for Port 2 PHY).

Essentially, if the Auto-Negotiation strap is set, the default value is 0, otherwise the default

is determined by the value of the duplex select strap. Refer to Section 4.2.4, "Configuration

Straps," on page 40 for more information.

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14.4.2.2

Port x PHY Basic Status Register (PHY_BASIC_STATUS_x)

Index (decimal):

Size:

16 bits

This register is used to monitor the status of the Port x PHY.

BITS

DESCRIPTION

TYPE

DEFAULT

100BASE-T4

This bit displays the status of 100BASE-T4 compatibility.

Note 14.52

0: PHY not able to perform 100BASE-T4

1: PHY able to perform 100BASE-T4

100BASE-X Full Duplex

This bit displays the status of 100BASE-X full duplex compatibility.

0: PHY not able to perform 100BASE-X full duplex

1: PHY able to perform 100BASE-X full duplex

100BASE-X Half Duplex

This bit displays the status of 100BASE-X half duplex compatibility.

0: PHY not able to perform 100BASE-X half duplex

1: PHY able to perform 100BASE-X half duplex

10BASE-T Full Duplex

This bit displays the status of 10BASE-T full duplex compatibility.

0: PHY not able to perform 10BASE-T full duplex

1: PHY able to perform 10BASE-T full duplex

10BASE-T Half Duplex

This bit displays the status of 10BASE-T half duplex compatibility.

0: PHY not able to perform 10BASE-T half duplex

1: PHY able to perform 10BASE-T half duplex

100BASE-T2 Full Duplex

This bit displays the status of 100BASE-T2 full duplex compatibility.

Note 14.52

0: PHY not able to perform 100BASE-T2 full duplex

1: PHY able to perform 100BASE-T2 full duplex

100BASE-T2 Half Duplex

This bit displays the status of 100BASE-T2 half duplex compatibility.

Note 14.52

0: PHY not able to perform 100BASE-T2 half duplex

1: PHY able to perform 100BASE-T2 half duplex

8:6

RESERVED

Auto-Negotiation Complete

This bit indicates the status of the Auto-Negotiation process.

0: Auto-Negotiation process not completed

1: Auto-Negotiation process completed

Remote Fault

RO/LH

This bit indicates if a remote fault condition has been detected.

0: No remote fault condition detected

1: Remote fault condition detected

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BITS

DESCRIPTION

TYPE

DEFAULT

Auto-Negotiation Ability

This bit indicates the status of the PHY’s auto-negotiation.

0: PHY is unable to perform auto-negotiation

1: PHY is able to perform auto-negotiation

Link Status

RO/LL

RO/LH

This bit indicates the status of the link.

0: Link is down

1: Link is up

Jabber Detect

This bit indicates the status of the jabber condition.

0: No jabber condition detected

1: Jabber condition detected

Extended Capability

This bit indicates whether extended register capability is supported.

0: Basic register set capabilities only

1: Extended register set capabilities

Note 14.52 The PHY supports 100BASE-TX (half and full duplex) and 10BASE-T (half and full duplex)

only. All other modes will always return as 0 (unable to perform).

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14.4.2.3

Port x PHY Identification MSB Register (PHY_ID_MSB_x)

Index (decimal):

Size:

16 bits

This read/write register contains the MSB of the Organizationally Unique Identifier (OUI) for the Port x

PHY. The LSB of the PHY OUI is contained in the Port x PHY Identification LSB Register

(PHY_ID_LSB_x).

BITS

DESCRIPTION

TYPE

DEFAULT

15:0

PHY ID

R/W

0007h

This field is assigned to the 3rd through 18th bits of the OUI, respectively

(OUI = 00800Fh).

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14.4.2.4

Port x PHY Identification LSB Register (PHY_ID_LSB_x)

Index (decimal):

Size:

16 bits

This read/write register contains the LSB of the Organizationally Unique Identifier (OUI) for the Port x

PHY. The MSB of the PHY OUI is contained in the Port x PHY Identification MSB Register

(PHY_ID_MSB_x).

BITS

DESCRIPTION

TYPE

DEFAULT

15:10

PHY ID

R/W

30h

This field is assigned to the 19th through 24th bits of the PHY OUI,

respectively. (OUI = 00800Fh).

9:4

3:0

Model Number

R/W

0Dh

This field contains the 6-bit manufacturer’s model number of the PHY.

Revision Number

This field contain the 4-bit manufacturer’s revision number of the PHY.

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14.4.2.5

Port x PHY Auto-Negotiation Advertisement Register (PHY_AN_ADV_x)

Index (decimal):

Size:

16 bits

This read/write register contains the advertised ability of the Port x PHY and is used in the Auto-

Negotiation process with the link partner.

Note: This register is re-written by the EEPROM Loader following the release of reset or a RELOAD

command. Refer to Section 10.2.4, "EEPROM Loader," on page 149 for additional information.

BITS

DESCRIPTION

TYPE

DEFAULT

15:14

RESERVED

Remote Fault

R/W

This bit determines if remote fault indication will be advertised to the link

partner.

0: Remote fault indication not advertised

1: Remote fault indication advertised

RESERVED

R/W

Note:

This bit should be written as 0.

Asymmetric Pause

This bit determines the advertised asymmetric pause capability.

Note 14.53

0: No Asymmetric PAUSE toward link partner advertised

1: Asymmetric PAUSE toward link partner advertised

Symmetric Pause

This bit determines the advertised symmetric pause capability.

R/W

Note 14.53

Note 14.54

0: No Symmetric PAUSE toward link partner advertised

1: Symmetric PAUSE toward link partner advertised

RESERVED

100BASE-X Full Duplex

This bit determines the advertised 100BASE-X full duplex capability.

R/W

0: 100BASE-X full duplex ability not advertised

1: 100BASE-X full duplex ability advertised

100BASE-X Half Duplex

R/W

This bit determines the advertised 100BASE-X half duplex capability.

0: 100BASE-X half duplex ability not advertised

1: 100BASE-X half duplex ability advertised

10BASE-T Full Duplex

This bit determines the advertised 10BASE-T full duplex capability.

Note 14.55

T a ble 14.8

0: 10BASE-T full duplex ability not advertised

1: 10BASE-T full duplex ability advertised

10BASE-T Half Duplex

This bit determines the advertised 10BASE-T half duplex capability.

Note 14.56

T a ble 14.9

0: 10BASE-T half duplex ability not advertised

1: 10BASE-T half duplex ability advertised

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BITS

DESCRIPTION

TYPE

DEFAULT

4:0

Selector Field

R/W

00001b

This field identifies the type of message being sent by Auto-Negotiation.

00001: IEEE 802.3

Note 14.53 The Pause and Asymmetric Pause bits are loaded into the PHY registers by the EEPROM

Loader.

Note 14.54 The default value of this bit is determined by the Manual Flow Control Enable Strap

(manual_FC_strap_x). When the Manual Flow Control Enable Strap is 0, this bit defaults

to 1 (symmetric pause advertised). When the Manual Flow Control Enable Strap is 1, this

bit defaults to 0 (symmetric pause not advertised). Configuration strap values are latched

upon the de-assertion of a chip-level reset as described in Section 4.2.4, "Configuration

Straps," on page 40. Refer to Section 4.2.4, "Configuration Straps," on page 40 for

configuration strap definitions.

Note 14.55 The default value of this bit is determined by the logical OR of the Auto-Negotiation strap

(autoneg_strap_x) with the logical AND of the negated speed select strap (speed_strap_x)

and (duplex_strap_x). T a ble 14.8 defines the default behavior of this bit. Configuration

strap values are latched upon the de-assertion of a chip-level reset as described in Section

4.2.4, "Configuration Straps," on page 40. Refer to Section 4.2.4, "Configuration Straps,"

on page 40 for configuration strap definitions.

Table 14.8 10BASE-T Full Duplex Advertisement Default Value

autoneg_strap_x

speed_strap_x

duplex_strap_x

Default 10BASE-T Full Duplex (Bit 6) Value

Note 14.56 The default value of this bit is determined by the logical OR of the Auto-Negotiation strap

(autoneg_strap_x) and the negated speed strap (speed_strap_x). T a ble 14.9 defines the

default behavior of this bit. Configuration strap values are latched upon the de-assertion

of a chip-level reset as described in Section 4.2.4, "Configuration Straps," on page 40.

Refer to Section 4.2.4, "Configuration Straps," on page 40 for configuration strap

definitions.

Table 14.9 10BASE-T Half Duplex Advertisement Bit Default Value

autoneg_strap_x

speed_strap_x

Default 10BASE-T Half Duplex (Bit 5) Value

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Table 14.9 10BASE-T Half Duplex Advertisement Bit Default Value

speed_strap_x Default 10BASE-T Half Duplex (Bit 5) Value

autoneg_strap_x

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14.4.2.6

Port x PHY Auto-Negotiation Link Partner Base Page Ability Register

(PHY_AN_LP_BASE_ABILITY_x)

Index (decimal):

Size:

16 bits

This read-only register contains the advertised ability of the link partner’s PHY and is used in the Auto-

Negotiation process between the link partner and the Port x PHY.

BITS

DESCRIPTION

TYPE

DEFAULT

This bit indicates the link partner PHY page capability.

0: Link partner PHY does not advertise next page capability

1: Link partner PHY advertises next page capability

Acknowledge

This bit indicates whether the link code word has been received from the

partner.

0: Link code word not yet received from partner

1: Link code word received from partner

Remote Fault

This bit indicates whether a remote fault has been detected.

0: No remote fault

1: Remote fault detected

RESERVED

Asymmetric Pause

This bit indicates the link partner PHY asymmetric pause capability.

0: No Asymmetric PAUSE toward link partner

1: Asymmetric PAUSE toward link partner

Pause

This bit indicates the link partner PHY symmetric pause capability.

0: No Symmetric PAUSE toward link partner

1: Symmetric PAUSE toward link partner

100BASE-T4

This bit indicates the link partner PHY 100BASE-T4 capability.

0: 100BASE-T4 ability not supported

1: 100BASE-T4 ability supported

100BASE-X Full Duplex

This bit indicates the link partner PHY 100BASE-X full duplex capability.

0: 100BASE-X full duplex ability not supported

1: 100BASE-X full duplex ability supported

100BASE-X Half Duplex

This bit indicates the link partner PHY 100BASE-X half duplex capability.

0: 100BASE-X half duplex ability not supported

1: 100BASE-X half duplex ability supported

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BITS

DESCRIPTION

TYPE

DEFAULT

10BASE-T Full Duplex

This bit indicates the link partner PHY 10BASE-T full duplex capability.

0: 10BASE-T full duplex ability not supported

1: 10BASE-T full duplex ability supported

10BASE-T Half Duplex

This bit indicates the link partner PHY 10BASE-T half duplex capability.

0: 10BASE-T half duplex ability not supported

1: 10BASE-T half duplex ability supported

4:0

Selector Field

00001b

Note 14.57

This field identifies the type of message being sent by Auto-Negotiation.

00001: IEEE 802.3

Note 14.57 The Port 1 & 2 PHY’s support only IEEE 802.3.

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14.4.2.7

Port x PHY Auto-Negotiation Expansion Register (PHY_AN_EXP_x)

Index (decimal):

Size:

16 bits

This read/write register is used in the Auto-Negotiation process between the link partner and the Port

x PHY.

BITS

DESCRIPTION

TYPE

DEFAULT

15:5

RESERVED

Parallel Detection Fault

This bit indicates whether a Parallel Detection Fault has been detected.

RO/LH

0: A fault hasn’t been detected via the Parallel Detection function

1: A fault has been detected via the Parallel Detection function

Link Partner Next Page Able

This bit indicates whether the link partner has next page ability.

0: Link partner does not contain next page capability

1: Link partner contains next page capability

Local Device Next Page Able

This bit indicates whether the local device has next page ability.

0: Local device does not contain next page capability

1: Local device contains next page capability

Page Received

This bit indicates the reception of a new page.

RO/LH

0: A new page has not been received

1: A new page has been received

Link Partner Auto-Negotiation Able

This bit indicates the Auto-negotiation ability of the link partner.

0: Link partner is not Auto-Negotiation able

1: Link partner is Auto-Negotiation able

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14.4.2.8

Port x PHY Mode Control/Status Register (PHY_MODE_CONTROL_STATUS_x)

Index (decimal): 17

Size:

16 bits

This read/write register is used to control and monitor various Port x PHY configuration options.

BITS

DESCRIPTION

TYPE

DEFAULT

15:14

RESERVED

Energy Detect Power-Down (EDPWRDOWN)

This bit controls the Energy Detect Power-Down mode.

R/W

0: Energy Detect Power-Down is disabled

1: Energy Detect Power-Down is enabled

12:2

RESERVED

Energy On (ENERGYON)

This bit indicates whether energy is detected on the line. It is cleared if no

valid energy is detected within 256ms. This bit is unaffected by a software

reset and is reset to 1 by a hardware reset.

0: No valid energy detected on the line

1: Energy detected on the line

RESERVED

R/W

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14.4.2.9

Port x PHY Special Modes Register (PHY_SPECIAL_MODES_x)

Index (decimal): 18

Size:

16 bits

This read/write register is used to control the special modes of the Port x PHY.

Note: This register is re-written by the EEPROM Loader following the release of reset or a RELOAD

command. Refer to Section 10.2.4, "EEPROM Loader," on page 149 for more information.

BITS

DESCRIPTION

TYPE

DEFAULT

15:8

7:5

RESERVED

Note 14.59

PHY Mode (MODE[2:0])

This field controls the PHY mode of operation. Refer to T a ble 14.10 for a

definition of each mode.

R/W

NASR

Note 14.58

Note 14.60

4:0

PHY Address (PHYADD)

R/W

The PHY Address field determines the MMI address to which the PHY will

respond and is also used for initialization of the cipher (scrambler) key. Each

PHY must have a unique address. Refer to Section 7.1.1, "PHY

Addressing," on page 82 for additional information.

NASR

Note 14.58

Note:

No check is performed to ensure that this address is unique from

the other PHY addresses (Port 1 PHY, Port 2 PHY, and Virtual

PHY).

Note 14.58 Register bits designated as NASR are reset when the Port x PHY Reset is generated via

the Reset Control Register (RESET_CTL). The NASR designation is only applicable when

the R eset (PHY_RST) bit of the P ort x PHY Basic Control Register

(PHY_BASIC_CONTROL_x) is set.

Note 14.59 The default value of this field is determined by a combination of the configuration straps

autoneg_strap_x, speed_strap_x, and duplex_strap_x. If the autoneg_strap_x is 1, then

the default MODE[2:0] value is 111b. Else, the default value of this field is determined by

the remaining straps. MODE[2]=0, MODE[1]=(speed_strap_1 for Port 1 PHY,

speed_strap_2 for Port 2 PHY), and MODE[0]=(duplex_strap_1 for Port 1 PHY,

duplex_strap_2 for Port 2 PHY). Configuration strap values are latched upon the de-

assertion of a chip-level reset as described in Section 4.2.4, "Configuration Straps," on

page 40. Refer to Section 4.2.4, "Configuration Straps," on p age 40 for configuration strap

definitions.

Note 14.60 The default value of this field is determined by the phy_addr_sel_strap configuration strap.

Refer to Section 7.1.1, "PHY Addressing," on page 82 for additional information.

Table 14.10 MODE[2:0] Definitions

AFFECTED REGISTER BIT VALUES

MODE[2:0]

MODE DEFINITIONS

PHY_BASIC_CONTROL_x

[13,12,10,8]

PHY_AN_ADV_x

[8,7,6,5]

000

001

010

10BASE-T Half Duplex. Auto-negotiation disabled.

10BASE-T Full Duplex. Auto-negotiation disabled.

0000

0001

1000

N/A

100BASE-TX Half Duplex. Auto-negotiation

disabled. CRS is active during Transmit & Receive.

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Table 14.10 MODE[2:0] Definitions (continued)

AFFECTED REGISTER BIT VALUES

MODE[2:0]

MODE DEFINITIONS

PHY_BASIC_CONTROL_x

[13,12,10,8]

PHY_AN_ADV_x

[8,7,6,5]

011

100

100BASE-TX Full Duplex. Auto-negotiation

disabled. CRS is active during Receive.

1001

N/A

100BASE-TX Half Duplex is advertised. Auto-

negotiation enabled.

CRS is active during Transmit & Receive.

1100

0100

101

Repeater mode. Auto-negotiation enabled.

100BASE-TX Half Duplex is advertised.

CRS is active during Receive.

110

111

Power Down mode. In this mode the PHY wake-up

in Power-Down mode.

N/A

All capable. Auto-negotiation enabled.

X10X

1111

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14.4.2.10

Port x PHY Special Control/Status Indication Register (PHY_SPECIAL_CONTROL_STAT_IND_x)

Index (decimal): 27

Size:

16 bits

This read/write register is used to control various options of the Port x PHY.

BITS

DESCRIPTION

TYPE

DEFAULT

Auto-MDIX Control (AMDIXCTRL)

R/W

NASR

This bit is responsible for determining the source of Auto-MDIX control for

Port x. When set, the Manual MDIX and Auto MDIX straps

(manual_mdix_strap_1/auto_mdix_strap_1 for Port 1 PHY,

manual_mdix_strap_2/auto_mdix_strap_2 for Port 2 PHY) are overridden,

and Auto-MDIX functions are controlled using bit 14 (AMDIXEN) and bit 13

(AMDIXSTATE) of this register. When cleared, Auto-MDIX functionality is

controlled by the Manual MDIX and Auto MDIX straps by default. Refer to

Section 4.2.4, "Configuration Straps," on page 40 for configuration strap

definitions.

0: Port x Auto-MDIX determined by strap inputs

1: Port x Auto-MDIX determined by bits 14 and 13

Auto-MDIX Enable (AMDIXEN)

R/W

NASR

When bit 15 (AMDIXCTRL) of this register is set, this bit is used in

conjunction with bit 13 (Auto-MDIX State) to control the Port x Auto-MDIX

functionality as shown in T a ble 14.11.

Auto-MDIX State (AMDIXSTATE)

R/W

NASR

When bit 15 (AMDIXCTRL) of this register is set, this bit is used in

conjunction with bit 14 (Auto-MDIX Enable) to control the Port x Auto-MDIX

functionality as shown in T a ble 14.11.

RESERVED

SQE Test Disable (SQEOFF)

This bit controls the disabling of the SQE test (Heartbeat). SQE test is

enabled by default.

R/W

NASR

0: SQE test enabled

1: SQE test disabled

Receive PLL Lock Control (VCOOFF_LP)

R/W

NASR