Renesas Computer Hardware REJ06B0732 0100 User Guide

APPLICATION NOTE  
SH7211 Group  
Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode)  
Introduction  
This application note describes the operation of the DMAC, and is intended for reference to help in the design of user  
software.  
Target Device  
SH7211  
Contents  
1. Introduction ....................................................................................................................................... 2  
2. Description of Sample Application.................................................................................................... 3  
3. Documents of Reference ................................................................................................................ 11  
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Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode)  
2. Description of Sample Application  
In this sample application, the direct memory access controller (DMAC) is set to auto request mode to transfer 512-  
Kbtyte data stored in the on-chip RAM to another address.  
2.1  
Operation of Modules Used  
When a DMA transfer request is made, the DMAC starts to transfer data in accordance with the priority order of  
channels and continues the transfer operation until the transfer end condition is met. Transfer requests for the DMAC  
are of three kinds: auto requests, external requests, and on-chip peripheral module requests. The bus mode is selectable  
as burst mode or cycle-stealing mode.  
For details on the DMAC, refer to the section on the direct memory access controller in the SH7211 Group Hardware  
Manual.  
An overview of the DMAC is given in table 1. Examples of DMA transfer in cycle-stealing mode and burst mode are  
shown in figures 1 and 2, respectively. In addition, a block diagram of the DMAC is shown in figure 3.  
Table 1 Overview of DMAC  
Item  
Description  
Number of channels  
8 (CH0 to CH7)  
Only 4 (CH0 to CH3) can receive external requests.  
4 Gbytes  
Address space  
Length of transfer data  
Maximum transfer count  
Address mode  
Byte, word (2 bytes), longword (4 bytes), and 16 bytes (longword × 4)  
16,777,216 (24 bits) transfers  
Single address mode and dual address mode  
Transfer request  
External request, on-chip peripheral module request, and auto request  
(SCIF: 8 sources, IIC3: two sources, A/D converter: one source, MTU2:  
five sources, CMT: two sources)  
Bus mode  
Cycle-stealing mode (normal mode and intermittent mode) and burst  
mode  
Priority level  
Channel priority fixed mode and round-robin mode  
Interrupt request  
An interrupt request to the CPU is made when half or all of a transfer  
process is completed.  
External request detection  
DREQ input low/high level detection, rising/falling edge detection  
Transfer request acknowledge Active levels for DACK and TEND can be set independently  
signal/transfer end signal  
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Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode)  
In the normal mode of cycle stealing, bus mastership is given to another bus master after each DMA  
transfer of one transfer unit (byte, word, longword, or 16-byte unit). When a subsequent transfer  
request occurs, bus mastership is obtained from the other bus master and transfer proceeds for one  
transfer unit. When that transfer ends, the bus mastership is passed to another bus master. This is  
repeated until the transfer end condition is satisfied.  
The cycle-stealing normal mode can be used in transfer across any interval, regardless of the  
requesting source, source, and destination of the transfer.  
DREQ  
Bus mastership returned to CPU once  
CPU  
CPU  
CPU  
DMAC DMAC CPU  
Read Write  
DMAC DMAC CPU  
Read Write  
Bus cycle  
Figure 1 DMA Transfer Example in Cycle-Stealing Normal Mode  
(Dual Address, DREQ Low Level Detection)  
In burst mode, once the DMAC has obtained bus mastership, it continues to perform transfer without  
releasing the bus until the transfer end condition is satisfied. In external mode, however, when the DREQ  
signal is being level-detected and changes to the non-active level, even if the tranfer end condition has not  
been satisfied, bus mastership is passed to another bus master on completion of the DMA transfer request  
for which the request has already been accepted.  
DREQ  
DMAC DMAC DMAC DMAC CPU  
Read Write Read Write  
CPU  
CPU  
CPU  
CPU  
Bus cycle  
Figure 2 DMA Transfer Example in Burst Mode (Dual Address, DREQ Low Level Detection)  
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Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode)  
DMAC module  
RDMATCR_n  
On-chip  
memory  
Iteration  
control  
DMATCR_n  
RSAR_n  
SAR_n  
On-chip  
peripheral  
module  
Register  
control  
RDAR_n  
DAR_n  
Start-up  
control  
DMA transfer  
request signal  
CHCR_n  
DMAOR  
DMA transfer acknowledge signal  
Request  
priority  
control  
HEIn  
DEIn  
Interrupt controller  
DMARS0 to DMARS3  
External ROM  
Bus  
interface  
External RAM  
External device  
(memory mapped)  
Bus state  
controller  
External device  
(with acknowledge)  
DREQ0 to DREQ3  
DACK0 to DACK3,  
TEND0, TEND1  
[Legend]  
RDMATCR: DMA reload transfer count register  
DMATCR: DMA transfer count register  
CHCR:  
DMAOR:  
DMA channel control register  
DMA operation register  
RSAR:  
SAR:  
RDAR:  
DAR:  
DMA reload source address register  
DMA source address register  
DMA reload destination address register DEIn:  
DMA destination address register n:  
DMARS0 to DMARS3: DMA extension resource selectors 0 to 3  
HEIn:  
DMA transfer half-end interrupt request to the CPU  
DMA transfer end interrupt request to the CPU  
0, 1, 2, 3, 4, 5, 6, 7  
Figure 3 Block Diagram of DMAC  
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Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode)  
2.2  
Operational Description of Sample Program  
The settings of the DMAC for the sample program are listed in table 4. Also, the operation of the sample program is  
illustrated in figure 4.  
Table 4 Settings of DMAC  
DMA transfer condition  
Channel  
Auto request mode  
CH0  
Length of transfer data  
Maximum transfer count  
Address mode  
4 bytes  
128 transfers (128 × data length of 4 bytes = 512-byte data)  
Dual address mode  
Bus mode  
Cycle-stealing mode  
Priority level  
Interrupt request  
Channel priority level fixed mode  
Disable an interrupt request to the CPU at the end of a transfer  
On-chip RAM  
DMAC  
SAR  
Transfer source  
H'0xFFF81000  
address  
512-byte data  
DAR  
DMA transfer  
Transfer  
destination  
address  
H'0xFFF82000  
512-byte data  
[Legend]  
SAR:Source address register  
DAR:Destination address register  
Figure 4 Operation of Sample Program  
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Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode)  
2.3  
Procedure for Setting Modules  
This section describes the procedure for making initial settings when the DMAC is to be used to transfer data between  
locations within the on-chip RAM. Auto request mode is used for the transfer requests.  
By default, the on-chip peripheral modules of this MCU are in module standby mode. Whenever any of these modules  
is to be used, be sure to take it out of module standby mode before making the initial settings. Although processing to  
delete the end of DMA transfer is typically handled by interrupts, polling is used in this sample application. A  
flowchart of the sample program is shown in figure 5. In addition, a flowchart of DMAC initialization is shown in  
figure 6.  
For details on registers, refer to the SH7211 Group Hardware Manual.  
main  
[1] Cancel module standby mode  
[1]  
[2]  
Activate the DMAC  
STB.CR2.BIT._DMAC = 0  
DMAC_init  
[2] Initialize the DMAC (channel 0)  
No  
[3]  
512-byte Initialization  
completed?  
[3] Initialize the transfer destination  
Clear a 512-byte area to 0  
Yes  
[4] Enable DMA transfer  
Set DMA enable flag  
[4]  
DMAC0.CHCR.BIT.DE = 1  
No  
Transfer completed?  
Yes  
[5] Perform DMA transfer end processing  
Disable DMA transfer after confirmation  
of the tranfer end.  
[5]  
DMAC0.CHCR.BIT.DE = 0  
END  
* In this sample application, sleep processing is performed after the main routine is complete.  
Figure 5 Flowchart of Sample Program  
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Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode)  
DMAC_init  
[1] Disable DMA transfer  
Set the DE (DMA enable) bit to 0  
Disable DMA transfer  
Set DMA channel control register  
(CHCR_0)  
[1]  
[2]  
[2] Set the DMA transfer source address (SAR_0)  
Specify the DMA transfer source address  
Set DMA source address register  
(SAR_0)  
[3] Set the DMA transfer destination address (DAR_0)  
Specify the DMA transfer destination address  
Set DMA destination address  
register (DAR_0)  
[4] Specify the DMA transfer count (DMATCR_0)  
Set the DMA transfer count to 128  
[3]  
[4]  
[5]  
[6]  
[5] Set the channel control register (CHCR_0)  
Set TC to B’1: transfer data for the count specified in DMATCR  
Set RLD to B’0: disable the reload function  
Set RS[3:0] (resource selector) to B’0100: auto request  
Set DM[1:0] to B’01: increment the destination address  
Set SM[1:0] to B’00: fix the source address  
Set TB to B’0: cycle steal mode  
Set DMA transfer count register  
(DMATCR_0)  
Set DMA channel control register  
(CHCR_0)  
Set IE to B’0: disable interrupts  
Set DMA operation register  
(DMAOR)  
[6] Set the DMA operation register (DMAOR)  
Read from the AE and MNIF bits and clear them to 0  
Clear the address error flag  
Set the DME bit to 1 after clearing the flags  
Enable DMA transfer on all the channels  
END  
Figure 6 Flowchart of Initializing DMAC  
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Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode)  
2.4  
Register Settings for Sample Program  
2.4.1  
Clock Pulse Generator (CPG)  
The settings of the clock pulse generator for the sample program are described in table 5.  
Table 5 Settings of Clock Pulse Generator  
Register Name  
Address  
Setting Value  
Description  
Frequency control  
register (FRQCR)  
H’FFFE0010  
H’1303  
CKOEN = “B’1”: output clocks  
STC[1:0] = “B’00”: frequency multiplication  
ratio of PLL circuit × 1  
IFC[2:0] = “B’000”: internal clock × 1  
PFC[2:0] = “B’011”: peripheral clock × 1/4  
2.4.2  
Standby Control Register  
The settings of the standby control register for the sample program are described in table 6.  
Table 6 Settings of Standby Control Register  
Register Name  
Address  
Setting Value  
Description  
Standby control  
H’FFFE0018  
H’00  
MSTP8 = “B’0”: the DMAC operates  
register 2 (STBCR2)  
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Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode)  
2.4.3  
Direct Memory Access Controller (DMAC)  
The settings of DMAC registers for the sample program are described in table 7.  
Table 7 Settings of DMAC Registers  
Register Name  
Address  
Setting Value  
Description  
DMA source address  
register 0 (SAR)  
H’FFFE1000 H’FFF81000  
Transfer source start address  
DMA destination address H’FFFE1004 H’FFF82000  
register 0 (DAR)  
Transfer destination start address  
DMA transfer count  
register 0 (DMATCR)  
H’FFFE1008 D’128  
DMA transfer count:  
128 transfers  
DMA channel control  
register 0 (CHCR)  
H’FFFE100C H’0000 0000  
H’8000 4410  
Before DMA initialization  
DE = “B’0”: disables DMA transfer  
DMA initialization  
TC = “B’1”: transfers data for the count  
specified in DMATCR for each transfer  
request  
DM[1:0] = “B’01”: increments the destination  
address  
SM[1:0] = “B’00”: fixes the source address  
RS[3:0] = “B’0100”: auto request  
TB = “B’0”: cycle-stealing mode  
TS[1:0] = “B’10”: longword (4 bytes) unit  
IE = “B’0”: disables interrupt requests  
DE = “B’0”: disables DMA transfer  
H’8000 4411  
H’8000 4410  
When enabling DMA transfer  
DE = “B’1”: enables DMA transfer  
When disabling DMA transfer  
DE = “B’0”: disables DMA transfer  
DMA operation register  
(DMAOR)  
H’FFFE1200 H’0000 0001  
DME = “B’1”: enables DMA transfer on all the  
channels  
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Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode)  
3. Documents for Reference  
Software Manual  
SH-2A, SH2A-FPU Software Manual  
The most up-to-date version of this document is available on the Renesas Technology Website.  
Hardware Manual  
SH7211 Group Hardware Manual  
The most up-to-date version of this document is available on the Renesas Technology Website.  
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Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode)  
Website and Support  
Renesas Technology Website  
Inquiries  
Revision Record  
Description  
Rev.  
Date  
Page  
Summary  
1.00  
Mar.21.08  
First edition issued  
All trademarks and registered trademarks are the property of their respective owners.  
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Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode)  
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