INTEGRATED CIRCUITS
DATA SHEET
UDA1334BT
Low power audio DAC
Product specification
2002 May 22
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Philips Semiconductors
Product specification
Low power audio DAC
UDA1334BT
1
FEATURES
General
1.1
• 1.8 to 3.6 V power supply voltage
• Integrated digital filter plus DAC
• Supports sample frequencies from 8 to 100 kHz
• Automatic system clock versus sample rate detection
• Low power consumption
• No analog post filtering required for DAC
• Slave mode only applications
2
APPLICATIONS
This audio DAC is excellently suitable for digital audio
portable application, such as portable MD, MP3 and
DVD players.
• Easy application
• SO16 package.
1.2
Multiple format data interface
3
GENERAL DESCRIPTION
• I2S-bus and LSB-justified format compatible
The UDA1334BT supports the I2S-bus data format with
word lengths of up to 24 bits and the LSB-justified serial
data format with word lengths of 16, 20 and 24 bits.
• 1fs input data rate.
1.3
DAC digital sound processing
The UDA1334BT has basic features such as de-emphasis
(at 44.1 kHz sampling rate) and mute.
• Digital de-emphasis for 44.1 kHz sampling rate
• Mute function.
1.4
Advanced audio configuration
• High linearity, wide dynamic range and low distortion
• Standby or Sleep mode in which the DAC is powered
down.
4
ORDERING INFORMATION
TYPE
PACKAGE
NUMBER
NAME
DESCRIPTION
VERSION
UDA1334BT
SO16
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
2002 May 22
3
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Philips Semiconductors
Product specification
Low power audio DAC
UDA1334BT
5
QUICK REFERENCE DATA
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Supplies
VDDA
VDDD
IDDA
DAC analog supply voltage
digital supply voltage
1.8
1.8
−
−
−
2.0
2.0
2.3
125
1.4
3.6
3.6
−
−
−
V
V
DAC analog supply current
normal operating mode
Sleep mode
mA
µA
mA
IDDD
digital supply current
normal operating mode
Sleep mode
clock running
−
−
−40
250
20
−
−
−
µA
µA
°C
no clock running
Tamb
ambient temperature
+85
Digital-to-analog converter (VDDA = VDDD = 2.0 V)
Vo(rms)
(THD + N)/S total harmonic
distortion-plus-noise to signal
output voltage (RMS value)
at 0 dB (FS) digital input; note 1
fs = 44.1 kHz; at 0 dB
−
−
−
−
−
−
−
−
600
−80
−37
−75
−35
97
−
−
−
−
−
−
−
−
mV
dB
dB
dB
dB
dB
dB
dB
fs = 44.1 kHz; at −60 dB; A-weighted
fs = 96 kHz; at 0 dB
ratio
fs = 96 kHz; at −60 dB; A-weighted
fs = 44.1 kHz; code = 0; A-weighted
fs = 96 kHz; code = 0; A-weighted
S/N
signal-to-noise ratio
channel separation
95
αcs
100
Digital-to-analog converter (VDDA = VDDD = 3.0 V)
Vo(rms)
(THD + N)/S total harmonic
distortion-plus-noise to signal
output voltage (RMS value)
at 0 dB (FS) digital input; note 1
fs = 44.1 kHz; at 0 dB
−
−
−
−
−
−
−
−
900
−90
−40
−85
−37
100
98
−
−
−
−
−
−
−
−
mV
dB
dB
dB
dB
dB
dB
dB
fs = 44.1 kHz; at −60 dB; A-weighted
fs = 96 kHz; at 0 dB
ratio
fs = 96 kHz; at −60 dB; A-weighted
fs = 44.1 kHz; code = 0; A-weighted
fs = 96 kHz; code = 0; A-weighted
S/N
signal-to-noise ratio
channel separation
αcs
100
Power dissipation (at fs = 44.1 kHz)
P
power dissipation
playback mode
at 2.0 V supply voltage
at 3.0 V supply voltage
Sleep mode; at 2.0 V supply voltage
clock running
−
−
7.4
17
−
−
mW
mW
−
−
0.75
0.3
−
−
mW
mW
no clock running
Note
1. The DAC output voltage scales proportionally to the power supply voltage.
2002 May 22
4
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Philips Semiconductors
Product specification
Low power audio DAC
UDA1334BT
6
BLOCK DIAGRAM
V
V
SSD
5
DDD
4
1
2
3
BCK
WS
DIGITAL INTERFACE
DE-EMPHASIS
DATAI
UDA1334BT
6
7
SYSCLK
MUTE
DEEM
PCS
SFOR1
SFOR0
8
9
11
INTERPOLATION FILTER
NOISE SHAPER
10
14
16
DAC
DAC
VOUTR
VOUTL
13
15
12
ref(DAC)
MGU676
V
V
V
DDA
SSA
Fig.1 Block diagram.
2002 May 22
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Philips Semiconductors
Product specification
Low power audio DAC
UDA1334BT
7
PINNING
SYMBOL
PIN
PAD TYPE
DESCRIPTION
BCK
1
2
5 V tolerant digital input pad; note 1
5 V tolerant digital input pad; note 1
5 V tolerant digital input pad; note 1
digital supply pad
bit clock input
WS
word select input
serial data input
digital supply voltage
digital ground
DATAI
VDDD
3
4
VSSD
5
digital ground pad
SYSCLK
SFOR1
MUTE
DEEM
PCS
6
5 V tolerant digital input pad; note 1
5 V tolerant digital input pad; note 1
5 V tolerant digital input pad; note 1
5 V tolerant digital input pad; note 1
3-level input pad; note 2
digital input pad; note 2
system clock input
serial format select 1
mute control
7
8
9
de-emphasis control
10
11
12
13
14
15
16
power control and sampling frequency select
serial format select 0
SFOR0
Vref(DAC)
VDDA
analog pad
DAC reference voltage
DAC analog supply voltage
DAC output left
analog supply pad
VOUTL
VSSA
analog output pad
analog ground pad
DAC analog ground
VOUTR
analog output pad
DAC output right
Notes
1. 5 V tolerant is only supported if the power supply voltage is between 2.7 and 3.6 V. For lower power supply voltages
this is maximum 3.3 V tolerant.
2. Because of test issues these pads are not 5 V tolerant and they should be at power supply voltage level or at a
maximum of 0.5 V above that level.
handbook, halfpage
BCK
WS
1
2
3
4
5
6
7
8
16
15
VOUTR
V
SSA
DATAI
14 VOUTL
V
V
V
13
12
DDD
DDA
UDA1334BT
V
SSD
ref(DAC)
SYSCLK
SFOR1
MUTE
11 SFOR0
10 PCS
9
DEEM
MGU675
Fig.2 Pin configuration.
2002 May 22
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Philips Semiconductors
Product specification
Low power audio DAC
UDA1334BT
8
FUNCTIONAL DESCRIPTION
System clock
Table 2 Example using a 12.228 MHz system clock
8.1
CLOCK MODE
SAMPLING FREQUENCY
128fs
192fs
256fs
384fs
512fs
768fs
96 kHz
64 kHz(1)
48 kHz
32 kHz
24 kHz
16 kHz
The UDA1334BT operates in slave mode only; this means
that in all applications the system must provide the system
clock and the digital audio interface signals
(BCK and WS).
The system clock must be locked in frequency to the digital
interface signals.
The UDA1334BT automatically detects the ratio between
the SYSCLK and WS frequencies.
Note
1. This mode can only be supported for power supply
voltages down to 2.4 V. For lower voltages, in 192fs
mode the sampling frequency should be limited to
55 kHz.
The BCK clock can be up to 64fs, or in other words the
BCK frequency is 64 times the Word Select (WS)
frequency or less: fBCK ≤ 64 × fWS
.
Remarks:
8.2
Interpolation filter
1. The WS edge MUST fall on the negative edge of the
BCK at all times for proper operation of the digital I/O
data interface
The interpolation digital filter interpolates from 1fs to 64fs
by cascading FIR filters (see Table 3).
2. For LSB-justified formats it is important to have a WS
signal with a duty factor of 50%.
Table 3 Interpolation filter characteristics
The modes which are supported are given in Table 1.
ITEM
CONDITION
VALUE (dB)
Pass-band ripple
Stop band
0 to 0.45fs
>0.55fs
±0.02
−50
Table 1 Supported sampling ranges
CLOCK MODE
SAMPLING RANGE
Dynamic range
0 to 0.45fs
>114
768fs
512fs
384fs
256fs
192fs
128fs
8 to 55 kHz
8 to 100 kHz
8.3
Noise shaper
8 to 100 kHz
The 5th-order noise shaper operates at 64fs. It shifts
in-band quantization noise to frequencies well above the
audio band. This noise shaping technique enables high
signal-to-noise ratios to be achieved. The noise shaper
output is converted into an analog signal using a
Filter Stream DAC (FSDAC).
8 to 100 kHz
8 to 100 kHz(1)(2)
8 to 100 kHz(2)
Notes
1. This mode can only be supported for power supply
voltages down to 2.4 V. For lower voltages, in
192fs mode the sampling frequency should be limited
to 55 kHz.
2. Not supported in the low sampling frequency mode.
An example is given in Table 2 for a 12.228 MHz system
clock input.
2002 May 22
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Philips Semiconductors
Product specification
Low power audio DAC
UDA1334BT
8.4
Filter stream DAC
8.5
Power-on reset
The FSDAC is a semi-digital reconstruction filter that
converts the 1-bit data stream of the noise shaper to an
analog output voltage. The filter coefficients are
implemented as current sources and are summed at
virtual ground of the output operational amplifier. In this
way very high signal-to-noise performance and low clock
jitter sensitivity is achieved. No post-filter is needed due to
the inherent filter function of the DAC. On-board amplifiers
convert the FSDAC output current to an output voltage
signal capable of driving a line output.
The UDA1334BT has an internal Power-on reset circuit
(see Fig.3) which resets the test control block.
The reset time (see Fig.4) is determined by an external
capacitor which is connected between pin Vref(DAC) and
ground. The reset time should be at least 1 µs for
Vref(DAC) < 1.25 V. When VDDA is switched off, the device
will be reset again for Vref(DAC) < 0.75 V.
During the reset time the system clock should be running.
The output voltage of the FSDAC scales proportionally
with the power supply voltage.
3.0
handbook, halfpage
V
DDD
(V)
1.5
0
t
3.0
V
handbook, halfpage
DDA
13
12
V
3.0 V
DDA
(V)
50 kΩ
1.5
RESET
CIRCUIT
V
ref(DAC)
C1 >
10 µF
0
50 kΩ
t
UDA1334BT
3.0
V
MGU678
ref(DAC)
(V)
1.5
1.25
0.75
0
t
>1 µs
MGL984
Fig.3 Power-on reset circuit.
Fig.4 Power-on reset timing.
2002 May 22
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Philips Semiconductors
Product specification
Low power audio DAC
UDA1334BT
8.6
Feature settings
8.6.4
POWER CONTROL AND SAMPLING FREQUENCY
SELECT
The features of the UDA1334BT can be set by control
pins SFOR1, SFOR0, MUTE, DEEM and PCS.
Pin PCS is a 3-level pin and is used to set the mode of the
UDA1334BT. The definition is given in Table 7.
8.6.1
DIGITAL INTERFACE FORMAT SELECT
Table 7 PCS function definition
The digital audio interface formats (see Fig.5) can be
selected via the pins SFOR1 and SFOR0 as shown in
Table 4.
PCS
LOW
MID
FUNCTION
normal operating mode
low sampling frequency mode
Power-down or Sleep mode
Table 4 Data format selection
HIGH
SFOR1
SFOR0
INPUT FORMAT
I2S-bus input
LOW
LOW
HIGH
HIGH
LOW
HIGH
LOW
HIGH
The low sampling frequency mode is required to have a
higher oversampling rate in the noise shaper in order to
improve the signal-to-noise ratio. In this mode the
oversampling ratio of the noise shaper will be 128fs instead
of 64fs.
LSB-justified 16 bits input
LSB-justified 20 bits input
LSB-justified 24 bits input
8.6.2
MUTE CONTROL
The output signal can be soft muted by setting pin MUTE
to HIGH level as shown in Table 5.
Table 5 Mute control
MUTE
FUNCTION
LOW
mute off
mute on
HIGH
8.6.3
DE-EMPHASIS CONTROL
De-emphasis can be switched on for fs = 44.1 kHz by
setting pin DEEM at HIGH level. The function description
of pin DEEM is given in Table 6.
Table 6 De-emphasis control
DEEM
FUNCTION
de-emphasis off
de-emphasis on
LOW
HIGH
Remark: the de-emphasis function in only supported in
the normal operating mode, not in the low sampling
frequency mode.
2002 May 22
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RIGHT
LEFT
WS
1
2
3
> = 8
1
2
3
> = 8
BCK
DATA
MSB B2
MSB B2
MSB
2
I S-BUS FORMAT
WS
LEFT
RIGHT
16
15
2
1
16
15
2
1
BCK
DATA
B15 LSB
B15 LSB
MSB B2
MSB B2
LSB-JUSTIFIED FORMAT 16 BITS
WS
LEFT
20
RIGHT
20
19
18
17
16
15
2
1
19
18
17
16
15
2
1
BCK
DATA
B19 LSB
B19 LSB
MSB B2
B3
B4
B5
B6
MSB B2
B3
B4
B5
B6
LSB-JUSTIFIED FORMAT 20 BITS
WS
LEFT
20
RIGHT
20
24
23
22
21
19
18
17
16
15
2
1
24
23
22
21
19
18
17
16
15
2
1
BCK
DATA
MSB B2
B3
B4
B5
B6
B7
B8
B9 B10
B23 LSB
MSB B2
B3
B4
B5
B6
B7
B8
B9 B10
B23 LSB
MGS752
LSB-JUSTIFIED FORMAT 24 BITS
Fig.5 Digital audio formats
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Philips Semiconductors
Product specification
Low power audio DAC
UDA1334BT
9
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL
PARAMETER
supply voltage
CONDITIONS
MIN.
MAX.
4.0
UNIT
VDD
note 1
−
−
V
Txtal(max)
Tstg
maximum crystal temperature
storage temperature
150
°C
°C
°C
V
−65
−40
−2000
−200
+125
+85
Tamb
Ves
ambient temperature
electrostatic handling voltage
human body model
machine model
+2000
+200
V
Isc(DAC)
short-circuit current of DAC
note 2
output short-circuited to VSSA
output short-circuited to VDDA
−
−
450
300
mA
mA
Note
1. All supply connections must be made to the same power supply.
2. Short-circuit test at Tamb = 0 °C and VDDA = 3 V. DAC operation after short-circuiting cannot be warranted.
10 HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, it is good practice to take
normal precautions appropriate to handling MOS devices.
11 THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
VALUE
UNIT
Rth(j-a)
thermal resistance from junction to ambient in free air
145
K/W
12 QUALITY SPECIFICATION
In accordance with “SNW-FQ-611-D”.
13 DC CHARACTERISTICS
VDDD = VDDA = 2.0 V; Tamb = 25 °C; RL = 5 kΩ; all voltages with respect to ground (pins VSSA and VSSD); unless
otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VDDA
DAC analog supply voltage note 1
1.8
1.8
2.0
2.0
3.6
3.6
V
VDDD
digital supply voltage
note 1
V
IDDA
DAC analog supply current normal operating mode
at 2.0 V supply voltage
−
−
2.3
3.5
−
−
mA
mA
at 3.0 V supply voltage
Sleep mode
at 2.0 V supply voltage
−
−
125
175
−
−
µA
µA
at 3.0 V supply voltage
2002 May 22
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Philips Semiconductors
Product specification
Low power audio DAC
UDA1334BT
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
IDDD
digital supply current
normal operating mode
at 2.0 V supply voltage
at 3.0 V supply voltage
−
−
1.4
2.1
−
−
mA
mA
Sleep mode;
at 2.0 V supply voltage
clock running
−
−
250
20
−
−
µA
µA
no clock running
Sleep mode;
at 3.0 V supply voltage
clock running
−
−
375
30
−
−
µA
µA
no clock running
Digital input pins; note 2
VIH
HIGH-level input voltage
at 2.0 V supply voltage
at 3.0 V supply voltage
at 2.0 V supply voltage
at 3.0 V supply voltage
1.3
2.0
−
−
−
−
−
−
3.3
5.0
V
V
VIL
LOW-level input voltage
−0.5
−0.5
−
+0.5
+0.8
1
V
V
ILI
Ci
input leakage current
input capacitance
µA
pF
−
10
3-level input: pin PCS
VIH
VIM
VIL
HIGH-level input voltage
0.9VDDD
0.4VDDD
−0.5
−
−
−
VDDD + 0.5
0.6VDDD
+0.5
V
V
V
MID-level input voltage
LOW-level input voltage
DAC
Vref(DAC)
Ro(ref)
reference voltage
with respect to VSSA
0.45VDDA
0.5VDDA
25
0.55VDDA
V
output resistance on
pin Vref(DAC)
−
−
kΩ
Io(max)
maximum output current
(THD + N)/S < 0.1%;
RL = 800 Ω
−
1.6
−
mA
RL
CL
load resistance
3
−
−
−
50
kΩ
pF
load capacitance
note 3
−
Notes
1. All supply connections must be made to the same external power supply unit.
2. At 3 V supply voltage, the input pads are TTL compatible. However, at 2.0 V supply voltage no TTL levels can be
accepted, but levels from 3.3 V domain can be applied to the pins.
3. When the DAC drives a capacitive load above 50 pF, a series resistance of 100 Ω must be used to prevent
oscillations in the output operational amplifier.
2002 May 22
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Philips Semiconductors
Product specification
Low power audio DAC
UDA1334BT
14 AC CHARACTERISTICS
14.1 2.0 V supply voltage
VDDD = VDDA = 2.0 V; fi = 1 kHz; Tamb = 25 °C; RL = 5 kΩ.; all voltages with respect to ground (pins VSSA and VSSD);
unless otherwise specified.
SYMBOL
DAC
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Vo(rms)
output voltage (RMS value)
unbalance between channels
at 0 dB (FS) digital input
fs = 44.1 kHz; at 0 dB
−
600
−
mV
∆Vo
−
−
−
0.1
−
−
−
dB
dB
dB
(THD + N)/S total harmonic
distortion-plus-noise to signal
−80
−37
fs = 44.1 kHz; at −60 dB;
A-weighted
ratio
fs = 96 kHz; at 0 dB
−
−
−75
−35
97
−
−
−
−
−
−
dB
dB
dB
dB
dB
dB
fs = 96 kHz; at −60 dB; A-weighted
fs = 44.1 kHz; code = 0; A-weighted −
S/N
signal-to-noise ratio
fs = 96 kHz; code = 0; A-weighted
−
−
−
95
αcs
channel separation
100
60
PSRR
power supply rejection ratio
fripple = 1 kHz; Vripple = 30 mV (p-p)
14.2 3.0 V supply voltage
VDDD = VDDA = 3.0 V; fi = 1 kHz; Tamb = 25 °C; RL = 5 kΩ; all voltages with respect to ground (pins VSSA and VSSD);
unless otherwise specified.
SYMBOL
DAC
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Vo(rms)
output voltage (RMS value)
unbalance between channels
at 0 dB (FS) digital input
fs = 44.1 kHz; at 0 dB
−
900
−
mV
∆Vo
−
−
−
0.1
−
−
−
dB
dB
dB
(THD + N)/S total harmonic
distortion-plus-noise to signal
−90
−40
fs = 44.1 kHz; at −60 dB;
A-weighted
ratio
fs = 96 kHz; at 0 dB
−
−
−85
−37
100
98
−
−
−
−
−
−
dB
dB
dB
dB
dB
dB
fs = 96 kHz; at −60 dB; A-weighted
fs = 44.1 kHz; code = 0; A-weighted −
S/N
signal-to-noise ratio
fs = 96 kHz; code = 0; A-weighted
−
−
−
αcs
channel separation
100
60
PSRR
power supply rejection ratio
fripple = 1 kHz; Vripple = 30 mV (p-p)
2002 May 22
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Philips Semiconductors
Product specification
Low power audio DAC
UDA1334BT
14.3 Timing
VDDD = VDDA = 1.8 to 3.6 V; Tamb = −20 to +85 °C; RL = 5 kΩ; all voltages with respect to ground (pins VSSA and VSSD);
unless otherwise specified; note 1.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
System clock timing (see Fig.6)
Tsys
system clock cycle time
fsys = 256fs
35
88
780
520
390
ns
f
sys = 384fs
sys = 512fs
23
59
44
−
−
−
ns
ns
f
17
tCWH
system clock HIGH time
system clock LOW time
fsys < 19.2 MHz
fsys ≥ 19.2 MHz
fsys < 19.2 MHz
fsys ≥ 19.2 MHz
0.3Tsys
0.4Tsys
0.3Tsys
0.4Tsys
0.7Tsys ns
0.6Tsys ns
0.7Tsys ns
0.6Tsys ns
tCWL
−
Reset timing
treset
reset time
1
−
−
µs
Serial interface timing (see Fig.7)
fBCK
bit clock frequency
bit clock HIGH time
bit clock LOW time
rise time
−
−
−
−
−
−
−
−
−
−
64fs
−
−
20
20
−
−
−
−
Hz
ns
ns
ns
ns
ns
ns
ns
ns
tBCKH
tBCKL
tr
50
50
−
−
20
0
tf
fall time
tsu(DATAI)
th(DATAI)
tsu(WS)
th(WS)
set-up time data input
hold time data input
set-up time word select
hold time word select
20
10
Note
1. The typical value of the timing is specified at fs = 44.1 kHz (sampling frequency).
2002 May 22
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Philips Semiconductors
Product specification
Low power audio DAC
UDA1334BT
t
CWH
MGR984
t
CWL
T
sys
Fig.6 System clock timing.
WS
t
h(WS)
t
BCKH
t
su(WS)
t
t
f
r
BCK
t
su(DATAI)
t
BCKL
T
t
cy(BCK)
h(DATAI)
DATAI
MGL880
Fig.7 Serial interface timing.
2002 May 22
15
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Product specification
Low power audio DAC
UDA1334BT
15 APPLICATION INFORMATION
analog
digital
supply voltage
supply voltage
R7
1 Ω
R6
1 Ω
C9
C5
47 µF
(16 V)
47 µF
(16 V)
C10
C6
100 nF
(63 V)
100 nF
(63 V)
V
V
V
V
SSA
DDA
SSD
DDD
14
15
13
5
4
R5
SYSCLK
system
clock
6
47 Ω
C3
R3
VOUTL
left
output
100 Ω
BCK
WS
47 µF
1
R1
220 kΩ
(16 V)
C1
10 nF
(63 V)
2
DATAI
SFOR1
SFOR0
3
7
C4
R4
100 Ω
VOUTR
right
output
16
12
11
UDA1334BT
47 µF
(16 V)
R2
220 kΩ
10 nF
(63 V)
C2
MUTE
DEEM
PCS
8
V
ref(DAC)
9
C8
100 nF
(63 V)
C7
47 µF
(16 V)
10
MGU677
Fig.8 Typical application diagram.
2002 May 22
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Product specification
Low power audio DAC
UDA1334BT
16 PACKAGE OUTLINE
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
c
y
H
v
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.050
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
97-05-22
99-12-27
SOT109-1
076E07
MS-012
2002 May 22
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Product specification
Low power audio DAC
UDA1334BT
17 SOLDERING
If wave soldering is used the following conditions must be
observed for optimal results:
17.1 Introduction to soldering surface mount
packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
17.2 Reflow soldering
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 220 °C for
thick/large packages, and below 235 °C for small/thin
packages.
17.4 Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
17.3 Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
2002 May 22
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Product specification
Low power audio DAC
UDA1334BT
17.5 Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE(1)
WAVE
not suitable
REFLOW(2)
BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA
suitable
HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, not suitable(3)
HVSON, SMS
suitable
PLCC(4), SO, SOJ
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
suitable
not recommended(4)(5) suitable
not recommended(6)
suitable
Notes
1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy
from your Philips Semiconductors sales office.
2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.
4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2002 May 22
19
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Product specification
Low power audio DAC
UDA1334BT
18 DATA SHEET STATUS
PRODUCT
STATUS(2)
DATA SHEET STATUS(1)
DEFINITIONS
Objective data
Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
Preliminary data
Product data
Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Changes will be
communicated according to the Customer Product/Process Change
Notification (CPCN) procedure SNW-SQ-650A.
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
19 DEFINITIONS
20 DISCLAIMERS
Short-form specification
The data in a short-form
Life support applications
These products are not
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes
Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
the use of any of these products, conveys no licence or title
under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.
Application information
Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2002 May 22
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Product specification
Low power audio DAC
UDA1334BT
NOTES
2002 May 22
21
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Product specification
Low power audio DAC
UDA1334BT
NOTES
2002 May 22
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Product specification
Low power audio DAC
UDA1334BT
NOTES
2002 May 22
23
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©cKoninklijke Philips Electronics N.V.c2002SCA74All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changedwithout notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any licenseunder patent- or other industrial or intellectual property rights.Philips Semiconductors
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