Oki Network Card MSM66201 User Manual

E2E1027-27-Y4  
This version: Jan. 1998  
Previous version: Nov. 1996  
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MSM66201/66P201/66207/  
66P207  
OLMS-66K Series 16-Bit Microcontroller  
GENERAL DESCRIPTION  
The MSM66201/66207 is a high performance microcontroller that employs OKI original nX-8/  
200 CPU core. This chip includes a 16-bit CPU, ROM, RAM, I/O ports, multifunction 16-bit  
timers, 10-bit A/D converter, serial I/O port, and pulse width modulator (PWM). The  
MSM66P201/66P207 is the OTP (One-Time Programmable) version of the MSM66201/66207.  
FEATURES  
• 64K address space for program memory  
• 64K address space for data memory  
: Internal ROM : MSM66201  
MSM66207  
16K bytes  
32K bytes  
512 bytes  
1024 bytes  
: Internal RAM : MSM66201  
MSM66207  
• High-speed execution  
Minimum cycle for instruction  
• Powerful instruction set  
: 400ns @ 10MHz  
: Instruction set superior in orthogonal matrix  
8/16-bit data transfer instructions  
8/16-bit arithmetic instructions  
Multiplication and division operation instructions  
Bit manipulation instructions  
Bit logic instrucitons  
ROM table reference instructions  
: Register addressing  
• Abundant addressing modes  
Page addressing  
Pointing register indirect addressing  
Stack addressing  
Immediate value addressing  
• I/O port  
Input-output port  
: 5 ports ¥ 8 bits  
(Each bit can be assigned to input or output)  
Input port  
• Built-in multifunctional 16-bit timer  
Following 4 modes can be set for each timer : Auto-reload timer mode  
Clock output mode  
: 1 port ¥ 8 bits  
: 4  
Capture register mode  
Real time output mode  
• Serial port  
: 1 channel (Synchronous/UART switchable  
mode with baud rate generators)  
: 2  
• 16-bit pulse width modulator  
• Watchdog timer  
• Transition detector  
• 10-bit A/D converter  
• Interrupts  
: 4  
: 8 channels  
Nonmaskable  
Maskable  
: 1  
: Internal 16/external 2  
• Stand-by function  
STOP mode  
: Software clock stop mode  
: Software CPU stop mode  
: Hardware CPU stop mode  
HALT mode  
HOLD mode  
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MSM66201/66P201/66207/66P207  
BLOCK DIAGRAM  
P5  
P4  
P3  
P2  
P1  
P0  
HLDA/P2.5  
HOLD/P2.4  
FLT  
RES  
OSC1  
OSC0  
GND  
VDD  
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MSM66201/66P201/66207/66P207  
PIN CONFIGURATION (TOP VIEW)  
AD0/P0.0  
AD1/P0.1  
AD2/P0.2  
AD3/P0.3  
AD4/P0.4  
AD5/P0.5  
AD6/P0.6  
AD7/P0.7  
A8/P1.0  
1
2
3
4
5
6
7
8
9
64 VDD  
63 VREF  
62 AGND  
61 P5.7/AI7  
60 P5.6/AI6  
59 P5.5/AI5  
58 P5.4/AI4  
57 P5.3/AI3  
56 P5.2/AI2  
55 P5.1/AI1  
54 P5.0/AI0  
53 P4.7/TRNS3  
52 P4.6/TRNS2  
51 P4.5/TRNS1  
50 P4.4/TRNS0  
49 P4.3/PWM1  
48 P4.2/PWM0  
47 P4.1/TM1CK  
46 P4.0/TM0CK  
45 P3.7/TM3IO  
44 P3.6/TM2IO  
A9/P1.1 10  
A10/P1.2 11  
A11/P1.3 12  
A12/P1.4 13  
A13/P1.5 14  
A14/P1.6 15  
A15/P1.7 16  
P2.0 17  
P2.1 18  
P2.2 19  
CLKOUT/P2.3 20  
RESOUT 21  
22  
23  
24  
43  
42  
41  
ALE  
PSEN  
RD  
P3.5/TM1IO  
P3.4/TM0IO  
P3.3/INT1  
WR 25  
READY 26  
EA 27  
40 P3.2/INT0  
39 P3.1/RXD  
38 P3.0/TXD  
37 P2.7/RXC  
36 P2.6/TXC  
35 P2.5/HLDA  
34 P2.4/HOLD  
FLT 28  
RES 29  
OSC0 30  
OSC1 31  
GND  
NMI  
32  
33  
64-Pin Plastic Shrink DIP  
4/30  
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MSM66201/66P201/66207/66P207  
PIN CONFIGURATION (TOP VIEW) (Continued)  
A8/P1.0  
A9/P1.1  
A10/P1.2  
A11/P1.3  
A12/P1.4  
A13/P1.5  
A14/P1.6  
A15/P1.7  
P2.0  
1
2
3
4
5
6
7
8
9
48 P5.2/AI2  
47 P5.1/AI1  
46 P5.0/AI0  
45 P4.7/TRNS3  
44 P4.6/TRNS2  
43 P4.5/TRNS1  
42 P4.4/TRNS0  
41 P4.3/PWM1  
40 P4.2/PWM0  
39 P4.1/TM1CK  
38 P4.0/TM0CK  
37 P3.7/TM3IO  
36 P3.6/TM2IO  
35 P3.5/TM1IO  
34 P3.4/TM0IO  
33 P3.3/INT1  
P2.1 10  
P2.2 11  
CLKOUT/P2.3 12  
RESOUT 13  
ALE 14  
PSEN 15  
RD 16  
64-Pin Plastic QFP  
5/30  
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MSM66201/66P201/66207/66P207  
PIN CONFIGURATION (TOP VIEW) (Continued)  
AI3/P5.3  
AI4/P5.4  
AI5/P5.5  
AI6/P5.6  
AI7/P5.7  
AGND  
P3.2/INT0  
P3.1/RXD  
P3.0/TXD  
P2.7/RXC  
P2.6/TXC  
P2.5/HLDA  
P2.4/HOLD  
NMI  
61  
62  
63  
64  
65  
66  
67  
68  
1
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
VREF  
VDD  
GND  
VDD  
AD0/P0.0  
AD1/P0.1  
AD2/P0.2  
AD3/P0.3  
AD4/P0.4  
AD5/P0.5  
AD6/P0.6  
AD7/P0.7  
GND  
2
OSC1  
OSC0  
3
4
RES  
FLT  
EA  
READY  
WR  
5
6
7
8
9
NC : No-connection pin  
68-Pin Plastic QFJ (PLCC)  
6/30  
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MSM66201/66P201/66207/66P207  
PIN DESCRIPTION  
Symbol  
Type  
Description  
I/O  
P0.0–P0.7/  
AD0–AD7  
P0: 8-bit input-output port. Each bit can be assigned to input or output.  
AD: Outputs the lower 8 bits of program counter during external program memory fetch,  
and receives the addressed instruction under the control of PSEN. This pin also  
outputs the address and outputs or inputs data during an external data memory  
access instruction, under the control of ALE, RD, and WR.  
P1.0–P1.7/  
A8–A15  
I/O  
I/O  
P1: 8-bit input-output port. Each bit can be assigned to input or output.  
A: Outputs the upper 8 bits of program counter (PC8–15) during external program  
memory fetch. This pin also outputs the upper 8 bits of address during external  
data memory access instructions.  
P2.0–P2.2  
P2.3/CLKOUT  
P2: 8-bit input-output port. Each bit can be assigned to input or output.  
CLKOUT: Output pin for supplying a clock to peripheral circuits.  
HOLD: Input pin to request the CPU to enter the hardware power-down state.  
P2.4/HOLD  
P2.5/HLDA  
HLDA: HOLD ACKNOWLEDGE: the HLDA signal appears in response to the HOLD  
signal and indicates that the CPU has entered the power-down state.  
P2.6/TXC  
P2.7/RXC  
TXC: Transmitter clock input/output pin.  
RXC: Receiver clock input/output pin.  
P3.0/TXD  
P3: 8-bit input-output port. Each bit can be assigned to input or output.  
TXD: Transmitter data output pin.  
I/O  
P3.1/RXD  
P3.2/INT0  
P3.3/INT1  
P3.4/TM0IO  
P3.5/TM1IO  
P3.6/TM2IO  
P3.7/TM3IO  
RXD: Receiver data input pin.  
INT: Interrupt request input pin.  
Falling edge trigger or level trigger is selectable.  
TM0IO-TM3IO: One of the following signals is output or input.  
• Clock at twice the frequency range of the 16-bit timer overflow  
• Load trigger signal to the capture register input  
• Setting value output  
Whether the signal is input or output depends on the mode.  
P4.0/TM0CK  
P4.1/TM1CK  
I/O  
P4: 8-bit input-output port. Each bit can be assigned to input or output.  
TM0CK, TM1CK: Clock input pins of timer 0, timer 1.  
P4.2/PWM0  
P4.3/PWM1  
P4.4 – P4.7/  
TRANS: Transition detector.  
The input pins which sense the falling edge and set the flag.  
PWM: 16-bit pulse-width modulator output pin.  
TRANS0 –  
TRANS3  
I
P5.0 – P5.7/  
AI0 –AI7  
P5: 8-bit input port.  
AI: Analog signal input pin for A/D converter.  
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MSM66201/66P201/66207/66P207  
PIN DESCRIPTION (Continued)  
Symbol  
RESOUT  
Type  
Description  
Outputs "H" level in the case of internal reset.  
Reset to"L" level by program.  
O
ALE  
Address Latch Enable:  
O
The timing pulse to latch the lower 8 bits of the address  
output from port 0 when the CPU accesses the external  
memory.  
O
O
O
The strobe pulse to fetch to external program  
memory.  
PSEN  
RD  
Program Strobe Enable:  
Output strobe activated during a bus read cycle.  
Used to enable data onto the bus from the external data memory.  
WR  
Output strobe during a bus write cycle.  
Used as write strobe to external data memory.  
READY  
I
I
Used when the CPU accesses low-speed peripherals.  
EA  
Normaly set to "H" level.  
If set to "L" level, the CPU fetches the code from external program memory.  
FLT  
I
If FLT is "H" level, ALE, WR, RD, PSEN are set to "H" level when reset.  
If FLT is set to "L", ALE, WR, RD, PSEN are set to floating level when reset.  
I
RES  
RESET input pin.  
OSC0  
OSC1  
NMI  
Basic clock oscillation pin.  
Basic clock oscillation pin.  
Non-maskable interrupt input pin (falling edge).  
Reference voltage input pin for A/D converter.  
Ground for A/D converter.  
System power supply.  
I
O
I
VREF  
AGND  
VDD  
GND  
Ground.  
8/30  
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MSM66201/66P201/66207/66P207  
REGISTERS  
Accumulator  
15  
0
ACC  
Control Register (CR)  
15  
0
PSW  
Bit 15 : Carry flag (CY)  
Bit 14 : Zero flag (ZF)  
Bit 13 : Half carry flag (HC)  
Bit 12 : Data descriptor (DD)  
Bit 8 : Master interrupt priority flag (MIP)  
Bit 9,5,4: User flag (MIP)  
Bit 2-0 : System control base 2-0 (SCB2-0)  
15  
0
PC  
LRB  
SSP  
Pointing Register (PR)  
15  
0
X1  
Index Register 1  
Index Register 2  
X2  
DP  
Data Pointer  
User Stack Pointer  
USP  
Local Register  
7
0
7
0
ER0  
ER1  
ER2  
ER3  
R1  
R0  
R2  
R4  
R6  
R3  
R5  
R7  
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MSM66201/66P201/66207/66P207  
SFR  
Address  
(HEX)  
8/16-bit  
Operation  
Name  
Symbol R/W  
Reset  
0000  
FFH  
FFH  
SSP  
(ASSP)  
System stack printer  
0001  
0002  
0003  
0004I  
0005I  
0006  
0007  
0010I  
0011  
0012I  
0013  
0018  
0019  
001A  
001B  
001CI  
0020  
0021  
0022  
0023  
0024  
0025  
0026I  
0028  
0029  
002A  
002C  
002D  
002E  
002F  
LRB  
(ALRB)  
undefined  
Local register base  
Program status word  
Accumulator  
R/W  
8/16  
PSWL  
C8H  
0CH  
00H  
00H  
F8H  
(APSW)  
PSWH  
ACC  
Standby control register  
Watchdog timer  
SBYCON  
00H/WDT  
WDT  
W
R/W  
W
is stopped  
8
FDH  
"0"  
Peripheral control register  
Stop code acceptor  
PRPHF  
STPACP  
00H  
Interrupt request register  
Interrupt enable register  
IRQ  
IE  
00H  
8/16  
00H  
00H  
FCH  
External Iinterrupt control register  
Port 0 data register  
EXICON  
P0  
undefined  
00H  
Port 0 mode register  
P0IO  
P1  
undefined  
00H  
Port 1 data register  
Port 1 mode register  
R/W  
P1IO  
P2  
undefined  
00H  
Port 2 data register  
Port 2 mode register  
P2IO  
P2SF  
P3  
8
07H  
Port 2 secondary function control register  
Port 3 data register  
undefined  
00H  
Port 3 mode register  
P3IO  
P3SF  
P4  
00H  
Port 3 secondary function control register  
Port 4 data register  
undefined  
00H  
Port 4 mode register  
P4IO  
P4SF  
P5  
00H  
Port 4 secondary function control register  
Port 5  
R
0030  
0031  
0032  
0033  
0034  
0035  
0036  
0037  
00H  
Timer 0 counter  
Timer 0 register  
Timer 1 counter  
Timer 1 register  
TM0  
TMR0  
TM1  
00H  
00H  
00H  
R/W  
16  
00H  
00H  
00H  
TMR1  
00H  
Note: A I mark in the address column indicates that there is a bit that does not exist in the  
register.  
10/30  
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MSM66201/66P201/66207/66P207  
SFR (Continued)  
Addres  
(HEX)  
Abbreviated  
8/16-bit  
Operation  
Name  
R/W  
Reset  
Name  
0038  
00H  
00H  
Timer 2 counter  
0039  
TM2  
003A  
00H  
Timer 2 register  
003B  
TMR2  
TM3  
00H  
16  
003C  
00H  
Timer 3 counter  
003D  
00H  
003E  
00H  
Timer 3 register  
003F  
TMR3  
00H  
0040  
00H  
Timer 0 control register  
TCON0  
TCON1  
TCON2  
TCON3  
TRNSIT  
STTM  
0041  
00H  
Timer 1 control register  
R/W  
0042  
00H  
Timer 2 control register  
0043  
00H  
Timer 3 control register  
0046I  
0048  
undefined  
00H  
Transition detector register  
Serial port transmission baud rate generator counter  
Serial port transmission baud rate generator register  
0049  
00H  
STTMR  
STTMC  
004AI  
0CH  
Serial port transmission baud rate generator control  
register  
Serial port receiving baud rate generator counter  
8
004C  
00H  
00H  
0EH  
SRTM  
SRTMR  
SRTMC  
004D  
Serial port receiving baud rate generator register  
Serial port receiving baud rate generator control  
register  
004EI  
Serial port transmission mode control register  
Serial port transmission data buffer register  
Serial port receiving mode control register  
Serial port receiving data buffer register  
Serial port receiving error register  
A/D scan mode register  
0050I  
0051  
80H  
undefined  
00H  
STCON  
STBUF  
W
R/W  
R
0054  
SRCON  
SRBUF  
SRSTAT  
0055  
undefined  
F0H  
0056I  
0058I  
0059I  
0060I  
0061  
80H  
ADSCAN R/W  
ADSEL  
A0H  
A/D select mode register  
A/D conversion result register 0  
ADCR0  
R
8/16  
undefined  
Note: A I mark in the address column indicates that there is a bit that does not exist in the  
register.  
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MSM66201/66P201/66207/66P207  
SFR (Continued)  
Address  
(HEX)  
Abbreviated  
Name  
8/16-bit  
operation  
Name  
R/W  
Reset  
0062I  
A/D conversion result register 1  
A/D conversion result register 2  
A/D conversion result register 3  
A/D conversion result register 4  
A/D conversion result register 5  
A/D conversion result register 6  
A/D conversion result register 7  
PWM 0 counter  
ADCR1  
ADCR2  
ADCR3  
ADCR4  
ADCR5  
ADCR6  
ADCR7  
PWMC0  
PWMR0  
0063  
0064I  
0065  
0066I  
0067  
R
undefined  
0068I  
0069  
006AI  
006B  
006CI  
006D  
006EI  
006F  
8/16  
0070  
00H  
00H  
00H  
00H  
00H  
00H  
00H  
00H  
00H  
00H  
0071  
0072  
PWM 0 register  
0073  
0074  
PWM 1 counter  
PWMC1 R/W  
PWMR1  
0075  
0076  
PWM 1 register  
0077  
0078  
PWM 0 control register  
PWM 1 countrol register  
PWCON0  
PWCON1  
8
007A  
Note: A I mark in the address column indicates that there is a bit that does not exist in the  
register.  
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MSM66201/66P201/66207/66P207  
ADDRESSING MODES  
The MSM66201/66207 provides independent 64K-byte data and 64K-byte program space with  
varioustypesofaddressingmodes.Thesemodesareshownbelow,forbothRAM(fordataspace)  
and ROM (for program space).  
1. RAM Addressing Modes (for data space)  
1.1  
Register Direct Addressing  
Example  
ROR  
DP  
DP  
1.2  
Displacement Addressing  
a) Zero Page  
Example  
L
0000H  
0018H  
A, 18H  
SFR  
b) Direct Page  
Example  
xx00H  
xx10H  
ST  
A, off 10H  
RAM  
1.3  
Pointing Register (PR) Indirect Addressing  
a) Data Point (DP) Indirect  
Example  
SLL  
[DP]  
DP  
RAM  
b) User Stack Pointer (USP) Indirect  
Example  
SRL 10H [USP]  
RAM  
USP  
–128 to +127  
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MSM66201/66P201/66207/66P207  
c) Index Register (X1, X2) Indirect  
Example  
INC 300H [X1]  
RAM  
X1  
0 to 65535  
1.4  
Immediate Addressing  
Example  
MOV  
SSP, #27FH  
2. ROM Addressing Modes (for program space)  
2.1  
Direct Addressing  
Example  
LC  
200H  
A,  
ROM  
0200H  
2.2  
Simple Indirect Addressing  
a) Local Register Indirect  
Example  
LC  
A,[ER0]  
ER0  
ROM  
b) Pointing Register Indirect  
1)  
Data Pointer (DP) Indirect  
Example  
LC  
A, [DP]  
DP  
ROM  
2)  
User Stack Pointer (USP) Indirect  
Example  
LC  
A,[USP]  
USP  
ROM  
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3)  
Index Register (X1, X2) Indirect  
Example  
LC  
A, [X1]  
X1  
ROM  
ROM  
c) System Stack Pointer (SSP) Indirect  
Example  
LC  
A,[SSP]  
SSP  
d) Local Register Base (LRB) Indirect  
Example  
LC  
A,[LRB]  
LRB  
ROM  
e) RAM Indirect  
Example  
J
A, [0C0H]  
RAM  
ROM  
0C0H  
2.3  
Double Indirect Addressing  
a) Data Pointer (DP) Double Indirect  
Example  
J
[[DP]]  
RAM  
ROM  
DP  
b) User Stack Pointer (USP) Double Indirect  
Example  
LC A, [–2 [USP]]  
RAM  
ROM  
USP  
–128 to +127  
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c) Index Register (X1, X2) Double Indirect  
Example  
LC A, [10000H [x1]]  
RAM  
ROM  
X1  
0 to 65535  
2.4  
Indirect Addressing with 16-bit Offset  
a) Pointing Register Indirect  
1)  
2)  
3)  
Data Pointer (DP) Indirect  
Example  
LC  
A, [100H [DP]]  
ROM  
DP  
0 to 65535  
User Stack Pointer (USP) Indirect  
Example  
LC A, [100H [USP]]  
ROM  
USP  
0 to 65535  
Index Register (X1, X2) Indirect  
Example  
LC  
A, [100H [X1]]  
ROM  
X1  
0 to 65535  
b) RAM Indirect  
Example  
LC A, [2000H [80H]]  
RAM  
80H  
ROM  
0 to 65535  
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MSM66201/66P201/66207/66P207  
MEMORY MAPS  
Program Memory Space  
0000H  
0000H  
Vector  
Table  
Area  
(40 bytes)  
0027H  
0028H  
Internal  
ROM Area  
VCAL  
Table  
Area  
(16 bytes)  
0037H  
0038H  
7FFFH *  
External  
Memory  
FFFFH  
7FFFH *  
* MSM66201 : 3FFFH  
Data Memory Space  
0000H  
0000H  
SFR Area  
PR Area  
Special  
Function  
Registors  
007FH  
0080H  
Zero  
00BFH  
Page  
00C0H  
PORT, A/DC,  
TIMER, PWM,  
etc....  
00FFH  
0100H  
007FH  
0080H  
Internal  
RAM  
80  
82  
(Low Order)  
(High Order)  
PR0  
PR1  
PR2  
PR3  
PR4  
PR5  
PR6  
PR7  
X1  
X2  
Area  
047FH *  
84  
86  
DP  
USP  
00BFH  
00C0H  
External  
Memoly  
Area  
FFFFH  
047FH *  
* MSM66201 : 027FH  
17/30  
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MSM66201/66P201/66207/66P207  
ABSOLUTE MAXIMUM RATINGS  
(Ta=25°C)  
Parameter  
Supply Voltage  
Symbol  
VDD  
VI  
Condition  
Rating  
–0.3 to 7.0  
–0.3 to VDD+0.3  
–0.3 to VDD+0.3  
–0.3 to VDD+0.3  
–0.3 to VREF  
930  
Unit  
Input Voltage  
Output Voltage  
VO  
V
GND=AGND=0V  
Analog Ref. Voltage  
Analog Input Voltage  
VREF  
VAI  
64-pin shrink DIP  
Ta=85°C  
per Package  
Power Dissipation  
PD  
64-pin QFP  
68-pin QFJ  
565  
mW  
°C  
1120  
–55 to +150  
Storage Temperature  
TSTG  
RECOMMENDED OPERATING CONDITIONS  
Parameter  
Supply Voltage  
Symbol  
VDD  
Condition  
fOSC £ 10MHz  
fOSC = 0Hz  
Range  
4.5 to 5.5  
2.0 to 5.5  
0 to 10  
–40 to +85  
20  
Unit  
V
Memory Hold Voltage  
Operating Frequency  
Ambient Temperature  
VDDH  
fOSC  
MHz  
°C  
V
DD = 5V 10%  
Ta  
MOS load  
P0  
Fan Out  
N
2
TTL load  
P1, P2, P3, P4  
1
18/30  
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MSM66201/66P201/66207/66P207  
ELECTRICAL CHARACTERISTICS  
DC Characteristics  
(VDD = 5V 10%, Ta = –40 to +85°C)  
Parameter  
Symbol  
Condition  
Min.  
2.4  
4.0  
4.2  
3.6  
–0.3  
–0.3  
–0.3  
4.2  
4.2  
Typ.  
5
Max.  
VDD+0.3  
VDD+0.3  
VDD+0.3  
VDD+0.3  
0.8  
Unit  
"H" Input Voltage 1, 3, 6  
"H" Input Voltage 5, 7  
"H" Input Voltage 8  
"H" Input Voltage 2  
"L" Input Voltage 1, 2, 3, 6  
"L" Input Voltage 5, 7  
"L" Input Voltage 8  
VIH  
VIL  
0.8  
V
0.4  
"H" Output Voltage 1, 4  
"H" Output Voltage 2  
"L" Output Voltage 1, 4  
"L" Output Voltage 2  
Input Leakage Current 3, 6, 7  
Input Current 5  
IO = –400mA  
IO = –200mA  
IO = 3.2mA  
IO = 1.6mA  
VOH  
VOL  
0.4  
0.4  
1/–1  
1/–20  
IIH/IIL  
VI = VDD/0V  
mA  
Input Current 8  
10/10  
"H" Output Current 1  
"H" Output Current 2  
"L" Output Current 1  
"L" Output Current 2  
Output Leakage Current 1, 2, 4  
Input Capacitance  
–2  
2
IOH  
IOL  
–1  
mA  
VO = 2.4V  
10  
5
ILO  
CI  
VO = VDD 0V  
/
mA  
2
f = 1MHz  
Ta = 25°C  
pF  
Output Capacitance  
CO  
7
A/D in operation  
A/D stopped  
VDD = 2V  
0.3  
0.5  
0.2  
1
mA  
Analog Reference Power  
Supply Current  
IREF  
IDDS  
IDDH  
IDD  
10  
10  
100  
10  
15  
35  
40  
mA  
Current Consumption  
(during STOP) *  
mA  
6
Current Consumption  
(during HALT)  
**  
8
f
OSC = 10MHz  
No Load  
mA  
20  
30  
Current Consumption  
**  
Note:  
1
2
3
4
5
6
7
8
*
Applied to P0  
Applied to P1, P2, P3 and P4  
Applied to P5  
Applied to ALE, PSEN, RD, WR and RESOUT  
Applied to RES and NMI  
Applied to READY and EA  
Applied to FLT  
Applied to OSC  
0
V
DD  
or GND for ports serving as the input pin. No load for any other.  
** Applied to MSM66P201/66P207  
19/30  
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MSM66201/66P201/66207/66P207  
AC Characteristics  
• External program memory control  
(VDD=5V 10%, Ta=–40 to +85°C)  
Parameter  
Symbol  
tfW  
Condition  
Min.  
Max.  
Unit  
Clock (OSC) Pulse  
50  
ALE Pulse Width  
tAW  
3tfW  
–20  
–20  
–20  
PSEN Pulse Width  
tPW  
4tfW  
PSEN Pulse Delay Time  
Low Address Setup time  
Low Address Hold Time  
High Address Delay Time  
High Address Hold Time  
Instruction Setup Time  
Instruction Hold Time  
tPAD  
tAAS  
tAAH  
tAAD  
tAPH  
tIS  
tfW  
2tfW  
tfW  
+20  
2tfW  
–35  
–20  
–20  
–20  
+20  
+40  
+40  
+40  
ns  
CL = 50pF  
tfW  
tfW  
tfW  
tfW  
tfW  
tfW  
100  
tIH  
0
tfW  
–20  
• External data memory control  
(VDD=5V 10%, Ta=–40 to +85°C)  
Parameter  
Clock (OSC) Pulse  
Symbol  
tfW  
Condition  
Min.  
Max.  
Unit  
50  
ALE Pulse Width  
tAW  
3tfW  
–20  
–20  
–20  
–20  
–20  
RD Pulse Width  
tRW  
4tfW  
4tfW  
WR Pulse Width  
tWW  
tRAD  
tWAD  
tAAS  
tAAH  
tAAD  
tARH  
tAWH  
tMS  
RD Pulse Delay Time  
WR Pulse Delay Time  
Low Address Setup Time  
Low Address Hold Time  
High Address Setup Time  
High Address Hold Time  
High Address Hold Time  
Memory Data Setup Time  
Memory Data Hold Time  
Data Delay Time  
tfW  
tfW  
2tfW  
tfW  
+20  
+20  
tfW  
2tfW  
–35  
–20  
–20  
–20  
–20  
+20  
+40  
+40  
+40  
+40  
tfW  
tfW  
tfW  
tfW  
tfW  
tfW  
tfW  
tfW  
ns  
CL = 50pF  
100  
tMH  
0
tfW  
tfW  
tfW  
–20  
+40  
+40  
tDD  
tfW  
–20  
–20  
Data Hold Time  
tDH  
tfW  
20/30  
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MSM66201/66P201/66207/66P207  
CLK  
tW tW  
ALE  
tAW  
PSEN  
tPAD  
tPW  
AD0-7  
PC0-7  
tAAS  
INST0-7  
tAAH  
tIS  
tIH  
A8-15  
PC8-15  
RAP8-15  
RAP8-15  
tAAD  
tAAD  
tAAD  
tAPH  
RD  
tRAD  
tRW  
AD0-7  
A8-15  
WR  
RAP0-7  
tAAS tAAH  
DIN0-7  
tMS  
tMH  
tAPH  
tWAD  
tWW  
AD0-7  
A8-15  
RAP0-7  
tAAS  
DOUT0-7  
tAAH  
tDD  
tDH  
tAWH  
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MSM66201/66P201/66207/66P207  
• Serial port control  
Master mode  
(VDD=5V 10%, Ta=–40 to +85°C)  
Parameter  
Symbol  
tfW  
Condition  
Min.  
50  
Max.  
Unit  
Clock (OSC) Pulse Width  
Serial Clock Pulse Width  
Output Data Setup Time  
Output Data Hold Time  
Input Data Setup Time  
Input Data Hold Time  
tSCKW  
8tfW  
tSTMXS  
tSTMXH  
tSRMXS  
tSRMXH  
8tfW+40  
6tfW–20  
2tfW+10  
50  
ns  
CL=50pF  
Slave mode  
(VDD=5V 10%, Ta=–40 to +85°C)  
Parameter  
Symbol  
tfW  
Condition  
Min.  
50  
Max.  
Unit  
Clock (OSC) Pulse Width  
Serial Clock Pulse Width  
Output Data Setup Time  
Output Data Hold Time  
Input Data Setup Time  
Input Data Hold Time  
tSCKW  
tSTSXS  
tSTSXH  
tSRSXS  
tSRSXH  
8tfW  
6tfW+40  
6tfW–20  
100  
ns  
CL=50pF  
100  
22/30  
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MSM66201/66P201/66207/66P207  
OSC  
tW  
tW  
SCK  
tSCKW  
tSCKW  
SDOUT  
(TXD)  
tSTMXH  
tSTMXS  
SDIN  
(RXD)  
Valid  
Valid  
tSRMXH  
tSRMXS  
SCK  
tSCKW  
tSCKW  
SDOUT  
(TXD)  
tSTSXS  
tSTSXH  
SDIN  
(RXD)  
Valid  
Valid  
tSRSXH  
tSRSXS  
23/30  
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MSM66201/66P201/66207/66P207  
A/D Converter Characteristics  
• Operating range  
Parameter  
Symbol  
VDD  
Condition  
Min.  
4.5  
Typ.  
Max.  
5.5  
Unit  
V
Power Supply Voltage  
Analog Reference Voltage  
Analog Input Voltage  
fOSC £ 10MHz  
VR  
4.5  
VDD  
VR  
VAI  
VAG  
VAG = GND = 0V  
VDD = 5V 10%  
Analog Reference Power  
Voltage Resistance  
RR  
16  
kW  
°C  
Operating Temperature  
Top  
–40  
+85  
• A/D Converter accuracy  
Normal operation mode  
(VDD=5V 10%, fOSC=10MHz, Ta=–40 to +85°C)  
Min.  
Typ.  
Max.  
Parameter  
Resolution  
Symbol  
Condition  
Unit  
*
*
*
See the  
recommended  
circuit.  
n
0
0
0.5  
10  
10  
Bit  
+3.0  
+2.0  
Absolute Error  
Relative Error  
EA  
ER  
EZ  
EF  
ED  
EC  
–3.5  
–3.5  
VR=VDD  
1.5  
1.0  
VAG=GND=0V  
Analog input source  
impedance  
£5kW  
Zero Point Error  
Full Scale Error  
Differential Linearity Error  
Crosstalk  
+3.0 +2.0  
–3.5 –3.5  
+3.0 +2.0  
LSB  
–0.5 –1.0  
One channel  
conversion time  
tC=64ms  
0.5  
*
V =5V, Ta=25°C  
DD  
HALT/HOLD operation mode  
(VDD=5V 10%, fOSC=10MHz, Ta=–40 to +85°C)  
Min.  
Typ.  
Max.  
Parameter  
Resolution  
Symbol  
Condition  
Unit  
*
*
*
See the  
recommended  
circuit.  
n
0.5  
10  
10  
Bit  
+2.0  
+1.0  
Absolute Error  
Relative Error  
EA  
ER  
EZ  
EF  
ED  
EC  
–3.5  
–2.0  
VR=VDD  
1.0  
0.5  
VAG=GND=0V  
Zero Point Error  
Full Scale Error  
Differential Linearity Error  
Crosstalk  
Analog input source +0.5 +0.5  
impedance  
+2.0 +1.0  
–3.5 –2.0  
+2.0 +1.0  
LSB  
–1.0 –1.5  
£5kW  
One channel  
conversion time  
tC=64ms  
0.5  
*
V
DD  
=5V, Ta=25°C  
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MSM66201/66P201/66207/66P207  
• Recommended circuit  
Reference  
Voltage  
VREF  
VDD  
+5V  
+
+
0.1 47  
0.1 47  
mF mF  
mF mF  
RI  
+
AI0-7  
GND  
0V  
Analog Input  
AGND  
0.1  
mF  
R (Analog input source impedance) £ 5kW  
I
• A/D Converter conversion characteristics 1  
[HEX]  
3FF  
EF  
MAX  
EF  
MIN  
Ideal Conversion (center line)  
Actual Conversion width  
Conversion Code  
Actual Conversion (center line)  
000  
EZ  
EZ  
VREF [V]  
MIN  
MAX  
Analog Input  
Conversion Characteristics Diagram 1  
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MSM66201/66P201/66207/66P207  
Absolute error (E )  
A
The absolute error indicates a difference between actual conversion and ideal conversion,  
excluding a quantizing error. The absolute error of the A/D converter gets larger as it  
approaches the zero point or full scale. (Refer to Conversion Characteristics Diagram 1.)  
Relative error (E )  
R
The relative error indicates a deviation from a line which connects the center point of the zero  
point conversion width with that of the full scale conversion width, excluding a quantizing  
error.  
The relative error of this A/D converter is almost due to a differential linearity error.  
Zero point error (Ez) and full scale error (E )  
F
The zero point error and full scale error indicate a difference between actual conversion and  
ideal conversion at the zero point and full scale, respectively. (Refer to Conversion  
Characteristics Diagram 1.)  
A/D Converter Conversion Characteristics 2 (temperature characteristics)  
[HEX]  
3FF  
[LSB]  
+4  
+25°C  
–40°C  
+85°C  
+3  
ES  
Conversion  
Code  
Differential  
Linearity  
+2  
During normal  
operation  
ES  
+1  
0
During HALT  
ES  
000  
[°C]  
–40  
+85  
Eta  
[V]  
Analog Input  
Temparature Ta  
Conversion Characteristics  
Diagram 2-1  
Conversion Characteristics  
Diagram 2-2  
Differential linearity error (E )  
D
The differential linearity error indicates a difference between the actual conversion width  
(actual step width) and ideal value (1LSB).  
With this A/D converter, a voltage for actual conversion is shifted and the inclination of a  
voltage is changed, with changes of temperature (see Conversion Characteristics Diagram 2-  
1). Specifications described in the foregoing tables are established from Eta shown in  
ConversionCharacteristicsDiagram2-1(E =Eta–1LSB). ConversionCharacteristicsDiagram  
D
2-2showstemperaturecharacteristicsofdifferentiallinearityofEsinConversionCharacteristics  
Diagram 2-1.  
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PACKAGE DIMENSIONS  
SDIP64-P-750-1.78  
MSM66201/66P201/66207/66P207  
(Unit : mm)  
Package material  
Lead frame material  
Pin treatment  
Solder plate thickness  
Package weight (g)  
Epoxy resin  
Cu alloy  
Solder plating  
5 mm or more  
8.70 TYP.  
Notes for Mounting the Surface Mount Type Package  
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which  
are very susceptible to heat in reflow mounting and humidity absorbed in storage.  
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the  
product name, package name, pin number, package code and desired mounting conditions  
(reflow method, temperature and times).  
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MSM66201/66P201/66207/66P207  
(Unit : mm)  
QFP64-P-1414-0.80-BK  
Mirror finish  
Package material  
Lead frame material  
Pin treatment  
Solder plate thickness  
Package weight (g)  
Epoxy resin  
42 alloy  
Solder plating  
5 mm or more  
0.87 TYP.  
Notes for Mounting the Surface Mount Type Package  
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which  
are very susceptible to heat in reflow mounting and humidity absorbed in storage.  
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the  
product name, package name, pin number, package code and desired mounting conditions  
(reflow method, temperature and times).  
28/30  
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MSM66201/66P201/66207/66P207  
(Unit : mm)  
QFJ68-P-S950-1.27  
Mirror finish  
Package material  
Lead frame material  
Pin treatment  
Solder plate thickness  
Package weight (g)  
Epoxy resin  
Cu alloy  
Solder plating  
5 mm or more  
4.50 TYP.  
Notes for Mounting the Surface Mount Type Package  
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which  
are very susceptible to heat in reflow mounting and humidity absorbed in storage.  
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the  
product name, package name, pin number, package code and desired mounting conditions  
(reflow method, temperature and times).  
29/30  
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MSM66201/66P201/66207/66P207  
(Unit : mm)  
ADIP64-C-750-1.78  
Notes for Mounting the Surface Mount Type Package  
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which  
are very susceptible to heat in reflow mounting and humidity absorbed in storage.  
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the  
product name, package name, pin number, package code and desired mounting conditions  
(reflow method, temperature and times).  
30/30  
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This datasheet has been download from:  
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