Important Information
Warranty
The DAQCard-6024E, PCI-6023E, PCI-6024E, PCI-6025E, and PXI-6025E devices are warranted against defects in materials and
workmanship for a period of one year from the date of shipment, as evidenced by receipts or other documentation. National
Instruments will, at its option, repair or replace equipment that proves to be defective during the warranty period. This warranty
includes parts and labor.
The media on which you receive National Instruments software are warranted not to fail to execute programming instructions,
due to defects in materials and workmanship, for a period of 90 days from date of shipment, as evidenced by receipts or other
documentation. National Instruments will, at its option, repair or replace software media that do not execute programming
instructions if National Instruments receives notice of such defects during the warranty period. National Instruments does not
warrant that the operation of the software shall be uninterrupted or error free.
A Return Material Authorization (RMA) number must be obtained from the factory and clearly marked on the outside of
the package before any equipment will be accepted for warranty work. National Instruments will pay the shipping costs of
returning to the owner parts which are covered by warranty.
National Instruments believes that the information in this document is accurate. The document has been carefully reviewed
for technical accuracy. In the event that technical or typographical errors exist, National Instruments reserves the right to
make changes to subsequent editions of this document without prior notice to holders of this edition. The reader should consult
National Instruments if errors are suspected. In no event shall National Instruments be liable for any damages arising out of
or related to this document or the information contained in it.
EXCEPT AS SPECIFIED HEREIN, NATIONAL INSTRUMENTS MAKES NO WARRANTIES, EXPRESS OR IMPLIED, AND SPECIFICALLY DISCLAIMS ANY
WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. CUSTOMER’S RIGHT TO RECOVER DAMAGES CAUSED BY FAULT OR
NEGLIGENCE ON THE PART OF NATIONAL INSTRUMENTS SHALL BE LIMITED TO THE AMOUNT THERETOFORE PAID BY THE CUSTOMER. NATIONAL
INSTRUMENTS WILL NOT BE LIABLE FOR DAMAGES RESULTING FROM LOSS OF DATA, PROFITS, USE OF PRODUCTS, OR INCIDENTAL OR
CONSEQUENTIAL DAMAGES, EVEN IF ADVISED OF THE POSSIBILITY THEREOF. This limitation of the liability of National Instruments will
apply regardless of the form of action, whether in contract or tort, including negligence. Any action against National Instruments
must be brought within one year after the cause of action accrues. National Instruments shall not be liable for any delay in
performance due to causes beyond its reasonable control. The warranty provided herein does not cover damages, defects,
malfunctions, or service failures caused by owner’s failure to follow the National Instruments installation, operation, or
maintenance instructions; owner’s modification of the product; owner’s abuse, misuse, or negligent acts; and power failure or
surges, fire, flood, accident, actions of third parties, or other events outside reasonable control.
Copyright
Under the copyright laws, this publication may not be reproduced or transmitted in any form, electronic or mechanical, including
photocopying, recording, storing in an information retrieval system, or translating, in whole or in part, without the prior written
consent of National Instruments Corporation.
Trademarks
CVI™, DAQ-STC™, LabVIEW™, Measurement Studio™, MITE™, National Instruments™, ni.com™ , NI-DAQ™, NI-PGIA™
PXI™, RTSI™, SCXI™, and VirtualBench™ are trademarks of National Instruments Corporation.
,
Product and company names mentioned herein are trademarks or trade names of their respective companies.
WARNING REGARDING USE OF NATIONAL INSTRUMENTS PRODUCTS
(1) NATIONAL INSTRUMENTS PRODUCTS ARE NOT DESIGNED WITH COMPONENTS AND TESTING FOR A LEVEL
OF RELIABILITY SUITABLE FOR USE IN OR IN CONNECTION WITH SURGICAL IMPLANTS OR AS CRITICAL
COMPONENTS IN ANY LIFE SUPPORT SYSTEMS WHOSE FAILURE TO PERFORM CAN REASONABLY BE
EXPECTED TO CAUSE SIGNIFICANT INJURY TO A HUMAN.
(2) IN ANY APPLICATION, INCLUDING THE ABOVE, RELIABILITY OF OPERATION OF THE SOFTWARE PRODUCTS
CAN BE IMPAIRED BY ADVERSE FACTORS, INCLUDING BUT NOT LIMITED TO FLUCTUATIONS IN ELECTRICAL
POWER SUPPLY, COMPUTER HARDWARE MALFUNCTIONS, COMPUTER OPERATING SYSTEM SOFTWARE
FITNESS, FITNESS OF COMPILERS AND DEVELOPMENT SOFTWARE USED TO DEVELOP AN APPLICATION,
INSTALLATION ERRORS, SOFTWARE AND HARDWARE COMPATIBILITY PROBLEMS, MALFUNCTIONS OR
FAILURES OF ELECTRONIC MONITORING OR CONTROL DEVICES, TRANSIENT FAILURES OF ELECTRONIC
SYSTEMS (HARDWARE AND/OR SOFTWARE), UNANTICIPATED USES OR MISUSES, OR ERRORS ON THE PART OF
THE USER OR APPLICATIONS DESIGNER (ADVERSE FACTORS SUCH AS THESE ARE HEREAFTER
COLLECTIVELY TERMED “SYSTEM FAILURES”). ANY APPLICATION WHERE A SYSTEM FAILURE WOULD
CREATE A RISK OF HARM TO PROPERTY OR PERSONS (INCLUDING THE RISK OF BODILY INJURY AND DEATH)
SHOULD NOT BE RELIANT SOLELY UPON ONE FORM OF ELECTRONIC SYSTEM DUE TO THE RISK OF SYSTEM
FAILURE. TO AVOID DAMAGE, INJURY, OR DEATH, THE USER OR APPLICATION DESIGNER MUST TAKE
REASONABLY PRUDENT STEPS TO PROTECT AGAINST SYSTEM FAILURES, INCLUDING BUT NOT LIMITED TO
BACK-UP OR SHUT DOWN MECHANISMS. BECAUSE EACH END-USER SYSTEM IS CUSTOMIZED AND DIFFERS
FROM NATIONAL INSTRUMENTS' TESTING PLATFORMS AND BECAUSE A USER OR APPLICATION DESIGNER
MAY USE NATIONAL INSTRUMENTS PRODUCTS IN COMBINATION WITH OTHER PRODUCTS IN A MANNER NOT
EVALUATED OR CONTEMPLATED BY NATIONAL INSTRUMENTS, THE USER OR APPLICATION DESIGNER IS
ULTIMATELY RESPONSIBLE FOR VERIFYING AND VALIDATING THE SUITABILITY OF NATIONAL
INSTRUMENTS PRODUCTS WHENEVER NATIONAL INSTRUMENTS PRODUCTS ARE INCORPORATED IN A
SYSTEM OR APPLICATION, INCLUDING, WITHOUT LIMITATION, THE APPROPRIATE DESIGN, PROCESS AND
SAFETY LEVEL OF SUCH SYSTEM OR APPLICATION.
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About This Manual
Chapter 1
Using PXI with CompactPCI.........................................................................................1-2
What You Need to Get Started ......................................................................................1-2
National Instruments Application Software....................................................1-3
NI-DAQ Driver Software................................................................................1-4
Optional Equipment.......................................................................................................1-5
Chapter 2
Installation and Configuration
Software Installation......................................................................................................2-1
Unpacking......................................................................................................................2-1
Chapter 3
Analog Output Glitch ......................................................................................3-6
Digital I/O......................................................................................................................3-7
Timing Signal Routing...................................................................................................3-7
Programmable Function Inputs .......................................................................3-8
Device and RTSI Clocks .................................................................................3-9
RTSI Triggers..................................................................................................3-9
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Contents
Chapter 4
Signal Connections
I/O Connector................................................................................................................ 4-1
Analog Input Signal Overview...................................................................................... 4-8
Floating Signal Sources.................................................................... 4-9
Ground-Referenced Signal Sources.................................................. 4-9
Analog Input Signal Connections.................................................................................. 4-11
Differential Connection Considerations (DIFF Input Configuration) ............ 4-13
Differential Connections for Ground-Referenced Signal Sources ... 4-14
Differential Connections for Nonreferenced or Floating Signal
Analog Output Signal Connections............................................................................... 4-19
TRIG1 Signal.................................................................................... 4-34
TRIG2 Signal.................................................................................... 4-35
STARTSCAN Signal........................................................................ 4-36
CONVERT* Signal .......................................................................... 4-38
AIGATE Signal ................................................................................ 4-39
SISOURCE Signal............................................................................ 4-40
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GPCTR1_SOURCE Signal...............................................................4-46
GPCTR1_GATE Signal....................................................................4-46
GPCTR1_UP_DOWN Signal...........................................................4-47
Field Wiring Considerations..........................................................................................4-49
Chapter 5
Calibration
Self-Calibration..............................................................................................................5-2
External Calibration.......................................................................................................5-2
Other Considerations .....................................................................................................5-3
Appendix A
Specifications
Appendix B
Custom Cabling and Optional Connectors
Appendix C
Common Questions
Appendix D
Technical Support Resources
Glossary
Index
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Contents
Figures
Block Diagram...................................................................................... 3-1
Figure 4-1.
Figure 4-2.
Figure 4-7.
I/O Connector Pin Assignment for the 6023E/6024E........................... 4-2
I/O Connector Pin Assignment for the 6025E ...................................... 4-3
Single-Ended Input Connections for Nonreferenced or
Floating Signals .................................................................................... 4-18
Figure 4-10. Digital I/O Connections ........................................................................ 4-21
Figure 4-11. Digital I/O Connections Block Diagram............................................... 4-22
Figure 4-16. Timing I/O Connections ....................................................................... 4-31
Figure 4-17. Typical Posttriggered Acquisition ........................................................ 4-32
Figure 4-18. Typical Pretriggered Acquisition.......................................................... 4-33
Figure 4-19. SCANCLK Signal Timing.................................................................... 4-33
Figure 4-20. EXTSTROBE* Signal Timing ............................................................. 4-34
Figure 4-21. TRIG1 Input Signal Timing.................................................................. 4-34
Figure 4-22. TRIG1 Output Signal Timing ............................................................... 4-35
Figure 4-23. TRIG2 Input Signal Timing.................................................................. 4-36
Figure 4-24. TRIG2 Output Signal Timing ............................................................... 4-36
Figure 4-25. STARTSCAN Input Signal Timing...................................................... 4-37
Figure 4-26. STARTSCAN Output Signal Timing ................................................... 4-37
Figure 4-27. CONVERT* Input Signal Timing ........................................................ 4-38
Figure 4-28. CONVERT* Output Signal Timing...................................................... 4-39
Figure 4-29. SISOURCE Signal Timing ................................................................... 4-40
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Figure 4-30. WFTRIG Input Signal Timing ..............................................................4-41
Figure 4-31. WFTRIG Output Signal Timing............................................................4-41
Figure 4-32. UPDATE* Input Signal Timing............................................................4-42
Figure 4-33. UPDATE* Output Signal Timing .........................................................4-42
Figure 4-34. UISOURCE Signal Timing...................................................................4-43
Figure 4-36. GPCTR0_GATE Signal Timing in Edge-Detection Mode...................4-45
Figure 4-37. GPCTR0_OUT Signal Timing..............................................................4-45
Figure 4-40. GPCTR1_OUT Signal Timing..............................................................4-47
Figure 4-41. GPCTR Timing Summary.....................................................................4-48
Figure B-4.
50-Pin Extended Digital Input Connector Pin Assignments.................B-6
Tables
Table 4-1.
Table 4-2.
Table 4-3.
Table 4-4.
Table 4-5.
I/O Connector Details............................................................................4-1
I/O Connector Signal Descriptions........................................................4-4
I/O Signal Summary..............................................................................4-7
Port C Signal Assignments....................................................................4-23
Signal Names Used in Timing Diagrams..............................................4-25
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About This Manual
The 6023, 6024, and 6025 E Series boards are high-performance
multifunction analog, digital, and timing I/O boards for PCI, PXI,
PCMCIA, and CompactPCI bus computers. Supported functions include
analog input, analog output, digital I/O, and timing I/O.
This manual describes the electrical and mechanical aspects of the
PCI-6023E, PCI-6024E, DAQCard-6024E, PCI-6025E, and PXI-6025E
boards from the E Series product line and contains information concerning
their operation and programming.
Conventions Used in This Manual
The following conventions are used in this manual:
<>
Angle brackets containing numbers separated by an ellipsis represent a
range of values associated with a bit or signal name—for example,
DBIO<3..0>.
♦
The ♦ symbol indicates that the text following it applies only to a specific
product, a specific operating system, or a specific software version.
This icon denotes a note, which alerts you to important information.
This icon denotes a caution, which advises you of precautions to take to
avoid injury, data loss, or a system crash.
bold
Bold text denotes items that you must select or click on in the software,
such as menu items and dialog box options. Bold text also denotes
parameter names.
CompactPCI
CompactPCI refers to the core specification defined by the PCI Industrial
Computer Manufacturer’s Group (PICMG).
italic
Italic text denotes variables, emphasis, a cross reference, or an introduction
to a key concept. This font also denotes text that is a placeholder for a word
or value that you must supply.
monospace
Monospace font denotes text or characters that you should enter from the
keyboard, sections of code, programming examples, and syntax examples.
This font is also used for the proper names of disk drives, paths, directories,
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About This Manual
programs, subprograms, subroutines, device names, functions, operations,
variables, filenames and extensions, and code excerpts.
NI-DAQ
PXI
NI-DAQ refers to the NI-DAQ driver software for PC compatible
computers unless otherwise noted.
PXI stands for PCI eXtensions for Instrumentation. PXI is an open
specification that builds off the CompactPCI specification by adding
instrumentation-specific features.
Related Documentation
The following documents contain information you may find helpful:
•
DAQ-STC Technical Reference Manual
•
National Instruments Application Note 025, Field Wiring and Noise
Considerations for Analog Signals
•
•
•
•
PCI Local Bus Specification Revision 2.2
PICMG CompactPCI 2.0 R2.1
PXI Specification Revision 2.0
PC Card (PCMCIA) 7.1 Standard
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1
Introduction
This chapter describes the 6023E, 6024E, and 6025E devices, lists what
you need to get started, gives unpacking instructions, and describes the
optional software and equipment.
Features of the 6023E, 6024E, and 6025E
The 6025E features 16 channels (eight differential) of analog input,
two channels of analog output, a 100-pin connector, and 32 lines of digital
I/O. The 6024E features 16 channels of analog input, two channels of
analog output, a 68-pin connector and eight lines of digital I/O. The 6023E
is identical to the 6024E, except that it does not have analog output
channels.
These devices use the National Instruments DAQ-STC system timing
controller for time-related functions. The DAQ-STC consists of three
timing groups that control analog input, analog output, and general-purpose
counter/timer functions. These groups include a total of seven 24-bit and
three 16-bit counters and a maximum timing resolution of 50 ns. The
DAQ-STC makes possible such applications as buffered pulse generation,
equivalent time sampling, and seamless changing of the sampling rate.
♦
PCI-6023E, PCI-6024E, PCI-6025E, and PXI-6025E only
With many DAQ devices, you cannot easily synchronize several
measurement functions to a common trigger or timing event. These devices
have the Real-Time System Integration (RTSI) bus to solve this problem. In
a PCI system, the RTSI bus consists of the National Instruments RTSI bus
interface and a ribbon cable to route timing and trigger signals between
several functions on as many as five DAQ devices in your computer. In a
PXI system, the RTSI bus consists of the National Instruments RTSI bus
interface and the PXI trigger signals on the PXI backplane to route timing
and trigger signals between several functions on as many as seven DAQ
devices in your system.
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These devices can interface to an SCXI system—the instrumentation front
end for plug-in DAQ devices—so that you can acquire analog signals from
thermocouples, RTDs, strain gauges, voltage sources, and current sources.
You can also acquire or generate digital signals for communication and
control.
Using PXI with CompactPCI
Using PXI compatible products with standard CompactPCI products is an
important feature provided by PXI Specification, Revision 1.0. If you use a
PXI compatible plug-in card in a standard CompactPCI chassis, you cannot
use PXI-specific functions, but you can still use the basic plug-in card
functions. For example, the RTSI bus on your PXI E Series device is
available in a PXI chassis, but not in a CompactPCI chassis.
The CompactPCI specification permits vendors to develop sub-buses that
coexist with the basic PCI interface on the CompactPCI bus. Compatible
operation is not guaranteed between CompactPCI devices with different
sub-buses nor between CompactPCI devices with sub-buses and PXI.
The standard implementation for CompactPCI does not include these
sub-buses. Your PXI E Series device works in any standard CompactPCI
chassis adhering to PICMG CompactPCI 2.0 R2.1 core specification.
PXI specific features are implemented on the J2 connector of the
CompactPCI bus. Table 3-3, Pins Used by PXI E Series Device, lists the J2
pins used by your PXI E Series device. Your PXI device is compatible with
any Compact PCI chassis with a sub-bus that does not drive these lines.
Even if the sub-bus is capable of driving these lines, the PXI device is still
compatible as long as those pins on the sub-bus are disabled by default and
not ever enabled. Damage can result if these lines are driven by the sub-bus.
What You Need to Get Started
To set up and use your device, you need the following:
❑ One of the following devices:
–
–
–
–
PCI-6023E
PCI-6024E
PXI-6025E
DAQCard-6024E
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❑ 6023E/6024E/6025E User Manual
❑ One of the following software packages and documentation:
–
–
–
LabVIEW for Windows
Measurement Studio
VirtualBench
❑ NI-DAQ for PC Compatibles
–
–
–
PCI bus for a PCI device
PXI or CompactPCI chassis and controller for a PXI device
Type II PCMCIA slot for a DAQCard device
Note Read Chapter 2, Installation and Configuration, before installing your device.
Always install your software before installing your device.
Software Programming Choices
When programming your National Instruments DAQ and SCXI hardware,
you can use National Instruments application software or another
application development environment (ADE). In either case, you use
NI-DAQ.
National Instruments Application Software
LabVIEW features interactive graphics, a state-of-the-art user interface,
and a powerful graphical programming language. The LabVIEW Data
Acquisition VI Library, a series of virtual instruments for using LabVIEW
with National Instruments DAQ hardware, is included with LabVIEW. The
LabVIEW Data Acquisition VI Library is functionally equivalent to
NI-DAQ software.
Measurement Studio, which includes LabWindows/CVI, tools for Visual
C++, and tools for Visual Basic, is a development suite that allows you to
use ANSI C, Visual C++, and Visual Basic to design your test and
measurement software. For C developers, Measurement Studio includes
LabWindows/CVI, a fully integrated ANSI C application development
environment that features interactive graphics and the LabWindows/CVI
Data Acquisition and Easy I/O libraries. For Visual Basic developers,
Measurement Studio features a set of ActiveX controls for using National
Instruments DAQ hardware. These ActiveX controls provide a high-level
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Chapter 1
Introduction
programming interface for building virtual instruments. For Visual C++
developers, Measurement Studio offers a set of Visual C++ classes and
tools to integrate those classes into Visual C++ applications. The libraries,
ActiveX controls, and classes are available with Measurement Studio and
the NI-DAQ software.
VirtualBench features virtual instruments that combine DAQ products,
software, and your computer to create a stand-alone instrument with the
added benefit of the processing, display, and storage capabilities of your
computer. VirtualBench instruments load and save waveform data to disk
in the same forms that can be used in popular spreadsheet programs and
word processors.
Using LabVIEW, Measurement Studio, or VirtualBench software greatly
reduces the development time for your data acquisition and control
application.
NI-DAQ Driver Software
The NI-DAQ driver software shipped with your 6023E/6024E/6025E is
compatible with you device. It has an extensive library of functions that
you can call from your application programming environment. These
functions allow you to use all features of your 6023E/6024E/6025E.
the DAQ hardware such as programming interrupts. NI-DAQ maintains a
consistent software interface among its different versions so that you can
change platforms with minimal modifications to your code. Whether you
are using LabVIEW, Measurement Studio, or other programming
languages, your application uses the NI-DAQ driver software, as illustrated
in Figure 1-1.
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Chapter 1
Introduction
LabVIEW,
Measurement Studio,
or VirtualBench
Conventional
Programming Environment
NI-DAQ
Driver Software
Personal
Computer or
Workstation
DAQ or
SCXI Hardware
Figure 1-1. The Relationship Between the Programming Environment,
NI-DAQ, and Your Hardware
To download a free copy of the most recent version of NI-DAQ, click
Download Software at ni.com.
Optional Equipment
National Instruments offers a variety of products to use with your device,
including cables, connector blocks, and other accessories, as follows:
•
•
•
•
Cables and cable assemblies, shielded and ribbon
Connector blocks, shielded and unshielded screw terminals
RTSI bus cables
SCXI modules and accessories for isolating, amplifying, exciting, and
multiplexing signals for relays and analog output. With SCXI you can
condition and acquire up to 3,072 channels.
•
Low channel count signal conditioning modules, devices, and
accessories, including conditioning for strain gauges and RTDs,
simultaneous sample and hold, and relays
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Chapter 1
Introduction
For more information about these products, refer to the National
Instruments catalogue or web site or call the office nearest you.
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2
Installation and Configuration
This chapter explains how to install and configure your 6023E, 6024E,
or 6025E device.
Software Installation
Install your software before installing your device.
If you are using LabVIEW, LabWindows/CVI, ComponentWorks, or
VirtualBench, install this software before installing the NI-DAQ driver
software. Refer to the software release notes of your software for
installation instructions.
If you are using NI-DAQ, refer to your NI-DAQ release notes. Find
the installation section for your operating system and follow the
instructions given there.
Unpacking
Your device is shipped in an antistatic package to prevent electrostatic
damage to the device. Electrostatic discharge can damage several
components on the device. To avoid such damage in handling the device,
take the following precautions:
•
•
•
Ground yourself by using a grounding strap or by holding a grounded
object.
Touch the antistatic package to a metal part of your computer chassis
before removing the device from the package.
Remove the device from the package and inspect the device for
loose components or any other sign of damage. Notify National
Instruments if the device appears damaged in any way. Do not install
a damaged device into your computer.
Never touch the exposed pins of connectors.
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Chapter 2
Installation and Configuration
Hardware Installation
After installing your software, you are ready to install your hardware. Your
device will fit in any available slot in your computer. However, to achieve
best noise performance, leave as much room as possible between your
device and other devices. The following are general installation
instructions. Consult your computer user manual or technical reference
manual for specific instructions and warnings.
♦
PCI device installation
1. Turn off and unplug your computer.
2. Remove the top cover of your computer.
3. Remove the expansion slot cover on the back panel of the computer.
4. Touch any metal part of your computer chassis to discharge any static
electricity that might be on your clothes or body.
5. Insert the device into a 5 V PCI slot. Gently rock the device to ease it
into place. It may be a tight fit, but do not force the device into place.
6. Screw the mounting bracket of the device to the back panel rail of the
computer.
7. Visually verify the installation.
8. Replace the top cover of your computer.
9. Plug in and turn on your computer.
♦
♦
PCMCIA card installation
Insert the DAQCard into any available Type II PCMCIA slot until the
connector is seated firmly. Insert the card face-up. It is keyed so that you
can only insert it one way.
PXI device installation
1. Turn off and unplug your computer.
2. Choose an unused PXI slot in your system. For maximum
performance, the device has an onboard DMA controller that you can
only use if the device is installed in a slot that supports bus arbitration,
or bus master cards. National Instruments recommends installing the
device in such a slot. The PXI specification requires all slots to support
bus master cards, but the CompactPCI specification does not. If you
install in a CompactPCI non-master slot, you must disable the onboard
DMA controller of the device using software.
3. Remove the filler panel for the slot you have chosen.
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Chapter 2
Installation and Configuration
4. Touch any metal part of your computer chassis to discharge any static
electricity that might be on your clothes or body.
5. Insert the device into a 5 V PXI slot. Use the injector/ejector handle to
fully insert the device into the chassis.
6. Screw the front panel of the device to the front panel mounting rail of
the system.
7. Visually verify the installation.
8. Plug in and turn on your computer.
The device is installed. You are now ready to configure your hardware and
software.
Hardware Configuration
National Instruments standard architecture for data acquisition and
standard bus specifications, makes these devices completely
software-configurable. You must perform two types of configuration on the
devices—bus-related and data acquisition-related configuration.
The PCI devices are fully compatible with the industry-standard PCI Local
Bus Specification Revision 2.2. The PXI device is fully compatible with the
automatically set the device base memory address and interrupt channel
without your interaction.
You can modify data acquisition-related configuration settings, such as
analog input range and mode, through application-level software. Refer to
Chapter 3, Hardware Overview, for more information about the various
settings available for your device. These settings are changed and
configured through software after you install your device. Refer to your
software documentation for configuration instructions.
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3
Hardware Overview
This chapter presents an overview of the hardware functions on your
device.
Figure 3-1 shows a block diagram for the PCI-6023E, PCI-6024E,
PCI-6025E, and PXI-6025E.
Voltage
REF
Calibration
EEPROM
DACs
(8)
(8)
Control
Analog
Input
Muxes
Generic
Bus
Interface
PCI
Bus
Interface
Analog Mode
Multiplexer
MINI-
MITE
ADC
FIFO
A/D
Converter
PGIA
Data
Address/Data
Calibration
Mux
Dither
Generator
Configuration
Memory
AI Control
EEPROM
IRQ
DMA
DMA/
Interrupt
Request
Trigger
Interface
Analog Input
Timing/Control
PFI / Trigger
Analog
Input
Control
EEPROM
DMA
Control Interface
Counter/
Timing I/O
Bus
Interface
DAQ-STC
Bus
Interface
Plug
DAQ - STC
Timing
and
DAQ - APE
Play
Analog Output
Timing/Control
Analog
Output
Control
82C55
Bus
RTSI Bus
Interface
Digital I/O
DIO
Interface
Digital I/O
Control
AO Control
DAC0
DAC1
Calibration DACs
RTSI Connector
Analog Output
(Not on 6023E)
DIO (24)
DIO Control
82C55A
(6025E Only)
Figure 3-1. PCI-6023E, PCI-6024E, PCI-6025E, and PXI-6025E Block Diagram
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Figure 3-2 shows the block diagram for the DAQCard-6024E.
Voltage
REF
Calibration
DACs
3
+
(8)
(8)
Analog
12-Bit
Mux Mode
NI-PGIA
Gain
Amplifier
Sampling
A/D
ADC
FIFO
Selection
Switches
Muxes
Converter
–
Calibration
Mux
Dither
Circuitry
EEPROM
Configuration
Memory
AI Control
IRQ
Interrupt
Request
Analog Input
Analog
Trigger
EEPROM
Control
PFI / Trigger
Timing
Input
Timing/Control
Control
Counter/
Timing I/O
Bus
Interface
DAQ - STC
DAQ-PCMCIA
Analog Output RTSI Bus
Timing/Control Interface
DAQ-STC Analog
Digital I/O
Bus
Interface
Bus
Output
Digital I/O (8)
Interface Control
DAC0
AO Control
DAC1
6
Calibration
DACs
Figure 3-2. DAQCard-6024E Block Diagram
Analog Input
The analog input section of each device is software configurable. The
following sections describe in detail each of the analog input settings.
Input Mode
(NRSE), referenced single-ended (RSE), and differential (DIFF) input. The
single-ended input configurations provide up to 16 channels. The DIFF
input configuration provides up to eight channels. Input modes are
programmed on a per channel basis for multimode scanning. For example,
you can configure the circuitry to scan 12 channels—four DIFF channels
and eight RSE channels. Table 3-1 describes the three input configurations.
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Table 3-1. Available Input Configurations
Configuration
Description
DIFF
A channel configured in DIFF mode uses two analog
input lines. One line connects to the positive input of
the programmable gain instrumentation amplifier
(PGIA) of the device, and the other connects to the
negative input of the PGIA.
RSE
A channel configured in RSE mode uses one analog
input line, which connects to the positive input of the
PGIA. The negative input of the PGIA is internally
tied to analog input ground (AIGND).
NRSE
analog input line, which connects to the positive
input of the PGIA. The negative input of the PGIA
connects to analog input sense (AISENSE).
For diagrams showing the signal paths of the three configurations, refer to
the Analog Input Signal Overview section in Chapter 4, Signal
Connections.
Input Range
The devices have a bipolar input range that changes with the programmed
gain. You can program each channel with a unique gain of 0.5, 1.0, 10, or
100 to maximize the 12-bit analog-to-digital converter (ADC) resolution.
With the proper gain setting, you can use the full resolution of the ADC to
measure the input signal. Table 3-2 shows the input range and precision
according to the gain used.
Table 3-2. Measurement Precision
Gain
0.5
Input Range
–10 to +10 V
–5 to +5 V
Precision1
4.88 mV
1.0
2.44 mV
10.0
100.0
–500 to +500 mV
–50 to +50 mV
244.14 µV
24.41 µV
1 The value of 1 LSB of the 12-bit ADC; that is, the voltage increment corresponding to a
change of one count in the ADC 12-bit count.
Note: See Appendix A, Specifications, for absolute maximum ratings.
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Dithering
When you enable dithering, you add approximately 0.5 LSBrms of white
Gaussian noise to the signal to be converted by the ADC. This addition is
useful for applications involving averaging to increase the resolution of
your device, as in calibration or spectral analysis. In such applications,
noise modulation is decreased and differential linearity is improved by the
addition of dithering. When taking DC measurements, such as when
checking the device calibration, enable dithering and average about
analysis, you may want to disable dithering to reduce noise. Your software
Figure 3-3a shows a small ( 4 LSB) sine wave acquired with dithering off.
The ADC quantization is clearly visible. Figure 3-3b shows what happens
when 50 such acquisitions are averaged together; quantization is still
plainly visible. In Figure 3-3c, the sine wave is acquired with dithering on.
There is a considerable amount of visible noise, but averaging about 50
such acquisitions, as shown in Figure 3-3d, eliminates both the added noise
and the effects of quantization. Dithering has the effect of forcing
quantization noise to become a zero-mean random variable rather than a
deterministic function of the input signal.
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LSBs
6.0
LSBs
6.0
4.0
2.0
4.0
2.0
0.0
0.0
-2.0
-2.0
-4.0
-6.0
-4.0
-6.0
0
100
200
300
400
500
0
100
200
300
400
500
a. Dither disabled; no averaging
b. Dither disabled; average of 50 acquisitions
LSBs
6.0
LSBs
6.0
4.0
2.0
4.0
2.0
0.0
0.0
-2.0
-2.0
-4.0
-6.0
-4.0
-6.0
0
100
200
300
400
500
0
100
200
300
400
500
c. Dither enabled; no averaging
d. Dither enabled; average of 50 acquisitions
Figure 3-3. Dithering
Multichannel Scanning Considerations
The devices can scan multiple channels at the same maximum rate as their
single-channel rate; however, pay careful attention to the settling times for
each of the devices. No extra settling time is necessary between channels
as long as the gain is constant and source impedances are low. Refer to
Appendix A, Specifications, for a complete listing of settling times for each
of the devices.
When scanning among channels at various gains, the settling times can
increase. When the PGIA switches to a higher gain, the signal on the
previous channel can be well outside the new, smaller range. For instance,
suppose a 4 V signal connects to channel 0 and a 1 mV signal connects to
channel 1, and suppose the PGIA is programmed to apply a gain of one to
channel 0 and a gain of 100 to channel 1. When the multiplexer switches to
channel 1 and the PGIA switches to a gain of 100, the new full-scale range
is 50 mV.
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The approximately 4 V step from 4 V to 1 mV is 4,000% of the new
full-scale range. It can take as long as 100 µs for the circuitry to settle to
1 LSB after such a large transition. In general, this extra settling time is not
needed when the PGIA is switching to a lower gain.
Settling times can also increase when scanning high-impedance signals
due to a phenomenon called charge injection, where the analog input
multiplexer injects a small amount of charge into each signal source when
that source is selected. If the impedance of the source is not low enough,
the effect of the charge—a voltage error—has not decayed by the time the
ADC samples the signal. For this reason, keep source impedances under
1 kΩ to perform high-speed scanning.
Due to the previously described limitations of settling times resulting from
these conditions, multiple-channel scanning is not recommended unless
sampling rates are low enough or it is necessary to sample several signals
as nearly simultaneously as possible. The data is much more accurate and
channel-to-channel independent if you acquire data from each channel
independently (for example, 100 points from channel 0, then 100 points
from channel 1, then 100 points from channel 2, and so on).
Analog Output
♦
6025E and 6024E only
These devices supply two channels of analog output voltage at the I/O
connector. The bipolar range is fixed at 10 V. Data written to the
digital-to-analog converter (DAC) is interpreted in two’s complement
format.
Analog Output Glitch
In normal operation, a DAC output glitches whenever it is updated with a
new value. The glitch energy differs from code to code and appears as
distortion in the frequency spectrum.
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Digital I/O
The devices contain eight lines of digital I/O (DIO<0..7>) for
general-purpose use. You can individually software-configure each line for
either input or output. At system startup and reset, the digital I/O ports are
all high impedance.
The hardware up/down control for general-purpose counters 0 and 1 are
connected onboard to DIO6 and DIO7, respectively. Thus, you can use
DIO6 and DIO7 to control the general-purpose counters. The up/down
control signals are input only and do not affect the operation of the DIO
lines.
♦
6025E only
The 6025E device uses an 82C55A programmable peripheral interface to
provide an additional 24 lines of digital I/O that represent three 8-bit
The 82C55A has three modes of operation—simple I/O (mode 0), strobed
I/O (mode 1), and bidirectional I/O (mode 2). In modes 1 and 2, the three
ports are divided into two groups—group A and group B. Each group has
eight data bits, plus control and status bits from Port C (PC). Modes 1 and
2 use handshaking signals from the computer to synchronize data transfers.
Refer to Chapter 4, Signal Connections, for more detailed information.
Timing Signal Routing
The DAQ-STC chip provides a flexible interface for connecting timing
signals to other devices or external circuitry. Your device uses the RTSI
bus to interconnect timing signals between devices (PCI and PXI buses
only), and the programmable function input (PFI) pins on the I/O connector
to connect the device to external circuitry. These connections are designed
circuits.
There are a total of 13 timing signals internal to the DAQ-STC that you can
control by an external source. You can also control these timing signals by
signals generated internally to the DAQ-STC, and these selections are fully
software-configurable. Figure 3-4 shows an example of the signal routing
multiplexer controlling the CONVERT* signal.
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†RTSI Trigger <0..6>
CONVERT*
PFI<0..9>
Sample Interval Counter TC
GPCTR0_OUT
†PCI and PXI Buses Only
Figure 3-4. CONVERT* Signal Routing
only) and PFI<0..9> and the internal signals Sample Interval Counter TC
and GPCTR0_OUT.
On PCI and PXI devices, many of these timing signals are also available as
outputs on the RTSI pins, as indicated in the RTSI Triggers section in this
chapter, and on the PFI pins, as indicated in Chapter 4, Signal Connections.
Programmable Function Inputs
Ten PFI pins are available on the device connector as PFI<0..9> and
connect to the internal signal routing multiplexer of the device for each
timing signal. Software can select any one of the PFI pins as the external
source for a given timing signal. It is important to note that you can use any
of the PFI pins as an input by any of the timing signals and that multiple
timing signals can use the same PFI simultaneously. This flexible routing
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scheme reduces the need to change physical connections to the I/O
connector for different applications.
You can also individually enable each of the PFI pins to output a specific
internal timing signal. For example, if you need the UPDATE* signal as an
output on the I/O connector, software can turn on the output driver for the
PFI5/UPDATE* pin.
Device and RTSI Clocks
♦
PCI and PXI buses
Many device functions require a frequency timebase to generate the
necessary timing signals for controlling A/D conversions, DAC updates,
or general-purpose signals at the I/O connector.
These devices can use either its internal 20 MHz timebase or a timebase
received over the RTSI bus. In addition, if you configure the device to use
the internal timebase, you can also program the device to drive its internal
timebase over the RTSI bus to another device that is programmed to receive
this timebase signal. This clock source, whether local or from the RTSI bus,
is used directly by the device as the primary frequency source. The default
configuration at startup is to use the internal timebase without driving the
RTSI bus timebase signal. This timebase is software selectable.
♦
♦
PXI-6025E
The RTSI clock connects to other devices through the PXI trigger bus on
the PXI backplane. The RTSI clock signal uses the PXI trigger <7> line for
this connection.
RTSI Triggers
PCI and PXI buses
The seven RTSI trigger lines on the RTSI bus provide a very flexible
interconnection scheme for any device sharing the RTSI bus. These
bidirectional lines can drive any of eight timing signals onto the RTSI bus
and can receive any of these timing signals. This signal connection scheme
is shown in Figure 3-5 for PCI devices and Figure 3-6 for PXI devices.
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DAQ-STC
TRIG1
TRIG2
CONVERT*
UPDATE*
WFTRIG
GPCTR0_SOURCE
GPCTR0_GATE
GPCTR0_OUT
STARTSCAN
AIGATE
Trigger
7
SISOURCE
UISOURCE
GPCTR1_SOURCE
GPCTR1_GATE
RTSI_OSC (20 MHz)
Clock
switch
Figure 3-5. PCI RTSI Bus Signal Connection
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DAQ-STC
TRIG1
TRIG2
CONVERT*
UPDATE*
WFTRIG
PXI Star (6)
GPCTR0_SOURCE
GPCTR0_GATE
GPCTR0_OUT
STARTSCAN
PXI Trigger (0..5)
AIGATE
SISOURCE
UISOURCE
GPCTR1_SOURCE
GPCTR1_GATE
RTSI_OSC (20 MHz)
PXI Trigger (7)
switch
Figure 3-6. PXI RTSI Bus Signal Connection
Table 3-3 lists the name and number of pins used by the PXI-6025E.
Table 3-3. Pins Used by PXI E Series Device
PXIE Series
Signal
RTSI<0..5>
RTSI 6
PXI Pin Name
PXI Trigger<0..5>
PXI Star
PXI J2 Pin Number
B16, A16, A17, A18, B18, C18
D17
RTSI Clock
Reserved
Reserved
PXI Trigger 7
E16
C20, E20, A19, C19
LBR<0..12>
A21, C21, D21, E21, A20,
B20, E15, A3, C3, D3, E3,
A2, B2
for a description of the signals shown in Figures 3-5 and 3-6.
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4
Signal Connections
This chapter describes how to make input and output signal connections to
your device through the I/O connector. Table 4-1 shows the cables that can
be used with the I/O connectors to connect to different accessories.
Table 4-1. I/O Connector Details
Cable for
Connecting
to 100-pin
Accessories
Cable for
Connecting
to 68-pin
Cable for
Connecting to
50-pin Signal
Accessories
Device with I/O
Connector
Numberof
Pins
Accessories
PCI-6023E,
PCI-6024E
68
N/A
SH6868Shielded SH6850Shielded
Cable,
Cable,
R6868 Ribbon
Cable
R6850 Ribbon
Cable
DAQCard-6024E
68
N/A
SHC68-68EP
68M-50F
Shielded Cable,
Adapter when
RC68-68 Ribbon used with the
Cable
SHC68-68EP or
RC68-68
6025E
100
SH100100
SH1006868
R1005050
Shielded Cable
Shielded Cable
Ribbon Cable
Caution Connections that exceed any of the maximum ratings of input or output signals
on the devices can damage the device and the computer. Maximum input ratings for each
for any damages resulting from such signal connections.
I/O Connector
Figure 4-1 shows the pin assignments for the 68-pin I/O connector on the
PCI-6023E, PCI-6024E, and DAQCard-6024E. Figure 4-2 shows the pin
assignments for the 100-pin I/O connector on the PCI-6025E. Refer to
Appendix B, Custom Cabling and Optional Connectors, for pin
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assignments of the optional 50- and 68-pin connectors. A signal description
follows the figures.
34 68
ACH1 33 67
ACH8
ACH0
AIGND
ACH9
32 66
31 65
30 64
29 63
28 62
AIGND
ACH10
ACH3
ACH2
AIGND
ACH11
AISENSE
ACH12
ACH5
AIGND
ACH4
AIGND 27 61
ACH13 26 60
ACH6
AIGND 24 58
25 59
AIGND
ACH14
ACH7
ACH15
23 57
22 56
21 55
DAC0OUT1
DAC1OUT1
AIGND
AOGND
AOGND
DGND
DIO0
RESERVED 20 54
19 53
18 52
17 51
16 50
15 49
DIO4
DGND
DIO1
DIO5
DIO6
DGND
DIO2
DGND
+5 V 14 48
DGND 13 47
DGND 12 46
DIO7
DIO3
SCANCLK
PFI0/TRIG1
11 45
10 44
EXTSTROBE*
DGND
PFI1/TRIG2
DGND
9
8
7
6
5
4
3
2
1
43
42
41
40
39
38
37
36
35
PFI2/CONVERT*
PFI3/GPCTR1_SOURCE
PFI4/GPCTR1_GATE
GPCTR1_OUT
DGND
+5 V
DGND
PFI5/UPDATE*
PFI6/WFTRIG
DGND
PFI7/STARTSCAN
PFI8/GPCTR0_SOURCE
DGND
PFI9/GPCTR0_GATE
GPCTR0_OUT
FREQ_OUT
DGND
1 Not available on the 6023E
Figure 4-1. I/O Connector Pin Assignment for the 6023E/6024E
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AIGND
AIGND
ACH0
1
2
3
51
PC7
GND
PC6
GND
PC5
GND
PC4
GND
PC3
GND
PC2
GND
PC1
GND
PC0
GND
PB7
GND
PB6
GND
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
ACH8
4
ACH1
5
ACH9
ACH2
6
7
ACH10
ACH3
ACH11
ACH4
ACH12
ACH5
ACH13
ACH6
8
9
10
11
12
13
14
15
16
17
18
19
20
ACH14
ACH7
ACH15
AISENSE
DAC0OUT
DAC1OUT
RESERVED
AOGND
DGND
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
PB5
GND
PB4
GND
PB3
GND
PB2
GND
PB1
GND
PB0
GND
PA7
DIO0
DIO4
DIO1
DIO5
DIO2
DIO6
DIO3
DIO7
DGND
+5 V
GND
PA6
+5 V
SCANCLK
EXTSTROBE*
PFI0/TRIG1
GND
PA5
GND
PFI1/TRIG2
PFI2/CONVERT*
PFI3/GPCTR1_SOURCE
PFI4/GPCTR1_GATE
GPCTR1_OUT
PFI5/UPDATE*
PFI6/WFTRIG
PFI7/STARTSCAN
PFI8/GPCTR0_SOURCE
PFI9/GPCTR0_GATE
GPCTR0_OUT
39
40
41
42
43
44
45
46
47
48
49
89
90
91
92
93
94
95
96
97
98
99
PA4
GND
PA3
GND
PA2
GND
PA1
GND
PA0
GND
+5 V
GND
FREQ_OUT
50 100
Figure 4-2. I/O Connector Pin Assignment for the 6025E
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Table 4-2 shows the I/O connector signal descriptions for the 6023E,
6024E, and 6025E.
Table 4-2. I/O Connector Signal Descriptions
Signal Name
Reference
Direction
Description
AIGND
—
—
Analog input ground—these pins are the reference point for
single-ended measurements in RSE configuration and the
bias current return point for DIFF measurements. All three
ground references—AIGND, AOGND, and DGND—are
connected on your device.
ACH<0..15>
AIGND
Input
Analog input channels 0 through 15—you can configure
each channel pair, ACH<i, i+8> (i = 0..7), as either one
DIFF input or two single-ended inputs.
AISENSE
DAC0OUT1
DAC1OUT1
AOGND
AIGND
AOGND
AOGND
—
Input
Output
Output
—
Analog input sense—this pin serves as the reference node
for any of channels ACH <0..15> in NRSE configuration.
Analog channel 0 output—this pin supplies the voltage
output of analog output channel 0.
Analog channel 1 output—this pin supplies the voltage
output of analog output channel 1.
Analog output ground—the analog output voltages are
referenced to this node. All three ground
references—AIGND, AOGND, and DGND—areconnected
together on your device.
DGND
—
—
Digital ground—this pin supplies the reference for the
digital signals at the I/O connector as well as the +5 VDC
supply. All three ground references—AIGND, AOGND,
and DGND—are connected on your device.
DIO<0..7>
PA<0..7>2
DGND
DGND
Input or
Output
Digital I/O signals—DIO6 and 7 can control the up/down
signal of general-purpose counters 0 and 1, respectively.
Input or
Output
Port A bidirectional digital data lines for the 82C55A
programmable peripheral interface on the 6025E. PA7
is the MSB. PA0 is the LSB.
PB<0..7>2
PC<0..7>2
+5 V
DGND
DGND
Input or
Output
Port B bidirectional digital data lines for the 82C55A
programmable peripheral interface on the 6025E. PB7
is the MSB. PB0 is the LSB.
Input or
Output
Port C bidirectional digital data lines for the 82C55A
programmable peripheral interface on the 6025E. PC7
is the MSB. PC0 is the LSB.
Output
+5 VDC Source—these pins are fused for up to 1 A of
+5 V supply on the PCI and PXI devices, or up to 0.75 A
from a DAQCard device. The fuse is self-resetting.
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Table 4-2. I/O Connector Signal Descriptions (Continued)
Signal Name
SCANCLK
Reference
Direction
Description
DGND
Output
scan clock—this pin pulses once for each A/D conversion
in scanning mode when enabled. The low-to-high edge
input or switched to another signal.
EXTSTROBE*
PFI0/TRIG1
DGND
DGND
Output
Input
External strobe—you can toggle this output under software
control to latch signals or trigger events on external devices.
PFI0/Trigger 1—as an input, this is one of the
programmable function inputs (PFIs). PFI signals are
explained in the Timing Connections section in this chapter.
As an output, this is the TRIG1 (AI start trigger) signal.
In posttrigger data acquisition sequences, a low-to-high
transition indicates the initiation of the acquisition
sequence. In pretrigger applications, a low-to-high
transition indicates the initiation of the pretrigger
conversions.
Output
PFI1/TRIG2
DGND
Input
PFI1/Trigger 2—as an input, this is one of the PFIs.
Output
As an output, this is the TRIG2 (AI stop trigger) signal. In
pretrigger applications, a low-to-high transition indicates
the initiation of the posttrigger conversions. TRIG2 is not
used in posttrigger applications.
PFI2/CONVERT*
DGND
DGND
DGND
DGND
Input
PFI2/Convert—as an input, this is one of the PFIs.
Output
As an output, this is the CONVERT* (AI convert) signal.
A high-to-low edge on CONVERT* indicates that an A/D
conversion is occurring.
PFI3/GPCTR1_SOURCE
PFI4/GPCTR1_GATE
GPCTR1_OUT
Input
PFI3/Counter 1 Source—as an input, this is one of the PFIs.
Output
As an output, this is the GPCTR1_SOURCE signal. This
signal reflects the actual source connected to the
general-purpose counter 1.
Input
PFI4/Counter 1 Gate—as an input, this is one of the PFIs.
Output
As an output, this is the GPCTR1_GATE signal. This signal
reflects the actual gate signal connected to the
general-purpose counter 1.
Output
Counter 1 Output—this output is from the general-purpose
counter 1 output.
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Table 4-2. I/O Connector Signal Descriptions (Continued)
Signal Name
Reference
Direction
Description
PFI5/UPDATE*
DGND
Input
PFI5/Update—as an input, this is one of the PFIs.
Output
As an output, this is the UPDATE* (AO Update) signal. A
high-to-low edge on UPDATE* indicates that the analog
output primary group is being updated for the 6024E or
6025E.
PFI6/WFTRIG
DGND
DGND
DGND
DGND
Input
PFI6/Waveform Trigger—as an input, this is one of the
PFIs.
Output
As an output, this is the WFTRIG (AO Start Trigger) signal.
In timed analog output sequences, a low-to-high transition
indicates the initiation of the waveform generation.
PFI7/STARTSCAN
PFI8/GPCTR0_SOURCE
PFI9/GPCTR0_GATE
Input
PFI7/Start of Scan—as an input, this is one of the PFIs.
Output
As an output, this is the STARTSCAN (AI Scan Start)
signal. This pin pulses once at the start of each analog input
scan in the interval scan. A low-to-high transition indicates
the start of the scan.
Input
PFI8/Counter 0 Source—as an input, this is one of the
PFIs.
Output
As an output, this is the GPCTR0_SOURCE signal.
This signal reflects the actual source connected to the
general-purpose counter 0.
Input
PFI9/Counter 0 Gate—as an input, this is one of the PFIs.
Output
As an output, this is the GPCTR0_GATE signal. This signal
reflects the actual gate signal connected to the
general-purpose counter 0.
GPCTR0_OUT
FREQ_OUT
DGND
DGND
Output
Output
Counter 0 Output—this output is from the general-purpose
counter 0 output.
Frequency Output—this output is from the frequency
generator output.
* Indicates that the signal is active low
1 Not available on the 6023E
2 Not available on the 6023E or 6024E
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Table 4-3 shows the I/O signal summary for the 6023E, 6024E, and 6025E.
Table 4-3. I/O Signal Summary
Signal
Type and
Direction
Impedance
Input/
Output
Protection
(Volts)
On/Off
Sink
(mA
at V)
Rise
Time
(ns)
Source
(mA at V)
Signal Name
Bias
ACH<0..15>
AI
100 GΩ
in
parallel
with
42/35
40/25
—
—
—
—
—
—
200 pA
100 pF
AISENSE
AIGND
AI
100 GΩ
in
parallel
with
—
—
200 pA
100 pF
AO
AO
—
—
—
—
—
DAC0OUT
(6024E and 6025E only)
0.1 Ω
Short-circuit
to ground
5 at 10
5 at -10
10
V/µs
DAC1OUT
(6024E and 6025E only)
AO
0.1 Ω
Short-circuit
to ground
5 at 10
5 at -10
10
V/µs
—
AOGND
DGND
VCC
AO
DO
DO
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.1 Ω
Short-circuit
to ground
1A fused
DIO<0..7>
DIO
DIO
DIO
DIO
—
—
—
—
V
V
V
V
+0.5
+0.5
+0.5
+0.5
13 at (V -0.4)
cc
24 at
0.4
1.1
5
50 kΩ pu
cc
cc
cc
cc
PA<0..7>
(6025E only)
2.5 at 3.7min
2.5 at 3.7min
2.5 at 3.7min
2.5 at
0.4
100 kΩ
pu
PB<0..7>
(6025E only)
2.5 at
0.4
5
100 kΩ
pu
PC<0..7>
(6025E only)
2.5 at
0.4
5
100 kΩ
pu
SCANCLK
DO
DO
—
—
—
—
—
—
—
3.5 at (V -0.4) 5 at 0.4
cc
1.5
1.5
1.5
1.5
1.5
1.5
50 kΩ pu
50 kΩ pu
50 kΩ pu
50 kΩ pu
50 kΩ pu
EXTSTROBE*
PFI0/TRIG1
—
3.5 at (V -0.4) 5 at 0.4
cc
DIO
DIO
DIO
DIO
V
V
V
V
+0.5
3.5 at (V -0.4) 5 at 0.4
cc
cc
cc
cc
cc
PFI1/TRIG2
+0.5
+0.5
+0.5
3.5 at (V -0.4) 5 at 0.4
cc
PFI2/CONVERT*
PFI3/GPCTR1_SOURCE
3.5 at (V -0.4) 5 at 0.4
cc
3.5 at (V -0.4) 5 at 0.4
cc
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Chapter 4
Signal Connections
Table 4-3. I/O Signal Summary (Continued)
Signal
Type and
Direction
Impedance
Input/
Output
Protection
(Volts)
On/Off
Sink
(mA
at V)
Rise
Time
(ns)
Source
(mA at V)
Signal Name
Bias
PFI4/GPCTR1_GATE
GPCTR1_OUT
DIO
DO
—
—
—
—
—
—
—
—
—
V
+0.5
3.5 at (V -0.4) 5 at 0.4
cc
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
50 kΩ pu
50 kΩ pu
50 kΩ pu
50 kΩ pu
50 kΩ pu
50 kΩ pu
50 kΩ pu
50 kΩ pu
50 kΩ pu
cc
—
3.5 at (V -0.4) 5 at 0.4
cc
PFI5/UPDATE*
DIO
DIO
DIO
DIO
DIO
DO
V
cc
V
cc
V
cc
V
cc
V
cc
+0.5
+0.5
+0.5
+0.5
+0.5
3.5 at (V -0.4) 5 at 0.4
cc
PFI6/WFTRIG
3.5 at (V -0.4) 5 at 0.4
cc
PFI7/STARTSCAN
PFI8/GPCTR0_SOURCE
PFI9/GPCTR0_GATE
GPCTR0_OUT
3.5 at (V -0.4) 5 at 0.4
cc
3.5 at (V -0.4) 5 at 0.4
cc
3.5 at (V -0.4) 5 at 0.4
cc
—
3.5 at (V -0.4) 5 at 0.4
cc
FREQ_OUT
DO
—
3.5 at (V -0.4)
cc
5 at 0.4
AI = Analog Input
AO = Analog Output
DIO = Digital Input/Output
DO = Digital Output
pu = pullup
Note: The tolerance on the 50 kΩ pullup and pulldown resistors is very large. Actual value can range between 17 kΩ and
100 kΩ.
Analog Input Signal Overview
The analog input signals for these devices are ACH<0..15>, ASENSE, and
AIGND. Connection of these analog input signals to your device depends
on the type of input signal source and the configuration of the analog input
channels you are using. This section provides an overview of the different
types of signal sources and analog input configuration modes. More
specific signal connection information is provided in the Analog Input
Signal Connections section.
Types of Signal Sources
When configuring the input channels and making signal connections,
you must first determine whether the signal sources are floating or
ground-referenced.
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Floating Signal Sources
A floating signal source is not connected in any way to the building ground
system, but has an isolated ground-reference point. Some examples of
floating signal sources are outputs of transformers, thermocouples,
battery-powered devices, optical isolators, and isolation amplifiers. An
instrument or device that has an isolated output is a floating signal source.
You must tie the ground reference of a floating signal to the analog input
ground of your device to establish a local or onboard reference for the
signal. Otherwise, the measured input signal varies as the source floats out
of the common-mode input range.
Ground-Referenced Signal Sources
A ground-referenced signal source is connected in some way to the
building system ground and is, therefore, already connected to a common
ground point with respect to the device, assuming that the computer is
plugged into the same power system. Non-isolated outputs of instruments
and devices that plug into the building power system fall into this category.
The difference in ground potential between two instruments connected to
the same building power system is typically between 1 and 100 mV, but can
be much higher if power distribution circuits are not properly connected.
If a grounded signal source is improperly measured, this difference can
appear as an error in the measurement. The connection instructions for
grounded signal sources are designed to eliminate this ground potential
difference from the measured signal.
Analog Input Modes
You can configure your device for one of three input
modes—nonreferenced single ended (NRSE), referenced single ended
(RSE), and differential (DIFF). With the different configurations, you can
use the PGIA in different ways. Figure 4-3 shows a diagram of the PGIA
of your device.
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Programmable
Gain
Instrumentation
Amplifier
Vin+
+
+
PGIA
Vm
Measured
Voltage
Vin-
-
-
Vm = [Vin+ - Vin-]* Gain
Figure 4-3. Programmable Gain Instrumentation Amplifier (PGIA)
In single-ended mode (RSE and NRSE), signals connected to ACH<0..15>
are routed to the positive input of the PGIA. In DIFF mode, signals
connected to ACH<0..7> are routed to the positive input of the PGIA, and
signals connected to ACH<8..15> are routed to the negative input of the
PGIA.
Caution Exceeding the DIFF and common-mode input ranges distorts your input signals.
Exceeding the maximum input voltage rating can damage the device and the computer.
National Instruments is not liable for any damages resulting from such signal connections.
The maximum input voltage ratings are listed in the Protection column of Table 4-3.
In NRSE mode, the AISENSE signal connects internally to the negative
input of the PGIA when their corresponding channels are selected. In DIFF
and RSE modes, AISENSE is left unconnected.
AIGND is an analog input common signal that routes directly to the ground
connection point on the devices. You can use this signal for a general analog
ground connection point to your device if necessary.
The PGIA applies gain and common-mode voltage rejection and presents
high input impedance to the analog input signals connected to your device.
Signals are routed to the positive and negative inputs of the PGIA through
input multiplexers on the device. The PGIA converts two input signals to a
signal that is the difference between the two input signals multiplied by the
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Chapter 4
Signal Connections
gain setting of the amplifier. The amplifier output voltage is referenced to
measures this output voltage when it performs A/D conversions.
Reference all signals to ground either at the source device or at the device.
If you have a floating source, reference the signal to ground by using the
RSE input mode or the DIFF input configuration with bias resistors (see the
Differential Connections for Nonreferenced or Floating Signal Sources
section). If you have a grounded source, do not reference the signal to
AIGND. You can avoid this reference by using DIFF or NRSE input
configurations.
Analog Input Signal Connections
The following sections discuss the use of single-ended and DIFF
measurements and recommendations for measuring both floating and
ground-referenced signal sources.
Figure 4-4 summarizes the recommended input configuration for both
types of signal sources.
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Chapter 4
Signal Connections
Signal Source Type
Grounded Signal Source
Floating Signal Source
(Not Connected to Building Ground)
Examples
Examples
• Plug-in instruments with
nonisolated outputs
• Ungrounded Thermocouples
• Signal conditioning with isolated outputs
• Battery devices
Input
ACH(+)
+
ACH(+)
+
+
-
V1
+
-
V1
ACH (-)
ACH (-)
-
-
R
Differential
(DIFF)
AIGND
AIGND
See text for information on bias resistors.
NOT RECOMMENDED
ACH
ACH
Single-Ended —
Ground
Referenced
(RSE)
+
+
+
+
V1
V1
AIGND
-
-
-
-
+
Vg
-
Ground-loop losses, Vg, are added to
measured signal
ACH
ACH
+
+
+
Single-Ended —
Nonreferenced
(NRSE)
+
V1
V1
AISENSE
AISENSE
R
-
-
-
-
AIGND
AIGND
See text for information on bias resistors.
Figure 4-4. Summary of Analog Input Connections
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Chapter 4
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Differential Connection Considerations (DIFF Input Configuration)
A DIFF connection is one in which the analog input signal has its own
reference signal or signal return path. These connections are available
when the selected channel is configured in DIFF input mode. The input
signal is connected to the positive input of the PGIA, and its reference
signal, or return, is connected to the negative input of the PGIA.
When you configure a channel for DIFF input, each signal uses two
multiplexer inputs—one for the signal and one for its reference signal.
Therefore, with a DIFF configuration for every channel, up to eight analog
input channels are available.
Use DIFF input connections for any channel that meets any of the following
conditions:
•
•
The input signal is low level (less than 1 V).
The leads connecting the signal to the device are greater than
3 m (10 ft).
•
•
The input signal requires a separate ground-reference point or return
signal.
The signal leads travel through noisy environments.
DIFF signal connections reduce picked up noise and increase
common-mode noise rejection. DIFF signal connections also allow input
signals to float within the common-mode limits of the PGIA.
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Signal Connections
Differential Connections for Ground-Referenced
Signal Sources
Figure 4-5 shows how to connect a ground-referenced signal source to a
channel on the device configured in DIFF input mode.
ACH+
Ground-
Referenced
Signal
Source
+
Programmable Gain
Instrumentation
V
s
Amplifier
+
–
PGIA
+
ACH–
Measured
Voltage
–
Vm
Common-
Mode
Noise and
Ground
–
+
V
cm
–
Potential
Input Multiplexers
AISENSE
AIGND
I/O Connector
Selected Channel in DIFF Configuration
Figure 4-5. Differential Input Connections for Ground-Referenced Signals
With this type of connection, the PGIA rejects both the common-mode
noise in the signal and the ground potential difference between the signal
source and the device ground, shown as Vcm in Figure 4-5.
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Chapter 4
Signal Connections
Differential Connections for Nonreferenced or
Floating Signal Sources
Figure 4-6 shows how to connect a floating signal source to a channel
configured in DIFF input mode.
ACH+
Bias
resistors
(see text)
Programmable Gain
Instrumentation
+
Floating
Signal
Source
V
s
Amplifier
+
–
PGIA
+
ACH–
Measured
Voltage
–
Vm
–
Bias
Current
Return
Paths
Input Multiplexers
AISENSE
AIGND
I/O Connector
Selected Channel in DIFF Configuration
Figure 4-6. Differential Input Connections for Nonreferenced Signals
Figure 4-6 shows two bias resistors connected in parallel with the signal
leads of a floating signal source. If you do not use the resistors and the
source is truly floating, the source is not likely to remain within the
common-mode signal range of the PGIA. The PGIA then saturates, causing
erroneous readings.
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You must reference the source to AIGND. The easiest way is to connect the
positive side of the signal to the positive input of the PGIA and connect the
negative side of the signal to AIGND as well as to the negative input of the
PGIA, without any resistors at all. This connection works well for
DC-coupled sources with low source impedance (less than 100 Ω).
However, for larger source impedances, this connection leaves the DIFF
signal path significantly out of balance. Noise that couples electrostatically
onto the positive line does not couple onto the negative line because it is
connected to ground. Hence, this noise appears as a DIFF-mode signal
instead of a common-mode signal, and the PGIA does not reject it. In this
case, instead of directly connecting the negative line to AIGND, connect it
to AIGND through a resistor that is about 100 times the equivalent source
impedance. The resistor puts the signal path nearly in balance, so that about
the same amount of noise couples onto both connections, yielding better
rejection of electrostatically coupled noise. Also, this configuration does
not load down the source (other than the very high input impedance of the
PGIA).
You can fully balance the signal path by connecting another resistor of the
same value between the positive input and AIGND, as shown in Figure 4-6.
This fully balanced configuration offers slightly better noise rejection but
has the disadvantage of loading the source down with the series
combination (sum) of the two resistors. If, for example, the source
impedance is 2 kΩ and each of the two resistors is 100 kΩ, the resistors
load down the source with 200 kΩ and produce a –1% gain error.
Both inputs of the PGIA require a DC path to ground in order for the PGIA
to work. If the source is AC coupled (capacitively coupled), the PGIA needs
a resistor between the positive input and AIGND. If the source has low
impedance, choose a resistor that is large enough not to significantly load
the source but small enough not to produce significant input offset voltage
as a result of input bias current (typically 100 kΩ to 1 MΩ). In this case,
you can tie the negative input directly to AIGND. If the source has high
output impedance, balance the signal path as previously described using the
same value resistor on both the positive and negative inputs; be aware that
there is some gain error from loading down the source.
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Single-Ended Connection Considerations
A single-ended connection is one in which the device analog input signal is
referenced to a ground that it can share with other input signals. The input
signal is tied to the positive input of the PGIA, and the ground is tied to the
negative input of the PGIA.
When every channel is configured for single-ended input, up to 16 analog
input channels are available.
You can use single-ended input connections for any input signal that meets
the following conditions:
•
•
•
The input signal is high level (greater than 1 V).
The leads connecting the signal to the device are less than 10 ft (3 m).
The input signal can share a common reference point with other
signals.
DIFF input connections are recommended for greater signal integrity for
any input signal that does not meet the preceding conditions.
Using your software, you can configure the channels for two different types
of single-ended connections—RSE configuration and NRSE configuration.
The RSE configuration is used for floating signal sources; in this case, the
device provides the reference ground point for the external signal. The
NRSE input configuration is used for ground-referenced signal sources; in
this case, the external signal supplies its own reference ground point and the
device should not supply one.
In single-ended configurations, more electrostatic and magnetic noise
couples into the signal connections than in DIFF configurations. The
coupling is the result of differences in the signal path. Magnetic coupling
is proportional to the area between the two signal conductors. Electrical
coupling is a function of how much the electric field differs between the
two conductors.
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Signal Connections
Single-Ended Connections for Floating Signal
Sources (RSE Configuration)
Figure 4-7 shows how to connect a floating signal source to a channel
configured for RSE mode.
ACH
Programmable Gain
Instrumentation Amplifier
+
Floating
+
Signal
V
s
Source
PGIA
–
+
Input Multiplexers
AISENSE
Measured
Voltage
–
V
m
–
AIGND
I/O Connector
Selected Channel in RSE Configuration
Figure 4-7. Single-Ended Input Connections for Nonreferenced or Floating Signals
Single-Ended Connections for Grounded Signal
Sources (NRSE Configuration)
To measure a grounded signal source with a single-ended configuration,
you must configure your device in the NRSE input configuration. Connect
the signal to the positive input of the PGIA, and connect the signal local
ground reference to the negative input of the PGIA. The ground point of the
signal, therefore, connects to the AISENSE pin. Any potential difference
between the device ground and the signal ground appears as a
common-mode signal at both the positive and negative inputs of the PGIA,
and this difference is rejected by the amplifier. If the input circuitry of a
device were referenced to ground, in this situation as in the RSE input
configuration, this difference in ground potentials appears as an error in the
measured voltage.
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Figure 4-8 shows how to connect a grounded signal source to a channel
configured for NRSE mode.
ACH<0..15>
Instrumentation
+
Ground-
Referenced
Signal
Amplifier
+
Vs
Source
PGIA
–
+
Input Multiplexers
Measured
Voltage
Vm
–
+
AISENSE
AIGND
Common-
Mode
Noise
–
Vcm
and Ground
Potential
–
Selected Channel in NRSE Configuration
I/O Connector
Figure 4-8. Single-Ended Input Connections for Ground-Referenced Signals
Common-Mode Signal Rejection Considerations
Figures 4-5 and 4-8 show connections for signal sources that are already
referenced to some ground point with respect to the device. In these cases,
the PGIA can reject any voltage caused by ground potential differences
between the signal source and the device. In addition, with DIFF input
connections, the PGIA can reject common-mode noise pickup in the leads
connecting the signal sources to the device. The PGIA can reject
common-mode signals as long as V+in and V–in (input signals) are both
within 11 V of AIGND.
Analog Output Signal Connections
♦
6024E and 6025E
The analog output signals are DAC0OUT, DAC1OUT, and AOGND.
DAC0OUT and DAC1OUT are not available on the 6023E. DAC0OUT is
the voltage output signal for analog output channel 0. DAC1OUT is the
voltage output signal for analog output channel 1.
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AOGND is the ground reference signal for both analog output channels and
the external reference signal. Figure 4-9 shows how to make analog output
connections to your device.
DAC0OUT
Channel 0
+
VOUT 0
Load
Load
–
AOGND
–
VOUT 1
DAC1OUT
+
Channel 1
Analog Output Channels
I/O Connector
Figure 4-9. Analog Output Connections
Digital I/O Signal Connections
All Devices
All devices have digital I/O signals DIO<0..7> and DGND. DIO<0..7> are
the signals making up the DIO port, and DGND is the ground-reference
signal for the DIO port. You can program all lines individually as inputs or
outputs. Figure 4-10 shows signal connections for three typical digital I/O
applications.
Caution Exceeding the maximum input voltage ratings, which are listed in Table 4-2, can
damage the DAQ device and the computer. National Instruments is not liable for any
damages resulting from such signal connections.
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Chapter 4
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+5 V
LED
DIO<4..7>
DIO<0..3>
TTL Signal
+5 V
Switch
DGND
I/O Connector
Figure 4-10. Digital I/O Connections
Figure 4-10 shows DIO<0..3> configured for digital input and DIO<4..7>
configured for digital output. Digital input applications include receiving
TTL signals and sensing external device states such as the state of the
switch shown in the Figure 4-11. Digital output applications include
sending TTL signals and driving external devices such as the LED shown
in Figure 4-11. Figure 4-11 depicts signal connections for three typical
digital I/O applications.
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Signal Connections
+5 V
LED
Port A
PA<3..0>
Port B
TTL Signal
PB<7..4>
+5 V
Switch
GND
I/O Connector
DIO Device
Figure 4-11. Digital I/O Connections Block Diagram
Programmable Peripheral Interface (PPI)
♦
6025E only
The 6025E device uses an 82C55A PPI to provide an additional 24 lines
program each port as an input or output port.
In Figure 4-11, port A of one PPI is configured for digital output, and
port B is configured for digital input. Digital input applications include
receiving TTL signals and sensing external device states such as the state
of the switch in Figure 4-11. Digital output applications include sending
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Chapter 4
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TTL signals and driving external devices such as the LED shown in
Figure 4-11.
Port C Pin Assignments
♦
6025 only
The signals assigned to port C depend on how the 82C55A is configured.
In mode 0, or no handshaking configuration, port C is configured as two
is used for status and handshaking signals with any leftover lines available
for general-purpose I/O. Table 4-4 summarizes the port C signal
assignments for each configuration. You can also use ports A and B in
different modes; the table does not show every possible combination.
Note Table 4-4 shows both the port C signal assignments and the terminology
correlation between different documentation sources. The 82C55A terminology refers
to the different 82C55A configurations as modes, whereas NI-DAQ, ComponentWorks,
LabWindows/CVI, and LabVIEW documentation refers to them as handshaking and no
handshaking.
Table 4-4. Port C Signal Assignments
Configuration Terminology
Signal Assignments
6023E/
6024E/6025E
User Manual
National
Instruments
Software
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Mode 0
No
(Basic I/O)
Handshaking
I/O
I/O
IBFA
I/O
STBA*
I/O
INTRA
INTRA
INTRA
STBB*
ACKB*
I/O
IBFBB
OBFB*
I/O
INTRB
INTRB
I/O
Mode 1
(Strobed Input)
Handshaking
OBFA*
OBFA*
ACKA*
ACKA*
Mode 1
(Strobed Output)
Handshaking
Handshaking
IBFA
STBA*
Mode 2
(Bidirectional
Bus)
* Indicates that the signal is active low.
Subscripts A and B denote port A or port B handshaking signals.
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Power-up State
♦
6025E only
The 6025E contains bias resistors that control the state of the digital I/O
lines PA<0..7>,PB<0..7>,PC<0..7> at power up. Each digital I/O line is
configured as an input, pulled high by a 100 kΩ bias resistor.
You can change individual lines from pulled up to pulled down by adding
your own external resistors. This section describes the procedure.
Changing DIO Power-up State to Pulled Low
Each DIO line is pulled to Vcc (approximately +5 VDC) with a 100 kΩ
resistor. To pull a specific line low, connect between that line and ground
a pull-down resistor (RL) whose value gives you a maximum of 0.4 VDC.
The DIO lines provide a maximum of 2.5 mA at 3.7 V in the high state.
than necessary to perform the pull-down task.
However, make sure the value of the resistor is not so large that leakage
current from the DIO line along with the current from the 100 kΩ pull-up
resistor drives the voltage at the resistor above a TTL-low level of 0.4 VDC.
Figure 4-12 shows the DIO configuration for high DIO power-up state.
Device
+5 V
100 k
82C55
Digital I/O Line
RL
GND
Figure 4-12. DIO Channel Configured for High DIO Power-up State with External Load
Example
A given DIO line is pulled high at power up. To pull it low on power up with
an external resistor, follow these steps:
greater the current consumption and the lower the voltage.
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2. Using the following formula, calculate the largest possible load to
maintain a logic low level of 0.4 V and supply the maximum driving
current:
V = I × RL ⇒ RL = V/I
where:
V = 0.4 V
Voltage across RL
I = 46 µA + 10 µA 4.6 V across the 100 kΩ pull-up resistor
and 10 µA maximum leakage current
Therefore:
RL = 7.1 kΩ
; 0.4 V/56 µA
This resistor value, 7.1 kΩ, provides a maximum of 0.4 V on the DIO line
at power up. You can substitute smaller resistor values to lower the voltage
or to provide a margin for Vcc variations and other factors. However,
smaller values draw more current, leaving less drive current for other
circuitry connected to this line. The 7.1 kΩ resistor reduces the amount of
logic high source current by 0.4 mA with a 2.8 V output.
Timing Specifications
♦
6025E only
This section lists the timing specifications for handshaking with your
6025E PC<0..7> lines. The handshaking lines STB* and IBF synchronize
input transfers. The handshaking lines OBF* and ACK* synchronize
output transfers. Table 4-5 describes signals appearing in the handshaking
diagrams.
Table 4-5. Signal Names Used in Timing Diagrams
Name
STB*
Type
Description
Input
Strobe input—a low signal on this handshaking line loads data into
the input latch.
IBF
Output
Input buffer full—a high signal on this handshaking line indicates
that data has been loaded into the input latch. A low signal indicates
the device is ready for more data. This is an input acknowledge
signal.
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Table 4-5. Signal Names Used in Timing Diagrams (Continued)
Name
Type
Input
Description
ACK*
Acknowledge input—a low signal on this handshaking line
indicates that the data written to the port has been accepted. This
signal is a response from the external device indicating that it has
received the data from your DIO device.
OBF*
INTR
Output
Output
Output buffer full—a low signal on this handshaking line indicates
that data has been written to the port.
Interrupt request—this signal becomes high when the 82C55A
requests service during a data transfer. You must set the appropriate
interrupt enable bits to generate this signal.
RD*
Internal
Read—this signal is the read signal generated from the control lines
of the computer I/O expansion bus.
WR*
DATA
Internal
Write—this signal is the write signal generated from the control
lines of the computer I/O expansion bus.
Bidirectional
Data lines at the specified port—for output mode, this signal
indicates the availability of data on the data line. For input mode,
this signal indicates when the data on the data lines should be valid.
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Mode 1 Input Timing
Timing specifications for an input transfer in mode 1 are shown in
Figure 4-13.
T1
T2
T4
STB *
IBF
T7
T6
INTR
RD *
T3
T5
DATA
Name
T1
Description
Minimum
Maximum
—
100
—
20
—
50
—
—
STB* Pulse Width
T2
150
STB* = 0 to IBF = 1
Data before STB* = 1
STB* = 1 to INTR = 1
Data after STB* = 1
RD* = 0 to INTR = 0
RD* = 1 to IBF = 0
T3
—
T4
150
T5
—
T6
200
T7
150
All timing values are in nanoseconds.
Figure 4-13. Timing Specifications for Mode 1 Input Transfer
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Mode 1 Output Timing
Timing specifications for an output transfer in mode 1 are shown in
Figure 4-14.
T3
WR*
T4
OBF*
T1
T6
INTR
ACK*
DATA
T5
T2
Name
T1
Description
WR* = 0 to INTR = 0
Minimum
Maximum
250
—
—
T2
200
WR* = 1 to Output
T3
—
150
WR* = 1 to OBF* = 0
ACK* = 0 to OBF* = 1
ACK* Pulse Width
T4
—
150
T5
100
—
—
T6
150
ACK* = 1 to INTR = 1
All timing values are in nanoseconds.
Figure 4-14. Timing Specifications for Mode 1 Output Transfer
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Mode 2 Bidirectional Timing
Timing specifications for a bidirectional transfer in mode 2 are shown in
Figure 4-15.
T1
WR *
T6
OBF *
INTR
T7
ACK *
T3
STB *
T10
T4
IBF
RD *
T5
T9
T2
T8
DATA
Name
T1
Description
Minimum
Maximum
150
—
—
20
WR* = 1 to OBF* = 0
T2
Data before STB* = 1
STB* Pulse Width
T3
100
—
—
T4
150
—
STB* = 0 to IBF = 1
Data after STB* = 1
ACK* = 0 to OBF* = 1
ACK* Pulse Width
ACK* = 0 to Output
ACK* = 1 to Output Float
RD* = 1 to IBF = 0
T5
50
T6
—
150
—
T7
100
—
T8
150
250
T9
20
T10
—
All timing values are in nanoseconds.
Figure 4-15. Timing Specifications for Mode 2 Bidirectional Transfer
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Power Connections
Two pins on the I/0 connector supply +5 V from the computer power
supply through a self-resetting fuse. The fuse resets automatically within a
few seconds after the overcurrent condition is removed. These pins are
referenced to DGND and you can use them to power external digital
circuitry. The power rating is +4.65 to +5.25 VDC at 1 A for the PCI and
PXI devices, and +4.65 to +5.25 VDC at 0.75A for PCMCIA cards.
Caution Under no circumstances connect these +5 V power pins directly to analog or
digital grounds, or to any other voltage source on the device or any other device. Doing so
can damage the device and the computer. National Instruments is not liable for damages
resulting from such a connection.
Timing Connections
damage the device and the computer. National Instruments is not liable for any damages
resulting from such signal connections.
All external control over the timing of your device is routed through the
10 programmable function inputs labeled PFI<0..9>. These signals are
explained in detail in the Programmable Function Input Connections
section. These PFIs are bidirectional; as outputs they are not programmable
and reflect the state of many DAQ, waveform generation, and
general-purpose timing signals. There are five other dedicated outputs for
the remainder of the timing signals. As inputs, the PFI signals are
general-purpose timing signals.
the waveform generation signals in the Waveform Generation Timing
Connections section, and the general-purpose timing signals in the
General-Purpose Timing Signal Connections section.
All digital timing connections are referenced to DGND. This reference
is demonstrated in Figure 4-16, which shows how to connect an external
TRIG1 source and an external CONVERT* source to two PFI pins.
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PFI0/TRIG1
PFI2/CONVERT*
TRIG1
Source
CONVERT*
Source
DGND
I/O Connector
Figure 4-16. Timing I/O Connections
Programmable Function Input Connections
There are a total of 13 internal timing signals that you can externally
control from the PFI pins. The source for each of these signals is
software-selectable from any of the PFIs when you want external control.
This flexible routing scheme reduces the need to change the physical
wiring to the device I/O connector for different applications requiring
alternative wiring.
You can individually enable each of the PFI pins to output a specific
internal timing signal. For example, if you need the CONVERT* signal as
an output on the I/O connector, software can turn on the output driver for
the PFI2/CONVERT* pin. Be careful not to drive a PFI signal externally
when it is configured as an output.
As an input, you can individually configure each PFI pin for edge or level
detection and for polarity selection, as well. You can use the polarity
selection for any of the 13 timing signals, but the edge or level detection
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depends upon the particular timing signal you are controlling. The
detection requirements for each timing signal are listed within the section
that discusses that individual signal.
In edge-detection mode, the minimum pulse width required is 10 ns. This
applies for both rising-edge and falling-edge polarity settings. There is no
maximum pulse-width requirement in edge-detect mode.
In level-detection mode, there are no minimum or maximum pulse-width
requirements imposed by the PFIs themselves, but there can be limits
imposed by the particular timing signal that is controlled. These
requirements are listed in this chapter under the section for each applicable
signal.
DAQ Timing Connections
The DAQ timing signals are SCANCLK, EXTSTROBE*, TRIG1, TRIG2,
Posttriggered data acquisition allows you to view only data that is acquired
after a trigger event is received. A typical posttriggered DAQ sequence is
shown in Figure 4-17. Pretriggered data acquisition allows you to view data
that is acquired before the trigger of interest in addition to data acquired
after the trigger. Figure 4-18 shows a typical pretriggered DAQ sequence.
The description for each signal shown in these figures is included in this
chapter under the section for each corresponding signal.
TRIG1
STARTSCAN
CONVERT*
Scan Counter
4
3
2
1
0
Figure 4-17. Typical Posttriggered Acquisition
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TRIG1
TRIG2
Don't Care
STARTSCAN
CONVERT*
Scan Counter
3
2
1
0
2
2
2
1
0
Figure 4-18. Typical Pretriggered Acquisition
SCANCLK Signal
edge occurring approximately 50 to 100 ns after an A/D conversion begins.
The polarity of this output is software-selectable, but is typically
configured so that a low-to-high leading edge can clock external analog
input multiplexers indicating when the input signal has been sampled and
can be removed. This signal has a 400 to 500 ns pulse width and is
software-enabled. Figure 4-19 shows the timing for the SCANCLK signal.
CONVERT*
t
d
SCANCLK
t
w
t
t
d
= 50 to 100 ns
w = 400 to 500 ns
Figure 4-19. SCANCLK Signal Timing
EXTSTROBE* Signal
EXTSTROBE* is an output-only signal that generates either a single pulse
or a sequence of eight pulses in the hardware-strobe mode. An external
device can use this signal to latch signals or to trigger events. In the
single-pulse mode, software controls the level of the EXTSTROBE*
signal. A 10 µs and a 1.2 µs clock are available for generating a sequence
of eight pulses in the hardware-strobe mode. Figure 4-20 shows the timing
for the hardware-strobe mode EXTSTROBE* signal.
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V
V
OH
OL
t
t
t
w
w
w
= 600 ns or 5 µs
Figure 4-20. EXTSTROBE* Signal Timing
TRIG1 Signal
Any PFI pin can externally input the TRIG1 signal, which is available as
an output on the PFI0/TRIG1 pin.
Refer to Figures 4-17 and 4-18 for the relationship of TRIG1 to the DAQ
sequence.
As an input, the TRIG1 signal is configured in the edge-detection mode.
You can select any PFI pin as the source for TRIG1 and configure the
polarity selection for either rising or falling edge. The selected edge of the
TRIG1 signal starts the data acquisition sequence for both posttriggered
and pretriggered acquisitions.
As an output, the TRIG1 signal reflects the action that initiates a DAQ
sequence. This is true even if the acquisition is externally triggered by
another PFI. The output is an active high pulse with a pulse width of
50 to 100 ns. This output is set to high impedance at startup.
Figures 4-21 and 4-22 show the input and output timing requirements for
the TRIG1 signal.
t
w
Rising-Edge
Polarity
Falling-Edge
Polarity
t
= 10 ns minimum
w
Figure 4-21. TRIG1 Input Signal Timing
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t
w
t
= 50-100 ns
w
Figure 4-22. TRIG1 Output Signal Timing
The device also uses the TRIG1 signal to initiate pretriggered DAQ
operations. In most pretriggered applications, the TRIG1 signal is
generated by a software trigger. Refer to the TRIG2 signal description for
a complete description of the use of TRIG1 and TRIG2 in a pretriggered
DAQ operation.
TRIG2 Signal
Any PFI pin can externally input the TRIG2 signal, which is available as
an output on the PFI1/TRIG2 pin. Refer to Figure 4-18 for the relationship
of TRIG2 to the DAQ sequence.
As an input, the TRIG2 signal is configured in the edge-detection mode.
You can select any PFI pin as the source for TRIG2 and configure the
polarity selection for either rising or falling edge. The selected edge of the
TRIG2 signal initiates the posttriggered phase of a pretriggered acquisition
sequence. In pretriggered mode, the TRIG1 signal initiates the data
acquisition. The scan counter indicates the minimum number of scans
before TRIG2 can be recognized. After the scan counter decrements to
zero, it is loaded with the number of posttrigger scans to acquire while the
acquisition continues. The device ignores the TRIG2 signal if it is asserted
prior to the scan counter decrementing to zero. After the selected edge of
TRIG2 is received, the device acquires a fixed number of scans and the
acquisition stops. This mode acquires data both before and after receiving
TRIG2.
As an output, the TRIG2 signal reflects the posttrigger in a pretriggered
acquisition sequence. This is true even if the acquisition is externally
triggered by another PFI. The TRIG2 signal is not used in posttriggered
data acquisition. The output is an active high pulse with a pulse width of
50 to 100 ns. This output is set to high impedance at startup.
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Figures 4-23 and 4-24 show the input and output timing requirements for
the TRIG2 signal.
t
w
Rising-Edge
Polarity
Falling-Edge
Polarity
t
= 10 ns minimum
w
Figure 4-23. TRIG2 Input Signal Timing
t
w
t
= 50-100 ns
w
STARTSCAN Signal
Any PFI pin can externally input the STARTSCAN signal, which is
available as an output on the PFI7/STARTSCAN pin. Refer to Figures 4-17
and 4-18 for the relationship of STARTSCAN to the DAQ sequence.
As an input, the STARTSCAN signal is configured in the edge-detection
mode. You can select any PFI pin as the source for STARTSCAN and
configure the polarity selection for either rising or falling edge. The
selected edge of the STARTSCAN signal initiates a scan. The sample
interval counter starts if you select internally triggered CONVERT*.
As an output, the STARTSCAN signal reflects the actual start pulse that
initiates a scan. This is true even if the starts are externally triggered by
another PFI. You have two output options. The first is an active high pulse
with a pulse width of 50 to 100 ns, which indicates the start of the scan. The
second action is an active high pulse that terminates at the start of the last
conversion in the scan, which indicates a scan in progress. STARTSCAN is
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deasserted toff after the last conversion in the scan is initiated. This output is
set to high impedance at startup.
Figures 4-25 and 4-26 show the input and output timing requirements for
the STARTSCAN signal.
t
w
Rising-Edge
Polarity
Falling-Edge
Polarity
t
= 10 ns minimum
w
Figure 4-25. STARTSCAN Input Signal Timing
t
w
STARTSCAN
t
= 50-100 ns
w
a. Start of Scan
Start Pulse
CONVERT*
STARTSCAN
t
off
t
= 10 ns minimum
off
b. Scan in Progress, Two Conversions per Scan
Figure 4-26. STARTSCAN Output Signal Timing
The CONVERT* pulses are masked off until the device generates the
STARTSCAN signal. If you are using internally generated conversions, the
first CONVERT* appears when the onboard sample interval counter
reaches zero. If you select an external CONVERT*, the first external pulse
after STARTSCAN generates a conversion. Separate the STARTSCAN
pulses by at least one scan period.
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A counter on your device internally generates the STARTSCAN signal
unless you select some external source. This counter is started by the
TRIG1 signal and is stopped either by software or by the sample counter.
Scans generated by either an internal or external STARTSCAN signal are
inhibited unless they occur within a DAQ sequence. Scans occurring within
a DAQ sequence can be gated by either the hardware (AIGATE) signal or
software command register gate.
CONVERT* Signal
Any PFI pin can externally input the CONVERT* signal, which is
available as an output on the PFI2/CONVERT* pin.
Refer to Figures 4-17 and 4-18 for the relationship of CONVERT* to the
DAQ sequence.
As an input, the CONVERT* signal is configured in the edge-detection
mode. You can select any PFI pin as the source for CONVERT* and
configure the polarity selection for either rising or falling edge. The
selected edge of the CONVERT* signal initiates an A/D conversion.
The ADC switches to hold mode within 60 ns of the selected edge. This
hold-mode delay time is a function of temperature and does not vary from
one conversion to the next. Separate the CONVERT* pulses by at least 5 µs
(200 kHz sample rate).
As an output, the CONVERT* signal reflects the actual convert pulse that
is connected to the ADC. This is true even if the conversions are externally
generated by another PFI. The output is an active low pulse with a pulse
width of 50 to 150 ns. This output is set to high impedance at startup.
Figures 4-27 and 4-28 show the input and output timing requirements for
the CONVERT* signal.
t
w
Rising-Edge
Polarity
Falling-Edge
Polarity
t
= 10 ns minimum
w
Figure 4-27. CONVERT* Input Signal Timing
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t
w
t
= 50-150 ns
w
Figure 4-28. CONVERT* Output Signal Timing
The sample interval counter on the device normally generates the
CONVERT* signal unless you select some external source. The counter is
started by the STARTSCAN signal and continues to count down and reload
itself until the scan is finished. It then reloads itself in preparation for the
next STARTSCAN pulse.
A/D conversions generated by either an internal or external CONVERT*
signal are inhibited unless they occur within a DAQ sequence. Scans
occurring within a DAQ sequence can be gated by either the hardware
(AIGATE) signal or software command register gate.
AIGATE Signal
Any PFI pin can externally input the AIGATE signal, which is not
available as an output on the I/O connector. The AIGATE signal can
mask off scans in a DAQ sequence. You can configure the PFI pin you
select as the source for the AIGATE signal in either the level-detection or
edge-detection mode. You can configure the polarity selection for the
PFI pin for either active high or active low.
In the level-detection mode if AIGATE is active, the STARTSCAN signal
is masked off and no scans can occur. In the edge-detection mode, the first
active edge disables the STARTSCAN signal, and the second active edge
enables STARTSCAN.
The AIGATE signal can neither stop a scan in progress nor continue a
previously gated-off scan; in other words, once a scan has started, AIGATE
does not gate off conversions until the beginning of the next scan and,
conversely, if conversions are gated off, AIGATE does not gate them back
on until the beginning of the next scan.
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SISOURCE Signal
Any PFI pin can externally input the SISOURCE signal, which is not
available as an output on the I/O connector. The onboard scan interval
counter uses the SISOURCE signal as a clock to time the generation of the
STARTSCAN signal. You must configure the PFI pin you select as the
source for the SISOURCE signal in the level-detection mode. You can
configure the polarity selection for the PFI pin for either active high or
active low.
The maximum allowed frequency is 20 MHz, with a minimum pulse width
of 23 ns high or low. There is no minimum frequency limitation.
Either the 20 MHz or 100 kHz internal timebase generates the SISOURCE
signal unless you select some external source. Figure 4-29 shows the timing
requirements for the SISOURCE signal.
t
p
t
t
w
w
t
= 50 ns minimum
= 23 ns minimum
p
t
w
Figure 4-29. SISOURCE Signal Timing
Waveform Generation Timing Connections
The analog group defined for your device is controlled by WFTRIG,
UPDATE*, and UISOURCE.
WFTRIG Signal
Any PFI pin can externally input the WFTRIG signal, which is available as
an output on the PFI6/WFTRIG pin.
As an input, the WFTRIG signal is configured in the edge-detection mode.
You can select any PFI pin as the source for WFTRIG and configure the
polarity selection for either rising or falling edge. The selected edge of the
WFTRIG signal starts the waveform generation for the DACs. The update
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waveform generation. This is true even if the waveform generation is
externally triggered by another PFI. The output is an active high pulse with
a pulse width of 50 to 100 ns. This output is set to high impedance at
startup.
Figures 4-30 and 4-31 show the input and output timing requirements for
the WFTRIG signal.
t
w
Rising-Edge
Polarity
Falling-Edge
Polarity
t
= 10 ns minimum
w
Figure 4-30. WFTRIG Input Signal Timing
t
w
t
= 50-100 ns
w
Figure 4-31. WFTRIG Output Signal Timing
UPDATE* Signal
Any PFI pin can externally input the UPDATE* signal, which is available
as an output on the PFI5/UPDATE* pin.
As an input, the UPDATE* signal is configured in the edge-detection mode.
You can select any PFI pin as the source for UPDATE* and configure the
polarity selection for either rising or falling edge. The selected edge of the
UPDATE* signal updates the outputs of the DACs. In order to use
UPDATE*, you must set the DACs to posted-update mode.
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As an output, the UPDATE* signal reflects the actual update pulse that is
connected to the DACs. This is true even if the updates are externally
generated by another PFI. The output is an active low pulse with a pulse
width of 300 to 350 ns. This output is set to high impedance at startup.
Figures 4-32 and 4-33 show the input and output timing requirements for
the UPDATE* signal.
t
w
Rising-Edge
Polarity
Falling-Edge
Polarity
t
= 10 ns minimum
w
Figure 4-32. UPDATE* Input Signal Timing
t
w
t
= 300-350 ns
w
Figure 4-33. UPDATE* Output Signal Timing
The DACs are updated within 100 ns of the leading edge. Separate the
UPDATE* pulses with enough time that new data can be written to the DAC
latches.
The device UI counter normally generates the UPDATE* signal unless you
select some external source. The UI counter is started by the WFTRIG
signal and can be stopped by software or the internal Buffer Counter.
D/A conversions generated by either an internal or external UPDATE*
signal do not occur when gated by the software command register gate.
UISOURCE Signal
Any PFI pin can externally input the UISOURCE signal, which is not
available as an output on the I/O connector. The UI counter uses the
UISOURCE signal as a clock to time the generation of the UPDATE*
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Chapter 4
Signal Connections
signal. You must configure the PFI pin you select as the source for the
UISOURCE signal in the level-detection mode. You can configure the
polarity selection for the PFI pin for either active high or active low.
Figure 4-34 shows the timing requirements for the UISOURCE signal.
t
p
t
t
w
w
t
= 50 ns minimum
= 23 ns minimum
p
t
w
Figure 4-34. UISOURCE Signal Timing
The maximum allowed frequency is 20 MHz, with a minimum pulse width
of 23 ns high or low. There is no minimum frequency limitation.
Either the 20 MHz or 100 kHz internal timebase normally generates the
UISOURCE signal unless you select some external source.
General-Purpose Timing Signal Connections
The general-purpose timing signals are GPCTR0_SOURCE,
GPCTR0_GATE, GPCTR0_OUT, GPCTR0_UP_DOWN,
GPCTR1_SOURCE, GPCTR1_GATE, GPCTR1_OUT,
GPCTR1_UP_DOWN, and FREQ_OUT.
GPCTR0_SOURCE Signal
Any PFI pin can externally input the GPCTR0_SOURCE signal, which is
available as an output on the PFI8/GPCTR0_SOURCE pin.
As an input, the GPCTR0_SOURCE signal is configured in the
edge-detection mode. You can select any PFI pin as the source for
GPCTR0_SOURCE and configure the polarity selection for either rising
or falling edge.
As an output, the GPCTR0_SOURCE signal reflects the actual clock
connected to general-purpose counter 0. This is true even if another PFI
is externally inputting the source clock. This output is set to high
impedance at startup.
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Figure 4-35 shows the timing requirements for the GPCTR0_SOURCE
signal.
t
p
t
t
w
w
t
= 50 ns minimum
= 23 ns minimum
p
t
w
Figure 4-35. GPCTR0_SOURCE Signal Timing
The maximum allowed frequency is 20 MHz, with a minimum pulse width
of 23 ns high or low. There is no minimum frequency limitation.
The 20 MHz or 100 kHz timebase normally generates the
GPCTR0_SOURCE signal unless you select some external source.
GPCTR0_GATE Signal
Any PFI pin can externally input the GPCTR0_GATE signal, which is
available as an output on the PFI9/GPCTR0_GATE pin.
As an input, the GPCTR0_GATE signal is configured in the edge-detection
mode. You can select any PFI pin as the source for GPCTR0_GATE and
configure the polarity selection for either rising or falling edge. You can use
the gate signal in a variety of different applications to perform actions such
counter contents, and so on.
As an output, the GPCTR0_GATE signal reflects the actual gate signal
connected to general-purpose counter 0. This is true even if the gate is
externally generated by another PFI. This output is set to high impedance
at startup. Figure 4-36 shows the timing requirements for the
GPCTR0_GATE signal.
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t
w
Rising-Edge
Polarity
Falling-Edge
Polarity
t
= 10 ns minimum
w
Figure 4-36. GPCTR0_GATE Signal Timing in Edge-Detection Mode
GPCTR0_OUT Signal
This signal is available only as an output on the GPCTR0_OUT pin. The
GPCTR0_OUT signal reflects the terminal count (TC) of general-purpose
counter 0. You have two software-selectable output options—pulse on TC
and toggle output polarity on TC. The output polarity is software-selectable
for both options. This output is set to high impedance at startup.
Figure 4-37 shows the timing of the GPCTR0_OUT signal.
TC
GPCTR0_SOURCE
GPCTR0_OUT
(Pulse on TC)
GPCTR0_OUT
(Toggle Output on TC)
Figure 4-37. GPCTR0_OUT Signal Timing
GPCTR0_UP_DOWN Signal
This signal can be externally input on the DIO6 pin and is not available as
an output on the I/O connector. The general-purpose counter 0 counts down
when this pin is at a logic low and count up when it is at a logic high. You
can disable this input so that software can control the up-down
functionality and leave the DIO6 pin free for general use.
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Signal Connections
GPCTR1_SOURCE Signal
Any PFI pin can externally input the GPCTR1_SOURCE signal, which is
available as an output on the PFI3/GPCTR1_SOURCE pin. As an input,
the GPCTR1_SOURCE signal is configured in the edge-detection mode.
You can select any PFI pin as the source for GPCTR1_SOURCE and
configure the polarity selection for either rising or falling edge.
As an output, the GPCTR1_SOURCE monitors the actual clock connected
to general-purpose counter 1. This is true even if the source clock is
externally generated by another PFI. This output is set to high impedance
at startup.
Figure 4-38 shows the timing requirements for the GPCTR1_SOURCE
signal.
t
p
t
t
w
w
t
= 50 ns minimum
= 23 ns minimum
p
t
w
Figure 4-38. GPCTR1_SOURCE Signal Timing
The maximum allowed frequency is 20 MHz, with a minimum pulse width
of 23 ns high or low. There is no minimum frequency limitation.
The 20 MHz or 100 kHz timebase normally generates the
GPCTR1_SOURCE unless you select some external source.
GPCTR1_GATE Signal
Any PFI pin can externally input the GPCTR1_GATE signal, which is
available as an output on the PFI4/GPCTR1_GATE pin.
As an input, the GPCTR1_GATE signal is configured in edge-detection
mode. You can select any PFI pin as the source for GPCTR1_GATE and
configure the polarity selection for either rising or falling edge. You can use
the gate signal in a variety of different applications to perform such actions
as starting and stopping the counter, generating interrupts, saving the
counter contents, and so on.
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As an output, the GPCTR1_GATE signal monitors the actual gate signal
connected to general-purpose counter 1. This is true even if the gate is
externally generated by another PFI. This output is set to high impedance
at startup.
Figure 4-39 shows the timing requirements for the GPCTR1_GATE signal.
t
w
Rising-Edge
Polarity
Falling-Edge
Polarity
t
= 10 ns minimum
w
Figure 4-39. GPCTR1_GATE Signal Timing in Edge-Detection Mode
GPCTR1_OUT Signal
This signal is available only as an output on the GPCTR1_OUT pin.
The GPCTR1_OUT signal monitors the TC device general-purpose
counter 1. You have two software-selectable output options—pulse on TC
and toggle output polarity on TC. The output polarity is software-selectable
for both options. This output is set to high impedance at startup.
Figure 4-40 shows the timing requirements for the GPCTR1_OUT signal.
TC
GPCTR1_SOURCE
GPCTR1_OUT
(Pulse on TC)
GPCTR1_OUT
(Toggle Output on TC)
Figure 4-40. GPCTR1_OUT Signal Timing
GPCTR1_UP_DOWN Signal
This signal can be externally input on the DIO7 pin and is not available as
an output on the I/O connector. General-purpose counter 1 counts down
when this pin is at a logic low and counts up at a logic high. This input can
be disabled so that software can control the up-down functionality and
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leave the DIO7 pin free for general use. Figure 4-41 shows the timing
requirements for the GATE and SOURCE input signals and the timing
specifications for the OUT output signals of your device.
tsc
tsp
tsp
V
IH
SOURCE
VIL
tgsu
tgh
V
IH
IL
GATE
OUT
V
tgw
tout
V
V
OH
OL
Source Clock Period
Source Pulse Width
Gate Setup Time
Gate Hold Time
Gate Pulse Width
Output Delay Time
tsc
50 ns minimum
23 ns minimum
10 ns minimum
0 ns minimum
10 ns minimum
80 ns maximum
tsp
tgsu
tgh
tgw
tout
Figure 4-41. GPCTR Timing Summary
The GATE and OUT signal transitions shown in Figure 4-41 are referenced
to the rising edge of the SOURCE signal. This timing diagram assumes that
the counters are programmed to count rising edges. The same timing
edge of the source signal, applies when the counter is programmed to count
falling edges.
The GATE input timing parameters are referenced to the signal at the
SOURCE input or to one of the internally generated signals on your device.
Figure 4-41 shows the GATE signal referenced to the rising edge of a
source signal. The gate must be valid (either high or low) for at least 10 ns
before the rising or falling edge of a source signal for the gate to take effect
at that source edge, as shown by tgsu and tgh in Figure 4-41. The gate signal
is not required to be held after the active edge of the source signal.
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If you use an internal timebase clock, the gate signal cannot be
synchronized with the clock. In this case, gates applied close to a source
arrangement results in an uncertainty of one source clock period with
respect to unsynchronized gating sources.
The OUT output timing parameters are referenced to the signal at the
SOURCE input or to one of the internally generated clock signals on the
devices. Figure 4-41 shows the OUT signal referenced to the rising edge of
a source signal. Any OUT signal state changes occur within 80 ns after the
rising or falling edge of the source signal.
FREQ_OUT Signal
This signal is available only as an output on the FREQ_OUT pin. The
frequency generator of the device outputs the FREQ_OUT pin. The
frequency generator is a 4-bit counter that can divide its input clock by the
numbers 1 through 16. The input clock of the frequency generator is
software-selectable from the internal 10 MHz and 100 kHz timebases. The
output polarity is software-selectable. This output is set to high impedance
at startup.
Field Wiring Considerations
Environmental noise can seriously affect the accuracy of measurements
made with your device if you do not take proper care when running
signal wires between signal sources and the device. The following
recommendations apply mainly to analog input signal routing to the device,
although they also apply to signal routing in general.
Minimize noise pickup and maximize measurement accuracy by taking the
following precautions:
•
•
Use DIFF analog input connections to reject common-mode noise.
Use individually shielded, twisted-pair wires to connect analog input
signals to the device. With this type of wire, the signals attached to the
CH+ and CH– inputs are twisted together and then covered with a
shield. You then connect this shield only at one point to the signal
source ground. This kind of connection is required for signals traveling
through areas with large magnetic fields or high electromagnetic
interference.
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5
Calibration
This chapter discusses the calibration procedures for your device. If you
are using the NI-DAQ device driver, that software includes calibration
functions for performing all of the steps in the calibration process.
Calibration refers to the process of minimizing measurement and output
voltage errors by making small circuit adjustments. For these devices, these
adjustments take the form of writing values to onboard calibration DACs
(CalDACs).
Some form of device calibration is required for all but the most forgiving
applications. If you do not calibrate your device, your signals and
measurements could have very large offset, gain, and linearity errors.
Three levels of calibration are available to you and described in this chapter.
The first level is the fastest, easiest, and least accurate, whereas the last
level is the slowest, most difficult, and most accurate.
Loading Calibration Constants
Your device is factory calibrated before shipment at approximately 25 °C
to the levels indicated in Appendix A, Specifications. The associated
calibration constants—the values that were written to the CalDACs to
achieve calibration in the factory—are stored in the onboard nonvolatile
memory (EEPROM). Because the CalDACs have no memory capability,
they do not retain calibration information when the device is unpowered.
Loading calibration constants refers to the process of loading the CalDACs
with the values stored in the EEPROM. NI-DAQ software determines
when this is necessary and does it automatically. If you are not using
NI-DAQ, you must load these values yourself.
In the EEPROM there is a user-modifiable calibration area in addition to
the permanent factory calibration area. This means that you can load the
CalDACs with values either from the original factory calibration or from a
calibration that you subsequently performed.
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Calibration
This method of calibration is not very accurate because it does not take into
account the fact that the device measurement and output voltage errors can
vary with time and temperature. It is better to self-calibrate the device when
it is installed in the environment in which it will be used.
Self-Calibration
Your device can measure and correct for almost all of its calibration-related
errors without any external signal connections. Your National Instruments
software provides a self-calibration method. This self-calibration process,
which generally takes less than a minute, is the preferred method of
assuring accuracy in your application. Initiate self-calibration to minimize
the effects of any offset, gain, and linearity drifts, particularly those due to
warmup.
Immediately after self-calibration, the only significant residual calibration
error could be gain error due to time or temperature drift of the onboard
voltage reference. This error is addressed by external calibration, which is
discussed in the following section. If you are interested primarily in relative
measurements, you can ignore a small amount of gain error, and
self-calibration should be sufficient.
External Calibration
Your device has an onboard calibration reference to ensure the accuracy of
self-calibration. Its specifications are listed in Appendix A, Specifications.
The reference voltage is measured at the factory and stored in the EEPROM
for subsequent self-calibrations. This voltage is stable enough for most
applications, but if you are using your device at an extreme temperature or
if the onboard reference has not been measured for a year or more, you may
wish to externally calibrate your device.
An external calibration refers to calibrating your device with a known
external reference rather than relying on the onboard reference.
Redetermining the value of the onboard reference is part of this process and
you can save the results in the EEPROM, so you should not have to perform
an external calibration very often. You can externally calibrate your device
by calling the NI-DAQ calibration function.
To externally calibrate your device, be sure to use a very accurate external
reference. Use a reference that is several times more accurate than the
device itself.
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Calibration
Other Considerations
adjusting the value of the reference voltage supplied to that channel. This
calibration mechanism is designed to work only with the internal 10 V
reference. Thus, in general, it is not possible to calibrate the analog output
gain error when using an external reference. In this case, it is advisable to
account for the nominal gain error of the analog output channel either in
software or with external hardware. See Appendix A, Specifications, for
analog output gain error information.
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A
Specifications
This appendix individually lists the specifications of each bus type and are
typical at 25 °C.
PCI and PXI Buses
Analog Input
Input Characteristics
Number of channels ............................... 16 single-ended or 8 differential
(software-selectable per channel)
Type of ADC.......................................... Successive approximation
Resolution .............................................. 12 bits, 1 in 4,096
Sampling rate ......................................... 200 kS/s guaranteed
Input signal ranges ................................. Bipolar only
Board Gain
(Software-Selectable)
Range
10 V
0.5
1
5 V
10
100
500 mV
50 mV
Input coupling ........................................ DC
Max working voltage
(signal + common mode) ....................... Each input should remain
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Appendix A
Specifications for PCI and PXI Buses
Overvoltage protection
Signal
ACH<0..15>
AISENSE
Powered On
Powered Off
42
40
35
25
FIFO buffer size......................................512 S
Data transfers..........................................DMA, interrupts,
programmed I/O
DMA modes ...........................................Scatter-gather
(single transfer, demand transfer)
Configuration memory size ....................512 words
Accuracy Information
Absolute Accuracy
Relative Accuracy
Resolution (mV)
Noise + Quantization
(mV)
Absolute
Accuracy
at Full
Scale
Nominal Range (V)
% of Reading
Temp
Drift
Positive
FS
Negative
FS
Offset
(mV)
24 Hours
1 Year
0.0914
0.0314
0.0914
0.0914
Single Pt.
3.91
Averaged
0.975
(%/ °C)
(mV)
Single Pt.
5.89
Averaged
1.28
10
5
–10
–5
0.0872
0.0272
0.0872
0.0872
6.38
3.20
0.0010
0.0005
0.0010
0.0010
16.504
5.263
0.846
0.106
1.95
0.488
2.95
0.295
0.073
0.642
0.064
0.008
0.5
0.05
–0.5
–0.05
0.340
0.054
0.195
0.063
0.049
0.006
Note: Accuracies are valid for measurements following an internal E Series calibration. Averaged numbers assume dithering and averaging of
100 single-channel readings. Measurement accuracies are listed for operational temperatures within 1 °C of internal calibration temperature
and 10 °C of external or factory-calibration temperature. One-year calibration interval recommended. The Absolute Accuracy at Full Scale
calculations were performed for a maximum range input voltage (for example, 10 V for the 10 V range) after one year, assuming 100 pt
averaging of data.
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Specifications for PCI and PXI Buses
Transfer Characteristics
Relative accuracy ................................... 0.5 LSB typ dithered,
1.5 LSB max undithered
DNL ....................................................... 0.5 LSB typ, 1.0 LSB max
No missing codes ................................... 12 bits, guaranteed
Offset error
Pregain error after calibration......... 12 µV max
Pregain error before calibration ...... 28 mV max
Postgain error after calibration ....... 0.5 mV max
Postgain error before calibration..... 100 mV max
Gain error (relative to calibration reference)
After calibration (gain = 1) ............. 0.02% of reading max
Before calibration ........................... 2.75% of reading max
Gain ≠ 1 with gain error
adjusted to 0 at gain = 1.................. 0.05% of reading max
Amplifier Characteristics
Input impedance
Normal powered on ........................ 100 GΩ in parallel with 100 pF
Powered off..................................... 4 kΩ min
Overload.......................................... 4 kΩ min
Input bias current ................................... 200 pA
Input offset current................................. 100 pA
CMRR (DC to 60 Hz)
Gain 0.5, 1.0.................................... 85 dB
Gain 10, 100.................................... 90 dB
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Appendix A
Specifications for PCI and PXI Buses
Dynamic Characteristics
Bandwidth
Signal
Bandwidth
500 kHz
Small (–3 dB)
Large (1% THD)
225 kHz
Settling time for full-scale step...............5 µs max to 1.0 LSB accuracy
System noise (LSBrms, not including quantization)
Gain
0.5 to 10
100
Dither Off
Dither On
0.6
0.1
0.7
0.8
Crosstalk .................................................–60 dB, DC to 100 kHz
Stability
Recommended warm-up time.................15 min.
Offset temperature coefficient
Pregain............................................. 15 µV/°C
Postgain ........................................... 240 µV/°C
Gain temperature coefficient .................. 20 ppm/°C
Analog Output
♦
6024E and 6025E only
Output Characteristics
Number of channels................................2 voltage
Resolution...............................................12 bits, 1 in 4,096
Max update rate
DMA................................................10 kHz, system dependent
Interrupts..........................................1 kHz, system dependent
Type of DAC ..........................................Double buffered, multiplying
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Specifications for PCI and PXI Buses
FIFO buffer size..................................... None
Data transfers ......................................... DMA, interrupts,
programmed I/O
DMA modes........................................... Scatter-gather
(Single transfer, demand transfer)
Accuracy Information
Absolute Accuracy
Absolute
Accuracy at
Full Scale
(mV)
Nominal Range (V)
% of Reading
90 Days
Temp Drift
(%/ °C)
Positive FS
Negative FS
24 Hours
1 Year
Offset (mV)
10
–10
0.0177
0.0197
0.0219
5.93
0.0005
8.127
Note: Temp Drift applies only if ambient is greater than 10 °C of previous external calibration.
Transfer Characteristics
Relative accuracy (INL)
After calibration.............................. 0.3 LSB typ, 0.5 LSB max
Before calibration ........................... 4 LSB max
DNL
After calibration.............................. 0.3 LSB typ, 1.0 LSB max
Before calibration ........................... 3 LSB max
Monotonicity.......................................... 12 bits, guaranteed after
calibration
Offset error
After calibration.............................. 1.0 mV max
Before calibration ........................... 200 mV max
Gain error (relative to internal reference)
After calibration.............................. 0.01% of output max
Before calibration ........................... 0.75% of output max
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Specifications for PCI and PXI Buses
Voltage Output
Range...................................................... 10 V
Output coupling ......................................DC
Output impedance...................................0.1 Ω max
Current drive........................................... 5 mA max
Protection................................................Short-circuit to ground
Power-on state (steady state) .................. 200 mV
Initial power-up glitch
Magnitude........................................ 1.1 V
Duration........................................... 2.0 ms
Power reset glitch
Magnitude........................................ 2.2 V
Duration........................................... 4.2 µs
Dynamic Characteristics
Settling time for full-scale step...............10 µs to 0.5 LSB accuracy
Slew rate .................................................10 V/µs
Noise.......................................................200 µVrms, DC to 1 MHz
Midscale transition glitch
Magnitude........................................ 45 mV
Duration........................................... 2.0 µs
Stability
Offset temperature coefficient................ 50 µV/°C
Gain temperature coefficient .................. 25 ppm/°C
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Appendix A
Specifications for PCI and PXI Buses
Digital I/O
Number of channels
6025E.............................................. 32 input/output
6023E and 6024E............................ 8 input/output
Compatibility ......................................... TTL/CMOS
DIO<0..7>
Digital logic levels
Level
Min
0 V
2 V
—
Max
0.8 V
5 V
Input low voltage
Input high voltage
Input low current (Vin = 0 V)
Input high current (Vin = 5 V)
Output low voltage (IOL = 24 mA)
Output high voltage (IOH = 13 mA)
–320 µA
10 µA
0.4 V
—
—
—
4.35 V
Power-on state........................................ Input (High-Z),
50 kΩ pull up to +5 VDC
Data transfers ......................................... Programmed I/O
PA<0..7>,PB<0..7>,PC<0..7>
6025E only
♦
Digital logic levels
Level
Min
Max
0.8 V
5 V
Input low voltage
Input high voltage
0 V
2.2 V
—
Input low current (Vin = 0 V, 100 kΩ pull up)
Input high current (Vin = 5 V, 100 kΩ pull up)
Output low voltage (IOL = 2.5 mA)
–75 µA
10 µA
—
—
—
Output high voltage (IOH = 2.5 mA)
3.7 V
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Specifications for PCI and PXI Buses
Handshaking ...........................................2-wire
Power-on state
PA<0..7> .........................................Input (High-Z),
100 kΩ pull-up to +5 VDC
PB<0..7>..........................................Input (High-Z),
100 kΩ pull-up to +5 VDC
PC<0..7>..........................................Input (High-Z),
100 kΩ pull-up to +5 VDC
Data transfers..........................................Interrupts, programmed I/O
Timing I/O
Number of channels................................2 up/down counter/timers,
1 frequency scaler
Resolution
Counter/timers.................................24 bits
Frequency scalers ............................4 bits
Compatibility..........................................TTL/CMOS
Base clocks available
Counter/timers.................................20 MHz, 100 kHz
Frequency scalers ............................10 MHz, 100 kHz
Base clock accuracy................................ 0.01%
Max source frequency.............................20 MHz
Min source pulse duration ......................10 ns in edge-detect mode
Min gate pulse duration ..........................10 ns in edge-detect mode
Data transfers..........................................DMA, interrupts,
programmed I/O
DMA modes ...........................................Scatter-gather
(single transfer, demand transfer)
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Specifications for PCI and PXI Buses
Triggers
Digital Trigger
Compatibility ......................................... TTL
Response ................................................ Rising or falling edge
Pulse width............................................. 10 ns min
RTSI
Trigger lines ........................................... 7
Calibration
Recommended warm-up time ................ 15 min
Interval ................................................... 1 year
External calibration reference ................ > 6 and < 10 V
Onboard calibration reference
Level ............................................... 5.000 V ( 3.5 mV) (actual
value stored in EEPROM)
Temperature coefficient.................. 5 ppm/°C max
Long-term stability ......................... 15 ppm/ 1, 000 h
Power Requirement
+5 VDC ( 5%)....................................... 0.7 A
Note Excludes power consumed through Vcc available at the I/O connector.
Power available at I/O connector........... +4.65 to +5.25 VDC at 1 A
Physical
Dimensions (not including connectors)
PCI devices ..................................... 17.5 by 10.6 cm (6.9 by 4.2 in.)
PXI devices..................................... 16.0 by 10.0 cm (6.3 by 3.9 in.)
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Appendix A
Specifications for PCI and PXI Buses
I/O connector
6023E/6024E...................................68-pin male SCSI-II type
6025E...............................................100-pin female 0.05D type
Operating Environment
Ambient temperature ..............................0 to 55 °C
Relative humidity ...................................10 to 90% noncondensing
PXI-6025E only
♦
Functional shock.....................................MIL-T-28800 E Class 3 (per
Section 4.5.5.4.1) Half-sine shock
pulse, 11 ms duration, 30 g peak,
30 shocks per face
Operational random vibration.................5 to 500 Hz, 0.31 grms, 3 axes
Storage Environment
Ambient temperature ..............................–20 to 70 °C
Relative humidity ...................................5% to 95% noncondensing
PXI-6025E only
♦
Non-operational random vibration .........5 to 500 Hz, 2.5 grms, 3 axes
Note Random vibration profiles for the PXI-6025E were developed in accordance with
MIL-T-28800E and MIL-STD-810E Method 514. Test levels exceed those recommended
in MIL-STD-810E for Category 1, Basic Transportation.
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Appendix A
Specifications for PCMCIA Bus
PCMCIA Bus
Analog Input
Input Characteristics
Number of channels ............................... 16 single-ended or 8 differential
(software-selectable per channel)
Type of ADC.......................................... Successive approximation
Resolution .............................................. 12 bits, 1 in 4,096
Sampling rate ........................................ 200 kS/s guaranteed
Input signal ranges ................................ Bipolar only
Board Gain
(Software-Selectable)
Range
10 V
0.5
1
5 V
10
100
500 mV
50 mV
Input coupling ........................................ DC
Max working voltage
(signal + common mode) ....................... Each input should remain
within 11 V of ground
Overvoltage protection
Signal
ACH<0..15>
AISENSE
Powered On
Powered Off
42
40
35
25
FIFO buffer size..................................... 2048 S
Data transfers ......................................... Interrupts, programmed I/O
Configuration memory size.................... 512 words
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Appendix A
Specifications for PCMCIA Bus
Accuracy Information
Absolute Accuracy
Relative Accuracy
Resolution (mV)
Noise + Quantization
(mV)
Absolute
Accuracy
at Full
Scale
Nominal Range (V)
% of Reading
Temp
Drift
Positive
FS
Negative
FS
Offset
(mV)
24 Hours
1 Year
0.0914
0.0314
0.0914
0.0914
Single Pt.
Averaged
1.042
(%/ °C)
(mV)
Single Pt.
5.89
Averaged
1.37
10
5
–10
–5
0.0872
0.0272
0.0872
0.0872
8.83
4.42
3.91
1.95
0.0010
0.0005
0.0010
0.0010
19.012
6.517
0.972
0.119
0.521
2.95
0.516
0.073
0.686
0.069
0.009
0.5
0.05
–0.5
–0.05
0.462
0.066
0.452
0.063
0.052
0.007
Note: Accuracies are valid for measurements following an internal E Series calibration. Averaged numbers assume dithering and averaging of
100 single-channel readings. Measurement accuracies are listed for operational temperatures within 1 °C of internal calibration temperature
and 10 °C of external or factory calibration temperature.
Transfer Characteristics
Relative accuracy.................................... 0.5 LSB typ dithered,
1.5 LSB max undithered
DNL........................................................ 0.75 LSB typ,
–0.9 to +1.5 LSB max
No missing codes....................................12 bits, guaranteed
Offset error
Pregain error after calibration.......... 12 µV max
Pregain error before calibration....... 28 mV max
Postgain error after calibration........ 0.5 mV max
Postgain error before calibration ..... 100 mV max
Gain error (relative to calibration reference)
After calibration (gain = 1).............. 0.02% of reading max
Before calibration............................ 2.75% of reading max
Gain ≠ 1 with gain error
adjusted to 0 at gain = 1................... 0.05% of reading max
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Appendix A
Specifications for PCMCIA Bus
Amplifier Characteristics
Input impedance
Normal powered on ........................ 100 GΩ in parallel with 100 pF
Powered off..................................... 4 kΩ min
Overload.......................................... 4 kΩ min
Input bias current ................................... 200 pA
Input offset current................................. 100 pA
CMRR (DC to 60 Hz)
Gain 0.5, 1.0.................................... 85 dB
Gain 10, 100.................................... 90 dB
Dynamic Characteristics
Bandwidth
Signal
Bandwidth
500 kHz
Small (–3 dB)
Large (1% THD)
225 kHz
Settling time for full-scale step .............. 5 µs max to 1.0 LSB accuracy
System noise (LSBrms, not including quantization)
Gain
0.5 to 1
10
Dither Off
0.10
Dither On
0.65
0.45
0.65
100
0.70
0.90
Crosstalk................................................. –60 dB, DC to 100 kHz
Stability
Recommended warm-up time ................ 30 min
Offset temperature coefficient
Pregain ............................................ 15 µV/°C
Postgain........................................... 240 µV/°C
© National Instruments Corporation
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Appendix A
Specifications for PCMCIA Bus
Gain temperature coefficient .................. 20 ppm/°C
Analog Output
Output Characteristics
Number of channels................................2 voltage
Resolution...............................................12 bits, 1 in 4,096
Max update rate
Interrupts..........................................1 kHz, system dependent
Type of DAC ..........................................Double buffered, multiplying
FIFO buffer size......................................None
Data transfers..........................................Interrupts, programmed I/O
Accuracy Information
Absolute Accuracy
Absolute
Nominal Range (V)
% of Reading
90 Days
Accuracy at
Full Scale
(mV)
Temp Drift
(%/ °C)
Positive FS
Negative FS
24 Hours
1 Year
Offset (mV)
10
–10
0.0177
0.0197
0.0219
5.93
0.0005
8.127
Note: Temp Drift applies only if ambient is greater than 10 °C of previous external calibration.
Transfer Characteristics
Relative accuracy (INL)
After calibration............................... 0.5 LSB typ, 1.0 LSB max
Before calibration............................ 4 LSB max
DNL
After calibration............................... 0.5 LSB typ, 1.0 LSB max
Before calibration............................ 3 LSB max
Monotonicity ..........................................12 bits, guaranteed after
calibration
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Appendix A
Specifications for PCMCIA Bus
Offset error
After calibration.............................. 1.0 mV max
Before calibration ........................... 200 mV max
Gain error (relative to internal reference)
After calibration.............................. 0.01% of output max
Before calibration ........................... 0.75% of output max
Voltage Output
Range ..................................................... 10 V
Output coupling...................................... DC
Output impedance .................................. 0.1 Ω max
Current drive .......................................... 5 mA max
Protection ............................................... Short-circuit to ground
Power-on state (steady state).................. 200 mV
Initial power-up glitch
Magnitude ....................................... 1.5 V
Duration .......................................... 1.0 s
Power reset glitch
Magnitude ....................................... 1.5 V
Duration .......................................... 1.0 s
Dynamic Characteristics
Settling time for full-scale step .............. 10 µs to 0.5 LSB accuracy
Slew rate................................................. 10 V/µs
Noise ...................................................... 200 µVrms, DC to 1 MHz
Midscale transition glitch
Magnitude ....................................... 20 mV
Duration .......................................... 2.5 µs
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Appendix A
Specifications for PCMCIA Bus
Stability
Offset temperature coefficient................ 50 µV/°C
Gain temperature coefficient .................. 25 ppm/°C
Digital I/O
Number of channels................................8 input/output
Compatibility..........................................TTL/CMOS
DIO<0..7>
Digital logic levels
Level
Min
0 V
2 V
—
Max
0.8 V
5 V
Input low voltage
Input high voltage
Input low current (Vin = 0 V)
Input high current (Vin = 5 V)
Output low voltage (IOL = 24 mA)
Output high voltage (IOH = 13 mA)
–320 µA
10 µA
0.4 V
—
—
—
4.35 V
Power-on state.........................................Input (High-Z),
50 kΩ pull up to +5 VDC
Data transfers..........................................Programmed I/O
Timing I/O
Number of channels................................2 up/down counter/timers,
1 frequency scaler
Resolution
Counter/timers.................................24 bits
Frequency scalers ............................4 bits
Compatibility..........................................TTL/CMOS
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Appendix A
Specifications for PCMCIA Bus
Base clocks available
Counter/timers ................................ 20 MHz, 100 kHz
Frequency scalers............................ 10 MHz, 100 kHz
Base clock accuracy............................... 0.01%
Max source frequency............................ 20 MHz
Min source pulse duration...................... 10 ns in edge-detect mode
Min gate pulse duration.......................... 10 ns in edge-detect mode
Data transfers ......................................... Interrupts, programmed I/O
Triggers
Digital Trigger
Compatibility ......................................... TTL
Response ................................................ Rising or falling edge
Pulse width............................................. 10 ns min
Calibration
Recommended warm-up time ................ 30 min
Interval ................................................... 1 year
External calibration reference ................ > 6 and < 10 V
Onboard calibration reference
Level ............................................... 5.000 V ( 3.5 mV) (actual
value stored in EEPROM)
Temperature coefficient.................. 5 ppm/°C max
Long-term stability ......................... 15 ppm/ 1, 000 h
Power Requirement
+5 VDC ( 5%)....................................... 270 mA
Note Excludes power consumed through Vcc available at the I/O connector.
Power available at I/O connector........... +4.65 to +5.25 VDC at 0.75 A
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Appendix A
Specifications for PCMCIA Bus
Physical
PC card type............................................Type II
I/O connector ..........................................68-position VHDCI female
connector
Environment
Operating temperature ............................0 to 40 °C with a maximum
internal device temperature of
70 °C as measured by onboard
temperature sensor.
Storage temperature................................–20 to 70 °C
Relative humidity ...................................10 to 95% non-condensing
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B
Custom Cabling and Optional
Connectors
This appendix describes the various cabling and connector options for the
DAQCard-6024E, PCI-6023E, PCI-6024E, PCI-6025E, and PXI-6025E
devices.
Custom Cabling
National Instruments offers cables and accessories for you to prototype
your application or to use if you frequently change device interconnections.
If you want to develop your own cable, however, use the following
guidelines:
•
For the analog input signals, shielded twisted-pair wires for each
analog input pair yield the best results, assuming that you use
differential inputs. Tie the shield for each signal pair to the ground
reference at the source.
•
•
Route the analog lines separately from the digital lines.
When using a cable shield, use separate shields for the analog and
digital parts of the cable. Failure to do so results in noise coupling into
the analog signals from transient digital signals.
The following list gives recommended connectors that mate to the I/O
connector on your device.
♦
♦
PCI-6023E and PCI-6024E
Honda 68-position, solder cup, female connector
Honda backshell
DAQCard-6024E
Honda 68-Position, VHDCI
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Appendix B
Custom Cabling and Optional Connectors
♦
6025E
AMP 100-position IDC male connector
AMP backshell, 0.50 max O.D. cable
AMP backshell, 0.55 max O.D. cable
Mating connectors and a backshell kit for making custom 68-pin cables are
available from National Instruments.
Optional Connectors
The following table shows the optional connector and cable assembly
combinations you can use for each device.
Device
Connector
Cable Assembly
SH6868, R6868
SH6850, R6850
PCI-6023E/6024E
68-Pin E Series
50-Pin E Series
68-Pin E Series
50-Pin E Series
DAQCard-6024E
6025E
SHC68-68-EP, RC68-68
68M-50F adapter plus
SHC68-68-EP or RC68-68 cable
MIO-16 68-Pin, 68-Pin Extended
Digital Input
SH1006868
RI005050
50-Pin E Series, 50-Pin Extended
Digital Input
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Appendix B
Custom Cabling and Optional Connectors
Figure B-1 shows the pin assignments for the 68-Pin E Series connector.
34 68
ACH1 33 67
ACH8
ACH0
AIGND
ACH9
32 66
31 65
30 64
29 63
28 62
AIGND
ACH10
ACH3
ACH2
AIGND
ACH11
AISENSE
ACH12
ACH5
AIGND
ACH4
AIGND 27 61
ACH13 26 60
ACH6
AIGND 24 58
25 59
AIGND
ACH14
ACH7
ACH15
23 57
22 56
21 55
DAC0OUT1
DAC1OUT1
AIGND
AOGND
AOGND
DGND
DIO0
RESERVED 20 54
19 53
18 52
17 51
16 50
15 49
DIO4
DGND
DIO1
DIO5
DIO6
DGND
DIO2
DGND
+5 V 14 48
DGND 13 47
DGND 12 46
DIO7
DIO3
SCANCLK
PFI0/TRIG1
11 45
10 44
EXTSTROBE*
DGND
PFI1/TRIG2
DGND
9
8
7
6
5
4
3
2
1
43
42
41
40
39
38
37
36
35
PFI2/CONVERT*
PFI3/GPCTR1_SOURCE
PFI4/GPCTR1_GATE
GPCTR1_OUT
DGND
+5 V
DGND
PFI5/UPDATE*
PFI6/WFTRIG
DGND
PFI7/STARTSCAN
PFI8/GPCTR0_SOURCE
DGND
PFI9/GPCTR0_GATE
GPCTR0_OUT
FREQ_OUT
DGND
1 Not available on the 6023E
Figure B-1. 68-Pin E Series Connector Pin Assignments
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Appendix B
Custom Cabling and Optional Connectors
Figure B-2 shows the pin assignments for the 68-pin extended digital input
connector.
34 68
PC6 33 67
GND
PC7
GND
GND
PC4
GND
GND
PC1
GND
GND
PB6
32 66
31 65
30 64
29 63
28 62
PC5
GND
PC3
PC2
GND
PC0 27 61
PB7 26 60
GND
PB5 24 58
25 59
GND
GND
PB3
PB4
23 57
22 56
21 55
GND
GND
PB2
PB1 20 54
GND
GND
PA7
19 53
18 52
17 51
16 50
15 49
PB0
GND
PA6
GND
PA5
GND
PA4
GND
PA3 14 48
PA2 13 47
GND 12 46
GND
GND
PA1
GND
GND
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
PA0
+5 V
N/C
11 45
10 44
9
8
7
6
5
4
3
2
1
43
42
41
40
39
38
37
36
35
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
Figure B-2. 68-Pin Extended Digital Input Connector Pin Assignments
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Appendix B
Custom Cabling and Optional Connectors
Figure B-3 shows the pin assignments for the 50-pin E Series connector.
1
3
5
7
9
2
4
AIGND
ACH0
ACH1
AIGND
ACH8
ACH9
ACH10
ACH11
ACH12
ACH13
ACH14
6
8
ACH2
ACH3
10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
ACH4
ACH5
ACH6
ACH7
ACH15
DAC0OUT1
RESERVED
AISENSE
DAC1OUT1
AOGND
DIO0
DGND
DIO4
DIO1
DIO5
DIO2
DIO6
DIO3
DIO7
DGND
+5 V
+5 V 35 36
SCANCLK
PFI0/TRIG1
PFI2/CONVERT*
PFI4/GPCTR1_GATE
PFI5/UPDATE*
PFI7/STARTSCAN
PFI9/GPCTR0_GATE
FREQ_OUT
37 38
39 40
41 42
43 44
45 46
47 48
49 50
EXTSTROBE*
PFI1/TRIG2
PFI3/GPCTR1_SOURCE
GPCTR1_OUT
PFI6/WFTRIG
PFI8/GPCTR0_SOURCE
GPCTR0_OUT
1 Not available on the 6023E
Figure B-3. 50-Pin E Series Connector Pin Assignments
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Appendix B
Custom Cabling and Optional Connectors
Figure B-4 shows the pin assignments for the 50-pin extended digital input
connector.
1
3
5
7
9
2
4
PC7
PC6
PC5
PC4
PC3
GND
GND
GND
GND
GND
GND
GND
GND
6
8
10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
PC2
PC1
PC0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PA7
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PA6 35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50
PA5
PA4
PA3
PA2
PA1
PA0
+5 V
Figure B-4. 50-Pin Extended Digital Input Connector Pin Assignments
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C
Common Questions
This appendix contains a list of commonly asked questions and their
answers relating to usage and special features of your device.
General Information
What is the DAQ-STC?
The DAQ-STC is the system timing control application-specific integrated
circuit (ASIC) designed by National Instruments and is the backbone of the
E Series devices. The DAQ-STC contains seven 24-bit counters and three
16-bit counters. The counters are divided into the following three groups:
•
•
•
Analog input—two 24-bit, two 16-bit counters
Analog output—three 24-bit, one 16-bit counters
General-purpose counter/timer functions—two 24-bit counters
You can configure the groups independently with timing resolutions of
50 ns or 10 µs. With the DAQ-STC, you can interconnect a wide variety of
internal timing signals to other internal blocks. The interconnection scheme
is quite flexible and completely software configurable. New capabilities
such as buffered pulse generation, equivalent time sampling, and seamless
changing of the sampling rate are possible.
What does sampling rate mean to me?
It means that this is the fastest you can acquire data on your device and
still achieve accurate results. For example, these devices have a sampling
rate of 200 kS/s. This sampling rate is aggregate—one channel at 200 kS/s
or two channels at 100 kS/s per channel illustrates the relationship.
What type of 5 V protection do the devices have?
The PCI and PXI devices have 5 V lines equipped with a self-resetting
1 A fuse. The PCMCIA cards have 5 V lines equipped with a self-resetting
0.75 A fuse.
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Appendix C
Common Questions
Installation and Configuration
How do I set the base address for my device?
The base address of your device is assigned automatically through the
PCI/PXI bus protocol. This assignment is completely transparent to you.
What jumpers should I be aware of when configuring my E Series
device?
The E Series devices are jumperless and switchless.
Which National Instruments document should I read first to get
started using DAQ software?
Your NI-DAQ or application software release notes documentation is
always the best starting place.
What version of NI-DAQ must I have to use my 6023E/6024E/6025E?
You must have NI-DAQ for PC Compatibles version 6.5 or higher to use a
PCI a PXI device. To use the DAQCard-6024E you must have NI-DAQ for
PC compatibles version 6.9 or higher.
Analog Input and Output
I’m using my device in differential analog input mode and I have
connected a differential input signal, but my readings are random and
drift rapidly. What’s wrong?
a level that is considered floating with reference to the device ground
reference. Even if you are in differential mode, you must still reference the
signal to the same ground level as the board reference. There are various
methods of achieving this while maintaining a high common-mode
rejection ratio (CMRR). These methods are outlined in Chapter 4, Signal
Connections.
I’m using the DACs to generate a waveform, but I discovered with a
digital oscilloscope that there are glitches on the output signal. Is this
normal?
When it switches from one voltage to another, any DAC produces glitches
due to released charges. The largest glitches occur when the most
significant bit (MSB) of the D/A code switches. You can build a lowpass
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Appendix C
Common Questions
deglitching filter to remove some of these glitches, depending on the
frequency and nature of your output signal.
Can I synchronize a one-channel analog input data acquisition with a
one-channel analog output waveform generation on my PCI E Series
device?
Yes. One way to accomplish this is to use the waveform generation timing
pulses to control the analog input data acquisition. To do this, follow steps
1 through 4 below, in addition to the usual steps for data acquisition and
waveform generation configuration.
1. Enable the PFI5 line for output, as follows:
•
If you are using NI-DAQ, call
Select_Signal(deviceNumber,ND_PFI_5,
ND_OUT_UPDATE,ND_HIGH_TO_LOW).
•
If you are using LabVIEW, invoke the Route Signal VI with the
signal name set to PFI5 and the signal source set to AO Update.
2. Set up data acquisition timing so that the timing signal for A/D
conversion comes from PFI5, as follows:
•
If you are using NI-DAQ, call
Select_Signal(deviceNumber,ND_IN_CONVERT,
ND_PFI_5,ND_HIGH_TO_LOW).
•
If you are using LabVIEW, invoke AI Clock Config VI with clock
source code set to PFI pin, high to low, and clock source string set
to 5.
3. Initiate analog input data acquisition, which starts only when the
analog output waveform generation starts.
4. Initiate analog output waveform generation.
Timing and Digital I/O
What types of triggering can be hardware-implemented on my device?
Digital triggering is hardware-supported on every device.
Will the counter/timer applications that I wrote previously work with
the DAQ-STC?
using the CTR VIs will still run. However, there are many differences in the
counters between the E Series and other devices; the counter numbers are
different, timebase selections are different, and the DAQ-STC counters are
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Appendix C
Common Questions
24-bit counters (unlike the 16-bit counters on devices without the
DAQ-STC).
If you are using the NI-DAQ language interface or LabWindows/CVI, the
answer is no, the counter/timer applications that you wrote previously will
not work with the DAQ-STC. You must use the GPCTR functions; ICTR
and CTR functions will not work with the DAQ-STC. The GPCTR
functions have the same capabilities as the ICTR and CTR functions, plus
more, but you must rewrite the application with the GPCTR function calls.
I am using one of the general-purpose counter/timers on my device, but
I do not see the counter/timer output on the I/O connector. What am I
doing wrong?
If you are using the NI-DAQ language interface or LabWindows/CVI, you
must configure the output line to output the signal to the I/O connector. Use
the Select_Signalcall in NI-DAQ to configure the output line. By
default, all timing I/O lines except EXTSTROBE* are high impedance.
What are the PFIs and how do I configure these lines?
PFIs are programmable function inputs. These lines serve as connections to
virtually all internal timing signals. If you are using the NI-DAQ language
interface or LabWindows/CVI, use the Select_Signalfunction to route
internal signals to the I/O connector, route external signals to internal
timing sources, or tie internal timing signals together.
If you are using NI-DAQ with LabVIEW and you want to connect external
signal sources to the PFI lines, you can use AI Clock Config, AI Trigger
Config, AO Clock Config, AO Trigger and Gate Config, CTR Mode
Config, and CTR Pulse Config advanced level VIs to indicate which
function the connected signal serves. Use the Route Signal VI to enable the
PFI lines to output internal signals.
Caution If you enable a PFI line for output, do not connect any external signal source to it;
if you do, you can damage the device, the computer, and the connected equipment.
What are the power-on states of the PFI and DIO lines on the I/O
connector?
At system power-on and reset, both the PFI and DIO lines are set to high
impedance by the hardware. This means that the device circuitry is not
actively driving the output either high or low. However, these lines can have
pull-up or pull-down resistors connected to them as shown in Table 4-3, I/O
Signal Summary. These resistors weakly pull the output to either a logic
high or logic low state. For example, DIO(0) is in the high impedance state
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Common Questions
after power on, and Table 4-3, I/O Signal Summary, shows that there is a
50 kΩ pull-up resistor. This pull-up resistor sets the DIO(0) pin to a logic
high when the output is in a high impedance state.
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D
Technical Support Resources
Web Support
National Instruments Web support is your first stop for help in solving
installation, configuration, and application problems and questions. Online
problem-solving and diagnostic resources include frequently asked
questions, knowledge bases, product-specific troubleshooting wizards,
manuals, drivers, software updates, and more. Web support is available
through the Technical Support section of ni.com
NI Developer Zone
The NI Developer Zone at ni.com/zoneis the essential resource for
building measurement and automation systems. At the NI Developer Zone,
you can easily access the latest example programs, system configurators,
tutorials, technical news, as well as a community of developers ready to
share their own techniques.
Customer Education
National Instruments provides a number of alternatives to satisfy your
training needs, from self-paced tutorials, videos, and interactive CDs to
instructor-led hands-on courses at locations around the world. Visit the
Customer Education section of ni.comfor online course schedules,
syllabi, training centers, and class registration.
System Integration
If you have time constraints, limited in-house technical resources, or other
dilemmas, you may prefer to employ consulting or system integration
services. You can rely on the expertise available through our worldwide
network of Alliance Program members. To find out more about our
Alliance system integration solutions, visit the System Integration section
of ni.com
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Appendix D
Technical Support Resources
Worldwide Support
National Instruments has offices located around the world to help address
your support needs. You can access our branch office Web sites from the
Worldwide Offices section of ni.com. Branch office web sites provide
up-to-date contact information, support phone numbers, e-mail addresses,
and current events.
If you have searched the technical support resources on our Web site and
still cannot find the answers you need, contact your local office or National
Instruments corporate. Phone numbers for our worldwide offices are listed
at the front of this manual.
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Glossary
Prefix
p-
Meanings
pico-
Value
10–12
10–9
10– 6
10–3
103
n-
nano-
micro-
milli-
kilo-
µ-
m-
k-
M-
G-
t-
mega-
giga-
106
109
tera-
1012
Numbers/Symbols
°
degree
>
<
–
greater than
less than
negative of, or minus
ohm
Ω
/
per
%
percent
plus or minus
positive of, or plus
square root of
+
+5 V
+5 VDC source signal
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Glossary
A
A
amperes
AC
ACH
A/D
ADC
alternating current
analog input channel signal
analog-to-digital
analog-to-digital converter—an electronic device, often an integrated
circuit, that converts an analog voltage to a digital number
ADC resolution
the resolution of the ADC, which is measured in bits. An ADC with 16 bits
has a higher resolution, and thus a higher degree of accuracy, than a 12-bit
ADC.
AI
analog input
AIGATE
AIGND
AISENSE
ANSI
analog input gate signal
analog input ground signal
analog input sense signal
American National Standards Institute
analog output
AO
AOGND
ASIC
analog output ground signal
Application-Specific Integrated Circuit—a proprietary semiconductor
component designed and manufactured to perform a set of specific
functions for a specific customer
B
base address
a memory address that serves as the starting address for programmable
registers. All other addresses are located by adding to the base address.
bipolar
a voltage range spanning both negative and positive voltages
breakdown voltage
the voltage high enough to cause breakdown of optical isolation,
semiconductors, or dielectric materials. Also see working voltage.
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Glossary
bus
the group of conductors that interconnect individual circuitry in a computer.
Typically, a bus is the expansion interface to which I/O or other devices are
connected. Examples of PC buses are the ISA bus and PCI bus.
bus master
a type of a plug-in board or controller with the ability to read and write
devices on the computer bus
C
C
Celsius
channel
CH
channel
pin or wire lead to which you apply, or from which you read, an analog or
digital signal. Analog signals can be single-ended or differential. For digital
signals, channels are grouped to form ports.
CMRR
common-mode rejection ratio—a measure of the ability of a differential
amplifier to reject interference from a common-mode signal, usually
expressed in decibels (dB)
CONVERT*
counter/timer
crosstalk
convert signal
a circuit that counts external pulses or clock pulses (timing)
an unwanted signal on one channel due to an input on a different channel
counter
CTR
current drive
capability
the amount of current a digital or analog output channel is capable of
sourcing or sinking while still operating within voltage range specifications
D
D/A
digital-to-analog
DAC
D/A converter—an electronic device, often an integrated circuit, that
converts a digital number into a corresponding analog voltage or current
DAC0OUT
DAC1OUT
analog channel 0 output signal
analog channel 1 output signal
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Glossary
DAQ
data acquisition—(1) collecting and measuring electrical signals from
sensors, transducers, and test probes or fixtures and processing the
measurement data using a computer; (2) collecting and measuring the same
kinds of electrical signals with A/D and/or DIO boards plugged into a
computer, and possibly generating control signals with D/A and/or DIO
boards in the same computer
dB
decibel—the unit for expressing a logarithmic measure of the ratio of two
signal levels: dB=20log10 V1/V2, for signals in volts
DC
direct current
DGND
digital ground signal
differential input configuration
DIFF
differential amplifier
an amplifier with two input terminals, neither of which are tied to a ground
reference, whose voltage difference is amplified
differential input
DIO
the two-terminal input to a differential amplifier
digital input/output
dithering
DMA
the addition of Gaussian noise to an analog input signal
direct memory access—a method by which data can be transferred to/from
computer memory from/to a device or memory on the bus while the
processor does something else. DMA is the fastest method of transferring
data to/from computer memory.
DNL
differential nonlinearity—a measure in LSB of the worst-case deviation of
code widths from their ideal value of 1 LSB
DO
digital output
drivers/driver software
software that controls a specific hardware device such as a DAQ device
E
EEPROM
electrically erasable programmable read-only memory—ROM that can be
erased with an electrical signal and reprogrammed. Some SCXI modules
contain an EEPROM to store measurement-correction coefficients.
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Glossary
electrostatically coupled propagating a signal by means of a varying electric field
EXTSTROBE
external strobe signal
F
FIFO
first-in first-out memory buffer
floating signal sources
signal sources with voltage signals that are not connected to an absolute
reference or system ground. Also called nonreferenced signal sources.
Some common example of floating signal sources are batteries,
transformers, or thermocouples.
FREQ_OUT
ft
frequency output signal
feet
G
g
grams
gain
the factor by which a signal is amplified, sometimes expressed in decibels
gate signal
GATE
glitch
an unwanted momentary deviation from a desired signal
general purpose counter
GPCTR
GPCTR0_GATE
GPCTR0_OUT
GPCTR0_SOURCE
GPCTR0_UP_DOWN
GPCTR1_GATE
GPCTR1_OUT
GPCTR1_SOURCE
general purpose counter 0 gate signal
general purpose counter 0 output signal
general purpose counter 0 clock source signal
general purpose counter 0 up down
general purpose counter 1 gate signal
general purpose counter 1 output signal
general purpose counter 1 clock source signal
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Glossary
GPCTR1_UP_DOWN
GPIB
general purpose counter 1 up down
General Purpose Interface bus, synonymous with HP-IB. The standard bus
used for controlling electronic instruments with a computer. Also called
IEEE 488 bus because it is defined by ANSI/IEEE Standards 488-1978,
488.1-1987, and 488.2-1987.
grounded measurement See RSE.
system
H
h
hour
hex
Hz
hexadecimal
hertz—cycles per second of a periodic signal
I
INL
integral nonlinearity—a measure in LSB of the worst-case deviation from
the ideal A/D or D/A transfer characteristic of the analog I/O circuitry
input bias current
input impedance
the current that flows into the inputs of a circuit
the measured resistance and capacitance between the input terminals of a
circuit
input offset current
the difference in the input bias currents of the two inputs of an
instrumentation amplifier
instrumentation
amplifier
a very accurate differential amplifier with a high input impedance
interrupt
a computer signal indicating that the CPU should suspend its current task
to service a designated activity
I/O
input/output—the transfer of data to/from a computer system involving
communications channels, operator interface devices, and/or data
acquisition and control interfaces
IOH
current, output high
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Glossary
IOL
current, output low
interrupt request
IRQ
K
k
kilo—the standard metric prefix for 1,000, or 103, used with units of
measure such as volts, hertz, and meters
K
kilo—the prefix for 1,024, or 210, used with B in quantifying data or
computer memory
kS
1,000 samples
L
LabVIEW
laboratory virtual instrument engineering workbench
light-emitting diode
LED
library
a file containing compiled object modules, each comprised of one of more
functions, that can be linked to other object modules that make use of these
functions. NIDAQMSC.LIB is a library that contains NI-DAQ functions.
The NI-DAQ function set is broken down into object modules so that only
the object modules that are relevant to your application are linked in, while
those object modules that are not relevant are not linked.
linearity
LSB
the adherence of device response to the equation R = KS, where
R = response, S = stimulus, and K = a constant
least significant bit
M
MIO
multifunction I/O
most significant bit
MSB
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Glossary
N
NI-DAQ
National Instruments driver software for DAQ hardware
noise
an undesirable electrical signal—Noise comes from external sources such
as the AC power line, motors, generators, transformers, fluorescent lights,
soldering irons, CRT displays, computers, electrical storms, welders, radio
transmitters, and internal sources such as semiconductors, resistors, and
capacitors. Noise corrupts signals you are trying to send or receive.
NRSE
nonreferenced single-ended mode—all measurements are made with
respect to a common measurement system reference, but the voltage at this
reference can vary with respect to the measurement system ground
O
OUT
output pin—a counter output pin where the counter can generate various
TTL pulse waveforms
P
PCI
Peripheral Component Interconnect—a high-performance expansion bus
architecture originally developed by Intel to replace ISA and EISA. It is
achieving widespread acceptance as a standard for PCs and work-stations;
it offers a theoretical maximum transfer rate of 132 Mbytes/s.
PFI
programmable function input
PFI0/trigger 1
PFI0/TRIG1
PFI1/TRIG2
PFI2/CONVERT*
PFI1/trigger 2
PFI2/convert
PFI3/GPCTR1_
SOURCE
PFI3/general purpose counter 1 source
PFI4/GPCTR1_GATE
PFI4/general purpose counter 1 gate
PFI6/WFTRIG
PFI6/waveform trigger
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Glossary
PFI7/STARTSCAN
PFI7/start of scan
PFI8/GPCTR0_
SOURCE
PFI8/general purpose counter 0 source
PFI9/GPCTR0_GATE
PFI9/general purpose counter 0 gate
PGIA
port
programmable gain instrumentation amplifier
(1) a digital port consisting of multiple I/O lines on a DAQ device
(2) a serial or parallel interface connector on a PC
PPI
programmable peripheral interface
parts per million
ppm
pu
pullup
pulse trains
multiple pulses
Q
quantization error
the inherent uncertainty in digitizing an analog value due to the finite
resolution of the conversion process
R
referenced signal
sources
signal sources with voltage signals that are referenced to a system ground,
such as the earth or a building ground. Also called grounded signal sources.
resolution
the smallest signal increment that can be detected by a measurement
system. Resolution can be expressed in bits, in proportions, or in percent
of full scale. For example, a system has 12-bit resolution, one part in
4,096 resolution, and 0.0244% of full scale.
ribbon cable
rise time
a flat cable in which the conductors are side by side
the difference in time between the 10% and 90% points of a system’s step
response
rms
instantaneous signal amplitude; a measure of signal amplitude
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Glossary
RSE
referenced single-ended mode—all measurements are made with respect
to a common reference measurement system or a ground. Also called a
grounded measurement system.
RTSI bus
real-time system integration bus—the National Instruments timing bus that
connects DAQ devices directly, by means of connectors on top of the
devices, for precise synchronization of functions
S
s
seconds
samples
S
sample counter
the clock that counts the output of the channel clock, in other words, the
number of samples taken. On boards with simultaneous sampling, this
counter counts the output of the scan clock and hence the number of scans.
scan
one or more analog samples taken at the same time, or nearly the same time.
Typically, the number of input samples in a scan is equal to the number of
channels in the input group. For example, one scan, acquires one new
sample from every analog input channel in the group.
scan clock
scan rate
the clock controlling the time interval between scans.
the number of scans a system takes during a given time period, usually
expressed in scans per second
SCXI
SE
Signal Conditioning eXtensions for Instrumentation
single-ended—a term used to describe an analog input that is measured
with respect to a common ground
self-calibrating
a property of a DAQ board that has an extremely stable onboard reference
and calibrates its own A/D and D/A circuits without manual adjustments by
the user
sensor
a device that converts a physical phenomenon into an electrical signal
settling time
the amount of time required for a voltage to reach its final value within
specified accuracy limits
signal conditioning
the manipulation of signals to prepare them for digitizing
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Glossary
SISOURCE
SI counter clock signal
software trigger
software triggering
a programmed event that triggers an event such as data acquisition
a method of triggering in which you simulate an analog trigger using
software. Also called conditional retrieval.
SOURCE
S/s
source signal
samples per second—used to express the rate at which a DAQ board
samples an analog signal
STARTSCAN
STC
start scan signal
system timing controller
synchronous
(1) hardware—a property of an event that is synchronized to a reference
clock (2) software—a property of a function that begins an operation and
returns only when the operation is complete
T
TC
terminal count—the highest value of a counter
THD
THD+N
total harmonic distortion
signal-to-THD plus noise—the ratio in decibels of the overall rms signal to
the rms signal of harmonic distortion plus noise introduced
TRIG
trigger
TTL
trigger signal
any event that causes or starts some form of data capture
transistor-transistor logic
U
UI
update interval
unipolar
UISOURCE
a signal range that is always positive (for example, 0 to +10 V)
update interval counter clock signal
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Glossary
update
the output equivalent of a scan. One or more analog or digital output
samples. Typically, the number of output samples in an update is equal to
the number of channels in the output group. For example, one pulse from
the update clock produces one update which sends one new sample to every
analog output channel in the group.
update rate
the number of output updates per second
V
V
volts
Vcc
VDC
VI
positive supply voltage
volts direct current
virtual instrument—(1) a combination of hardware and/or software
elements, typically used with a PC, that has the functionality of a classic
stand-alone instrument (2) a LabVIEW software module (VI), which
consists of a front panel user interface and a block diagram program
VIH
VIL
Vin
volts, input high
volts, input low
volts in
Vm
measured voltage
volts, output high
volts, output low
reference voltage
volts, root mean square
VOH
VOL
Vref
Vrms
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Glossary
W
waveform
WFTRIG
working voltage
waveform generation trigger signal
the highest voltage that should be applied to a product in normal use,
normally well under the breakdown voltage for safety margin.
See also breakdown voltage.
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Index
AISENSE signal
description (table), 4-4
NRSE mode, 4-10
signal summary (table), 4-7
analog input
Numbers
+5 V signal
description (table), 4-4
self-resetting fuse, C-1
82C55A Programmable Peripheral Interface. See
PPI (Programmable Peripheral Interface).
6023E/6024E/6025E devices. See also hardware
overview; specifications.
available input configurations (table), 3-3
common questions, C-2 to C-3
dithering, 3-4 to 3-5
input modes, 3-2 to 3-3
input range, 3-3
block diagram, 3-1
features, 1-1 to 1-2
multichannel scanning
considerations, 3-5 to 3-6
optional equipment, 1-5 to 1-6
requirements for getting started, 1-2 to 1-3
software programming choices, 1-3 to 1-5
National Instruments application
software, 1-3 to 1-4
analog input signal connections, 4-8 to 4-19
common-mode signal rejection
considerations, 4-19
differential connections, 4-13 to 4-16
ground-referenced signal sources, 4-14
nonreferenced or floating signal
sources, 4-15 to 4-16
NI-DAQ driver software, 1-4 to 1-5
unpacking, 2-1
using PXI with CompactPCI, 1-2
exceeding common-mode input ranges
(caution), 4-10
PGIA (figure), 4-10
recommended input connections
(figure), 4-12
single-ended connection, 4-17 to 4-19
floating signal sources (RSE
configuration), 4-18
A
ACH<0..15> signal
description (table), 4-4
signal summary (table), 4-7
ACK* signal
description (table), 4-26
mode 1 output timing (figure), 4-28
mode 2 bidirectional timing (figure), 4-29
acquisition timing connections. See DAQ timing
connections.
grounded signal sources (NRSE
configuration), 4-18 to 4-19
summary of input connections (table), 4-12
types of signal sources, 4-8 to 4-9
floating signal sources, 4-9
ground-referenced signal sources, 4-9
analog input specifications
PCI and PXI buses, A-1 to A-4
accuracy information, A-2
amplifier characteristics, A-3
AIGATE signal, 4-39
AIGND signal
analog input mode, 4-10
description (table), 4-4
signal summary (table), 4-7
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dynamic characteristics, A-4
input characteristics, A-1 to A-2
stability, A-4
B
bipolar input, 3-3
block diagrams
transfer characteristics, A-3
PCMCIA bus, A-11 to A-14
accuracy information, A-12
amplifier characteristics, A-13
dynamic characteristics, A-13
input characteristics, A-11
stability, A-13 to A-14
6023E/6024E/6025E devices, 3-1
DAQCard-6024E, 3-2
C
cables. See also I/O connectors.
custom cabling, B-1 to B-2
field wiring considerations, 4-49
optional equipment, 1-5
transfer characteristics, A-12
analog output
analog output glitch, 3-6
calibration, 5-1 to 5-3
common questions, C-2 to C-3
overview, 3-6
adjusting gain error, 5-3
external calibration, 5-2
signal connections, 4-19 to 4-20
analog output specifications
PCI and PXI buses, A-4 to A-6
accuracy information, A-5
dynamic characteristics, A-6
output characteristics, A-4 to A-5
stability, A-6
loading calibration constants, 5-1 to 5-2
self-calibration, 5-2
specifications
PCI and PXI buses, A-9
PCMCIA bus, A-17
charge injection, 3-6
clocks, device and RTSI, 3-9
commonly asked questions. See questions and
answers.
transfer characteristics, A-5
voltage output, A-6
PCMCIA bus, A-14 to A-16
accuracy information, A-14
dynamic characteristics, A-15
output characteristics, A-14
stability, A-16
common-mode signal rejection
considerations, 4-19
CompactPCI products, using with PXI, 1-2
configuration
common questions, C-2
transfer characteristics, A-14 to A-15
voltage output, A-15
hardware configuration, 2-3
connectors. See I/O connectors.
conventions used in manual, xi-xii
CONVERT* signal
DAQ timing connections, 4-38 to 4-39
signal routing (figure), 3-8
custom cabling, B-1 to B-2
customer education, D-1
AOGND signal
analog output signal connections,
4-19 to 4-20
description (table), 4-4
signal summary (table), 4-7
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differential connections, 4-13 to 4-16
D
ground-referenced signal sources, 4-14
nonreferenced or floating signal
sources, 4-15 to 4-16
DAC0OUT signal
analog output signal connections,
4-19 to 4-20
when to use, 4-13
description (table), 4-4
signal summary (table), 4-7
DAC1OUT signal
digital I/O. See also PPI (Programmable
Peripheral Interface).
common questions, C-3 to C-5
overview, 3-7
analog output signal connections,
4-19 to 4-20
signal connections, 4-20 to 4-22
block diagram of digital I/O
connections (figure), 4-22
digital I/O connections (figure), 4-21
digital I/O specifications
PCI and PXI buses, A-7 to A-8
DIO<0..7>, A-7
description (table), 4-4
signal summary (table), 4-7
DAQ timing connections, 4-32 to 4-40
AIGATE signal, 4-39
CONVERT* signal, 4-38 to 4-39
EXTSTROBE* signal, 4-33 to 4-34
SCANCLK signal, 4-33
SISOURCE signal, 4-40
STARTSCAN signal, 4-36 to 4-38
TRIG1 signal, 4-34 to 4-35
TRIG2 signal, 4-35 to 4-36
typical posttriggered acquisition
(figure), 4-32
PA<0..7>, PB<0..7>, PC<0..7>, A-7
PCMCIA bus, A-16
DIO<0..7>, A-16
digital trigger specifications, A-9
DIO power-up state, changing to pulled
low, 4-24 to 4-25
DIO<0..7> signal
typical pretriggered acquisition
(figure), 4-33
description (table), 4-4
digital I/O signal connections,
4-20 to 4-21
DAQCard-6024E block diagram, 3-2
DAQ-STC, C-1
DATA signal
description (table), 4-26
mode 1 input timing (figure), 4-27
mode 1 output timing (figure), 4-28
mode 2 bidirectional timing (figure), 4-29
device and RTSI clocks, 3-9
DGND signal
digital I/O specifications, A-7
signal summary (table), 4-7
dithering, 3-4 to 3-5
documentation
conventions used in manual, xi-xii
related documentation, xii
description (table), 4-4
digital I/O signal connections,
4-20 to 4-21
E
EEPROM storage of calibration constants, 5-1
environment specifications
PCI and PXI buses, A-10
signal summary (table), 4-7
DIFF mode
PCMCIA bus, A-18
description (table), 3-3
recommended configuration
(figure), 4-12
environmental noise, 4-49
equipment, optional, 1-5 to 1-6
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Index
EXTSTROBE* signal
GPCTR0_OUT signal
DAQ timing connections, 4-33 to 4-34
description (table), 4-5
signal summary (table), 4-7
description (table), 4-6
general-purpose timing signal
connections, 4-45
signal summary (table), 4-8
GPCTR0_SOURCE signal, 4-43 to 4-44
GPCTR0_UP_DOWN signal, 4-45
GPCTR1_GATE signal, 4-46 to 4-47
GPCTR1_OUT signal
F
field wiring considerations, 4-49
floating signal sources
description, 4-9
description (table), 4-5
differential connections, 4-15 to 4-16
single-ended connections (RSE
configuration), 4-18
general-purpose timing signal
connections, 4-47
signal summary (table), 4-8
GPCTR1_SOURCE signal, 4-46
GPCTR1_UP_DOWN signal, 4-47 to 4-49
ground-referenced signal sources
description, 4-9
FREQ_OUT signal
description (table), 4-6
general-purpose timing signal
connections, 4-49
signal summary (table), 4-8
frequently asked questions. See questions and
answers.
differential connections, 4-14
single-ended connections (NRSE
configuration), 4-18 to 4-19
fuse, self-resetting, C-1
H
G
hardware
gain error, adjusting, 5-3
configuration, 2-3
general-purpose timing signal connections,
4-43 to 4-49
installation, 2-2 to 2-3
hardware overview
FREQ_OUT signal, 4-49
analog input, 3-2 to 3-6
dithering, 3-4 to 3-5
input modes, 3-2 to 3-3
input range, 3-3
analog output, 3-6
block diagram
6023E/6024E/6025E devices, 3-1
DAQCard-6024E, 3-2
digital I/O, 3-7
timing signal routing, 3-7 to 3-11
device and RTSI clocks, 3-9
programmable function
inputs, 3-8 to 3-9
GPCTR0_GATE signal, 4-44 to 4-45
GPCTR0_OUT signal, 4-45
GPCTR0_SOURCE signal, 4-43 to 4-44
GPCTR0_UP_DOWN signal, 4-45
GPCTR1_GATE signal, 4-46 to 4-47
GPCTR1_OUT signal, 4-47
GPCTR1_SOURCE signal, 4-46
GPCTR1_UP_DOWN signal,
4-47 to 4-49
glitch, analog output, 3-6
GPCTR0_GATE signal, 4-44 to 4-45
RTSI triggers, 3-9 to 3-11
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I
L
IBF signal
LabVIEW and LabWindows/CVI application
software, 1-3 to 1-4
description (table), 4-25
mode 1 input timing (figure), 4-27
mode 2 bidirectional timing (figure), 4-29
input modes, 3-2 to 3-3. See also analog input.
input range
M
manual. See documentation.
Measurement Studio software, 1-3 to 1-4
mode 1 input timing (figure), 4-27
mode 1 output timing (figure), 4-28
mode 2 bidirectional timing (figure), 4-29
multichannel scanning
exceeding common-mode input ranges
(caution), 4-10
measurement precision (table), 3-3
overview, 3-3
installation
considerations, 3-5 to 3-6
common questions, C-2
hardware, 2-2 to 2-3
software, 2-1
unpacking 6023E/6024E/6025E, 2-1
INTR signal
N
NI Developer Zone, D-1
NI-DAQ driver software, 1-4 to 1-5
noise, environmental, 4-49
NRSE (nonreferenced single-ended) mode
configuration, 4-9 to 4-10
description (table), 3-3
description (table), 4-26
mode 1 input timing (figure), 4-27
mode 1 output timing (figure), 4-28
mode 2 bidirectional timing (figure), 4-29
I/O connectors, 4-1 to 4-8
exceeding maximum ratings
(warning), 4-1
differential connections, 4-15 to 4-16
recommended configuration
(figure), 4-12
single-ended connections for
ground-referenced signal
I/O connector details (table), 4-1
optional connectors, B-2 to B-6
50-pin E Series connector pin
assignments (figure), B-5
50-pin extended digital input
connector pin assignments
(figure), B-6
sources, 4-18 to 4-19
O
OBF* signal
68-pin E Series connector pin
assignments (figure), B-3
68-pin extended digital input
connector pin assignments
(figure), B-4
description (table), 4-26
mode 1 output timing (figure), 4-28
mode 2 bidirectional timing (figure), 4-29
operating environment specifications
PCI and PXI buses, A-10
PCMCIA bus, A-18
optional equipment, 1-5 to 1-6
pin assignments (table)
6023E/6024E, 4-2
6025E, 4-3
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PFI7/STARTSCAN signal
description (table), 4-6
signal summary (table), 4-8
PFI8/GPCTR0_SOURCE signal
description (table), 4-6
signal summary (table), 4-8
PFI9/GPCTR0_GATE signal
description (table), 4-6
signal summary (table), 4-8
PFIs (programmable function inputs)
common questions, C-4 to C-5
signal routing, 3-8 to 3-9
timing connections, 4-31 to 4-32
PGIA (programmable gain instrumentation
amplifier)
P
PA<0..7> signal
description (table), 4-4
digital I/O specifications, A-7
signal summary (table), 4-7
PB<0..7> signal
description (table), 4-4
digital I/O specifications, A-7
signal summary (table), 4-7
PC<0..7> signal
description (table), 4-4
digital I/O specifications, A-7
signal summary (table), 4-7
PCI and PXI bus specifications. See
specifications.
PCMCIA bus specifications. See
specifications.
PFI0/TRIG1 signal
analog input modes, 4-9 to 4-11
differential connections
ground-referenced signal sources
(figure), 4-14
nonreferenced or floating signal
sources, 4-15 to 4-16
description (table), 4-5
signal summary (table), 4-7
PFI1/TRIG2 signal
single-ended connections
floating signal sources (figure), 4-18
ground-referenced signal sources
(figure), 4-19
description (table), 4-5
signal summary (table), 4-7
PFI2/CONVERT* signal
description (table), 4-5
signal summary (table), 4-7
PFI3/GPCTR1_SOURCE signal
description (table), 4-5
signal summary (table), 4-7
PFI4/GPCTR1_GATE signal
description (table), 4-5
signal summary (table), 4-8
PFI5/UPDATE signal
physical specifications
PCI and PXI buses, A-9 to A-10
PCMCIA bus, A-18
pin assignments
6023E/6024E (figure), 4-2
6025E (figure), 4-3
Port C pin assignments
description, 4-23
signal assignments (table), 4-23
posttriggered acquisition (figure), 4-32
power connections, 4-30
power requirement specifications
PCI and PXI buses, A-9
PCMCIA bus, A-17
description (table), 4-6
signal summary (table), 4-8
PFI6/WFTRIG signal
description (table), 4-6
signal summary (table), 4-8
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power-up state, digital I/O, 4-24 to 4-25
PPI (Programmable Peripheral Interface)
6025E only, 4-22 to 4-23
referenced single-ended input (RSE). See RSE
(referenced single-ended) mode.
requirements for getting started, 1-2 to 1-3
RSE (referenced single-ended) mode
configuration, 4-9 to 4-10
description (table), 3-3
changing DIO power-up state to pulled
low, 4-24 to 4-25
digital I/O connections block diagram
(figure), 4-22
mode 1 input timing (figure), 4-27
mode 1 output timing (figure), 4-28
mode 2 bidirectional timing (figure), 4-29
Port C pin assignments, 4-23
recommended configuration
(figure), 4-12
single-ended connections for floating
signal sources, 4-18
RTSI clocks, 3-9
RTSI trigger lines
power-up state, 4-24 to 4-25
overview, 3-9
signal names used in diagrams
(table), 4-25 to 4-26
signal connection
timing specifications, 4-25 to 4-29
pretriggered acquisition (figure), 4-33
programmable function inputs (PFIs). See
PFIs (programmable function inputs).
programmable gain instrumentation amplifier.
See PGIA (programmable gain
PCI devices (figure), 3-10
PXI devices (figure), 3-11
PXI E series devices (figure), 3-11
specifications, A-9
S
instrumentation amplifier).
Programmable Peripheral Interface (PPI). See
PPI (Programmable Peripheral Interface).
PXI products, using with CompactPCI, 1-2
sampling rate, C-1
SCANCLK signal
DAQ timing connections, 4-33
description (table), 4-5
signal summary (table), 4-7
scanning, multichannel, 3-5 to 3-6
settling time, in multichannel scanning, 3-6
signal connections
Q
questions and answers, C-1 to C-5
analog input and output, C-2 to C-3
general information, C-1
analog input, 4-8 to 4-19
common-mode signal rejection
considerations, 4-19
installation and configuration, C-2
timing and digital I/O, C-3 to C-5
differential connection
considerations, 4-13 to 4-16
input modes, 4-9 to 4-11
single-ended connection
considerations, 4-17 to 4-19
summary of input connections
(table), 4-12
R
RD* signal
description (table), 4-26
mode 1 input timing (figure), 4-27
mode 2 bidirectional timing (figure), 4-29
types of signal sources, 4-8 to 4-9
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analog output, 4-19 to 4-20
digital I/O, 4-20 to 4-22
field wiring considerations, 4-49
I/O connectors, 4-1 to 4-8
exceeding maximum ratings
(warning), 4-1
programmable function input
connections, 4-31 to 4-32
waveform generation timing
connections, 4-40 to 4-43
signal sources, 4-8 to 4-9
floating signal sources, 4-9
ground-referenced signal sources, 4-9
single-ended connections, 4-17 to 4-19
floating signal sources (RSE
configuration), 4-18
I/O connector details (table), 4-1
I/O connector signal descriptions
(table), 4-4 to 4-6
I/O signal summary (table),
4-7 to 4-8
grounded signal sources (NRSE
configuration), 4-18 to 4-19
when to use, 4-17
pin assignments (figure), 4-2 to 4-3
I/O connectors, optional, B-2 to B-6
50-pin E Series connector pin
assignments (figure), B-5
50-pin extended digital input
connector pin assignments
(figure), B-6
SISOURCE signal, 4-40
software installation, 2-1
software programming choices, 1-3 to 1-5
LabVIEW and LabWindows/CVI,
1-3 to 1-4
68-pin E Series connector pin
assignments (figure), B-3
68-pin extended digital input
connector pin assignments
(figure), B-4
Measurement Studio software, 1-3 to 1-4
National Instruments application
software, 1-3 to 1-4
NI-DAQ driver software, 1-4 to 1-5
VirtualBench, 1-4
power connections, 4-30
Programmable Peripheral Interface
6025E only, 4-22 to 4-23
mode 1 input timing (figure), 4-27
mode 1 output timing (figure), 4-28
mode 2 bidirectional timing
(figure), 4-29
specifications
PCI and PXI buses
analog input, A-1 to A-4
analog output, A-4 to A-6
calibration, A-9
digital I/O, A-7 to A-8
operating environment, A-10
physical, A-9 to A-10
power requirement, A-9
storage environment, A-10
timing I/O, A-8
Port C pin assignments, 4-23
power-up state, 4-24 to 4-25
signal names used in diagrams
(table), 4-25 to 4-26
timing specifications, 4-25 to 4-29
timing connections, 4-30 to 4-49
DAQ timing connections,
4-32 to 4-40
triggers, A-9
PCMCIA bus, A-11 to A-18
analog input, A-11 to A-14
analog output, A-14 to A-16
calibration, A-17
connections, 4-43 to 4-49
digital I/O, A-16
environment, A-18
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physical, A-18
GPCTR1_OUT signal, 4-47
GPCTR1_SOURCE signal, 4-46
GPCTR1_UP_DOWN
power requirements, A-17
timing I/O, A-16 to A-17
triggers, A-17
signal, 4-47 to 4-49
overview, 4-30
programmable function input
connections, 4-31 to 4-32
STARTSCAN signal, 4-36 to 4-38
STB* signal
description (table), 4-25
timing I/O connections (figure), 4-31
waveform generation timing
connections, 4-40 to 4-43
mode 1 input timing (figure), 4-27
mode 2 bidirectional timing (figure), 4-29
storage environment specifications, PCI and
PXI buses, A-10
system integration, by National
Instruments, D-1
UISOURCE signal, 4-42 to 4-43
UPDATE* signal, 4-41 to 4-42
WFTRIG signal, 4-40 to 4-41
timing I/O
common questions, C-3 to C-5
specifications
PCI and PXI buses, A-8
T
technical support resources, D-1
timing connections, 4-30 to 4-49
DAQ timing connections, 4-32 to 4-40
AIGATE signal, 4-39
PCMCIA bus, A-16 to A-17
timing signal routing, 3-7 to 3-11
CONVERT* signal routing (figure), 3-8
device and RTSI clocks, 3-9
programmable function inputs, 3-8 to 3-9
RTSI triggers, 3-9 to 3-11
CONVERT* signal, 4-38 to 4-39
EXTSTROBE* signal, 4-33 to 4-34
SCANCLK signal, 4-33
SISOURCE signal, 4-40
timing specifications, 4-25 to 4-29
mode 1 input timing (figure), 4-27
mode 1 output timing (figure), 4-28
mode 2 bidirectional timing (figure), 4-29
signal names used in diagrams
(table), 4-25 to 4-26
STARTSCAN signal, 4-36 to 4-38
TRIG1 signal, 4-34 to 4-35
TRIG2 signal, 4-35 to 4-36
typical posttriggered acquisition
(figure), 4-32
typical pretriggered acquisition
(figure), 4-33
general-purpose timing signal
connections, 4-43 to 4-49
TRIG1 signal, 4-34 to 4-35
TRIG2 signal, 4-35 to 4-36
trigger specifications
PCI and PXI buses
FREQ_OUT signal, 4-49
digital trigger, A-9
GPCTR0_GATE signal, 4-44 to 4-45
GPCTR0_OUT signal, 4-45
GPCTR0_SOURCE signal,
4-43 to 4-44
GPCTR0_UP_DOWN signal, 4-45
GPCTR1_GATE signal, 4-46 to 4-47
RTSI trigger, A-9
PCMCIA bus, A-17
digital trigger, A-17
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Index
waveform generation timing
connections, 4-40 to 4-43
U
UISOURCE signal, 4-42 to 4-43
unpacking 6023E/6024E/6025E, 2-1
UPDATE* signal, 4-41 to 4-42
UISOURCE signal, 4-42 to 4-43
UPDATE* signal, 4-41 to 4-42
WFTRIG signal, 4-40 to 4-41
Web support from National Instruments, D-1
WFTRIG signal, 4-40 to 4-41
Worldwide technical support, D-2
WR* signal
V
VCC signal (table), 4-7
VirtualBench software, 1-4
voltage output specifications
PCI and PXI buses, A-6
PCMCIA bus, A-15
description (table), 4-26
mode 1 output timing (figure), 4-28
mode 2 bidirectional timing (figure), 4-29
W
waveform generation, questions
about, C-2 to C-3
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