TFA9810
Stereo full-bridge audio amplifier 2 x 12 W
Rev. 03 — 20 February 2008
Product data sheet
1. General description
The TFA9810 is a two-channel power comparator for high-efficiency class D audio
amplifier systems. It contains two full-bridge Bridge-Tied Load (BTL) power stages, drive
logic, protection control logic and full differential input comparators. By using this power
comparator a compact closed-loop self-oscillating digital amplifier system or open-loop
system can be built. The TFA9810 does not require a heat sink and operates using an
asymmetrical supply voltage.
2. Features
I Stereo full-bridge power comparator for class D audio amplifier applications
I No external heat sink required
I Operating voltage range: asymmetrical from 8 V to 20 V
I Thermally protected
I Zero dead-time switching
I Current-limiting (no audible interruptions)
3. Applications
I Self-oscillating or open-loop class D audio amplifier applications
I Flat-panel television sets
I Flat-panel monitors
I Multimedia systems
I Wireless speakers
I High-end CRT television sets
4. Quick reference data
Table 1.
Quick reference data
Symbol
Parameter
Condition
Min
Typ
12
Max Unit
VP
Ioff
Iq
supply voltage
off-state current
quiescent current
VP = VDDPx − VSSPx
off mode
8
-
20
V
110
35
200
45
µA
mA
with load, filter and
snubbers connected
-
ηpo
output power
efficiency
output power
2 x 9 W into 8 Ω;
Po = Po(nom)
87
89
-
%
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TFA9810
NXP Semiconductors
Audio amplifier 2 x 12 W
6. Block diagram
TFA9810
27 BOOT1P
V
DDP1
25
DRIVER
HIGH
26 OUT1P
CONTROL
LOGIC
V
DDA1
4
DRIVER
LOW
V
SSP1
30
IN1P
IN1N
2
3
COMPARATOR 1
STABI1
29 BOOT1N
V
SSA1
5
V
DDP1
DRIVER
HIGH
10
DIAG
PROTECTION
28 OUT1N
CONTROL
LOGIC
OVP
UVP
OCP
OTP
ODP
WP
DRIVER
LOW
V
SSP1
31
11
6
TEST
STAB1
SO/OL
REFERENCE
22 BOOT2P
ENABLE
CDELAY
7
8
V
24
DDP2
DRIVER
HIGH
OUT2P
23
CONTROL
LOGIC
DRIVER
LOW
V
DDA2 13
V
19
20
SSP2
IN2P 15
IN2N 14
STABI2
COMPARATOR 2
BOOT2N
V
DDP2
V
SSA2
12
DRIVER
HIGH
OUT2N
STAB2
21
18
CONTROL
LOGIC
DRIVER
LOW
V
SSP2
HEATSPREADER
1
16 17
32
9
n.c.
010aaa016
V
SSD(HW)
Fig 1. Block diagram
TFA9810_3
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Audio amplifier 2 x 12 W
7. Pinning information
7.1 Pinning
1
2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
V
SSD(HW)
SSD(HW)
IN1P
STAB1
3
IN1N
V
SSP1
4
V
BOOT1N
OUT1N
BOOT1P
OUT1P
DDA1
5
V
SSA1
6
SO/OL
7
ENABLE
CDELAY
n.c.
8
V
V
DDP1
DDP2
TFA9810
SO32
9
10
11
12
13
14
15
16
DIAG
OUT2P
TEST
BOOT2P
OUT2N
BOOT2N
V
SSA2
V
DDA2
IN2N
V
SSP2
IN2P
STAB2
V
V
)
SSD(HW
SSD(HW)
010aaa017
Fig 2. Pin configuration
The SO32 package has four corner leads. These leads (1, 16, 17, and 32) are internally
connected to the die pad and must be connected to VSSA in the application. Together with
the applied copper area on the Printed Circuit Board (PCB) these leads determine the
ambient temperature, which affects the thermal resistance of the junction.
7.2 Pin description
Table 3.
Symbol
VSSD(HW)
Pin description
Pin
Description
1, 16, 17, Negative digital supply voltage and handle wafer
32
IN1P
2
Positive input comparator channel 1
IN1N
3
Negative input comparator channel 1
VDDA1
VSSA1
SO/OL
ENABLE
CDELAY
n.c.
4
Positive analog supply voltage channel 1
Negative analog supply voltage channel 1
SO/OL input enables self-oscillating / open-loop configuration
Enable input to switch between SLEEP and OPERATING
CDELAY input determines the switch on/off timing
Not connected
5
6
7
8
9
DIAG
10
11
12
13
Diagnostic output; open drain
TEST
VSSA2
VDDA2
Test signal input; for testing purposes only
Negative analog supply voltage channel 2
Positive analog supply voltage channel 2
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Audio amplifier 2 x 12 W
Table 3.
Pin description …continued
Description
Symbol
IN2N
Pin
14
15
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Negative input comparator channel 2
Positive input comparator channel 2
IN2P
STAB2
VSSP2
Decoupling of internal 11 V regulator for channel 2 drivers
Negative power-supply voltage channel 2
Bootstrap high-side driver negative output channel 2
Negative output channel 2
BOOT2N
OUT2N
BOOT2P
OUT2P
VDDP2
Bootstrap high-side driver positive output channel 2
Positive output channel 2
Positive supply voltage power channel 2
Positive power supply voltage channel 1
Positive output channel 1
VDDP1
OUT1P
BOOT1P
OUT1N
BOOT1N
VSSP1
Bootstrap high-side driver positive output channel 1
Negative output channel 1
Bootstrap high-side driver negative output channel 1
Negative supply voltage power channel 1
Decoupling of internal 11 V regulator for channel 1 drivers
STAB1
8. Functional description
8.1 General
The TFA9810 is a dual-switching power comparator. It is the main building block for a
stereo high-efficiency Class D audio power amplifier system. It contains two full-bridge
BTL power stages, drive logic, protection-control logic and full differential input
closed-loop self-oscillating digital amplifier system or open-loop system can be built. A
second-order low-pass filter converts the Pulse Width Modulation (PWM) output signal
into an analog audio signal across the speaker.
8.2 Interfacing
The pins ENABLE and SO/OL control the operating mode of the TFA9810. Both the
ENABLE and the SO/OL pins refer to VSSD(HW)
.
When the SO/OL pin is connected to VSSA the TFA9810 is in self-oscillating mode: when
the SO/OL pin is floating the TFA9810 is in open-loop mode.
The TEST pin needs to be connected to VDDA in both situations.
Table 4.
SO/OL connections
Interfacing
SO/OL connected to
VSSD(HW)
Configuration
Self-oscillating
Open-loop
Open
The device has two modes: SLEEP and OPERATING.
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Audio amplifier 2 x 12 W
In SLEEP mode the TFA9810 is not biased and has a very low supply current.
When the TFA9810 is set to OPERATING mode the device is started via the start-up
sequence, which provides a pop-free start-up behavior. After start-up the reference
voltages STAB are present and the outputs start switching.
Table 5.
Start-up
Interfacing
ENABLE [V]
Mode
ENABLE < 0.8 V
ENABLE > 3 V
SLEEP
OPERATING
8.3 Input comparators
The input stages have a differential input and are optimized for low noise and low offset.
This results in maximum flexibility in the application.
8.3.1 Operating in self-oscillating configuration
The inputs (IN1P, IN1N, IN2P, IN2N) of the comparators are internally set to a voltage level
of 0.5VP, but only during the start-up sequence. In operating mode the inputs are
high-ohmic.
8.3.2 Operating in open-loop configuration
No internal voltages are applied to the inputs. The input pins (IN1P, IN1N, IN2P, IN2N) are
pulled down to VSSA level by internal resistors.
8.4 Diagnostic
The DIAG output is an open-drain output. The maximum current is 2 mA. Whenever one
of the protections is triggered the DIAG output is activated low. The DIAG output refers to
VSSD
.
8.5 Protections
Overtemperature, overcurrent, overvoltage, undervoltage, overdissipation sensors, and
window protection are included in the TFA9810. When one of these sensors exceeds its
threshold level either the output power stage is switched off and the outputs (OUT1N,
OUT1P, OUT2N, OUT2P) become floating, or the TFA9810 shuts down and starts up
immediately.
• OverTemperature Protection (OTP)
If the junction temperature (Tj) exceeds a threshold level of about 150 °C then the
outputs become floating. The device will start switching again after 5 µs and when the
temperature is below 150 °C. This is thermal limitation without audible interruptions.
• OverCurrent Protection (OCP)
If the output current exceeds the maximum output current threshold level the output
becomes floating. The device will start switching again after 5 µs. This is current
limitation without audible interruptions.
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Audio amplifier 2 x 12 W
• OverVoltage Protection (OVP)
When the supply voltage applied to the TFA9810 exceeds the maximum supply
voltage threshold level the device will shut down. The device will restart when the
supply voltage is within the operating range.
• UnderVoltage Protection (UVP)
When the supply voltage applied to the TFA9810 falls below the minimum supply
voltage threshold level the device will shut down. The device will restart when the
supply voltage is within the operating range.
• OverDissipation Protection (ODP)
The ODP in the TFA9810 is a combination of two protections. Exceeding a
temperature threshold level of 135 °C an internal pre-warning is generated. When an
overcurrent is detected during the pre-warning the device will shut down. When the
ENABLE pin is high the TFA9810 will restart automatically. The restart sequence
(switch-off → switch-on) will take 200 ms to 500 ms.
• Window Protection (WP)
During start-up, if one of the outputs is shorted to VSS or VDD the device will not start.
This is an effective measure to protect the device against shorts between the outputs
(before the filter) and the ground or supply lines. The supply must be switched off prior
to removing any short. The WP protects the device against failure during board
assembly.
Table 6.
Overview protections
Protections
Symbol
OTP
Condition
Tj > 150 °C
IO > IORM
VP > 20 V
VP < 8 V
DIAG
LOW
LOW
LOW
LOW
Outputs
Floating
Floating
Floating
Floating
Floating
Recovering
Automatic, after 5 µs and Tj < 150 °C
Automatic, after 5 µs and IO < IORM
Restart (switch-off → switch-on when VP < 20 V)
Restart (switch-off → switch-on when VP > 8 V)
Restart (switch-off → switch-on when
OCP
OVP
UVP
ODP
Tj > 135 °C and IO > IORM LOW
Tj < 135 °C or IO < IORM
)
WP
OUTX > VDDA - 1 V or
OUTX < VSSA + 1 V
LOW
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Audio amplifier 2 x 12 W
8.6 Start-up sequence
V
P
ENABLE
STAB1
CDELAY
V IN x
FLOATING
FLOATING
PWM
PWM
OUT x
AUDIO
AUDIO
AUDIO
DIAG
SLEEP
START-UP
OPERATING
FAULT RESTART
OPERATING
SHUT-DOWN
SLEEP
010aaa018
Fig 3. Start-up sequence
9. Internal circuitry
1,16, 17, 32
V
DDA
22 V
V
SSA
010aaa024
Fig 4. Internal circuitry 0001
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NXP Semiconductors
Audio amplifier 2 x 12 W
V
DDA1
2
135 kΩ
5.5 V
V
SSA
hvp
135 kΩ
5.5 V
3
V
SSA1
010aaa025
Fig 5. Internal circuitry 0002
4
5
22 V
010aaa026
Fig 6. Internal circuitry 0003
V
DDA1
V
DDA1
50 µA
110 kΩ
6
V
SSA1
V
SSA
010aaa027
Fig 7. Internal circuitry 0004
TFA9810_3
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NXP Semiconductors
Audio amplifier 2 x 12 W
V
DDA1
3 kΩ
7
250 nA
V
SSA
010aaa028
Fig 8. Internal circuitry 0005
V
DDA1
2 nA
8
200 nA
5 kΩ
DISCHARGE
V
SSA1
010aaa029
Fig 9. Internal circuitry 0006
V
DDA1
10
V
V
SSA1
SSD
010aaa030
Fig 10. Internal circuitry 0007
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NXP Semiconductors
Audio amplifier 2 x 12 W
V
DDA1
11
13 kΩ
V
SSA1
010aaa031
Fig 11. Internal circuitry 0008
Fig 12. Internal circuitry 0009
V
DDA2
14
5.5 V
130 kΩ
hvp
V
SSA2
130 kΩ
5.5 V
15
V
SSA2
010aaa033
Fig 13. Internal circuitry 0010
V
DDA2
100 mA
18
12 V
V
SSD
010aaa034
Fig 14. Internal circuitry 0011
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NXP Semiconductors
Audio amplifier 2 x 12 W
24
19
23.5 V
010aaa035
Fig 15. Internal circuitry 0012
20
12 V
OUT2N
010aaa036
Fig 16. Internal circuitry 0013
V
DDP2
21
V
SSP2
010aaa037
Fig 17. Internal circuitry 0014
22
12 V
OUT2P
010aaa038
Fig 18. Internal circuitry 0015
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Audio amplifier 2 x 12 W
V
DDP2
23
V
SSP2
010aaa039
Fig 19. Internal circuitry 0016
25
23.5 V
30
010aaa040
Fig 20. Internal circuitry 0017
V
DDP1
26
V
SSP1
010aaa041
Fig 21. Internal circuitry 0018
Fig 22. Internal circuitry 0019
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NXP Semiconductors
Audio amplifier 2 x 12 W
V
DDP1
28
V
SSP1
010aaa043
Fig 23. Internal circuitry 0020
29
12 V
OUT1N
010aaa044
Fig 24. Internal circuitry 0021
V
DDA1
100 mA
31
12 V
V
SSD
010aaa045
Fig 25. Internal circuitry 0022
10. Limiting values
Table 7.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min
Max
+23
-
Unit
V
VP
supply voltage
asymmetrical −0.3
IORM
Tj
repetitive peak output current
junction temperature
storage temperature
ambient temperature
maximum power dissipation
3
A
-
+150
+150
+85
2.5
°C
°C
°C
W
Tstg
Tamb
Pmax
−55
−40
-
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Audio amplifier 2 x 12 W
Table 7.
Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
DIAG
Min
Max
Unit
V
Vx
voltage on pin x
VSS − 0.3
−12
+12
IN1P - IN1N
IN2P - IN2N
all other pins
+12
V
−12
+12
V
VSS − 0.3
−1500
VDD + 0.3
+1500
V
Vesd
electrostatic discharge voltage
VINX with
respect to
other pins
V
all other pins
−2000
+2000
V
11. Thermal characteristics
Table 8.
Symbol
Rth(j-a)
Characteristics
Parameter
Conditions
Min
Typ
41
Max
44
-
Unit
K/W
K/W
thermal resistance
from junction to
ambient
SO32. JEDEC test board
-
SO32. Two-layer application
board
-
44
Ψj-lead
thermal
SO32
30
K/W
characterization
parameter from
junction to lead
Ψj-top
thermal
SO32
4
8
K/W
characterization
parameter from
junction to top of
package
[1] Measured in a JEDEC high K-factor test board (standard EIA/JESD 51-7) in free air with natural convection.
[2] Strongly depends on where the measurement is taken on the case.
12. Characteristics
12.1 Static characteristics
Table 9.
Static characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Supply voltage
VP
Ioff
Iq
supply voltage
VP = VDDPx − VSSPx
8
-
12
20
V
off-state current
quiescent current
off mode
110
35
200
45
µA
mA
with load, filter, and snubbers
connected
-
ENABLE input
VIL
VIH
LOW-level input voltage with respect to VSSD
HIGH-level input voltage with respect to VSSD
−0.3
-
-
+0.8
VP
V
V
3
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Audio amplifier 2 x 12 W
Table 9.
Static characteristics …continued
Tamb = 25 °C; VP = 12 V; fosc = 550 kHz; Figure 33 unless otherwise specified
Symbol
II
Parameter
Conditions
Min
Typ
Max
Unit
input current
VI = 5 V
-
1
20
µA
SO/OL input
VIL
LOW-level input voltage with respect to VSSD
HIGH-level input voltage with respect to VSSD
-
-
0.4
4.5
V
V
VIH
3
4
STABI
VSTABI
voltage on pin STABI
with respect to VSS
10
11
12
V
Comparator full-differential input stage
Voffset(i)(eq) equivalent input offset
voltage
-
-
-
-
-
1
mV
µV
V
20 Hz < f < 20 kHz
-
15
Vcm
IIB
common mode voltage
input bias current
VSSA + 3
-
VDDA −1
1
µA
OverTemperature Protection (OTP)
Tprot protection temperature
OverVoltage Protection (OVP)
150
20
-
-
°C
Vth(ovp)
overvoltage protection
threshold voltage
level internal fixed
21.5
23
V
UnderVoltage Protection (UVP)
VP(uvp)
undervoltage protection level internal fixed
supply voltage
7
3
7.5
3.5
8
-
V
A
OverCurrent Protection (OCP)
IO(ocp)
overcurrent protection
output current
Window Protection (WP)
VO output voltage
high level
low level
-
-
VDDA − 1
-
-
V
V
VSSA + 1
[1] Current limiting concept: in overcurrent condition no interruption of the audio signal in case of impedance drop.
12.2 Dynamic characteristics
Table 10. Dynamic characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
PWM output
tr
tf
rise time
fall time
-
-
10
10
-
-
ns
ns
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Audio amplifier 2 x 12 W
Table 10. Dynamic characteristics …continued
Tamb = 25 °C; VP = 12 V; RL = 8 Ω; Figure 33 unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
60
Max
Unit
ns
tresp
response time
transition PWM output from
LOW to HIGH
-
-
-
-
50
ns
VI = 70 mV
VI = 3.3 V
transition PWM output from
HIGH to LOW
-
-
60
50
-
-
ns
ns
VI = 70 mV
VI = 3.3 V
tw(min)
RDSon
minimum pulse width PWM output
-
-
60
-
ns
drain-source on-state
resistance
0.28
0.35
Ω
ηpo
output power
efficiency
output power 2 x 9 W into 8 Ω.
Po = Po(nom)
87
89
-
%
[1] High-side and low-side power switch have the same series resistance.
[2] Output power measured across the loudspeaker load. Output power is measured indirectly via RDSon
.
12.3 AC characteristics measured in a typical application
Table 11. AC characteristics measured in typical application
Symbol
VP
Parameter
Conditions
Min
Typ
12
Max
20
-
Unit
V
supply voltage
RMS output power
VP = VDDPx − VSSPx
8
-
Po(RMS)
RL = 8 Ω; VP = 12 V;
9.5
W
THD = 10 %; Two channel
driven; no heat sink required.
Po
output power
VP = 12 V; RL = 8 Ω
THD = 10 %
8.5
6.5
-
9.5
7.5
12
-
-
-
W
W
W
THD = 1 %
VP = 14 V; RL = 8 Ω;
THD = 10 %; thermally limited
VP = 16 V; RL = 8 Ω;
-
15
-
W
W
W
%
THD = 10 %; thermally limited
VP = 12 V; RL = 6 Ω;
THD = 10 %; thermally limited
-
12
-
VP = 12 V; RL = 4 Ω;
THD = 10 %; thermally limited
-
15
-
THD+N
ηpo
total harmonic
distortion-plus-noise
Po is 1 W; f = 1 kHz; AES17
brick-wall filter
-
0.04
89
0.1
-
output power
efficiency
Po = 9 W
87
19
-
%
Gv(cl)
Vn(o)
closed-loop voltage
gain
VI = 100 mV (RMS); fi = 1 kHz
19.7
150
21
-
dB
µV
output noise voltage
Inputs shorted;
AES17 brick-wall filter
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Audio amplifier 2 x 12 W
Table 11. AC characteristics measured in typical application …continued
Tamb = 25 °C; VP = 12 V; RL = 8 Ω; fosc = 550 kHz; Figure 33 unless otherwise specified.
Symbol
S/N
Parameter
Conditions
Min
-
Typ
96
Max
Unit
dB
signal-to-noise ratio
Vo = 10 V (RMS); gain 20 dB
-
-
SVRR
supply voltage ripple Vripple = 2 V(p-p); fi= 1 kHz
rejection
34
45
dB
αcs
channel separation
Po = 1 W; fi = 1 kHz
55
70
-
dB
[1] Minimum value determined by R5, R10, R17, R22 equalling +1 % and R7, R14, R18, R20 equalling −1 %.
13. Quality specification
In accordance with SNW-FQ-611-E, ‘if this type is used as an audio amplifier’. The
number of the quality specification can be found in the Quality Reference Handbook. The
handbook can be ordered using the code 9398 510 63011.
14. Application information
14.1 Output power estimation
For BTL configuration the output power just before clipping can be estimated using
2
RL
× VP
-----------------------------------------------------
RL + 2 × (RDSon + Rs)
--------------------------------------------------------------------------------
2 × RL
BTL : Po0.5 %
=
(1)
Where,
• VP = supply voltage (VDDPx − VSSPx) [V]
• RL = load resistance [Ω]
• RDSon = drain-source on-state resistance [Ω]
• Rs = series resistance [Ω]
• Po0.5 % = output power at the THD level of 0.5 % [W]
P
= 1.25 × Po0.5 %
(2)
o10 %
THD = 10 % as a function of the BLT supply voltage for different load impedances.
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Audio amplifier 2 x 12 W
010aaa019
(3)
25
20
15
10
5
P
(W)
o
(2)
(1)
0
8
12
16
20
V
(V)
P
(1) RL = 4 Ω
(2) RL = 6 Ω
(3) RL = 8 Ω
Fig 26. BTL output power as function of supply voltage: THD = 0.5 %. 3 A
010aaa020
30
(3)
P
o
(W)
(2)
20
(1)
10
0
8
12
16
20
V
(V)
P
(1) RL = 4 Ω
(2) RL = 6 Ω
(3) RL = 8 Ω
Fig 27. BTL output power as function of supply voltage: THD = 10 %. 3 A
14.2 Output current limiting
The peak output current is internally limited above a level of 3 A minimum. During normal
operation the output current should not exceed this threshold level of 3 A, otherwise the
output signal will be distorted. The peak output current in BTL can be estimated using
VP
I max ≤
≤3 A
(3)
-----------------------------------------------------
O
RL + 2 × (RDSon + Rs)
Where:
• VP = supply voltage (VDDPx − VSSPx) [V].
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Audio amplifier 2 x 12 W
• RL = load resistance [Ω].
• RDSon = drain-source on-state resistance [Ω].
• Rs = series resistance [Ω].
Example:
A 4 Ω speaker in BTL configuration can be used up to a supply voltage of 12 V without
running into current limiting. Current limiting (clipping) will avoid audio holes, but it causes
a sound distortion similar to voltage clipping.
14.3 Speaker configuration and impedance
For a flat-frequency response (second-order Butterworth filter) it is necessary to change
the low-pass filter components LLC and CLC according to the speaker configuration and
Table 12. Filter component values
Configuration
Impedance [Ω]
LLC [µF]
10
CLC [nF]
1500
BTL
4
6
8
16
1000
22
680
14.4 Differential input
For a high common-mode rejection ratio and a maximum of flexibility in the application,
the audio inputs of the application are fully differential.
OUT1P
+
IN1P
AUDIO
DSP
IN1N
−
V
SS
OUT1N
010aaa021
Fig 28. Input configuration for differential input
14.5 Single-ended input
When using an audio source with a single-ended ‘out’, it is important to connect the IN1N
from the application board to the VSS/GND of the audio source (e.g. Audio DSP).
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Audio amplifier 2 x 12 W
OUT1P
+
IN1P
IN1N
AUDIO
DSP
−
OUT1N
010aaa022
Fig 29. Input configuration for single-ended input
14.6 Curves measured in a typical application
010aaa197
+30
G
v
(dB)
+25
+20
+15
+10
(1)
(2)
−2
−1
2
10
10
1
10
10
f (Hz)
i
VP = 12 V, Vi = 100 mV
(1) OUT1
(2) OUT2
Fig 30. Gain as a function of frequency
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Audio amplifier 2 x 12 W
010aaa195
10
THD+N
(%)
1
−1
10
(2)
(1)
−2
10
2
3
4
5
10
10
10
10
10
f (Hz)
i
VP = 12 V, RL = 8 Ω, Po = 1 W
(1) OUT1
(2) OUT2
Fig 31. Total harmonic distortion + noise as a function of frequency
010aaa196
10
THD+N
(%)
1
−1
10
(1)
(2)
−2
10
10
−2
−1
10
1
10
P
(W)
o
VP = 12 V, RL = 8 Ω, fi = 1 kHz
(1) OUT1
(2) OUT2
Fig 32. Total harmonic distortion as a function of output power
14.7 Typical application diagram TFA9810
The typical application diagram with the TFA9810 supplied from an asymmetrical supply is
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1
12 V
12 V
12 V
VP J1
L1
BEAD
L2
BEAD
C2
220 µF
R3
10 Ω
C32
220 µF
C33
100 nF
C1
220 µF
2
SW1
C3
100 nF
C31
100 nF
ENABLE
GND
GND
C4
100 nF
C5
100 nF
OUT1−
GND
GND
GND
V
V
V
V
DDP2
n.c DDP1
DDA1
DDA2
R5
100 kΩ
4
2
13
9 25 24
L3
22 µH
C6
1 µF
OUT1+
R7
R6
R31
OUT1P
IN1P
IN1N
2
1
26
J3
10 kΩ
10 kΩ
10 kΩ
C9
220 nF
2
C8
IN1
J2
220 pF
C27
470 pF
C12
BOOT1P
BOOT1N
C11
47 pF
R27
10 Ω
27
29
680 nF
C10
220 pF
C7
1 µF
GND
R10
R11
R32
10 kΩ
3
GND
GND
C13
R28
10 Ω
C28
470 pF
10 kΩ
10 kΩ
680 nF
C14
J4
R14
100 kΩ
220 nF
C15
330 nF
1
OUT1N
STABI1
28
31
18
CDELAY
SO/OL
L4
22 µH
OUT1
8
6
OUT1−
GND
OUT1+
C16
Snubber network
(Optional)
1µF
GND
TFA9810
GND
STABI2
ENABLE
DIAG
7
C17
OUT2−
1µF
OUT2+
10
L5
GND
22 µH
V
2
OUT2P
11, TEST
DDA2
23
22
20
R17
J6
C19
220 nF
100 kΩ
C18
C20
680 nF
C29
470 pF
R29
10 Ω
BOOT2P
BOOT2N
1 µF
R18
R19
R33
IN2P
IN2N
1
15
10 kΩ
10 kΩ
10 kΩ
C21
2
IN2
J5
220 pF
GND
GND
C22
68 pF
R30
10 Ω
C23
680 nF
C30
470 pF
C24
220 pF
C25
220 nF
C26
1 µF
GND
R22
R23
R34
10 kΩ
OUT2N
1
14
21
OUT2
10 kΩ
10 kΩ
L6
22 µH
OUT2−
5
12
1
16
17 32
30 19
J7
R26
100 kΩ
R100
22 Ω
GND
V
V
V
V
V
V
V
V
SSA1
SSA2 SSD SSD SSD SSD SSP1 SSP2
OUT2+
010aaa023
GND
Fig 33. Typical application diagram TFA9810
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1
12 V
12 V
12 V
VP J1
L1
BEAD
L2
BEAD
C2
220 µF
R3
10 Ω
C32
220 µF
C33
100 nF
C1
220 µF
2
SW1
C3
100 nF
C31
100 nF
ENABLE
GND
GND
C4
100 nF
C5
100 nF
OUT1−
GND
GND
GND
V
V
V
V
DDP2
n.c DDP1
DDA1
DDA2
R5
100 kΩ
4
2
13
9 25 24
L3
22 µH
C6
1 µF
OUT1+
R7
R6
R31
OUT1P
IN1P
IN1N
2
1
26
J3
10 kΩ
10 kΩ
10 kΩ
C9
220 nF
2
C8
IN1
J2
220 pF
C27
470 pF
C12
680 nF
BOOT1P
BOOT1N
C11
47 pF
R27
10 Ω
27
29
C10
220 pF
C7
1 µF
GND
R10
R11
R32
10 kΩ
3
GND
GND
C13
680 nF
R28
10 Ω
C28
470 pF
10 kΩ
10 kΩ
C14
220 nF
J4
STAB1
R14
100 kΩ
1
OUT1N
STAB1
R35
200 kΩ
CDELAY
28
31
18
C15
4.7 µF
L4
22 µH
OUT1
OUT1−
GND
8
6
OUT1+
C16
1µF
SO/OL
Snubber network
(Optional)
GND
TFA9810
STAB2
ENABLE
DIAG
7
GND
C17
1µF
OUT2+
OUT2−
10
11
L5
22 µH
GND
V
2
OUT2P
DDA2
23
22
20
R17
100 kΩ
J6
C19
220 nF
C18
1 µF
C20
680 nF
C29
470 pF
R29
10 Ω
BOOT2P
BOOT2N
R18
R19
10 kΩ
R33
IN2P
IN2N
1
15
10 kΩ
10 kΩ
C21
2
IN2
J5
220 pF
GND
GND
C22
68 pF
R30
10 Ω
C23
680 nF
C30
470 pF
C24
220 pF
C25
220 nF
C26
1 µF
GND
R22
R23
R34
10 kΩ
OUT2N
1
14
5
21
OUT2
10 kΩ
10 kΩ
L6
22 µH
OUT2−
12
V
1
16
17 32
30 19
J7
R26
100 kΩ
R100
22 Ω
GND
V
V
V
V
V
V
V
SSA1
SSA2 SSD SSD SSD SSD SSP1 SSP2
OUT2+
010aaa431
GND
Fig 34. Typical application diagram TFA9810 with externally adjusted switch-on time
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Audio amplifier 2 x 12 W
14.8 Typical application: bill of materials
Table 13. Typical application: bill of materials
Item
1
Quantity
Reference
C1, C2.
Part
Description
2
5
2
4
4
4
1
4
1
1
1
3
2
2
2
220 µF/35 V
100 nF/50 V
1 µF/50 V
1 µF/25 V
220 pF/25 V
220 nF/25 V
47 pF/25 V
680 nF/25 V
330 nF/25 V
68 pF/25 V
1000 µF/25 V
Screw terminal
CINCH
General purpose 85 °C, diameter 8 mm
SMD 0805 X7R
SMD 1206 X7R
MKT
2
C3, C4, C5, C31, C33.
C16, C17.
C6, C7, C18, C26
C8, C10, C21, C24.
C9, C14, C19, C25.
C11
3
4
5
SMD 0402 NP0
SMD 0805 X7R
SMD 0402 NP0
MKT
6
7
8
C12, C13, C20, C23.
C15
9
SMD 0805 X7R
SMD 0402 NP0
CE12-02R
10
11
12
13
14
15
C22.
C32
J1, J3, J6.
J2, J5.
Two pins
CINCH
J4, J7
Jumper
Closed on demo board only
L1, L2.
BEAD
SMD 1206 Würth Elektronik
DC < 0.5 Ω 10 MHz > 80 Ω
16
4
L3, L4, L5, L6.
22 µH
8RDY TOKO A7040HN-220M,
11RHBP TOKO A7503CY-220M or Sagami
7311NA-220M
17
18
5
4
R3
10 / 0.25 W / 5 %
SMD 1206
SMD 0603
R5, R14, R17, R26.
100 k / 0.1 W /
1 % for 20 dB
200 k / 0.1 W /
1 % for 26 dB
19
12
R6, R7, R10, R11, R18,
R19, R22, R23, R31, R32,
R33, R34.
10 k / 0.1 W / 1 %
SMD 0603
20
21
1
1
SW1
U1
PCB switch
TFA9810T
Secme 090320901
SOT287-1 (SO32) NXP Semiconductors
14.9 Snubber network
Table 14. Snubber network: bill of materials
Item Quantity Reference Part
Footprint
1
2
4
4
C27, C28, C29, C30 470 pF, 25 V SMD 0805 X7R
R27, R28, R29, R30 10 / 0.25 W / SMD 1206
5 %
15. Test information
General Quality Specification for General Applications, Power management and
RF Power. Document SNW-FQ-611 refers.
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Audio amplifier 2 x 12 W
16. Package outline
SO32: plastic small outline package; 32 leads; body width 7.5 mm
SOT287-1
D
E
A
X
c
y
H
v
M
A
E
Z
17
32
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
16
1
w M
detail X
b
p
e
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
E
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
max.
0.3
0.1
2.45
2.25
0.49
0.36
0.27 20.7
0.18 20.3
7.6
7.4
10.65
10.00
1.1
0.4
1.2
1.0
0.95
0.55
mm
2.65
0.25
0.01
1.27
0.05
1.4
0.25
0.01
0.25
0.01
0.1
8o
0o
0.012 0.096
0.004 0.089
0.02 0.011 0.81
0.01 0.007 0.80
0.30
0.29
0.419
0.394
0.043 0.047
0.016 0.039
0.037
0.022
inches
0.1
0.004
0.055
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
00-08-17
03-02-19
SOT287-1
MO-119
Fig 35. Package outline SOT287-1 (SO23)
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Audio amplifier 2 x 12 W
17. Revision history
Table 15. Revision history
Document ID
TFA9810_3
Release date
20080220
Data sheet status
Change notice
Supersedes
Product data sheet
-
TFA9810_2
Modifications:
TFA9810_2
TFA9810_1
20070831
Preliminary data sheet
-
-
TFA9810_1
-
20070815
Preliminary data sheet
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Audio amplifier 2 x 12 W
18. Legal information
18.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
18.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
18.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
18.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
19. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
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Audio amplifier 2 x 12 W
20. Contents
application. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For sales office addresses, please send an email to: [email protected]
Date of release: 20 February 2008
Document identifier: TFA9810_3
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