NEC Computer Hardware PD75402A User Manual

USER'S MANUAL  
µPD75402A  
4-BIT SINGLE-CHIP MICROCOMPUTER  
µPD75402A  
µPD75P402  
Document No. IEU1270C  
(O. D. No. IEU-644D)  
Date Published March 1994 P  
Printed in Japan  
© NEC Corporation 1989  
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Major Revisions in This Version  
Section  
P.117  
P.179 to 181  
Description  
Amendment: Fig. 5-52 “Data Transmission from Slave Device  
to Master Device”  
Change: Appendix B “Development Tools”  
The mark shows main revised points.  
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PREFACE  
USER  
This manual is intended for user engineers who wish to understand the µPD75402A’s, 75P402’s functions and  
design an application system using them.  
OBJECTIVE  
The objective of this manual is for the user to understand the µPD75402A’s, 75P402’s hardware functions shown  
below.  
COMPOSITION  
This manual is composed roughly of the following contents.  
• General description  
• Pin functions  
• Internal block functions  
• Interrupt  
• Other internal peripheral functions  
• Instruction functions  
READING  
The reader of this manual must have general knowledge of electricity, logic circuitry and microcomputers.  
• Use as the µPD75P402 manual  
This manual describes the µPD75402A as the representative model unless there are particular differences in  
functions. If using it as the µPD75P402 manual, the µPD75402A should be read as the µPD75P402.  
• Checking an instruction function with a known mnemonic  
Appendix D. “Instructions Index (in Alphabetical Order)” should be used.  
• Checking an instruction with an unknown mnemonic but with a roughly known function  
Check the instruction’s mnemonic in 9.2 “Instruction Set and Its Operation” and then check the function in 9.4  
“Instruction Functions and Application”.  
• Roughly understanding the µPD75402A’s, 75P402’s functions  
Follow the contents.  
LEGEND  
Data notation weight  
Notation of active low  
Memory map address  
*
:
:
:
:
:
:
:
High-order digit on the left, low-order digit on the right  
××× (line over pin, signal name)  
Upper__low order, lower__high order  
Explanation of * in text  
Note  
Content to be read carefully  
Supplementary explanation of text  
Binary ... ×××× or ××××B  
Remarks  
Numeric notation  
Decimal ... ××××  
Hexadecimal ... ××××H  
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Related Documentation  
Device Related Documents  
Document Name  
Document Number  
IEU-644  
User's Manual  
Instruction Application Table  
Application Note  
IEM-5504  
IEA-638  
75X Series Selection Guide  
IF-151  
Development Tool Related Documents  
Document Name  
Document Number  
EEU-846  
IE-75000-R/IE-75001-R User's Manual  
IE-75000-R-EM User's Manual  
EP-75402C-R User's Manual  
EP-75402GB-R User's Manual  
PG-1500 User's Manual  
EEU-673  
EEU-701  
EEU-702  
EEU-651  
Operation  
Language  
RA75X Assembler Package l  
User's Manua  
EEU-731  
EEU-730  
PG-1500 Controller User's Manual  
EEU-704  
Other Related Documents  
Document Name  
Document Number  
IEI –635  
Package Manual  
Surface Mount Technology Manual  
IEI –616  
Quality Grade on NEC Semiconductor Devices  
NEC Semiconductor Device Reliability & Quality Control  
Electrostatic Discharge (ESD) Test  
IEI –620  
IEM –5068  
MEM –539  
MEI –603  
Semiconductor Devices Quality Control Guarantee Guide  
Microcomputer Related Products Guide. Other Manufacturers  
MEI –604  
Note The above documents are subject to change without notice.  
The latest documents should be used for design purposes, etc.  
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CONTENTS  
CHAPTER 1. GENERAL...............................................................................................................................  
1
1.1 OUTLINE OF FUNCTIONS . ..........................................................................................................................  
1.2 ORDERING INFORMATION AND QUALITY GRADE..................................................................................  
1.3 DIFFERENCES BETWEEN µPD75402A AND µPD75402, 75P402..............................................................  
1.4 BLOCK DIAGRAM ..........................................................................................................................................  
1.5 PIN CONFIGURATION...................................................................................................................................  
2
3
4
5
6
6
8
1.5.1  
1.5.2  
28-Pin Plastic DIP (600 mil), Shrink DIP (400 mil) .....................................................................  
44-Pin Plastic QFP ( 10 mm) ....................................................................................................  
CHAPTER 2. PIN FUNCTIONS .................................................................................................................. 10  
2.1 µPD75402A PIN FUNCTION LIST ................................................................................................................ 11  
2.1.1  
2.1.2  
Port Pin List .................................................................................................................................... 11  
List of Pins Other than Port Pins ................................................................................................. 12  
2.2 NORMAL OPERATING MODE ...................................................................................................................... 13  
2.2.1  
2.2.2  
2.2.3  
2.2.4  
2.2.5  
2.2.6  
2.2.7  
2.2.8  
2.2.9  
2.2.10  
P00 to P03 (Port 0), P10, P12 (Port 1) ......................................................................................... 13  
P20 to P23 (Port 2), P30 to P33 (Port 3), P50 to P53 (Port 5), P60 to P63 (Port 6) ................ 14  
SCK, SO/SB0, SI............................................................................................................................. 14  
INT0 ................................................................................................................................................. 14  
INT2 ................................................................................................................................................. 14  
PCL .................................................................................................................................................. 14  
X1, X2.............................................................................................................................................. 15  
RESET (Reset) ................................................................................................................................ 15  
VDD ................................................................................................................................................... 15  
VSS ................................................................................................................................................... 15  
2.3 PROM MODE.................................................................................................................................................. 16  
2.3.1  
2.3.2  
2.3.3  
2.3.4  
2.3.5  
2.3.6  
2.3.7  
A0 to A14 (Address) ...................................................................................................................... 16  
O0 to O7 (Data) .............................................................................................................................. 16  
CE (Chip Enable)............................................................................................................................ 16  
OE (Output Enable) ....................................................................................................................... 16  
VPP .................................................................................................................................................... 16  
VDD ................................................................................................................................................... 16  
VSS ................................................................................................................................................... 16  
2.4 PIN INPUT/OUTPUT CIRCUITS ................................................................................................................... 17  
2.5 UNUSED PIN TREATMENT .......................................................................................................................... 20  
2.6 NOTES ON USE OF P00 PIN AND RESET PIN........................................................................................... 20  
CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP............................................... 21  
3.1 DATA MEMORY BANK CONFIGURATION AND ADDRESSING MODES ............................................... 21  
3.1.1  
3.1.2  
Data Memory Bank Configuration .............................................................................................. 21  
Data Memory Addressing Modes ............................................................................................... 24  
3.2 MEMORY-MAPPED I/O ................................ .............................................................................................. 28  
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CHAPTER 4. INTERNAL CPU FUNCTIONS ........................................................................................... 31  
4.1 PROGRAM COUNTER (PC)........................................................................................................................... 31  
4.2 PROGRAM MEMORY (ROM) . ..................................................................................................................... 32  
4.3  
DATA MEMORY (RAM) ............................................................................................................................... 33  
4.4 GENERAL REGISTER . .................................................................................................................................. 35  
4.5 ACCUMULATOR ............................................................................................................................................ 36  
4.6 STACK POINTER (SP) ................................................................................................................................... 37  
4.7 PROGRAM STATUS WORD (PSW) ............................................................................................................. 39  
CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS ........................................................................ 41  
5.1 DIGITAL INPUT/OUTPUT PORTS ................................................................................................................ 41  
5.1.1  
5.1.2  
5.1.3  
5.1.4  
5.1.5  
5.1.6  
Digital Input/Output Port Types, Characteristics and Configuration...................................... 42  
Input/Output Mode Setting .......................................................................................................... 46  
Digital Input/Output Port Handling Instructions ....................................................................... 47  
Digital Input/Output Port Operations.......................................................................................... 49  
Internal Pull-Up Resistors ............................................................................................................ 51  
Digital Input/Output Port Input/Output Timing ......................................................................... 53  
5.2 CLOCK GENERATION CIRCUIT.................................................................................................................... 54  
5.2.1  
5.2.2  
5.2.3  
5.2.4  
Clock Generation Circuit Configuration ..................................................................................... 54  
Clock Generation Circuit Function and Operation .................................................................... 55  
CPU Clock Setting ......................................................................................................................... 59  
Differences Between µPD75402A and µPD75402 ...................................................................... 61  
5.3 CLOCK OUTPUT CIRCUIT............................................................................................................................. 63  
5.3.1  
5.3.2  
5.3.3  
5.3.4  
Clock Output Circuit Configuration............................................................................................. 63  
Clock Output Mode Register (CLOM) ......................................................................................... 64  
Clock Output Procedure ............................................................................................................... 65  
Example of Remote Control Application.................................................................................... 65  
5.4 BASIC INTERVAL TIMER .............................................................................................................................. 66  
5.4.1  
5.4.2  
5.4.3  
5.4.4  
Basic Interval Timer Configuration ............................................................................................. 66  
Basic Interval Timer Mode register (BTM)................................................................................. 67  
Basic Interval Timer Operation.................................................................................................... 68  
Examples of Basic Interval Timer Applications ........................................................................ 69  
5.5 SERIAL INTERFACE ....................................................................................................................................... 70  
5.5.1  
5.5.2  
5.5.3  
5.5.4  
5.5.5  
5.5.6  
Serial Interface Functions ............................................................................................................ 70  
Serial Interface Configuration ..................................................................................................... 71  
Register Functions......................................................................................................................... 74  
Operation-Halt Mode .................................................................................................................... 83  
3-Wire Serial I/O Mode Operation............................................................................................... 84  
SBI Mode Operation ..................................................................................................................... 93  
CHAPTER 6. INTERRUPT FUNCTIONS .................................................................................................. 126  
6.1 INTERRUPT CONTROL CIRCUIT CONFIGURATION.................................................................................. 126  
6.2 INTERRUPT SOURCE TYPES AND VECTOR TABLE ................................................................................. 128  
6.3 INTERRUPT CONTROL CIRCUIT HARDWARE ........................................................................................... 129  
6.4 INTERRUPT SEQUENCE ............................................................................................................................... 134  
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6.5 MACHINE CYCLES BEFORE INTERRUPT SERVICING .............................................................................. 135  
6.6 INTERRUPT APPLICATIONS ........................................................................................................................ 137  
CHAPTER 7. STANDBY FUNCTION ....................................................................................................... 141  
7.1 STANDBY MODE SETTING AND OPERATION STATES .......................................................................... 142  
7.2 STANDBY MODE RESET .............................................................................................................................. 143  
7.3 OPERATION AFTER STANDBY MODE RESET ........................................................................................... 145  
7.4 STANDBY MODE APPLICATION ................................................................................................................. 145  
CHAPTER 8. RESET FUNCTION ............................................................................................................... 146  
CHAPTER 9. INSTRUCTION SET ............................................................................................................. 148  
9.1 SPECIAL INSTRUCTION ............................................................................................................................... 149  
9.1.1  
9.1.2  
9.1.3  
9.1.4  
Bit Operation Instructions ............................................................................................................ 149  
Stack Instructions .......................................................................................................................... 149  
Base Correction Instructions........................................................................................................ 150  
Skip Instruction and Number of Machine Cycles Required by Skip ...................................... 150  
9.2 INSTRUCTION SET AND ITS OPERATION ................................................................................................. 151  
9.3 OPERATION CODE OF EACH INSTRUCTION............................................................................................. 156  
9.4 INSTRUCTION FUNCTIONS AND APPLICATION ...................................................................................... 159  
9.4.1  
9.4.2  
9.4.3  
9.4.4  
9.4.5  
9.4.6  
9.4.7  
9.4.8  
9.4.9  
9.4.10  
9.4.11  
9.4.12  
9.4.13  
Move Instructions.......................................................................................................................... 159  
Table Reference Instructions ....................................................................................................... 162  
Arithmetic and Logic Instructions ............................................................................................... 163  
Accumulator Operation Instructions .......................................................................................... 165  
Increment/Decrement Instructions.............................................................................................. 166  
Compare Instructions ................................................................................................................... 167  
Carry Flag Operation Instructions ............................................................................................... 168  
Bit Manipulation Instructions ...................................................................................................... 169  
Branch Instructions ....................................................................................................................... 171  
Subroutine Stack Control Instructions ....................................................................................... 172  
Interrupt Control Instructions ...................................................................................................... 174  
Input/Output Instructions ............................................................................................................. 175  
CPU Control Instructions .............................................................................................................. 176  
APPENDIX A. TABLE OF INSTRUCTION USABLE WITH EVAKIT-75X ONLY .............................. 177  
APPENDIX B. DEVELOPMENT TOOLS................................................................................................... 179  
APPENDIX C. MASK ROM ORDERING PROCEDURE ......................................................................... 182  
APPENDIX D. INSTRUCTION INDEX (ALPHABETIC ORDER)............................................................ 183  
APPENDIX E. HARDWARE INDEX (ALPHABETIC ORDER) ................................................................ 184  
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CONTENTS OF FIGURES  
Title  
Fig. No  
Page  
3-1  
Static RAM Address Updating Method ............................................................................................. 25  
4-1  
4-2  
4-3  
4-4  
4-5  
4-6  
4-7  
4-8  
4-9  
4-10  
Program Counter Configuration ......................................................................................................... 31  
Program Memory Map ........................................................................................................................ 32  
Data Memory Map ............................................................................................................................... 33  
General Register Configuration.......................................................................................................... 35  
Register Pair Configuration................................................................................................................. 35  
Accumulators ........................................................................................................................................ 36  
Stack Pointer Configuration ................................................................................................................ 37  
Data Saved to Stack Memory ............................................................................................................. 38  
Data Restored from Stack Memory ................................................................................................... 38  
Program Status Word Configuration ................................................................................................. 39  
5-1  
Digital Input/Output Port Data Memory Addresses ......................................................................... 41  
Configuration of Ports 0 and 1 ........................................................................................................... 43  
Configuration of Port 3 . ...................................................................................................................... 44  
Configuration of Ports 2 and 6 ........................................................................................................... 45  
Configuration of Port 5 ........................................................................................................................ 46  
Format of Port Mode Registers .......................................................................................................... 47  
Format of Pull-Up Resistor Specification Register .......................................................................... 52  
Pull-Up Resistor Incorporation Switching Timing ........................................................................... 52  
Digital Input/Output Port Input/Output Timing ................................................................................ 53  
Clock Generation Circuit Block Diagram ........................................................................................... 54  
Processor Clock Control Register Format ......................................................................................... 56  
System Clock Oscillation Circuit External Circuitry......................................................................... 57  
Example of Poor Resonator Connection Circuit............................................................................... 57  
Use of Variable Minimum Instruction Execution Time Function................................................... 59  
Change of Φ after Power-On Reset .................................................................................................... 60  
Clock Generation Circuit - Differences between µPD75402A and µPD75402 ............................... 61  
µPD75402 Processor Clock Control Register Format....................................................................... 62  
Clock Output Circuit Configuration .................................................................................................... 63  
Clock Output Mode Register Format ................................................................................................ . 64  
Example of Remote Control Application........................................................................................... 65  
Basic Interval Timer Configuration .................................................................................................... 66  
Basic Interval Timer Mode Register Format ..................................................................................... 67  
Example of SBI System Configuration .............................................................................................. 71  
Serial Interface Block Diagram ........................................................................................................... 72  
Serial Operating Mode Register (CSIM) Format .............................................................................. 75  
Serial Bus Interface Control Register (SBIC) Format....................................................................... 78  
Configuration Around Shift Register ................................................................................................. 81  
Example of 3-Wire Serial I/O System Configuration ....................................................................... 84  
3-Wire Serial I/O Mode Timing ........................................................................................................... 88  
RELT & CMDT Operation..................................................................................................................... 89  
Shift Register (SIO) and Internal Bus Configuration ....................................................................... 90  
5-2  
5-3  
5-4  
5-5  
5-6  
5-7  
5-8  
5-9  
5-10  
5-11  
5-12  
5-13  
5-14  
5-15  
5-16  
5-17  
5-18  
5-19  
5-20  
5-21  
5-22  
5-23  
5-24  
5-25  
5-26  
5-27  
5-28  
5-29  
5-30  
5-31  
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Fig. No.  
Title  
Page  
5-32  
5-33  
5-34  
5-35  
5-36  
5-37  
5-38  
5-39  
5-40  
5-41  
5-42  
5-43  
5-44  
5-45  
5-46  
5-47  
5-48  
5-49  
5-50  
5-51  
5-52  
5-53  
5-54  
5-55  
5-56  
5-57  
5-58  
5-59  
5-60  
5-61  
Example of SBI Serial Bus System Configuration ........................................................................... 93  
SBI Transfer Timing ............................................................................................................................. 95  
Bus Release Signal ............................................................................................................................... 96  
Command Signal .................................................................................................................................. 96  
Address .................................................................................................................................................. 97  
Slave Selection by Address ................................................................................................................ 97  
Command .............................................................................................................................................. 98  
Data ........................................................................................................................................................ 98  
Acknowledge Signal ............................................................................................................................ 99  
Busy Signal & Ready Signal ............................................................................................................. 100  
RELT, CMDT, RELD & CMDD Operation (Master) .......................................................................... 106  
RELT, CMDT, RELD & CMDD Operation (Slave) ........................................................................... . 106  
ACKT Operation .................................................................................................................................. 107  
ACKE Operation .................................................................................................................................. 108  
ACKD Operation ................................................................................................................................. 109  
BSYE Operation .................................................................................................................................. 109  
Pin Configuration Diagram ............................................................................................................... 112  
Address Transmission from Master Device to Slave Device (WUP = 1) .................................... 114  
Command Transmission from Master Device to Slave Device ................................................... 115  
Data Transmission from Master Device to Slave Device.............................................................. 116  
Data Transmission from Slave Device to Master Device.............................................................. 117  
Example of Serial Bus Configuration .............................................................................................. 119  
READ Command Transfer Format.................................................................................................... 121  
WRITE & END Command Transfer Format ..................................................................................... 121  
STOP Command Transfer Format.................................................................................................... 122  
STATUS Command Transfer Format............................................................................................... 123  
STATUS Command Status Format .................................................................................................. 123  
RESET Command Transfer Format .................................................................................................. 124  
CHGMST Command Transfer Format ............................................................................................ . 124  
Master and Slave Operations after an Error................................................................................... 125  
6-1  
6-2  
6-3  
6-4  
6-5  
6-6  
6-7  
6-8  
Interrupt Control Circuit Block Diagram.......................................................................................... 127  
Interrupt Vector Table ........................................................................................................................ 128  
Configuration of INT0 and INT2 ....................................................................................................... 130  
INT0 Noise Elimination Circuit Input/Output Timing .................................................................... 131  
INT2 Input Noise Elimination . ......................................................................................................... 131  
Edge Detection Mode Register Format ........................................................................................... 132  
IME Format .......................................................................................................................................... 132  
Interrupt Servicing Procedure .......................................................................................................... 134  
7-1  
Standby Mode Reset Operation ....................................................................................................... 144  
8-1  
8-2  
Reset Signal Acceptance ................................................................................................................... 146  
Reset at Power-on .............................................................................................................................. 146  
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CONTENTS OF TABLES  
Title  
Table No.  
Page  
1-1  
Differences Between µPD75402A and µPD75402, 75P402 ................................................................. 4  
2-1  
2-2  
2-3  
2-4  
Port Pin List ........................................................................................................................................... 11  
List of Pins Other than Port Pins ........................................................................................................ 12  
Port 0’s, 1’s Dual-Function Pins.......................................................................................................... 13  
Pin Input/Output Types ........................................................................................................................ 17  
3-1  
Data Memory Configuration and Address Range  
in Each Addressing Mode ................................................................................................................... 22  
Addressing Mode List .......................................................................................................................... 23  
Applicable Addressing Modes at Peripheral Hardware Operation ............................................... 28  
µPD75402A I/O Map ............................................................................................................................. 29  
3-2  
3-3  
3-4  
4-1  
4-2  
Carry Flag Manipulation Instructions ................................................................................................ 39  
Interrupt Status Flag Indication Content ........................................................................................... 40  
5-1  
5-2  
5-3  
5-4  
5-5  
5-6  
5-7  
5-8  
Digital Input/Output Port Types and Characteristics ....................................................................... 42  
List of Input/Output Pin Handling Instructions................................................................................. 48  
Operations with Input/Output Port Handling Instructions .............................................................. 50  
Internal Pull-up Resister Specification for Each Port ...................................................................... 51  
Maximum Time Required for Change of CPU Clock ....................................................................... 60  
Serial Clock Selection and Use (in 3-Wire Serial I/O Mode) .......................................................... 89  
Serial Clock Selection and Use (in SBI Mode) ............................................................................... 105  
Signals in SBI Mode........................................................................................................................... 110  
6-1  
6-2  
6-3  
Interrupt Request Source Types....................................................................................................... 128  
Interrupt Request Flag Setting Signal ............................................................................................. 129  
IST0 Interrupt Servicing Status ........................................................................................................ 133  
7-1  
8-1  
Standby Mode Operation States ...................................................................................................... 142  
State of Hardware after Reset .......................................................................................................... 147  
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CHAPTER 1. GENERAL  
The µPD75402A, 75P402 is a CMOS 4-bit single-chip microcomputer adopting the 75X architecture. With its built-  
in NEC standard serial bus interface (SBI), it is suitable as a slave microcomputer in a multiprocessor system  
configuration using the 75X, 78K series as the host microcomputer.  
The µPD75402A has shortened the conventional µPD75402’s minimum instruction execution time to 0.95 µs. The  
µPD75P402 is also capable of high-speed processing.  
It is possible to reduce the burden on the host microcomputer by using the µPD75402A, 75P402 as the slave  
microcomputer by using the µPD75402A, 75P402 as the slave microcomputer for decentralized processing. The  
µPD75402A, or 75P402 is most suitable for slave processes for the following devices such as the key input control,  
LED, etc. display control, or remote control send/receive control, etc.  
• FAX  
• PPC  
• Printer  
• ECR  
• VCR  
• Remote control commander  
The µPD75P402 is a product with the µPD75402A’s built-in mask ROM having been replaced with the one-time  
PROM. It is compatible with theµPD75402A except for the program memory and the mask option. The pin connection  
at write is the same as in the standard EPROM µPD27C256A and also has the same writing characteristics. Therefore,  
it is possible to write directly using the general-purpose PROM writer. The µPD75P402 is suitable for preproduction  
at system development and short-run and multiple-device production.  
Name  
µPD75402A  
µPD75P402  
Program Memory  
1920 × 8 (mask ROM)  
Data Memory  
64 × 4 (RAM)  
64 × 4 (RAM)  
1920 × 8 (one-time PROM)  
Remarks In this manual, the µPD75402A is described as the representative model unless there are particular  
differences in functions. If using it as the µPD75P402 manual, the µPD75402A, should be read as the  
µPD75P402.  
1
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CHAPTER 1. GENERAL  
1.1 OUTLINE OF FUNCTIONS  
Item  
Description  
Number of basic  
instructions  
37  
Instruction  
execution time  
• 0.95 µs, 1.91 µs, 15.3 µs (at 4.19 MHz operation)  
selectable between 3 levels  
Built-in  
memory  
Program  
memory  
1920 × 8 bits (µPD75402A: Mask ROM, µPD75P402: One-time PROM)  
64 × 4 bits (RAM)  
Data  
memory  
General register  
Accumulators  
4 bits × 4, or 8 bits × 2 (memory mapping)  
3 accumulators to suit manipulation data length  
• Bit accumulator (CY), 4-bit accumulator (A), 8-bit accumulator (XA)  
I/O line  
Total 22 lines  
• CMOS input port  
• CMOS input/output port (LED direct drivable 8 lines)  
• N-ch open-drain input/ output port (LED direct drivable)  
: 6 lines  
: 12 lines  
: 4 lines  
Pull-up resistor  
Clock output  
• Pull-up resistor built-in control possible by software  
• Pull-up resistor built-in control possible by mask option (µPD75402A only) : 4 lines  
: 16 lines  
• 1.05 MHz, 524 kHz, 65.5 kHz (at 4.19 MHz operation)  
• Applicable to remote control output  
Timer/Counter  
8-bit basic interval timer  
• Reference time generation (1.95 ms, 31.3 ms : at 4.19 MHz operation)  
• Watchdog timer applicable  
Serial interface  
• 8 bits  
• 2 transfer modes (clock synchronous 3-wire system mode/SBI mode)  
Vectored  
interrupt  
External: 1 line, internal : 2 lines  
Test input  
External: 1 line  
(For details, see CHAPTER 6 “INTERRUPT FUNCTIONS”.)  
Standby  
STOP mode/HALT mode  
Instruction set  
• Bit manipulation instruction (set, clear, test, Boolean operation)  
• 1-byte relative branch instruction  
• 4-bit operation instruction (add, Boolean operation, compare)  
• 4, 8-bit data transfer instruction  
Package  
• 28-pin plastic DIP (600 mil)  
• 28-pin plastic shrink DIP (400 mil)  
• 44-pin plastic QFP ( 10 mm)  
2
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CHAPTER 1. GENERAL  
1.2 ORDERING INFORMATION AND QUALITY GRADE  
(1) Ordering Information  
Ordering Code  
µPD75402AC-×××  
µPD75402ACT-×××  
µPD75402AGB-×××-3B4  
µPD75P402C  
Package  
Program Memory  
Mask ROM  
28-pin plastic DIP  
(600 mil)  
(400 mil)  
( 10mm)  
(600 mil)  
(400 mil)  
( 10mm)  
28-pin plastic shrink DIP  
44-pin plastic QFP  
28-pin plastic DIP  
One-time PROM  
µPD75P402CT  
28-pin plastic shrink DIP  
44-pin plastic QFP  
µPD75P402GB-3B4  
×××: ROM code number  
(2) Quality Grade  
Standard  
Please refer to “Quality grade on NEC Semiconductor Devices” (Document number IEI-1209) published by NEC  
Corporation to know the specification of quality grade on the devices and its recommended applications.  
3
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CHAPTER 1. GENERAL  
1.3 DIFFERENCES BETWEEN µPD75402A AND µPD75402, 75P402  
Table 1-1 shows the differences between the µPD75402A and the µPD75402, 75P402. Otherwise the µPD75402A  
and the µPD75402, 75P402 have the same functions and are pin-compatible.  
Table 1-1 Differences Between µPD75402A and µPD75402, 75P402  
Item  
µPD75402A  
µPD75402  
µPD75P402  
ROM configuration  
Mask ROM  
One-time PROM  
Instruction  
0.95, 1.91, 15.3 µs  
1.91, 15.3 µs*  
0.95, 1.91, 15.3 µs  
execution time  
(at 4.19 MHz operation)  
(at 4.19 MHz operation)  
(at 4.19 MHz operation)  
Port 5’s pull-up resistor  
Designatable to be built in by mask option  
NC  
Not available  
1-pin (SDIP)  
30-pin (QFP)  
Pin  
VPP  
functions  
Supply voltage  
Operating  
2.7 to 6.0 V  
5 V ±10%  
–40 to +85°C  
–10 to +70°C  
temperature range  
Package  
• 28-pin plastic DIP (600 mil)  
• 28-pin plastic shrink DIP (400 mil)  
• 44-pin plastic QFP ( 10 mm)  
*
The µPD75402A has shortened the µPD75402’s minimum instruction execution time to 0.95 µs.  
For details, see 5.2.4 “Differences Between µPD75402A And µPD75402”.  
4
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4
2
PORT0  
PORT1  
P00-P03  
P10, P12  
BASIC  
INTERVAL  
TIMER  
ALU  
CY  
SP (5)  
PROGRAM  
COUNTER(11)  
INTBT  
4
PORT2  
PORT3  
PORT5  
PORT6  
P20-P23  
P30-P33  
P50-P53  
P60-P63  
SI  
SO/SB0  
SCK  
SERIAL  
INTERFACE  
ROM (PROM)  
PROGRAM  
MEMORY  
4
4
4
GENERAL REG.  
DECODE  
AND  
INTCSI  
CONTROL  
RAM  
DATA MEMORY  
64 x 4 bits  
1920 × 8 bits  
INT0  
INT2  
INTERRUPT  
CONTROL  
fxx/2N  
CPU CLOCK  
CLOCK  
OUTPUT  
CONTROL  
ø
CLOCK  
DIVIDER  
CLOCK  
GENERATOR  
STAND BY  
CONTROL  
PCL  
X1  
X2  
VDD  
VSS RESET  
NC  
(VPP)  
Remarks Parentheses for the µPD75P402.  
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CHAPTER 1. GENERAL  
1.5  
PIN CONFIGURATION  
1.5.1 28-Pin Plastic Dip (600 mil), Shrink Dip (400 mil)  
(1) Normal operating mode  
*
VDD  
1
2
(VPP) NC  
RESET  
P00  
28  
X1  
27  
26  
25  
24  
23  
X2  
3
4
5
6
7
8
9
P12/INT2  
P10/INT0  
P23  
P01/SCK  
µ
µ
P02/SO/SB0  
P03/SI  
P22/PCL  
P21  
P50  
P51  
P52  
P53  
P30  
P31  
P32  
22  
21  
20  
19  
18  
17  
16  
15  
P20  
P63  
10  
11  
12  
13  
14  
P62  
P61  
P60  
P33  
VSS  
P00 to P03 : Port 0  
SCK  
: Serial clock input/output  
: Serial output/input/output  
: Serial input  
P10, P12  
: Port 1  
SO/SB0  
SI  
P20 to P23 : Port 2  
P30 to P33 : Port 3  
P50 to P53 : Port 5  
P60 to P63 : Port 6  
PCL  
: Clock output  
INT0  
INT2  
X1, X2  
RESET  
VDD  
: External vectored interrupt input  
: External test input  
: Oscillator pin  
: Reset input  
: Power supply  
VSS  
: Ground  
VPP  
: Externally set to GND potential  
: No connection  
NC  
Remarks Parentheses for the µPD75P402.  
*
If using the µPD75P402 and the printed circuit board commonly in the µPD75402A, the NC pin is to be set to the  
GND potential.  
6
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CHAPTER 1. GENERAL  
(2) PROM mode  
1
2
3
4
VPP  
A12  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
O0  
O1  
O2  
VSS  
28  
27  
26  
25  
24  
23  
22  
VDD  
A14  
A13  
A8  
5
6
7
8
9
µ
A9  
A11  
OE  
A10  
CE  
21  
20  
19  
18  
17  
16  
15  
10  
11  
12  
13  
14  
O7  
O6  
O5  
O4  
O3  
A0 to A14  
O0 to O7  
CE  
: Address input  
: Data input/output  
: Chip enable input  
: Output enable input  
: Power supply  
OE  
VDD  
VPP  
: Program power supply  
: Ground  
VSS  
7
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CHAPTER 1. GENERAL  
1.5.2 44-Pin Plastic QFP ( 10mm)  
(1) Normal operating mode  
34  
44 43 42 41 40 39 38 37 36 35  
1
2
3
4
5
6
7
8
9
P30  
P31  
P32  
NC  
P01/SCK  
P00  
33  
32  
31  
30  
RESET  
NC (VPP)*  
NC  
VSS  
NC  
NC  
29  
µPD75402AGB-×××-3B4  
28  
NC  
µPD75P402GB-×××-3B4  
NC  
27  
26  
25  
VDD  
P33  
P60  
P61  
NC  
X1  
10  
24  
X2  
11  
23  
NC  
12 13 14 15 16 17 18 19 20 21 22  
Remarks Parentheses for the µPD75P402.  
*
If using the µPD75P402 and the printed circuit board commonly in the µPD75402A, the NC pin of the 30-pin  
corresponding to the µPD75P402’s VPP is to be set to the GND potential.  
8
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CHAPTER 1. GENERAL  
(2) PROM mode  
44 43 42 41 40 39 38 3357 34  
36  
A6  
O0  
O1  
O2  
NC  
VSS  
NC  
NC  
O3  
O4  
O5  
NC  
1
2
33  
A7  
32  
31  
30  
3
4
A12  
VPP  
NC  
NC  
NC  
VDD  
A14  
5
29  
28  
27  
26  
25  
24  
6
µPD75P402GB-3B4  
7
8
9
A13  
NC  
10  
11  
23  
12 13 14 15 16 17 18 19 20 21 22  
9
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CHAPTER 2. PIN FUNCTIONS  
The µPD75402A operates by the pin functions in the normal operating mode.  
For the µPD75P402’s pin functions, the 2 modes of the normal operating mode (µPD75402A mode) and the PROM  
mode are available.  
The operating mode switches according to the VPP pin level as shown in the table below.  
VPP  
Operating Mode  
Low level (GND potential)  
High level (+5 V)  
Normal operating mode  
PROM read mode  
PROM mode  
High level (+12.5 V)  
PROM write/verify mode  
10  
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CHAPTER 2. PIN FUNCTIONS  
2.1 µPD75402A PIN FUNCTION LIST  
2.1.1 Port Pin List  
Table 2-1 Port Pin List  
Functions  
Pin Name  
Input/Output  
Dual-Function Pin  
A 4-bit input port (Port 0).  
P00  
P01  
P02  
P03  
P10  
Input  
For P01 to P03, it is designatable to build in the pull-up resistor by  
software in 3-bit units.  
Input/output  
Input/output  
Input  
SCK  
SO/SB0  
SI  
A 2-bit input port (Port 1).  
Input  
INT0  
P10 is built in with the noise eliminator by the sampling clock.  
P12 is built in with the noise eliminator by analog delay.  
For P12, it is designatable to build in the pull-up resistor by  
software.  
P12  
INT2  
A 4-bit input/output port (Port 2).  
P20  
P21  
Input/output  
Input/output  
It is designatable to input/output in 4-bit units.  
It is designatable to build in the pull- up resistor by software in 4-  
bit units.  
P22  
PCL  
P23  
A programmable 4-bit input/output port (Port 3).  
It is designatable to input/output bit-wise.  
It is designatable to build in the pull-up resistor by software in 4-  
bit units.  
P30 to P33  
It is possible to drive the LED directly.  
A 4-bit N-ch open drain input/output port (Port 5).  
It is designatable to input/output in 4-bit units.  
It is designatable to build in the pull-up resistor by mask  
option bit-wise.  
P50 to P53  
Input/output  
It is possible to drive the LED directly.  
A 4-bit input/output port (Port 6).  
Input/output  
P60 to P63  
It is designatable to input/output in 4-bit units.  
It is designatable to build in the pull-up resistor by software in  
4-bit units.  
It is possible to drive the LED directly.  
Remarks 1. In the µPD75402A, 8-bit input/output with 2 ports making up a pair is impossible.  
2. For the status of each pin at reset, see CHAPTER 8 “RESET FUNCTION”.  
11  
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CHAPTER 2. PIN FUNCTIONS  
2.1.2 List of Pins Other Than Port Pins  
Table 2-2 List of Pins Other than Port Pins  
Functions  
Pin Name  
INT0  
Input/Output  
Input  
Dual-Function Pin  
An edge-detected vectored interrupt request input pin (detected  
edge selectable by mode register).  
Built in with the noise eliminator by the sampling clock.  
An edge detected external test input pin (rising edge detection).  
A serial data input pin.  
P10  
INT2  
SI  
Input  
P12  
P03  
Input  
A serial data output pin.  
SO  
Input/output  
Input/output  
Input/output  
Input/output  
Input  
P02/SB0  
P01  
A serial clock input/output pin.  
SCK  
SB0  
PCL  
X1, X2  
A serial bus input/output pin.  
P02/SO  
P22  
A clock output pin.  
A system clock oscillation crystal/ ceramic resonator connection  
pin. If supplying the clock from the exterior, input to X1 and input  
the inverted phase to X2.  
A system reset input pin. Built in with the noise eliminator by  
analog delay.  
RESET  
Input  
A positive power supply pin.  
VDD  
VSS  
A GND potential pin.  
No Connection  
NC*8  
Remarks For the status of each pin at reset, see CHAPTER 8 “RESET FUNCTION”.  
*
If using the µPD75P402 and the printed circuit board commonly, the NC pin should be connected directly to VSS.  
12  
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CHAPTER 2. PIN FUNCTIONS  
2.2 NORMAL OPERATING MODE  
2.2.1 P00 to P03 (Port 0) ..... SCK, SO/SB0, SI Dual-Function Input  
P10, P12 (Port 1) ..... INT0, INT2 Dual-Function Input  
P00 to P03 are the 4-bit input port: Port 0’s input pins. P10 and P12 are the 2-bit input port: Port 1’s input pins.  
Ports 0 and 1 also have the functions of the various control signal pins shown in Table 2-1 in addition to the  
functions as input ports. The status of each of Ports 0 and 1 is always inputtable irrespective of the dual-function  
pin operation.  
Both Ports 0 and 1 have Schmitt-triggered input to prevent malfunction by noise. P10 is built in with the noise  
eliminator by the sampling clock and P12 is built in with the noise eliminator by analog delay.  
Ports 0 and 1 allow to designate to build in the pull-up resistor respectively in 3-bit units (P01 to P03) and bit-  
wise (P12 only). Such designation is made using the pull-up resistor designation register (POGA). Neither P00 or  
P10 can be built in with the pull-up resistor.  
Any of these pins assumes the input port mode at RESET input.  
Table 2-3 Port 0’s, 1’s Dual-Function Pins  
Port 0  
P00  
Dual-Function  
Pin Port 1  
P10  
Dual-Function Pin  
INT0  
INT2  
P01  
SCK  
SO/SB0  
SI  
P12  
P02  
P03  
13  
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CHAPTER 2. PIN FUNCTIONS  
2.2.2 P20 to P23 (Port 2) ..... PCL Dual-Function 3-Stae Input/Otput  
P30 to P33 (Port 3) ..... 3-State Input/Output  
P50 to P53 (Port 5) ..... N-ch Open Drain Middle-Voltage (10 V) Input/Output  
P60 to P63 (Port 6) ..... 3-State Input/Output  
The 4-bit input/output port with the output latch: Port 2’s, 3’s, 5’s, 6’s 4-bit input/output pins. Port 2 also shares  
the programmable clock output (PCL) function with P22 in addition to having the input/output port function. Port  
5 has the N-ch open drain middle-voltage (10 V) output.  
Port 3 allows to designate input/output bit-wise using the port mode register (PMGA). Ports 2, 5 and 6 allow to  
designate input/output in 4-bit units using the port mode register (PMGA, PMGB).  
Ports 2, 3 and 6 allow to designate to build in the pull-up resistor by software in 4-bit units. Such designation  
is made using the pull-up resistor designation register (POGA).  
The µPD75402A’s Port 5 allows to designate to build in the pull-up resistor by mask option bit-wise. The  
µPD75P402’s Port 5 cannot be built in with the pull-up resistor. Ports 3, 5 and 6 have large-current output and can  
drive the LED directly.  
Ports 2, 3 and 6 turn input ports (output high impedance) at RESET input. Port 5 turns high level (if built in with  
the pull-up resistor) or high impedance. The content of the output latch turns indeterminate.  
2.2.3 SCK, SO/SB0, SI ..... Port 0 Dual-Function 3-State Input/Output  
A serial interface input/output pin. It operates according to the serial operating mode register (CSIM) setting.  
Each has Schmitt-triggered input.  
The serial interface stops at RESET input and each turns into an input port.  
2.2.4  
INT0 ..... Port 1 Dual-Function Input  
An external interrupt request input pin. It is designatable for either of the 3 of rising edge detection, falling edge  
detection and rising and falling edge detection using the external interrupt mode register (IM0).  
INT0 has Schmitt-triggered input and is built in with the noise eliminator by the sampling clock.  
2.2.5 INT2 ..... Port 1 Dual-Function Input  
An external test input pin. The detected edge is fixed to the rising edge. It has Schmitt-triggered input and is built  
in with the noise eliminator by analog delay.  
INT2 has asynchronous input. It accepts a signal having a certain high-level width irrespective of the CPU’s  
operation clock if one is input.  
2.2.6 PCL ..... Port 2 Dual-Function Output  
A programmable clock output pin. It is used to supply the clock to the peripheral LSI. The PCL output is also  
applicable to the remote control carrier signal.  
The clock output function stops at RESET input and PCL turns into an input port (P22).  
14  
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CHAPTER 2. PIN FUNCTIONS  
2.2.7 X1, X2 (Crystal)  
The built-in clock oscillation crystal/ceramic input.  
It is also possible to supply the clock from the exterior.  
(a) Crystal/Ceramic Oscillation  
(b) External Clock  
V
DD  
µPD75402A  
µPD75402A  
X1  
V
DD  
External  
Clock  
X1  
µPD74HC04  
X2  
X2  
Crystal Resonator  
or Ceramic Oscillator (Standard 4.194304 MHz)  
2.2.8 RESET (Reset)  
A low level active system reset input pin. It has Schmitt-triggered input and is built in with the noise eliminator  
by analog delay.  
It has asynchronous input for RESET. It accepts a signal having a certain low-level width irrespective of the CPU’s  
operation clock if one is input and system reset is effected under priority over any other operation.  
2.2.9 VDD  
A positive power supply pin.  
2.2.10 VSS  
A GND potential pin.  
15  
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CHAPTER 2. PIN FUNCTIONS  
2.3 PROM MODE  
The PROM mode is designatable in the µPD75P402 alone.  
2.3.1 A0 to A14 (Address) ..... Input  
A 15-bit address input pin at PROM write/verify, read. As the PROM built into the µPD75P402 has 2K bytes, it is  
addressed by the low-order 11 bits (A0 to A10). A11 to A14 should be fixed to the low level.  
2.3.2 O0 to O7 (Data) ..... Input/Output  
An 8-bit data input/output pin at PROM write/verify, read.  
2.3.3 CE (Chip Enable) ..... Input  
A chip enable signal input pin.  
2.3.4 OE (Output Enable) ..... Input  
An output enable signal input pin.  
2.3.5 VPP  
A high voltage application pin at PROM write/verify.  
It must be connected to VSS during normal operation.  
2.3.6 VDD  
A supply voltage application pin.  
2.3.7 VSS  
A GND potential pin.  
16  
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CHAPTER 2. PIN FUNCTIONS  
2.4 PIN INPUT/OUTPUT CIRCUITS  
The input/output circuit of each pin is shown below in a partly simplified format.  
Table 2-4 Pin Input/output Types  
Input/Output Type  
Pin  
µPD75402A  
µPD75P402  
P00  
B
P01/SCK  
P02/SO/SB0  
P03/SI  
F - A  
F - B  
B - C  
B
P10/INT0  
P12/INT2  
P20, P21, P23  
P22/PCL  
B - C  
E - B  
E - B  
P30 to P33  
P50 to P53  
P60 to P63  
RESET  
M
M - A  
E - B  
B
Remarks A circle  
indicates Schmitt-triggered input.  
17  
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CHAPTER 2. PIN FUNCTIONS  
Type A (for Types E - B)  
Type D (for Type E - B, F - A, Y - D)  
VDD  
VDD  
data  
P-ch  
P-ch  
IN  
OUT  
N-ch  
output  
disable  
N-ch  
Push-pull output that can be turned output high  
impedance (P-ch, N-ch, both off)  
An input buffer of the CMOS standard  
Type E - B  
Type B  
VDD  
P.U.R.  
P.U.R.  
enable  
P-ch  
data  
IN/OUT  
IN  
Type D  
output  
disable  
Type A  
Schmitt-triggered input having  
hysteresis characteristics  
P. U. R : Pull-Up Resistor  
Type B - C  
Type F - A  
VDD  
P.U.R.  
P-ch  
VDD  
P.U.R.  
enable  
P.U.R.  
data  
IN/OUT  
P.U.R.  
enable  
P-ch  
Type D  
output  
disable  
IN  
Type B  
P. U. R : Pull-Up Resistor  
P. U. R : Pull-Up Resistor  
18  
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CHAPTER 2. PIN FUNCTIONS  
Type F - B  
Type M - A  
VDD  
P.U.R.  
P-ch  
IN/OUT  
P.U.R.  
enable  
output  
disable  
(P)  
VDD  
P-ch  
data  
N-ch (+10 V  
Withstand  
Voltage)  
output  
disable  
IN/OUT  
data  
output  
disable  
N-ch  
output  
disable  
(N)  
Middle-High Voltage Input Buffer  
(+10 V Withstand Voltage)  
P. U. R : Pull-Up Resistor  
Type M  
VDD  
P.U.R  
(Mask Option)  
IN/OUT  
N-ch (+10 V  
Withstand  
Voltage)  
data  
output  
disable  
Middle-High Voltage Input Buffer  
(+10 V Withstand Voltage)  
P. U. R : Pull-Up Resistor  
19  
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CHAPTER 2. PIN FUNCTIONS  
2.5 UNUSED PIN TREATMENT  
Pin  
Recommended Connection Method  
P00  
Connect to VSS.  
P01 to P03  
P10 and P12  
• With pull-up resistor Connect to VDD.  
• Without pull-up resistor  
Connect to VSS or VDD.  
P20 to P23  
P30 to P33  
P50 to P53  
• With pull-up resistor  
Input status: Connect to VDD.  
Output status: Leave open.  
• Without pull-up resistor  
Input status: Connect to VSS to VDD.  
Output status: Leave open.  
P60 to P63  
NC  
*
Leave open or connect directly to VSS.  
*
If using the µPD75P402 and the printed circuit board commonly, the NC pins should be connected directly to VSS.  
2.6 NOTES ON USE OF P00 PIN AND RESET PIN  
The P00 and RESET pins are provided with the test mode setting function of test mode (for IC test) which tests  
the internal operation of the µPD75402A in addition to the functions described in 2.2.1 and 2.2.8.  
When a voltage exceeding VDD is applied to either of these pins, the test mode is set. Consequently, if noise  
exceeding VDD is added even in a normal operation, the test mode is set and the normal operation may not be  
continued.  
For example, when wires from the P00 pin or RESET pin are long, inter-wiring noise may be added to these pins  
and the pin voltage may exceed VDD, resulting in a misoperation.  
Therefore, wiring should be carried out so that inter-wiring noise is suppressed as far as possible.  
If it is impossible to suppress the noise, noise prevention measures by means of external parts should be taken  
as shown below.  
o
Insert diode with small  
VF (less than 0.3 V)  
between VDD and  
P00/RESET pin.  
o
Insert capacitor between  
VDD and P00/RESET pin.  
VDD  
VDD  
Diode with  
Small VF  
VDD  
VDD  
P00, RESET  
P00, RESET  
20  
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CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP  
The µPD75402A’s architecture is a subset of the 75X architecture. Its features are outlined below.  
3.1 DATA MEMORY BANK CONFIGURATION AND ADDRESSING MODES  
3.1.1 Data Memory Bank Configuration  
The µPD75402A’s data memory space has a bank configuration. Addresses 000H to 03FH of Bank 0 are a data  
area as shown in Table 3-1 and are built in with a static RAM (64 × 4 bits). Addresses F80H to FFFH of Bank 15 are  
a peripheral hardware area and are built in with the input/output port, serial interface, etc. To address this data  
memory space of a 12-bit address, the low-order 8-bit address is specified directly or indirectly by an instruction.  
The high-order 4-bit address is determined by the memory bank (MB) to be accessed.  
The µPD75402A is built in with only Memory bank 0 and 15 and does not require bank switching unlike other  
products of the 75X series. The memory bank to be accessed is determined by the addressing mode and the address  
to be specified (see Tables 3-1 and 3-2).  
21  
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CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP  
Table 3-1 Data Memory Configuration and Address Range in Each Addressing Mode  
Addressing  
mem  
mem. bit  
Stack  
Addressing  
Mode  
@ HL  
fmem. bit  
Data Memory  
Adress  
000H  
003H  
General  
Register Area  
Data Memory  
Static RAM  
(Memory Bank 0)  
020H  
03FH  
Stack Area  
Not built in.  
F80H  
Peripheral  
Hardware Area  
(Memory Bank 15)  
FB0H  
FBFH  
FF0H  
FFFH  
22  
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CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP  
Table 3-2 Addressing Mode List  
Notation  
mem. bit  
Specified Address  
Addressing Mode  
The bit indicated by bit of the address indicated by mem. However:  
Memory bank 0 is accessed if mem = 00H to 3FH.  
Memory bank 15 is accessed if mem = 80H to FFH.  
The address indicated by mem. However:  
1-bit direct  
addressing  
mem  
4-bit direct  
addressing  
Memory bank 0 is accessed if mem = 00H to 3FH.  
Memory bank 15 is accessed if mem = 80H to FFH.  
The address indicated by mem (mem: Even address). However:  
Memory bank 0 is accessed if mem = 00H to 3EH.  
Memory bank 15 is accessed if mem = 80H to FEH.  
The address indicated by the content of HL of Memory bank 0. If HL = 00H to 3FH,  
however.  
8-bit direct  
addressing  
@HL  
4-bit register  
indirect  
addressing  
Bit manipulation  
addressing  
fmem. bit  
The bit indicated by bit of the address indicated by fmem of Memory bank 15.  
If the following, however:  
fmem = FB0H to FBFH (interrupt, etc. hardware)  
fmem = FF0H to FFFH (input/output port)  
The address indicated by SP of Memory bank 0.  
Limited to 20H to 3FH, however.  
Stack  
addressing  
23  
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CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP  
3.1.2 Data Memory Addressing Modes  
In the µPD75402A, the 6 types of addressing modes listed on Table 3-2 are available for the data memory space  
for efficient addressing per the bit length of the data to be processed.  
Also in the µPD75402A, the memory bank to be accessed is fixed by the addressing mode unlike in other products  
of the 75X series. So programming is possible without caring about memory bank switching.  
(1) 1-bit direct addressing (mem.bit)  
An addressing mode to specify each bit of the whole data memory space directly by the instruction’s operand.  
The specified memory bank (MB) is MB = 0 if the address specified by the operand is 00H to 3FH and MB = 15  
if it is 80H to FFH. Consequently, all the bits in both the static RAM area of 000H to 03FH and the peripheral hardware  
area of FF0H to FFFH are addressable. In the peripheral hardware area, however, the bits capable of 1-bit  
manipulation are limited (see Table 3-2).  
This addressing mode is applied to the 4 instructions of the bit set and reset instructions (SET1, CLR1) and  
testinstructions (SKT, SKF).  
Example Set FLAG1, reset FLAG2 and test whether FLAG3 is 0 or not.  
FLAG1 EQU  
FLAG2 EQU  
FLAG3 EQU  
03FH.1  
027H.2  
017H.0  
; Address 3FH, bit 1  
; Address 27H, bit 2  
; Address 17H, bit 0  
SET1  
CLR1  
SKF  
FLAG1  
FLAG2  
FLAG3  
; FLAG 1  
; FLAG 0  
; FLAG = 0?  
(2) 4-bit direct addressing (mem)  
An addressing mode to specify the whole data memory space directly by the instruction’s operand per 4 bits.  
The specified memory bank (MB) is MB = 0 if the address specified by the operand is 00H to 3FH and MB = 15  
if it is 80H to FFH. Consequently, both the static RAM area of 000H to 03FH and the peripheral hardware area of FF0H  
to FFFH are addressable.  
This addressing mode is applied to the MOV, XCH, INCS, IN, and OUT instructions.  
Example 1. Input Port 2 and store it in “DATA1”.  
DATA1  
EQU  
IN  
2FH  
; “DATA1” is at address 2FH  
A, PORT 2 ; A Port 2  
MOV  
DATA1, A  
; (DATA1) A  
2. Output the data of “BUFF” to Port 5.  
BUFF  
EQU  
MOV  
OUT  
01AH  
; “BUFF” is at address 01AH  
A, BUFF  
; A (BUFF)  
PORT 5, A ; PORT 5 A  
24  
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CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP  
(3) 8-bit direct addressing (mem)  
An addressing mode to specify the whole data memory space directly by the instruction’s operand per 8 bits.  
The specified memory bank (MB) is MB = 0 if the address specified by the operand is 00H to 3EH and MB = 15  
if it is 80H to FEH. Consequently, both the static RAM area of 000H to 03FH and the peripheral hardware area of FF0H  
to FFFH are addressable. In the peripheral hardware area, however, the addresses capable of 8-bit manipulation  
are limited. (See Table 3-4).  
This addressing mode is applied to the MOV and XCH instructions.  
Example 1. Store the serial interface shift register’s (SIO) 8-bit data at addresses 20H and 21H.  
DATA  
EQU  
MOV  
MOV  
020H  
XA, SIO  
; XA SIO  
DATA, XA ; (21H) X, (20H) A  
2. Take the 8-bit data input to the SIO into the XA register pair as well as setting the transfer data  
stored in the XA register pair.  
XCH  
XA, SIO  
; XA SIO  
(4) 4-bit register indirect addressing (@HL)  
An addressing mode to specify the data memory space indirectly according to the content of the HL register per  
4 bits.  
The memory bank (MB) addressed in this addressing mode is fixed to to 0. Consequently, the static RAM area  
of 000H to 03FH alone is addressable. The peripheral hardware area is not addressable. Data in the range of 00H  
to 3FH should be set in the HL register pair.  
This addressing mode is applied widely to data transfer, operation, compare, etc.  
If combined with the HL register pair’s increase or decrease instruction (INCS, DECS), meanwhile, this addressing  
mode allows the data memory space address to be updated freely.  
Example Turn all the contents of 20H to 2FH into FH.  
MOV  
MOV  
MOV  
DECS  
BR  
HL, #2FH  
A, #0FH  
@HL, A  
L
; A FH  
; (HL) A  
LOOP:  
LOOP  
Fig. 3-1 Static RAM Address Updating Method  
× 0H  
× FH  
0 × H  
DECS H  
Direct  
Addressing  
Bit  
@ HL 4-bit  
Manipulation  
4-bit  
INCS L  
DECS L  
Manipulation  
Transfer  
8-bit  
Transfer  
INCS H  
3 × F  
25  
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CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP  
(5) Specific address bit manipulation addressing (fmem. bit)  
An addressing mode to specify each bit of the input/output port, interrupt, etc. flag, etc. of the peripheral hardware  
directly by the instruction’s operand. Consequently, the data memory addresses to which this addressing mode is  
applied are FB0H to FBFH, FF0H to FFFH.  
While the 1-bit direct addressing mode (mem.bit) is applicable only to the bit set/reset/test instructions, this  
addressing mode enables multifarious bit manipulation such as the Boolean operation by the AND1, OR1 and XOR1  
instructions, test and reset by the SKTCLR instruction in addition to them.  
Example 1. Test the basic interval timer interrupt request flag (IRQBT) and, if set, clear IRQBT and reset the  
P63 pin level.  
SKTCLR  
BR  
IRQBT  
NO  
; IRQBT = 1?  
; NO  
CLR1  
PORT 6. 3  
; YES  
2. If P30 and p61 both 1, reset P53.  
P30  
P53  
P61  
(i) SET1  
AND1  
AND1  
SKT  
BR  
CY  
; CY 1  
CY, PORT3. 0 ; CYP30  
CY, PORT6. 1 ; CYP61  
CY  
; CY = 1?  
SETP  
PORT5. 3  
CLR1  
.
;P53 0  
.
SETP: SET1 PORT5. 3  
; P53 1  
; P30 = 1?  
; P61 = 1?  
; P53 0  
(ii) SKT  
PORT3. 0  
SETP  
BR  
SKT  
BR  
CLR1  
.
PORT6. 1  
SETP  
PORT5. 3  
.
SETP: SET1 PORT5. 3  
; P53 1  
26  
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CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP  
(6) Stack addressing  
This addressing mode is for the saving/restoring operation during the interrupting process, subroutine process.  
The data memory is addressed indirectly according to the content of the stack pointer (SP : 8 bits).  
The memory bank (MB) addressed in this addressing mode is fixed to 0. Also as the stack pointer’s high-order  
3 bits are fixed to 001, the addressable area is limited to 020H to 03FH.  
This addressing mode is also applied at register save/restore by the PUSH, POP instruction in addition to the  
interrupting process, subroutine process.  
Note The Evachip packaged on the board for evaluation can address the whole area of Memory bank 0 in this  
addressing mode unlike in the µPD75402A. To eliminate such a difference during the evaluation, a value  
not to access beyond the range of 20H to 3FH should be set in the stack pointer.  
Example 1. Save/restore the register during the subroutine process.  
SUB:  
PUSH  
PUSH  
XA  
HL  
POP  
POP  
RET  
HL  
XA  
2. Transfer the content of the HL register pair to the XA register pair.  
PUSH  
POP  
HL  
XA  
; XA HL  
3. Branch to the address indicated by the (XAHL) register.  
PUSH  
PUSH  
RET  
HL  
XA  
; Branch to address XAHL  
27  
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CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP  
3.2 MEMORY-MAPPED I/O  
The µPD75402A adopts memory-mapped I/O to map such peripheral hardware as the input/output port, serial  
interface at addresses F80H to FFFH in the data memory space shown in Table 3-1. As a result, there is no special  
instruction to control the peripheral hardware; the peripheral hardware is controlled wholly by memory manipu-  
lation instructions (some hardware control mnemonics are available to make the program easy to understand).  
Table 3-3 shows the addressing modes available when operating the peripheral hardware.  
Table 3-3 Applicable Addressing Modes at Peripheral Hardware Operation  
Applicable Addressing Mode  
Specify the bit to be manipulated by the direct  
addressing mem.bit.  
Applicable Hardware  
All the hardware capable of bit  
manipulation  
Bit manipulation  
Specify the bit to be manipulated by the direct  
addressing fmem.bit.  
IE×××, IRQ×××, PORTn.×  
Specify the address to be manipulated by the direct  
addressing mem.  
All the hardware capable of 4-bit  
manipulation.  
4-bit manipulation  
8-bit manipulation  
Specify the address to be manipulated by the direct  
addressing mem. Mem is an even address, however.  
All the hardware capable of 8-bit  
manipulation.  
Table 3-4 summarizes the µPD75402A’s I/O map. The items shown in this table have the following meaning.  
• Symbol:  
A name to indicate the address of the built-in hardware. It can be described in  
the instruction’s operand column. IME is excepted, however.  
• Number of manipulatable bits: The number of applicable processing bits when operating the relevant  
hardware. Such symbols as R/W, indicate whether the relevant hardware is  
readable/writable or not.  
R/W : Readable/Writable  
R
: Readable  
: Writable  
W
• Bit manipulation addressing:  
The applicable bit manipulation addressing when bit manipulating the relevant  
hardware.  
28  
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CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP  
Table 3-4 µPD75402A I/O Map (1/2)  
No. of Manipulatable  
Addressing  
Hardware Name (Symbol)  
Bit  
Remarks  
Address  
F80H  
Manipula-  
tion  
1 Bit  
4 Bits  
8 Bits  
b3  
b2  
b1  
b0  
Bit 0 is fixed to 0.  
Stack pointer (SP)  
W
11 must always  
be written in  
bit 1, 0.  
F85H  
F86H  
W
Basic interval timer mode register (BTM)  
Basic interval timer (BT)  
R
Manipulation  
by EI. DI instruc-  
tion  
FB2H  
(IME)  
FB3H  
FB4H  
FB8H  
FBDH  
FBEH  
FBFH  
Processor clock control register (PCC)  
INT0 mode register (IM0)  
W
W
Bit 2 is fixed to 0.  
0
0
0
0
0
0
0
0
IEBT  
IECSI  
IE0  
IRQBT  
IRQCSI  
IRQ0  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
fmem. bit  
IE2  
IRQ2  
FD0H  
FDCH  
Clock output mode register (CLOM)  
W
Pull-up resistor specify register  
Group A (POGA)  
W
Remarks 1. IE××× is an interrupt enable flag.  
2. IRQ××× is an interrupt request flag.  
29  
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CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP  
Table 3-4 µPD75402A I/O Map (2/2)  
No. of Manipulatable  
Addressing  
Hardware Name (Symbol)  
Bit  
Remarks  
Address  
Manipula-  
tion  
1 Bit  
4 Bits  
8 Bits  
b3  
b2  
b1  
b0  
FE0H  
FE1H  
FE2H  
FE3H  
FE4H  
Serial operation mode register (CSIM)  
W
0 must always be  
written in bit 0.  
* 1  
* 2  
* 3  
mem. bit  
mem. bit  
CSIE  
COI  
WUP  
0
CMDD  
RELD  
CMDT  
RELT  
Bit manipulation  
only is possible  
for all the bits.  
SBI control register (SBIC)  
BSYE ACKD ACKE  
ACKT  
Serial I/O shift register (SIO)  
Slave address register (SVA)  
R/W  
W
11000 must  
FE6H  
FE8H  
FECH  
always be written  
in the high-order  
5 bits.  
Port mode register Group A (PMGA)  
Port mode register Group B (PMGB)  
W
W
FF0H  
FF1H  
FF2H  
FF3H  
FF5H  
FF6H  
R
R
Port 0 (PORT 0)  
Port 1 (PORT 1)  
Port 2 (PORT 2)  
Port 3 (PORT 3)  
Port 5 (PORT 5)  
Port 6 (PORT 6)  
Bits 3 and 1 are  
fixed to 0.  
R
R
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
fmem. bit  
*
1. Bits 3 and 1: W; bit 2: R.  
2. Bits 3 and 2: R; bits 1 and 0: W.  
3. Bits 3 and 1: R/W; bit 2: R; bit 0: W.  
30  
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CHAPTER 4. INTERNAL CPU FUNCTIONS  
4.1 PROGRAM COUNTER (PC) ..... 11 BITS  
An 11-bit binary counter to hold the program memory address information.  
Fig. 4-1 Program Counter Configuration  
PC10 PC9  
PC8  
PC7  
PC6  
PC5  
PC4  
PC3  
PC2  
PC1  
PC0  
The program counter operates as follows.  
• Normal operation  
The content is incremented automatically according to the number of bytes of the instruction every time one is  
executed.  
• Branch instruction (BR, BRCB) execution  
The immediate data indicating the address of the destination of branching is set in the PC.  
• Subroutine call instruction (CALLF) execution and vector interrupt  
The content of the PC at that time is saved in the stack memory and then the address of each destination of  
branching is set in the PC.  
• Return instruction (RET, RETS, RETI) execution  
The content of the stack memory is set in the PC.  
• RESET input  
The low-order 3 bits of the program memory’s address 000H is set in PC10 to PC8 and the content of address  
001H is set in PC7 to PC0 and then initialized. It is possible to start the program from any address.  
31  
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CHAPTER 4. INTERNAL CPU FUNCTIONS  
4.2 PROGRAM MEMORY (ROM) ..... 1,920 WORDS × 8 BITS  
A mask programmable ROM of a 1,920-word × 8-bit configuration. It stores the program, table data, etc.  
The program memory is addressed by the program counter. It is also possible to read the table data in the ROM  
by the table refer instruction (MOVT).  
It is possible to branch to any area of the program memory by the branch instruction, subroutine call instruction  
(see Fig. 4-2). With the relative branch instruction (BR $addr), it is possible to branch to the range of (-15 to -1, +2  
to +16) from the address indicated by the PC after the instruction execution.  
The program memory’s addresses cover 000H to 77FH and the addresses shown below are assigned specially.  
All the areas excluding 000H and 001H are available as the normal program memory.  
Fig. 4-2 Program Memory Map  
Address  
0 0 0 H  
7
0
6
0
5
0
4
0
3
0
0
Reset Start Address  
(high-order 3 bits)  
0 0 1 H  
0 0 2 H  
0 0 3 H  
Reset Start Address (low-order 8 bits)  
INTBT Start Address  
(high-order 3 bits)  
0
0
0
0
0
0
CALLF !faddr  
Instruction Entry  
Address  
INTBT Start Address (low-order 8 bits)  
INT0 Start Address  
(high-order 3 bits)  
0 0 4 H  
0 0 5 H  
0
0
0
0
INT0 Start Address (low-order 8 bits)  
BRCB !caddr  
Instruction Branch  
Address  
INTCSI Start Address  
(high-order 3 bits)  
0 0 8 H  
0 0 9 H  
0
0
0
0
0
BR $addr  
Instruction Relative  
Branch Address  
INTCSI Start Address (low-order 8 bits)  
–15 to –1  
+2 to +16  
~
~
~
~
7 7 F H  
32  
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CHAPTER 4. INTERNAL CPU FUNCTIONS  
4.3 DATA MEMORY (RAM)  
The data memory consists of the data and peripheral hardware areas as shown in Fig. 4-3.  
Fig. 4-3 Data Memory Map  
Data Memory  
0 0 0 H  
Memory Bank  
General  
Register Area  
(4 × 4)  
0 0 3 H  
0 0 4 H  
Data Area  
Static RAM  
(64 × 4)  
Bank 0  
0 2 0 H  
0 3 F H  
(64 × 4)  
(32 × 4)  
Stack Area  
Not built in.  
F 8 0 H  
Peripheral  
Hardware  
Area  
Bank 15  
128 × 4  
F F F H  
(1) Data area  
The µPD75402A’s data area consists of the static RAM (64 words× 4 bits). The data area is used to store processing  
data and is operated by the memory manipulation instruction.  
The static RAM is mapped to Memory bank 0 by 64 × 4 bits. While Bank 0 is mapped as the data area, it is also  
available as the general register area (000H to 003H) and the stack area (020H to 03FH).  
In the static RAM, 1 address consists of 4 bits. It is possible either to operate per 8 bits by the 8-bit memory  
manipulation instruction or to operate per bit by the bit manipulation instruction, however. In the 8-bit manipulation  
instruction, an even address should be specified.  
• General register area  
Operation is possible either by the general register manipulation instruction or by the memory manipulation  
instruction. Up to four 4-bit registers are available. Of the 4 general registers, that part which is not used in the  
program is available as the data area (see 4.4 “GENERAL REGISTER”).  
• Stack area  
The stack area is set by an instruction and is available as the save area at the subroutine or interrupting process  
execution (see 4.6 “STACK POINTER”). In that case, the stack area is at the static RAM’s addresses 020H to 03FH.  
33  
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CHAPTER 4. INTERNAL CPU FUNCTIONS  
(2) Peripheral hardware area  
The peripheral hardware area is mapped to memory bank 15’s addresses F80H to FFFH.  
The operation is performed by the memory manipulation instruction just as in the static RAM. In the peripheral  
hardware, however, the operable bit unit differs from one address to another. It is impossible to access an address  
to which the peripheral hardware is not assigned since the data memory is not built in. (See Table 3-4 “µPD75402A  
I/O Map".)  
Note The static RAM is indefinite at reset. Therefore, it should be initialized to zero at the beginning of the  
program (RAM clear). This must be carried out for sure to avoid unexpected bugs.  
Example Clear all the areas (00H to 3FH) of the static RAM (FFH remains in the HL register, however).  
MOV  
MOV  
MOV  
DECS  
BR  
HL, #3FH  
A, #0H  
LOOP:  
@HL, A: Clear (0) 00H to 3FH  
L
LOOP  
H
DECS  
BR  
LOOP  
34  
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CHAPTER 4. INTERNAL CPU FUNCTIONS  
4.4 GENERAL REGISTER ..... 4 × 4 BITS  
The general register is assigned to a specific address of the data memory. There are four 4-bit registers (H, L,  
X, A).  
While each general register is operated per 4 bits, HL and XA make up register pairs, each of which is operated  
per 8 bits. The HL register pair is available as the data pointer to indirectly address the memory.  
The general register area can be addressed and accessed as an ordinary RAM regardless of whether it is used  
as a register or not.  
Fig. 4-4 General Register Configuration  
X
A
L
0 1 H  
0 3 H  
0 0 H  
0 2 H  
H
Remarks The figure in the lower right corner is the assigned data memory address.  
Fig. 4-5 Register Pair Configuration  
3
3
0
3
0
0
H
X
L
0
3
A
35  
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CHAPTER 4. INTERNAL CPU FUNCTIONS  
4.5 ACCUMULATOR  
In the µPD75402A, the A register and the XA register pair function as accumulators. The 4-bit data process  
instruction is executed mainly by the A register and the 8-bit data process instruction is executed mainly by the XA  
register pair.  
In the bit manipulation instruction, the carry flag (CY) functions as the bit accumulator.  
Fig. 4-6 Accumulators  
Bit Accumulator  
4-Bit Accumulator  
8-Bit Accumulator  
CY  
A
A
X
36  
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CHAPTER 4. INTERNAL CPU FUNCTIONS  
4.6 STACK POINTER (SP) ..... 8 BITS  
The µPD75402A uses a static RAM as the stack memory (LIFO format). The 8-bit register holding the top address  
information of such a stack memory area is the stack pointer (SP). Fig. 4-7 shows its format.  
As the SP’s high-order 3 bits are fixed to 001, the stack area is at the static RAM’s addresses 020H to 03FH.  
The SP is decremented before write (save) in the stack memory and is incremented after read (restore) from the  
stack memory. Figs. 4-8 and 4-9 show the data saved and restored by each stacking operation.  
The SP sets the initial value by the 8-bit data transfer instruction to determine the stack area. It is impossible to  
read the content of the SP.  
Zero is always written in the SP’s bit 0.  
It is recommended to initialize by writing 40H in the SP and use the built-in RAM’s maximum address (03FH) and  
beyond as the stack area.  
The content of the SP turns indeterminate at RESET input, so it must be initialized to your desired value by the  
program initialization routine.  
Note The SP of the Evachip packaged on the board for evaluation can address all the areas of 000H to 0FFH unlike  
in the µPD75402A. To eliminate such a difference at evaluation, the SP should be set not to access beyond  
the range of 020H to 03FH.  
Example SP initialize  
MOV  
MOV  
XA, #40H  
SP, XA  
; SP 40H  
Fig. 4-7 Stack Pointer Configuration  
Address  
F80H  
7
0
6
0
5
1
4
3
2
1
0
Symbol  
SP  
SP4  
SP3  
SP2  
SP1  
SP0  
0 Fixed  
37  
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CHAPTER 4. INTERNAL CPU FUNCTIONS  
Fig. 4-8 Data Saved to Stack Memory  
PUSH Instruction  
Stack  
CALLF Instruction  
Interrupt  
Stack  
Stack  
SP - 6  
0
0
PC10 - PC8  
0
0
PC10 - PC8  
SP - 4  
0
0
0
SP - 5  
SP - 4  
SP - 3  
SP - 2  
0
0
0
0
SP - 3  
SP - 2  
Register Pair  
Low Order  
SP - 2  
PC3 - PC0  
PC7 - PC4  
PC3 - PC0  
PC7 - PC4  
Register Pair  
High Order  
SP - 1  
SP  
SP - 1  
SP  
0
IST0  
PSW  
SK2 SK1 SK0  
0
CY  
SP - 1  
SP  
Fig. 4-9 Data Restored from Stack Memory  
POP Instruction  
Stack  
RET, RETS Instruction  
RETI Instruction  
Stack  
Stack  
Register Pair  
Low Order  
0
0
PC10 - PC8  
0
0
PC10 - PC8  
SP  
SP  
SP  
Register Pair  
High Order  
0
0
0
0
0
0
0
SP + 1  
SP + 2  
SP + 1  
SP + 2  
SP + 3  
SP + 4  
SP + 1  
SP + 2  
SP + 3  
SP + 4  
PC3 - PC0  
PC7 - PC4  
PC3 - PC0  
PC7 - PC4  
0
IST0  
PSW  
SK2 SK1 SK0  
0
CY  
SP + 5  
SP + 6  
38  
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CHAPTER 4. INTERNAL CPU FUNCTIONS  
4.7 PROGRAM STATUS WORD (PSW) ..... 8 BITS  
The program status word (PSW) consists of various flags concerning closely the processor operation. Fig. 4-10  
shows its configuration.  
Saved to the stack memory per 8 bits at the interrupt acceptance and restored from the stack memory per 8 bits  
at the RETI instruction execution (see Figs. 4-8 and 4-9).  
Fig. 4-10 Program Status Word Configuration  
7
6
5
4
3
0
2
1
0
0
0
CY  
SK2  
SK1  
SK0  
IST0  
Interrupt Status Flag  
Skip Flag  
Carry Flag  
The PSW is not assigned to the data memory space. So it is impossible to operate each flag by the memory  
manipulation instruction. The carry flag (CY) alone is operable by a dedicated instruction, however.  
IST0 turns 0 and SK0 to SK2 and CY turn indeterminate at RESET input.  
(1) Carry flag (CY)  
The carry flag is a 1-bit flag to store the overflow occurrence information at the operation instruction with carry  
(ADDC) execution.  
The carry flag also has the function of the bit accumulator, so it can perform Boolean operation with the bit address  
specify data memory and can store its results.  
The carry flag is operated by a dedicated instruction irrespective of the other PSW bits.  
The carry flag turns indeterminate with the RESET input.  
Table 4-1 Carry Flag Manipulation Instructions  
Instruction (Mnemonic)  
SET1 CY  
Carry Flag Operation, Process  
Carry flag manipulation  
dedicated  
Set (1) CY  
CLR1 CY  
Clear (0) CY  
NOT1 CY  
Invert the content of CY  
SKT CY  
Skip if the content of CY is 1  
Bit Boolean instruction  
Interrupting process  
AND1 CY, fmem.bit  
OR1 CY, fmem.bit  
XOR1 CY, fmem.bit  
At interrupt execution  
Take AND/OR/XOR of the contents bit of the specified bit and CY  
and store the result in CY  
Save to the stack memory in 8 bits parallel to the other PSW bits  
---------------------------------------------------------------------------------------------------------  
RETI  
Restore from the stack memory in parallel to the other PSW  
39  
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CHAPTER 4. INTERNAL CPU FUNCTIONS  
Example Take AND of bit 3 at address 3FH and P33 and set the result in CY.  
SET1  
SKT  
CY  
; CY1  
3FH. 3  
; Skip if bit 3 at address 3FH is 1  
CLR1  
AND1  
CY  
; CY0  
; CYCYP33  
CY, PORT 3. 3  
(2) Skip flag (SK2, SK1, SK0)  
The skip flag is a flag to store the skip status. It is set/reset automatically as the CPU executes an instruction.  
It is impossible for the user to operate it directly by the program.  
(3) Interrupt status flag (IST0)  
The interrupt status flag is a flag to store the status of the process under execution (for details, see Table 6-3).  
It is impossible for the user to operate it directly by the program.  
Table 4-2 Interrupt Status Flag Indication Content  
Status of Process  
under Execution  
Processing Content and  
Interrupt Control  
IST0  
0
1
Status 0  
In a normal programming process.  
Enable to accept any interrupt.  
Status 1  
In an interrupting process.  
Disable to accept any interrupt.  
The content of IST0 is saved to the stack memory as part of the PSW if the interrupt is accepted and then set  
automatically to 1 and set to 0 by the RETI instruction.  
As it is impossible to operate IST0 by an instruction, it is always that IST0 = 1 during the interrupting process.  
So it is impossible to multiplex interrupts, all the interrupt requests having occurred during the interrupting process  
are pending until the interrupting process under execution ends (for details, see CHAPTER 6 “INTERRUPT  
FUNCTIONS”).  
40  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
5.1 DIGITAL INPUT/OUTPUT PORTS  
The µPD75402A has the following digital input/output ports on chip: Ports 0 through 3, 5 and 6.  
The µPD75402A uses memory mapped I/O, and all input/output ports are mapped onto data memory space.  
All data memory handling instructions can be used on all of the ports, and a wide variety of bit operations can  
be performed in addition to 4-bit input/output.  
Note On the µPD75402A it is not possible to perform 8-bit input/output by pairing two ports.  
Fig. 5-1 Digital Input/Output Port Data Memory Addresses  
Address  
FF0H  
3
2
1
0
Symbol  
PORT0  
PORT1  
PORT2  
PORT3  
P03  
0
P02  
P12  
P22  
P32  
P01  
0
P00  
P10  
P20  
P30  
FF1H  
FF2H  
P23  
P33  
P21  
P31  
FF3H  
FF5H  
FF6H  
P53  
P63  
P52  
P62  
P51  
P61  
P50  
P60  
PORT5  
PORT6  
41  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
5.1.1 Digital Input/Output Port Types, Characteristics and Configuration  
The different types of digital input/output ports are shown in Table 5-1, and the configuration of each port is shown  
in Figs. 5-2, 5-3, 5-4 and 5-5.  
Table 5-1 Digital Input/Output Port Types and Characteristics  
Port  
(Symbol)  
Function  
4-bit input  
Operation/Characteristics  
Remarks  
PORT0  
PORT1  
Can always be read or tested  
regardless of dual-function pin  
operating mode.  
Pins also function as SO/SB0, SI,  
SCK, INT0, INT2. (See chapter 1.)  
PORT3*  
4-bit input/output  
Can be set to input or output  
mode bit by bit.  
PORT2  
PORT6*  
Can be set to input or output  
mode as a 4-bit unit.  
Port 2 pins also function as PCL.  
PORT5*  
4-bit input/ output  
(N-ch open-drain,  
up to 10 V)  
Can be set to input or output  
mode as a 4-bit unit.  
Internal pull-up resistor can be  
specified bit by bit by mask  
option. (µPD75402A only.)  
*
LED direct drive capability  
On the µPD75402A, a pull-up resistor can be incorporated on chip for all port pins except pins P00, P10. On the  
µPD75P402, a pull-up resistor can be incorporated on chip for all port pins except pins P00, P10, and P50 through  
P53 (see section 5.5).  
P10 has a dual function as the external vectored interrupt input pin, and has an on-chip circuit for noise elimination  
by the sampling clock (see section 6.2 for details).  
Upon RESET input the output latches of ports 2, 3, 5 and 6 are cleared, the output buffer is turned off, and input  
mode is set.  
42  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
Fig. 5-2 Configuration of Ports 0 and 1  
Internal  
SCK  
SI  
SCK  
SO  
VDD  
Pull-Up  
Resistors  
Selcetor  
CSIM  
POGA  
Bit 0  
P-ch  
P00  
PO0  
P01/SCK  
P02/SO/SB0  
P03/SI  
Output Buffer with Capability  
of Switching between Push-Pull  
Output and N-ch Open-Drain Output  
Input Buffer  
VDD  
Pull-Up  
Resistor  
POGA  
Bit 1  
PO1  
P-ch  
Input Buffer  
or fXX/64  
Φ
P10/INT0  
P12/INT2  
Noise Elimination Circuit  
Input Buffer with  
Hysteresis Characteristics  
INT2  
INT0  
43  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
Fig. 5-3 Configuration of Port 3  
VDD  
PM 3 n=0  
PM 3 n=1  
Input Buffer  
Pull-Up  
Resistor  
M
P
X
POGA  
Bit 3  
PO3  
P-ch  
Output  
Buffer  
P 3 n  
Output Latch  
PM 3 n  
PMGA Bit n  
Remarks n = 0 to 3  
44  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
Fig. 5-4 Configuration of Ports 2 and 6  
VDD  
Pull-up  
Resistors  
POGA  
Bit m  
P-ch  
POm  
Input Buffer  
PMm = 0  
M
P
PMm = 1  
X
P m 0  
P m 1  
P m 2  
P m 3  
Output  
Buffer  
*
PM2/  
PM60 to  
63  
PMGB Bit 2,  
PMGA bits  
4 to 7  
*
Input/output mode specification is performed by bit 2 (PM2) of PMGB for port 2 and by bits 4 to 7 (PM60 to 63)  
of PMGA for port 6.  
Remarks m = 2 or 6  
45  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
Fig. 5-5 Configuration of Port 5  
VDD  
Pull-Up Resistors  
(Mask Option; µPD75402A  
Only)  
Input Buffer  
PM5=0  
M
P
X
PM5=1  
P50  
P51  
P52  
P53  
N-ch  
Open-Drain  
Output  
Buffer  
PM5  
PMGB  
Bit 5  
5.1.2 Input/Output Mode Setting  
The input/output mode for each input/output port is set by a port mode register as shown in Fig. 5-6. For port  
3, input/output can be specified bit by bit by port mode register group A (PMGA). Input/output is specified in 4-bit  
units by PMGB for ports 2 and 5, and by PMGA for port 6.  
Each port operates as an input port when the corresponding port mode register bit is “0”, and as an output port  
when “1”.  
Since, when output mode is selected by setting the port mode register, the output latch contents are simulta-  
neously output to the output pin, the output latch contents must be overwritten in advance with the required value  
before output mode is set.  
Port mode register group A and B are each set by an 8-bit memory handling instruction.  
With a RESET input, all bits of each port mode register are cleared to zero, and thus the output buffer is turned  
off and all ports are set to input mode.  
46  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
Fig. 5-6 Format of Port Mode Registers  
Port Mode Register Group A  
Address  
7
6
5
4
3
2
1
0
Symbol  
PMGA  
FE8H PM63 PM62 PM61 PM60 PM33 PM32 PM31 PM30  
P30 Input/Output Specification  
P31 Input/Output Specification  
P32 Input/Output Specification  
P33 Input/Output Specification  
Port 6 (P60 to P63) Input/Output Specification*  
Port Mode Register Group B  
Address  
FECH  
7
6
5
4
3
2
1
0
Symbol  
PMGB  
PM5  
PM2  
Port 2 (P20 to P23) Input/Output Specification  
Port 5 (P50 to P53) Input/Output Specification  
Specification  
0
1
Input mode (output buffer off)  
Output mode (output buffer on)  
*
Port 6 input/output specification is performed as a 4-bit unit. Ensure that 0000 or 1111 is written to PMGA bits  
7 through 4.  
5.1.3 Digital Input/Output Port Handling Instructions  
As all the input/output ports in the µPD75402A are mapped onto data memory space, all data memory handling  
instructions can be used. Those data memory handling instructions which are considered particularly useful for  
input/output pin operations are shown in Table 5-2 together with their scope of application.  
47  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
(1) Bit handling instructions  
Direct addressing of specific address bits (fmem.bit) can be used on all digital input/output ports.  
Example To OR P50 and P31 and output the result to P61.  
SET1  
AND1  
OR1  
SKT  
CY  
; CY 1  
; CY CY P50  
; CY CY P31  
CY, PORT5.0  
CY, PORT3.1  
CY  
BR  
CLRP  
SET1  
PORT6.1  
; P61 1  
CLRP : CLR1  
PORT6.1  
; P61 0  
(2) 4-bit handling instructions  
All 4-bit memory handling instructions can be used, such as MOV, XCH, ADDS and INCS, in addition to the IN/  
OUT instructions.  
Example 1. To output accumulator contents to port 3.  
OUT  
PORT3, A  
2. To add the accumulator value to the data output to port 5, and output the result.  
MOV  
ADDS  
NOP  
HL, #PORT5  
A, @HL  
; A A + PORT5  
MOV  
@HL, A  
; PORT5 A  
Table 5-2 List of Input/Output Pin Handling Instructions  
PORT 0  
PORT 1  
PORT2  
PORT 3  
PORT5  
PORT 6  
IN A, PORTn  
OUT PORTn, A  
SET1 PORTn.bit  
CLR1 PORTn.bit  
SKT  
SKF  
PORTn.bit  
PORTn.bit  
AND1 CY, PORTn.bit  
OR1 CY, PORTn.bit  
XOR1 CY, PORTn.bit  
48  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
5.1.4 Digital Input/Output Port Operations  
Port and port pin operations when a data memory handling instruction is executed for a digital input/output port  
differ according to the input/output mode setting (see Table 5-3). This is because, as can be seen from the input/  
output port configurations, data fetched onto the internal bus is treated as pin data in input mode and as output  
latch data in output mode.  
(1) Operations when input mode is set  
When a test instruction such as the SKT instruction, or an instruction which fetches port data as 4 bits onto the  
internal bus (IN, MOV and bit operation instructions) is executed, individual pin data is manipulated.  
When an instruction which performs a 4-bit transfer of accumulator contents to a port (OUT or MOV instruction)  
is executed, the accumulator data is latched in the output latch. The output buffer remains off.  
When an XCH instruction is executed, the individual pin data is input to the accumulator, and the accumulator  
data is latched in the output latch. The output buffer remains off.  
When an INCS instruction is executed, data comprising the individual pin data (4-bit) + 1 is latched in the output  
latch. The output buffer remains off.  
When a bit-wise data memory rewriting instruction such as the SET1/CLR1/SKTCLR instructions is executed, the  
output latch for the specified bit can be rewritten as directed by the instruction, but the contents of the output latches  
for the other bits are undefined.  
(2) Operations when output mode is set  
When a test instruction, bit input instruction, or an instruction which fetches port data as 4 bits onto the internal  
bus is executed, the output latch contents are manipulated.  
When an instruction which performs a 4-bit transfer of accumulator contents is executed, when the output latch  
data is overwritten it is simultaneously output from the pins.  
When an XCH instruction is executed, the output latch contents are transferred to the accumulator, and the  
accumulator contents are latched in the output latches and output from the pins.  
When an INCS instruction is executed, data comprising the output latch contents + 1 is latched in the output  
latches and output from the pins.  
When a bit output instruction is executed, the specified output latch bit is rewritten and output from the pin.  
49  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
Table 5-3 Operations with Input/Output Port Handling Instructions  
Port and Individual Pin Operations  
Instruction Executed  
Input Mode  
Tests pin data.  
Output Mode  
Tests output latch data.  
SKT  
SKF  
PORTn.bit  
PORTn.bit  
Operation between pin data and  
CY  
Operation between output latch  
data and CY  
AND1 CY, PORTn.bit  
OR1 CY, PORTn.bit  
XOR1 CY, PORTn.bit  
Transfers pin data to accumula-  
tor.  
Transfers output latch data to  
accumulator.  
IN  
A, PORTn  
MOV A, PORTn  
Transfers accumulator data to  
output latches. (Output buffer  
remains off.)  
Transfers accumulator data to  
output data to output latches,  
and outputs data from pins.  
OUT PORTn, A  
MOV PORTn, A  
Transfers pin data to accumula-  
tor, and transfers accumulator  
data to output  
Exchanges data between output  
latches and accumulator.  
XCH A, PORTn  
latches. (Output buffer remains  
off.)  
Latches pin data + 1 in output  
latches.  
Increments output latch contents  
by 1.  
INCS PORTn  
Specified bit output latch is  
rewritten as per instruction,  
but output latches for other bits  
are undefined.  
Changes output pin status as per  
instruction.  
SET1 PORTn.bit  
CLR1 PORTn.bit  
SKTCLR PORTn.bit  
50  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
5.1.5 Internal Pull-up Resistors  
The µPD75402A can incorporate internal pull-up resistors for all port pins except P00 and P10. The µPD75P402  
can incorporate internal pull-up resistors for all port pins except P00, P10, and P50 through P53.  
As shown in Table 5-4, internal pull-up resistors can be specified by software or by a mask option (although  
specification by mask option is not possible on the µPD75P402).  
The pull-up resistor specification register which specifies internal pull-up resistors for ports 0 through 3 and 6  
(POGA) is an 8-bit write-only register. Its format is shown in Fig. 5-7. POGA is set by an 8-bit write instruction. Reading  
and bit manipulation is not possible. RESET input clears this register to zero.  
Internal pull-up resistor specification for port 3 is valid only for input pins specified as in input mode. The status  
of pins specified as in output mode is “without pull-up resistor” irrespective of the POGA setting.  
Table 5-4 Internal Pull-Up Resistor Specification for Each Port  
Port (Pin Name)  
Port 0 (P01 to P03)*1  
Port 1 (P12)*1  
Internal Pull-Up Resistor Specification Method  
3-bit unit internal specification by software  
Internal specification by software  
Specification Bits  
POGA.0  
POGA.1  
Port 2 (P20 to P23)  
Port 3 (P30 to P33)  
Port 6 (P60 to P63)  
4-bit unit internal specification by software  
POGA.2  
POGA.3  
POGA.6  
Port 5 (P50 to P53)  
Bit-wise internal specificationby mask option*2  
*
1. Pull-up resistors cannot be incorporated into the P00 and P10 pins.  
2. On the µPD75P402, pull-up resistors cannot be incorporated into port 5.  
51  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
Fig. 5-7 Format of Pull-Up Resistor Specification Register  
Address  
FDCH  
7
6
5
4
3
2
1
0
Symbol  
POGA  
PO6  
PO3  
PO2  
PO1  
PO0  
Port 0 (P01 to P03)  
Port 1 (P12)  
Port 2 (P20 to P23)  
Port 3 (P30 to P33)  
Port 6 (P60 to P63)  
Specification  
0
1
Pull-up resistor not incorporated  
Pull-up resistor incorporated  
The timing for switching of pull-up resistor presence/ absence by the setting of the pull-up resistor specification  
register (POGA) is shown in Fig. 5-8.  
Fig. 5-8 Pull-Up Resistor Incorporation Switching Timing  
2-Machine Cycles  
Φ 3  
Φ
0
Φ 1  
Instruction  
Execution  
Manipulation Instruction  
POGA  
Remarks Φo through Φ3 are internal operation timing clock pulses.  
After pull-up resistor incorporation has been specified by overwriting POGA, in consideration of the external load  
capacity the pin level should be stabilized by execution of an NOP instruction etc. before an input/output instruction  
is executed.  
Example To perform input after specifying incorporation of a pull-up resistor in port 1.  
MOV  
MOV  
XA, #02H  
; Pull-up resistor incorporated in port 1  
POGA, XA  
Wait until pin level is stabilized in consideration of  
external load capacity.  
IN  
A, PORT1  
52  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
5.1.6 Digital Input/Output Port Input/Output Timing  
The timing for outputting data to the output latch and fetching pin data or output latch data onto the internal bus  
is shown in Fig. 5-9.  
Fig. 5-9 Digital Input/Output Port Input/Output Timing  
(a) Data fetch by 1-machine-cycle instruction  
1-Machine Cycles  
Instruction  
Execution  
Manipulation  
Instruction  
Input Timing  
(b) Data fetch by 2-machine-cycle instruction  
2-Machine Cycles  
Instruction  
Execution  
Manipulation Instruction  
Input Timing  
(c) Data latching by 1-machine-cycle instruction  
Φ 3  
Manipulation Instruction  
Φ
0
Φ
1
Instruction  
Execution  
Output Latch  
(Output Pin)  
(d) Data latching by 2-machine-cycle instruction  
Φ 0  
Φ
1
Instruction  
Execution  
Manipulation Instruction  
Output Latch  
(Output Pin)  
53  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
5.2 CLOCK GENERATION CIRCUIT  
The clock generation circuit supplies various clocks to the CPU and peripheral hardware, and controls the  
operating mode of the CPU.  
5.2.1 Clock Generation Circuit Configuration  
The configuration of the clock generation circuit is shown in Fig. 5-10.  
Fig. 5-10 Clock Generation Circuit Block Diagram  
• Basic Interva Timer (BT)  
• Clock Output Circuit  
• Serial Interface  
• INT0 Noise Eliminator  
• Clock Output Circuit  
X1  
VDD  
System  
Clock  
1/16 to 1/512  
fXX or fX  
Oscillation  
Circuit  
Frequency Divider  
1/2 1/16  
X2  
STOP  
Oscillation  
Frequency  
Divider  
Φ
1/4  
• CPU  
• INT0 Noise  
Eliminator  
• Clock Output  
Circuit  
PCC  
PCC0  
PCC1  
PCC2  
4
HALT F/F  
S
HALT*  
PCC3  
STOP*  
R
Q
Clear  
all bits  
RESET Input Rising Edge  
Detection Signal  
STOP F/F  
Clear  
PCC2  
Q
S
RESET Input Falling Edga  
Detection Signal  
R
Standby Release Signal from  
Interrupt Control Circuit  
Remarks 1. fXX = System clock frequency  
2. fX = External clock frequency  
3. PCC: Processor clock control register  
4. 1 clock cyck (fCY) of Φ is 1 machine cycle of an instruction.  
Instruction execution  
*
54  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
5.2.2 Clock Generation Circuit Function and Operaion  
The clock generation circuit generates the CPU clock ( Φ ) and various clocks for supply to peripheral hardware,  
and controls the CPU operating mode, such as standby mode etc.  
Clock generation circuit operation is determined by the processor clock control register (PCC).  
Upon RESET input, the PCC is cleared to 0000 and the µPD75402A operates in low-speed mode (15.3 µs: when  
operating at 4.19 MHz).  
Peripheral hardware is supplied with various clocks scaled from the system clock generation circuit output (fXX  
in the case of crystal/ceramic oscillation, and fX when an external clock is used) by the frequency divider.  
From this section on, only fXX is used when expressing the speed of the various clocks; for an external clock, this  
should be replaced by fX.  
The operation of each block is described below.  
(1) Processor clock control register (PCC)  
The PCC is a 4-bit register which performs selection of the CPU clock Φ and control of the CPU operating mode.  
The format of the PCC is shown in Fig. 5-11.  
When bit 3 or bit 2 is set (1), standby mode is selected. When standby mode is released by the Standby Release  
signal, both bits are automatically cleared and the normal operating mode is reestablished (see CHAPTER 7  
“STANDBY FUNCTION” for details).Setting of the low-order 2 bits of the PCC is performed by a 4-bit memory  
handling instruction. At this time, ensure that bits 3 and 2 are reset to “0” so that the pattern “00××” is written.  
Bits 3 and 2 are set (1) by the STOP instruction and the HALT instruction respectively.  
RESET input clears the PCC to 0000.  
Example 1. To set the machine cycle to 0.95 µs (fXX = 4.19 MHz).  
SEL  
MB15  
MOV  
MOV  
A, #0011B  
PCC, A  
2. To set the machine cycle to 1.63 µs (fXX = 4.91 MHz).  
SEL  
MB15  
MOV  
MOV  
A. # 0010B  
PCC, A  
3. To select the STOP mode. (Be sure to include an NOP instruction after a STOP or HALT instruction.)  
STOP  
NOP  
55  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
Fig. 5-11 Processor Clock Control Register Format  
Address  
FB3H  
3
2
1
0
Symbol  
PCC  
PCC3 PCC2 PCC1 PCC0  
CPU clock selection bits when fXX 4.19 MHz  
(
) : When fXX = 4.19 MHz  
CPU Clock Frequency  
Φ Output = fXX/64 (65.5 kHz)  
Setting prohibited  
1 Machine Cycle  
15.3 µs  
0
0
1
1
0
1
0
1
Φ = fXX/8 (524 kHz)  
Φ = fXX/4 (1.05 MHz)  
19.1 µs  
0.95 µs  
When 4.19 MHz < fXX 5.0 MHz  
(
) : When fXX = 4.19 MHz  
CPU Clock Frequency  
1 Machine Cycle  
0
0
1
1
0
1
0
1
Φ Output = fXX/64 (76.7 kHz)  
Setting prohibited  
13 µs  
1.63 µs  
Φ = fXX/8 (614 kHz)  
Setting prohibited  
fXX : Main system clock oscillation circuit output frequency  
CPU operating mode control bit  
0
0
1
1
0
1
0
1
Normal operating mode  
HALT mode  
STOP mode  
Setting prohibited  
Note When using a calue of fXX such that 4.19 MHz < fXX 5.0 MHz, if maximum speed mode : Φ fXX/4 (PCC1, PCC0  
= 11) is set as CPU clock frequency, 1 machine cycle is less than 0.95 µs and the standard minimum value  
0.95 µs is not kept.  
Therefore, is this case, PCC1, PCC0 = 11 cannot be set, so it should be used with PCC1, PCC0 = 00 or 10.  
As a result, the combination of “fXX = 4.19 MHz, PCC1, PCC0 = 11” is maximum speed selection (1 machin  
cycle = 0.95 µs) as CPU clock.  
56  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
(2) System clock oscillation circuit  
The system clock oscillation circuit oscillates by means of a crystal resonator or ceramic resonator connected  
to the X1 and X2 pins (standard: 4.194304 MHz).  
An external clock can also be input.  
Fig. 5-12 System Clock Oscillation Circuit External Circuitry  
(a) Crystal/ceramic oscillation  
(b) External clock  
µPD75402A  
X1  
VDD  
External  
Clock  
µPD75402A  
VDD  
X1  
X2  
X2  
Crystal Resonator  
or Ceramic Oscillator  
(Standard 4.194304 MHz)  
Note 1. When an external clock is input, STOP mode cannot be set. If STOP mode is set, the X1 pin is shorted  
to VSS (GND potential) internally to suppress clock oscillation circuit leakage.  
2. When using the system clock generation circuit the area enclosed in dotted line in Fig. 5-12 should be  
wired in order to avoid effects of wiring capacitance etc., as shown below.  
• Minimize the length of wiring  
• Do not cross other signal lines, or position wiring close to a variable high current.  
• The connecting point of the oscillator capacitor should always be of the same potential as VDD. Do  
not connect it to the supply pattern where there is a high current.  
• Do not pick up the signal from the oscillator.  
Fig. 5-13 Example of Poor Resonator Connection Circuit (1/2)  
(a) Long connection circuit wiring  
(b) Crossed signal lines  
PORTn  
VDD  
µPD75402A  
n = 0,1,2,3,5,6,  
µPD75402A  
VDD  
VDD  
VDD  
X1  
X2  
X1  
X2  
57  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
Fig. 5-13 Example of Poor Resonator Connection Circuit (2/2)  
(c) Signal line close to varyin high current  
(d) Current flows an oscillator power supply line.  
(potentials at A, B and C fluctuate.)  
VDD  
µPD75402A  
VDD  
µPD75402A  
VDD  
VDD  
A
PORTn  
X1  
X2  
X1  
X2  
High  
current  
C
B
(e) Signal is picked up.  
µPD75402A  
VDD  
X1  
X2  
58  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
5.2.3 CPU Clock Setting  
The CPU clock Φ is the clock supplied to the µPD75402A’s internal CPU, and the reciprocal of this clock is the  
minimum instruction execution time (defined in this manual as 1 machine cycle).  
On the µPD75402A, Φ can be switched in 3 steps by setting the PCC. In other words, with the same system clock  
oscillator frequency fXX, the minimum instruction execution time can be changed in 3 steps. By using this function  
to select operation at high speed (0.95 µs: When operating at 4.19 MHz) when the power supply voltage is 5 V and  
low-speed operation (15.3 µs: When operating at 4.19 MHz) in backup mode, applications can be implemented in  
which reduced current consumption and low-power operation is possible, which is an extremely useful facility.  
Fig. 5-14 Use of Variable Minimum Instruction Execution Time Function  
5V  
Supply Voltage  
3V  
0.95 µs  
15.3 µs  
0.95 µs  
Minimum Instruction  
Execution Time  
(4.19 MHz Operation)  
Note As explained in the previous section, Φ is changed by a 4-bit memory handling instruction, but after a PCC  
change, operation is at the pre-change Φ rate for the number of machine cycles shown in Table 5-5.  
Example  
;
;
Assume PCC = 0011.  
MOV  
MOV  
BR  
A, #0000  
0.95 µs/4.19 MHz  
PCC, A  
PCC 0000  
16 machine cycles  
15.3 µs/4.19 MHz  
59  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
As the PCC is set in 0 by RESET input, Φ is reset-started at the slowest speed (state in which the operating voltage  
range is wide). For this reason, in a system with a slow supply voltage rise (such as a system with a high- capacitance  
capacitor connected), correct operation is possible even when an adequate supply voltage cannot be attained after  
a power-on reset.  
Fig. 5-15 Change of Φ after Power-On Reset  
5V  
Supply  
Voltage  
0V  
RESET Input Signal  
Φ
Progran  
Start  
Change (By Program)  
CPU  
Operation  
Oscillator  
Stabilization  
Time  
Low-Speed  
Operation  
High-Speed  
Operation  
Table 5-5 Maximum Time Required for Change of CPU Clock  
Max. Time Required for Change of  
Max. No. of Machine Cycles  
Required for Change of Φ  
PCC Before Change  
0000  
PCC After Change  
Φ * (When fXX = 4.19 MHz)  
0010  
0011  
0000  
0011  
0000  
0010  
1
1
8
0010  
0011  
15.3 µs  
8
16  
16  
*
When standby mode is not set until Φ changes.  
60  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
5.2.4 Differences Between µPD75402A and µPD75402  
Part of the clock generation circuit differs between the µPD75402A and the µPD75402.  
The µPD75402 does not include the sections enclosed in dotted lines.  
Fig. 5-16 Clock Generation Circuit - Differences between µPD75402A and µPD75402  
• Basic Interva Timer (BT)  
• Clock Output Circuit  
• Serial Interface  
• INT0 Noise Eliminator  
• Clock Output Circuit  
X1  
VDD  
System  
Clock  
Oscillation  
Circuit  
1/16 to 1/512  
fXX or fX  
Frequency Divider  
1/2 1/6  
X2  
STOP  
Oscillation  
Frequency  
Divider  
Φ
1/4  
• CPU  
• INT0 Noise  
Eliminator  
• Clock Output  
Circuit  
PCC  
0
PCC1  
PCC2  
4
HALT F/F  
S
HALT*  
PCC3  
STOP*  
R
Q
Clear  
all bits  
RESET Input Rising Edge  
Detection Signal  
STOP F/F  
Clear  
PCC2  
Q
S
RESET Input Falling Edga  
Detection Signal  
R
Standby Release Signal from  
Interrupt Control Circuit  
*
Instruction execution  
Remarks 1. fXX = System clock frequency  
2. fX = external clock frequency  
3. PCC: Processor clock control register  
4. 1 clock cycle (tCY) of Φ is 1 machine cycle of an instruction.  
61  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
Next, the processor clock control register (PCC) of the µPD75402 is shown below. Setting of bit 1 of the PCC is  
performed by a 4-bit memory handling instruction. At this time, ensure that bits 3, 2 and 0 are reset to “0” so that  
the pattern “00 × 0” is written.  
Fig. 5-17 µPD75402 Processor Clock Control Register Format  
Address  
FB3H  
3
2
1
0
0
Symbol  
PCC  
PCC3 PCC2 PCC1  
CPU clock selection bits when fXX 4.19 MHz  
(
) : When fXX = 4.19 MHz  
CPU Clock Frequency  
Φ Output = fXX/64 (65.5 kHz)  
Φ = fXX/8 (524 kHz)  
1 Machine Cycle  
15.3 µs  
0
1
19.1 µs  
When 4.19 MHz < fXX 5.0 MHz  
(
) : When fXX = 4.91 MHz  
CPU Clock Frequency  
Φ Output = fXX/64 (76.7 kHz)  
Φ = fXX/8 (614 kHz)  
1 Machine Cycle  
13 µs  
0
1
1.63 µs  
fXX : Main system clock oscillation circuit output frequency  
CPU operating mode control bit  
0
0
1
1
0
1
0
1
Normal operating mode  
HALT mode  
STOP mode  
Setting prohibited  
Note 1. Ensure that 0 is always written to PCC bit 0.  
2. Unlike the µPD75402A, in the µPD75402, switching Φ is 2-step rather than 3-step. High-speed mode (0.95  
µs at 4.19 MHz) cannot be specified.  
62  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
5.3 CLOCK OUTPUT CIRCUIT  
The clock output circuit outputs clock pulses from the P22/PCL pin, and is used to supply clock pulses to peripheral  
LSIs, etc.  
5.3.1 Clock Output Circuit Configuration  
The configuration of the clock output circuit is shown in Fig. 5-18.  
Fig. 5-18 Clock Output Circuit Configuration  
From Clock  
Generation  
Circuit  
Output  
Buffer  
Φ
Selector  
fXX/26  
P22/PCL  
PORT2.2  
P22  
Output  
Latch  
PMGB Bit 2  
Port 2 Input/  
Output Mode  
Specification Bit  
CLOM3  
0
CLOM1 CLOM0 CLOM  
4
Internal Bus  
Remarks When switching between clock output enabled/disabled states, consideration has been given to ensuring  
that a short pulse is not output.  
63  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
5.3.2 Clock Output Mode Register (CLOM)  
CLOM is a 4-bit register used to control clock output.  
CLOM is set by a 4-bit memory handling instruction. Bit handling instructions cannot be used. Also, this register  
cannot be read.  
RESET input clears CLOM to zero and selects the clock output disabled state.  
Fig. 5-19 Clock Output Mode Register Format  
Address  
FD0H CLOM3  
3
2
0
1
0
Symbol  
CLOM  
CLOM1 CLOM0  
Clock output frequency selection bits ( ) : When fXX = 4.19 MHz  
0
0
1
1
0
1
0
1
Φ output* (1.05 MHz, 524 kHz, 65.5 kHz)  
Setting prohibited  
fXX/26 output (65.5 kHz)  
* Φ is the CPU clock selected by PCC  
Clock output enable/disable bit  
0
0
Output disabled  
Output enabled  
Note Ensure that 0 is written to bit 2 of CLOM.  
64  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
5.3.3 Clock Output Procedure  
Clock pulse output is performed by the following procedure.  
(i) Set the clock output mode register.  
(ii) Write 0 to the P22 output latch.  
(iii) Set the port 2 input/output mode to output.  
This procedure may be reversed depending on the treatment of P22/PCL prior to clock output.  
Example 1. To output a 65.5 kHz (at 4.19 MHz operation) clock from the PCL/P22 pin. (The PCL/P22 pin outputs  
the clock from the high-impedance state.)  
MOV  
MOV  
CLR1  
MOV  
MOV  
A, #1011B  
CLOM, A  
PORT2.2  
; CLOM = 1011B  
; P22 0  
XA, #04H  
PMGB, XA  
; PMGB = 00000100B  
2. To output Φ . (The PCL/P22 pin outputs the clock from the low-impedance state.)  
MOV  
OUT  
MOV  
MOV  
MOV  
MOV  
A, #0  
PORT2, A  
XA, #04H  
PMGB, XA  
A, #1000B  
CLOM, A  
; P22 0  
; CLOM 1000B  
5.3.4 Examle of Remote Control Application  
The µPD75402A clock output functions can be used in remote control applications. The remote control output  
carrier frequency is selected by the clock frequency selection bits of the clock output mode register. Pulse output  
enabling/disabling is performed by software control of the enable/disable bit.  
When switching between clock output enabled/disabled states, consideration has been given to ensuring that  
a short pulse is not output.  
Fig. 5-20 Example of Remote Control Application  
CLOM.3  
PCL Pin  
Output  
65  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
5.4 BASIC INTERVAL TIMER  
The µPD75402A is equipped with an 8-bit basic interval timer which has the following functions:  
(a) Standard time generation (2 different time intervals)  
(b) Reading counter contents  
This basic interval timer can also be used as a watchdog timer for the detection of inadvertent program looping.  
5.4.1 Basic Interval Timer Configuration  
The configuration of the basic interval timer is shown in Fig. 5-21.  
Fig. 5-21 Basic Interval Timer Configuration  
Clear  
Clear  
From Clock  
Generation  
Circuit  
fxx/25  
Basic Interval Timer  
( 8-Bit Frequency Divider)  
Set  
Bt  
Interrupt  
Request  
Flag  
MPX  
Vectored  
Interrupt  
Request  
Signal  
fxx/29  
IRQBT  
BT  
BTM3  
BTM2  
1
1
BTM  
8
4
SET1*  
Internal Bus  
*
Instruction execution  
66  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
5.4.2 Basic Intercal Timer Mode Register (BTM)  
BTM is a 4-bit register which controls the operation of the basic interval timer.  
BTM is set by a 4-bit memory handling instruction. Bit operations are not possible.  
Example To set the interrupt generation interval to 1.95 ms (4.19 MHz).  
MOV  
MOV  
A, #1111B  
BTM. A  
; BTM 1111B  
When bit 3 is set (1), the contents of the basic interval timer are cleared and at the same time the basic interval  
timer interrupt request flag (IRQBT) is also cleared (start of basic interval timer).  
With a RESET input, BTM contents are cleared to zero and the interrupt request signal generation interval is set  
to the maximum length.  
Fig. 5-22 Basic Interval Timer Mode Register Format  
3
2
1
1
0
1
Symbol  
BTM  
Address  
F85H BTM3 BTM3  
Interrupt Interval  
Input Clock Specification  
Wait Time when Standby )  
( Mode is Released)  
0
1
fXX/29 (8.18 kHz)  
fXX/25 (131 kHz)  
217/fXX (31.3 ms)  
213/fXX (19.5 ms)  
(
) : Values when fXX = 4.19 MHz  
Basic interval timer start control bit  
Basic interval timer is started by writeng “1”* (counter  
and interrupt request flay are interrupt request flag are  
cleared). Automaticallyreset(0)whenoperationisstarted.  
* Ensure that the write is performed by a 4-bit write instruction.  
Note Ensure that 1 is written to bits 1 and 0.  
67  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
5.4.3 Basic Interval Timer Operation  
The basic interval timer (BT) is constantly incremented by the clock from the clock generation circuit, and sets  
the interrupt request flag (IRQBT) when it overflows. The BT count operation cannot be stopped.  
Either of two times can be selected as the interrupt generation interval by setting the BTM (Fig. 5-22).  
The basic interval timer and the interrupt request flag can be cleared by setting (1) bit 3 of BTM (directive to start  
as interval timer).  
The basic interval timer (BT) count status can be read by an 8-bit handling instruction. Data cannot be written  
to the timer.  
Note When the basic interval timer contents are read, it may happen that unstable data in the process of count  
updating is read. To prevent this, the read instruction should be executed twice, then the two read contents  
should be compared. If a comparison of the two read contents shows appropriate values, the latter contents  
are taken as the result of the read. If the values are completely different, the operation should be repeated  
from the beginning.  
Example To read the BT count contents  
MOV  
LOOP: MOV  
MOV  
HL, #TEMP  
XA, BT  
TEMP, XA  
XA, BT  
A, @HL  
LOOP  
; Set table address to HL  
; First read  
; Save read value  
MOV  
; Second read  
SKE  
; Comparison of low-order 4 bits  
BR  
INCS  
L
XCH  
A, X  
SKE  
A, @HL  
LOOP  
; Comparison of high- order 4 bits  
BR  
68  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
5.4.4 Examples of Basic Interval Timer Applications  
Example 1. In this example the basic interval timer is enabled, and the interrupt generation interval is set to 1.95  
ms (at 4.19 MHz operation).  
SEL  
MOV  
MOV  
EI  
MB15  
A, #1111B  
BTM,A  
; Setting and start  
; Enable interrupts  
; Enable BT interrupts  
EI  
IEBT  
Example 2. Example of watchdog timer application  
When used as a watchdog timer, the basic interval timer’s function of generating an interrupt (INTBT)  
at set intervals is used.  
First, the standard time generated by the basic interval timer is decided.  
Next, the program is divided into a number of modules whose processing should terminate within  
the standard time, and the counter (BT) and interrupt request flag (IRQBT) are cleared each time a  
module ends. A program is written such that an interrupt (INTBT) is not generated if operation is  
normal. In other words, if an interrupt is generated, this is interpreted as indicating inadvertent  
program looping.  
The interrupt generation interval is set to 31.25 ms (in 4.19 MHz operation) so that the processing  
time for each module is less than 31.25 ms.  
SEL  
MOV  
MOV  
EI  
MB15  
; or CLR1 MBE  
A, #1011B  
BTM, A  
Initial  
; Interval setting and counter start  
Setting  
EI  
IEBT  
Module 1  
Processing termination within 31.25 ms  
MOV A, #1011B  
MOV BTM, A  
Module 2  
Processing termination within 31.25 ms  
MOV A, #1011B  
MOV BTM, A  
69  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
5.5 SERIAL INTERFACE  
5.5.1 Serial Interface Functions  
The µPD75402A incorporates a clocked 8-bit serial interface, with the following three modes available.  
(1) Operation-halted mode  
This mode is used when no serial transfer is to be performed, and allows power dissipation to be reduced.  
(2) 3-wire serial I/O mode  
In this mode, 8-bit data transfer is performed using three lines: The serial clock (SCK), serial output (SO), and  
serial input (SI).  
In the 3-wire serial I/O mode simultaneous transmission and reception is possible, increasing the data transfer  
processing speed.  
The 3-wire serial I/O mode allows connection to 75X series and 78K series devices and various peripheral I/O  
devices.  
Serial data transfer is performed MSB-first.  
70  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
(3) SBI mode (serial bus interface mode)  
In the SBI mode, communication is performed with multiple devices by means of two lines: The serial clock (SCK)  
and the serial data bus (SB0).  
This mode conforms to the NEC serial bus format.  
In the SBI mode, the sender can output to the serial data bus an address to select the target device for serial  
communication, a command which gives a directive to the target device, and actual data. The receiver can determine  
by hardware whether the received data is an address, command or actual data.  
Fig. 5-23 Example of SBI System Configuration  
VDD  
Slave CPU  
Master CPU  
Serial Clock  
SCK  
SB0  
SCK  
SB0  
Address 1  
#1  
Address  
Command  
Data  
Slave IC  
SCK  
SB0  
Address N  
#N  
Note When the µPD75402A is used as a slave CPU, its address is limited to the range C0H to C7H.  
5.5.2 Serial Interface Configuration  
The serial interface block diagram is shown in Fig. 5-24.  
71  
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Fig. 5-24 Serial Interface Block Diagram  
Internal Bus  
Bit  
Test  
Bit  
Bit Test  
8
8
8
Manipulation  
Slave Address  
Register (SVA)  
CSIM  
SBIC  
(8)  
Match  
Signal  
RELT  
Address Comparator  
CMDT  
(8)  
P03/SI  
SO  
Latch  
SET CLR  
Shift Registe (SIO)r  
D
Q
(8)  
P02/SO/SB0  
Busy/Ac-  
Knowledge  
Output  
Circuit  
RELD  
CMDD  
ACKD  
Bus Release/  
Command/Ac-  
Knowledge  
Detection  
Circuit  
P01/SCK  
INTCSI  
Control  
Circuit  
INTCSI  
(IRQCSI  
Signal  
Serial Clock  
Copunter  
Setting)  
fxx/24  
Serial Clock  
Control  
Cirucit  
Serial  
Clock  
Selector  
External  
SCK  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
(1) Serial operating mode register (CSIM)  
CSIM is an 8-bit register which specifies the serial interface operating mode, serial clock, wake-up function, etc.  
(See 5.5.3 (1) “Serial operating mode register” for details.)  
(2) Serial bus interface control register (SBIC)  
SBIC is an 8-bit register composed of bits which control the serial bus and flags which indicate various statuses  
of the input data from the serial bus, and is mainly used in the SBI mode. (See 5.5.3 (2) “Serial bus interface control  
register” for details.)  
(3) Shift register (SIO)  
The SIO register converts 8-bit serial data to parallel data and 8-bit parallel data to serial data. It performs  
transmission/reception operations (shift operations) in synchronization with the serial clock. A serial transfer is  
started by writing data to SIO. Actual transmission/reception operations are controlled by writes to the SIO. (See  
5.5.3 (3) “Shift register” for details).  
(4) SO latch  
A latch which holds the SO/SB0 and SI pin levels. Can be directly controlled by software. Set at the end of the  
8th SCK pulse in the SBI mode. (See 5.5.3 (2) “Serial bus interface control register” for details.)  
(5) Serial clock selector  
Selects the serial clock to be used.  
(6) Serial clock counter  
Counts the serial clock cycles output and input in a transmission/reception operation, and checks that 8-bit data  
transmission/reception has been performed.  
(7) Slave address register (SVA), address comparator  
In SBI mode, this register is used when the µPD75402A is used as a slave device. The slave sets its own  
specification number (slave address value) in the SVA register. The master outputs a slave address to select a  
specific slave.  
The address comparator is used to compare the slave address received from the master with the SVA value: If  
they match the relevant slave is determined to have been selected. (See5.5.3 (4) “Slave address registerfor details.)  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
(8) INTCSI control circuit  
Controls the generation of interrupt requests. In the following case, the interrupt requests (INTCSI) are generated  
and interrupt request flags (IRQCSI) are set (see Fig. 6-1 “Interrupt Control Circuit Block Diagram”).  
• In 3-wire serial I/O mode  
An interrupt request is generated on each count of 8 serial clock cycles.  
• In SBI mode  
When WUP* = “0”  
An interrupt request is generated on each count of 8 serial clock cycles.  
An interrupt request is generated when the SVA and SIO values match after address  
reception.  
When WUP = “1”  
*
WUP: Wake-up function specified bit (bit 5 of CSIM)  
(9) Serial clock control circuit  
Controls the supply of the serial clock to the shift register. Also controls the clock output to the SCK pin when  
the internal system clock is used.  
(10) Busy/acknowledge output circuit, bus release/command acknowledge detection circuit  
These circuits perform output and detection of various control signals in the SBI mode.  
They do not operate in the 3-wire serial I/O mode.  
5.5.3 Register Functions  
(1) Serial operating mode register (CSIM)  
The format of the serial operating mode register (CSIM) is shown in Fig. 5-25.  
CSIM is an 8-bit register which specifies the serial interface operating mode, serial clock, wake-up function, etc.  
CSIM is manipulated by 8-bit memory manipulation instructions. The high-order 3 bits can be manipulated bit  
by bit using the individual bit names.  
Read/write capability differs from bit to bit (see Fig. 5-25). Bit 6 can be tested only, and data written to this bit  
is invalid.  
Reset input clears this register to 00H.  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
Fig. 5-25 Serial Operating Mode Register (CSIM) Format (1/2)  
Address  
FE0H  
7
6
5
4
0
3
2
0
1
0
0
Symbol  
CSIM  
CSIE  
COI  
WUP  
CSIM3  
CSIM1  
Serial Clock Selection Bit (W)  
Serial Interface Operating Mode Selection Bit (W)  
Wake-up Function Specification Bit (W)  
Signal from Address Comparator (R)  
Serial Interface Operation Enable/Disable Specification Bit (W)  
Remarks (R) Read only  
(W) Write only  
Note 0 must be written to CSIM bits 4, 2, 0.  
Serial clock selection bit (W)  
Serial Clock  
CSIM1  
SCK Pin Mode  
3-Wire Serial I/O Mode  
SBI Mode  
0
1
Input clock to SCK pin from off chip  
fXX/24 (262 kHz)  
Input  
Output  
Remarks  
(
) When fXX = 4.19 MHz  
Serial interface operating mode selection bit (W)  
Shift Register  
Bit Order  
CSIM3  
0
Operating Mode  
SO Pin Function  
SI Pin Function  
SIO 7 to 0 XA  
(MBS-first transfer)  
SI/P03  
(Input)  
3-wire serial  
I/O mode  
SO/P02  
(CMOS output)  
SB0/P02  
(N-ch open-drain  
input/output)  
SIO 7 to 0 XA  
(MBS-first transfer)  
P03 input  
1
SBI mode  
75  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
Fig. 5-25 Serial Operating Mode Register (CSIM) Format (2/2)  
Wake-up function specification bit (W)  
0
IRQCSI set at end of every serial transfer in each mode.  
WUP  
Used only in SBI mode. IRQCSI is set only when the address received after bus  
release matches the slave address register data (wake-up status). SB0 is high  
impedance.  
1
Note If WUP = 1 is set during BUSY signal output, BUSY is not released. With the SBI, the BUSY signal is output  
after the BUSY release directive until the next fall of the serial clock (SCK). When setting WUP = 1, it is  
necessary to confirm that the SB0 pin has been driven high after BUSY is released before setting WUP =  
1.  
Signal from address comparator (R)  
Clearing Condition (COI = 0)  
Setting Condition (COI = 1)  
COI*  
When slave address register (SVA) and  
shift register data do not match  
When slave address register (SVA) and shift  
register data match.  
*
A COI read is valid only before the start or after completion of a serial transfer. During a transfer an indeterminate  
value will be read. Also, COI data written by an 8-bit manipulation instruction is ignored.  
Serial interface operation enable/disable specification bit (W)  
Shift Register  
Operation  
Serial Clock  
Counter  
IRQCSI Flag  
Retained  
SO/SB0 & SI Pins  
Shift operation  
disabled  
0
1
Cleared  
Port 0 function only  
CSIE  
Function in each  
mode plus port 0  
function  
Shift operation  
enabled  
Count operation  
Settable  
76  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
Remarks 1. The operating mode can be selected according to the setting of CSIE and CSIM3.  
CSIE  
CSIM3  
Operating Mode  
Operation-halted mode  
0
1
1
×
0
1
3-wire serial I/O mode  
SBI mode  
2. The P10/SCK pin status depends on the setting of CSIE and CSIM0 as shown below.  
CSIE  
CSIM1  
P10/SCK Pin Status  
0
0
1
1
0
1
0
1
Input port  
High-level output  
Serial clock input (high impedance)  
Serial clock output (high-level output)  
3. The following procedure should be used to clear CSIE during a serial transfer.  
Clear the interrupt enable flag to set the interrupt disabled state.  
Clear CSIE.  
Clear the interrupt request flag.  
Example 1. This example selects fXX/24 as the serial clock, generates an IRQCSI serial interrupt at the end of each  
serial transfer, and selects the mode in which serial transfers are performed in the SBI mode with  
the SB0 pin as the serial data bus.  
MOV  
MOV  
XA, #10001010B  
CSIM, XA  
; CSIM 10001010B  
2. To enable serial transfers in accordance with the contents of CSIM.  
SET1  
CSIE  
77  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
(2) Serial bus interface control register (SBIC)  
The format of the serial bus interface control register (SBIC) is shown in Fig. 5-26.  
SBIC is an 8-bit register composed of bits which control the serial bus and flags which indicate various statuses  
of the input data from the serial bus, and is mainly used in the SBI mode.  
SBIC is manipulated by bit-manipulation instructions; it cannot be manipulated by 4-bit or 8-bit memory  
manipulation instructions.  
Read/write capability differs from bit to bit (see Fig. 5-26).  
Reset input clears this register to 00H.  
Note In the 3-wire serial I/O mode, only the following bits can be used:  
• Bus release trigger bit (RELT)  
• Command trigger bit (CMDT)  
SO latch setting  
SO latch clearing  
Fig. 5-26 Serial Bus Interface Control Register (SBIC) Format (1/3)  
Address  
FE2H  
7
6
5
4
3
2
1
0
Symbol  
SBIC  
BSYE  
ACKD  
ACKE  
ACKT  
CMDD  
RELD  
CMDT  
RELT  
Bus Release Trigger Bit (W)  
Command Trigger Bit (W)  
Bus Release Datection Flag (R)  
Command Detection Flag (R)  
Acknowledge Trigger Bit (W)  
Acknowledge Enable Bit (R/W)  
Acknowledge Detection Flag (R)  
Busy Enable Bit (R/W)  
Remarks (R)  
Read only  
(W) Write only  
(R/W) Read/write enabled  
78  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
Fig. 5-26 Serial Bus Interface Control Register (SBIC) Format (2/3)  
Bus release trigger bit (W)  
The bus release signal (REL) trigger output control bit. The SO latch is set (1) by setting this  
bit (RELT = 1), after which the RELT bit is automatically cleared (0).  
RELT  
Note SB0 must not be cleared during a serial transfer: Ensure that it is cleared before a transfer is started or after  
it is completed.  
Command trigger bit (W)  
The command signal (CMD) trigger output control bit. The SO latch is cleared (0) by setting  
this bit (CMDT = 1), after which the CMDT bit is automatically cleared (0).  
CMDT  
Note SB0 must not be cleared during a serial transfer: Ensure that it is cleared before a transfer is started or after  
it is completed.  
Bus release detection flag (R)  
Clearing Conditions (RELD = 0)  
Setting Condition (RELD = 1)  
When a transfer start instruction is  
executed  
When RESET is input  
When CSIE = 0 (See Fig. 5-25)  
RELD  
When the bus release signal (REL) is de-  
tected  
When SVA and SIO do not match  
4
when an address is received  
Command detection flag (R)  
Clearing Conditions (CMDD = 0)  
Setting Condition (CMDD = 1)  
When a transfer start instruction is  
executed  
When tje bus release signal (REL) is  
detected  
CMDD  
When the command signal (CMD) is de-  
tected  
When RESET is input  
When CSIE = 0 (See Fig. 5-25)  
4
Acknowledge trigger bit (W)  
When ACKT is set after the end of a transfer, ACK is output in synchronization with the next  
SCK. After th ACK signal is output, ACKT is automatically cleared (0).  
ACKT  
Note 1. ACKT must not be set (1) before completion of a serial tramsfer or during a  
transfer.  
2. ACKT cannot be clearedby software.  
3. When ACKT is set, ACKE should be reset to 0.  
79  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
Fig. 5-26 Serial Bus Interface Control Register (SBIC) Format (3/3)  
Acknowledge enable bit (R/W)  
Disables automatic output of the acknowledge signal (ACK) (outpt by ACKT is  
possibel).  
0
1
ACK is output is synchronization with the 9th  
When set before end of transfer  
ACKE  
SCK clock cycle.  
ACK is output in synchronization with SCK  
immediately after execution of the setting  
instruction.  
When set after end of transfer  
Acknowledge detection flag (R)  
Clearing Conditions (ACKD = 0)  
Setting Condition (ACKD = 1)  
ACKD  
When a transfer is started  
When RESET is input  
When the acknowledge signal (ACK) is de-  
tected (Synchronized with rise of SCK)  
Busy enable bit (R/W)  
Disablin of automatic busy signal output  
0
Busy signal output is stopped in synchronization with the fall of SCK immediately  
after execution ofthe clearing instruction.  
BSYE  
The busy signal is output in synchronization with the fall or SCK following the  
acknowledge signal.  
1
Example 1. To output the command signal.  
SET1 CMDT  
2. To test RELD and CMDD, and perform different processing according to the type of receive data.  
This interrupt routine is only performed when WUP = 1 and there is an address match.  
SKF  
BR  
RELD  
!ADRS  
CMDD  
;
;
Test RELD  
SKT  
BR  
Test CMDD  
!DATA  
...............  
CMD  
:
;
;
;
Command interpretation  
Data processing  
DATA : ...............  
ADRS : ...............  
Address decoding  
80  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
(3) Shift register (SIO)  
The configuration around the shift register is shown in Fig. 5-27. SIO is an 8-bit register which carries out parallel-  
to-serial conversion and performs serial transmission/reception (shift operations) in synchronization with the serial  
clock.  
A serial transfer is started by writing data to SIO.  
In transmission, the data written to SIO is output to the serial output (SO) or the serial data bus (SB0). In reception,  
data is read into SIO from the serial input (SI) or SB0.  
SIO can be read or written to by an 8-bit manipulation instruction.  
If RESET is input during its operation, the value of SIO is indeterminate. If RESET is input in the standby mode,  
the value of SIO is retained.  
The shift operation stops after transmission/reception of 8 bits.  
Fig. 5-27 Configuration Around Shift Register  
RELT  
Address  
Comparator  
Internal Bus  
CMDT  
SET  
CLR  
Shift Register  
(SIO)  
SO Latch  
P02/SO  
/SB0  
D
Q
CLK  
BUSY/ACK  
Shift Clock  
N-ch Open-Drain Output  
SIO reading and the start of a serial transfer (write) are possible at the following times:  
• When the serial interface operation enable/disable bit (CSIE) = 1, except when CSIE is set to “1” after data has  
been written into the shift register.  
• When the serial clock has been masked agter an 8-bit serial transfer.  
• When SCK is high.  
Ensure that SCK is high when data is written to or read from the SIO register.  
In the SBI mode data bus configuration, input pins and output pins have dual functions. Output pins have an N-  
ch open-drain configuration. Therefore, in a device in which reception is about to be performed, FFH should be set  
in the SIO register.  
81  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
(4) Slave address register (SVA)  
SVA is an 8-bit register used by the slave to set the slave address value (its own specification number).  
SVA is a write-only register which is manipulated by 8-bit manipulation instructions.  
After RESET signal input, the value of SVA is indeterminate. However, when RESET is input in the standby mode,  
the value of SVA is retained.  
In the SBI mode, the slave address register (SVA) has the following two functions:  
(a) Slave address detection  
Used when the µPD75402A is connected to the serial bus as a slave device.  
The high-order 5 bits of the SVA register are fixed at 11000 by hardware. Therefore, the address assigned  
to the µPD75402A is limited to the range C0H to C7H.  
The master outputs to its connected slaves a slave address to select a specific slave. If these two data items  
(the slave address output from the master and the SVA value) are found to match when compared by the  
address comparator, the relevant slave is determined to have been selected.  
At this time, bit 6 (COI) of the serial operating mode register (CSIM) is set to “1”.  
When an address is received the bus release detection flag (RELD) is cleared (0) if a match is not detected.  
IRQCSI is set only when a match is detected when WUP = 1. This interrupt request indicates that a  
communication request has been issued from the master to the µPD75402A.  
(b) Error detection  
The SVA performs error detection in the following cases:  
• When the µPD75402A transmits addresses, commands or data as the master device.  
• When the µPD75402A transmits data as a slave device.  
See 5.5.6 (8) “Error detection” for details.  
Note When data is written to SVA, ensure that a value between C0H and C7H is written.  
82  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
5.5.4 Operation-Halted Mode  
The operation-halted mode is used when no serial transfer is performed, allowing power dissipation to be  
reduced.  
In this mode, the shift register does not perform shift operations and can be used as an ordinary 8-bit register.  
When the RESET signal is input the operation-halted mode is set. The P02/SO/SB0 and P03/SI pins are fixed as  
input ports. P01/SCK can be used as an input port depending on the setting of the serial operating mode register.  
(1) Register setting  
Operation-halted mode setting is performed by the serial operating mode register (CSIM) (see 5.5.3 (1)“Serial  
operating mode register” for full details of CSIM).  
CSIM is manipulated by 8-bit memory manipulation instructions, but bit manipulation of CSIE is also possible.  
Manipulation is also possible using bit names.  
Reset input clears this register to 00H.  
The shaded area indicates bits used in the operation-halted mode.  
Address  
FE0H  
7
6
5
4
0
3
2
0
1
0
0
Symbol  
CSIM  
CSIE  
C0I  
WUP  
CSIM3  
CSIM1  
Serial Clock Celection Bit (W)*  
Serial Interface Operating Mode Selection Bit (W)  
Wake-up Function Specification Bit (w)  
Match Signal from Address Comparator (R)  
Serial Interface Operation Enable/Disable Specification Bit (W)  
*
Allow selection of P01/SCK pin status.  
Remarks (R)  
Read only  
(W) Write only  
Serial interface operation enable/disable specification bit (W)  
Serial Clock  
Counter  
Shift Register  
Operation  
IRQCSI Flag  
Retained  
SO/SB0 & SI Pins  
Shift operation  
disabled  
Cleared  
Port o function only  
0
CSIE  
83  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
Serial clock selection bit (W)  
The P01/SCK pin status depends on the CSIM1 setting as shown below.  
CSIM1  
P01/SCK Pin Status  
High impedance  
High level  
0
1
The following procedure should be used to clear CSIE during a serial transfer.  
Clear the interrupt enable flag (IECSI) to set the interrupt disabled state.  
Clear CSIE.  
Clear the interrupt request flag (IRQCSI).  
5.5.5 3-Wire Serial I/O Mode Operation  
The 3-wire serial I/O mode allows connection to the system used in the 75X series, µPD7500 series, 87AD series,  
etc.  
Communication is performed using three lines: The serial clock (SCK), serial output (SO), and serial input (SI).  
Fig. 5-28 Example of 3-Wire Serial I/O System Configuration  
3-wire serial I/O 3-wire serial I/O  
Master CPU  
Slave CPU  
SCK  
SCK  
SO  
SI  
SI  
SO  
(1) Register setting  
When the device is used in the 3-wire serial I/O mode, setting can be performed by means of the following two  
registers:  
• Serial operating mode register (CSIM)  
• Serial bus interface control register (SBIC)  
84  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
(a) Serial operating mode register (CSIM)  
When the 3-wire serial I/O mode is used, CSIM is set as shown below (see 5.5.3 (1) “Serial operating mode  
register” for full details of CSIM).  
CSIM is manipulated by 8-bit memory manipulation instructions. Bit manipulation of bits 7, 6 and 5 is also  
possible.  
Reset input clears the CSIM register to 00H.  
The shaded area indicates bits used in the 3-wire serial I/O mode.  
Address  
FE0H  
7
6
5
4
0
3
2
0
1
0
0
Symbol  
CSIM  
CSIE  
C0I  
WUP  
CSIM3  
CSIM1  
Serial Clock Selection Bit (W)  
Serial Interface Operating Mode Selection Bit (W)  
Wake-up Function Specification Bit (w)  
Match Signal from Address Comparator (R)  
Serial Interface Operation Enable/Disable Specification Bit (W)  
Remarks (R)  
Read only  
(W) Write only  
Serial clock selection bit (W)  
Serial Clock  
CSIM1  
SCK Pin Mode  
3-Wire Serial I/O Mode  
SBI Mode  
0
1
Input clock to SCK pin from off chip  
fXX/24 (262 kHz)  
Input  
Output  
Remarks Figuer in ( ) apply to fXX = 4.19 MHz operation  
Serial interface operating mode selection bit (W)  
CSIM3  
0
Operating Mode  
Shift Register Bit Order  
SO Pin Function  
Si Pin Function  
3-wire serial I/O  
mode  
SIO 7 to 0 XA  
(MSB-fist transfer)  
SO/P02  
(CMOS Output)  
SI/P03 (Input)  
Wake-up function specification bit (W)  
WUP  
0
IRQCSI set at end of every serial transfer.  
85  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
Signal from address comparator (R)  
Clearing Conditions (COI = 0)  
Setting Condition (COI = 1)  
COI*  
When slave address register (SVA) and  
shift register data do not match.  
When slave address register (SVA) and shift  
register data match.  
*
A CIO read is valid only before the start of after completion of a serial transfer. During a transfer an indeterminate  
value will be read.  
Also, COI data written by an 8-bit manipulation instruction is ignored.  
Serial interface operation enable/disable specification bit (W)  
Shift Register  
Operation  
Serial Clock  
Counter  
IRQCSI Flag  
Settable  
SO/SB0 & SI Pins  
Function in each  
mode plus port 0  
function  
Shift operation  
enabled  
Count operation  
1
CSIE  
86  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
(b) Serial bus interface control register (SBIC)  
When the 3-wire serial I/O mode is used, SBIC is set as shown below (see 5.5.3 (2) “Serial bus interface  
control register” for full details of SBIC).  
SBIC is manipulated by bit manipulation instructions.  
Reset input clears the SBIC register to 00H.  
The shaded area indicates bits used in the 3-wire serial I/O mode.  
Address  
FE2H  
7
6
5
4
3
2
1
0
Symbol  
SBIC  
BSYE  
ACKD  
ACKE  
ACKT  
CMDD  
RELD  
CMDT  
RELT  
Bus Release Trigger Bit (W)  
Should not used in 3-wire serial I/O mode  
Command Trigger Bit (w)  
Remarks (W) Write only  
Bus release trigger bit (W)  
The command signal (REL) trigger output control bit. The SO latch is cleared (0) by setting  
this bit (RELT = 1), after which the RELT bit is automatically cleared (0).  
RELT  
Command trigger bit  
The command signal (CMD) Trigger output control bit. The SO latch is cleared (0) by setting  
this bit (CMDT = 1), after which the CMDT bit is automatically cleared (0).  
CMDT  
Note Bits other than RELT and CMDT should not be used in the 3-wire serial I/O mode.  
87  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
(2) Communication operation  
In the 3-wire serial I/O mode, data transmission/ reception is performed in 8-bit units. Data is transmitted/received  
bit by bit in synchronization with the serial clock.  
Shift register shift operations are performed in synchronization with the fall of the serial clock (SCK). Then send  
data is held in the SO latch output from the SO pin. Also, receive data input to the SI pin is latched in the shift register  
on the rise of SCK.  
At the end of an 8-bit transfer the operation of the shift register stops automatically and the IRQCSI interrupt  
request flag is set.  
Fig. 5-29 3-Wire Serial I/O Mode Timing  
SCK  
1
2
3
4
5
6
7
8
DI7  
DI6  
DI5  
DI4  
DI3  
DI2  
DI1  
DI0  
SI  
SO  
DO7  
DO6  
DO5  
DO4  
DO2  
DO1  
DO0  
DO3  
IRQCSI  
End of  
Transfer  
Start of Transfer Symchronized with Fall of SCK  
Execution of Instruction which Writes Data to SIO  
(Trasfer Start Directive)  
The SO pin becomes a CMOS output and outputs the SO latch status, and thus the SO pin output status can be  
manipulated in accordance with the setting of the RELT bit and CMDT bit.  
However, manipulation should not be performed during a serial transfer.  
88  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
(3) Serial clock selection  
Serial clock selection is performed by setting bit 1 of the serial operating mode register (CSIM). Either of the  
following clocks can be selected.  
Table 5-6 Serial Clock Selection and Use (in 3-Wire Serial I/O Mode)  
Mode  
Register  
Serial Clock  
Possible Timing for Shift  
Register R/W and Serial  
Transfer Start  
Use  
Serial Clock  
Masking  
Source  
CSIM 1  
Automatically  
masked at end of  
8-bit data  
Possible only when serial transfer  
is halted* or when SCK is high.  
External  
SCK  
Slave CPU  
0
1
transfer.  
Possible only when serial transfer  
is halted* or when SCK is high.  
Medium-speed  
serial transfer  
fXX/24  
*
“When serial transfer is halted” means in the operation-halted mode, or when the serial clock is masked after  
an 8-bit transfer.  
(4) Signals  
RELT and CMDT operation is shown in Fig. 5-30.  
Fig. 5-30 RELT & CMDT Operation  
SO  
RELT  
CMDT  
89  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
(5) Data transfer order  
The µPD75402A 3-wire serial I/O mode differs from that of other 75X series products in that it is not possible to  
switch between MSB and LSB as the first bit.  
Serial transfer is performed MSB-first.  
Fig. 5-31 Shift Register (SIO) and Internal Bus Configuration  
7
6
Internal  
Bus  
1
0
Read/Write Gate  
SO Latch  
Shift Register (SIO)  
SI  
D
Q
SO  
SCK  
(6) Start of transfer  
When the following two conditions are met a serial transfer is started by setting transfer data in the shift register  
(SIO).  
• The serial interface operation enable/disable bit (CSIE) = 1.  
• After an 8-bit serial transfer, the internal serial clock is stopped or SCK is high.  
Note  
The transfer will not be started if CSIE is set to “1” after data is written into the shift register.  
When an 8-bit transfer ends, the serial transfer stops automatically and the IRQCSI interrupt request flag is set.  
Example In the following example the data in the RAM specified by the HL register is transferred to SIO, and at  
the same time the SIO data is fetched into the accumulator and the serial transfer is started.  
MOV  
XCH  
XA, @HL ; Fetch send data from RAM  
XA, SIO ; Exchange send data with receive data and start transfer  
90  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
(7) 3-wire serial I/O mode applications  
(a) To transfer data MSB-first (master operation) using a 262 kHz transfer clock (when operating at 4.19 MHz).  
<Sample program>  
MOV  
MOV  
MOV  
MOV  
XA, #10000010B  
CSIM, XA  
; Transfer mode setting  
XA, TDATA  
SIO, XA  
; TDATA is transfer data storage address  
; Transfer data setting & start of transfer  
Note From the second time onward, the transfer can be started by setting data in SIO (MOV SIO, XA or XCH XA,  
SIO).  
µPD75402A  
SCK  
SCK  
SI  
SO/SB0  
In this application the µPD75402A SI pin can be used as an input port.  
91  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
(b) To transmit/receive MSB-first data using an external clock (slave operation).  
µPD75402A  
Other Microcomputer  
P01/SCK  
SCK  
SO  
SI  
SI  
SO/SB0  
<Sample program>  
Main routine  
MOV  
MOV  
MOV  
MOV  
EI  
XA, #80H  
CSIM, XA  
XA, TDATA  
SIO, XA  
; Serial operation stopped, external clock specification  
; Transfer data setting & start of transfer  
IECSI  
EI  
Interrupt routine  
MOV  
XCH  
MOV  
RETI  
XA, TDATA  
XA, SIO  
; Receive data ÷ send data & start of transfer  
RDATA, XA ; Receive data save  
92  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
5.5.6 SBI Mode Operation  
The SBI (serial bus interface) is a high-speed serial interface which conforms to the the NEC serial bus format.  
The SBI is a single-master high-speed serial bus. Its format includes the addition of bus configuration functions  
to the clocked serial I/O method to enable communication to be performed with multiple devices using two signal  
lines. Consequently, when a serial bus is configured with multiple microcomputers and peripheral ICs, it is possible  
to reduce the number of ports used and the amount of wiring on the substrate.  
The master can output to a slave on the serial data bus an address to select the target device for serial  
communication, a command which gives a directive to the target device, and actual data. The slave can determine  
by hardware whether the received data is an address, command or actual data. This function allows the serial  
interface control portion of the application program to be simplified.  
SBI functions are incorporated in a number of devices including the 75X series, and 78K series 8-bit single-chip  
microcomputers.  
An example of a serial bus configuration when CPUs and peripheral ICs with a serial interface conforming to the  
SBI are used is shown in Fig. 5-32.  
In the SBI the SB0 serial data bus pin is an open-drain output and thus the serial data bus line is in the wired-  
OR state. The serial data bus line requires a pull-up resistor.  
Fig. 5-32 Example of SBI Serial Bus System Configuration  
+ VDD  
Seroal Data Bis  
SB0  
SCK  
SB0  
SCK  
Slave CPU  
Address 1  
Master  
CPU  
Serial Clock  
SB0  
SCK  
Slave CPU  
Address 2  
SB0  
SCK  
Slave IC  
Address N  
Note When master/slave exchange processing is performed, since serial clock line (SCK) input/output switching  
is performed asynchronously between master and slave, a pull-up resistor is also required for the serial  
clock line (SCK).  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
(1) SBI functions  
Since conventional serial I/O methods have only data transfer functions, when a serial bus is configured with  
multiple devices connected a large number of ports and wires are required for Chip Select signal and command/  
data differentiation, busy status recognition, etc. If these controls are performed by software, the load incurred by  
software is very large.  
When the SBI, a serial bus can be configured using only two lines: The serial clock, SCK, and the serial data bus,  
SB0. As a result, the number of microcomputer ports and the amount of substrate wiring can be significantly  
reduced.  
SBI functions are described below.  
(a) Address/command/data differentiation function  
Identifies serial data as an address, command or actual data.  
(b) Chip selection by address  
The master performs chip selection by address transmission.  
(c) Wake-up function  
A slave can identify address reception (chip selection) easily by means of the wake-up function (settable/  
releasable by software).  
When the wake-up function is set, an interrupt (IRQCSI) is generated when a matching address is received.  
As a result, non-selected CPUs can operate without regard to serial communications even when commu-  
nication with multiple devices is performed.  
(d) Acknowledge signal (ACK) control function  
Controls the acknowledge signal used to confirm serial data reception.  
(e) Busy signal (BUSY) control function  
Controls the busy signal used to give notification of a slave busy status.  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
(2) SBI definition  
The SBI serial data format and the meaning of the signals used are explained in the following section. Serial data  
transmitted via the SBI is classified into three types: Commands, addresses and data. Serial data forms a frame with  
the configuration shown below.  
Address, command and data transfer timing is shown in Fig. 5-33.  
Fig. 5-33 SBI Transfer Timing  
Address Transfer  
8
9
SCK  
SB0  
BUSY  
A7  
A0  
ACK  
Bus Release  
Signal  
Command Transfer  
Command Signal  
SCK  
9
SB0  
C7  
C0ACK  
BUSY  
READY  
Data Transfer  
8
9
SCK  
SB0  
ACK  
D0  
BUSY  
READY  
D7  
The bus release signal and command signal are output by the master. The BUSY signal is output by the slave.  
ACK can be output by either the master or slave (normally output by the 8-bit data receiver).  
The serial clock is output by the master continuously from the start of an 8-bit data transfer until BUSY is released.  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
(a) Bus release signal (REL)  
The bus release signal indicates that the SB0 line has changed from low to high when the SCK line is high  
(when the serial clock is not being output). This signal is output by the master.  
Fig. 5-34 Bus Release Signal  
SCK  
SB0  
“H”  
The bus release signal indicates that the master is about to send an address to a slave. Slaves incorporate  
hardware to detect the bus release signal.  
(b) Command signal (CMD)  
The command signal indicates that the SB0 line has changed from high to low when the SCK line is high  
(when the serial clock is not being output). This signal is output by the master.  
Fig. 5-35 Command Signal  
SCK  
SB0  
“H”  
Slave incorporate hardware to detect the command signal.  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
(c) Address  
An address is 8-bit data output by the master to slaves connected to the bus line in order to select a particular  
slave.  
Fig. 5-36 Address  
1
2
3
4
5
6
7
8
SCK  
SB0  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
Address  
Bus Release Signal  
Command Signal  
The 8-bit data following the bus release signal and command signal is defined as an address. In a slave this  
condition is detected by hardware and a check is performed by hardware to see if the 8-bit data matches the  
slave’s own specification number (slave address). If the 8-bit data matches the slave address, that slave is  
determined to have been selected and communication is subsequently performed with the master until a  
disconnect directive is received from the master.  
Fig. 5-37 Slave Selection by Address  
Master  
Slave 1  
Slave 2  
Slave 3  
Slave 4  
Not Selected  
Selected  
Sends Address  
of Slave  
Not Selected  
Selected  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
(d) Command & data  
The master performs command transmission to or data transmission/reception to/from the slave selected  
by address transmission.  
Fig. 5-38 Command  
1
2
3
4
5
6
7
8
SCK  
SB0  
C7  
C6  
C5  
C4  
C3  
C2  
C1  
C0  
Command Signal  
Command  
Fig. 5-39 Data  
SCK  
SB0  
1
2
3
4
5
6
7
8
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
Data  
The 8-bit data following the command signal is defined as a command. 8-bit data with no command signal  
is defined as data. The way in which commands and data are used can be freely decided according to the  
communication specifications.  
98  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
(e) Acknowledge signal (ACK)  
The acknowledge signal is used to confirm serial data reception between the sender and receiver.  
Fig. 5-40 Acknowledge Signal  
[When output in synchronization with 11th SCK clock cycke]  
SCK  
SB0  
8
9
10  
11  
ACK  
[When output in synchronization with 9th SCK clock cycke]  
SCK  
SB0  
8
9
ACK  
The acknowledge signal is a one-shot pulse synchronized with the fall of SCK after an 8-bit data transfer.  
Its position is arbitrary and it can be synchronized with any SCK clock cycle.  
After 8-bit data transmission the sender checks whether the receiver has sent back an acknowledge signal.  
If an acknowledge signal is not returned within a specific time after data transmission, reception can be judged  
not to have been performed correctly.  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
(f) Busy signal (BUSY), ready signal (READY)  
The busy signal notifies the master that a slave is preparing for data transmission/reception.  
The ready signal notifies the master that a slave is ready for data transmission/reception.  
Fig. 5-41 Busy Signal & Ready Signal  
SCK  
8
9
SB0  
ACK  
BUSY  
READY  
With the SBI a slave reports its busy status to the master by driving the SB0 line low.  
The busy signal is output following the acknowledge signal output by the master or slave. Busy signal  
setting/release is performed in synchronization with the fall of SCK. When the busy signal is released the  
master automatically terminates output of the SCK serial clock.  
When the busy signal is released and the ready signal sate is entered the master can start the next transfer.  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
(3) Register setting  
When the device is used in the SBI mode, setting can be performed by means of the following two registers:  
• Serial operating mode register (CSIM)  
• Serial bus interface control register (SBIC)  
(a) Serial operating mode register (CSIM)  
When the SBI mode is used, CSIM is set as shown below (see 5.5.3 (1) “Serial operating mode register”  
for full details of CSIM).  
CSIM is manipulated by 8-bit manipulation instructions. Bit manipulation of bits 7, 6 and 5 is also possible.  
Reset input clears the CSIM register to 00H.  
The shaded area indicates bits used in the SBI mode.  
Address  
FE0H  
7
6
5
4
0
3
2
0
1
0
0
Symbol  
CSIM  
CSIE  
COI  
WUP  
CSIM3  
CSIM1  
Serial Clock Selection Bit (W)  
Serial Interface Operating Mode Selection Bit (W)  
Wake-up Functing Specification Bit (w)  
Signal from Address Comparator (R)  
Serial Interface Operation Enable/Disable Specification Bit (W)  
Remarks (R)  
Read only  
(W) Write only  
Serial clock selection bit (W)  
Serial Clock  
CSIM1  
SCK Pin Mode  
3-Wire Serial I/O Mode  
Input clock to SCK pin from off chip  
fXX/24 (262 kHz)  
SBI Mode  
0
1
Input  
Output  
Remarks Figure in ( ) apply to fXX = 4.19 MHz operation  
Serial interface operating mode selection bit (W)  
Shift Register  
CSIM3  
1
Operating Mode  
SBI mode  
SO Pin Function  
SI Pin Function  
P03 input  
Bit Order  
SB0/P02  
(N-ch open-drain  
input/output)  
SIO 7 to 0 XA  
(MBS-first transfer)  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
Wake-up function specification bit (W)  
IRQCSI set at end of every serial transfer in SBI mode mask state.  
0
1
User only when functioning as a slave in SBI mode. IRQCSI is set only when the  
address received after bus release matches the slace address register data (wake-up  
status). SB0 is high impedance.  
WUP  
Note If WUP = 1 is set during BUSY signal output, BUSY is not released. With the SBI, the BUSY signal is output  
after the BUSY release directive until the next fall of the serial clock (SCK). when setting WUP = 1, it is  
necessary to confirm that the SB0 pin has been driven high after BUSY is released before setting WUP =  
1.  
Signal from address comparator (R)  
Clearing Conditions (COI = 0)  
Setting Condition (COI = 1)  
COI*  
When slave address register (SVA) and  
shift register data do not match.  
When slave address register (SVA) and shift  
register data match.  
*
A COI read is valid only before the start or after completion of a serial transfer. During a transfer an indeterminate  
value will be read.  
Also, COI data written by an 8-bit manipulation instruction is ignored.  
Serial interface operation enable/disable specification bit (W)  
Serial Clock  
Counter  
Shift Register  
Operation  
IRQCSI Flag  
Settable  
SO/SB0 & SI Pins  
Function in each  
mode plus port 0  
function  
Shift operation  
enabled  
Count operation  
1
CSIE  
102  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
(b) Serial bus interface control register (SBIC)  
When the SBI mode is used, SBIC is set as shown below (see 5.5.3 (2) “Serial bus interface control register”  
for full details of SBIC).  
SBIC is manipulated by bit manipulation instructions.  
Reset input clears the SBIC register to 00H.  
The shaded area indicates bits used in the SBI mode.  
Address  
FE2H  
7
6
5
4
3
2
1
0
Symbol  
SBIC  
BSYE  
ACKD  
ACKE  
ACKT  
CMDD  
RELD  
CMDT  
RELT  
Bus Release Trigger Bit (W)  
Command Trigger Bit (W)  
Bus Release Datection Flag (R)  
Command Detection Flag (R)  
Acknowledge Trigger Bit (W)  
Acknowledge Enable Bit (R/W)  
Acknowledge Detection Flag (R)  
Busy Enable Bit (R/W)  
Remarks (R)  
Read only  
(W) Write only  
(R/W) Read/write enabled  
Bus release trigger bit (W)  
The bus release signal (REL) trigger output control bit. The SO latch is set (1) by setting this  
bit (RELT = 1), after which the RELT bit is automatically cleared (0).  
RELT  
Note SB0 must not be set during a serial transfer: Ensure that it is set before a transfer is started or after it is  
completed.  
Command trigger bit (W)  
The command signal (CMD) trigger output control bit. The SO latch is cleared (0) by setting  
this bit (CMDT = 1), after which the CMDT bit is automatically cleared (0).  
CMDT  
Note SB0 must not be set during a serial transfer: Ensure that it is set before a transfer is started or after it is  
completed.  
103  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
Bus release detection flag (R)  
Clearing Conditions (RELD = 0)  
Setting Condition (RELD = 1)  
When a transfer start instruction is  
executed  
When RESET is input  
When CSIE = 0 (See Fig. 5-25)  
RELD  
When the bus release signal (REL) is de-  
tected  
4
When SVA and SIO do not match  
when an address is received  
Command detection flag (R)  
Clearing Conditions (CMDD = 0)  
Setting Condition (CMDD = 1)  
When a transfer start instruction is  
executed  
When the bus release signal (REL) is  
detected  
CMDD  
When the command signal (CMD) is de-  
tected  
When RESET is input  
When CSIE = 0 (See Fig. 5-25)  
4
Acknowledge trigger bit (W)  
When ACKT is set after the end of a transfer, ACK is output in synchronization with the next  
SCK. After the ACK signal is output, ACKT is automatically cleared (0).  
ACKT  
Note 1. ACKT must not be set (1) before completion of a serial tramsfer or during a  
transfer.  
2. ACKT cannot be clearedby software.  
3. When ACKT is set, ACKE should be reset to 0.  
Acknowledge enable bit (R/W)  
Disables automatic output of the acknowledge signal (outpt by ACKT is possibel).  
0
1
ACK is output is synchronization with the 9th  
SCK clock cycle.  
When set before end of transfer  
When set after end of transfer  
ACKE  
ACK is output in synchronization with SCK  
immediately after execution of the setting  
instruction.  
Acknowledge detection flag (R)  
Clearing Conditions (ACKD = 0)  
Setting Condition (ACKD = 1)  
ACKD  
When a transfer is started  
When RESET is input  
When the acknowledge signal (ACK) is de-  
tected (Synchronized with the rise of SCK)  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
Busy enable bit (R/W)  
Disablin of automatic busy signal output  
Busy signal output is stopped in synchronization with the fall of SCK immediately  
after execution ofthe clearing instruction.  
0
BSYE  
The busy signal is output in synchronization with the fall or SCK following the  
acknowledge signal.  
1
(4) Serial clock selection  
Serial clock selection is performed by setting bit 1 of the serial operating mode register (CSIM). Either of the  
following clocks can be selected.  
Table 5-7 Serial Clock Selection and Use (in SBI Mode)  
Mode  
Register  
Serial Clock  
Possible Timing for Shift  
Register R/W and Serial  
Transfer Start  
Use  
Serial Clock  
Masking  
Source  
CSIM 1  
Automatically  
masked at end of  
8-bit data  
Possible only when serial transfer  
is halted* or when SCK is high.  
External  
SCK  
Slave CPU  
0
1
transfer.  
Possible only when serial transfer  
is halted* or when SCK is high.  
Medium-speed  
serial transfer  
fXX/24  
*
“When serial transfer is halted” means in the operation- halted mode, or when the serial clock is masked after  
an 8-bit transfer.  
When the internal system clock is selected SCK stops at 8 pulses internally, but externally the count continues  
until the slave is in the ready state.  
105  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
(5) Signals  
The operation of signals and flags in SBIC in the SBI mode are shown in Figs. 5-42 to 5-47, and SBI signals are  
listed in Table 5-8.  
Fig. 5-42 RELT, CMDT, RELD & CMDD Operation (Master)  
Tramsfer Start Directive  
SIO  
SCK  
SB0  
RELT  
CMDT  
RELD  
CMDD  
Fig. 5-43 RELT, CMDT, RELD & CMDD Operation (Slave)  
Transfer Start Directive  
Write to SIO  
SIO  
SCK  
1
2
3
4
5
6
7
8
9
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
So Latch  
RELT  
(Master)  
CMDT  
(Master)  
When Address Matches  
RELD  
When Address Does not Match  
CMDD  
106  
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Fig. 5-44 ACKT Operation  
SCK  
SB0  
6
7
8
9
ACK signal is output in 1  
clock interval immediately  
after ACKT is set.  
D2  
D1  
D0  
ACK  
ACKT  
When set in this interval  
Note ACKT must not be set before the end of a transfer.  
107  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
Fig. 5-45 ACKE Operation  
(a) When ACKE = 1 on completion of transfer  
SCK  
SB0  
1
2
7
8
9
ACK signal is output in 9th  
clock cycle.  
D7  
D6  
D2  
D1  
D0  
ACK  
ACKE  
When ACKE = 1 at this point  
(b) When ACKE is set after completion of transfer  
6
7
8
9
SCK  
SB0  
ACK signal is output in 1  
clock interval immediately  
after ACKE is set.  
D2  
D1  
D0  
ACK  
ACKE  
When ACKE is set in this interval and ACKE = 1 on  
next fall of SCK  
(c) When ACKE = 0 on completion of transfer  
SCK  
SCK  
1
2
7
8
9
ACK signal is not output.  
D7  
D6  
D2  
D1  
D0  
ACKE  
When ACKE = 0 at this point  
(d) When ACKE = 1 interval is short  
SCK  
ACK signal is not output.  
D2  
D1  
D0  
SB0  
ACKE  
When ACKE is set and cleared in this interval and  
ACKE = 0 on next fall of SCK  
108  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
Fig. 5-46 ACKD Operation  
(a) When ACK signal is output in 9th SCK clock interval  
Transfer Start Directive  
SIO  
Start of Transfer  
SCK  
SB0  
6
7
8
9
ACK  
D2  
D1  
D0  
ACKD  
(b) When ACK signal is output after 9th SCK clock interval  
Transfer Start Directive  
SIO  
Start of  
Transfer  
SCK  
SB0  
6
7
8
9
ACK  
D2  
D1  
D0  
ACKD  
(c) Clearing timing when transfer start directive is given during busy state  
Transfer Start Directive  
SIO  
Start of Transfer  
SCK  
SB0  
7
8
9
6
ACK  
BUSY  
D2  
D1  
D0  
D7  
D6  
ACKD  
Fig. 5-47 BSYE Operation  
SCK  
SB0  
6
7
8
9
BUSY  
ACK  
D2  
D1  
D0  
BSYE  
When BSYE is Reset in this  
Interval and BSYE = 0 when  
SCK Falls  
When BSYE = 1 at  
this Point  
109  
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Table 5-8 Signals in SBI Mode (1/2)  
Output  
Device  
Output  
Meaning of  
Signal  
Effect on  
Flag  
Signal Name  
Timing Chart  
Definition  
Condition  
SB0 rising edge when  
SCK = 1  
Outputs next CMD  
signal and indicates  
send data is address.  
Bus release  
signal (REL)  
Master  
• RELT set  
• RELD set  
• CMDD  
SCK  
SB0  
“H”  
Cleared  
SB0 falling edge when  
SCK = 1  
i) After REL signal  
output send data is  
address.  
Command  
Master  
• CMDT set • CMDD set  
signal (CMD)  
SCK  
SB0  
“H”  
ii) send data with no  
REL signal output is  
command.  
Low-level signal output to  
SB0 in 1 SCK clock intercal  
after serial receive comple-  
tion.  
Receive completion  
Acknowledge  
singnl (ACK)  
Master/  
slave  
ACKE = 1 • ACKD set  
ACKE set  
Low-level signal output to  
SB0 after Acknowledge  
signal.  
Busy signal  
(BUSY)  
Slave  
Slave  
Serial transmission/  
reception disabled  
because processing is in  
progress.  
• BSYE = 1  
SCK  
SB0 D0  
SB0  
9
BUSY  
ACK  
ACK  
READY  
READY  
BUSY  
High-level signal output to  
SBO before start or after  
completion of serial transfer.  
Serial transmission/  
reception enabled  
Ready signal  
(READY)  
BSYE = 0  
Execution  
of instruc-  
tion to  
D0  
write data  
to SIO  
(transfer  
start  
directive)  
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Table 5-8 Signals in SBI Mode (2/2)  
Output  
Device  
Output  
Meaning of  
Signal  
Effect on  
Flag  
Signal Name  
Timing Chart  
Definition  
Condition  
Synchronization clock for  
output of address/command/  
data, ACK signal,  
Timing of signal output  
to serial data bus  
Serial Clock  
(SCK)  
Master  
Exection of IRQCSI set  
instruction  
to write to  
SIO when  
CSIE = 1  
(rise of 9th  
SCK clock  
cycle) *1  
SCK  
SB0  
1
2
7
8
9
10  
Synchronous BUSY signal,  
etc.  
Address/command/ data is  
transferred in first 8 cycles.  
(serial  
transfer  
start  
8-bit data transferred in  
synchronization with SCK  
after REL signl and CMD  
signal output.  
SCK  
SB0  
1
7
8
Address value of slave  
device on serial bus  
Address  
Master  
Master  
2
(A7 to A0)  
directive) *2  
REL  
CMD  
1
8-bit data transferred in  
synchronization with SCK  
after CMD signal only is  
output without output of REL  
signal.  
Directive, meddage,  
etc., to slave device.  
SCK  
SB0  
2
7
8
Command  
(C7 to C0)  
CMD  
8-bit data transferred in  
synchronization with SCK  
with no output of either REL  
signal or CMD signal.  
Data to ve processed by  
slave or master device  
Data  
Master/  
slave  
(D7 to D0)  
SCK  
SB0  
1
2
7
8
*
1. When WUP = 0, IRQCSI is always set on the 9th rise of SCK.  
When WUP = 1, IRQCSI is set on the 9th rise of SCK only with an address is receive and that address matches the value of the slave address register  
(SVA).  
2. In data transmission/reception, when in the BUSY stare, the transfer starts after transition to the READY state.  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
(6) Pin configuration  
The configuration of the serial clock pin (SCK) and the serial data bus pin SB0 is as shown below.  
(a) SCK .................... Pin for input/output of serial clock  
Master ........ CMOS, push-pull output  
Slave ........... Schmitt input  
(b) SB0 .................... Serial data input/output dual- function pin  
For both master and slave, output is N-ch open-drain, input is Schmitt input.  
Since the serial data bus line output is N-ch open-drain, an external pull-up resistor is necessary.  
Fig. 5-48 Pin Configuration Diagram  
Slave Device  
Master Device  
(Clock Output)  
Clock Output  
(Clock Input)  
Clock Input  
Serial Clock  
R
L
N-ch Open Drain  
SB0  
SB0 N-ch Open Drain  
Serial Data Bus  
SO  
SI  
SO  
SI  
Note Since the N-ch open drain must be turned off during data reception, FFH should be written to SIO  
beforehand. It can always be turned off during transmission.  
However, when the wake-up function specification bit (WUP) is 1, the N-ch transistor is always off, and  
therefore FFH need not be written to SIO prior to reception.  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
(7) Address match detection method  
In the SBI mode, master address communication is used to select a specific slave and start communication.  
Address match detection is performed by hardware. A slave address register (SVA) is provided, and IRQCSI is  
set only when the address sent from the master and the value set is SVA match in the wake-up state (WUP = 1).  
Note 1. Detection of the slave selected/nonselected state is performed by detection of a match with a slave  
address received after bus release (when RELD = 1).  
An address match interrupt (IRQCSI) generated when WUP = 1 is normally used for this match detection.  
Therefore, detection of selection/nonselection by the slave address should be performed with WUP =  
1.  
2.  
For selection/nonselection detection without using an interrupt when WUP = 0, the address detection  
method is not used: Instead, detection should be performed by transmission/reception of commands  
set beforehand by the program.  
(8) Error detection  
In the SBI mode, since the status of the serial bus SB0 pin during transmission is also written into the SIO shift  
register of the transmitting device, transmission errors can be detected in the following ways:  
(a) Comparison of pre-transmission and post-transmission SIO data  
In this case, a transmission error is judged to have been generated if the two data items are different.  
(b) Use of slave address register (SVA)  
Transmission is performed after also setting the send data in the SVA register. After transmission the COI  
bit of the serial operating mode register (CSIM) (the match signal from the address comparator) is tested: “1”  
indicates normal transmission, and “0”, a transmission error.  
(9) Communication operation  
With the SBI, the master normally selects the slave device to be communicated with from among the multiple  
connected devices by outputting an address onto the serial bus.  
After the target communication device has been determined, commands and data are exchanged between the  
master device and slave device, thus implementing serial communication.  
Data communication timing charts are shown in Figs. 5-49 through 5-52.  
In the SBI mode, shift register shift operations are performed in synchronization with the fall of the serial clock  
(SCK), and send data is latched in the SO latch and is output MSB-first from the SB0/P02 or P03 pin. Receive data  
input to the SB0 pin is latched in the shift register on the rise of SCK.  
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Fig. 5-49 Address Transmission form Master Device to Slave Device (WUP = 1)  
Master Device Processing  
(Transmission Side)  
Program  
Processing  
Write  
to SIO  
CMDT  
Setting  
CMDT  
Setting  
Interrupt Servicing  
(Preparation for Next Serial Transfer)  
RELT  
Setting  
SCK  
IRQCSI  
Gene-  
ration  
Hardware  
Operation  
ACKD  
Setting  
Stop-  
page  
Serial Transmit Operation  
Transfer Line  
SCK Pin  
1
2
3
7
8
9
4
5
6
READY  
ACK BUSY  
SB0 Pin  
A7  
A4  
A6  
A5  
A3  
A2  
A1  
A0  
Address  
Slave Device Processing  
(Reception Side)  
Program  
Processing  
BUSY  
Clear-  
ance  
ACKT  
Setting  
WUP  
0
IRQCSI  
Gene-  
ration  
Hardware  
Operation  
CMDD  
Clear-  
ance  
BUSY  
Clear-  
ance  
BUSY  
Output  
ACK  
Output  
CMDD  
Setting  
CMDD  
Setting  
Serial Receive Operation  
RELD  
Setting  
(When SVA = SIO)  
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Fig. 5-50 Command Transmission from Master Device to Slave Device  
Master Device Processing Transmission Side)  
Program  
Processing  
CMDT Write  
Setting  
Interrupt Servicing  
(Preparation for Next Serial Transfer)  
to SIO  
SCK  
Stop-  
page  
IRQCSI  
Genera-  
tion  
ACKD  
Setting  
Hardware  
Operation  
Serial Transmit Operation  
Transfer Line  
SCK Pin  
SB0 Pin  
1
2
3
4
5
6
7
8
9
ACK  
BUSY  
READY  
C7  
C6  
C5  
C4  
Command  
C3  
C2  
C1  
C0  
Slave Device Processing Reception Side)  
BUSY  
Clear-  
ance  
SIO  
Read  
Command  
Analysis  
ACKT  
Setting  
Program  
Processing  
IRQCSI  
Genera-  
tion  
BUSY  
Clear-  
ance  
ACK  
Output  
BUSY  
Output  
Hardware  
Operation  
CMDD  
Setting  
Serial Receive Operation  
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Fig. 5-51 Data Transmission from Master Device to Slave Device  
Master Device Processing  
(Transmission Side)  
Interrupt Servicing  
(Preparation for Next Serial Transfer)  
Write  
to SIO  
Program  
Processing  
SCK  
Stop-  
page  
IRQCSI  
Genera-  
tion  
ACKD  
Setting  
Hardware  
Operation  
Serial Transmit Operation  
Transfer Line  
SCK Pin  
1
2
3
4
5
7
8
9
6
ACK  
BUSY  
READY  
SB0 Pin  
D7  
D5  
D4  
D2  
D1  
D0  
D6  
D3  
Data  
Slave Device Processing  
(Reception Side)  
BUSY  
Clear-  
ance  
Program  
Processing  
ACKT  
Setting  
SIO  
Read  
IRQCSI  
Genera-  
tion  
BUSY  
Clear-  
ance  
ACK  
Output  
Hardware  
Operation  
BUSY  
Output  
Serial Receive Operation  
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Fig. 5-52 Data Transmission from Slave Device to Master Device  
Master Device Processing (Reception Side)  
ACKT  
Setting  
Program  
Processing  
SIO  
Read  
FFH Write  
to SIO  
FFH Write  
to SIO  
Receive Data Processing  
Serial  
SCK  
Stop-  
page  
IRQCSI  
Genera-  
Hardware  
Operation  
ACK  
Output  
Serial Receive Operation  
Reception  
tion  
Transfer Line  
SCK Pin  
1
2
3
4
5
6
7
8
9
1
2
ACK BUSY  
D7  
D6  
BUSY  
READY  
D7  
D6  
D5  
D4  
Data  
D3  
D2  
D1  
D0  
SB0 Pin  
READY  
Slave Device Processing (Transmission Side)  
Write  
Write  
Program  
to  
to  
Processing  
SIO  
SIO  
IRQCSI  
Genera-  
tion  
Hardware  
Operation  
BUSY  
Clear-  
ance  
BUSY  
Clear-  
ance  
ACKD  
Setting Output  
BUSY  
Serial Transmit Operation  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
(10) Start of transfer  
When the following two conditions are met a serial transfer is started by setting transfer data in the shift register  
(SIO).  
• The serial interface operatio enable/disable bit (CSIE) = 1.  
• After an 8-bit serial transfer, the internal serial clock is stopped or SCK is high.  
Note 1. The transfer will not be started if CSIE is set to “1” after data is written into the shift register.  
2. Since the N-ch transistor must be turned off during data reception, FFH should be written to SIO  
beforehand.  
However, when the wake-up function specification bit (WUP) is 1, the N-ch transistor is always off, and  
therefore FFH need not be written to SIO prior to reception.  
3. If data is written to SIO when the slave is in the busy state, that data is not lost.  
The transfer starts when the busy state is released and the SB0 input becomes high (ready state).  
When an 8-bit transfer ends, the serial transfer stops automatically and the IRQCSI interrupt request flag is set.  
Example In the following example the data in the RAM specified by the HL register is transferred to SIO, and at  
the same time the SIO data is fetched into the accumulator and the serial transfer is started.  
MOV XA, @HL ; Fetch send data from RAM  
XCH XA, SIO ; Exchange send data with receive data and start transfer  
(11) Points to note concerning SBI mode  
(a) Detection of the slave selected/nonselected state is performed by detection of a match with a slave address  
received after bus release (when RELD = 1).  
An address match interrupt (IRQCSI) generated when WUP = 1 is normally used for this match detection.  
Therefore, detection of selection/nonselection by the slave address should be performed with WUP = 1.  
(b) For selection/nonselection detection without using an interrupt when WUP = 0, the address detection  
method is not used: Instead, detection should be performed by transmission/reception of commands set  
beforehand by the program.  
(c) When WUP is set to 1 during BUSY signal output, BUSY is not released. With the SBI, the BUSY signal is  
output following a BUSY release directive until the next fall of the serial clock (SCK). When WUP is set to  
1, a check must be performed to ensure that SB0 has been driven high after BUSY is released before setting  
WUP to 1.  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
(12) SBI mode application  
This section presents examples of applications in which serial data communication is performed in SBI mode.  
In these application examples, the µPD75402A is operated as a slave CPU on the serial bus.  
Also, the master can be changed by a command.  
(a) Serial bus configuration  
In the serial bus configuration in the application examples given here, the µPD75402A is connected to the  
bus line as one of the devices on the serial bus.  
The µPD75402A uses two pins: The serial data bus SB0 (P02/SO), and the serial clock SCK (P01).  
An example of the serial bus configuration is shown in Fig. 5-53. Only addresses C0H through C7H can be  
allocated to the µPD75402A.  
Fig. 5-53 Example of Serial Bus Configuration  
VDD  
Master CPU  
Slave CPU  
µPD75308  
µPD75328  
SB0 (SB1)  
SB0 (SB1)  
SCK  
Address 1  
SCK  
Slave CPU  
µPD75402A  
SB0  
SCK  
Address C0H  
Slave IC  
SB0 (SB1)  
Address N  
SCK  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
(b) Description of commands  
(i) Command types  
The following command types are used in these application examples.  
READ command  
WRITE command  
END command  
: Performs data transfer from slave to master.  
: Performs data transfer from master to slave.  
: Notifies slave of completion of WRITE command.  
: Notifies slave of suspension of WRITE command.  
4
STOP command  
STATUS command : Reads slave-side status.  
6
RESET command  
: Makes currently selected slave non-selected.  
7
CHGMST command : Passes mastership to slave side.  
(ii) Communication procedure  
The procedure for communication between master and slave is as follows.  
The master starts the communication by transmitting the address of the slave to be communicated  
with and selecting the slave (chip selection).  
When the slave receives the address, it communicates with the master by returning ACK. (The  
slave changes from non-selected to selected status.)  
Communication is performed between the slave selected by the processing in and the master  
by the transfer of commands and data.  
However, as command and data transfers are one-to-one master- slave transfers, other slaves  
must be in the non-selected status.  
Communication is ended by the slave changing to non-selected status. The slave changes to non-  
selected status in the following cases:  
• When a RESET command is sent from the master, the selected slave changes to non-selected  
status.  
• When the master is changed by the CHGMST command, the device which is changed from  
master to slave changes to non-selected status.  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
(iii) Command formats  
The transfer format of each command is shown below.  
READ command  
This command performs a read from the slave. The read data length is variable between 1 and  
256 bytes, and is specified as a parameter by the master. If 00H is specified as the data length, this  
is interpreted as a 256-byte data transfer specification.  
Fig. 5-54 READ Command Transfer Format  
M
S
M
S
S
S
S
S
ACK  
ACK  
Data N  
ACK  
READ  
ACK  
Data Length  
Data 0  
Data  
Data  
Command  
Data  
Remarks M : Output by master  
S : Output by slave  
After the slave receives the data length, if the transmissible data is equal to or greater than that  
data length, the slave returns ACK. If the data is insufficient, ACK is not returned and an error is  
generated.  
When a data transfer is performed, the slave compares the SIO contents before and after the  
transfer to check whether the data was correctly output onto the bus. If the SIO contents before and  
after the transfer are different, ACK is not returned and an error is generated.  
WRITE, END and STOP commands  
This command performs a data write to the slave. The write data length is variable between 1 and  
256 bytes, and is specified as a parameter by the master. If 00H is specified as the data length, this  
is interpreted as a 256-byte data transfer specification.  
Fig. 5-55 WRITE & END Command Transfer Format  
M
M
M
S
M
S
M
S
S
S
ACK  
Data Length  
ACK  
ACK  
Data N  
ACK  
END  
ACK  
WRITE  
Data 0  
Data  
Data  
Data  
Command  
Command  
Remarks M : Output by master  
S : Output by slave  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
After the slave receives the data length, if the area for storing the receive data is at least as large as  
that data length, the slave returns ACK. If the data storage area is too small, ACK is not returned and an  
error is generated.  
When all the data has been transferred, the master sends an END command. This command notifies  
the slave that all the data has been correctly transferred.  
The slave may also receive an END command before the reception of all the data. In this case, the data  
up to the reception of the END command is valid.  
When data is transmitted, the master compares the SIO contents before and after the transmission  
to check whether the data was correctly output onto the bus. If the SIO contents before and after the  
transmission are different, the master suspends data transmission by sending a STOP command.  
Fig. 5-56 STOP Command Transfer Format  
M
S
M
S
Data  
Data  
ACK  
STOP  
ACK  
Command  
Data Check  
Error Generation  
Data Transfer Suspended  
Remarks M : Output by master  
S : Output by slave  
When the slave receives a STOP command, the byte of data received immediately before the command  
is invalid.  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
STATUS command  
This command is used to read the status of the currently selected slave.  
Fig. 5-57 STATUS Command Transfer Format  
S
M
S
S
ACK  
Status  
ACK  
STATUS  
Data  
Command  
Remarks M : Output by master  
S : Output by slave  
The format of the status byte returned by the slave is shown below.  
Fig. 5-58 STATUS Command Status Format  
MSB  
Status  
LSB  
7
6
5
4
3
2
1
0
All 0s  
Bit indicating possibility of data transmission  
0 : No data for transmission  
1 : 1 or more bytes of send data ready  
Bit indicating possibility of data reception  
0 : No receive data storage area  
1 : 1 or more bytes of receive data storage area ready  
Bit indicating error occurrence  
0 : No error  
1 : Error occurred in previous transfer  
Bit indicatin possibility of change of master  
0 : Chang of master not possible  
1 : Change of mster possible  
When the slave sends status data, it compares the SIO contents before and after transmission and  
if they do not match an error is generated and no ACK is returned.  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
RESET command  
4
This command is used to change the currently selected slave to non-selected status. All slaves  
can be placed in non-selected status by sending the RESET command.  
Fig. 5-59 RESET Command Transfer Format  
M
S
RESET  
ACK  
Command  
Remarks M : Output by master  
S : Output by slave  
CHGMST command  
This command passes mastership to the currently selected slave.  
Fig. 5-60 CHGMST Command Transfer Format  
S
M
S
S
ACK  
Data  
ACK  
CHGMST  
Data  
Command  
Remarks M : Output by master  
S : Output by slave  
When a slave receives the CHGMST command, it determines whether it can assume mastership  
and returns data to the master. This data is as follows:  
• 0FFH : Change of master possible  
• 00H : Change of master not possible  
When the slave sends this data, it compares the SIO contents before and after transmission and  
if they do not match an error is generated and no ACK is returned.  
If there is no error after the 0FFH data has been transmitted, the master operates as a slave and  
the slave operates as the master from that point on.  
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS  
(iv) Error occurrence  
Operation in the event of an error in communication is described below.  
A slave indicates the occurrence of an error by failing to return ACK to the master. When an error  
occurs, the status bit indicating the occurrence of an error is set and all command processing being  
executed is canceled.  
After sending or receiving a byte, the master checks for ACK from the slave. If ACK is not returned  
by the slave within a certain time after the end of transmission or reception, an error is judged to have  
occurred and the master outputs an ACK signal (as a dummy).  
Fig. 5-61 Master and Slave Operations after an Error  
End of Reception  
Judges error to have occurred,  
stops processing  
Slave  
Processing  
SB0  
Error Data  
ACK  
ACK Wait Time  
Master  
Processin  
Checks for ACK from slave  
Judges error to have  
occurred, outputs ACK  
End of Transmission  
Start of ACK Check  
Errors are generated in the following circumstances:  
Errors generated on the slave side  
If the command transfer format is wrong.  
If an undefined command is received.  
If the transferred data length is insufficient in a READ command.  
4
If the data storage area is too small in a WRITE command.  
If the data changes in a READ, STATUS or CHGMST command data transmission.  
ACK is not returned if any of the above cases.  
Errors generated on the master side  
If the data changes in a WRITE command data transmission, a STOP command is sent to the slave.  
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CHAPTER 6. INTERRUPT FUNCTIONS  
On the µPD75402A there are 3 vectored interrupt sources and one testable input, enabling a wide variety of  
applications to be handled.  
Moreover, the µPD75402A’s interrupt control circuit has the following special features, making possible  
extremely fast interrupt servicing.  
(a) Acknowledgment enabling/disabling is possible by means of the interrupt master enable flag (IME) and  
the interrupt enable flag (IE×××).  
(b) Any desired interrupt service start address can be set using the vector table (for rapid starting of the actual  
interrupt service program).  
(c) Interrupt request flag (IRQ×××) can be tested and cleared (allowing checking of interrupt generation by  
software).  
(d) Standby mode (HALT) can be released by an interrupt request (release source is selectable from other than  
INT0 by means of interrupt enable flag).  
6.1 INTERRUPT CONTROL CIRCUIT CONFIGURATION  
The interrupt control circuit is configured as shown in Fig. 6-1, with each hardware item mapped onto data  
memory space.  
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Fig. 6-1 Interrupt Control Circuit Block Diagram  
Internal Bus  
3
IME  
IST0  
Interrupt Enable Flag (IE×××)  
IM0  
Decoder  
Sampling Clock  
Noise Elimination  
Circuit  
VRQ1  
INT  
BT  
IRQBT  
VRQ2  
VRQ3  
Priority  
Control  
Circuit  
Vector  
Table  
Address  
Generation  
Circuit  
Edge  
INT0/P10  
INT2/P12  
IRQ0  
Detection  
Circuit  
INTCSI  
IRQCSI  
IRQ2  
Rising Edge  
Detection  
Circuit  
Analog Delay Noise  
Elimination Circuit  
Standby Release Signal  
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CHAPTER 6. INTERRUPT FUNCTIONS  
6.2 INTERRUPT SOURCE TYPES AND VECTOR TABLE  
The µPD75402A’s interrupt source types and interrupt vector table are shown in Table 6-1 and Fig. 6-2.  
Table 6-1 Interrupt Request Source Types  
Interrupt Request  
Generation Source  
Interrupt  
Internal/  
External  
Vectored Interrupt Request Signal  
(Vector Table Address)  
Priority*1  
VRQ1(0002H)  
INTBT  
Internal  
1
(Basic time interval signal from basic interval timer)  
INT0 (INT0 pin input specified edge detection)  
INTCSI (Serial data transfer termination signal)  
INT2*2 (INT2 pin input rising edge detection)  
External  
Internal  
External  
2
3
VRQ2(0004H)  
VRQ3(0008H)  
Testable input signal (sets) IRQ2 flag)  
*
1. The interrupt priority is the order of precedence when multiple interrupt requests occur simultaneously.  
2. A test source. This is affected by an interrupt enable flag in the same way as an interrupt source, but no  
vectored interrupt is generated.  
Fig. 6-2 Interrupt Vector Table  
Address  
0 0 0 2 H  
0
0
0
0
0
0
0
0
0
0
INTBT start address (high-order 3 bits)  
INTBT start address (low-order 8 bits)  
INT0 start address (high-order 3 bits)  
INT0 start address (low-order 8 bits)  
0 0 0 4 H  
0 0 0 8 H  
0
0
0
0
0
INTCSI start address (high-order 3 bits)  
INTCSI start address (low-order 8 bits)  
The interrupt priority shown in the table shows the order in which interrupts are executed when multiple interrupt  
requests are generated simultaneously or when multiple interrupt requests are pending.  
The vector table contains the interrupt service routine start addresses. Vector table setting is performed by the  
VENTn assembler pseudoinstruction.  
Example INTBT vector table setting.  
VENT1  
GOTOBT  
Address 0002  
vector table  
Symbol indicating start address  
of interrupt service routine  
Note The vector table address specified by VENTn (n = 1, 2 and 4) is address 2n.  
Example INTBT and INT0 vector table setting.  
VENT1  
VENT2  
GOTOBT  
GOTO0  
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CHAPTER 6. INTERRUPT FUNCTIONS  
6.3 INTERRUPT CONTROL CIRCUIT HARDWARE  
(1) Interrupt request flag & interrupt enable flag  
There are four interrupt request flags (IRQ×××) corresponding to the interrupt sources (interrupt: 3, test: 1) as  
follows.  
INT0 interrupt request flag (IRQ0)  
INT2 interrupt request flag (IRQ2)  
BT interrupt request flag (IRQBT)  
Serial interface interrupt request flag (IRQCSI)  
An interrupt request flag is set (1) by generation of an interrupt request and cleared (0) automatically by execution  
of an interrupt service.  
There are four interrupt enable flags (IE×××) corresponding to the interrupt request flags as follows.  
INT0 interrupt enable flag (IE0)  
INT2 interrupt enable flag (IE2)  
BT interrupt enable flag (IEBT)  
Serial interface interrupt enable flag (IECSI)  
An interrupt enable flag enables an interrupt when its contents are “1” and disables it when 0.  
When an interrupt request flag is set and the interrupt enable flag permits an interrupt, a vectored interrupt  
request (VRQn) is generated. This signal is also used to release standby mode (HALT mode) (with the exception of  
VRQ2).  
The interrupt request flags and interrupt enable flags are manipulated by bit-handling instructions and 4-bit  
memory handling instructions. In addition, the interrupt enable flags are manipulated by the EI IE××× instruction  
and the DI IE××× instruction. The SKTCLR is normally used for interrupt request flag testing.  
Example EI  
IE0  
; INT0 enabled  
DI  
IEBT  
IRQCSI  
; INTBT disabled  
SKTCLR  
; Skip and clear if IRQCSI is 1  
When the interrupt request flag is set by an instruction, although no interrupt is generated, a vectored interrupt  
is executed in the same way as when an interrupt is generated.  
With a RESET input, the interrupt request flags and interrupt enable flags are cleared (0) and all interrupts are  
disabled.  
Table 6-2 Interrupt Request Flag Setting Signal  
Interrupt Request Flag  
Interrupt Enable Flag  
Interrupt Request Flag Setting Signal  
Set by basic time interval signal from basic interval timer.  
Set by INT0/P10 pin input signal edge detection. Detected  
edge is selected by INT0 mode register (IM0).  
Set by serial interface serial data transfer operation  
termination signal.  
IRQBT  
IRQ0  
IEBT  
IE0  
IRQCSI  
IRQ2  
IECSI  
IE2  
Set by INT2/P12 pin input signal rising edge detection.  
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CHAPTER 6. INTERRUPT FUNCTIONS  
(2) External interrupt input pin hardware  
The configuration of INT0 and INT2 is shown in Fig. 6-3.  
Fig. 6-3 Configuration of INT0 and INT2  
Sampling Clock  
Noise Elimina-  
tion Circuit  
Edge Detec-  
tion Circuit  
INT0  
INT0/P10  
(IRQ0 Setting Signal)  
IM01, IM00  
IM03  
Φ
Selector  
2
fxx  
64  
Φ
Analog Delay  
Noise Elimina-  
tion Circuit  
Rising Edge  
Detection  
Circuit  
INT2  
INT2/P12  
(IRQ2 Setting Signal)  
Input Buffer  
with Hysteresis  
Characteristics  
IM0  
Input  
Buffer  
4
Internal Bus  
INT0 functions as an external interrupt input on which sampling clock noise elimination and detected edge  
selection can be performed. The INT0 noise elimination circuit detects a change in level in 2 sampling clock pulses.  
Therefore, pulses narrower than the width of the 2 cycles (2tCY* or 128/fXX) of sampling clock are eliminated as noise,  
and a pulse exceeding the width is properly acknowledged as an interrupt signal (see Fig. 6-4). One of 3 clocks can  
be selected as the timing clocks.  
*
Cycle time  
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CHAPTER 6. INTERRUPT FUNCTIONS  
Fig. 6-4 INT0 Noise Elimination Circuit Input/Output Timing  
tSMP  
tSMP  
tSMP  
tSMP  
tSMP  
➀ꢀ Sampling Cycle  
L
L
(tSMP) or Less  
INT0  
Eliminated as Noise  
H
Sheped  
Output  
➁ꢀ 1 to 2 Times tSMP  
H
L
L
L
(a)  
INT0  
Sheped  
Output  
H
L
L
(b)  
INT0  
Eliminated as Noise  
H
Sheped  
Output  
H
2 or More Times  
➂ꢀ  
L
L
tSMP  
INT0  
Sheped  
Output  
Remarks tSMP = tCY or 64/fXX  
Specification of the detected edge of the INT0 input and selection of the sampling clock is performed by the edge  
detection mode register (IM0).  
As signals are also input via the noise elimination circuit when the INT0 pin inputs data as a port, the input data  
must be of sufficient width to avoid being eliminated as noise.  
INT2 functions as an externally testable input which sets a testable flag on detection of a rising edge. Noise  
elimination by the sampling clock is not performed, but as there is a function for eliminating pulses which are  
narrower than the analog delay, a signal of adequate width must be input as in the case of INT0 (see Fig. 6-5).  
Fig. 6-5 INT2 Input Noise Elimination  
INT2 Input  
Analog  
Delay  
Analog  
Delay  
Eliminated  
as Noise  
INT2 Input  
Received  
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CHAPTER 6. INTERRUPT FUNCTIONS  
The format of the edge detection mode register (IM0) which is used to select the detected edge is shown in Fig.  
6-6. IM0 is set by 4-bit memory handling instructions.  
On an RESET input, all bits of IM0 are cleared to 0 and the rising edge is specified for INT0.  
Fig. 6-6 Edge Detection Mode Register Format  
Address  
FB4H  
3
2
0
1
0
Symbol  
IM0  
IM03  
IM01 IM00  
Detected edge specification  
0
0
1
1
0
1
0
1
Rising edge specification  
Falling edge specification  
Rising and falling edge specification  
Ignored (interrupt request flag is not set)  
Sampling clock specification  
0
1
Φ (0.95 µs/1.91 µs/15.3 µs: operating at 4.19 MHz)  
fx/64 (15.3 µs: Operating at 4.19 MHz)  
Note As the interrupt request flag may be set when the edge detection mode register is modified, the following  
procedure should be used: Disable interrupts and modify the mode register in advance, clear the interrupt  
request flag with the CLR1 instruction, and then enable interrupts again. Also, when fX/64 is selected as  
the sampling clock by modifying IM0, the interrupt request flag must be cleared after the elapse of 16  
machine cycles following the mode register modification.  
(3) Interrupt master enable flag (IME)  
The interrupt master enable flag specifies acknowledgment enabled/disabled for all interrupts.  
IME is manipulated by the EI/DI instructions.  
With a RESET input, IME is cleared to 0 and acknowledgment of all interrupts is disabled.  
Fig. 6-7 IME Format  
Address  
FB2H  
3
IME  
Interrupt master enable flag (IME)  
All interrupts are disabled, vectored interrupts  
0
are notinitiated.  
Interrupt enabling/disabling is controlled by the  
corresponding interrupt enable flag.  
1
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CHAPTER 6. INTERRUPT FUNCTIONS  
(4) Interrupt status flag  
The interrupt status flag (IST0) is the flag which shows the status of the processing currently being executed by  
the CPU, and is contained in the PSW.  
The interrupt priority control circuit performs interrupt control according to the contents of this flag as shown  
in Table 6-3.  
IST0 cannot be modified by 4-bit handling instructions or bit-handling instructions. IST0 is always set to 1 during  
interrupt servicing. Therefore, it is not possible to write 0 to IST in the interrupt service routine which would result  
in multiple interrupt.  
After being saved to stack memory together with the rest of the PSW when an interrupt is acknowledged, IST0  
is automatically set to 1. When an RETI instruction is executed, the original IST0 value (0) is restored.  
A RESET input clears (0) the flag contents.  
Table 6-3 IST0 Interrupt Servicing Status  
Executing  
Interrupt Requests of which  
Acknowledgment is Possible  
After Interrupt  
CPU Processing  
IST0  
Processing Status  
Acknowledgment  
IST0  
1
Status 0  
Status 1  
Acknowledgment of all interrupts  
possible  
Normal program  
processing in  
progress  
0
1
Acknowledgment of all interrupts  
disabled  
Interrupt servicing in  
progress  
133  
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CHAPTER 6. INTERRUPT FUNCTIONS  
6.4 INTERRUPT SEQUENCE  
When an interrupt is generated, it is serviced by the procedure shown in Fig. 6-8.  
Fig. 6-8 Interrupt Servicing Procedure  
Interrupt (INT×××) generation  
IRQxxx set  
NO  
Hold pending until  
IExxx is set  
IExxx set?  
YES  
Corresponding VRQn  
generation  
NO  
NO  
Hold pending  
until IME is set  
IME=1  
YES  
Hold pending until  
end of processing  
in execution  
IST0=0  
YES  
Save PC and PSW contents to stack memory; place data in vector table corresponding  
to initiated VRQn into PC.  
Change IST0 contents to 1  
Reset (0) acknowledged IRQxxx  
Branch to start address of interrupt service program proccessing  
134  
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CHAPTER 6. INTERRUPT FUNCTIONS  
6.5 MACHINE CYCLES BEFORE INTERRUPT SERVICING  
On the 75X, the machine cycles from the setting of the interrupt request flag (IRQn) until execution of the interrupt  
routine program are as shown below.  
(1) When IRQn is set during execution of an interrupt control instruction  
When IRQn is set during execution of an interrupt control instruction, the interrupt routine program is executed  
after 3 machine cycles of interrupt servicing have been performed following execution of the next instruction.  
Interrupt  
(INTxxx)  
generation  
A
B
C
D
A : Setting of IRQn  
B : Execution of next instruction (between 1 and 3 machine cycles depending on instruction)  
C : Interrupt servicing (3 machine cycles)  
D : Execution of interrupt routine  
Remarks 1. An interrupt control instruction is an instruction which manipulates interrupt-related hardware (data  
memory FB×H address). These instructions comprise the DI and EI instructions.  
2. The 3 machine cycles of interrupt servicing include the time for manipulation of the stack on  
acknowledgment of an interrupt, etc.  
Note 1. If there are a number of consecutive interrupt control instructions, the interrupt routine program is  
executed after 3 machine cycles of interrupt servicing have been performed following execution of the  
instruction which follows the last interrupt control instruction executed.  
2. When IRQn is set, or when the interrupt control instruction executed thereafter is a DI instruction, the  
interrupt request by which IRQn was set is held pending.  
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CHAPTER 6. INTERRUPT FUNCTIONS  
(2) When IRQn is set during execution of an instruction other than an interrupt control instruction  
(a) When IRQn is set in the last machine cycle of the instruction being executed  
In this case, the interrupt routine program is executed after 3 machine cycles of interrupt servicing have been  
performed following execution of the instruction which follows the instruction being executed.  
Instruction other  
than interrupt  
control instruction  
A
B
C
D
A : Setting of IRQn  
B : Execution of next instruction (between 1 and 3 machine cycles depending on instruction)  
C : Interrupt servicing (3 machine cycles)  
D: Execution of interrupt routine  
Note If the next instruction is an interrupt control instruction, the interrupt routine program is executed after  
3 machine cycles of interrupt servicing have been performed following execution of the instruction which  
follows the last interrupt control instruction executed. Also, if the interrupt control instruction executed  
after IRQn is set is a DI instruction, the interrupt request by which IRQn was set is held pending.  
(b) When IRQn is set before the last machine cycle of the instruction being executed  
In this case, the interrupt routine program is executed after 3 machine cycles of interrupt servicing have been  
performed following the instruction being executed.  
Instruction other  
than interrupt  
control instruction  
A
C
D
A : Setting of IRQn  
C : Interrupt servicing (3 machine cycles)  
D : Execution of interrupt routine  
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CHAPTER 6. INTERRUPT FUNCTIONS  
6.6  
INTERRUPT APPLICATIONS  
When the interrupt function is used, the following setting are first carried out in the main program.  
The interrupt enable flag corresponding to the interrupt to be used is set to “1” (EI IE××× instruction).  
If INT0 is used, the active edge is selected (IM0 setting).  
The interrupt master enable flag (IME) is set to “1” (EI instruction).  
Return from the interrupt service program is by means of an RETI instruction.  
(1) Interrupt enabling/disabling  
<Main Program>  
Reset  
Interrupts disabled  
EI IE0  
EI IECSI  
EI  
INT0 & INTCSI enabled  
DI IE0  
INTCSI enabled  
DI  
Interrupts disabled  
All interrupts disabled by RESET input.  
Interrupt enable flag set by EI IE××× instruction.  
At this stage, all interrupts are still disabled.  
Interrupt master enable flag set by EI instruction.  
At this stage, INT0 & INTCSI are enabled.  
4
Interrupt enable flag cleared by DI IE××× instruction; INT0 disabled.  
All interrupts disabled by DI instruction.  
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CHAPTER 6. INTERRUPT FUNCTIONS  
(2) Example using INTBT, INT0 (falling edge active), and INTCSI  
<Main Program>  
; MBE = 0  
Reset  
MOV  
MOV  
CLR1  
A, #1  
IM0, A  
IRQ0  
IEBT  
IE0  
EI  
EI  
EI  
EI  
IECSI  
Status 0  
<INT0 Service Program>  
INT0  
Status 1  
RETI  
Status 0  
4
All interrupts disabled and status 0 set by RESET input.  
INT0 set to falling edge active.  
Interrupts enabled by EI and EI IE××× instructions.  
On fall of INT0, INT0 interrupt service program is started, status is changed to 1 and all interrupts are  
disabled.  
RETI instruction effects return from interrupt, restores status to 0, and enables interrupts.  
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CHAPTER 6. INTERRUPT FUNCTIONS  
(3) Pending interrupt execution - interrupt input in interrupt disabled state  
<Main program>  
Reset  
EI IE0  
<INT0 Service Program>  
INT0  
EI  
INTCSI  
RETI  
<INTCSI Service Program>  
EI IECSI  
RETI  
4
Although INT0 is set in the interrupt disabled state, the interrupt flag is held pending.  
The INT0 service program is started at point at which interrupts are enabled by the EI instruction.  
Same as .  
The INTCSI service routine is started at the point at which the pending INTCSI is enabled.  
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CHAPTER 6. INTERRUPT FUNCTIONS  
(4) Pending interrupt execution  
<Main Program>  
<Main Program>  
Reset  
EI  
EI  
EI  
IECSI  
IE0  
<INT0 Service Program>  
INT0  
INTCSI  
RETI  
<INTCSI Service Program>  
RETI  
If INT0 and INTCSI are generated simultaneously (during execution of the same instruction), INT0, which  
has the higher interrupt priority, is executed first (INTCSI is held pending).  
When the INT0 service program is ended by the RETI instruction, the pending INTCSI service program is  
started.  
140  
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CHAPTER 7. STANDBY FUNCTION  
The µPD75402A has a standby function which can reduce the system power consumption. The standby function  
has the following two modes:  
• STOP mode  
• HALT mode  
(1) STOP mode  
In this mode, the main system clock oscillator is stopped and the whole system stops. The CPU current drain is  
reduced considerably.  
Data memory low voltage (up to VDD = 2 V) hold is also possible. Therefore, this mode is effective when retaining  
the contents of data memory at an ultra-low current drain.  
The µPD75402A STOP mode cannot be reset by interrupt request. It is reset only by RESET input.  
(2) HALT mode  
This mode stops the CPU operation clock. The system clock oscillator continues to oscillate. In this mode, the  
current drain is not reduced as much as the STOP mode, but this mode is effective when desiring to resume  
processing immediately by interrupt request and when desiring to perform intermittent operation, such as timer  
operation.  
The HALT mode is reset by RESET input or interrupt request.  
In either mode, the contents of the registers, flags, and data memory immediately before setting to the standby  
mode are retained. Because the states of the I/O port output latch and the output buffer are retained, the state of  
the I/O ports is preprocessed so that the current drain of the entire system is minimum.  
Note 1. Low current, low voltage operation is possible by switching the standby mode and CPU clock. However,  
in either case, the time described in paragraph 5.2.3 is necessary between operation of the PCC register  
and selection of the new clock and the start of operation by the new clock after switching. Therefore,  
when combining the clock switching function and standby mode, set the µPD75402A to the standby  
mode after the time required for switching has elapsed.  
2. When using the standby mode, ensure that the consumption current at the input/output is a minimum.  
In particular, do not leave the input port open : be sure to input a low-level or high-level signal.  
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CHAPTER 7. STANDBY FUNCTION  
7.1 STANDBY MODE SETTING AND OPERATION STATES  
Table 7-1 Standby Mode Operation States  
STOP Mode  
HALT Mode  
Setting instruction  
Clock generator  
STOP instruction  
HALT instruction  
CPU clock Φ only stopped oscillator  
(oscillation continues)  
Clock oscillation stopped  
Operation  
(IRQBT set at basic time interval)  
Operation stopped  
Basic interval timer  
Serial interface  
Operation possible  
Operation possible only when external  
SCK input selected as serial clock  
Output other than CPU clock Φ possible  
Operation stopped  
Clock output circuit  
External interrupt  
INT2 : Operation possible  
INT0 : Operation impossible  
CPU  
Operation stopped  
Interrupt request signal from operable  
RESET input  
Reset signal  
hardware enabled by interrupt enable  
flag or RESET input.  
The STOP mode is set by STOP instruction and the HALT mode is set by HALT instruction. (The STOP instruction  
and HALT instruction set bits 3 and 2 of the PCC respectively.)  
Always write an NOP instruction after the STOP instruction or HALT instruction.  
When the CPU operation clock is changed by means of the low-order two bits of the PCC, a time lag may be  
generated between rewriting of the PCC and changing of the CPU clock. Therefore, when changing the operating  
clock before the standby mode and when changing the CPU clock after standby mode reset, set the standby mode  
after the number of machine cycles required to change the CPU clock has elapsed after the PCC is rewritten.  
In the standby mode, the data of the general register, flags, mode registers, output latch, and all the other registers  
which stop operating in the standby mode and the data memory is retained.  
Notes are given below.  
Note 1. When the STOP mode is set, the X1 pin is shorted internally to VSS (GND potential) to suppress clock  
oscillator leakage. Therefore, do not use the STOP mode with systems that use an external clock.  
2. STOP mode reset by interrupt request differs as follows for the µPD75402A and the evachip installed  
on the evaluation board:  
µPD75402A  
Evachip  
••••••  
STOP mode not reset by interrupt request.  
STOP mode reset by interrupt request.  
••••••••••••••  
To eliminate the affect of this difference, disable all interrupt requests before setting the µPD75402A  
to the STOP mode.  
3. From the standpoint that an interrupt request signal is used to reset the HALT mode, when there is an  
interrupt source which sets both the interrupt request flag and interrupt enable flag (1), the HALT mode,  
even if entered, is immediately reset.  
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CHAPTER 7. STANDBY FUNCTION  
7.2 STANDBY MODE RESET  
The STOP mode is reset only by RESET input. The HALT mode is reset by standby release signal by setting of  
an interrupt request flag enabled by the interrupt enable flag and by RESET input.  
The standby mode reset operation is shown in Fig. 7-1.  
Note When a standby mode (STOP/HALT) was reset by RESET input, theµPD75402A does not insert a wait before  
the start of instruction execution. Instruction execution begins simultaneously with resetting of the  
standby mode.  
(1) STOP mode reset by RESET input  
When the RESET input drops from high to low, the oscillator begins to oscillate simultaneously with entry into  
the reset state.  
When the RESET input level returns from low to high, instruction execution begins even if oscillation is unstable.  
Therefore, provide an oscillation stabilization time by making the RESET input low level sufficiently wide.  
When the reset state is released, the program branches to the reset start address.  
This is different from normal reset operation because the contents of data memory before STOP mode setting  
are retained.  
(2) HALT mode reset by RESET input  
When the RESET input drops from high to low, the HALT mode is reset and the µPD75402A enters the reset state.  
When the RESET input level returns from low to high, the program branches to the reset start address and  
instruction execution begins.  
This is different from the normal reset operation because the contents of data memory before HALT mode setting  
are retained.  
(3) HALT mode reset by interrupt generation  
When an interrupt request flag enabled by interrupt enable flag is set (1), a standby release signal is generated  
and the HALT mode is reset. However, the INT0 interrupt request does not generate the standby release signal.  
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CHAPTER 7. STANDBY FUNCTION  
Fig. 7-1 Standby Mode Reset Operation  
(a) STOP mode reset by RESET input  
Oscillation  
Stabilization Time  
STOP  
Instruction  
RESET  
Input  
Operating  
Mode  
Operating  
Mode  
STOP Mode  
HALT Mode  
Oscillation  
Oscillation  
Stopped  
Oscillation  
Clock  
(b) HALT mode reset by RESET input  
HALT  
Instruction  
RESET  
Input  
Operating  
Mode  
HALT Mode  
Operating Mode  
Oscillation  
Clock  
(c) HALT mode reset by interrupt generation  
2 Instructions  
Execution  
HALT  
Instruction  
Standby  
Rlease  
Signal  
Operating  
Mode  
HALT Mode  
Operating Mode  
Oscillation  
Clock  
Remarks The broken line is for the case when an interrupt request that reset the HALT mode was accepted (IME  
= 1).  
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CHAPTER 7. STANDBY FUNCTION  
7.3 OPERATION AFTER STANDBY MODE RESET  
(1) When the standby mode was reset by RESET input, normal reset operation is executed. (STOP and HALT modes)  
(2) When the standby mode was reset by interrupt request generation, whether or not a vector interrupt is executed  
when the CPU resumes instruction execution is determined by the contents of the interrupt master enable flag  
(IME). (HALT mode)  
(a) IME = 0  
After HALT mode reset, execution is resumed from the instruction (NOP instruction) after the HALT mode  
setting instruction.  
The interrupt request flag is held.  
(b) IME = 1  
After HALT mode is reset, a vector interrupt is executed two instructions after the HALT mode setting  
instruction. However, because a vector interrupt is not generated when the HALT mode was reset by INT2  
(testable input), the same processing as (a) is performed.  
7.4 STANDBY MODE APPLICATION  
When using the standby mode, proceed as follows:  
Power interruption or other standby mode setting cause detection by interrupt input or port input.  
I/O port processing (Process for minimum current drain)  
In particular, do not leave the input port open : be sure to input a low-level or high-level signal.  
Specification of interrupt which resets the standby mode (However, for HALT mode, interrupt enable flags  
which is not reset are cleared.)  
4
Specification of operation after reset (IME is operated according to whether or not interrupt processing  
is performed after HALT mode resetting.)  
6
Specification of CPU clock after reset (For switching, provide the number of machine cycles necessary up  
to standby mode setting.)  
Standby mode setting (STOP and HALT instructions)  
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CHAPTER 8. RESET FUNCTION  
When low level is input to the RESET pin, system reset is applied and the hardware enters the state shown in  
Table 8-1.  
When the RESET input goes from low level to high level, the reset state is released. Then, the contents of the  
lower-order three bits of address 000H of the reset vector table are set into program counter (PC) bits 10 to 8 and  
the contents of the low-order three bits of address 001H are set into PC bits 7 to 0 and the program branches and  
begins executing from that branch address. Therefore, reset and starting from an arbitrary address is possible.  
Initialize the contents of each register as required in the program.  
The RESET pin is a Schmitt-triggered input with hysteresis characteristics at the threshold level. To prevent  
misoperation by noise, a function which rejects narrow band noise by analog delay is also provided on the chip  
(see Fig. 8-1).  
For reset operation at power-on, provide an ample oscillation stabilization time from power-on to reset signal  
acceptance as shown in Fig. 8-2.  
Fig. 8-1 Reset Signal Acceptance  
RESET  
Reset branch destination  
address instruction  
execution  
Contents of reset  
Analog  
Delay  
Analog  
Delay  
Analog  
Delay  
vector table set  
in PC (PC initialize)  
Rejected  
as Noise  
Reset  
Acceptance  
Reset  
Release  
Fig. 8-2 Reset at Power-on  
V
DD  
RESET  
Reset branch  
destination address  
instruction execution  
Contents of reset  
vector table set  
in PC (PC initialize)  
Oscillation  
Stabilization  
Time  
Analog  
Delay  
Reset  
Release  
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CHAPTER 8. RESET FUNCTION  
Table 8-1 State of Hardware after Reset  
RESET Input  
standby mode  
RESET Input  
during operation  
Hardware  
Low-order 3 bits of  
program memory address program memory address  
Low-order 3 bits of  
Program counter (PC)  
000H set in PC10 to PC8  
and contents of address  
001H set in PC7 to PC0  
000H set in PC10 to PC8  
and contents of address  
001H set in PC7 to PC0  
Carry flag (CY)  
Skip flag (SK0 to SK2)  
Interrupt status flag (IST0)  
Retained  
Undefined  
PSW  
0
0
0
Undefined  
Retained*  
Retained  
Undefined  
0
0
Stack pointer (SP)  
Undefined  
Undefined  
Data Memory (RAM)  
General register (X, A, H, L)  
Basic interval timer  
Undefined  
Counter (BT)  
Undefined  
Mode register (BTM)  
0
Shift register (SIO)  
Retained  
0
Undefined  
Serial interface  
Operation mode register (CSIM)  
SBI control register (SBIC)  
Slave address register (SVA)  
0
0
0
Retained  
0
Undefined  
0
Processor clock control register  
(PCC)  
Clock generator,  
clock output circuit  
Clock output mode register  
(CLOM)  
0
0
Interrupt function  
Interrupt request flag (IRQ×××)  
Interrupt enable flag (IE×××)  
Interrupt master enable flag (IME)  
INT0 mode register (IM0)  
Output buffer  
Reset (0)  
Reset (0)  
0
0
0
0
0
0
Digital input/output port  
OFF  
OFF  
Output latch  
Clear (0)  
Clear (0)  
I/O mode register (PMGA, PMGB)  
0
0
0
0
Pull-up resistor specification  
register (POGA)  
Pin state  
Pin state P00 to P03, P10, P12, P20  
to P23, P30 to P33, P60 to P63  
Input  
Input  
P50 to P53  
On-chip pull-up resistor  
••••• High level  
Open-drain  
On-chip pull-up resistor  
••••• High level  
Open-drain  
••••• High impedance  
••••• High impedance  
*
The contents of data memory addresses 038H to 03DH are made undefined by RESET input.  
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CHAPTER 9. INSTRUCTION SET  
The 75X series instruction set is an improved and expanded version of old µPD7500 series instruction set. It is  
a revolutionary new instruction set which retains succession from the µPD7500 series. The µPD75402A instruction  
set is a 75X instruction subset, and has the following features:  
(1) Multipurpose bit manipulation instruction  
(2) Efficient 4-bit manipulation instruction  
(3) 8-bit data transfer instruction  
(4) Stack instructions and base correction instructions with increase program efficiency  
(5) Table reference instructions suitable for continuous reference  
(6) 1-byte relative branch instruction  
(7) Easy to understand NEC standard mnemonics  
For the addressing modes which can be used when operating the data memory, see CHAPTER 3 “FEATURES OF  
ARCHITECTURE AND MEMORY MAP”.  
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CHAPTER 9. INSTRUCTION SET  
9.1 SPECIAL INSTRUCTIONS  
This section outlines the special instructions of the µPD75402A instruction set.  
9.1.1 Bit Manipulation Instructions  
µPD75402A bit manipulation can be performed by various instructions, such as the following:  
(a) Bit set  
:
SET1  
SET1  
CLR1  
CLR1  
SKT  
mem. bit  
fmem. bit  
mem. bit  
fmem. bit  
mem. bit  
fmem. bit  
mem. bit  
fmem. bit  
(b) Bit clear:  
(c) Bit test :  
(d) Bit test :  
SKT  
SKF  
SKF  
(e) Bit test & clear :  
SKTCLR fmem. bit  
(f) Boolean operation:  
AND1  
OR1  
CY, fmem. bit  
CY, fmem. bit  
CY, fmem. bit  
XOR1  
fmem. bit is the bit address specified by special address bit manipulation addressing.  
Especially, since I/O ports can always use all the bit manipulation instructions above, I/O port operation can be  
performed very efficiently.  
9.1.2 Stack Instructions  
The following two kinds of stack instructions are available with the µPD75402A.  
(a) MOV A, #n4 or MOV XA, #n8  
(b) MOV HL, #n8  
“Stack” signifies that these two kinds of instructions are placed in contiguous addresses.  
Example A0 : MOV A,  
#0  
#1  
A1 : MOV A,  
XA7: MOV XA, #07  
When stack instructions are stacked such as in the example above, when the address executed first is A0, it is  
executed by replacing the next two instructions with NOP instructions. When the address executed first is A1, it is  
executed by replacing the next instruction with an NOP instruction. That is, only the instruction executed first is  
effective, all the stack instructions following it are processed as NOP instructions.  
Constants can be efficiently set to accumulator (A register, register pair XA) and data pointer (register pair HL)  
by using these stack instructions.  
149  
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CHAPTER 9. INSTRUCTION SET  
9.1.3 Base Correction Instructions  
Depending on the application, the result of addition of 4-bit data must be converted to decimal numbers or to  
base-6, such as time.  
Base correction instructions for converting the result of addition of 4-bit data to an arbitrary base are available  
with the µPD75402A instruction set.  
(a) Base correction at addition  
If the base value to be corrected is made m, accumulator and memory (HL) are added and the sum is converted  
to base-m by combination:  
-
ADDS A, #16 m  
ADDC A, @HL  
ADDS A, #m  
; A, CY A + (HL) + CY  
Overflow remains in the carry flag.  
When a carry is output as a result of execution of the ADDC A, @HL instruction, the following ADDS A, #n4  
instruction is skipped. If carry is not output, the ADDS A, #n4 instruction is executed. At this time, this instruction  
skip function is disabled and the next instruction is not skipped even if carry is output as the result of addition.  
Therefore, the program can continue after the ADDS A, #n4 instruction.  
Example Decimal add accumulator and memory.  
ADDS  
ADDC  
ADDS  
A, #6  
A, @HL  
A, #10  
; A, CY A + (HL) + CY  
9.1.4 Skip Instruction and Number of Machine Cycles Required by Skip  
With the µPD75402A instruction set, a program is formed by condition judgment by skip.  
If the skip condition is satisfied when a skip instruction is executed, the following instruction is skipped and the  
instruction after the instruction is executed.  
When a skip was generated, one machine cycle is required to skip.  
150  
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CHAPTER 9. INSTRUCTION SET  
9.2 INSTRUCTION SET AND ITS OPERATION  
(1) Operation identifier and description  
The operands are described in the operand field of each instruction in accordance with the description for the  
operand identifier of the instruction. (See "RA 75X Assembler Package User's Manual Language Volume (EEU-730)  
for details.) For parameters with multiple elements in the description, one of the elements is selected. Upper case  
letters and the symbols #, @, !, and $ are key words and described unchanged.  
For immediate data, a suitable value or label is described.  
Instead of mem, fmem, bit, etc., various kinds of registers and flag symbols shown in Table 3-4 can be written  
as labels (however, in the case of fmem there are restrictions on the labels that can be written. See Table 3-3  
"Applicable Addressing Modes at Peripheral Hardware Operation" and Table 3-4" µPD75402A I/O Map" for details.  
Identifier  
Description  
reg  
X, A, H, L  
X, H, L  
reg1  
rp  
XA, HL  
n4  
4-bit immediate data or label  
8-bit immediate data or label  
8-bit immediate data or label*  
2-bit immediate data or label  
FB0H to FBFH, FF0H to FFFH immediate data or label  
11-bit immediate data or label  
11-bit immediate data or label  
11-bit immediate data or label  
PORT0 to PORT3, PORT5, PORT6  
IEBT, IECSI, IE0, IE2  
n8  
mem  
bit  
fmem  
addr  
caddr  
faddr  
PORTn  
IE×××  
*
For 8-bit data processing, mem can describe even address only.  
(2) Operation description legend  
A
: A register; 4-bit accumulator  
H
: H register  
L
: L register  
X
: X register  
XA  
HL  
: Register pair (XA); 8-bit accumulator  
: Register pair (HL)  
PC  
: Program counter  
SP  
: Stack pointer  
CY  
: Carry flag; bit accumulator  
: Program status word  
: Port n (n = 0 to 3, 5, 6)  
: Interrupt master enable flag  
: Interrupt enable flag  
: Processor clock control register  
: Address, bit delimiter  
: Contents addressed by ××  
: Hexadecimal data  
PSW  
PORTn  
IME  
IE×××  
PCC  
.
( ×× )  
××H  
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CHAPTER 9. INSTRUCTION SET  
(3) Description of addressing area field symbols  
* 1  
MB = 0  
* 2  
MB = 0 (00H to 3FH)  
Data memory  
addressing  
MB = 15 (80H to FFH)  
* 3  
MB = 15, fmem = FB0H to FBFH,  
FF0H to FFFH  
* 4  
addr = 000H to 77FH  
* 5  
addr = (Current PC) – 15 to (Current PC) – 1,  
(Current PC) + 16 to (Current PC) + 2  
caddr = 000H to 77FH  
Program memory  
addressing  
* 6  
* 7  
faddr = 000H to 77FH  
Remarks 1. MB is the accessible memory bank.  
2. *4 to *7 are the addressable areas.  
(4) Description of machine cycle field  
S is the number of machine cycles required when the skip operation is performed by an instruction with skip.  
The value of S changes as follows:  
• Do not skip next instruction ..... S = 0  
• Skip next instruction ................. S = 1  
One machine cycle equals one cycle of CPU clock Φ. Three times can be selected by PCC setting. (See section  
5.2.2(1).)  
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CHAPTER 9. INSTRUCTION SET  
Machine  
Addressing  
Area  
Skip  
Note 1  
Bytes  
Operation  
Mnemonic  
Operand  
A, #n 4  
Cycle  
Condition  
1
2
2
1
1
2
2
2
2
1
2
2
1
1
1
1
1
1
1
1
1
2
1
2
1
2
1
1
1
1
1
1
2
2
1
1
2
2
2
2
1
2
2
1
3
A n 4  
Stack A  
Stack A  
Stack B  
XA, #n 8  
HL, #n 8  
A, @HL  
@HL, A  
A, mem  
XA, mem  
mem, A  
mem, XA  
A, @HL  
A, mem  
XA, mem  
A, reg1  
XA, @PCXA  
A, #n 4  
A, @HL  
A, @HL  
A. @HL  
A, @HL  
A, @HL  
A
XA n 8  
HL n 8  
A (HL)  
(HL) A  
A (mem)  
*1  
*1  
*2  
*2  
*2  
*2  
*1  
*2  
*2  
MOV  
XA (mem)  
(mem) A  
(mem) XA  
A (HL)  
A (mem)  
XCH  
XA (mem)  
A reg1  
MOVT  
ADDS  
XA (PC10 – 8 + XA) ROM  
A A + n 4  
1 + S  
carry  
carry  
1 + S  
A A + (HL)  
A, CY A + (HL) + CY  
A A (HL)  
A A (HL)  
A A (HL)  
CY A0, A3 CY, An–1 An  
A A  
*1  
*1  
*1  
*1  
*1  
ADDC  
AND  
OR  
1
1
1
XOR  
RORC  
NOT  
1
1
A
2
reg  
1 + S  
2 + S  
1 + S  
2 + S  
1 + S  
1
reg reg + 1  
(mem) (mem) + 1  
reg reg – 1  
Skip if reg = n 4  
Skip if A = (HL)  
CY 1  
reg = 0  
INCS  
mem  
*2  
*1  
(mem) = 0  
reg = FH  
reg = n4  
A = (HL)  
DECS  
reg  
reg, #n 4  
A, @HL  
CY  
SKE  
SET 1  
CLR 1  
SKT  
CY  
1
CY 0  
CY  
1 + S  
1
Skip if CY = 1  
CY CY  
CY = 1  
NOT 1  
CY  
Note 1. Instruction Group  
2. Accumulator operation instructions  
3. Increment/decrement instructions  
4. Compare instructions  
153  
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CHAPTER 9. INSTRUCTION SET  
Machine  
Addressing  
Area  
Skip  
Note  
Bytes  
Operation  
(mem. bit) 1  
Mnemonic  
Operand  
mem. bit  
Cycle  
Condition  
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
*2  
*3  
*2  
*3  
*2  
*3  
*2  
*3  
*3  
*3  
*3  
*3  
*4  
SET 1  
CLR 1  
SKT  
f mem. bit  
mem. bit  
(f mem.bit) 1  
(mem. bit) 0  
f mem. bit  
mem. bit  
(f mem. bit) 0  
2 + S  
Skip if (mem. bit) = 1  
Skip if (f mem. bit) = 1  
Skip if (mem. bit) = 0  
Skip if (f mem. bit) = 0  
Skip if (f mem. bit) = 1 and clear  
CY CY (f mem. bit)  
CY CY (f mem. bit)  
CY CY (f mem. bit)  
PC 10 – 0 addr  
(mem. bit) = 1  
(f mem. bit) = 1  
(mem. bit) = 0  
(f mem. bit) = 0  
(f mem. bit) = 1  
f mem. bit  
mem. bit  
2 + S  
2 + S  
2 + S  
2 + S  
2
SKF  
f mem. bit  
f mem. bit  
CY, f mem. bit  
CY, f mem. bit  
CY, f mem. bit  
addr  
SKTCLR  
AND 1  
OR 1  
2
XOR 1  
2
The assembler selects the opti-  
mum instruction from among  
BR  
(
)
BRCB!, caddr, and BR$ addr.  
$addr  
1
2
2
2
PC 10 – 0 addr  
*5  
*6  
BRCB  
! caddr  
PC 10 – 0 caddr  
(SP–4) (SP –1) (SP–2) 0, PC 10 – 0  
(SP – 3) 0000  
CALLF  
! faddr  
2
1
1
2
3
*7  
PC 10 – 0 faddr, SP SP – 4  
PC 10 – 0 (SP) (SP + 3) (SP + 2)  
SP SP + 4  
RET  
PC 10 – 0 (SP) (SP + 3) (SP + 2)  
SP SP + 4,  
RETS  
3 + S  
None  
then skip unconditionally  
PC 10 – 0 (SP) (SP + 3) (SP + 2)  
PSW (SP + 4) (SP + 5),  
SP SP + 6  
RETI  
1
3
PUSH  
POP  
rp  
rp  
1
1
2
2
2
2
1
1
2
2
2
2
(SP–1) (SP–2) rp, SP SP–2  
rp (SP + 1) (SP) , SP SP + 2  
IME (IPS. 3) 1  
EI  
IE×××  
IE××× ← 1  
IME (IPS. 3) 0  
DI  
IE×××  
IE××× ← 0  
Note Instruction Group  
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CHAPTER 9. INSTRUCTION SET  
Machine  
Addressing  
Area  
Skip  
Bytes  
Operation  
Mnemonic  
Operand  
Note 1  
Cycle  
Condition  
IN  
A, PORTn  
PORTn, A  
2
2
2
2
1
2
2
2
2
1
A PORTn (n = 0 – 3, 5, 6)  
PORTn A (n + 2, 3, 5, 6)  
Set HALT Mode (PCC.2 1)  
Set STOP Mode (PCC.3 1)  
No Operation  
OUT  
HALT  
STOP  
NOP  
Note 1. Instruction Group  
2. I/O instructions  
155  
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CHAPTER 9. INSTRUCTION SET  
9.3 OPERATION CODE OF EACH INSTRUCTION  
(1) Description of operation code symbols  
R1  
0
R0  
0
reg  
A
P1  
0
reg-pair  
XA  
rp  
0
1
X
1
HL  
reg  
1
0
L
reg 1  
1
1
H
N2  
0
N1  
0
N0  
0
IE×××  
IEBT  
IECSI  
IE0  
1
0
1
1
1
0
1
1
1
IE2  
In : Immediate data for n4, n8  
Dn : Immediate data for mem  
Bn : Immediate data for bit  
Nn : Immediate data for n, IE×××  
An : Immediate data for [relative address distance with branch address (2 to 16)] - 1  
Sn : Immediate data for one’s complement of [relative address distance with branch address (15 to 1)]  
(2) Bit manipulation addressing operation code  
bit-addr of the second byte of the operation code of an instruction with fmem. bit at the operands is shown below.  
bit-addr  
Accessible bits  
Operable bits of FB0H to FBFH  
Operable bits of FF0H to FFFH  
1
1
0
1
B1  
B1  
B0  
B0  
F3  
F3  
F2  
F2  
F1  
F1  
F0  
F0  
Bn : Immediate data for bit address (0 to 3) described at bit  
Fn : Immediate data for low-order four bits of address described at fmem  
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CHAPTER 9. INSTRUCTION SET  
Operation Code  
Mnemonic  
Note 1  
Operand  
B1  
B2  
A, #n 4  
0
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
0
0
0
1
0
0
1
1
1
1
0
0
0
0
0
0
1
0
1
0
0
1
1
1
1
1
0
1
1
1
1
0
0
1
1
1
0
0
1
0
1
0
1
1
0
0
0
0
0
0
0
1
1
0
0
1
0
0
0
0
0
1
1
0
1
1
1
1
0
1
0
1
0
1
1
1
0
0
0
1
0
0
0
1
1
I3  
1
0
1
0
0
0
0
1
0
0
1
0
I3  
0
1
0
0
0
1
1
0
0
1
1
0
0
0
0
0
I2  
0
0
0
0
0
0
0
0
0
0
0
0
I2  
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
I1  
P1  
0
I0  
1
rp, #n 8  
A, @HL  
@HL, A  
A,mem  
XA, mem  
mem, A  
mem, XA  
A, @HL  
A, mem  
XA, mem  
A, reg1  
XA, @PCXA  
A, #n 4  
A, @HL  
A, @HL  
A, @HL  
A, @HL  
A, @HL  
A
I7  
I6  
I5  
I4  
I3  
I2  
I1  
I0  
1
0
0
MOV  
1
1
D7  
D7  
D7  
D7  
D6  
D6  
D6  
D6  
D5  
D5  
D5  
D5  
D4  
D4  
D4  
D4  
D3  
D3  
D3  
D3  
D2  
D2  
D2  
D2  
D1  
D1  
D1  
D1  
D0  
0
1
0
1
1
D0  
0
1
0
0
1
1
1
D7  
D6  
D6  
D5  
D5  
D4  
D4  
D3  
D3  
D2  
D2  
D1  
D1  
D0  
XCH  
1
0
D7  
0
R1  
0
R0  
0
MOVT  
ADDS  
I1  
1
I0  
0
ADDC  
AND  
OR  
0
1
0
0
0
0
XOR  
RORC  
NOT  
0
0
0
0
A
0
1
0
D7  
I7  
1
D6  
I6  
0
D5  
I5  
1
D4  
I4  
1
D3  
0
1
D2  
0
1
1
reg  
R1  
1
R0  
0
INCS  
DECS  
SKE  
mem  
D1  
R1  
D0  
R0  
reg  
R1  
1
R0  
0
reg, #n 4  
A, @HL  
CY  
0
0
SET 1  
CLR 1  
SKT  
1
1
CY  
1
0
CY  
1
1
NOT 1  
CY  
1
0
Note 1. Instruction Group  
2. Accumulator operation instructions  
3. Increment/decrement instructions  
4. Compare instruction  
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CHAPTER 9. INSTRUCTION SET  
Operation Code  
Note 1 Mnemonic  
Operand  
B1  
B2  
mem. bit  
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
0
1
1
1
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
B1  
0
B0  
1
0
1
0
1
0
1
0
1
1
1
1
1
A3  
S3  
0
0
1
0
1
1
1
1
1
1
1
0
0
1
1
0
1
1
0
0
1
1
D7  
D7  
D7  
D7  
D6  
D6  
D6  
D6  
D5  
D5  
D5  
D5  
D4  
D3  
D3  
D3  
D3  
D2  
D2  
D2  
D2  
D1  
D1  
D1  
D1  
D0  
D0  
D0  
0
SET 1  
f mem. bit  
mem. bit  
bit-addr  
D4  
B1  
0
B0  
1
1
0
0
CLR 1  
SKT  
f mem. bit  
mem. bit  
1
0
0
bit-addr  
D4  
B1  
1
B0  
1
1
1
1
f mem. bit  
mem. bit  
1
1
1
bit-addr  
D4  
B1  
1
B0  
1
1
1
0
SKF  
f mem. bit  
f mem. bit  
CY, f mem. bit  
CY, f mem. bit  
CY, f mem. bit  
1
1
0
bit-addr  
bit-addr  
bit-addr  
bit-addr  
bit-addr  
SKTCLR  
AND 1  
OR 1  
0
1
1
1
1
1
0
1
0
0
1
0
1
1
0
XOR 1  
1
1
1
0
0
(+16)  
0
0
A2  
S2  
A1  
S1  
A0  
S0  
(+ 2)  
(– 1)  
BR  
$addr  
1
1
(–15)  
BRCB  
CALLF  
RET  
! caddr  
! faddr  
0
1
caddr  
faddr  
0
0
1
0
1
0
1
0
0
1
1
1
1
0
0
1
1
0
1
0
0
0
1
1
0
1
1
0
0
1
1
1
1
0
RETS  
RETI  
1
0
1
0
1
PUSH  
POP  
rp  
rp  
0
0
P1  
P1  
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
0
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
0
0
0
0
N2  
0
1
N1  
1
0
N0  
0
EI  
IE×××  
0
1
0
0
1
0
DI  
IE×××  
0
1
0
N2  
N2  
N2  
0
N1  
N1  
N1  
1
N0  
N0  
N0  
1
IN  
A, PORTn  
PORTn, A  
1
0
1
OUT  
HALT  
STOP  
NOP  
0
1
1
0
1
0
0
1
0
0
1
1
1
0
0
Note 1. Instruction Group  
2. Branch instructions  
3. I/O instructions  
4. CPU control instructions  
158  
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CHAPTER 9. INSTRUCTION SET  
9.4 INSTRUCTION FUNCTIONS AND APPLICATION  
9.4.1 Move Instructions  
MOV A, #n4  
Function: A n4; n4 = I3 to I0 : 0 to FH  
Moves 4-bit immediate data n4 to the A register (4-bit accumulator).  
This instruction has a stacking effect (group A). When placed after a MOV A, #n4 or MOV XA, #n8 instruction,  
stack instructions following the executed instruction are processed as NOP.  
Application examples: Set 0BH into accumulator.  
MOV A, #0BH  
Select the data to be output at Port 3 from 0 to 2.  
A0: MOV A, #0  
A1: MOV A, #1  
A2: MOV A, #2  
OUT PORT 3, A  
MOV rp, #n8  
Function: rp n8; n8 = I7 to I0 : 00H to FFH  
Moves 8-bit immediate data n8 to register pair rp (XA, HL).  
This instruction has a stacking effect. There are two stacking effects: Group A (MOV A, #n4 instruction and  
MOV XA, #n8 instruction), and group B (MOV HL, #n8 instruction). When instructions of the same group are  
placed consecutively, the stack instructions after the executed instruction are processed as NOP.  
Application example: Set 5FH into register pair HL.  
MOV HL, #5FH  
MOV A, @HL  
Function: A (HL)  
Moves the data memory contents addressed by the contents of register pair HL to the A register.  
Application example: Move the data of address 3EH to the A register.  
MOV HL, #3EH  
MOV A, @HL  
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CHAPTER 9. INSTRUCTION SET  
MOV @HL, A  
Function: (HL) A  
Moves the contents of the A register to the data memory addressed by the contents of register pair HL.  
MOV A, mem  
Function: A (mem); mem = D7 to D0 : 00H to 3FH  
Moves the data memory contents addressed by 8-bit immediate data mem to the A register.  
MOV XA, mem  
Function: A (mem), X (mem + 1); mem = D7 to D0 : 00H to 3EH  
Moves the data memory contents addressed by 8-bit immediate data mem to the A register and the contents  
of the next address to the X register.  
mem can specify even addresses.  
Application example: Move the data of addresses 20H and 21H to register pair XA.  
MOV XA, 20H  
MOV mem, A  
Function: (mem) A; mem = D7 to D0 : 00H to 3FH  
Move the contents of the A register to the data memory addressed by 8-bit immediate data mem.  
MOV mem, XA  
Function: (mem) A, (mem + 1) X; mem = D7 to D0 : 00H to 3EH  
Moves the contents of the A register to the data memory addressed by 8-bit immediate data mem and the  
contents of the X register to the next memory address.  
mem can specify even addresses.  
160  
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CHAPTER 9. INSTRUCTION SET  
XCH A, @HL  
Function: A (HL)  
Exchanges the contents of the A register and the contents of the data memory addressed by the contents  
of register pair HL.  
Application example: Exchange the data of data memory addresses 20H to 2FH and the data of addresses 30H  
to 3FH.  
MOV HL, #30H  
LOOP: XCH A, @HL  
MOV H, #2  
; A (3×)  
XCH A, @HL  
MOV H, #3  
; A (2×)  
XCH A, @HL  
INCS L  
; A (3×)  
; L L + 1  
BR  
LOOP  
XCH A, mem  
Function: A (mem); mem = D7 to D0 ; 00H to 3FH  
Exchanges the contents of the A register and the data memory contents addressed by 8-bit immediate data  
mem.  
XCH XA, mem  
Function: A (mem), X (mem + 1); mem = D7 to D0 : 00H to 3EH  
Exchanges the contents of the A register and the data memory contents addressed by 8-bit immediate data  
mem and exchanges the contents of the X register and the contents of the next memory address.  
mem can specify even addresses.  
XCH A, reg1  
Function: A reg1  
Exchanges the contents of the A register and the contents of register reg1 (X, H, L).  
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CHAPTER 9. INSTRUCTION SET  
9.4.2 Table Reference Instructions  
MOVT XA, @PCXA  
Function: XA ROM (PC10 to PC8 + XA)  
Moves the high-order three bits (PC10 to PC8 ) of the program counter (PC) and the low-order four bits of  
the table data in the program memory addressed by the contents of register pair XA to the A register and the  
high-order four bits to the X register.  
The high-order three bits of the table address are determined by the contents of the grogram counter (PC)  
when this instruction is executed.  
The necessary data must be preprogrammed at the table area by assembler pseudo instruction (DB  
instruction).  
The program counter is not affected by execution of this instruction.  
This instruction is effective when referencing table data consecutively.  
Program Memory  
12  
8
7
4 3  
0
7
4
3
0
Table  
Table  
Data H  
Table  
Data L  
A 3–0  
PC 12–8  
X 3–0  
Address  
3
0
3
0
X
X
Note The MOVT XA, @PCXA instruction usually references the table data of the page containing the instruction.  
However, when the instruction is at address ×FFH, the table data of the next page is referenced instead of  
the table data on that page.  
Program Memory  
7
0
Page2  
02FFH  
0300H  
Page3  
For instance, when there is a MOVT XA, @PCXA instruction at position in the figure above, the table data  
specified by the contents of register pair XA of page 3 instead of page 2 is moved to register pair XA.  
162  
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CHAPTER 9. INSTRUCTION SET  
9.4.3 Arithmetic and Logic Instructions  
ADDS A, #n4  
Function: A A + n4; Skip if carry; n4 = I3 to I0 : 0 to FH  
Binary adds 4-bit immediate data n4 to the contents of the A register and skips the next instruction if a carry  
is generated. The carry flag is not affected.  
When combined with an ADDC A, @HL instruction, this instruction becomes a base correction instruction.  
(See section 9.1.)  
ADDS A, @HL  
Function: A A + (HL); Skip if carry  
Binary adds the data memory contents addressed by register pair HL to the contents of the A register and  
skips the next instruction if a carry is generated. The carry flag is not affected.  
ADDC A, @HL  
Function: A, CY A + (HL) + CY  
Binary adds the data memory contents addressed by register pair HL to the contents of the A register,  
including the carry flag. If a carry is generated, the carry flag is set. If a carry is not generated, the carry flag  
is reset.  
When an ADDS A, #n4 instruction is placed after this instruction, when a carry is generated at this instruction,  
the ADDS A, #n4 instruction is skipped. When a carry is not generated, the ADDS A, #n4 instruction is executed  
and the skip function of the ADDS A, #n4 instruction is disabled. Therefore, the combination of these  
instructions can be used in base correction (see section 9.1).  
AND A, @HL  
Function: A A (HL)  
ANDs the contents of the A register and the data memory contents addressed by register pair HL and sets  
the result into the A register.  
163  
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CHAPTER 9. INSTRUCTION SET  
OR A, @HL  
Function: A A (HL)  
ORs the contents of the A register and the data memory contents addressed by register pair HL and sets  
the result into the A register.  
XOR A, @HL  
Function: A A (HL)  
Exclusive-ORs the contents of the A register and the data memory contents addressed by register pair HL  
and sets the result into the A register.  
164  
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CHAPTER 9. INSTRUCTION SET  
9.4.4 Accumulator Operation Instructions  
RORC A  
Function: CY A0 An to A1 An , A3 CY (n = 1 to 3)  
Rotates the contents of the A register (4-bit accumulator), including the carry flag, to the right one bit at a  
time.  
A
CY  
0
3
0
2
1
1
0
0
1
Before  
Execution  
RORC A  
After  
Execution  
1
0
0
1
0
NOT A  
Function: A A  
Takes the one’s complement (inverts each bit) of the A register (4-bit accumulator).  
165  
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CHAPTER 9. INSTRUCTION SET  
9.4.5 Increment/Decrement Instructions  
INCS reg  
Function: reg reg + 1; Skip if reg = 0  
Increments the contents of register reg (X, A, H, L). When the contents of register reg become 0 as the result  
of incrementing, skips the next instruction.  
INCS mem  
Functions: (mem) (mem) + 1; Skip if (mem) = 0, mem = D7 to D0 : 00H to FFH  
Increments the data memory contents addressed by 8-bit immediate data mem. When the data memory  
contents become 0 as a result of incrementing, skips the next instruction.  
DECS reg  
Function: reg reg - 1; Skip if reg = FH  
Decrements the contents of register reg (X, A, H, L). When the contents of register reg become FH as a result  
of decrementing, skips the next instruction.  
166  
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CHAPTER 9. INSTRUCTION SET  
9.4.6 Compare Instructions  
SKE reg, #n4  
Function: Skip if reg = n4; n4 = I3 to I0 : 0 to FH  
If the contents of register reg (X, A, H, L) equal 4-bit immediate data n4, skips the next instruction.  
SKE A, @HL  
Function: Skip if A = (HL)  
If the contents of the A register and the data memory contents addressed by register pair HL, skips the next  
instruction.  
167  
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CHAPTER 9. INSTRUCTION SET  
9.4.7 Carry Flag Operation Instructions  
SET1 CY  
Function: CY 1  
Sets the carry flag.  
CLR1 CY  
Function: CY 0  
Clears the carry flag.  
SKT CY  
Function: Skip if CY = 1  
When the carry flag is 1, skips the next instruction.  
NOT1 CY  
Function: CY CY  
Inverts the carry flag. If the carry flag is 0, it becomes 1 and if it is 1, it becomes 0.  
168  
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CHAPTER 9. INSTRUCTION SET  
9.4.8 Bit Manipuration Instructions  
SET1 mem. bit  
Function: (mem. bit) 1; mem = D7 to D0 : 00H to 3FH, bit = B1 to B0 : 0 to 3  
Sets the bit specified by 2-bit immediate data bit of the address specified by 8-bit immediate data mem.  
SET1 fmem. bit  
Function: (bit specified by operand) 1  
Sets the data memory bit specified by bit manipulation addressing (fmem. bit).  
CLR1 mem. bit  
Function: (mem. bit) 0; mem = D7 to D0 : 00H to 3FH, bit = B1 to B0 : 0 to 3  
Clears the bit specified by 2-bit immediate data bit of the address specified by 8-bit immediate data mem.  
CLR1 fmem. bit  
Function: (bit specified by operand) 0  
Clears the data memory bit specified by bit manipulation addressing (fmem. bit).  
SKT mem. bit  
Function: Skip if (mem. bit) = 1; mem = D7 to D0 : 00H to 3FH, bit = B1 to B0 : 0 to 3  
If 2-bit immediate data bit of the address specified by 8-bit immediate data mem is 1, skips the next  
instruction.  
SKT fmem. bit  
Function: Skip if (bit specified by operand) = 1  
If the data memory bit specified by bit manipulation addressing (fmem. bit) is 1, skips the next instruction.  
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CHAPTER 9. INSTRUCTION SET  
SKF mem. bit  
Function: Skit if (mem. bit) = 0; mem = D7 to D0 : 00H to 3FH, bit = B1 to B0 : 0 to 3  
If the bit specified by 2-bit immediate data bit of the address specified by 8-bit immediate data mem is 0,  
skips the next instruction.  
SKF fmem. bit  
Function: Skip if (bit specified by operand) = 0  
If the contents of the data memory bit specified by bit manipulation addressing (fmem. bit) is 0, skips the  
next instruction.  
SKTCLR fmem. bit  
Function: Skip if (bit specified by operand) = 1 then clear  
If the data memory bit specified by bit manipulation addressing (fmem. bit) is 1, skips the next instruction  
and clears that bit to 0.  
AND1 CY, fmem. bit  
Function: CY CY (bit specified by operand)  
ADDs the contents of the carry flag and the contents of the data memory bit specified by bit manipulation  
addressing (fmem. bit) and sets the result into the carry flag.  
OR1 CY, fmem. bit  
Function: CY CY (bit specified by operand)  
ORs the contents of the carry flag and the contents of the data memory bit specified by bit manipulation  
addressing (fmem. bit) and sets the result into the carry flag.  
XOR1 CY, fmem. bit  
Function: CY CY (bit specified by operand)  
Exclusive-ORs the contents of the carry flag and the contents of the data memory bit specified by bit  
manipulation addressing (fmem. bit) and sets the result into the carry flag.  
170  
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CHAPTER 9. INSTRUCTION SET  
9.4.9 Branch Instructions  
BR addr  
Function: PC10 to PC0 addr; addr = 000H to 77FH  
Branches to the address addressed by 11-bit immediate data addr.  
This instruction is an assembler pseudo instruction. During assembly, the assembler automatically replaces  
this instruction with the optimum instruction from among the BRCB !caddr and BR $addr instructions.  
BR $addr  
Function: PC addr; addr = (PC-15) to (PC-1), (PC+2) to (PC+16)  
This is a relative branch instruction with a branch range of (-15 to -1) and (+2 to +16) from the current address.  
Page boundary and block boundary are not affected.  
BRCB !caddr  
Function: PC10 to PC0 caddr; caddr = A10 to A0 : 000H to 77FH  
Branches to the address addressed by 11-bit immediate data caddr (A10 to A0 ).  
171  
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CHAPTER 9. INSTRUCTION SET  
9.4.10 Subroutine Stack Control Instructions  
CALLF !faddr  
Function: (SP-1) PC7 to PC4 , (SP-2) PC3 to PC0 ,  
(SP-3) 0, 0, 0, 0  
(SP-4) 0, PC10 to PC8 ,  
SP SP-4, PC A10 to A0  
faddr = A10 to A0 : 000H to 77FH  
Saves the contents of the program counter (PC; return address) to the data memory (stack) addressed by  
the stack pointer (SP) and decrements the SP, then branches to the address addressed by 11-bit immediate  
data faddr.  
The range that can be called is limited to addresses 000H to 77FH (0 to 1919).  
RET  
Function: PC10 to PC8 (SP), PC3 to PC0 (SP+2),  
PC7 to PC4 (SP+3), SP SP+4  
Restores the contents of the data memory (stack) addressed by the stack pointer (SP) to the program counter  
(PC), then increments the contents of the SP.  
RETS  
Function: PC10 to PC8 (SP), PC3 to PC0 (SP+2)  
PC7 to PC4 (SP+3), SP SP+4, Then skip unconditionally  
Restores the contents of the data memory (stack) addressed by the stack pointer (SP) to the program counter  
(PC) and increments the contents of the SP, then skips unconditionally.  
RETI  
Function: PC10 to PC8 (SP), PC3 to PC0 (SP+2),  
PC7 to PC4 (SP+3), PSWL (SP+4), PSWH (SP+5), SP SP+6  
Restores the contents of the data memory (stack) addressed by the stack pointer (SP) to the program counter  
(PC) and program status word (PSW), then increments the SP.  
This instruction is used to return from an interrupt handling routine.  
172  
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CHAPTER 9. INSTRUCTION SET  
PUSH rp  
Function: (SP-1) rpH, (SP-2) rpL, SP SP-2  
Saves the contents of register pair rp (XA, HL) to the data memory (stack) addressed by the stack pointer  
(SP), then decrements the SP.  
The high-order side (rpH: X, H) of the register pair is saved to the stack addressed by (SP-1) and the low-  
order side (rpL: A, L) is saved to the stack addressed by (SP-2).  
POP rp  
Function: rpL (SP), rpH (SP+1), SP SP+2  
Restores the contents of the data memory (stack) addressed by the stack pointer (SP) to register pair rp (XA,  
HL), then increments the SP.  
The contents of (SP) are restored to the low-order side (rpL: A, L) of the register pair and the contents of (SP+1)  
are restored to the high-order side (rpH: X, H).  
173  
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CHAPTER 9. INSTRUCTION SET  
9.4.11 Interrupt Control Instructions  
EI  
Function: IME 1  
Sets the interrupt master enable flag (1), and enables interrupts. Whether or not interrupts are accepted is  
determined by each interrupt enable flag.  
EI IEXXX  
Function: IE××× ← 1; ××× = N2 to N0  
Sets the interrupt enable flag (IE×××) (1), and enables the interrupt. (××× = BT, CSI, 0, 2)  
DI  
Function: IME 0  
Resets the interrupt master enable flag and disables interrupts regardless of the contents of each interrupt  
enable flag.  
DI IEXXX  
Function: IE××× ← 0; ××× = N2 to N0  
Resets the interrupt enable flag (IE×××) (0), and disables the interrupt. (××× = BT, CSI, 0, 2)  
174  
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CHAPTER 9. INSTRUCTION SET  
9.4.12 Input/Output Instructions  
IN A, PORTn  
Function: A PORTn; n = N3 to N0 : 0 to 3, 5, 6  
Transfers the contents of the port specified by PORTn (n = 0 to 3, 5, 6) to the A register.  
Note Only 0 to 3, 5 or 6 can be specified at n.  
Output latch data (output mode) or pin data (input mode) is fetched according to input/output mode  
specification.  
OUT PORTn, A  
Function: PORTn A; n = N3 to N0 : 2, 3, 5, 6  
Transfers the contents of the A register to the output latch of the port specified by PORTn (n = 2, 3, 5, 6)  
Note Only 2, 3, 5, or 6 can be specified at n.  
175  
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CHAPTER 9. INSTRUCTION SET  
9.4.13 CPU Control Instructions  
HALT  
Function: PCC. 2 1  
Sets the HALT mode (This instruction sets bit 2 of the processor clock control register.).  
Note The instruction following the HALT instruction is made an NOP instruction.  
STOP  
Function: PCC. 3 1  
Sets the STOP mode (This instruction sets bit 3 of the processor clock control register).  
Note The instruction following the STOP instruction is made an NOP instruction.  
NOP  
Function: Expend one machine cycle without performing any operation.  
176  
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APPENDIX A. TABLE OF INSTRUCTION USABLE WITH EVAKIT-75X ONLY  
Since EVAKIT-75X (75X series common evaluation board) supports the 75X series functions, it can execute the  
following instructions not available with theµPD75402A. Since the µPD75402A and µPD75P402 cannot execute these  
instructions even though they can be executed on the EVAKIT, do not use them.  
Mnemonic  
MOV  
Operands  
Mnemonic  
ADDC  
Operands  
A, reg  
rp’1, XA  
XA, rp’  
A, reg  
reg, A  
XA, @HL  
@HL, XA  
A, @HL  
rp’1, XA  
XA, rp’  
A, reg  
reg, A  
XA, @HL  
@HL, XA  
A,#n4  
A, @rpa  
reg1, A  
reg1, #n4  
rp’1, XA  
XA, rp’  
XA, @HL  
@HL, XA  
A, @rpa  
HL, mem  
XA, @HL  
XA, rp’  
SUBS, SUBC  
XCH  
MOVT  
MOV1  
XA, @PCDE  
XA, @BCDE  
XA, @BCXA  
AND, OR, XOR  
rp’1, XA  
XA, rp’  
mem, A  
A, reg  
reg, A  
XA, @HL  
@HL, XA  
rp  
CY, fmem. bit  
CY, pmem. @L  
CY, @H + mem. bit  
fmem. bit, CY  
pmem. @L, CY  
@H + mem. bit, CY  
rp’1, XA  
ADDS  
ROLC  
XA, rp’  
A
XA, #n8  
RORC  
INCS  
rp  
A, reg  
rp1  
reg, A  
@HL  
XA, @HL  
XA  
@HL, XA  
DECS  
rp’  
177  
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APPENDIX A. TABLE OF INSTRUCTION USABLE WITH EVAKIT-75X ONLY  
Mnemonic  
NOT1  
Operands  
Mnemonic  
DECS  
Operands  
fmem. bit  
mem  
pmem. @L  
@HL  
@H + mem. bit  
!addr  
SKE  
A, reg  
BR  
XA, rp’  
XA, @HL  
@HL, #n4  
A, mem  
pmem. @L  
PCDE  
PCXA  
BCDE  
BCXA  
SET1, CLR1,  
SKF, SKT,  
SKTCLR  
CALL  
PUSH  
POP  
IN  
!addr  
@H + mem. bit  
CY, pmem. @L  
CY, @H + mem. bit  
CY,/fmem. bit  
BS  
AND1, OR1  
BS  
XA, PORTn  
PORTn, XA  
MBn  
OUT  
SEL  
CY,/pmem. @L  
CY,/@H + mem. bit  
CY, pmem. @L  
CY, @H + mem. bit  
RBn  
XOR1  
GETI  
taddr  
reg : X, A, B, C, D, E, H, L  
rp  
:
:
XA, BC, DE, HL  
rp’  
XA, BC, DE, HL, XA’, BC’, DE’, HL’  
rpa : HL+, HL-, DE, DL  
178  
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APPENDIX B. DEVELOPMENT TOOLS  
The following development tools are available for system development using the µPD75402A:  
Language Processor  
RA75X relocatable assembler  
Ordering Code  
(Product Name)  
Host Machine  
PC-9800 series  
OS  
Supply Medium  
3.5-inch 2HD  
MS-DOSTM  
µS5A13RA75X  
µS5A10RA75X  
µS7B10RA75X  
Ver. 3.30  
Ver. 5.00 A*  
5-inch 2HD  
5-inch 2HC  
PC DOSTM  
(Ver. 3.1)  
IBM PC/ATTM  
PROM Writing Tools  
PG-1500  
This PROM programmer allows programming, in standalone a mode or via operation  
from a host computer, of a singlechip microcomputer with on-chip PROM by  
connection of the d board provided and a separately available programmer adapter.  
It can program typical 256K-bit to 4M-bit PROMs.  
PA-75P402CT  
PA-75P402GB  
PROM programmer adapter for µPD75P402C/CT/GB, used connected to the PG-1500.  
...  
PA-75P402CT  
PA-75P402GB  
For µPD75P402C/CT  
...  
For µPD75P402GB  
PG-1500 controller  
Connects PG-1500 and host machine via a serial and parallel interface, and controls  
the PG-1500 on the host f machine.  
Ordering Code  
Host Machine  
(Product Name)  
Supply Medium  
OS  
PC-9800 series  
IBM PC/AT  
MS-DOS  
3.5-inch 2HD  
µS5A13PG1500  
µS5A10PG1500  
µS7B10PG1500  
Ver. 3.30  
Ver. 5.00 A*  
5-inch 2HD  
5-inch 2HC  
PC DOS  
(Ver. 3.1)  
*
The task swap function, which is provided with Ver.5.00/5.00A, is not available with this software.  
Remarks Operation of the relocatable assembler and PG-1500 controller is guaranteed only on the host machines  
and operating systems quoted above.  
179  
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APPENDIX B. DEVELOPMENT TOOLS  
Debugging Tools  
The following in-circuit emulators (IE-75000-R and IE-75001-R) are available as the µPD75402A program  
debugging tools.  
Their respective system configurations are as follows.  
IE-75000-R*1  
The IE-75000-R is an in-circuit emulator for hardware/software debugging in develop-  
ment of an application system using the 75X series.  
Used in combination with an emulation probe.  
Connected with a host machine and PROM programmer, the IE- 75000-R can perform  
efficient debugging.  
IE-75000-R-EM  
Emulation board for evaluation of an application system using the 75X series.  
Used in combination with the IE-75000-R or IE-75001-R.  
Incorporated in the IE-75000-R.  
IE-75001-R*2  
The IE-75001-R is an in-circuit emulator for hardware/software debugging in develop-  
ment of an application system using the 75X series.  
Used in combination with the separately available IE-75000-R- EM emulation board  
and emulation probe.  
Connected with a host machine and PROM programmer, the IE- 75001-R can perform  
efficient debugging.  
EP-75402C-R  
µPD75402AC/75402ACT emulation probe.  
Used connected with the IE-75000-R, IE-75001-R or IE-75000-R- EM.  
EP-75402GB-R  
µPD75402AGB emulation probe.  
Used connected with the IE-75000-R, IE-75001-R or IE-75000-R- EM  
Provided with the EV-9200G-44, 44-pin conversion socket which facilitates connection  
with the target system.  
EV-9200G-44  
IE control program  
Connects the IE-75000-R or IE-75001-R with a host machine via RS-232-C or  
Centronics I/F and controls the IE-75000-R or IE-75001-R on the host machine.  
Ordering Code  
Host Machine  
(Product Name)  
Supply Medium  
OS  
PC-9800 series  
IBM PC/AT  
MS-DOS  
3.5-inch 2HD  
µS5A13IE75X  
µS5A10IE75X  
µS7B10IE75X  
Ver. 3.30  
Ver. 5.50 A*3  
5-inch 2HD  
5-inch 2HC  
PC DOS  
(Ver. 3.1)  
*
1. Maintenance product  
2. IE-75000-R-EM is sold separately.  
3. The task swap function, which is provided with Ver.5.00/5.00A, is not available with this software.  
Remarks Operation of the IE control program is guaranteed only on the above quoted host machines and  
operating systems.  
180  
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Development Tool Configuration  
In-Circuit Emulator  
Emulation Probe  
IE-75000-R  
IE-75001-R  
EP-75402C-R  
EP-75402GB-R  
Centronics I/F  
*1  
IE-75000-R-EM  
IE  
Control  
Program  
RS-232-C  
Host Machine  
PC-9800 Series  
IBM PC/AT  
(Symbolic  
Debugging  
Capability)  
Target System  
*2  
PG-1500  
Controller  
On-chip PROM  
Products  
PROM Programmer  
PG-1500  
µ
PD75P402C/CT/GB  
Relocatable  
Assembler  
Programmer Adapter  
*
1. The IE-75001-R does not incorporate  
the IE-75000-R-EM (Sold separately)  
2. EV-9200G-44  
PA-75P402CT  
PA-75P402GB  
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APPENDIX C. MASK ROM ORDERING PROCEDURE  
When completing the µPD75402A program and ordering the mask ROM, proceed as follows:  
Mask ROM order reservation  
Provide us with the mask ROM ordering schedule through your dealer or our sales department (If we are  
not informed in advance, processing may be delayed.).  
Preparation of ordering medium  
The medium for mask ROM order is UV-EPROM or 8-inch IBM format floppy disk. When ordered with UV-  
EPROM, please prepare three UV-EPROMs with the same contents. (Send the mask options data filled in the  
mask option information documents.)  
Preparation of the necessary documents  
When ordering the mask ROM, please fill in the following documents:  
Mask type ROM order form  
Mask type ROM order check sheet  
Mask option information documents  
Send the medium prepared in and the documents described in to us through your special agents or  
our sales department by the scheduled order date.  
4
Note For details, refer to the infamation document “ROM Code Ordering Method” “Documents No. IEM-834”.  
182  
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APPENDIX D. INSTRUCTION INDEX (ALPHABETIC ORDER)  
Instruction  
Page  
176  
165  
168  
164  
170  
175  
173  
173  
172  
172  
172  
165  
168  
169  
169  
167  
167  
170  
170  
168  
169  
169  
170  
176  
161  
161  
161  
161  
164  
170  
Instruction  
A, @HL  
A, #n4  
Page  
163  
163  
163  
163  
170  
171  
171  
171  
172  
168  
169  
169  
166  
174  
174  
174  
174  
176  
175  
166  
166  
160  
159  
159  
160  
160  
159  
160  
160  
162  
ADDC  
ADDS  
ADDS  
AND  
AND1  
BR  
NOP  
NOT  
NOT1  
OR  
A
A, @HL  
A, @HL  
CY, fmem. bit  
addr  
CY  
A, @HL  
CY, fmem. bit  
PORTn, A  
rp  
OR1  
OUT  
POP  
BR  
$addr  
BRCB  
CALLF  
CLR1  
CLR1  
CLR1  
DECS  
DI  
! caddr  
! faddr  
CY  
PUSH  
RET  
rp  
RETI  
RETS  
RORC  
SET1  
SET1  
SET1  
SKE  
fmem. bit  
mem. bit  
reg  
A
CY  
fmem. bit  
mem. bit  
A, @H  
DI  
IE×××  
EI  
EI  
IE×××  
SKE  
reg, #n4  
fmem. bit  
mem. bit  
CY  
HALT  
IN  
SKF  
A, PORTn  
mem  
SKF  
INCS  
INCS  
MOV  
MOV  
MOV  
MOV  
MOV  
MOV  
MOV  
MOV  
MOVT  
SKT  
reg  
SKT  
fmem. bit  
mem. bit  
fmem. bit  
A, mem  
A, #n4  
SKT  
SKTCLR  
STOP  
XCH  
XCH  
XCH  
XCH  
XOR  
XOR1  
A, @HL  
mem, A  
mem, XA  
rp, #n8  
A, @HL  
A, mem  
A, reg1  
XA, mem  
@HL, A  
XA, @PCXA  
XA, mem  
A, @HL  
CY, fmem. bit  
183  
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APPENDIX E. HARDWARE INDEX (ALPHABETIC ORDER)  
Hardware  
Name  
Hardware  
Name  
Page  
Page  
Symbol  
Symbol  
ACKD Acknowledge detect flag  
ACKE Acknowledge enable flag  
ACKT Acknowledge trigger bit  
80, 104, IRQ2  
109  
80, 104, IRQBT  
108  
INT2 interrupt request flag  
BT interrupt request flag  
129  
129  
129  
133  
31  
79, 104,  
107  
IRQCS Serial interface interrupt request flag  
80, 105,  
109  
BSYE  
BT  
Sync busy enable bit  
IST0  
PC  
Interrupt status flag  
66  
67  
64  
Basic interval timer  
Program counter  
55  
BTM  
Basic interval timer mode register  
PCC  
Processor clock control mode register  
47  
CLOM Clock output mode register  
CMDD Command detect flag  
CMDT Command trigger bit  
PMGA, Port mode register (A, B)  
PMGB  
79,104,  
106  
51  
42  
POGA Pull-up resistor specification register  
79, 87,  
103,106  
PORT 0 Port 0 to 3, 5, 6  
to 3,  
5, 6  
76, 86,  
102  
COI  
Address comparator coincidence signal  
76, 83,  
86,102  
CSIE  
Serial interface operation enable/disable  
specification bit  
39  
PSW  
Program status word  
Bus release detect flag  
79, 104,  
106  
79, 87,  
103,106  
78, 87,  
103,106  
to 109  
73, 81,  
113  
RELD  
73, 74,  
85, 101  
39  
CSIM  
CY  
Serial operating mode register  
Carry flag  
RELT  
SBIC  
Bus release trigger bit  
Serial bus interface control register  
129  
129  
129  
129  
131  
132  
129  
IE0  
INT0 interrupt enable flag  
INT2 interrupt enable flag  
BT interrupt enable flag  
Serial interface interrupt enable flag  
INT0 mode register  
IE2  
SIO  
Serial I/O shift register  
IEBT  
IECSI  
IM0  
IME  
IRQ0  
40  
SK0 to Skip flag  
SK2  
37  
SP  
Stack pointer  
73, 82,  
113  
76, 85,  
102  
SVA  
WUP  
Slave address register  
Interrupt master enable flag  
INT0 interrupt request flag  
Wake-up function specification bit  
184  
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