82540EP Gigabit Ethernet Controller
Networking Silicon
Datasheet
Revision 1.2
April 2003
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Networking Silicon — 82540EP
Revision History
Date
Revision
Notes
Apr 2002
Nov 2002
Jan 2003
0.25
1.0
Initial Release
Changed document status to Intel Confidential.
1.1
Section 1.0. Replaced Block Diagram
Section 2.6. Added Table footnote
Section 4.1, 4.2, 4.3. Replaced tables
Section 5.1. Added Visual Pin Reference
Section 4.4 Removed Power Supply Characteristics; added note to I/O Charac-
teristics
Section 5.0 Replaced Pinout Diagram
Apr 2003
1.2
Removed confidential status.
Section 1.0. Added product ordering code.
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Networking Silicon — 82540EP
Contents
Introduction.........................................................................................................................1
Document Scope...................................................................................................3
Reference Documents...........................................................................................3
Product Code ........................................................................................................3
Features of the 82540EP Gigabit Ethernet Controller........................................................5
PCI Features .........................................................................................................5
MAC Specific Features..........................................................................................5
PHY Specific Features ..........................................................................................6
Host Offloading Features ......................................................................................6
Manageability Features.........................................................................................7
Additional Device Features ...................................................................................8
Technology Features.............................................................................................8
Signal Descriptions.............................................................................................................9
Signal Type Definitions..........................................................................................9
PCI Bus Interface ..................................................................................................9
3.2.2 Arbitration Signals ..................................................................................11
3.2.3 Interrupt Signal.......................................................................................11
3.2.4 System Signals.......................................................................................11
3.2.5 Error Reporting Signals..........................................................................11
3.2.8 SMB Signals...........................................................................................12
Miscellaneous Signals.........................................................................................13
3.4.1 LED Signals............................................................................................13
3.4.2 Other Signals..........................................................................................13
3.5.1 Crystal Signals .......................................................................................14
3.5.2 Analog Signals .......................................................................................14
Power Supply Connections .................................................................................15
3.7.1 Digital Supplies.......................................................................................15
3.7.2 Analog Supplies .....................................................................................15
3.7.3 Ground and No Connects.......................................................................16
3.7.4 Control Signals.......................................................................................16
Voltage, Temperature, and Timing Specifications............................................................17
Absolute Maximum Ratings.................................................................................17
Recommended Operating Conditions .................................................................17
DC Specifications................................................................................................18
AC Characteristics...............................................................................................21
4.5.1 PCI Bus Interface ...................................................................................22
4.5.2 Link Interface Timing ..............................................................................26
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82540EP — Networking Silicon
4.5.3 EEPROM Interface.................................................................................26
Package and Pinout Information......................................................................................27
Device Identification ...........................................................................................27
Package Information ...........................................................................................28
Thermal Specifications........................................................................................29
Pinout Information ...............................................................................................30
Visual Pin Reference...........................................................................................39
vi
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Networking Silicon — 82540EP
1.0
Introduction
The Intel® 82540EP Gigabit Ethernet Controller is a single, compact component with an integrated
Gigabit Ethernet Media Access Control (MAC) and physical layer (PHY) functions. For desktop,
workstation and mobile PC Network designs with critical space constraints, the Intel® 82540EP
allows for a Gigabit Ethernet implementation in a very small area that is footprint compatible with
current generation 10/100 Mbps Fast Ethernet designs
The Intel® 82540EP integrates Intel’s fourth generation gigabit MAC design with fully integrated,
physical layer circuitry to provide a standard IEEE 802.3 Ethernet interface for 1000BASE-T,
100BASE-TX, and 10BASE-T applications (802.3, 802.3u, and 802.3ab). The controller is capable
of transmitting and receiving data at rates of 1000 Mbps, 100 Mbps, or 10 Mbps. In addition to
managing MAC and PHY layer functions, the controller provides a 32-bit wide direct Peripheral
Component Interconnect (PCI) 2.2 compliant interface capable of operating at 33 or 66 MHz.
The 82540EP also incorporates the CLKRUN protocol and hardware supported downshift
capability to two or three-pair 100 Mb/s operation. These features optimize mobile applications.
The Intel® 82540EP’s on-board System Management Bus (SMB) port enables network
manageability implementations required by information technology personnel for remote control
and alerting via the LAN. With SMB, management packets can be routed to or from a management
processor. The SMB port enables industry standards, such as Intelligent Platform Management
Interface (IPMI) and Alert Standard Forum (ASF), to be implemented using the 82540EP. In
addition, on chip ASF 1.0 circuitry provides alerting and remote control capabilities with
standardized interfaces.
The 82540EP Gigabit Ethernet Controller architecture is designed to deliver high performance and
PCI bus efficiency. Wide internal data paths eliminate performance bottlenecks by efficiently
handling large address and data words. The 82540EP controller includes advanced interrupt
handling features to limit PCI bus traffic and a PCI interface that maximizes the use of bursts for
efficient bus usage. The 82540EP caches up to 64 packet descriptors in a single burst for efficient
PCI bandwidth use. A large 64 KByte on-chip packet buffer maintains superior performance as
available PCI bandwidth changes. In addition, using hardware acceleration, the controller offloads
tasks from the host controller, such as TCP/UDP/IP checksum calculations and TCP segmentation.
The 82540EP is packaged in a 15 mm2 196-ball grid array and is pin compatible with both the
82551QM 10/100 Mbps Fast Ethernet Multifunction PCI/CardBus Controller and the 82540EM
Gigabit Ethernet Controller (which does not have added power saving features like CLKRUN).
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82540EP — Networking Silicon
Data Alignment
Packet Buffer Interface
CSR Register
Access
TX Data
Figure 1. Gigabit Ethernet Controller Block Diagram
2
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Networking Silicon — 82540EP
1.1
1.2
Document Scope
This document contains datasheet specifications for the 82540EP Gigabit Ethernet Controller,
including signal descriptions, DC and AC parameters, packaging data, and pinout information.
Reference Documents
This application assumes that the designer is acquainted with high-speed design and board layout
techniques. The following documents provide additional information:
• 82544EI/82544GC Gigabit Ethernet Controller Software Developer's Manual, Revision 0.25,
Intel Corporation.
• PCI Local Bus Specification, Revision 2.3, PCI Special Interest Group.
• PCI Bus Power Management Interface Specification, Rev. 1.1, PCI Special Interest Group.
• IEEE Standard 802.3, 1996 Edition, Institute of Electrical and Electronics Engineers (IEEE).
• IEEE Standard 802.3u, 1995 Edition, Institute of Electrical and Electronics Engineers (IEEE).
• IEEE Standard 802.3x, 1997 Edition, Institute of Electrical and Electronics Engineers (IEEE).
• IEEE Standard 802.3z, 1998 Edition, Institute of Electrical and Electronics Engineers (IEEE).
• IEEE Standard 802.3ab, 1999 Edition, Institute of Electrical and Electronics Engineers
(IEEE).
• 82559 Fast Ethernet Controllers Timing Device Selection Guide, AP-419, Intel Corporation.
• PCI Mobile Design Guide, Rev. 1.1, PCI Special Interest Group
1.3
Product Code
The product ordering code for the 82540EP is: RC82540EP.
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Networking Silicon — 82540EP
2.0
Features of the 82540EP Gigabit Ethernet Controller
2.1
PCI Features
Features
Benefits
•
•
Application flexibility for LAN on Motherboard
(LOM) or embedded solutions
PCI Revision 2.3 support for 32-bit wide interface at
33 MHz and 66 MHz
64-bit addressing for systems with more than 4
Gigabytes of physical memory
•
•
•
Support for new PCI 2.3 interrupt status/control
Algorithms that optimally use advanced PCI, MWI,
MRM, and MRL commands
Efficient bus operations
Enables CardBus operation (when used with
external FLASH device and series termination on
PCI bus)
CardBus Information Services (CIS) Pointer
CLKRUN# Signal
•
PCI clock suspension for low power mobile design
2.2
MAC Specific Features
Features
Benefits
•
•
Network packets handled without waiting or buffer
overflow.
Low-latency transmit and receive queues
Control over the transmissions of pause frames
through software or hardware triggering
IEEE 802.3x compliant flow control support with
software controllable pause times and threshold
values
•
•
Frame loss reduced from receive overruns
Efficient use of PCI bandwidth
Caches up to 64 packet descriptors in a single burst
Programmable host memory receive buffers (256
Bytes to 16 KBytes) and cache line size (16 Bytes to
256 Bytes)
•
Efficient use of PCI bandwidth
•
•
Low latency data handling
Wide, optimized internal data path architecture
Superior DMA transfer rate performance
•
•
No external FIFO memory requirements
FIFO size adjustable to application
64 KByte configurable Transmit and Receive FIFO
buffers
Descriptor ring management hardware for transmit
and receive
•
•
Simple software programming model
Optimized descriptor fetching and write-back
mechanisms
Efficient system memory and use of PCI
bandwidth
Mechanism available for reducing interrupts
generated by transmit and receive operations
•
•
Maximizes system performance and throughput
Enables jumbo frames
Support for transmission and reception of packets up
to 16 KBytes
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82540EP — Networking Silicon
2.3
PHY Specific Features
Features
Benefits
Integrated PHY for 10/100/1000 Mbps full and half
duplex operation
•
•
•
Smaller footprint and lower power dissipation
compared to multi-chip MAC and PHY solutions
Automatic link configuration including speed,
duplex, and flow control
IEEE 802.3ab Auto-Negotiation support
Robust operation over the installed base of
Category-5 (CAT-5) twisted pair cabling
IEEE 802.3ab PHY compliance and compatibility
•
•
Robust performance in noisy environments
State-of-the-art DSP architecture implements digital
adaptive equalization, echo cancellation, and cross-
talk cancellation
Tolerance of common electrical signal
impairments
•
•
Easier network installation and maintenance
End-to-end wiring tolerance
PHY ability to automatically detect polarity and cable
lengths and MDI versus MDI-X cable at all speeds
Features
Benefits
Transmit and receive IP, TCP and UDP checksum off-
loading capabilities
•
Lower CPU utilization
•
•
Increased throughput and lower CPU utilization
Transmit TCP segmentation
Large send offload feature (in Microsoft*
Windows* XP) compatible
•
•
•
16 exact matched packets (unicast or multicast)
4096-bit hash filter for multicast frames
Advanced packet filtering
Promiscuous (unicast and multicast) transfer
mode support
•
•
•
Optical filtering of invalid frames
IEEE 802.1q VLAN support with VLAN tag insertion,
stripping and packet filtering for up to 4096 VLAN tags
Ability to create multiple virtual LAN segments
Optimized fetching and write-back mechanisms for
efficient system memory and PCI bandwidth
usage
Descriptor ring management hardware for transmit
and receive
•
•
High throughput for large data transfers on
networks supporting jumbo frames
16 KByte jumbo frame support
Increased throughput by reducing interrupts
generated by transmit and receive operations
Interrupt coalescing (multiple packets per interrupt)
6
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2.5
Manageability Features
Features
Benefits
Manageability features: SMB port, ASF 1.0, ACPI,
Wake on LAN, and PXE
•
Network management flexibility
•
•
Enables IPMI and ASF implementations
On-board SMB port
Allows packets routing to and from either LAN port
and a server management processor
Compliance with PCI Power Management 1.1 and
ACPI 2.0 register set compliant including:
•
•
D0 and D3 power states
•
PCI power management capability requirements
for PC and embedded applications
Network Device Class Power Management
Specification 1.1
•
PCI Specification 2.2
•
•
•
•
Easy system monitoring with industry standard
consoles
SNMP and RMON statistic counters
Remote network management capabilities through
DMI 2.0 and SNMP software
SDG 3.0, WfM 2.0, and PC2001 compliance
Packet recognition and wake-up for NIC and LOM
applications without software configuration
Wake on LAN support
Two or three-pair cable downshift
Assures link under adverse cable configurations
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82540EP — Networking Silicon
2.6
Additional Device Features
Features
Benefits
Four activity and link indication outputs that directly
drive LEDs
•
•
Link and activity indications (10, 100, and 1000
Mbps) on each port
Software definable function (speed, link, and
activity) and blinking allowing flexible LED
implementations
Programmable LED functionality
Internal PLL for clock generation can use a 25 MHz
crystal
•
Lower component count and system cost
Simplified testing using boundary scan
JTAG (IEEE 1149.1) Test Access Port built in silicon
•
•
Reduced number of on-board power supply
regulators
On-chip power control circuitrya
•
•
Simplified power supply design in less power-
critical applications
Additional flexibility for LEDs or other low speed
I/O devices
Four software definable pins
Supports little endian byte ordering for both 32 and 64
bit systems and big endian byte ordering for 64 bit
systems
•
Portable across application architectures
Two or three-pair cable downshift
Provides loopback capabilities
•
•
•
Supports modular hardware accessories
Validates silicon integrity
Minimal ballout change from the 82540EM
Pin Compatibility
a. If applying the “low-power” EEPROM setting for the 82540EP chip, then only external voltage regulator circuits should be used
instead of the on-chip power control circuitry
2.7
Technology Features
Features
Benefits
196-pin Ball Grid Array (TFBGA) package
•
•
15 mm2 component making LOM designs easier
Enables 10/100 Mbps Fast Ethernet or 1000 Mbps
Gigabit Ethernet implementations on the same
board with only minor stuffing option changes
Pin compatible with 82551QM and 82540EM
controllers
•
•
Offers lowest geometry to minimize power and
size while maintaining Intel quality reliability
standards
Implemented in 0.15u CMOS process
Operating temperature: 0° C to 70° C (maximum)
operating temperature
Simple thermal design
Heat sink or forced airflow not required
65° C to 140° C storage temperature range
PCI Signaling: 3.3 V (5 V tolerant) PCI signaling
Typical targeted power dissipation:
•
•
•
1.38W @ D0 1000 Mb/s
•
Lower power requirements for mobile applications
386mW @ D3 100 Mb/s (wake-up enabled)
<20mW @ D3 wake-up disabled
8
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Networking Silicon — 82540EP
3.0
Signal Descriptions
Note: The targeted signal names are subject to change without notice. Verify with your local Intel sales
office that you have the latest information before finalizing a design.
3.1
Signal Type Definitions
The signals of the 82540EP controller are electrically defined as follows:
Name
Definition
I
Input. Standard input only digital signal.
O
TS
Output. Standard output only digital signal.
Tri-state. Bi-directional three-state digital input/output signal.
Sustained Tri-state. Sustained digital three-state signal driven by one agent at a time.
An agent driving the STS pin low must actively drive it high for at least one clock before letting it
float. The next agent of the signal cannot drive the pin earlier than one clock after it has been
released by the previous agent.
STS
OD
Open Drain. Wired-OR with other agents.
The signaling agent asserts the OD signal, but the signal is returned to the inactive state by a
weak pull-up resistor. The pull-up resistor may require two or three clock periods to fully restore
the signal to the de-asserted state.
A
P
Analog. PHY analog data signal.
Power. Power connection, voltage reference, or other reference connection.
3.2
PCI Bus Interface
When the Reset signal (RST#) is asserted, the 82540EP will not drive any PCI output or bi-
directional pins except the Power Management Event signal (PME#).
3.2.1
PCI Address, Data and Control Signals
Symbol
Type
Name and Function
Address and Data.
The address phase is the clock cycle when the Frame signal (FRAME#) is asserted
low. During the address phase AD[31:0] contain a physical address (32 bits). For I/O,
this is a byte address, and for configuration and memory, a DWORD address. The
82540EP device uses little endian byte ordering.
AD[31:0]
TS
During data phases, AD[7:0] contain the least significant byte (LSB) and AD[31:24]
contain the most significant byte (MSB).
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Symbol
Type
Name and Function
Bus Command and Byte Enables. Bus command and byte enable signals are
multiplexed on the same PCI pins. During the address phase of a transaction,
CBE[3:0]# define the bus command. In the data phase, CBE[3:0]# are used as byte
enables. The byte enables are valid for the entire data phase and determine which byte
lanes contain meaningful data.
CBE[3:0]#
TS
CBE0# applies to byte 0 (LSB) and CBE3# applies to byte 3 (MSB).
Parity. The Parity signal is issued to implement even parity across AD[31:0] and
CBE[3:0]#. PAR is stable and valid one clock after the address phase. During data
phases, PAR is stable and valid one clock after either IRDY# is asserted on a write
transaction or TRDY# is asserted after a read transaction. Once PAR is valid, it remains
valid until one clock after the completion of the current data phase.
PAR
TS
When the 82540EP controller is a bus master, it drives PAR for address and write data
phases, and as a slave device, drives PAR for read data phases.
Cycle Frame.
82540EP device to indicate the
beginning and length of an access and indicate the beginning of a bus transaction.
While FRAME# is asserted, data transfers continue. FRAME# is de-asserted when the
transaction is in the final data phas
FRAME#
STS
Initiator Ready. Initiator Ready indicates the ability of the 82540EP controller (as bus
master device) to complete the current data phase of the transaction. IRDY# is used in
conjunction with the Target Ready signal (TRDY#). The data phase is completed on any
clock when both IRDY# and TRDY# are asserted.
IRDY#
STS
STS
During the write cycle, IRDY# indicates that valid data is present on AD[31:0]. For a
read cycle, it indicates the master is ready to accept data. Wait cycles are inserted until
both IRDY# and TRDY# are asserted together. The 82540EP controller drives IRDY#
when acting as a master and samples it when acting as a slave.
Target Ready. The Target Ready signal indicates the ability of the 82540EP controller
(as a selected device) to complete the current data phase of the transaction. TRDY# is
used in conjunction with the Initiator Ready signal (IRDY#). A data phase is completed
on any clock when both TRDY# and IRDY# are sampled asserted.
TRDY#
During a read cycle, TRDY# indicates that valid data is present on AD[31:0]. For a write
cycle, it indicates the target is ready to accept data. Wait cycles are inserted until both
IRDY# and TRDY# are asserted together. The 82540EP device drives TRDY# when
acting as a slave and samples it when acting as a master.
Stop. The Stop signal indicates the current target is requesting the master to stop the
current transaction. As a slave, the 82540EP controller drives STOP# to request the
bus master to stop the transaction. As a master, the 82540EP controller receives
STOP# from the slave to stop the current transaction.
STOP#
STS
I
Initialization Device Select. The Initialization Device Select signal is used by the
82540EP as a chip select signal during configuration read and write transactions.
IDSEL#
DEVSEL#
Device Select. When the Device Select signal is actively driven by the 82540EP, it
signals notifies the bus master that it has decoded its address as the target of the
current access. As an input, DEVSEL# indicates whether any device on the bus has
been selected.
STS
VIO. The VIO signal is a voltage reference for the PCI interface (3.3 V or 5 V PCI
signaling environment). It is used as the clamping voltage.
VIO
P
Note: An external resistor is required between the voltage reference and the VIO pin.
The target resistor value is 100 KΩ
10
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3.2.2
Arbitration Signals
Symbol
REQ#
Type
Name and Function
Request Bus. The Request Bus signal is used to request control of the bus from the
arbiter. This signal is point-to-point.
TS
Grant Bus. The Grant Bus signal notifies the 82540EP that bus access has been
granted. This is a point-to-point signal.
GNT#
I
I
Lock Bus. The Lock Bus signal is asserted by an initiator to require sole access to a
target memory device during two or more separate transfers. The 82540EP device
does not implement bus locking.
LOCK#
3.2.3
3.2.4
Interrupt Signal
Symbol
INTA#
Type
Name and Function
Interrupt A. Interrupt A is used to request an interrupt by port 1 of the 82540EP. It is an
active low, level-triggered interrupt signal.
TS
System Signals
Symbol
Type
Name and Function
PCI Clock.
82540EP
CLK
I
M66EN
RST#
I
I
66 MHz Enable. M66EN indicates whether the system bus is enabled for 66MHz.
PCI Reset. When the PCI Reset signal is asserted, all PCI output signals, except the
Power Management Event signal (PME#), are floated and all input signals are ignored.
The PME# context is preserved, depending on power management settings.
Most of the internal state of the 82540EP is reset on the de-assertion (rising edge) of
RST#.
Clock Run. This signal is used by the system to pause the PCI clock signal. It is used
by the 82540EP controller to request the PCI clock. When the CLKRUN# feature is
disabled, leave this pin unconnected.
I/O
OD
CLKRUN#
3.2.5
Error Reporting Signals
Symbol
Type
Name and Function
System Error. The System Error signal is used by the 82540EP controller to report
address parity errors. SERR# is open drain and is actively driven for a single PCI clock
when reporting the error.
SERR#
OD
Parity Error. The Parity Error signal is used by the 82540EP controller to report data
parity errors during all PCI transactions except by a Special Cycle. PERR# is sustained
tri-state and must be driven active by the 82540EP controller two data clocks after a
data parity error is detected. The minimum duration of PERR# is one clock for each
data phase a data parity error is present.
PERR#
STS
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3.2.6
Power Management Signals
Symbol
LAN_
PWR_
GOOD
Type
Name and Function
Power Good (Power-on Reset). The Power Good signal is used to indicate that stable
power is available for the 82540EP. When the signal is low, the 82540EP holds itself in
reset state and floats all PCI signals.
I
Power Management Event. The 82540EP device drives this signal low when it
receives a wake-up event and either the PME Enable bit in the Power Management
Control/Status Register or the Advanced Power Management Enable (APME) bit of the
Wake-up Control Register (WUC) is 1b.
PME#
OD
I
Auxiliary Power. If the Auxiliary Power signal is high, then auxiliary power is available
and the 82540EP device should support the D3cold power state.
AUX_PWR
3.2.7
Impedance Compensation Signals
Symbol
Type
Name and Function
N Device Impedance Compensation. This signal should be connected to an external
precision resistor (to VDD) that is indicative of the PCI trace load. This cell is used to
dynamically determine the drive strength required on the N-channel transistors in the
PCI I/O cells.
ZN_COMP I/O
ZP_COMP I/O
SMB Signals
P Device Impedance Compensation. This signal should be connected to an external
precision resistor (to VSS) that is indicative of the PCI trace load. This cell is used to
dynamically determine the drive strength required on the P-channel transistors in the
PCI I/O cells.
3.2.8
Symbol
Type
Name and Function
SMBCLK
I/O
I/O
O
SMB Clock. The SMB Clock signal is an open drain signal for serial SMB interface.
SMB Data. The SMB Data signal is an open drain signal for serial SMB interface.
SMB Alert. The SMB Alert signal is open drain for serial SMB interface.
SMBDATA
SMBALRT#
3.3
EEPROM and Serial FLASH Interface Signals
Symbol
EE_DI
Type
Name and Function
EEPROM Data Input. The EEPROM Data Input pin is used for output to the memory
O
device.
EEPROM Data Output. The EEPROM Data Output pin is used for input from the
memory device. The EE_DO includes an internal pull-up resistor.
EE_DO
EE_CS
EE_SK
I
O
O
EEPROM Chip Select. The EEPROM Chip Select signal is used to enable the device.
EEPROM Serial Clock. The EEPROM Shift Clock provides the clock rate for the
EEPROM interface, which is approximately 1 MHz.
12
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Symbol
Type
Name and Function
FL_CE#
O
FLASH Chip Enable Output. Used to enable FLASH device.
FLASH Serial Clock Output. The clock rate of the serial FLASH interface is
approximately 1 MHz.
FL_SCK
FL_SI
O
O
I
FLASH Serial Data Input. This pin is an output to the memory device.
FLASH Serial Data Output. This pin is an input from the FLASH memory. It has an
internal pullup device.
FL_SO
3.4
Miscellaneous Signals
3.4.1
LED Signals
Symbol
Type
Name and Function
LED0 / LINK Up. Programmable LED indication. Defaults to indicate link
connectivity.
LED0 / LINK#
O
LED1 / Activity. Programmable LED indication. Defaults to flash to indicate
transmit or receive activity.
LED1 / ACT#
O
O
O
LED2 / LINK 100. Programmable LED indication. Defaults to indicate link at
100 Mbps.
LED2 / LINK100#
LED3 / LINK1000#
LED3 / LINK 1000. Programmable LED indication. Defaults to indicate link at
1000 Mbps.
3.4.2
Other Signals
Symbol
Type
Name and Function
Software Defined Pin. The Software Defined Pins are reserved and programmable
with respect to input and output capability. These default to input signals upon power-up
but may be configured differently by the EEPROM. The upper four bits may be mapped
to the General Purpose Interrupt bits if they are configured as input signals.
SDP[7:6]
SDP[1:0]
TS
Note: SDP5 is not included in the group of Software Defined Pins.
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82540EP — Networking Silicon
3.5
3.5.1
Crystal Signals
Symbol
Type
Name and Function
Crystal One. The Crystal One pin is a 25 MHz +/- 50 ppm input signal. It can be
connected to either an oscillator or crystal. If a crystal is used, Crystal Two (XTAL2)
must also be connected.
XTAL1
I
Crystal Two. Crystal Two is the output of an internal oscillator circuit used to drive a
crystal into oscillation. If an external oscillator is used in the design, XTAL2 must be
disconnected.
XTAL2
O
3.5.2
Analog Signals
Symbol
REF
Type
Name and Function
Reference. This Reference signal should be connected to VSS through an external
2.49 KΩ resistor.
P
Media Dependent Interface [0].
1000BASE-T: In MDI configuration, MDI[0]+/- corresponds to BI_DA+/-, and in MDI-X
configuration, MDI[0]+/- corresponds to BI_DB+/-.
MDI[0]+/-
MDI[1]+/-
A
A
100BASE-TX: In MDI configuration, MDI[0]+/- is used for the transmit pair, and in MDI-X
configuration, MDI[0]+/- is used for the receive pair.
10BASE-T: In MDI configuration, MDI[0]+/- is used for the transmit pair, and in MDI-X
configuration, MDI[0]+/- is used for the receive pair.
Media Dependent Interface [1].
1000BASE-T: In MDI configuration, MDI[1]+/- corresponds to BI_DB+/-, and in MDI-X
configuration, MDI[1]+/- corresponds to BI_DA+/-.
100BASE-TX: In MDI configuration, MDI[1]+/- is used for the receive pair, and in MDI-X
configuration, MDI[1]+/- is used for the transit pair.
10BASE-T: In MDI configuration, MDI[1]+/- is used for the receive pair, and in MDI-X
configuration, MDI[1]+/- is used for the transit pair.
Media Dependent Interface [2].
1000BASE-T: In MDI configuration, MDI[2]+/- corresponds to BI_DC+/-, and in MDI-X
configuration, MDI[2]+/- corresponds to BI_DD+/-.
MDI[2]+/-
MDI[3]+/-
A
A
100BASE-TX: Unused.
10BASE-T: Unused.
Media Dependent Interface [3].
1000BASE-T: In MDI configuration, MDI[3]+/- corresponds to BI_DD+/-, and in MDI-X
configuration, MDI[3]+/- corresponds to BI_DC+/-.
100BASE-TX: Unused.
10BASE-T: Unused.
14
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Networking Silicon — 82540EP
3.6
Test Interface Signals
Symbol
Type
Name and Function
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
I
JTAG Clock.
JTAG TDI.
I
O
I
JTAG TDO.
JTAG TMS.
JTAG_
TRST#
JTAG Reset. This is an active low reset signal for JTAG. This signal should be
terminated using a pull-down resistor to ground. It must not be left unconnected.
I
TEST
I
Factory Test Pin.
Clock View. Output for GTX_CLK and RX_CLK during IEEE PHY conformance testing.
The clock is selected by register programming.
CLKVIEW
O
3.7
Power Supply Connections
3.7.1
Digital Supplies
Symbol
Type
Name and Function
VDDO
DVDD
P
3.3 V I/O Power Supply.
1.5 V Digital Core Power Supply.
P
3.7.2
Analog Supplies
Symbol
Type
Name and Function
AVDDH
AVDDL
P
3.3 V Analog Power Supply.
2.5 V Analog Power Supply.
P
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82540EP — Networking Silicon
3.7.3
Ground and No Connects
Symbol
GND
NC
Type
Name and Function
P
Ground.
No Connect. Do not connect any circuitry to these pins. Pull-up or pull-down resistors
should not be connected to these pins.
P
3.7.4
Control Signals
Symbol
Type
Name and Function
1.5V Control. LDO voltage regulator output to drive external pass transistor. If 1.5V is
already present in the system, leave output unconnected. To achieve optimal D3 power
consumption (<50 mw), leave the output unconnected and use a high-efficiency
external switching regulator.
CTRL_15
A
2.5V Control. LDO voltage regulator output to drive external pass transistor. If 2.5V is
already present in the system, leave output unconnected. To achieve optimal D3 power
consumption (<50 mw), leave the output unconnected and use a high-efficiency
external switching regulator.
CTRL_25
A
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Networking Silicon — 82540EP
4.0
Voltage, Temperature, and Timing Specifications
Note: The specification values listed in this section are subject to change without notice. Verify with your
local Intel sales office that you have the latest information before finalizing a design.
4.1
Absolute Maximum Ratings
Table 1. Absolute Maximum Ratingsa
Symbol
Parameter
Min
Max
Unit
VDD
DC supply voltage
-0.3
7
V
VIN
IIN
Input voltage
-1
VDD + 0.3
10
V
DC input pin current
-10
mA
Storage
temperature
TSTG
-40
125
°C
a. Maximum ratings are referenced to ground (VSS). Permanent device damage is likely to occur if the ratings in this table are
exceeded. These values should not be used as the limits for normal device operations.
4.2
Recommended Operating Conditions
Table 2. Recommended Operating Conditionsa (Sheet 1 of 2)
Symbol
Parameter
Condition
Min
Typ
Max
Unit
Operating
Temperature
TOP
0
70
°C
VIO Voltage
Range
VIO
3
3
5.25
3.6
V
V
Periphery
Voltage
Range
VDD
3.3V ± 10%
3.3
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82540EP — Networking Silicon
Table 2. Recommended Operating Conditionsa (Sheet 2 of 2)
Symbol
Parameter
Condition
Min
Typ
Max
Unit
Analog High
VDD Range
VAH
3.3V ± 10%
3
3.3
3.6
V
Core Digital
Voltage
Range
VD
1.5V ± 5%
2.5V ± 5%
1.425
2.375
1.5
2.5
1.575
2.625
V
V
Analog Low
VDD Range
VAL
a. Sustained operation of the device at conditions exceeding these values, even if they are within the absolute maximum rating
limits, might result in permanent damage.
4.3
DC Specifications
Table 3. DC Characteristics
Symbol
Parameter
Min
Typ
Max
Units
DC supply voltage on VDDO or
AVDDH
VDD (3.3)
VDD (2.5)
3.00
3.3
3.60
V
DC supply voltage on AVDDL
DC supply voltage on DVDD
2.38
1.43
2.5
1.5
2.62
1.57
V
V
V
DD (1.5)
Table 4. Power Specifications - D0a
D0a
unplugged/no link
@10 Mbps
TypIcc M ax Ic c
@100Mbps
@1000Mbps
Typ Icc
(mA)
MaxIcc
(mA)
Typ Icc
(mA)
MaxIcc
(mA)
Typ Icc
M a x I c c
(mA)
(mA)
(mA)
(mA)
125
145
400
3.3V
2.5V
1.5V
40
20
40
20
55
65
65
80
60
125
150
425
30
35
55
100
120
95
100
115
125
Total
Device
Power
325 mW
400 mW
525 mW
1.38 W
1.5 W
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Networking Silicon — 82540EP
Table 5. Power Specifications - D3cold
D3cold - wake
disabled - max
power savings
mode disabled
D3cold - wake
disabled - max
power savings
mode enableda
D3cold - wake-up enabled
unplugged/no link
@10 Mbps
@100Mbps
TypIcc
(mA)
MaxIcc
(mA)
Typ Icc
(mA)
MaxIcc
(mA)
Typ Icc
(mA)
MaxIcc
(mA)
Typ Icc
(mA)
MaxIcc
(mA)
Typ Icc
(mA)
MaxIcc
(mA)
3.3V
2.5V
1.5V
40
20
40
40
20
40
55
55
30
35
50
50
55
60
40
20
10
40
20
10
6
0.1
1
8
30
55
0.1
1
30
55
Total
Device
Power
240 mW
300 mW
385 mW
195 mW
20 mW
a. Special Note: To obtain the benefit of max power savings mode, do not use the internal voltage regulator control circuit and external pass transis-
tors. Use external switching regulators for highest efficiency.
Table 6. Power Specifications D(r) Uninitialized
D(r) Uninitialized
(LAN_PWR_GOOD=0)
Typ Icc
(mA)
Max Icc
(mA)
3.3V
2.5V
1.5V
40
40
45
45
190
200
TotalDevice
Power
520 mW
Table 7. Power Specifications - Complete Subsystem
Complete Subsystem (Reference Design)
Including Magnetics, LED, Regulator Circuits
D3cold - wake
disabled - max
power savings
mode disabled
D3cold - wake
disabled - max
power savings
mode enabled
D3cold wake-
enabled @10Mbps enabled @100Mbps
D3cold wake-
D0 @1000Mbps
active
Typ
Icc
(mA)
TypIcc MaxIcc
Typ Icc
(mA)
MaxIcc
(mA)
Typ Icc
(mA)
MaxIcc
(mA)
MaxIcc
(mA)
Ty p I c c
(mA)
MaxIcc
(mA)
(mA)
(mA)
3.3V
40
40
60
60
60
60
130
130
6
8
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82540EP — Networking Silicon
Table 7. Power Specifications - Complete Subsystem
2.5V
1.5V
20
10
20
10
40
30
40
35
80
55
80
60
240
400
245
425
0.1
1
0.1
1
Subsystem
3.3V current
70 mA
135 mA
200 mA
800 mA
10 mA
Table 8. I/O Characteristics
Symbol
Parameter
Voltage input LOW
Voltage input HIGH
Condition
Min
Typ
Max
Unit
VIL
VIH
-0.5
2
0.8
V
VDD
+0.3
V
VOL
VOH
VSH
Voltage output LOW
0.4
V
V
V
Voltage output HIGH
Schmitt Trigger Hysterysis
2.4
0.1
Output current LOW
3mA drivers (TTL3)
6mA drivers (TTL6)
12mA drivers (TTL12)
VOL
VOL
VOL
3
6
mA
mA
mA
a
IOL
12
Output current HIGH
3mA drivers (TTL3)
6mA drivers (TTL6)
12mA drivers (TTL12)
VOH
VOH
VOH
-3
-6
mA
mA
mA
a
IOH
-12
Input Current
VIN = VDD or
VSS
10
µA
µA
µA
TTL inputs
-10
150
-150
IIN
±1
VIN = VDD
IN = VSS
Inputs with pull-down resistors
TTL inputs with pull-up resistors
480
-480
V
VOH = VDD or
VSS
IOZ
3-state output leakage current
Input capacitance
-10
±1
2.5
2
10
µA
Any input and
bi-directional
buffer
CIN
pF
Any output
buffer
COUT
CPUD
Output capacitance
pF
Pull-up/down Resistor value
7.5
20
kΩ
a. TTL3 signals include: EE_DI, EE_SK, EE_CS, and JTAG_TDO.
TTL6 signals include: CLKRUN#, FL_CE#, FL_SCK, FL_SI, and CLK_VIEW.
TTL12 signals include: LED0 / LINK #, LED1 / ACT #, LED2 / LINK100 #, LED3 / LINK1000 #, SDP0, SDP1, SDP6, and SDP7.
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Networking Silicon — 82540EP
4.4
AC Characteristics
Table 9. AC Characteristics: 3.3 V Interfacing
Symbol
PCICLK
Parameter
Min
Typ
Max
Unit
Clock frequency in PCI mode
66
MHz
Table 10. 25 MHz Clock Input Requirements
Symbol
Parametera
Min
Typ
Max
Unit
25 + 50
ppm
fi_TX_CLK
TX_CLK_IN frequency
25 - 50 ppm
25
MHz
a. This parameter applies to an oscillator connected to the Crystal One (XTAL1) input. Alternatively, a crystal may be connected
to XTAL1 and XTAL2 as the frequency source for the internal oscillator.
Table 11. Link Interface Clock Requirements
Symbol
fGTXa
Parameter
Min
Typ
Max
Unit
GTX_CLK frequency
125
MHz
a. GTX_CLK is used externally for test purposes only.
Table 12. EEPROM Interface Clock Requirements
Symbol
Parameter
Min
Typ
Max
Unit
fSK
1
MHz
Table 13. AC Test Loads for General Output Pins
Symbol
CL
Signal Name
Value
Units
TDO
10
16
18
20
pF
pF
pF
pF
CL
CL
CL
PME#, SDP[7:0]
EE_DI, EE_SK
RX_ACTIVITY, TX_ACTIVITY, LINK_UP
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82540EP — Networking Silicon
Figure 1. AC Test Loads for General Output Pins
CL
4.5
Timing Specifications
Note: Timing specifications are subject to change. Verify with your local Intel sales office that you have
the latest information before finalizing a design.
4.5.1
PCI Bus Interface
4.5.1.1
PCI Bus Interface Clock
Table 14. PCI Bus Interface Clock Parameters
PCI 66 MHz
PCI 33 MHz
Symbol
Parametera
Units
Min
Max
Min
Max
TCYC
CLK cycle time
15
6
30
30
11
11
1
ns
ns
TH
TL
CLK high time
CLK low time
CLK slew rate
RST# slew rateb
6
ns
1.5
50
4
4
V/ns
mV/ns
50
a. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the
minimum peak-to-peak portion of the clock waveform as shown.
b. The minimum RST# slew rate applies only to the rising (de-assertion) edge of the reset signal and ensures that system
noise cannot render a monotonic signal to appear bouncing in the switching range.
Figure 2. PCI Clock Timing
Tcyc
3.3 V Clock
Th
0.6 Vcc
0.5 Vcc
0.4 Vcc
0.3 Vcc
0.4 Vcc p-to-p
(minimum)
0.2 Vcc
Tl
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Networking Silicon — 82540EP
4.5.1.2
PCI Bus Interface Timing
Table 15. PCI Bus Interface Timing Parameters
PCI 66MHz
PCI 33 MHz
Units
Symbol
Parameter
Min
Max
Min
Max
CLK to signal valid delay: bussed
signals
TVAL
2
6
2
11
ns
ns
CLK to signal valid delay: point-
to-point signals
TVAL(ptp)
2
2
6
2
2
12
28
TON
Float to active delay
Active to float delay
ns
ns
TOFF
14
Input setup time to CLK: bussed
signals
TSU
3
5
7
ns
ns
Input setup time to CLK: point-to-
point signals
TSU(ptp)
10, 12
TH
Input hold time from CLK
REQ64# to RST# setup time
RST# to REQ64# hold time
0
10*TCYC
0
0
10*TCYC
0
ns
ns
ns
TRRSU
TRRH
NOTES:
1. Output timing measurements are as shown.
2. REQ# and GNT# signals are point-to-point and have different output valid delay and input setup times than
bussed signals. GNT# has a setup of 10 ns; REQ# has a setup of 12 ns. All other signals are bussed.
3. Input timing measurements are as shown.
Figure 3. PCI Bus Interface Output Timing Measurement
VTH
PCI_CLK
VTEST
VTL
Output
Delay
VTEST
VSTEP (3.3V Signalling)
≤
output current
leakage current
Tri-State
Output
TON
TOFF
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82540EP — Networking Silicon
Figure 4. PCI Bus Interface Input Timing Measurement Conditions
VTH
VTL
PCI_CLK
VTEST
TSU
T
H
VTH
VTL
Input
Valid
Input
VMAX
VTEST
VTEST
Table 16. PCI Bus Interface Timing Measurement Conditions
PCI 66 MHz
3.3 v
Symbol
Parameter
Unit
VTH
Input measurement test voltage (high)
Input measurement test voltage (low)
Output measurement test voltage
Input signal slew rate
0.6*VCC
0.2*VCC
0.4*VCC
1.5
V
V
VTL
VTEST
V
V/ns
Figure 5. TVAL (max) Rising Edge Test Load
Pin
Test
Point
1/2 inch max.
25Ω
10 pF
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Networking Silicon — 82540EP
Figure 6. TVAL (max) Falling Edge Test Load
Pin
Test
Point
1/2 inch max.
25Ω
VCC
10 pF
Figure 7. TVAL (min) Test Load
Pin
Test
Point
1/2 inch max.
10 pF
1kΩ
1kΩ
VCC
Figure 8. TVAL Test Load (PCI 5 V Signaling Environment)
Pin
Test
Point
1/2 inch max.
50 pF
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82540EP — Networking Silicon
4.5.2
Link Interface Timing
Table 17. Rise and Fall Times
Symbol
Parameter
Clock rise time
Condition
Min
Max
Unit
TR
TF
TR
TF
0.8 V to 2.0 V
2.0 V to 0.8 V
0.8 to 2.0 V
0.7
0.7
0.7
0.7
ns
ns
ns
ns
Clock fall time
Data rise time
Data fall time
2.0 V to 0.8 V
Figure 9. Link Interface Rise/Fall Timing
2.0 V
0.8 V
T
R
T
F
4.5.3
EEPROM Interface
Table 18. Link Interface Clock Requirements
Symbol
TPW
Parameter
Min
Min
Typ
Max
Unit
EE_SK pulse width
TPERIOD*128
ns
a. The EEPROM clock is derived from a 125 MHz internal clock.
Table 19. Link Interface Clock Requirements
Symbol
Parametera
Typ
Max
Unit
TDOS
TDOH
a.
EE_DO setup time
EE_DO hold time
TCYC*2
0
ns
ns
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Networking Silicon — 82540EP
5.0
Package and Pinout Information
This section describes the 82540EP device, manufactured in a 196-lead ball grid array measuring
5.1
Device Identification
Figure 10. 82540EP Device Identification Markings
RC82540EP
YYWW © 'ZZ
Tnnnnnnnn
Country
82540EP
YYWW
Product Name
Date Code
Tnnnnnnnn
(c)’ZZ
Lot Trace Code
Copyright Information
Country of Origin Assembly
Country
NOTE: “•“indicates the location of pin 1. It is not an actual mark on the device
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Networking Silicon — 82540EP
5.3
Thermal Specifications
The 82540EP device is specified for operation when the ambient temperature (TA) is within the
range of 0° C to 70° C.
TC (case temperature) is calculated using the equation:
TC = TA + P (θJA - q JC)
TJ (junction temperature) is calculated using the equation:
TJ = TA + P θJA
P (power consumption) is calculated by using the typical ICC, as indicated inTable 4 of Section 4.0,
Table 18. Thermal Characteristics
Value at specified airflow (m/s)
Symbol
Parameter
Units
0
1
2
3
°C/
Watt
θJA
θJC
Thermal resistance, junction-to-ambient
Thermal resistance, junction-to-case
28.1
25.0
23.7
22.8
°C/
Watt
6.1
6.1
6.1
6.1
Thermal resistances are determined empirically with test devices mounted on standard thermal test
boards. Real system designs may have different characteristics due to board thickness, arrangement
of ground planes, and proximity of other components. The case temperature measurements should
be used to assure that the 82540EP device is operating under recommended conditions.
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82540EP — Networking Silicon
5.4
Pinout Information
Table 19. PCI Address, Data, and Control Signals
Signal
PCI_AD[0]
Pin
Signal
Pin
Signal
CBE0#
Pin
N7
M7
P6
P5
N5
M5
P4
N4
P3
N3
N2
M1
M2
M3
L1
PCI_AD[16]
PCI_AD[17]
PCI_AD[18]
PCI_AD[19]
PCI_AD[20]
PCI_AD[21]
PCI_AD[22]
PCI_AD[23]
PCI_AD[24]
PCI_AD[25]
PCI_AD[26]
PCI_AD[27]
PCI_AD[28]
PCI_AD[29]
PCI_AD[30]
PCI_AD[31]
K1
E3
D1
D2
D3
C1
B1
B2
B4
A5
B5
B6
C6
C7
A8
B8
M4
L3
F3
C4
J1
PCI_AD[1]
PCI_AD[2]
PCI_AD[3]
PCI_AD[4]
PCI_AD[5]
PCI_AD[6]
PCI_AD[7]
PCI_AD[8]
PCI_AD[9]
PCI_AD[10]
PCI_AD[11]
PCI_AD[12]
PCI_AD[13]
PCI_AD[14]
PCI_AD[15]
CBE1#
CBE2#
CBE3#
PAR
FRAME#
IRDY#
TRDY#
STOP#
DEVSEL#
VIO
F2
F1
G3
H1
H3
G2
A4
IDSEL
L2
Table 20. PCI Arbitration Signals
Signal
Pin
REQ#
GNT#
C3
J3
Table 21. Interrupt Signals
Signal
Pin
INTA#
H2
Table 22. System Signals
Signal
Pin
Signal
Pin
Signal
Pin
CLK
G1
M66EN
C2
RST#
B9
Table 23. Error Reporting Signals
Signal
SERR#
Pin
Signal
Pin
A2
PERR#
J2
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Networking Silicon — 82540EP
Table 24. Power Management Signals
Signal
Pin
Signal
AUX_PWR
CLKRUN#
Pin
LAN_PWR_
GOOD
A9
A6
J12
C8
PME#
Table 25. Impedance Compensation Signals
Signal
ZN_COMP
Pin
Signal
ZP_COMP
Pin
H4
G4
Table 26. SMB Signals
Signal
Pin
Signal
SMBDATA
Pin
Signal
Pin
SMBCLK
A10
C9
SMBALRT#
B10
Table 27. EEPROM and Serial FLASH Interface Signals
Signal
EE_SK
Pin
Signal
EE_DI
Pin
Signal
Pin
M10
N10
P7
P10
M9
FL_SCK
FLSO
N9
P9
EE_DO
EE_CS
FL_CE#
FL_SI
M11
Table 28. LED Signals
Signal
Pin
Signal
Pin
LED0 / LINK#
LED1 / ACT#
A12
C11
LED2 / LINK100#
LED3 / LINK1000#
B11
B12
Table 29. Other Signals
Signal
Pin
Signal
Pin
Signal
Pin
SDP0
SDP1
N14
P13
SDP6
SDP7
N13
M12
CTRL_15
CTRL_25
P11
B13
Table 30. IEEE Test Signals
Signal
Pin
CLK_VIEW
M8
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82540EP — Networking Silicon
Table 31. PHY Signals
Signal
Pin
Signal
MDI0+
Pin
Signal
MDI2+
Pin
XTAL1
XTAL2
REF
K14
J14
B14
C14
C13
E14
E13
F14
F13
H14
H13
MDI1-
MDI1+
MDI2-
MDI3-
MDI3+
MDI0-
Table 32. Test Interface Signals
Signal
Pin
Signal
Pin
Signal
Pin
JTAG_TCK
JTAG_TDI
L14
JTAG_TDO
JTAG_TMS
M14
L12
JTAG_RST#
TEST
L13
A13
M13
Table 33. Digital Power Signals
Signal
Pin
Signal
Pin
Signal
Pin
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
E11
E12
G5
G6
G13
H5
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
J8
DVDD (1.5V)
DVDD (1.5V)
VDDO (3.3V)
VDDO (3.3V)
VDDO (3.3V)
VDDO (3.3V)
VDDO (3.3V)
VDDO (3.3V)
VDDO (3.3V)
VDDO (3.3V)
VDDO (3.3V)
VDDO (3.3V)
VDDO (3.3V)
L9
J9
L10
A3
J10
J11
K5
K6
K7
K8
K9
A7
A11
E1
H6
K3
H7
K4
H8
K13
N6
N8
P2
H11
J5
K10
K11
L4
J6
J7
L5
P12
Table 34. Analog Power Signals
Signal
Pin
Signal
Pin
Signal
Pin
AVDDL (2.5 V)
AVDDL (2.5 V)
D9
AVDDL (2.5 V)
G12
AVDDL (2.5 V)
L8
D11
32
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Networking Silicon — 82540EP
Table 35. Grounds and No Connect Signals
Signal
GND
Pin
Signal
GND
Pin
Signal
GND
Pin
Signal
NC
Pin
B3
E7
E8
E9
E10
F4
G9
A1
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
B7
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
G10
G11
G14
H9
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
A14
C5
C10
C12
D4
D5
D6
D7
D8
D13
E2
D10
D12
D14
F12
H12
J4
F5
H10
K2
F6
F7
K12
L6
F8
F9
L11
M6
J13
L7
F10
F11
G7
G8
E4
N1
N11
P1
E5
N12
P8
E6
P14
Table 36. Signal Names in Pin Order (Sheet 1 of 6)
Signal Name
Pin
NC
A1
A2
SERR#
VDDO (3.3V)
IDSEL
A3
A4
PCI_AD[25]
PME#
A5
A6
VDDO (3.3V)
PCI_AD[30]
LAN_PWR_GOOD
SMBCLK
A7
A8
A9
A10
A11
A12
A13
A14
B1
VDDO (3.3V)
LED0 / LINK#
TEST
NC
PCI_AD[22]
PCI_AD[23]
GND
B2
B3
PCI_AD[24]
B4
Datasheet
33
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82540EP — Networking Silicon
Table 36. Signal Names in Pin Order (Sheet 2 of 6) (Continued)
Signal Name
PCI_AD[26]
Pin
B5
B6
PCI_AD[27]
GND
B7
PCI_AD[31]
RST#
B8
B9
SMBALRT#
LED2 / LINK100#
LED3 / LINK1000#
CTRL_25
REF
B10
B11
B12
B13
B14
C1
PCI_AD[21]
M66EN
C2
REQ#
C3
CBE3#
C4
NC
C5
PCI_AD[28]
PCI_AD[29]
CLKRUN#
SMBDATA
GND
C6
C7
C8
C9
C10
C11
C12
C13
C14
D1
LED1 / ACT#
GND
MDI0+
MDI0-
PCI_AD[18]
PCI_AD[19]
PCI_AD[20]
GND
D2
D3
D4
GND
D5
GND
D6
GND
D7
GND
D8
AVDDL (2.5 V)
NC
D9
D10
D11
D12
D13
D14
AVDDL (2.5 V)
NC
GND
NC
34
Datasheet
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Networking Silicon — 82540EP
Table 36. Signal Names in Pin Order (Sheet 3 of 6) (Continued)
Signal Name
VDDO (3.3V)
Pin
E1
E2
GND
PCI_AD[17]
GND
E3
E4
GND
E5
GND
E6
GND
E7
GND
E8
GND
E9
GND
E10
E11
E12
E13
E14
F1
DVDD (1.5V)
DVDD (1.5V)
MDI1+
MDI1-
IRDY#
FRAME#
CBE2#
GND
F2
F3
F4
GND
F5
GND
F6
GND
F7
GND
F8
GND
F9
GND
F10
F11
F12
F13
F14
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
GND
NC
MDI2+
MDI2-
CLK
VIO
TRDY#
ZP_COMP
DVDD (1.5V)
DVDD (1.5V)
GND
GND
GND
GND
Datasheet
35
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82540EP — Networking Silicon
Table 36. Signal Names in Pin Order (Sheet 4 of 6) (Continued)
Signal Name
Pin
GND
G11
G12
G13
G14
H1
AVDDL (2.5 V)
DVDD (1.5V)
GND
STOP#
INTA#
H2
DEVSEL#
ZN_COMP
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
GND
H3
H4
H5
H6
H7
H8
H9
GND
H10
H11
H12
H13
H14
J1
DVDD (1.5V)
NC
MDI3+
MDI3-
PAR
PERR#
J2
GNT#
J3
NC
J4
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
AUX_PWR
NC
J5
J6
J7
J8
J9
J10
J11
J12
J13
J14
K1
XTAL2
PCI_AD[16]
GND
K2
VDDO (3.3V)
VDDO (3.3V)
DVDD (1.5V)
DVDD (1.5V)
K3
K4
K5
K6
36
Datasheet
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Networking Silicon — 82540EP
Table 36. Signal Names in Pin Order (Sheet 5 of 6) (Continued)
Signal Name
DVDD (1.5V)
Pin
K7
K8
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
GND
K9
K10
K11
K12
K13
K14
L1
VDDO (3.3V)
XTAL1
PCI_AD[14]
PCI_AD[15]
CBE1#
L2
L3
DVDD (1.5V)
DVDD (1.5V)
GND
L4
L5
L6
NC
L7
AVDDL (2.5 V)
DVDD (1.5V)
DVDD (1.5V)
GND
L8
L9
L10
L11
L12
L13
L14
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
N1
JTAG_TMS
JTAG_RST#
JTAG_TCK
PCI_AD[11]
PCI_AD[12]
PCI_AD[13]
CBE0#
PCI_AD[5]
GND
PCI_AD[1]
CLK_VIEW
FL_CE#
EE_SK
FL_SI
SDP7
JTAG_TDI
JTAG_TDO
GND
PCI_AD[10]
N2
Datasheet
37
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82540EP — Networking Silicon
Table 36. Signal Names in Pin Order (Sheet 6 of 6) (Continued)
Signal Name
PCI_AD[9]
Pin
N3
N4
PCI_AD[7]
PCI_AD[4]
VDDO (3.3V)
PCI_AD[0]
VDDO (3.3V)
FL_SCK
EE_DO
N5
N6
N7
N8
N9
N10
N11
N12
N13
N14
P1
NC
GND
SDP6
SDP0
NC
VDDO (3.3V)
PCI_AD[8]
PCI_AD[6]
PCI_AD[3]
PCI_AD[2]
EE_CS
P2
P3
P4
P5
P6
P7
GND
P8
FL_SO
P9
EE_DI
P10
P11
P12
P13
P14
CTRL_15
VDDO (3.3V)
SDP1
NC
38
Datasheet
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Networking Silicon — 82540EP
5.5
Visual Pin Reference
A
B
C
D
E
F
G
H
J
K
L
M
N
P
•
14
13
12
11
10
9
PHY
MDI-
MDI-
MDI-
MDI-
NC
NC
VSS
XTAL2 XTAL1
JTCK
JTDO SDP[0]
NC
14
13
12
11
10
9
REF
[0]
[1]
[2]
[3]
CTRL
25
MDI+
[0]
MDI+
[1]
MDI+
[2]
MDI+
[3]
TEST
LINK
3.3V
VSS
NC
1.5V
NC
3.3V
VSS
1.5V
1.5V
1.5V
1.5V
1.5V
1.5V
1.5V
3.3V
3.3V
VSS
AD16
JTRST#
JTDI
SDP[6] SDP[1]
LINK
1000
2.5V
PHY
AUX
VSS
1.5V
1.5V
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AD17
VSS
3.3V
NC
NC
JTMS SDP[7]
VSS
NC
3.3V
PWR
LINK
100
ACT
LED
2.5V
PHY
FLSH
CTRL
15
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
1.5V
1.5V
1.5V
VSS
VSS
1.5V
1.5V
1.5V
1.5V
1.5V
1.5V
1.5V
1.5V
1.5V
1.5V
1.5V
NC
VSS
SI
SMB
CLK
SMB
VSS
NC
1.5V
1.5V
EESK
EEDO
EEDI
ALRT#
LAN
SMB
DAT
2.5V
PHY
FLSH
CE_N
FLSH
SCK
FLSH
SO
RST#
AD31
VSS
PWRGD
CLK
2.5V
PHY
CLK
AD30
3.3V
VSS
VSS
VSS
VSS
3.3V
AD0
3.3V
AD4
AD7
AD9
AD10
VSS
VSS
EECS
AD2
AD3
AD6
AD8
3.3V
NC
8
8
RUN#
VIEW
AD29
AD28
NC
NC
VSS
1.5V
1.5V
AD1
VSS
AD5
7
7
PME#
AD25
IDSEL
3.3V
AD27
AD26
6
6
5
5
CBE#
[0]
AD24 CBE# [3] VSS
PCIZP PCIZN
4
4
CBE#
[2]
DEV
TRDY#
CBE#
[1]
VSS
REQ#
AD20
GNT#
AD13
AD12
AD11
3
3
SEL#
FRAME
#
SERR#
NC
AD23 M66EN AD19
VIO
INTA# PERR#
AD15
AD14
2
2
AD22
AD21
AD18
IRDY#
CLK
STOP#
PAR
1
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
Figure 12. Ball Grid Array / Pin Reference for 196-TFBGA (thru-the-top view)
Datasheet
39
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