Intel Laptop 317443 001US User Manual
®
TM  
Intel Core 2 Duo processor with  
®
the Mobile Intel 945GME Express  
Chipset  
Development Kit User’s Manual  
May 2007  
Order Number: 317443-001US  
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Contents—Intel 945GME Express Chipset  
Contents  
1.0 About This Manual.....................................................................................................7  
1.1  
1.2  
1.3  
1.4  
Content Overview................................................................................................7  
Text Conventions ................................................................................................7  
Glossary of Terms and Acronyms...........................................................................9  
Support Options................................................................................................ 14  
1.4.1 Electronic Support Systems ..................................................................... 14  
1.4.2 Additional Technical Support.................................................................... 14  
Product Literature ............................................................................................. 14  
Related Documents ........................................................................................... 15  
1.5  
1.6  
2.0 Getting Started........................................................................................................ 16  
2.1  
Overview ......................................................................................................... 16  
2.1.1 Intel 945GME Express Chipset Development Kit Features........................... 16  
®
2.2  
2.3  
Included Hardware and Documentation ................................................................ 18  
Software Key Features....................................................................................... 18  
2.3.1 AMI* BIOS ............................................................................................ 18  
Before You Begin............................................................................................... 19  
Setting Up the Evaluation Board.......................................................................... 20  
Configuring the BIOS......................................................................................... 21  
2.4  
2.5  
2.6  
3.0 Theory of Operation................................................................................................. 22  
3.1  
3.2  
3.3  
3.4  
Block Diagram .................................................................................................. 22  
Mechanical Form Factor...................................................................................... 23  
Thermal Management ........................................................................................ 23  
System Features and Operation .......................................................................... 23  
3.4.1 Intel(R) 945GME GMCH........................................................................... 23  
3.4.1.1 System Memory ....................................................................... 24  
3.4.1.2 DMI ........................................................................................ 24  
3.4.1.3 Advanced Graphics and Display Interface..................................... 24  
3.4.2 ICH7-M................................................................................................. 24  
3.4.2.1 PCI Express* Slots.................................................................... 24  
3.4.2.2 PCI Slots ................................................................................. 25  
3.4.2.3 On-Board LAN .......................................................................... 25  
3.4.2.4 AC’97 and High Definition Audio.................................................. 25  
3.4.2.5 ATA / Storage .......................................................................... 25  
3.4.2.6 USB Connectors........................................................................ 26  
3.4.2.7 LPC Super I/O (SIO)/LPC Slot..................................................... 26  
3.4.2.8 Serial, IrDA.............................................................................. 26  
3.4.2.9 BIOS Firmware Hub (FWH)......................................................... 26  
3.4.2.10 System Management Controller (SMC)/Keyboard Controller............ 26  
3.4.2.11 Clocks..................................................................................... 27  
3.4.2.12 Real Time Clock........................................................................ 27  
3.4.2.13 Thermal Monitoring................................................................... 27  
3.4.3 System I/O and Connector Summary........................................................ 27  
3.4.3.1 PCI Express* Support................................................................ 28  
3.4.3.2 SATA Support........................................................................... 28  
3.4.3.3 IDE Support............................................................................. 28  
3.4.3.4 USB Ports ................................................................................ 28  
3.4.3.5 VGA Connector......................................................................... 28  
3.4.3.6 Keyboard/Mouse....................................................................... 29  
3.4.3.7 32 bit/33 MHz PCI Connectors .................................................... 29  
3.4.3.8 Ethernet Gigabit LAN Interface connector..................................... 29  
3.4.3.9 LVDS Flat Panel Display Interface................................................ 29  
3.4.4 POST Code Debugger.............................................................................. 29  
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Intel 945GME Express Chipset—Contents  
3.5  
3.6  
Clock Generation ...............................................................................................29  
Power Management States..................................................................................30  
3.6.1 Transition to S3......................................................................................31  
3.6.2 Transition to S4......................................................................................31  
3.6.3 Transition to S5......................................................................................31  
3.6.4 Transition to Full-On ...............................................................................31  
Power Measurement Support...............................................................................31  
3.7  
4.0 Hardware Reference ................................................................................................35  
4.1  
4.2  
4.3  
4.4  
4.5  
4.6  
Primary Features ...............................................................................................35  
Back Panel Connectors .......................................................................................38  
Configuration Settings........................................................................................39  
Power On and Reset Buttons ...............................................................................42  
LEDs................................................................................................................43  
Other Headers, Slots, and Sockets .......................................................................43  
4.6.1 H8 Programming Headers ........................................................................43  
4.6.2 Expansion Slots and Sockets ....................................................................44  
4.6.2.1 478 Pin Grid Array (Micro-FCPGA) Socket .....................................44  
4.6.2.2 PCI Express* (x16)....................................................................45  
4.6.2.3 Media Expansion Card (MEC) Slot................................................47  
4.6.2.4 PCI Express* (x1) .....................................................................49  
4.6.2.5 IDE Connector ..........................................................................51  
4.6.2.6 SATA Pinout .............................................................................51  
4.6.2.7 Fan Connectors.........................................................................52  
A
Heat Sink Installation Instructions ..........................................................................53  
Figures  
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1
2
3
4
5
6
7
8
9
Intel 945GME Express Chipset Development Kit Block Diagram.....................................22  
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Intel 945GME Express Chipset Component Locations...................................................35  
Back Panel Connector Locations..................................................................................38  
Configuration Jumper and Switch Locations..................................................................39  
®
Intel 945GME Express Chipset Development Kit Power On and Reset Buttons.................42  
Heatsink and Backplate.............................................................................................53  
Backplate Pins..........................................................................................................54  
Applying the Thermal Grease .....................................................................................55  
Squeezing Activation Arm..........................................................................................55  
10 Installing the Heatsink ..............................................................................................56  
11 Plugging in the Fan...................................................................................................57  
12 Completed Assembly.................................................................................................57  
Tables  
1
Acronyms................................................................................................................11  
2
3
4
5
6
7
8
9
Intel Literature Centers .............................................................................................14  
Related Documents...................................................................................................15  
Primary System Clocks..............................................................................................29  
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Intel 945GME Express Chipset Development Kit Power Management States....................30  
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Intel 945GME Express Chipset Development Kit Voltage Rails.......................................32  
®
Intel 945GME Express Chipset Component Location Legend .........................................36  
Supported Configuration Jumper/Switch Settings..........................................................40  
®
Intel 945GME Express Chipset LED Function Legend....................................................43  
10 H8 Programming Jumpers..........................................................................................44  
11 Expansion Slots and Sockets......................................................................................44  
12 PCI Express* (x16) Pinout (J6C1)...............................................................................45  
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Contents—Intel 945GME Express Chipset  
13 MEC Slot (J6C1)....................................................................................................... 47  
14 PCI Express* (x1) Pinout (J7C1, J8C1)........................................................................ 49  
15 IDE Connector (J7J1)................................................................................................ 51  
16 SATA Port 0 Data Connector Pinout (J7H1) .................................................................. 51  
17 SATA Port 0 Power Connector Pinout (J6H3) ................................................................ 52  
18 SATA Port 2 Mobile Drive Connector Pinout (J8J2) ........................................................ 52  
19 Fan Connectors (J3F1 and J3C1) ................................................................................ 52  
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Intel 945GME Express Chipset—Revision History  
Revision History  
Date  
Revision Description  
001 Initial release  
May 2007  
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About This Manual—Intel 945GME Express Chipset  
1.0  
About This Manual  
®
TM  
This user’s manual describes the use of the Intel Core 2 Duo processor with the  
®
Mobile Intel 945GME Express Chipset. This manual has been written for OEMs, system  
evaluators, and embedded system developers. This document defines all jumpers,  
headers, LED functions, and their locations on the board, along with subsystem  
features and POST codes. This manual assumes basic familiarity in the fundamental  
concepts involved with installing and configuring hardware for a personal computer  
system.  
®
For the latest information about the Intel 945GME Express Chipset Development Kit,  
visit:  
http://developer.intel.com/design/intarch/devkits/index.htm  
For design documents related to this platform please contact http://  
developer.intel.com/design/intarch/core2duo/tech_docs.htm.  
®
®
TM  
Note:  
The Intel 945GME Express Chipset supports both Intel Core Duo processors and  
®
TM  
®
®
Intel Core 2 Duo processors. For the Intel 945GME Express Chipset with Intel  
Core Duo Processors Development Kit User's Manual, visit http://download.intel.com  
TM  
1.1  
Content Overview  
Chapter 1.0, “About This Manual” — This chapter contains a description of conventions  
used in this manual. The last few sections explain how to obtain literature and contact  
customer support.  
Chapter 2.0, “Getting Started”— Provides complete instructions on how to configure  
the evaluation board and processor assembly by setting jumpers, connecting  
peripherals, providing power, and configuring the BIOS.  
Chapter 3.0, “Theory of Operation” — This chapter provides information on the system  
design.  
Chapter 4.0, “Hardware Reference”— This chapter provides a description of jumper  
settings and functions, board debug capabilities, and pinout information for connectors.  
Appendix A, “Heat Sink Installation Instructions” gives detailed installation instructions  
®
TM  
for the Intel Core 2 Duo processor heat sink.  
1.2  
Text Conventions  
The following notations may be used throughout this manual.  
#
The pound symbol (#) appended to a signal name indicates that  
the signal is active low. (e.g., PRSNT1#)  
Variables  
Variables are shown in italics. Variables must be replaced with  
correct values.  
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Intel 945GME Express Chipset—About This Manual  
Instructions  
Numbers  
Instruction mnemonics are shown in uppercase. When you are  
programming, instructions are not case-sensitive. You may use  
either uppercase or lowercase.  
Hexadecimal numbers are represented by a string of  
hexadecimal digits followed by the character H. A zero prefix is  
added to numbers that begin with A through F. (For example, FF  
is shown as 0FFH.) Decimal and binary numbers are  
represented by their customary notations. (That is, 255 is a  
decimal number and 1111 1111 is a binary number. In some  
cases, the letter B is added for clarity.)  
Units of Measure  
The following abbreviations are used to represent units of  
measure:  
A
amps, amperes  
GByte gigabytes  
KByte kilobytes  
KΩ  
kilo-ohms  
mA  
milliamps, milliamperes  
MByte megabytes  
MHz  
ms  
mW  
ns  
megahertz  
milliseconds  
milliwatts  
nanoseconds  
picofarads  
pF  
W
watts  
V
volts  
µA  
µF  
microamps, microamperes  
microfarads  
microseconds  
microwatts  
µs  
µW  
Signal Names  
Signal names are shown in uppercase. When several signals  
share a common name, an individual signal is represented by  
the signal name followed by a number, while the group is  
represented by the signal name followed by a variable (n). For  
example, the lower chip-select signals are named CS0#, CS1#,  
CS2#, and so on; they are collectively called CSn#. A pound  
symbol (#) appended to a signal name identifies an active-low  
signal. Port pins are represented by the port abbreviation, a  
period, and the pin number (e.g., P1.0).  
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1.3  
Glossary of Terms and Acronyms  
This section defines conventions and terminology used throughout this document.  
Aggressor  
Anti-etch  
A network that transmits a coupled signal to another network.  
Any plane-split, void or cutout in a VCC or GND plane.  
Assisted Gunning Transceiver Logic+  
The front-side bus uses a bus technology called AGTL+, or  
Assisted Gunning Transceiver Logic. AGTL+ buffers are open-  
drain, and require pull-up resistors to provide the high logic level  
and termination. AGTL+ output buffers differ from GTL+ buffers  
with the addition of an active pMOS pull-up transistor to assist  
the pull-up resistors during the first clock of a low-to-high  
voltage transition.  
Asynchronous GTL+ The processor does not utilize CMOS voltage levels on any  
signals that connect to the processor. As a result, legacy input  
signals such as A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/  
NMI, PWRGOOD, SMI#, SLP#, and STPCLK# utilize GTL+ input  
buffers. Legacy output signals (FERR# and IERR#) and non-  
AGTL+ signals (THERMTRIP# and PROCHOT#) also utilize GTL+  
output buffers. All of these signals follow the same DC  
requirements as AGTL+ signals, however the outputs are not  
actively driven high (during a logical 0 to 1 transition) by the  
processor (the major difference between GTL+ and AGTL+).  
These signals do not have setup or hold time specifications in  
relation to BCLK[1:0], and are therefore referred to as  
“Asynchronous GTL+ Signals”. However, all of the Asynchronous  
GTL+ signals are required to be asserted for at least two BCLKs  
in order for the processor to recognize them.  
Bus Agent  
Crosstalk  
A component or group of components that, when combined,  
represent a single load on the AGTL+ bus.  
The reception on a victim network of a signal imposed by  
aggressor network(s) through inductive and capacitive coupling  
between the networks.  
• Backward Crosstalk - Coupling that creates a signal in a  
victim network that travels in the opposite direction as the  
aggressor’s signal.  
• Forward Crosstalk - Coupling that creates a signal in a  
victim network that travels in the same direction as the  
aggressor’s signal.  
• Even Mode Crosstalk - Coupling from a signal or multiple  
aggressors when all the aggressors switch in the same  
direction that the victim is switching.  
• Odd Mode Crosstalk - Coupling from a signal or multiple  
aggressors when all the aggressors switch in the opposite  
direction that the victim is switching.  
Flight Time  
Flight time is a term in the timing equation that includes the  
signal propagation delay, any effects the system has on the TCO  
of the driver, plus any adjustments to the signal at the receiver  
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Intel 945GME Express Chipset—About This Manual  
needed to ensure the setup time of the receiver. More precisely,  
flight time is defined as:  
• The time difference between a signal at the input pin of a  
receiving agent crossing the switching voltage (adjusted to  
meet the receiver manufacturer’s conditions required for  
AC timing specifications; i.e., ringback, etc.) and the output  
pin of the driving agent crossing the switching voltage  
when the driver is driving a test load used to specify the  
driver’s AC timings.  
• Maximum and Minimum Flight Time - Flight time variations  
are caused by many different parameters. The more  
obvious causes include variation of the board dielectric  
constant, changes in load condition, crosstalk, power noise,  
variation in termination resistance, and differences in I/O  
buffer performance as a function of temperature, voltage,  
and manufacturing process. Some less obvious causes  
include effects of Simultaneous Switching Output (SSO)  
and packaging effects.  
• Maximum flight time is the largest acceptable flight time a  
network will experience under all conditions.  
• Minimum flight time is the smallest acceptable flight time a  
network will experience under all conditions.  
Infrared Data Assoc. The Infrared Data Association (IrDA) has outlined a specification  
for serial communication between two devices via a bi-  
directional infrared data port. The 945GME platform has such a  
port and it is located on the rear of the platform between the two  
USB connectors.  
®
IMVP6  
The Intel Mobile Voltage Positioning specification for the Intel  
Core™ 2 Duo Processor. It is a DC-DC converter module that  
supplies the required voltage and current to a single processor.  
Inter-Symbol Interference  
Inter-symbol interference is the effect of a previous signal (or  
transition) on the interconnect delay. For example, when a  
signal is transmitted down a line and the reflections due to the  
transition have not completely dissipated, the following data  
transition launched onto the bus is affected. ISI is dependent  
upon frequency, time delay of the line, and the reflection  
coefficient at the driver and receiver. ISI may impact both timing  
and signal integrity.  
Media Expansion Card  
The Media Expansion Card (MEC) provides digital display options  
through the SDVO interface. The MEC card also incorporates  
video-in.  
Network  
The network is the trace of a Printed Circuit Board (PCB) that  
completes an electrical connection between two or more  
components.  
Overshoot  
Pad  
The maximum voltage observed for a signal at the device pad,  
measured with respect to VCC.  
The electrical contact point of a semiconductor die to the  
package substrate. A pad is only observable in simulations.  
Pin  
The contact point of a component package to the traces on a  
substrate, such as the motherboard. Signal quality and timings  
may be measured at the pin.  
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Power-Good  
Ringback  
“Power-Good,” “PWRGOOD,” or “CPUPWRGOOD” (an active high  
signal) indicates that all of the system power supplies and clocks  
are stable. PWRGOOD should go active a predetermined time  
after system voltages are stable and should go inactive as soon  
as any of these voltages fail their specifications.  
The voltage to which a signal changes after reaching its  
maximum absolute value. Ringback may be caused by  
reflections, driver oscillations, or other transmission line  
phenomena.  
System Bus  
The System Bus is the microprocessor bus of the processor.  
Setup Window  
The time between the beginning of Setup to Clock (TSU_MIN)  
and the arrival of a valid clock edge. This window may be  
different for each type of bus agent in the system.  
Simultaneous Switching Output  
Simultaneous Switching Output (SSO) effects are differences in  
electrical timing parameters and degradation in signal quality  
caused by multiple signal outputs simultaneously switching  
voltage levels in the opposite direction from a single signal or in  
the same direction. These are called odd mode and even mode  
switching, respectively. This simultaneous switching of multiple  
outputs creates higher current swings that may cause additional  
propagation delay (“push-out”) or a decrease in propagation  
delay (“pull-in”). These SSO effects may impact the setup and/  
or hold times and are not always taken into account by  
simulations. System timing budgets should include margin for  
SSO effects.  
Stub  
The branch from the bus trunk terminating at the pad of an  
agent.  
Trunk  
The main connection, excluding interconnect branches, from  
one end  
System Management Bus  
A two-wire interface through which various system components  
may communicate.  
Undershoot  
(CPU core)  
The minimum voltage extending below VSS observed for a  
signal at the device pad.  
V
V
(CPU core) is the core power for the processor. The system  
CC  
CC  
bus is terminated to V (CPU core).  
CC  
Victim  
A network that receives a coupled crosstalk signal from another  
network is called the victim network.  
Table 1 defines the acronyms used throughout this document.  
Table 1.  
Acronyms (Sheet 1 of 3)  
Acronym  
Definition  
AC  
Audio Codec  
ACPI  
AGTL  
AMC  
ASF  
AMI  
Advanced Configuration and Power Interface  
Assisted Gunning Transceiver Logic  
Audio/Modem Codec.  
Alert Standard Format  
American Megatrends Inc. (BIOS developer)  
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Intel 945GME Express Chipset—About This Manual  
Table 1.  
Acronyms (Sheet 2 of 3)  
Acronym  
Definition  
ATA  
Advanced Technology Attachment (disk drive interface)  
Advance Technology Extended (motherboard form factor)  
ATX  
BGA  
BIOS  
CK-SSCD  
CMC  
CMOS  
CPU  
DDR  
DMI  
ECC  
EEPROM  
EHCI  
EMA  
EMI  
Ball Grid Array  
Built-In Self Test  
Spread Spectrum Differential Clock  
Common Mode Choke  
Configuration Memory Operating System  
Central Processing Unit (processor)  
Double Data Rate  
Direct Memory Interface  
Error Correcting Code  
Electrically Erasable Programmable Read-Only Memory  
Enhanced Host Controller Interface  
Extended Media Access  
Electro Magnetic Interference  
Electrostatic Discharge  
ESD  
EV  
Engineering Validation  
EVMC  
FIFO  
FS  
Electrical Validation Margining Card  
First In First Out - describes a type of buffer  
Full-speed. Refers to USB  
Front Side Bus  
FSB  
FWH  
GMCH  
HS  
Firmware Hub  
Graphics Memory Controller Hub  
High-speed. Refers to USB  
I/O Controller Hub  
ICH  
IDE  
Integrated Drive Electronics  
Intel Mobile Voltage Positioning  
Internet Protocol/Internet Protocol version 6  
Infrared Data Association  
Inter-Symbol Interference  
Keyboard Controller  
IMVP  
IP/IPv6  
IrDA  
ISI  
KBC  
LAI  
Logic Analyzer Interface  
Local Area Network  
LAN  
LED  
Light Emitting Diode  
LOM  
LPC  
LAN on Motherboard  
Low Pin Count  
LS  
Low-speed. Refers to USB  
Low Voltage Differential Signalling  
Modem Codec  
LVDS  
MC  
MEC  
Media Expansion Card  
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Table 1.  
Acronyms (Sheet 3 of 3)  
Acronym  
Definition  
MHz  
OEM  
PCIe  
PCM  
POST  
PLC  
Mega-Hertz  
Original Equipment Manufacturer  
PCI Express*  
Pulse Code Modulation  
Power On Self Test  
Platform LAN Connect  
RAID  
RTC  
Redundant Array of Inexpensive Disks  
Real Time Clock  
SATA  
SIO  
Serial ATA  
Super Input/Output  
SMBus  
SODIMM  
SPD  
System Management Bus  
Small Outline Dual In-line Memory Module  
Serial Presence Detect  
Serial Peripheral Interface  
Simultaneous Switching Output  
Suspend To RAM  
SPI  
SSO  
STR  
TCO  
Total Cost of Ownership  
Transmission Control Protocol  
Time Division Multiplexed  
Time Domain Reflectometry  
Micro Ball Grid Array  
TCP  
TDM  
TDR  
µBGA  
UDP  
UHCI  
USB  
User Datagram Protocol  
Universal Host Controller Interface  
Universal Serial Bus  
VGA  
VID  
Video Graphics Adapter  
Voltage Identification  
VREG  
XDP  
Voltage Regulator  
eXtended Debug Port  
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1.4  
Support Options  
1.4.1  
Electronic Support Systems  
Intel’s web site (http://www.intel.com/) provides up-to-date technical information and  
product support. This information is available 24 hours per day, 7 days per week,  
providing technical information whenever you need it.  
Product documentation is provided online in a variety of web-friendly formats at:  
http://www3.hibbertgroup.com/intel/main  
1.4.2  
Additional Technical Support  
If you require additional technical support, please contact your Intel Representative or  
local distributor.  
1.5  
Product Literature  
You can order product literature from the following Intel literature centers:  
Table 2.  
Intel Literature Centers  
Location  
U.S. and Canada  
Telephone Number  
1-800-548-4725  
U.S. (from overseas)  
Europe (U.K.)  
Germany  
708-296-9333  
44(0)1793-431155  
44(0)1793-421333  
44(0)1793-421777  
81(0)120-47-88-32  
France  
Japan (fax only)  
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®
About This Manual—Intel 945GME Express Chipset  
1.6  
Related Documents  
The table below provides a summary of publicly available documents related to this  
development kit. For additional documentation, please contact your Intel  
Representative.  
Table 3.  
Related Documents  
Document Title  
Location  
http://www.intel.com/design/mobile/datashts/  
309219.htm  
Mobile Intel® 945 Express Chipset Family Datasheet  
http://www.intel.com/design/chipsets/datashts/  
307013.htm  
Intel® I/O Controller Hub 7 (ICH7) Family Datasheet  
Mobile Intel® 945 Express Chipset Family Specification  
Update  
http://www.intel.com/design/mobile/specupdt/  
309220.htm  
Intel® Centrino® Duo Processor Technology Design  
Guide  
1
Order Number 654938  
Note:  
1.  
Contact your Intel representative for access to this document.  
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Intel 945GME Express Chipset—Getting Started  
2.0  
Getting Started  
This chapter identifies the evaluation kit’s key components, features and specifications.  
It also details basic board setup and operation.  
2.1  
Overview  
®
TM  
The evaluation board consists of a baseboard populated with the Intel Core 2 Duo  
®
processor and the Intel 945GME Express Chipset, other system board components,  
and peripheral connectors.  
Note:  
The evaluation board is shipped as an open system allowing for maximum flexibility in  
changing hardware configuration and peripherals. Since the board is not in a protective  
chassis, take extra precaution when handling and operating the system.  
2.1.1  
Intel® 945GME Express Chipset Development Kit  
Features  
Features of the development kit board are summarized below:  
Processor  
®
TM  
• Intel Core 2 Duo processor with 4 MByte L2 Cache on 65nm process in the  
478 pin Flip Chip Pin Grid Array (Micro-FCPGA) package  
®
Mobile Intel 945GME Express Graphics Memory Controller Hub (945GME  
Express GMCH)  
• 1466 pin Micro-FCBGA Package  
• Supports a 533/667 MHz front side bus  
• Supports dual-Channel DDR2 at 400/533/667 MHz  
• Two SODIMM slots (one per channel) support DDR2 SODIMMS (unbuffered, non-  
ECC) modules  
• Supports 128 MBytes to 4 GBytes using 256 Mbit, 512 Mbit, or 1 Gbit technology  
• x16 PCI Express* Graphics or Serial Digital Video Out (SDVO) port  
• 18 bpp LVDS, VGA & TV-D connector support  
I/O Controller Hub 7 (ICH7-M)  
• 652 pin plastic BGA package  
• DMI (x4) interface with GMCH  
• Two SATA and one IDE (40 pin) Hard Drive interface  
• Two PCI 2.3 compliant desktop slots  
• 82802AC8 Firmware Hub (FWH)  
• 82573E Gigabit Ethernet Controller  
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Getting Started—Intel 945GME Express Chipset  
• Two x1 PCI Express* slots.  
Note:  
There are actually three x1 PCI Express* slots but slot 2 was used for validation  
purposes. Only slots 0 and 1 are supported.  
Clocking  
• CK-410M and CK-SSCD  
• Battery-backed real time clock  
Connector Interface Summary  
• One x16 PCI Express* Video Interface, doubles as an MEC connector to provide  
access to dual SDVO ports if PCI Express* is unused  
• Two SATA ports  
• One Ultra ATA (33/66/100) IDE connector supporting up to two IDE devices  
• Eight Universal Serial Bus (USB) 2.0 ports (Five ports provided on rear-panel, three  
provided via headers (J6H2, J7E2)  
• Two PCI 2.3 compliant 33 MHz interface connectors  
• PS/2-style keyboard and PS/2 mouse (6-pin mini-DIN) connectors  
• TV Out D-connector at back panel interface  
• LVDS connector on top of circuit board near GMCH (J5F1)  
• One VGA connector provides access to integrated graphics  
• One LAN connector providing 10/100/1000 Mbps connectivity from the Intel  
82573E Gigabit Ethernet Controller  
• One 9-pin serial port connector.  
• One IrDA port (U4A1)  
• Two PCI Express* slots (x1)  
• Two SODIMM connectors on rear side of circuit board  
Debug Features  
• Extended Debug Port (XDP) connector  
• On-board Port 80h display  
Miscellaneous Features  
• Configurable for ATX 1.1 Power Supply in desktop mode or AC Mobile Brick/Battery  
Pack for Mobile Mode  
• ATX Form Factor eight layer PCB  
• AMI* system BIOS  
• Two built-in fan power connectors: Chassis Fan and CPU Fan  
• Power/Reset buttons  
• CMOS clear jumper  
• BIOS recovery jumper  
• Boot Block protection jumper  
• Support for Serial, IrDA, serial mouse, and keyboard  
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Intel 945GME Express Chipset—Getting Started  
2.2  
Included Hardware and Documentation  
The following hardware and documentation is included in the development kit:  
®
• One Intel 945GME Express Chipset Development Kit board  
®
TM  
• One Intel Core 2 Duo processor with 4 MB L2 Cache on 65nm process in the  
478 pin Flip-Chip Pin Grid Array (Micro-FCPGA) package (Installed)  
®
TM  
• One Intel Core Duo processor with 2 MByte L2 Cache on 65 nm process in the  
478 pin Flip Chip Pin Grid Array (Micro-FCPGA) package (included in kit box for  
evaluation– not populated on board)  
• One Firmware Hub (FWH) (Installed)  
• One GMCH (945GME) heat sink (Installed)  
• One Type 2032, socketed 3 V lithium coin cell battery (Installed)  
• One DDR2 SODIMM (200 Pin)  
• One CPU thermal solution and CPU back plate (included in kit box – not populated  
on board)  
• One hard drive  
• One cable kit  
2.3  
Software Key Features  
The driver CD included in the kit contains all of the software drivers necessary for basic  
system functionality under the following operating systems: Windows* 2000/XP/XP  
Embedded, and Linux*.  
Note:  
While every care was taken to ensure the latest versions of drivers were provided on  
the enclosed CD at time of publication, newer revisions may be available. Updated  
drivers for Intel components can be found at: http://developer.intel.com/design/  
intarch/software/index.htm  
For all third-party components, please contact the appropriate vendor for updated  
drivers.  
Note:  
Software in the kit is provided free by the vendor and is only licensed for evaluation  
purposes. Refer to the documentation in your evaluation kit for further details on any  
terms and conditions that may be applicable to the granted licenses. Customers using  
the tools that work with Microsoft* products must license those products. Any targets  
created by those tools should also have appropriate licenses. Software included in the  
kit is subject to change.  
Refer to http://developer.intel.com/design/intarch/devkits for details on additional  
software from other third-party vendors.  
2.3.1  
AMI* BIOS  
This development kit ships pre-installed with AMI* BIOS pre-boot firmware from AMI*.  
AMI* BIOS provides an industry-standard BIOS platform to run most standard  
operating systems, including Windows* 2000/XP/XP Embedded, Linux*, and others.  
The AMI* BIOS Application Kit (available through AMI*) includes complete source code,  
a reference manual, and a Windows-based expert system, BIOStart*, to enable easy  
®
and rapid configuration of customized firmware for your Intel 945GME Express  
Chipset.  
®
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Getting Started—Intel 945GME Express Chipset  
®
The following features of AMI* BIOS are enabled in the Intel 945GME Express  
Chipset:  
• DDR2 SDRAM detection, configuration, and initialization  
®
• Intel 945GME Express Chipset configuration  
• POST codes displayed to port 80h  
• PCI/PCI Express* device enumeration and configuration  
• Integrated video configuration and initialization  
• Super I/O configuration  
• CPU microcode update  
• Active Management Technology  
• RAID 0/1 Support  
2.4  
Before You Begin  
Additional hardware may be necessary to successfully set up and operate the  
evaluation board.  
VGA Monitor: Any standard VGA or multi-resolution monitor may be used. The setup  
instructions in this chapter assume the use of a standard VGA monitor, TV, or flat panel  
monitor.  
Keyboard: The evaluation board can support either a PS/2 or USB style keyboard.  
Mouse: The evaluation board can support either a PS/2 or USB style mouse.  
Hard Drives and Optical Disc Drives: Up to two SATA drives and two IDE devices  
(master and slave) may be connected to the evaluation board. An optical disc drive  
may be used to load the OS. All these storage devices may be attached to the board  
simultaneously.  
Video Adapter: Integrated video is provided on the back panel of the evaluation  
board. Alternately, a standard PCI Express* video adapter or an MEC video adapter  
may be used for additional display flexibility. Please contact the respective vendors for  
drivers and necessary software for adapters not provided with this development kit.  
Check the BIOS for the proper video settings. See Section 2.6, “Configuring the BIOS”  
on page 21 for more information.  
Note:  
The enclosed driver CD includes drivers necessary for LAN, Integrated graphics, and  
system INF utilities.  
Network Adapter: A Gigabit network interface is provided on the evaluation board.  
The network interface will not be operational until after all the necessary drivers have  
been installed. A standard PCI/PCI Express* adapter may be used in conjunction with,  
or in place of, the onboard network adapter. Please contact the respective vendors for  
drivers and necessary software for adapters not provided with this development kit.  
You must supply appropriate network cables to utilize the LAN connector or any other  
installed network cards.  
®
Power Supply: The Intel 945GME Express Chipset has the option to be powered  
®
from two different power sources: an ATX power supply, or ‘Mobile Brick’. The Intel  
945GME Express Chipset contains all of the voltage regulators necessary to power  
the system.  
®
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Intel 945GME Express Chipset—Getting Started  
There are two main supported power supply configurations, Desktop and Mobile. The  
Desktop solution consists of only using the ATX power supply. The Mobile solution  
consists of only using the AC Brick.  
Note:  
Desktop peripherals, including add-in cards, will not work in mobile power mode. If  
desktop peripherals are used, the platform must be powered using desktop power  
mode. The AC Brick power supply configuration does not provide the 12 V supply  
required by most desktop peripherals.  
Note:  
Note:  
Select a power supply that complies with the "ATX12V" 1.1 specification. For more  
information, refer to http://www.formfactors.org.  
If the power button on the ATX power supply is used to shut down the system, wait at  
least five seconds before turning the system on again to avoid damaging the system.  
Other Devices and Adapters: The evaluation board functions much like a standard  
desktop computer motherboard. Most PC-compatible peripherals can be attached and  
configured to work with the evaluation board.  
2.5  
Setting Up the Evaluation Board  
Once the necessary hardware (described in Section 2.4) has been gathered, follow the  
®
steps below to set up the Intel 945GME Express Chipset evaluation board.  
Note:  
To locate items discussed in the procedure below, please refer to Section 4.0.  
1. Create a safe work environment.  
Ensure a static-free work environment before removing any components from their  
anti-static packaging. The evaluation board is susceptible to electrostatic discharge  
(ESD) damage, and such damage may cause product failure or unpredictable  
operation. A flame retardant work surface must also be used.  
Caution:  
Caution:  
Because of this susceptibility, it is recommended that an ESD wrist strap be  
used when handling the board.  
2. Inspect the contents of your kit.  
Check for damage that may have occurred during shipment. Contact your sales  
representative if any items are missing or damaged.  
Since the board is not in a protective chassis, use caution when connecting  
cables to this product.  
Caution:  
Standby voltage is constantly applied to the board. Therefore, do not insert or  
remove any hardware unless the system is unplugged.  
Note:  
The evaluation board is a standard ATX form factor. An ATX chassis may be used if a  
protected environment is desired. If a chassis is not used, standoffs must be used to  
elevate the board off the working surface to protect the memory and to protect from  
any accidental contact to metal objects.  
3. Check the jumper default position setting. Refer to Figure 4 for jumper location.  
Jumper J6H1 is used to clear the CMOS memory. Make sure this jumper is set for  
normal operation.  
4. Be sure to populate the following hardware on your evaluation board:  
®
TM  
— One Intel Core 2 Duo processor  
— One processor thermal solution  
— One DDR2 SODIMM (200-pin)  
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Getting Started—Intel 945GME Express Chipset  
Note:  
Note:  
Ensure that the processor has been locked into the socket by turning the socket screw  
fully clockwise.  
For proper installation of the CPU thermal solution, please refer to Appendix A, “Heat  
Sink Installation Instructions”  
5. Connect a SATA or IDE hard disk drive.  
6. Connect any additional storage devices to the evaluation board.  
7. Connect the keyboard and mouse.  
Connect a PS/2-style or USB mouse and keyboard (see Figure 3 on page 38 for  
connector locations).  
Note:  
J1A1 (on the baseboard) is a stacked PS/2 connector. The bottom connector is for the  
keyboard and the top is for the mouse.  
8. Connect an Ethernet cable (optional).  
9. Connect the monitor through the VGA connector.  
10.Connect the power supply.  
Connect an appropriate power supply to the evaluation board. Make sure the power  
supply is not plugged into an electrical outlet (turned off). After connecting the  
power supply board connectors, plug the power supply cord into an electrical  
outlet.  
11.Power up the board.  
Power and Reset are implemented on the evaluation board through buttons located  
on SW1C1and SW1C2, respectively. See Figure 5 on page 42 for switch locations.  
Turn on the power to the monitor and evaluation board. Ensure that the fansink on  
the processor is operating.  
Note:  
Note that the power button may have to be pressed twice to turn the power on.  
12.Install operating system and necessary drivers  
Depending on the operating system chosen, all necessary drivers for components  
included in this development kit can be found on the enclosed CD. Please see  
Section 2.3 for information on obtaining updated drivers.  
2.6  
Configuring the BIOS  
AMI* BIOS is pre-loaded on the evaluation board. The default BIOS settings may need  
to be modified to enable/disable various features of the evaluation board. The setup  
program can be used to modify BIOS settings and can be accessed during the Power On  
Self Test (POST). Setup options are configured through a menu-driven user interface.  
For AMI BIOS POST codes, visit:  
http://www.ami.com  
For BIOS Updates please contact your Intel Sales Representative.  
®
TM  
®
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2 Duo processor with the Mobile Intel 945GME Express Chipset  
May 2007  
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®
Intel 945GME Express Chipset—Theory of Operation  
3.0  
Theory of Operation  
3.1  
Block Diagram  
®
Figure 1.  
Intel 945GME Express Chipset Development Kit Block Diagram  
CK-410M  
Clocking  
Intel® CoreTM 2 Duo  
Thermal  
Sensor  
XDP  
processor  
CK-SSCD  
Clocking  
LVDS/  
ALS/BLI  
LVDS  
VGA  
IMVP 6  
VR  
FSB  
533/667 MHz  
CRT  
TVO  
DDR VR  
Mobile Intel®  
945GME Express  
Chipset  
Dual Channel DDR2  
400/533/667 MHz  
TVOUT  
(GMCH)  
PCI Express / SDVO  
PCIE GFX  
945GME  
VREG  
USB 2.0  
7 USB Conn  
PCI 2.3  
1 Docking Conn  
x4 DMI  
IDE  
40 Pin Conn  
SATA Port 2  
SATA Port 0  
Intel® 82801GHM  
(ICH 7-M)  
Cable Connect  
Direct Connect  
PCIE Slot 0  
PCIE Slot 1  
Serial, IrDA/  
CIR  
LAN  
(82573E)  
PCIe  
LPC  
SIO  
2 - PS/2  
Scan Matrix  
AON  
Port 80h  
Decoder  
LPC  
Slot  
SMC/KBC  
FWH  
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Theory of Operation—Intel 945GME Express Chipset  
3.2  
3.3  
Mechanical Form Factor  
The evaluation board conforms to the ATX form factor. For extra protection in a  
development environment, you may want to install the evaluation board in an ATX  
chassis. Internal and rear panel system I/O connectors are described in Section 3.4.3.  
An overview of connector and slot locations is provided in Section 4.0.  
Thermal Management  
The objective of thermal management is to ensure that the temperature of each  
component is maintained within specified functional limits. The functional temperature  
limit is the range within which the electrical circuits can be expected to meet their  
specified performance requirements. Operation outside the functional limit can degrade  
system performance and cause reliability problems.  
The development kit is shipped with a fansink thermal solution for installation on the  
processor. This thermal solution has been tested in an open-air environment at room  
temperature and is sufficient for evaluation purposes. The designer must ensure that  
adequate thermal management is provided for any customer-derived designs.  
3.4  
System Features and Operation  
The following sections provide a detailed view of system features and operation. Refer  
to Figure 2 and Table 7 for the location of the major components of the platform.  
®
The Intel 945GME Express Chipset features the 82945GM Graphics Memory Controller  
®
Hub and the Intel I/O Controller Hub (ICH7-M).  
3.4.1  
Intel(R) 945GME GMCH  
®
The Intel 945GME Express Chipset GMCH provides the processor interface optimized  
®
TM  
for Intel Core 2 Duo processors, system memory interface, DMI and internal  
graphics. It provides flexibility and scalability in graphics and memory subsystem  
performance. The following list describes the reference board’s implementation of the  
®
Intel 945GME Express Chipset GMCH features.  
A list of features follows:  
• 1466 Micro-FCBGA package  
• 533/667 MHz Front Side Bus  
• 36-bit host bus addressing  
• System memory controller (DDR2 implemented)  
— Supports Dual Channel and Single Channel operation  
— Two 200-pin SODIMM slots  
— DDR2 400/533/667  
• Direct Media Interface (DMI)  
• Integrated graphics based on Intel’s Graphics Media Accelerator 950  
— Directly supports on-board VGA, S-Video and LVDS interfaces.  
— Supports resolutions up to 2048 x 1536 @ 75 Hz.  
• SDVO interface via PCI Express* x16 connector provides maximum display  
flexibility  
— Can drive up to two display outputs  
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Intel 945GME Express Chipset—Theory of Operation  
3.4.1.1  
System Memory  
The evaluation board supports DDR2 400/533/667 main memory. Two 200-pin  
SODIMM connectors (one per channel) on the board support unbuffered, non-ECC,  
single and double-sided DDR2 400/533/667 MHz SODIMMs. These SODIMMs provide  
the ability to use up to 1 Gbit technology for a maximum of 4 GBytes system memory.  
®
Note:  
Memory that utilizes 128 MBit technology is not supported on the Intel 945GME  
Express Chipset.  
Note:  
The SODIMM connectors are on the back side of the board.  
Caution:  
Standby voltage is applied to the SODIMM sockets when the system is in the S3 state.  
Therefore, do not insert or remove SODIMMs unless the system is unplugged.  
3.4.1.2  
3.4.1.3  
DMI  
®
The Intel 945GME Express Chipset GMCH’s Direct Media Interface (DMI) provides  
high-speed bi-directional chip-to-chip interconnect for communication with the ICH7-M.  
Advanced Graphics and Display Interface  
The reference board has five options for displaying video, VGA, LVDS, TVOUT, SDVO, or  
PCI Express* Graphics. SDVO (MEC) and PCI Express* Graphics are multiplexed on the  
®
®
same pins within the Intel 945GME Express Chipset. The Intel 945GME Express  
Chipset contains one SDVO/PCI Express* Graphics Slot (J6C1) for a PCI Express*  
compatible graphics card or an SDVO compatible graphics card, one LVDS connector  
(J5F1), one TVOUT connector (J2A1), and one 15-pin VGA connector (J2A2B).  
3.4.2  
ICH7-M  
The ICH7-M is a highly integrated multifunctional I/O controller hub that provides the  
interface to the system peripherals and integrates many of the functions needed in  
today’s PC platforms. The following sections describe the reference board  
implementation of the ICH7-M features, which are listed below:  
• Two PCI Express* (x1) connectors  
• Two PCI connectors  
• LPC interface  
• System management  
• ACPI* 2.0 compliant  
• Real Time Clock  
• 652 mBGA package  
• Two SATA drive connectors  
• One IDE connector  
• Eight Universal Serial Bus (USB) 2.0 ports (five ports provided on rear-panel, three  
provided via headers (J6H2, J7E2)  
3.4.2.1  
PCI Express* Slots  
The reference board has two x1 PCI Express* slots for add-in cards. The PCI Express*  
interface is compliant to the PCI Express* Rev. 1.0a Specification.  
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Theory of Operation—Intel 945GME Express Chipset  
3.4.2.2  
3.4.2.3  
PCI Slots  
The reference board has two PCI slots for add-in cards. The PCI bus is compliant to the  
PCI Rev. 2.3 Specification at 33 MHz.  
On-Board LAN  
The 82573E provides the LAN connectivity for this platform. It provides Gigabit  
ethernet as well as Intel® Active Management Technology functions. It is connected to  
the ICH7-M through a PCIe interface and to an RJ45 connector at J5A1A with built in  
magnetic decoupling. Access to this interface is provided on the rear I/O panel (See  
Figure 3 on page 38).  
Features of the 82573E are as follows:  
• x1 PCIe Interface  
• 2 Gbps peak bandwidth per direction  
• Wide, pipelined internal data path architecture  
• 32 KB configurable Receive (Rx) and Transmit (Tx) FIFO  
• IEEE 802.3x compliant flow control support with software controllable pause times  
and threshold values  
• Programmable host memory Rx buffers (256 B- 16 KB)  
• Descriptor ring management hardware for Tx and Rx  
• Tx/Rx IP, TCP, and UDP checksum offloading  
• Tx TCP Segmentation  
• IPv6 offloading  
• Intel® Active Management Technology  
• Wake on LAN (WoL) support  
Note:  
The 82573E is only powered in S3-S0 and will not support AMT or WoL support from S4  
or S5.  
• SPI or EEPROM support  
• Optional on-die voltage regulator  
Information on Intel® Active Management Technology can be found at:  
http://www.intel.com/technology/manage/iamt/  
3.4.2.4  
3.4.2.5  
AC’97 and High Definition Audio  
®
AC’97 and Intel High Definition Audio are not supported on the board.  
ATA / Storage  
®
The Intel 945GME Express Chipset provides one parallel ATA IDE connector and two  
serial ATA connectors. The parallel ATA IDE Connector is a standard 40-pin connector at  
J7J1 for a desktop IDE drive. A power connector is supplied on the platform to power a  
®
parallel ATA hard disk drive at J4J2. One of the two serial ATA connectors on the Intel  
945GME Express Chipset is a direct connect connector; located at J8J2. The other serial  
ATA connector is broken up into two connectors. One connector is for the serial data  
signals, and the other is to power the serial ATA hard disk drive. These connectors are  
located at J7H1 and J6H3. A green LED at location CR7J1 indicates activity on the ATA  
channel.  
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Intel 945GME Express Chipset—Theory of Operation  
®
The Intel 945GME Express Chipset also supports ‘ATA swap’ capability for both the  
parallel IDE channel and the serial ATA channels. A device can be powered down by  
software and the port can then be disabled, allowing removal and insertion of a new  
device. The parallel IDE device should be powered from the power connector, J4J2, on  
®
the Intel 945GME Express Chipset to utilize the hot swap feature. This feature  
requires customer-developed software support.  
Desktop hard drives must be powered using the external ATX power supply, not the  
onboard power supply.  
®
The Intel 945GME Express Chipset includes Intel® Matrix Storage Technology,  
providing greater performance and reliability through features such as Native  
Command Queuing (NCQ) and RAID 0/1. For more information about Intel® Matrix  
Storage Technology, refer to Intel’s website at:  
http://www.intel.com/design/chipsets/matrixstorage_sb.htm  
3.4.2.6  
3.4.2.7  
USB Connectors  
The ICH7-M provides a total of eight USB 2.0 ports. Three ports are routed to a triple-  
stack USB connector at J3A1. Two ports are routed to a combination RJ-45/dual USB  
connector at J5A1B. Three ports are routed to USB front panel headers at J6H2 and  
J7E2.  
LPC Super I/O (SIO)/LPC Slot  
®
An SMSC LPC47N207 serves as the SIO on the Intel 945GME Express Chipset  
platform. Shunting the jumper at J7E3 to the 2-3 positions can disable the SIO by  
holding it in reset. This allows other SIO solutions to be tested in the LPC slot at J8F1.  
A sideband header is provided at J9G2 for this purpose. This sideband header also has  
signals for LPC power management. Information on this header is on sheet 35 of the  
®
Intel 945GME Express Chipset schematics and is detailed in the “LPC Slot and  
Sideband Header Specification” (refer to Table 3, “Related Documents” on page 15).  
3.4.2.8  
3.4.2.9  
3.4.2.10  
Serial, IrDA  
The SMSC SIO incorporates a serial port, and IrDA (Infrared), as well as general  
purpose IOs (GPIO). The serial port connector is provided at J2A2A, and the IrDA  
transceiver is located at U4A1. The IrDA transceiver on Intel 945GME Express Chipset  
supports both SIR (slow IR) and CIR (Consumer IR). The option to select between the  
two is supported through software and GPIO pin on the SIO.  
®
BIOS Firmware Hub (FWH)  
®
The 8 Mbit Flash device used on the Intel 945GME Express Chipset to store system  
and video BIOS as well as an Intel Random Number Generator (RNG) is a socketed  
E82802AC8 a 32-pin PLCC package. The reference designator location of the FWH  
device is U8G1. The BIOS can be upgraded using an MS-DOS* based utility and is  
addressable on the LPC bus off of the ICH7-M.  
System Management Controller (SMC)/Keyboard Controller  
The Hitachi* H8S/2104V serves as both SMC and KBC for the platform. The SMC/KBC  
controller supports two PS/2 ports, battery monitoring and charging, EMA support,  
wake/runtime SCI events, and power sequencing control. The two PS/2 ports on the  
®
Intel 945GME Express Chipset are for legacy keyboard and mouse. The keyboard  
plugs into the bottom jack and the mouse plugs into the top jack at J1A1. Scan matrix  
keyboards can be supported via an optional connector at J9E1.  
®
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Theory of Operation—Intel 945GME Express Chipset  
3.4.2.11  
Clocks  
®
The Intel 945GME Express Chipset board uses a CK-410M and CK-SSCD compatible  
solution. The CK-SSCD solution offers improved EMI performance by spreading the  
radiated clock emissions over a wider spectrum than a single frequency. This is  
accomplished while controlling the clock frequency deviation such that system  
performance is not compromised. The FSB frequency is determined from decoding the  
processor BSEL[2:0] pin settings.  
3.4.2.12  
3.4.2.13  
Real Time Clock  
An on-board battery at BT5H1 maintains power to the real time clock (RTC) when in a  
®
mechanical off state. A CR2032 battery is installed on the Intel 945GME Express  
Chipset development kit.  
Thermal Monitoring  
The processor has a thermal diode for temperature monitoring. The SMC thermal  
monitoring device will throttle the processor if it becomes hot. If the temperature of the  
processor rises too high, the SMC will alternately blink the CAPS lock and NUM lock  
LEDs on the board, and the board will shut down.  
3.4.3  
System I/O and Connector Summary  
The evaluation board provides extensive I/O capability in the form of internal  
connectors and headers as detailed by the following list. For detailed information on  
these connectors and headers, please refer to “Hardware Reference” on page 35.  
• One (x16) PCI Express* connector  
• Two (x1) PCI Express* connectors  
• Two PCI connectors  
• One IDE connector (supports two drives)  
• Two SATA connectors  
• Two USB ports via front panel header (J8J1)  
• One LVDS video connector  
®
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Intel 945GME Express Chipset—Theory of Operation  
In addition to the internal I/O connections listed above, the evaluation board also  
contains the following I/O on the rear panel (as illustrated in Figure 3 on page 38).  
• Five USB ports on back panel.  
• VGA connector  
• PS/2-style keyboard and mouse ports  
• LAN connector  
• One 9-pin serial connector  
• One IrDA port  
• One TV D-connector  
3.4.3.1  
3.4.3.2  
PCI Express* Support  
The evaluation board provides access to one x16 PCI Express* connector. Any industry  
standard x16 PCI Express* video adapter may be used with this interface. The  
evaluation board also provides access to two x1 PCI Express* connectors. Any industry  
standard x1 PCI Express* adapter may be used with these interfaces.  
SATA Support  
The evaluation board provides support for up to two SATA disk drives. The SATA  
controllers are software compatible with IDE interfaces, while providing lower pin  
counts and higher performance.  
These are two SATA connectors on the evaluation board. The SATA Cable connect  
provides both signalling and power white the SATA Direct connect only provides signals  
(the user typically uses an ATX power supply for the drive power).  
3.4.3.3  
IDE Support  
The evaluation board has a 40-pin connector for the ICH7-M’s integrated IDE controller.  
This connector supports up to two Ultra ATA/100 hard drives; one master and one  
slave.  
Note:  
Desktop hard drives must be powered by an external ATX power supply.  
3.4.3.4  
USB Ports  
The evaluation board provides five USB (2.0) ports on the rear panel and three  
additional ports through headers (J6H2 and J7E2).  
There are four UHCI Host Controllers and an EHCI Host Controller. Each UHCI Host  
Controller includes a root hub with two separate USB ports each, for a total of eight  
legacy USB ports.  
The EHCI Host Controller includes a root hub that supports up to eight USB 2.0 ports.  
The connection to either the UHCI or EHCI controllers is dynamic and dependant on the  
particular USB device. As such, all ports support High Speed, Full Speed, and Low  
Speed (HS/FS/LS).  
3.4.3.5  
VGA Connector  
A standard 15 pin D-Sub connector on the rear panel provides access to the analog  
®
output of the Intel 945GME Express Chipset. The integrated graphics supports a  
maximum resolution of 2048 x 1536 @ 75Hz. This can be connected to any capable  
analog CRT or flat panel display with analog input.  
®
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Theory of Operation—Intel 945GME Express Chipset  
When used in conjunction with the other display options, the displays can operate in  
Dual Independent mode. This allows unique content to appear on each display at  
unique refresh rates and timings.  
3.4.3.6  
Keyboard/Mouse  
The keyboard and mouse connectors are PS/2 style, six-pin stacked miniature D-Sub  
connectors. The top connector is for the mouse and the bottom connector is for the  
keyboard.  
3.4.3.7  
3.4.3.8  
3.4.3.9  
32 bit/33 MHz PCI Connectors  
Two industry standard 32 bit/33 MHz PCI connectors are provided on the evaluation  
board. These slots support 5 V devices.  
Ethernet Gigabit LAN Interface connector  
The evaluation board provides one industry standard Gigabit RJ45 LAN Interface  
Connector (Integrated with the dual USB connector).  
LVDS Flat Panel Display Interface  
The evaluation board provides one forty-four pin LVDS video interface connector. The  
provided LVDS connects to most 18 bits per pixel (bpp) flat panel display assemblies.  
24 bpp LVDS is not supported.  
3.4.4  
3.5  
POST Code Debugger  
A port 80-83 display at CR6A1, CR6A2, CR6A3, and CR6A4 show the POST codes and  
can be used for debug information during POST. The evaluation board uses an AMI*  
BIOS.  
For AMI* BIOS POST codes, please visit: http://www.ami.com  
Clock Generation  
®
The Intel 945GME Express Chipset board uses a CK-410M and CK-SSCD compatible  
solution. The FSB frequency is determined from decoding the processor BSEL[2:0] pin  
settings.  
The clock generator provides Processor, GMCH, ICH7-M, PCI, PCI Express*, SATA, and  
USB reference clocks. Clocking for DDR2 is provided by the GMCH.  
Table 4.  
Primary System Clocks  
Clock Name  
Speed  
133 MHz @ 533 FSB Speed  
166 MHz @ 667 FSB Speed  
CPU  
100 MHz @ 400 Memory Speed  
133 MHz @ 533 Memory Speed  
166 MHz @ 667 Memory Speed  
DDR2  
PCI Express* and DMI  
100 MHz  
100 MHz  
33 MHz  
48 MHz  
SATA  
PCI  
USB  
®
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Intel 945GME Express Chipset—Theory of Operation  
3.6  
Power Management States  
The evaluation board supports the following ACPI System states: S0 (Full On), S3  
(Suspend to RAM), S4 (Suspend to disk), and S5 (Soft-off), ACPI CPU states: C0 (Full  
On), C1 (Auto Halt), C2 (Stop Grant), C3 (Deep Sleep), and C4 (Deeper Sleep), and  
ACPI Global Power States: G0 (Working), G1 (Sleeping), G2 (Soft Off), and G3  
(Mechanical Off). Transition requirements are detailed below.  
®
Table 5 lists the power management states that have been identified for the Intel  
945GME Express Chipset Platform.  
®
Table 5.  
Intel 945GME Express Chipset Development Kit Power Management States  
State  
G0/S0/C0  
Description  
Full On  
G0/S0/C2  
G0/S0/C3  
G0/S0/C4  
G1/S3  
STPCLK# signal active  
Deep Sleep: DPSLP# signal active  
Deeper Sleep: DPRSLP# signal active  
Suspend to RAM  
G1/S4  
Suspend to Disk  
G2/S5  
Soft Off  
G3  
Mechanical Off  
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Theory of Operation—Intel 945GME Express Chipset  
3.6.1  
Transition to S3  
If enabled, the transition to S3 from the full-on state can be accomplished in the  
following ways:  
• The OS performs the transition through software.  
• Press the front panel power button for less than four seconds (assuming the OS  
power management support has been enabled).  
Note:  
The power button is accessed by adding a switch to the pins 5 and 6 on the front panel  
header J8J1.  
3.6.2  
Transition to S4  
“Wake on S4” (Suspend to disk) is controlled by the operating system.  
3.6.3  
3.6.4  
Transition to S5  
The transition to S5 is accomplished by the following means:  
• Press the front panel power button for less than four seconds (if enabled through  
the OS).  
• Press the front panel power button for more than four seconds to activate power  
button override.  
Transition to Full-On  
The transition to the Full-On state can be from S3 or S5. The transition from S3 is a low  
latency transition that is triggered by one of the following wake events:  
• Power management timer expiration  
• Real Time Clock (RTC) triggered alarm  
• Power button activation  
• USB device interrupt  
• ICH7M pin PME# assertion  
• AC power loss  
For AC power loss, the system operation is defined by register settings in the Intel  
ICH7-M. Upon the return of power, a BIOS option, set prior to the power loss, allows  
the system to either go immediately to the S5 state, or reboot to the Full-On state, no  
matter what the state was before the power loss. External logic for this functionality is  
not necessary. If the BIOS remains in the S5 state after AC power loss, only the power  
button or the RTC alarm can bring the system out of the S5 state. The status of enabled  
wake events will be lost.  
3.7  
Power Measurement Support  
Power measurement resistors are provided on the platform to measure the power of  
most subsystems. All power measurement resistors have a tolerance of 1%. The value  
of these power measurement resistors are 2 mΩ by default. Power on a particular  
subsystem is calculated using the following formula:  
V2  
P =  
R
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Intel 945GME Express Chipset—Theory of Operation  
R is the value of the sense resistor (typically 0.002 Ω)  
V is the voltage measured across the sense resistor.  
It is recommended that the user use an oscilloscope or high precision digital multi-  
meter tool such as the Agilent* 34401A digital multi-meter. Such a meter has 6½ digits  
of accuracy and can provide a much greater accuracy in power measurement than a  
common 3½ digit multimeter.  
Table 6 summarizes the voltage rails and power measurement sense resistors located  
®
on the Intel 945GME Express Chipset platform. All sense resistors are 0.002 Ω unless  
otherwise noted. Please note that many voltage rails do not have sense resistors.  
®
Table 6.  
Intel 945GME Express Chipset Development Kit Voltage Rails (Sheet 1 of 3)  
Powered during  
System States  
Voltage Groups  
Voltage Rail  
Sense Resistor  
0.9V  
+V0.9  
R4N4  
S0,S3  
1.05V Switched  
1.2V  
+V1.05S  
R4V4  
R8A2  
S0  
+V1.2_LAN  
S0,S3  
1.5V Always  
+V1.5A_AZ_IO  
+V1.5A_PWRGD  
+V1.5S  
S0,S3,S4,S5  
S0,S3,S4,S5  
1.5V Switched  
R5F4  
R6D8  
R6D6  
S0  
S0  
S0  
S0  
S0  
S0  
S0  
S0  
S0  
+V1.5S_3GPLL  
+V1.5S_AUX  
+V1.5S_DPLLA  
+V1.5S_DPLLB  
+V1.5S_HPLL  
+V1.5S_MPLL  
+V1.5S_PCIE  
+V1.5S_PCIE_ICH  
R5E2  
R5F3  
+V1.5S_QTVDAC and  
+V1.5S_TVDAC  
S0  
1.8V  
2.5V  
+V1.8  
R5N2  
R7M2  
S0,S3  
+V2.5_LAN  
S0,S3  
+VLAN_2.5-3.3  
+V2.5S  
S0,S3  
2.5V Switched  
S0  
+V2.5S_CRTDAC  
+V2.5S_PWRGD  
+V3.3  
S0  
S0  
3.3V  
S0,S3  
3.3V Always  
+V3.3A  
S0,S3,S4,S5  
S0,S3,S4,S5  
S0,S3,S4,S5  
S0,S3,S4,S5  
S0  
+V3.3A/1.5A_AZ_IO  
+V3.3A_MBL  
+V3.3A_RTC  
+V3.3S  
3.3V Switched  
+V3.3_PCISLT3  
+V3.3S/1.5S_AZ_IO  
+V3.3S_DB800_VDDA  
R9B3  
R8F8  
S0  
S0  
S0  
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Theory of Operation—Intel 945GME Express Chipset  
®
Table 6.  
Intel 945GME Express Chipset Development Kit Voltage Rails (Sheet 2 of 3)  
Powered during  
System States  
Voltage Groups  
Voltage Rail  
Sense Resistor  
R6C2  
+V3.3S_PEG  
S0  
+V3.3S_PWRGD  
+V3.3S_SATA_P0  
+V3.3S_SATA_P2  
+V3.3S_TVDAC  
+V3.3S_TVDAC_LDO  
+V3.3S_TVDACA  
+V3.3S_TVDACB  
+V3.3S_TVDACC  
+VCCA_TVDAC  
+V5  
S0  
S0  
S0  
S0  
R4F2  
S0  
S0  
S0  
S0  
S0  
5V  
S0,S3  
5V Always  
+V5A  
S0,S3,S4,S5  
+V5A_MBL  
R3V4  
R8B5  
R1B2  
S0,S3,S4,S5  
5V Switched  
+V5S  
S0  
+V5_PCISLT3  
+V5S_F_DAC  
+V5S_IMVP6  
+V5S_L_DAC  
+V5S_PATA  
+V5S_PWRGD  
+V5S_SATA_P0  
+V5S_SATA_P2  
+V5SB_ATXA  
V5S_FAN  
S0  
S0  
S0  
S0  
S0  
S0  
S0  
S0  
S0  
S0  
-12V Always  
-V12A  
S0,S3,S4,S5  
S0  
-12V Switched  
+12V SWITCHED  
-V12S  
+V12S  
S0  
+V12S_PATA  
+V12S_PEG  
+V12S_SATA_P0  
+V12S_SATA_P2  
+V_BC_OUT  
+VAC_IN  
S0  
R6N6  
S0  
S0  
S0  
AC Power Brick  
S0,S3,S4,S5  
S0,S3,S4,S5  
S0,S3,S4,S5  
S0,S3,S4,S5  
S0,S3,S4,S5  
S0,S3,S4,S5  
S0,S3,S4,S5  
S0,S3,S4,S5  
+VAC_IN_L  
+VCHGR_OUT  
+VBAT  
Battery Voltage  
+VBAT_S4  
+VDC_PHASE  
+VBATA  
R1B3  
Battery Voltage Always  
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Intel 945GME Express Chipset—Theory of Operation  
®
Table 6.  
Intel 945GME Express Chipset Development Kit Voltage Rails (Sheet 3 of 3)  
Powered during  
System States  
Voltage Groups  
Voltage Rail  
Sense Resistor  
Battery Voltage Switched +VBATS  
+VBS  
S0  
S0  
S0  
Processor Core  
+VCC_CORE  
®
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Hardware Reference—Intel 945GME Express Chipset  
4.0  
Hardware Reference  
This section provides reference information on the hardware, including locations of  
evaluation board components, connector pinout information and jumper settings.  
Figure 2 provides an overview of basic board layout.  
4.1  
Primary Features  
®
Figure 2 shows the major components of the Intel 945GME Express Chipset board and  
Table 7 gives a brief description of each component.  
®
Figure 2.  
Intel 945GME Express Chipset Component Locations  
®
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Intel 945GME Express Chipset—Hardware Reference  
®
Table 7.  
Intel 945GME Express Chipset Component Location Legend (Sheet 1 of 2)  
Reference  
Designator  
No.  
Default Setting  
1
Reserved  
PCI Express* Slot 0  
PCI Express* Slot 1  
Reserved  
J9A2  
J8C1  
J7C1  
S9C1  
U7D1  
J8D1  
U7D3  
U7D10  
J9B1  
J8B1  
J8E1  
J7E2  
U7E4  
J8E2  
J9E2  
J9E1  
J9G2  
J8F1  
2
3
4
5
DB800 Clock Buffer  
Reserved  
6
7
CK-SSCD  
8
Port 80 Controller  
PCI Slot 4  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
PCI Slot 3  
Reserved  
Reserved  
SMSC SIO  
Reserved  
Reserved  
Keyboard Scan Matrix  
LPC Sideband Header  
LPC Slot  
Reserved  
J9G1  
U7G1  
U8G1  
U9H1  
SW9J2  
SW9J1  
J8J2  
®
Intel ICH7-M Digital Home  
Firmware Hub (FWH)  
KBC  
LID Switch  
Virtual Battery Switch  
SATA Direct Connect  
Front Panel Header  
SATA Cable Connect  
IDE (Parallel ATA)  
SATA Power Connector  
Reserved  
J8J1  
J7H1  
J7J1  
J6H3  
J6J1  
Front Panel USB  
LVDS Connector  
CK410M  
J6H2  
J5F1  
U6H1  
J4J1  
ATX Power Supply  
Battery  
BT5H1  
J4J2  
Parallel ATA Power  
4-in-1 VREG Controller  
Reserved  
U3H1  
J3J3  
Reserved  
J1J1  
®
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Hardware Reference—Intel 945GME Express Chipset  
®
Table 7.  
Intel 945GME Express Chipset Component Location Legend (Sheet 2 of 2)  
Reference  
Designator  
No.  
Default Setting  
40  
41  
Reserved  
J1H1  
J1G3  
AC Brick Power Connector  
CR2G1,  
CR3G1-3  
42  
System Power State LEDs  
43  
44  
45  
46  
47  
Reserved  
J3F2  
J3F1  
U2E1  
J1E1  
J3C1  
LAI Fan Header  
Intel Processor  
XDP Connector  
CPU Fan Header  
CR1B1-6,  
CR1C1  
48  
VID LEDs  
49  
50  
51  
52  
53  
54  
55  
56  
Reserved  
945GME GMCH  
Port 82-83 Display  
PCI Express* Graphics Slot  
Port 80-81 Display  
Reserved  
J2B1  
U5E1  
CR6A3,4  
J6C1  
CR6A1,2  
J7A1  
82573E Gb LAN  
Reserved  
U8A2  
J9A1  
®
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Intel 945GME Express Chipset—Hardware Reference  
4.2  
Back Panel Connectors  
®
This section describes the Intel 945GME Express Chipset panel connectors on the  
®
Intel 945GME Express Chipset platform.  
Note:  
Many of the connectors provide operating voltage (for example, +5 V DC and +12 V  
DC) to devices inside the computer chassis, such as fans and internal peripherals. Most  
of these connectors are not over-current protected. Do not use these connectors for  
powering devices external to the computer chassis. A fault in the load presented by the  
external devices could cause damage to the computer, the interconnecting cable, and  
the external devices themselves.  
®
Figure 3 shows the back panel connectors to the Intel 945GME Express Chipset  
platform.  
Figure 3.  
Back Panel Connector Locations  
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Hardware Reference—Intel 945GME Express Chipset  
4.3  
Configuration Settings  
Note:  
Do not move jumpers with the power on. Always turn off the power and unplug the  
power cord from the computer before changing jumper settings. Failure to do so may  
cause damage to the board.  
Figure 4 shows the location of the configuration jumpers and switches.  
Table 8 summarizes the jumpers and switches and gives their default and optional  
settings.  
The unsupported jumpers must remain in their default position or the operation of the  
®
platform is unpredictable. The Intel 945GME Express Chipset board is shipped with  
the jumpers and switches shunted in the default locations.  
Figure 4.  
Configuration Jumper and Switch Locations  
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Intel 945GME Express Chipset—Hardware Reference  
Table 8.  
Supported Configuration Jumper/Switch Settings (Sheet 1 of 2)  
Ref Des  
Function  
Default Setting  
Optional Setting  
Enginnering Validation  
(EV) Support  
J1F2  
J1F4  
J1G1  
J1G2  
Out - Normal Operation  
Not supported  
2-3 Force FSB Frequency - See schematic for valid  
combinations  
BSEL2  
BSEL1  
BSEL0  
1-2 CPU Driven FSB Frequency  
1-2 CPU Driven FSB Frequency  
1-2 CPU Driven FSB Frequency  
2-3 Force FSB Frequency - See schematic for valid  
combinations  
2-3 Force FSB Frequency - See schematic for valid  
combinations  
J2B2  
J2G1  
J2J1  
IMVP-6 Test  
CPU Clock Test  
EV Support  
Out - Normal Operation  
Out - Normal Operation  
Out - Normal Operation  
Not supported  
Not supported  
Not supported  
CRB/System Validation  
(SV) Detect  
J2J10  
2-3 - Normal Operation  
Not supported  
J2J11  
J2J12  
J2J2  
J2J3  
J2J4  
J2J5  
J2J6  
J2J7  
J2J8  
J2J9  
EV Support  
EV Support  
EV Support  
EV Support  
EV Support  
EV Support  
EV Support  
EV Support  
EV Support  
EV Support  
Out - Normal Operation  
Out - Normal Operation  
Out - Normal Operation  
Out - Normal Operation  
Out - Normal Operation  
Out - Normal Operation  
Out - Normal Operation  
Out - Normal Operation  
Out - Normal Operation  
Out - Normal Operation  
Not supported  
Not supported  
Not supported  
Not supported  
Not supported  
Not supported  
Not supported  
Not supported  
Not supported  
Not supported  
1-2 Connect CPU THERMDA to  
Sensor  
3-4 Connect CPU THERMDC to  
Sensor  
Thermal Diode  
Connection  
Out-DisconnectCPUfromThermalSensor  
Out - Disconnect CPU from Thermal Sensor  
J3B1  
J3H1  
J3J1  
J3J2  
J5H2  
J6C2  
J6D1  
J6E1  
J6G1  
J6H1  
J7A2  
J7A3  
J7A4  
J7B1  
J7E1  
J7E2  
J7E3  
Shutdown  
EV Support  
Out - Normal Operation  
Out - Normal Operation  
Out - Normal Operation  
In - Normal Operation  
Out - Normal Operation  
Out - Normal Operation  
2-3 and 5-6 - Normal Operation  
Out - Normal Operation  
Out - Normal Operation  
Out - Normal Operation  
1-2 Normal Operation  
1-2 Normal Operation  
Out - Normal Operation  
Out - Normal Operation  
Out - Normal Operation  
1-2 Normal Operation  
In - Force the board to shut down  
Not supported  
EV Support  
Not supported  
SATA HotSwap  
Out - Disable SATA Hotswap  
Not supported  
EVMC Schmoo Header  
EVMC Schmoo Header  
LVDS Panel Power Jumper  
EVMC Schmoo Header  
CMOS Clear  
Not supported  
Not supported  
Not supported  
In - Clear the CMOS  
Not supported  
82573E PHY Test  
KBC Program  
2-3 Connect RxD to KBC for programming  
2-3 Connect TxD to KBC for programming  
Not supported  
KBC Program  
82573E Clock View  
Port80 Select  
Not supported  
Enable SPI Boot BIOS  
SuperIO Reset  
Not supported  
2-3 to hold the SIO in reset  
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Hardware Reference—Intel 945GME Express Chipset  
Table 8.  
Supported Configuration Jumper/Switch Settings (Sheet 2 of 2)  
Ref Des  
Function  
Default Setting  
Optional Setting  
J7J3  
PATA Hotswap  
In - Normal Operation  
Out - Disable PATA Hotswap  
LAN Non-volatile  
Memory Protect  
J8A1  
Out - Normal Operation  
Not supported  
J8G1  
J8G2  
J8H1  
J9G3  
KBC Reset  
SV Set Up  
1-2 Normal Operation  
Out - Normal Operation  
Out - Normal Operation  
In - Normal Operation  
2-3 to hold the KBC in reset  
Not supported  
BIOS Recovery  
Boot Block Program  
In - Recover the BIOS  
Not supported  
Non-Maskable Interrupt  
Jumper (1 Hz Clock)  
J9H1  
Out - Normal Operation  
In - Enable KBC programming  
J9J1  
J9J2  
KBC Disable  
Mode Type (MD) 0  
SATA Device Status  
MD2  
Out - Normal Operation  
In - Normal Operation  
In - Normal Operation  
Out - Normal Operation  
Out - Normal Operation  
In - Normal Operation  
Out - Normal Operation  
1-2 Normal Operation  
1-2 Normal Operation  
In - KBC Disabled  
Not supported  
J9J3  
Not supported  
J9J4  
Not supported  
J9J5  
LID Jumper  
In - LID Jumper closed  
Not supported  
J9J6  
MD1  
J9J7  
Virtual Battery Jumper  
Virtual Battery Switch  
Lid Switch  
Not supported  
SW9J1  
SW9J2  
Not supported  
2-3 LID Switch closed  
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Intel 945GME Express Chipset—Hardware Reference  
4.4  
Power On and Reset Buttons  
®
The Intel 945GME Express Chipset board has two push buttons, POWER and RESET.  
The POWER button releases power to the entire board, causing the board to boot. The  
RESET button will force all systems to warm reset. The two buttons are located near  
the CPU close to the edge of the board. The POWER button is located at SW1C2 and the  
RESET button is located at SW1C1.  
Note:  
If the board is powered from an external ATX power supply (not a power brick), the  
Power button must be pressed twice to turn on the system.  
®
Figure 5.  
Intel 945GME Express Chipset Development Kit Power On and Reset Buttons  
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Hardware Reference—Intel 945GME Express Chipset  
4.5  
LEDs  
®
The following LEDs provide status for various functions on the Intel 945GME Express  
Chipset board.  
®
Table 9.  
Intel 945GME Express Chipset LED Function Legend  
Function  
LED  
CR9G1  
Keyboard Number Lock  
Keyboard Scroll Lock  
Keyboard Caps Lock  
System State S0  
System State S3  
System State S4  
System State S5  
ATA Activity  
VID 0  
CR9G2  
CR9G3  
CR3G1  
CR3G2  
CR3G3  
CR2G1  
CR7J1  
CR1B1  
CR1B2  
CR1B3  
CR1B4  
CR1B5  
CR1B6  
CR1C1  
VID 1  
VID 2  
VID 3  
VID 4  
VID 5  
VID 6  
4.6  
Other Headers, Slots, and Sockets  
H8 Programming Headers  
4.6.1  
The microcontroller for system management/keyboard/mouse control can be upgraded  
in two ways. The user can either use a special MS-DOS* utility or use an external  
computer connected to the system via the serial port on the board.  
Caution:  
Make sure the motherboard is not powered on and the power supply is disconnected  
before moving any of the jumpers.  
To program the microcontroller via the utility, the user must ensure that jumper J9H1 is  
populated. Once the programming is complete, jumper J9H1 should be unpopulated.  
If the user chooses to use an external computer connected to the system via the serial  
port, there are five jumpers that have to be set correctly first. Please refer to Table 10  
for a summary of these jumpers and see Figure 4 for the location of each jumper.  
Here is the sequence of events necessary to program the H8.  
1. With the board powered off, move the five jumpers listed in Table 10 to the  
programming stuffing option.  
2. Power the S5 voltage rails by attaching an AC brick or an ATX power supply to the  
system.  
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Intel 945GME Express Chipset—Hardware Reference  
3. Program the H8 via the serial port.  
4. Disconnect the power supply from the system.  
5. With the board powered off, move the five jumpers listed in Table 10 back to the  
default stuffing option.  
Table 10.  
H8 Programming Jumpers  
Reference  
Designator  
Programming Stuffing  
Option  
Jumper  
Default Stuffing Option  
Out - normal operation -  
clock enabled  
IN - clock disabled - enable H8  
programming  
1Hz Clock  
J9H1  
IN - normal operation and  
enable external H8  
programming  
H8 Programming J9J2 and J9J6  
Leave in for programming  
2-3 connect TxD to H8 for  
programming  
Tx Select  
Rx Select  
J7A4  
J7A3  
1-2 Normal Operation  
2-3 connect RxD to H8 for  
programming  
1-2 normal operation (SIO)  
4.6.2  
Expansion Slots and Sockets  
Following is a list of the slots and sockets available for attaching additional devices.  
Refer to Figure 2 for locations.  
Table 11.  
Expansion Slots and Sockets  
Reference  
Designator  
Slot/Socket Description  
Detail  
U2E1  
478 Pin Grid Array (Micro-FCPGA) Processor Socket  
DDR2 - Channel A - SODIMM slot  
DDR2 - Channel B - SODIMM slot  
LVDS Graphics Interface  
J5N1  
J5P1  
J5F1  
J6C1  
J6C1  
J7C1  
J8C1  
J8B1  
J9B1  
J7J1  
PCI Express* (x16)  
Table 12  
Table 13  
Table 14  
Table 14  
Media Expansion Card Slot  
PCI Express* (x1) Slot 1  
PCI Express* (x1) Slot 0  
PCI 2.3 Slot 3  
PCI 2.3 Slot 4  
IDE Interface Connector  
Table 15  
Table 18  
Table 16  
Table 17  
J8J2  
Mobile SATA Hard Drive Interface Connector  
Desk Top SATA Hard Drive Interface Connector  
SATA Desk Top Power Connector  
Intel Firmware Hub Socket  
Battery  
J7H1  
J6H3  
U8G1  
BT5H1  
4.6.2.1  
478 Pin Grid Array (Micro-FCPGA) Socket  
The pin locking mechanism on the CPU socket is released by rotating the screw on the  
socket 180 degrees counter-clockwise. CPU pins are keyed so as to only allow insertion  
in one orientation. DO NOT FORCE CPU into socket. Once the CPU is properly seated  
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Hardware Reference—Intel 945GME Express Chipset  
into the socket, turn the screw 180 degrees clock-wise to secure the CPU in the socket.  
Note that the slot on the screw aligns with the lock and unlock legend on the case of  
the CPU socket.  
Caution:  
Please refer to the CPU installation instruction in Appendix A prior to inserting the CPU  
as the CPU and socket can be easily damaged.  
4.6.2.2  
PCI Express* (x16)  
The platform has one x16 lane PCI Express* Graphics slot and supports either x1 or  
®
x16 modes. The slot is wired “lane reversed” which connects the Intel 945GME  
®
Express Chipset lanes 0 through 15 to lanes 15 through 0 on the slot. The Intel  
945GME Express Chipset will internally un-reverse this wiring since its CFG9 power-on  
strap is tied low.  
Table 12.  
PCI Express* (x16) Pinout (J6C1) (Sheet 1 of 3)  
Pin  
Description  
PRSNT1#  
Pin  
Description  
+12 V  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
A9  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
B9  
+12 V  
+12 V  
+12 V  
+12 V  
GND  
GND  
(JTAG) TCK  
(JTAG) TDI  
(JTAG) TDO  
(JTAG) TMS  
+3.3 V  
SMCLK  
SMDAT  
GND  
+3.3 V  
(JTAG) TRST#  
+3.3 VAUX  
WAKE#  
RSVD  
A10  
A11  
A12  
A13  
A14  
A15  
A16  
A17  
A18  
A19  
A20  
A21  
A22  
A23  
A24  
A25  
A26  
A27  
A28  
A29  
+3.3 V  
B10  
B11  
B12  
B13  
B14  
B15  
B16  
B17  
B18  
B19  
B20  
B21  
B22  
B23  
B24  
B25  
B26  
B27  
B28  
B29  
PERST#  
GND  
REFCLK+  
REFCLK-  
GND  
GND  
LANE 0 (T+)  
LANE 0 (T-)  
GND  
LANE 0 (R+)  
LANE 0 (R-)  
GND  
PRSNT2*  
GND  
RSVD  
LANE 1 (T+)  
LANE 1 (T-)  
GND  
GND  
LANE 1 (R+)  
LANE 1 (R-)  
GND  
GND  
LANE 2 (T+)  
LANE 2 (T-)  
GND  
GND  
LANE 2 (R+)  
LANE 2 (R-)  
GND  
GND  
LANE 3 (T+)  
LANE 3 (T-)  
GND  
GND  
LANE 3 (R+)  
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Table 12.  
PCI Express* (x16) Pinout (J6C1) (Sheet 2 of 3)  
Pin  
A30  
Description  
LANE 3 (R-)  
Pin  
B30  
Description  
RSVD  
A31  
A32  
A33  
A34  
A35  
A36  
A37  
A38  
A39  
A40  
A41  
A42  
A43  
A44  
A45  
A46  
A47  
A48  
A49  
A50  
A51  
A52  
A53  
A54  
A55  
A56  
A57  
A58  
A59  
A60  
A61  
A62  
A63  
A64  
A65  
A66  
A67  
A68  
A69  
GND  
B31  
B32  
B33  
B34  
B35  
B36  
B37  
B38  
B39  
B40  
B41  
B42  
B43  
B44  
B45  
B46  
B47  
B48  
B49  
B50  
B51  
B52  
B53  
B54  
B55  
B56  
B57  
B58  
B59  
B60  
B61  
B62  
B63  
B64  
B65  
B66  
B67  
B68  
B69  
PRSNT2#  
GND  
RSVD  
RSVD  
LANE 4 (T+)  
LANE 4 (T-)  
GND  
GND  
LANE 4 (R+)  
LANE 4 (R-)  
GND  
GND  
LANE 5 (T+)  
LANE 5 (T-)  
GND  
GND  
LANE 5 (R+)  
LANE 5 (R-)  
GND  
GND  
LANE 6 (T+)  
LANE 6 (T-)  
GND  
GND  
LANE 6 (R+)  
LANE 6 (R-)  
GND  
GND  
LANE 7 (T+)  
LANE 7 (T-)  
GND  
GND  
LANE 7 (R+)  
LANE 7 (R-)  
GND  
PRSNT#2  
GND  
RSVD  
LANE 8 (T+)  
LANE 8 (T-)  
GND  
GND  
LANE 8 (R+)  
LANE 8 (R-)  
GND  
GND  
LANE 9 (T+)  
LANE 9 (T-)  
GND  
GND  
LANE 9 (R+)  
LANE 9 (R-)  
GND  
GND  
LANE 10 (T+)  
LANE 10 (T-)  
GND  
GND  
LANE 10 (R+)  
LANE 10 (R-)  
GND  
GND  
LANE 11 (T+)  
LANE 11 (T-)  
GND  
GND  
LANE 11 (R+)  
LANE 11 (R-)  
GND  
GND  
LANE 12 (T+)  
LANE 12 (T-)  
GND  
GND  
LANE 12 (R+)  
LANE 12 (R-)  
GND  
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Table 12.  
PCI Express* (x16) Pinout (J6C1) (Sheet 3 of 3)  
Pin  
A70  
Description  
GND  
Pin  
B70  
Description  
LANE 13 (T+)  
LANE 13 (T-)  
GND  
A71  
A72  
A73  
A74  
A75  
A76  
A77  
A78  
A79  
A80  
A81  
A82  
GND  
B71  
B72  
B73  
B74  
B75  
B76  
B77  
B78  
B79  
B80  
B81  
B82  
LANE 13 (R+)  
LANE 13 (R-)  
GND  
GND  
LANE 14 (T+)  
LANE 14 (T-)  
GND  
GND  
LANE 14 (R+)  
LANE 14 (R-)  
GND  
GND  
LANE 15 (T+)  
LANE 15 (T-)  
GND  
GND  
LANE 15 (R+)  
LANE 15 (R-)  
GND  
PRST2#  
RSVD  
4.6.2.3  
Media Expansion Card (MEC) Slot  
When not being used for PCI Express*, the x16 slots can be used for Serial Digital  
Video Out (SDVO). SDVO cards provide for a third party vendor secondary graphics  
add-on such as a digital panel interface.  
The SDVO interface will also support a Media Expansion Card (MEC), which provide TV  
Capture over the PCI Express* x1 port in addition to the standard SDVO card video out  
capabilities.  
Table 13.  
MEC Slot (J6C1) (Sheet 1 of 3)  
Pin  
Number  
A
B
1
2
3
4
5
6
7
8
9
N/C  
12 V  
12 V  
12 V  
GND  
N/C  
12 V  
Reserved  
GND  
N/C  
N/C  
N/C  
N/C  
GND  
N/C  
3.3 V  
N/C  
3.3 V  
3.3 V  
RESET  
10  
11  
+3.3VA  
WAKE#  
Key  
12  
13  
14  
15  
16  
GND  
Reserved  
GND  
REFCLK+  
REFCLK-  
GND  
Lane 0 (T+)  
Lane 0 (T-)  
GND  
Lane 0 (R+)  
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Table 13.  
MEC Slot (J6C1) (Sheet 2 of 3)  
Pin  
Number  
A
B
17  
18  
Lane 0 (R-)  
GND  
SDVO_CtrlClk  
GND  
End of x1 Connector  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
Reserved  
GND  
N/C  
N/C  
N/C  
GND  
N/C  
GND  
GND  
GND  
N/C  
N/C  
N/C  
GND  
N/C  
GND  
GND  
GND  
N/C  
N/C  
N/C  
GND  
N/C  
Reserved  
SDVOB_CtrlData  
GND  
GND  
Reserved  
End of x4 Connector  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
Reserved  
GND  
N/C  
N/C  
N/C  
GND  
GND  
N/C  
N/C  
GND  
GND  
N/C  
N/C  
GND  
GND  
N/C  
N/C  
GND  
GND  
N/C  
N/C  
GND  
GND  
N/C  
N/C  
GND  
GND  
N/C  
N/C  
GND  
MEC_Enable  
GND  
N/C  
GND  
End of x8 Connector  
50  
51  
52  
53  
Reserved  
GND  
SDVOC_CLK+  
SDVOC_CLK-  
GND  
N/C  
N/C  
GND  
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Table 13.  
MEC Slot (J6C1) (Sheet 3 of 3)  
Pin  
Number  
A
B
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
GND  
SDVOC_Blue+  
SDVOC_Blue-  
GND  
GND  
N/C  
N/C  
GND  
GND  
SDVOC_Green+  
SDVOC_Green-  
GND  
GND  
SDVOC_Int+  
SDVOC_Int-  
GND  
GND  
SDVOC_Red+  
SDVOC_Red-  
GND  
GND  
N/C  
N/C  
GND  
GND  
SDVOB_Clk+  
SDVOB_Clk-  
GND  
GND  
N/C  
N/C  
GND  
GND  
SDVOB_Blue+  
SDVOB_Blue-  
GND  
GND  
SDVO_Stall+  
SDVO_Stall-  
GND  
GND  
SDVOB_Green+  
SDVOB_Green-  
GND  
GND  
SDVOB_Int+  
SDVOB_Int-  
GND  
GND  
SDVOB_Red+  
SDVOB_Red-  
GND  
GND  
SDVO_TVClkIn+  
SDVO_TVClkIn-  
GND  
N/C  
Reserved  
4.6.2.4  
PCI Express* (x1)  
The two PCI Express* x1 connectors allow the use of any industry standard PCI  
Express* device. The pin configuration of the connectors is given below.  
Table 14.  
PCI Express* (x1) Pinout (J7C1, J8C1) (Sheet 1 of 2)  
Pin  
Description  
PRSNT1#  
Pin  
Description  
+12 V  
A1  
A2  
A3  
A4  
B1  
B2  
B3  
B4  
+12 V  
+12 V  
GND  
+12 V  
RSVD  
GND  
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TM  
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2 Duo processor with the Mobile Intel 945GME Express Chipset  
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®
Intel 945GME Express Chipset—Hardware Reference  
Table 14.  
PCI Express* (x1) Pinout (J7C1, J8C1) (Sheet 2 of 2)  
A5  
(JTAG) TCK  
(JTAG) TDI  
(JTAG) TDO  
(JTAG) TMS  
+3.3 V  
B5  
SMCLK  
A6  
B6  
SMDAT  
A7  
B7  
GND  
A8  
B8  
+3.3 V  
A9  
B9  
(JTAG) TRST#  
+3.3 VAUX  
WAKE#  
RSVD  
A10  
A11  
A12  
A13  
A14  
A15  
A16  
A17  
A18  
+3.3 V  
B10  
B11  
B12  
B13  
B14  
B15  
B16  
B17  
B18  
PERST#  
GND  
REFCLK+  
REFCLK-  
GND  
GND  
LANE 0 (T+)  
LANE 0 (T-)  
GND  
LANE 0 (R+)  
LANE 0 (R-)  
GND  
PRSNT2*  
GND  
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Hardware Reference—Intel 945GME Express Chipset  
4.6.2.5  
IDE Connector  
The IDE interface can support up to two devices, a master and a slave. Ensure that the  
jumpers on the drives are properly selected for the given configuration. Mobile drives  
with an IDE interface will require an adapter to connect to this port. This adapter is  
included in the Development Kit.  
Table 15.  
IDE Connector (J7J1)  
Pin  
Signal  
Reset IDE  
Pin  
Signal  
Ground  
1
2
3
Host Data 7  
Host Data 6  
Host Data 5  
Host Data 4  
Host Data 3  
Host Data 2  
Host Data 1  
Host Data 0  
Ground  
4
Host Data 8  
Host Data 9  
Host Data 10  
Host Data 11  
Host Data 12  
Host Data 13  
Host Data 14  
Host Data 15  
Key  
5
6
7
8
9
10  
12  
14  
16  
18  
20  
22  
24  
26  
28  
30  
32  
34  
36  
38  
40  
11  
13  
15  
17  
19  
21  
23  
25  
27  
29  
31  
33  
35  
37  
39  
DRQ3  
Ground  
I/O Write  
Ground  
I/O Read  
Ground  
I/O Ch Ready  
DACK 3  
CSEL  
Ground  
IRQ 14  
NC  
Address 1  
Address 0  
Chip Select 0  
Activity  
DATA Detect  
Address 2  
Chip Select 1  
Ground  
4.6.2.6  
SATA Pinout  
Table 16.  
SATA Port 0 Data Connector Pinout (J7H1)  
Pin  
Signal  
1
2
3
4
5
6
7
GND  
TXP  
TXN  
GND  
RXN  
RXP  
GND  
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TM  
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Intel Core  
2 Duo processor with the Mobile Intel 945GME Express Chipset  
May 2007  
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®
Intel 945GME Express Chipset—Hardware Reference  
Table 17.  
SATA Port 0 Power Connector Pinout (J6H3)  
Pin  
Signal  
1, 2  
3, 4  
5
+3.3 V  
+5 V  
+12 V  
GND  
6, 7, 8, 9, 10  
Table 18.  
SATA Port 2 Mobile Drive Connector Pinout (J8J2)  
Pin  
Signal  
2
TX  
3
TX#  
RX#  
RX  
5
6
8, 9, 10  
+3.3 V  
+5 V  
+12 V  
GND  
GND  
14, 15, 16  
20, 21, 22  
1, 4, 7, 11  
12, 13, 17, 19  
4.6.2.7  
Fan Connectors  
Table 19.  
Fan Connectors (J3F1 and J3C1)  
Pin  
Signal  
1
2
+5V  
GND  
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Heat Sink Installation Instructions—Intel 945GME Express Chipset  
Appendix A Heat Sink Installation Instructions  
®
TM  
It is necessary for the Intel Core 2 Duo processor to have a thermal solution  
attached to it in order to keep it within its operating temperature.  
A heat sink is included in the kit. To install the heat sink:  
1. Remove the heatsink from its package and separate the fan heatsink portion from  
the heatsink backplate.  
Figure 6.  
Heatsink and Backplate  
2. Examine the base of the heatsink, where contact with the processor die is made.  
This surface should be clean of all materials and greases. Wipe the bottom surface  
clean with isopropyl alcohol.  
3. Place the backplate on the underside of the board so that the pins protrude through  
the holes in the system board around the processor.  
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TM  
®
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2 Duo processor with the Mobile Intel 945GME Express Chipset  
May 2007  
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Intel 945GME Express Chipset—Heat Sink Installation Instructions  
Figure 7.  
Backplate Pins  
4. Clean the die of the processor with isopropyl alcohol before the heatsink is attached  
to the processor. This ensures that the surface of the die is clean.  
5. Remove the tube of thermal grease from the package and use it to coat the bottom  
of the heatsink thermal plate with the thermal grease.  
®
TM  
®
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2 Duo processor with the Mobile Intel 945GME Express Chipset  
Manual  
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®
Heat Sink Installation Instructions—Intel 945GME Express Chipset  
Figure 8.  
Applying the Thermal Grease  
6. Pick up the heatsink and squeeze the activation arm until it comes in contact with  
the base plate that is attached to the heatsink base. This will cause the springs on  
the heatsink attachment mechanism to compress.  
Figure 9.  
Squeezing Activation Arm  
®
TM  
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2 Duo processor with the Mobile Intel 945GME Express Chipset  
May 2007  
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Intel 945GME Express Chipset—Heat Sink Installation Instructions  
7. While keeping the activation arm compressed, place the heatsink over the pins of  
the heatsink backplate. Lower the heatsink until the lugs have inserted into the  
base of the heatsink. Slide the heatsink over the lugs on the backplate pins so that  
the base is directly over the processor die and the pins on the backplate have  
traveled the entire length of the channel in the heatsink base. Slowly let go of the  
activation arm until the base of the heatsink makes contact with the processor die.  
The heatsink base should be flat on top of the processor die.  
Figure 10.  
Installing the Heatsink  
8. Plug the fan connector for the heatsink onto the CPU fan header (J3C1) on the  
motherboard.  
®
TM  
®
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2 Duo processor with the Mobile Intel 945GME Express Chipset  
Manual  
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®
Heat Sink Installation Instructions—Intel 945GME Express Chipset  
Figure 11.  
Plugging in the Fan  
Figure 12.  
Completed Assembly  
®
TM  
®
Intel Core  
2 Duo processor with the Mobile Intel 945GME Express Chipset  
May 2007  
Order Number: 317443-001US  
Manual  
57  
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